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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 46510a73e977273ec67747eb34cbdb43f815e451 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: df923c6a707f8fee6313f4d06764dce695a8987e [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]21#include "llvm/Target/TargetSubtarget.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]22#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]23#include "llvm/DerivedTypes.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]29#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]30#include "llvm/Support/MathExtras.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]31using namespace llvm;
32
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]33namespace llvm {
34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
40
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
44 else
45 return TLSModel::GeneralDynamic;
46 } else {
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
49 else
50 return TLSModel::InitialExec;
51 }
52}
53}
54
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]55/// InitLibcallNames - Set default libcall names.
56///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]57static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]58 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]61 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]62 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]65 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]66 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]69 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]70 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]74 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]75 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]76 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]79 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]80 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]81 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]84 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]85 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]86 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]89 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]90 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]91 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]94 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]99 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]103 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]107 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]115 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]116 Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]265}
266
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]267/// InitLibcallCallingConvs - Set default libcall CallingConvs.
268///
269static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
270 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
271 CCs[i] = CallingConv::C;
272 }
273}
274
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]275/// getFPEXT - Return the FPEXT_*_* value for the given types, or
276/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]277RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]278 if (OpVT == MVT::f32) {
279 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]280 return FPEXT_F32_F64;
281 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]282
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]283 return UNKNOWN_LIBCALL;
284}
285
286/// getFPROUND - Return the FPROUND_*_* value for the given types, or
287/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]288RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]289 if (RetVT == MVT::f32) {
290 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]291 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]292 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]293 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]294 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]295 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]296 } else if (RetVT == MVT::f64) {
297 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]298 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]299 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]300 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]301 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]302
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]303 return UNKNOWN_LIBCALL;
304}
305
306/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
307/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]308RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]309 if (OpVT == MVT::f32) {
310 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]311 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]312 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]313 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]314 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]315 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]316 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]317 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]318 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]319 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]320 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]321 if (RetVT == MVT::i8)
322 return FPTOSINT_F64_I8;
323 if (RetVT == MVT::i16)
324 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]325 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]326 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]327 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]328 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]329 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]330 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]331 } else if (OpVT == MVT::f80) {
332 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]333 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]334 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]335 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]336 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]337 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]338 } else if (OpVT == MVT::ppcf128) {
339 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]340 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]341 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]342 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]343 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]344 return FPTOSINT_PPCF128_I128;
345 }
346 return UNKNOWN_LIBCALL;
347}
348
349/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
350/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]351RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]352 if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]354 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]356 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]358 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]359 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]360 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]361 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]363 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]364 if (RetVT == MVT::i8)
365 return FPTOUINT_F64_I8;
366 if (RetVT == MVT::i16)
367 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]368 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]369 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]371 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]372 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]373 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]374 } else if (OpVT == MVT::f80) {
375 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]378 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]379 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]380 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]381 } else if (OpVT == MVT::ppcf128) {
382 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]383 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]384 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]385 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]386 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]387 return FPTOUINT_PPCF128_I128;
388 }
389 return UNKNOWN_LIBCALL;
390}
391
392/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
393/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]394RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 if (OpVT == MVT::i32) {
396 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]397 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]398 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]399 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]400 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 } else if (OpVT == MVT::i64) {
405 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]406 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]407 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]408 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]409 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]410 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]411 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]412 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 } else if (OpVT == MVT::i128) {
414 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]415 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]417 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]421 return SINTTOFP_I128_PPCF128;
422 }
423 return UNKNOWN_LIBCALL;
424}
425
426/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
427/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]428RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]429 if (OpVT == MVT::i32) {
430 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]431 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]432 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]433 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]434 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]435 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]436 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]437 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]438 } else if (OpVT == MVT::i64) {
439 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]440 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]441 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]442 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]443 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]446 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]447 } else if (OpVT == MVT::i128) {
448 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]449 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]451 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]452 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]453 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]454 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]455 return UINTTOFP_I128_PPCF128;
456 }
457 return UNKNOWN_LIBCALL;
458}
459
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]460/// InitCmpLibcallCCs - Set default comparison libcall CC.
461///
462static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
463 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
464 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
465 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
466 CCs[RTLIB::UNE_F32] = ISD::SETNE;
467 CCs[RTLIB::UNE_F64] = ISD::SETNE;
468 CCs[RTLIB::OGE_F32] = ISD::SETGE;
469 CCs[RTLIB::OGE_F64] = ISD::SETGE;
470 CCs[RTLIB::OLT_F32] = ISD::SETLT;
471 CCs[RTLIB::OLT_F64] = ISD::SETLT;
472 CCs[RTLIB::OLE_F32] = ISD::SETLE;
473 CCs[RTLIB::OLE_F64] = ISD::SETLE;
474 CCs[RTLIB::OGT_F32] = ISD::SETGT;
475 CCs[RTLIB::OGT_F64] = ISD::SETGT;
476 CCs[RTLIB::UO_F32] = ISD::SETNE;
477 CCs[RTLIB::UO_F64] = ISD::SETNE;
478 CCs[RTLIB::O_F32] = ISD::SETEQ;
479 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]480}
481
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]482/// NOTE: The constructor takes ownership of TLOF.
483TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
484 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]485 // All operations default to being supported.
486 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]487 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]488 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]489 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]490 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]491
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]492 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]494 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]495 for (unsigned IM = (unsigned)ISD::PRE_INC;
496 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]497 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
498 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]499 }
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]500
501 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]502 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
503 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]504 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]505
506 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]507 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]508
509 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]510 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]511 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]512 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
513 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
514 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]515
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]516 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]517 setOperationAction(ISD::FLOG , MVT::f64, Expand);
518 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
519 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
520 setOperationAction(ISD::FEXP , MVT::f64, Expand);
521 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
522 setOperationAction(ISD::FLOG , MVT::f32, Expand);
523 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
524 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
525 setOperationAction(ISD::FEXP , MVT::f32, Expand);
526 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]527
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]528 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]529 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]530
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]531 IsLittleEndian = TD->isLittleEndian();
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]532 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]533 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]534 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]535 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]536 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]537 UseUnderscoreSetJmp = false;
538 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]539 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]540 IntDivIsCheap = false;
541 Pow2DivIsCheap = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]542 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]543 ExceptionPointerRegister = 0;
544 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]545 BooleanContents = UndefinedBooleanContent;
Evan Cheng0577a222006-01-25 18:52:42 +0000[diff] [blame]546 SchedPreferenceInfo = SchedulingForLatency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]547 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]548 JumpBufAlignment = 0;
Evan Chengd60483e2007-05-16 23:45:53 +0000[diff] [blame]549 IfCvtBlockSizeLimit = 2;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]550 IfCvtDupBlockSizeLimit = 0;
551 PrefLoopAlignment = 0;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]552
553 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]554 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]555 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]556}
557
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]558TargetLowering::~TargetLowering() {
559 delete &TLOF;
560}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]561
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]562/// canOpTrap - Returns true if the operation can trap for the value type.
563/// VT must be a legal type.
564bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
565 assert(isTypeLegal(VT));
566 switch (Op) {
567 default:
568 return false;
569 case ISD::FDIV:
570 case ISD::FREM:
571 case ISD::SDIV:
572 case ISD::UDIV:
573 case ISD::SREM:
574 case ISD::UREM:
575 return true;
576 }
577}
578
579
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]580static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
581 unsigned &NumIntermediates,
582 EVT &RegisterVT,
583 TargetLowering* TLI) {
584 // Figure out the right, legal destination reg to copy into.
585 unsigned NumElts = VT.getVectorNumElements();
586 MVT EltTy = VT.getVectorElementType();
587
588 unsigned NumVectorRegs = 1;
589
590 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
591 // could break down into LHS/RHS like LegalizeDAG does.
592 if (!isPowerOf2_32(NumElts)) {
593 NumVectorRegs = NumElts;
594 NumElts = 1;
595 }
596
597 // Divide the input until we get to a supported size. This will always
598 // end with a scalar if the target doesn't support vectors.
599 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
600 NumElts >>= 1;
601 NumVectorRegs <<= 1;
602 }
603
604 NumIntermediates = NumVectorRegs;
605
606 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
607 if (!TLI->isTypeLegal(NewVT))
608 NewVT = EltTy;
609 IntermediateVT = NewVT;
610
611 EVT DestVT = TLI->getRegisterType(NewVT);
612 RegisterVT = DestVT;
613 if (EVT(DestVT).bitsLT(NewVT)) {
614 // Value is expanded, e.g. i64 -> i16.
615 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
616 } else {
617 // Otherwise, promotion or legal types use the same number of registers as
618 // the vector decimated to the appropriate level.
619 return NumVectorRegs;
620 }
621
622 return 1;
623}
624
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]625/// computeRegisterProperties - Once all of the register classes are added,
626/// this allows us to compute derived properties we expose.
627void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]628 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]629 "Too many value types for ValueTypeActions to hold!");
630
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]631 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]632 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]633 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]634 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]635 }
636 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]637 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]638
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]639 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]640 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]641 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]642 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]643
644 // Every integer value type larger than this largest register takes twice as
645 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]646 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]647 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
648 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]649 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]650 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]651 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
652 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]653 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]654 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]655
656 // Inspect all of the ValueType's smaller than the largest integer
657 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]658 unsigned LegalIntReg = LargestIntReg;
659 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]660 IntReg >= (unsigned)MVT::i1; --IntReg) {
661 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]662 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]663 LegalIntReg = IntReg;
664 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]665 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]666 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]667 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]668 }
669 }
670
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]671 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]672 if (!isTypeLegal(MVT::ppcf128)) {
673 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
674 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
675 TransformToType[MVT::ppcf128] = MVT::f64;
676 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]677 }
678
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]679 // Decide how to handle f64. If the target does not have native f64 support,
680 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]681 if (!isTypeLegal(MVT::f64)) {
682 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
683 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
684 TransformToType[MVT::f64] = MVT::i64;
685 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]686 }
687
688 // Decide how to handle f32. If the target does not have native support for
689 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]690 if (!isTypeLegal(MVT::f32)) {
691 if (isTypeLegal(MVT::f64)) {
692 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
693 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
694 TransformToType[MVT::f32] = MVT::f64;
695 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]696 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]697 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
698 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
699 TransformToType[MVT::f32] = MVT::i32;
700 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]701 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]702 }
Nate Begeman4ef3b812005-11-22 01:29:36 +0000[diff] [blame]703
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]704 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]705 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
706 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]707 MVT VT = (MVT::SimpleValueType)i;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]708 if (!isTypeLegal(VT)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]709 MVT IntermediateVT;
710 EVT RegisterVT;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]711 unsigned NumIntermediates;
712 NumRegistersForVT[i] =
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]713 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
714 RegisterVT, this);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]715 RegisterTypeForVT[i] = RegisterVT;
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]716
717 // Determine if there is a legal wider type.
718 bool IsLegalWiderType = false;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]719 EVT EltVT = VT.getVectorElementType();
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]720 unsigned NElts = VT.getVectorNumElements();
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]721 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
722 EVT SVT = (MVT::SimpleValueType)nVT;
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]723 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
Mon P Wang6fb474b2010-01-24 00:24:43 +0000[diff] [blame]724 SVT.getVectorNumElements() > NElts && NElts != 1) {
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]725 TransformToType[i] = SVT;
726 ValueTypeActions.setTypeAction(VT, Promote);
727 IsLegalWiderType = true;
728 break;
729 }
730 }
731 if (!IsLegalWiderType) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]732 EVT NVT = VT.getPow2VectorType();
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]733 if (NVT == VT) {
734 // Type is already a power of 2. The default action is to split.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]735 TransformToType[i] = MVT::Other;
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]736 ValueTypeActions.setTypeAction(VT, Expand);
737 } else {
738 TransformToType[i] = NVT;
739 ValueTypeActions.setTypeAction(VT, Promote);
740 }
741 }
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]742 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]743 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]744}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]745
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]746const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
747 return NULL;
748}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]749
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]750
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]751MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]752 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]753}
754
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]755MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
756 return MVT::i32; // return the default value
757}
758
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]759/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]760/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
761/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
762/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]763///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]764/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]765/// register. It also returns the VT and quantity of the intermediate values
766/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]767///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]768unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]769 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]770 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]771 EVT &RegisterVT) const {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]772 // Figure out the right, legal destination reg to copy into.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]773 unsigned NumElts = VT.getVectorNumElements();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]774 EVT EltTy = VT.getVectorElementType();
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]775
776 unsigned NumVectorRegs = 1;
777
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]778 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
779 // could break down into LHS/RHS like LegalizeDAG does.
780 if (!isPowerOf2_32(NumElts)) {
781 NumVectorRegs = NumElts;
782 NumElts = 1;
783 }
784
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]785 // Divide the input until we get to a supported size. This will always
786 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]787 while (NumElts > 1 && !isTypeLegal(
788 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]789 NumElts >>= 1;
790 NumVectorRegs <<= 1;
791 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]792
793 NumIntermediates = NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]794
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]795 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]796 if (!isTypeLegal(NewVT))
797 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]798 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]799
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]800 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 RegisterVT = DestVT;
Duncan Sands8e4eb092008-06-08 20:54:56 +0000[diff] [blame]802 if (DestVT.bitsLT(NewVT)) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]803 // Value is expanded, e.g. i64 -> i16.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]804 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]805 } else {
806 // Otherwise, promotion or legal types use the same number of registers as
807 // the vector decimated to the appropriate level.
Chris Lattner79227e22006-03-31 00:46:36 +0000[diff] [blame]808 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]809 }
810
Evan Chenge9b3da12006-05-17 18:10:06 +0000[diff] [blame]811 return 1;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]812}
813
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]814/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]815/// function arguments in the caller parameter area. This is the actual
816/// alignment, not its logarithm.
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]817unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]818 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]819}
820
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]821/// getJumpTableEncoding - Return the entry encoding for a jump table in the
822/// current function. The returned value is a member of the
823/// MachineJumpTableInfo::JTEntryKind enum.
824unsigned TargetLowering::getJumpTableEncoding() const {
825 // In non-pic modes, just use the address of a block.
826 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
827 return MachineJumpTableInfo::EK_BlockAddress;
828
829 // In PIC mode, if the target supports a GPRel32 directive, use it.
830 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
831 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
832
833 // Otherwise, use a label difference.
834 return MachineJumpTableInfo::EK_LabelDifference32;
835}
836
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]837SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
838 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]839 // If our PIC model is GP relative, use the global offset table as the base.
840 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]841 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]842 return Table;
843}
844
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]845/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
846/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
847/// MCExpr.
848const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]849TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
850 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]851 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]852 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]853}
854
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]855bool
856TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
857 // Assume that everything is safe in static mode.
858 if (getTargetMachine().getRelocationModel() == Reloc::Static)
859 return true;
860
861 // In dynamic-no-pic mode, assume that known defined values are safe.
862 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
863 GA &&
864 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]865 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]866 return true;
867
868 // Otherwise assume nothing is safe.
869 return false;
870}
871
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]872//===----------------------------------------------------------------------===//
873// Optimization Methods
874//===----------------------------------------------------------------------===//
875
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]876/// ShrinkDemandedConstant - Check to see if the specified operand of the
877/// specified instruction is a constant integer. If so, check to see if there
878/// are any bits set in the constant that are not demanded. If so, shrink the
879/// constant and return true.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]880bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]881 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]882 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]883
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]884 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]885 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]886 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]887 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]888 case ISD::AND:
889 case ISD::OR: {
890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
891 if (!C) return false;
892
893 if (Op.getOpcode() == ISD::XOR &&
894 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
895 return false;
896
897 // if we can expand it to have all bits set, do it
898 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]899 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]900 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
901 DAG.getConstant(Demanded &
902 C->getAPIntValue(),
903 VT));
904 return CombineTo(Op, New);
905 }
906
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]907 break;
908 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]909 }
910
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]911 return false;
912}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]913
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]914/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
915/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
916/// cast, but it could be generalized for targets with other types of
917/// implicit widening casts.
918bool
919TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
920 unsigned BitWidth,
921 const APInt &Demanded,
922 DebugLoc dl) {
923 assert(Op.getNumOperands() == 2 &&
924 "ShrinkDemandedOp only supports binary operators!");
925 assert(Op.getNode()->getNumValues() == 1 &&
926 "ShrinkDemandedOp only supports nodes with one result!");
927
928 // Don't do this if the node has another user, which may require the
929 // full value.
930 if (!Op.getNode()->hasOneUse())
931 return false;
932
933 // Search for the smallest integer type with free casts to and from
934 // Op's type. For expedience, just check power-of-2 integer types.
935 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
936 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
937 if (!isPowerOf2_32(SmallVTBits))
938 SmallVTBits = NextPowerOf2(SmallVTBits);
939 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]940 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]941 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
942 TLI.isZExtFree(SmallVT, Op.getValueType())) {
943 // We found a type with free casts.
944 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
945 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
946 Op.getNode()->getOperand(0)),
947 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
948 Op.getNode()->getOperand(1)));
949 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
950 return CombineTo(Op, Z);
951 }
952 }
953 return false;
954}
955
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]956/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
957/// DemandedMask bits of the result of Op are ever used downstream. If we can
958/// use this information to simplify Op, create a new simplified DAG node and
959/// return true, returning the original and new nodes in Old and New. Otherwise,
960/// analyze the expression and return a mask of KnownOne and KnownZero bits for
961/// the expression (used to simplify the caller). The KnownZero/One bits may
962/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]963bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]964 const APInt &DemandedMask,
965 APInt &KnownZero,
966 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]967 TargetLoweringOpt &TLO,
968 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]969 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]970 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]971 "Mask size mismatches value type size!");
972 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]973 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]974
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]975 // Don't know anything.
976 KnownZero = KnownOne = APInt(BitWidth, 0);
977
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]978 // Other users may use these bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]979 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]980 if (Depth != 0) {
981 // If not at the root, Just compute the KnownZero/KnownOne bits to
982 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]983 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]984 return false;
985 }
986 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]987 // just set the NewMask to all bits.
988 NewMask = APInt::getAllOnesValue(BitWidth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]989 } else if (DemandedMask == 0) {
990 // Not demanding any bits from Op.
991 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]992 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]993 return false;
994 } else if (Depth == 6) { // Limit search depth.
995 return false;
996 }
997
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]998 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]999 switch (Op.getOpcode()) {
1000 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1001 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1002 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1003 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1004 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1005 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1006 // If the RHS is a constant, check to see if the LHS would be zero without
1007 // using the bits from the RHS. Below, we use knowledge about the RHS to
1008 // simplify the LHS, here we're using information from the LHS to simplify
1009 // the RHS.
1010 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1011 APInt LHSZero, LHSOne;
1012 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1013 LHSZero, LHSOne, Depth+1);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1014 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1015 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1016 return TLO.CombineTo(Op, Op.getOperand(0));
1017 // If any of the set bits in the RHS are known zero on the LHS, shrink
1018 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1019 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1020 return true;
1021 }
1022
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1023 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1024 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1025 return true;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1026 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1027 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1028 KnownZero2, KnownOne2, TLO, Depth+1))
1029 return true;
1030 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1031
1032 // If all of the demanded bits are known one on one side, return the other.
1033 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1034 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1035 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1036 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1037 return TLO.CombineTo(Op, Op.getOperand(1));
1038 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1039 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1040 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1041 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1042 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1043 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1044 // If the operation can be done in a smaller type, do so.
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1045 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1046 return true;
1047
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1048 // Output known-1 bits are only known if set in both the LHS & RHS.
1049 KnownOne &= KnownOne2;
1050 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1051 KnownZero |= KnownZero2;
1052 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1053 case ISD::OR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1054 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1055 KnownOne, TLO, Depth+1))
1056 return true;
1057 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1058 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1059 KnownZero2, KnownOne2, TLO, Depth+1))
1060 return true;
1061 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1062
1063 // If all of the demanded bits are known zero on one side, return the other.
1064 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1065 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1066 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1067 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1068 return TLO.CombineTo(Op, Op.getOperand(1));
1069 // If all of the potentially set bits on one side are known to be set on
1070 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1071 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1072 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1073 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1074 return TLO.CombineTo(Op, Op.getOperand(1));
1075 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1076 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1077 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1078 // If the operation can be done in a smaller type, do so.
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1079 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1080 return true;
1081
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1082 // Output known-0 bits are only known if clear in both the LHS & RHS.
1083 KnownZero &= KnownZero2;
1084 // Output known-1 are known to be set if set in either the LHS | RHS.
1085 KnownOne |= KnownOne2;
1086 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1087 case ISD::XOR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1088 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1089 KnownOne, TLO, Depth+1))
1090 return true;
1091 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1092 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1093 KnownOne2, TLO, Depth+1))
1094 return true;
1095 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1096
1097 // If all of the demanded bits are known zero on one side, return the other.
1098 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1099 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1100 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1101 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1102 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1103 // If the operation can be done in a smaller type, do so.
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1104 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1105 return true;
1106
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1107 // If all of the unknown bits are known to be zero on one side or the other
1108 // (but not both) turn this into an *inclusive* or.
1109 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1110 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1111 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1112 Op.getOperand(0),
1113 Op.getOperand(1)));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1114
1115 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1116 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1117 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1118 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1119
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1120 // If all of the demanded bits on one side are known, and all of the set
1121 // bits on that side are also known to be set on the other side, turn this
1122 // into an AND, as we know the bits will be cleared.
1123 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1124 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1125 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1126 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1127 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1128 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1129 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1130 }
1131 }
1132
1133 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1134 // for XOR, we prefer to force bits to 1 if they will make a -1.
1135 // if we can't force bits, try to shrink constant
1136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1137 APInt Expanded = C->getAPIntValue() | (~NewMask);
1138 // if we can expand it to have all bits set, do it
1139 if (Expanded.isAllOnesValue()) {
1140 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1141 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1142 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1143 TLO.DAG.getConstant(Expanded, VT));
1144 return TLO.CombineTo(Op, New);
1145 }
1146 // if it already has all the bits set, nothing to change
1147 // but don't shrink either!
1148 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1149 return true;
1150 }
1151 }
1152
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1153 KnownZero = KnownZeroOut;
1154 KnownOne = KnownOneOut;
1155 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1156 case ISD::SELECT:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1157 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1158 KnownOne, TLO, Depth+1))
1159 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1160 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1161 KnownOne2, TLO, Depth+1))
1162 return true;
1163 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1164 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1165
1166 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1167 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1168 return true;
1169
1170 // Only known if known in both the LHS and RHS.
1171 KnownOne &= KnownOne2;
1172 KnownZero &= KnownZero2;
1173 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1174 case ISD::SELECT_CC:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1175 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1176 KnownOne, TLO, Depth+1))
1177 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1178 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1179 KnownOne2, TLO, Depth+1))
1180 return true;
1181 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1182 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1183
1184 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1185 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1186 return true;
1187
1188 // Only known if known in both the LHS and RHS.
1189 KnownOne &= KnownOne2;
1190 KnownZero &= KnownZero2;
1191 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1192 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1193 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1194 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1195 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1196
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1197 // If the shift count is an invalid immediate, don't do anything.
1198 if (ShAmt >= BitWidth)
1199 break;
1200
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1201 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1202 // single shift. We can do this if the bottom bits (which are shifted
1203 // out) are never demanded.
1204 if (InOp.getOpcode() == ISD::SRL &&
1205 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1206 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1207 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1208 unsigned Opc = ISD::SHL;
1209 int Diff = ShAmt-C1;
1210 if (Diff < 0) {
1211 Diff = -Diff;
1212 Opc = ISD::SRL;
1213 }
1214
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1215 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1216 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1217 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1218 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1219 InOp.getOperand(0), NewSA));
1220 }
1221 }
1222
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1223 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1224 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1225 return true;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1226 KnownZero <<= SA->getZExtValue();
1227 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1229 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1230 }
1231 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1232 case ISD::SRL:
1233 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1234 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1235 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1236 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1237 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1238
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1239 // If the shift count is an invalid immediate, don't do anything.
1240 if (ShAmt >= BitWidth)
1241 break;
1242
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1243 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1244 // single shift. We can do this if the top bits (which are shifted out)
1245 // are never demanded.
1246 if (InOp.getOpcode() == ISD::SHL &&
1247 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1248 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1249 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1250 unsigned Opc = ISD::SRL;
1251 int Diff = ShAmt-C1;
1252 if (Diff < 0) {
1253 Diff = -Diff;
1254 Opc = ISD::SHL;
1255 }
1256
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1257 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1258 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1259 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1260 InOp.getOperand(0), NewSA));
1261 }
1262 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1263
1264 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1265 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1266 KnownZero, KnownOne, TLO, Depth+1))
1267 return true;
1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1269 KnownZero = KnownZero.lshr(ShAmt);
1270 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1271
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1272 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1273 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1274 }
1275 break;
1276 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1277 // If this is an arithmetic shift right and only the low-bit is set, we can
1278 // always convert this into a logical shr, even if the shift amount is
1279 // variable. The low bit of the shift cannot be an input sign bit unless
1280 // the shift amount is >= the size of the datatype, which is undefined.
1281 if (DemandedMask == 1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1282 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1283 Op.getOperand(0), Op.getOperand(1)));
1284
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1285 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1286 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1287 unsigned ShAmt = SA->getZExtValue();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1288
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1289 // If the shift count is an invalid immediate, don't do anything.
1290 if (ShAmt >= BitWidth)
1291 break;
1292
1293 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1294
1295 // If any of the demanded bits are produced by the sign extension, we also
1296 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1297 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1298 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1299 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1300
1301 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1302 KnownZero, KnownOne, TLO, Depth+1))
1303 return true;
1304 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1305 KnownZero = KnownZero.lshr(ShAmt);
1306 KnownOne = KnownOne.lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1307
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1308 // Handle the sign bit, adjusted to where it is now in the mask.
1309 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1310
1311 // If the input sign bit is known to be zero, or if none of the top bits
1312 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1313 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1314 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1315 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1316 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1317 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1318 KnownOne |= HighBits;
1319 }
1320 }
1321 break;
1322 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1323 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1324
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1325 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1326 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1327 APInt NewBits =
1328 APInt::getHighBitsSet(BitWidth,
1329 BitWidth - EVT.getScalarType().getSizeInBits()) &
1330 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1332 // If none of the extended bits are demanded, eliminate the sextinreg.
1333 if (NewBits == 0)
1334 return TLO.CombineTo(Op, Op.getOperand(0));
1335
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1336 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1337 InSignBit.zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1338 APInt InputDemandedBits =
1339 APInt::getLowBitsSet(BitWidth,
1340 EVT.getScalarType().getSizeInBits()) &
1341 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1342
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1343 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1344 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1345 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1346
1347 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1348 KnownZero, KnownOne, TLO, Depth+1))
1349 return true;
1350 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1351
1352 // If the sign bit of the input is known set or clear, then we know the
1353 // top bits of the result.
1354
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1355 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1356 if (KnownZero.intersects(InSignBit))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1357 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1358 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1359
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1360 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1361 KnownOne |= NewBits;
1362 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1363 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1364 KnownZero &= ~NewBits;
1365 KnownOne &= ~NewBits;
1366 }
1367 break;
1368 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1369 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1370 unsigned OperandBitWidth =
1371 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1372 APInt InMask = NewMask;
1373 InMask.trunc(OperandBitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1374
1375 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1376 APInt NewBits =
1377 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1378 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1379 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1380 Op.getValueType(),
1381 Op.getOperand(0)));
1382
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1383 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1384 KnownZero, KnownOne, TLO, Depth+1))
1385 return true;
1386 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1387 KnownZero.zext(BitWidth);
1388 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1389 KnownZero |= NewBits;
1390 break;
1391 }
1392 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1393 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1394 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1395 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1396 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1397 APInt NewBits = ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1398
1399 // If none of the top bits are demanded, convert this into an any_extend.
1400 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1401 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1402 Op.getValueType(),
1403 Op.getOperand(0)));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1404
1405 // Since some of the sign extended bits are demanded, we know that the sign
1406 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1407 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1408 InDemandedBits |= InSignBit;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1409 InDemandedBits.trunc(InBits);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1410
1411 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1412 KnownOne, TLO, Depth+1))
1413 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1414 KnownZero.zext(BitWidth);
1415 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1416
1417 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1418 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1419 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1420 Op.getValueType(),
1421 Op.getOperand(0)));
1422
1423 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1424 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1425 KnownOne |= NewBits;
1426 KnownZero &= ~NewBits;
1427 } else { // Otherwise, top bits aren't known.
1428 KnownOne &= ~NewBits;
1429 KnownZero &= ~NewBits;
1430 }
1431 break;
1432 }
1433 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1434 unsigned OperandBitWidth =
1435 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1436 APInt InMask = NewMask;
1437 InMask.trunc(OperandBitWidth);
1438 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1439 KnownZero, KnownOne, TLO, Depth+1))
1440 return true;
1441 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1442 KnownZero.zext(BitWidth);
1443 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1444 break;
1445 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1446 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1447 // Simplify the input, using demanded bit information, and compute the known
1448 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1449 unsigned OperandBitWidth =
1450 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1451 APInt TruncMask = NewMask;
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1452 TruncMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1453 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1454 KnownZero, KnownOne, TLO, Depth+1))
1455 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1456 KnownZero.trunc(BitWidth);
1457 KnownOne.trunc(BitWidth);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1458
1459 // If the input is only used by this truncate, see if we can shrink it based
1460 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1461 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1462 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1463 switch (In.getOpcode()) {
1464 default: break;
1465 case ISD::SRL:
1466 // Shrink SRL by a constant if none of the high bits shifted in are
1467 // demanded.
1468 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1469 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1470 OperandBitWidth - BitWidth);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1471 HighBits = HighBits.lshr(ShAmt->getZExtValue());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1472 HighBits.trunc(BitWidth);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1473
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1474 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1475 // None of the shifted in bits are needed. Add a truncate of the
1476 // shift input, then shift it.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1477 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1478 Op.getValueType(),
1479 In.getOperand(0));
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1480 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1481 Op.getValueType(),
1482 NewTrunc,
1483 In.getOperand(1)));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1484 }
1485 }
1486 break;
1487 }
1488 }
1489
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1490 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1491 break;
1492 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1493 case ISD::AssertZext: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1494 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1495 APInt InMask = APInt::getLowBitsSet(BitWidth,
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1496 VT.getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1497 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1498 KnownZero, KnownOne, TLO, Depth+1))
1499 return true;
1500 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1501 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1502 break;
1503 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1504 case ISD::BIT_CONVERT:
1505#if 0
1506 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1507 // is demanded, turn this into a FGETSIGN.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1508 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1509 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1510 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1511 // Only do this xform if FGETSIGN is valid or if before legalize.
1512 if (!TLO.AfterLegalize ||
1513 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1514 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1515 // place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1516 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1517 Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1518 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1519 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1521 Sign, ShAmt));
1522 }
1523 }
1524#endif
1525 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1526 case ISD::ADD:
1527 case ISD::MUL:
1528 case ISD::SUB: {
1529 // Add, Sub, and Mul don't demand any bits in positions beyond that
1530 // of the highest bit demanded of them.
1531 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1532 BitWidth - NewMask.countLeadingZeros());
1533 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1534 KnownOne2, TLO, Depth+1))
1535 return true;
1536 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1537 KnownOne2, TLO, Depth+1))
1538 return true;
1539 // See if the operation should be performed at a smaller bit width.
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1540 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1541 return true;
1542 }
1543 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1544 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1545 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1546 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1547 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1548 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1549
1550 // If we know the value of all of the demanded bits, return this as a
1551 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1552 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1553 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1554
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1555 return false;
1556}
1557
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1558/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1559/// in Mask are known to be either zero or one and return them in the
1560/// KnownZero/KnownOne bitsets.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1561void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1562 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1563 APInt &KnownZero,
1564 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1565 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1566 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1567 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1568 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1569 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1570 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1571 "Should use MaskedValueIsZero if you don't know whether Op"
1572 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1573 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1574}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1575
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1576/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1577/// targets that want to expose additional information about sign bits to the
1578/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1579unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1580 unsigned Depth) const {
1581 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1582 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1583 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1584 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1585 "Should use ComputeNumSignBits if you don't know whether Op"
1586 " is a target node!");
1587 return 1;
1588}
1589
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1590/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1591/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1592/// determine which bit is set.
1593///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1594static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1595 // A left-shift of a constant one will have exactly one bit set, because
1596 // shifting the bit off the end is undefined.
1597 if (Val.getOpcode() == ISD::SHL)
1598 if (ConstantSDNode *C =
1599 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1600 if (C->getAPIntValue() == 1)
1601 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1602
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1603 // Similarly, a right-shift of a constant sign-bit will have exactly
1604 // one bit set.
1605 if (Val.getOpcode() == ISD::SRL)
1606 if (ConstantSDNode *C =
1607 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1608 if (C->getAPIntValue().isSignBit())
1609 return true;
1610
1611 // More could be done here, though the above checks are enough
1612 // to handle some common cases.
1613
1614 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1615 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1616 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1617 APInt Mask = APInt::getAllOnesValue(BitWidth);
1618 APInt KnownZero, KnownOne;
1619 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1620 return (KnownZero.countPopulation() == BitWidth - 1) &&
1621 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1622}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1623
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1624/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1625/// and cc. If it is unable to simplify it, return a null SDValue.
1626SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1627TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1628 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1629 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1630 SelectionDAG &DAG = DCI.DAG;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1631 LLVMContext &Context = *DAG.getContext();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1632
1633 // These setcc operations always fold.
1634 switch (Cond) {
1635 default: break;
1636 case ISD::SETFALSE:
1637 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1638 case ISD::SETTRUE:
1639 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1640 }
1641
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1642 if (isa<ConstantSDNode>(N0.getNode())) {
1643 // Ensure that the constant occurs on the RHS, and fold constant
1644 // comparisons.
1645 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1646 }
1647
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1648 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1649 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1650
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1651 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1652 // equality comparison, then we're just comparing whether X itself is
1653 // zero.
1654 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1655 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1656 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1657 const APInt &ShAmt
1658 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1659 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1660 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1661 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1662 // (srl (ctlz x), 5) == 0 -> X != 0
1663 // (srl (ctlz x), 5) != 1 -> X != 0
1664 Cond = ISD::SETNE;
1665 } else {
1666 // (srl (ctlz x), 5) != 0 -> X == 0
1667 // (srl (ctlz x), 5) == 1 -> X == 0
1668 Cond = ISD::SETEQ;
1669 }
1670 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1671 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1672 Zero, Cond);
1673 }
1674 }
1675
1676 // If the LHS is '(and load, const)', the RHS is 0,
1677 // the test is for equality or unsigned, and all 1 bits of the const are
1678 // in the same partial word, see if we can shorten the load.
1679 if (DCI.isBeforeLegalize() &&
1680 N0.getOpcode() == ISD::AND && C1 == 0 &&
1681 N0.getNode()->hasOneUse() &&
1682 isa<LoadSDNode>(N0.getOperand(0)) &&
1683 N0.getOperand(0).getNode()->hasOneUse() &&
1684 isa<ConstantSDNode>(N0.getOperand(1))) {
1685 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1686 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1687 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1688 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1689 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1690 unsigned maskWidth = origWidth;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1691 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1692 // 8 bits, but have to be careful...
1693 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1694 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1695 const APInt &Mask =
1696 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1697 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1698 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1699 for (unsigned offset=0; offset<origWidth/width; offset++) {
1700 if ((newMask & Mask) == Mask) {
1701 if (!TD->isLittleEndian())
1702 bestOffset = (origWidth/width - offset - 1) * (width/8);
1703 else
1704 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1705 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1706 bestWidth = width;
1707 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1708 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1709 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1710 }
1711 }
1712 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1713 if (bestWidth) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1714 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1715 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1716 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1717 SDValue Ptr = Lod->getBasePtr();
1718 if (bestOffset != 0)
1719 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1720 DAG.getConstant(bestOffset, PtrType));
1721 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1722 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1723 Lod->getSrcValue(),
1724 Lod->getSrcValueOffset() + bestOffset,
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]1725 false, false, NewAlign);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1726 return DAG.getSetCC(dl, VT,
1727 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1728 DAG.getConstant(bestMask.trunc(bestWidth),
1729 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1730 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1731 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1732 }
1733 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1734
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1735 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1736 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1737 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1738
1739 // If the comparison constant has bits in the upper part, the
1740 // zero-extended value could never match.
1741 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1742 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1743 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1744 case ISD::SETUGT:
1745 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1746 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1747 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1748 case ISD::SETULE:
1749 case ISD::SETNE: return DAG.getConstant(1, VT);
1750 case ISD::SETGT:
1751 case ISD::SETGE:
1752 // True if the sign bit of C1 is set.
1753 return DAG.getConstant(C1.isNegative(), VT);
1754 case ISD::SETLT:
1755 case ISD::SETLE:
1756 // True if the sign bit of C1 isn't set.
1757 return DAG.getConstant(C1.isNonNegative(), VT);
1758 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]1759 break;
1760 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1761 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1762
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1763 // Otherwise, we can perform the comparison with the low bits.
1764 switch (Cond) {
1765 case ISD::SETEQ:
1766 case ISD::SETNE:
1767 case ISD::SETUGT:
1768 case ISD::SETUGE:
1769 case ISD::SETULT:
1770 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1771 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1772 if (DCI.isBeforeLegalizeOps() ||
1773 (isOperationLegal(ISD::SETCC, newVT) &&
1774 getCondCodeAction(Cond, newVT)==Legal))
1775 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1776 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1777 Cond);
1778 break;
1779 }
1780 default:
1781 break; // todo, be more careful with signed comparisons
1782 }
1783 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1784 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1785 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1786 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1787 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1788 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1789
1790 // If the extended part has any inconsistent bits, it cannot ever
1791 // compare equal. In other words, they have to be all ones or all
1792 // zeros.
1793 APInt ExtBits =
1794 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1795 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1796 return DAG.getConstant(Cond == ISD::SETNE, VT);
1797
1798 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1799 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1800 if (Op0Ty == ExtSrcTy) {
1801 ZextOp = N0.getOperand(0);
1802 } else {
1803 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1804 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1805 DAG.getConstant(Imm, Op0Ty));
1806 }
1807 if (!DCI.isCalledByLegalizer())
1808 DCI.AddToWorklist(ZextOp.getNode());
1809 // Otherwise, make this a use of a zext.
1810 return DAG.getSetCC(dl, VT, ZextOp,
1811 DAG.getConstant(C1 & APInt::getLowBitsSet(
1812 ExtDstTyBits,
1813 ExtSrcTyBits),
1814 ExtDstTy),
1815 Cond);
1816 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1817 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1818 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1819 if (N0.getOpcode() == ISD::SETCC &&
1820 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1821 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1822 if (TrueWhenTrue)
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1823 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1824 // Invert the condition.
1825 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1826 CC = ISD::getSetCCInverse(CC,
1827 N0.getOperand(0).getValueType().isInteger());
1828 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1829 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1830
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1831 if ((N0.getOpcode() == ISD::XOR ||
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1832 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1833 N0.getOperand(0).getOpcode() == ISD::XOR &&
1834 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1835 isa<ConstantSDNode>(N0.getOperand(1)) &&
1836 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1837 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1838 // can only do this if the top bits are known zero.
1839 unsigned BitWidth = N0.getValueSizeInBits();
1840 if (DAG.MaskedValueIsZero(N0,
1841 APInt::getHighBitsSet(BitWidth,
1842 BitWidth-1))) {
1843 // Okay, get the un-inverted input value.
1844 SDValue Val;
1845 if (N0.getOpcode() == ISD::XOR)
1846 Val = N0.getOperand(0);
1847 else {
1848 assert(N0.getOpcode() == ISD::AND &&
1849 N0.getOperand(0).getOpcode() == ISD::XOR);
1850 // ((X^1)&1)^1 -> X & 1
1851 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1852 N0.getOperand(0).getOperand(0),
1853 N0.getOperand(1));
1854 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1855
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1856 return DAG.getSetCC(dl, VT, Val, N1,
1857 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1858 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1859 } else if (N1C->getAPIntValue() == 1 &&
1860 (VT == MVT::i1 ||
1861 getBooleanContents() == ZeroOrOneBooleanContent)) {
1862 SDValue Op0 = N0;
1863 if (Op0.getOpcode() == ISD::TRUNCATE)
1864 Op0 = Op0.getOperand(0);
1865
1866 if ((Op0.getOpcode() == ISD::XOR) &&
1867 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1868 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1869 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1870 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1871 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1872 Cond);
1873 } else if (Op0.getOpcode() == ISD::AND &&
1874 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1875 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1876 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1877 if (Op0.getValueType() != VT)
1878 Op0 = DAG.getNode(ISD::AND, dl, VT,
1879 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1880 DAG.getConstant(1, VT));
1881 return DAG.getSetCC(dl, VT, Op0,
1882 DAG.getConstant(0, Op0.getValueType()),
1883 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1884 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1885 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1886 }
1887
1888 APInt MinVal, MaxVal;
1889 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1890 if (ISD::isSignedIntSetCC(Cond)) {
1891 MinVal = APInt::getSignedMinValue(OperandBitSize);
1892 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1893 } else {
1894 MinVal = APInt::getMinValue(OperandBitSize);
1895 MaxVal = APInt::getMaxValue(OperandBitSize);
1896 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1897
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1898 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1899 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1900 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1901 // X >= C0 --> X > (C0-1)
1902 return DAG.getSetCC(dl, VT, N0,
1903 DAG.getConstant(C1-1, N1.getValueType()),
1904 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1905 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1906
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1907 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1908 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1909 // X <= C0 --> X < (C0+1)
1910 return DAG.getSetCC(dl, VT, N0,
1911 DAG.getConstant(C1+1, N1.getValueType()),
1912 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1913 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1914
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1915 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1916 return DAG.getConstant(0, VT); // X < MIN --> false
1917 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1918 return DAG.getConstant(1, VT); // X >= MIN --> true
1919 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1920 return DAG.getConstant(0, VT); // X > MAX --> false
1921 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1922 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1923
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1924 // Canonicalize setgt X, Min --> setne X, Min
1925 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1926 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1927 // Canonicalize setlt X, Max --> setne X, Max
1928 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1929 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1930
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1931 // If we have setult X, 1, turn it into seteq X, 0
1932 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1933 return DAG.getSetCC(dl, VT, N0,
1934 DAG.getConstant(MinVal, N0.getValueType()),
1935 ISD::SETEQ);
1936 // If we have setugt X, Max-1, turn it into seteq X, Max
1937 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1938 return DAG.getSetCC(dl, VT, N0,
1939 DAG.getConstant(MaxVal, N0.getValueType()),
1940 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1941
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1942 // If we have "setcc X, C0", check to see if we can shrink the immediate
1943 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1944
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1945 // SETUGT X, SINTMAX -> SETLT X, 0
1946 if (Cond == ISD::SETUGT &&
1947 C1 == APInt::getSignedMaxValue(OperandBitSize))
1948 return DAG.getSetCC(dl, VT, N0,
1949 DAG.getConstant(0, N1.getValueType()),
1950 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1951
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1952 // SETULT X, SINTMIN -> SETGT X, -1
1953 if (Cond == ISD::SETULT &&
1954 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1955 SDValue ConstMinusOne =
1956 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1957 N1.getValueType());
1958 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1959 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1960
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1961 // Fold bit comparisons when we can.
1962 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1963 (VT == N0.getValueType() ||
1964 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1965 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1966 if (ConstantSDNode *AndRHS =
1967 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1968 EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1969 getPointerTy() : getShiftAmountTy();
1970 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1971 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1972 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1973 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1974 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1975 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1976 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1977 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1978 // (X & 8) == 8 --> (X & 8) >> 3
1979 // Perform the xform if C1 is a single bit.
1980 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]1981 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1982 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1983 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1984 }
1985 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1986 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1987 }
1988
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1989 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1990 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1991 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1992 if (O.getNode()) return O;
1993 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]1994 // If the RHS of an FP comparison is a constant, simplify it away in
1995 // some cases.
1996 if (CFP->getValueAPF().isNaN()) {
1997 // If an operand is known to be a nan, we can fold it.
1998 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]1999 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2000 case 0: // Known false.
2001 return DAG.getConstant(0, VT);
2002 case 1: // Known true.
2003 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2004 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2005 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2006 }
2007 }
2008
2009 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2010 // constant if knowing that the operand is non-nan is enough. We prefer to
2011 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2012 // materialize 0.0.
2013 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2014 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2015
2016 // If the condition is not legal, see if we can find an equivalent one
2017 // which is legal.
2018 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2019 // If the comparison was an awkward floating-point == or != and one of
2020 // the comparison operands is infinity or negative infinity, convert the
2021 // condition to a less-awkward <= or >=.
2022 if (CFP->getValueAPF().isInfinity()) {
2023 if (CFP->getValueAPF().isNegative()) {
2024 if (Cond == ISD::SETOEQ &&
2025 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2026 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2027 if (Cond == ISD::SETUEQ &&
2028 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2029 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2030 if (Cond == ISD::SETUNE &&
2031 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2032 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2033 if (Cond == ISD::SETONE &&
2034 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2035 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2036 } else {
2037 if (Cond == ISD::SETOEQ &&
2038 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2039 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2040 if (Cond == ISD::SETUEQ &&
2041 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2042 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2043 if (Cond == ISD::SETUNE &&
2044 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2045 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2046 if (Cond == ISD::SETONE &&
2047 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2048 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2049 }
2050 }
2051 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2052 }
2053
2054 if (N0 == N1) {
2055 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2056 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2057 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2058 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2059 if (UOF == 2) // FP operators that are undefined on NaNs.
2060 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2061 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2062 return DAG.getConstant(UOF, VT);
2063 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2064 // if it is not already.
2065 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2066 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2067 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2068 }
2069
2070 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2071 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2072 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2073 N0.getOpcode() == ISD::XOR) {
2074 // Simplify (X+Y) == (X+Z) --> Y == Z
2075 if (N0.getOpcode() == N1.getOpcode()) {
2076 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2077 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2078 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2079 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2080 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2081 // If X op Y == Y op X, try other combinations.
2082 if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2083 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2084 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2085 if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2086 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2087 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2088 }
2089 }
2090
2091 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2092 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2093 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2094 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2095 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2096 DAG.getConstant(RHSC->getAPIntValue()-
2097 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2098 N0.getValueType()), Cond);
2099 }
2100
2101 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2102 if (N0.getOpcode() == ISD::XOR)
2103 // If we know that all of the inverted bits are zero, don't bother
2104 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2105 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2106 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2107 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2108 DAG.getConstant(LHSR->getAPIntValue() ^
2109 RHSC->getAPIntValue(),
2110 N0.getValueType()),
2111 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2112 }
2113
2114 // Turn (C1-X) == C2 --> X == C1-C2
2115 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2116 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2117 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2118 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2119 DAG.getConstant(SUBC->getAPIntValue() -
2120 RHSC->getAPIntValue(),
2121 N0.getValueType()),
2122 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2123 }
2124 }
2125 }
2126
2127 // Simplify (X+Z) == X --> Z == 0
2128 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2129 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2130 DAG.getConstant(0, N0.getValueType()), Cond);
2131 if (N0.getOperand(1) == N1) {
2132 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2133 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2134 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2135 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2136 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2137 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2138 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2139 N1,
2140 DAG.getConstant(1, getShiftAmountTy()));
2141 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2142 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2143 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2144 }
2145 }
2146 }
2147
2148 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2149 N1.getOpcode() == ISD::XOR) {
2150 // Simplify X == (X+Z) --> Z == 0
2151 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2152 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2153 DAG.getConstant(0, N1.getValueType()), Cond);
2154 } else if (N1.getOperand(1) == N0) {
2155 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2156 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2157 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2158 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2159 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2160 // X == (Z-X) --> X<<1 == Z
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2161 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2162 DAG.getConstant(1, getShiftAmountTy()));
2163 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2164 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2165 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2166 }
2167 }
2168 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2169
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2170 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2171 // Note that where y is variable and is known to have at most
2172 // one bit set (for example, if it is z&1) we cannot do this;
2173 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2174 if (N0.getOpcode() == ISD::AND)
2175 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2176 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2177 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2178 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2179 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2180 }
2181 }
2182 if (N1.getOpcode() == ISD::AND)
2183 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2184 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2185 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2186 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2187 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2188 }
2189 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2190 }
2191
2192 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2193 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2194 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2195 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2196 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2197 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2198 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2199 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2200 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2201 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2202 break;
2203 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2204 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2205 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2206 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2207 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2208 Temp = DAG.getNOT(dl, N0, MVT::i1);
2209 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2210 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2211 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2212 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2213 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2214 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2215 Temp = DAG.getNOT(dl, N1, MVT::i1);
2216 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2217 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2218 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2219 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2220 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2221 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2222 Temp = DAG.getNOT(dl, N0, MVT::i1);
2223 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2224 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2225 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2226 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2227 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2228 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2229 Temp = DAG.getNOT(dl, N1, MVT::i1);
2230 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2231 break;
2232 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2233 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2234 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2235 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2236 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2237 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2238 }
2239 return N0;
2240 }
2241
2242 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2243 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2244}
2245
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2246/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2247/// node is a GlobalAddress + offset.
Dan Gohman46510a72010-04-15 01:51:59 +0000[diff] [blame^]2248bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2249 int64_t &Offset) const {
2250 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2251 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2252 GA = GASD->getGlobal();
2253 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2254 return true;
2255 }
2256
2257 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2258 SDValue N1 = N->getOperand(0);
2259 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2260 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2261 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2262 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2263 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2264 return true;
2265 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2266 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2267 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2268 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2269 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2270 return true;
2271 }
2272 }
2273 }
2274 return false;
2275}
2276
2277
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2278SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2279PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2280 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2281 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2282}
2283
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2284//===----------------------------------------------------------------------===//
2285// Inline Assembler Implementation Methods
2286//===----------------------------------------------------------------------===//
2287
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2288
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2289TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2290TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2291 // FIXME: lots more standard ones to handle.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2292 if (Constraint.size() == 1) {
2293 switch (Constraint[0]) {
2294 default: break;
2295 case 'r': return C_RegisterClass;
2296 case 'm': // memory
2297 case 'o': // offsetable
2298 case 'V': // not offsetable
2299 return C_Memory;
2300 case 'i': // Simple Integer or Relocatable Constant
2301 case 'n': // Simple Integer
2302 case 's': // Relocatable Constant
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2303 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2304 case 'I': // Target registers.
2305 case 'J':
2306 case 'K':
2307 case 'L':
2308 case 'M':
2309 case 'N':
2310 case 'O':
2311 case 'P':
2312 return C_Other;
2313 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2314 }
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2315
2316 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2317 Constraint[Constraint.size()-1] == '}')
2318 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2319 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2320}
2321
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2322/// LowerXConstraint - try to replace an X constraint, which matches anything,
2323/// with another that has more specific requirements based on the type of the
2324/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2325const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2326 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2327 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2328 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2329 return "f"; // works for many targets
2330 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2331}
2332
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2333/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2334/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2335void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2336 char ConstraintLetter,
Evan Chengda43bcf2008-09-24 00:05:32 +0000[diff] [blame]2337 bool hasMemory,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2338 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2339 SelectionDAG &DAG) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2340 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2341 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2342 case 'X': // Allows any operand; labels (basic block) use this.
2343 if (Op.getOpcode() == ISD::BasicBlock) {
2344 Ops.push_back(Op);
2345 return;
2346 }
2347 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2348 case 'i': // Simple Integer or Relocatable Constant
2349 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2350 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2351 // These operands are interested in values of the form (GV+C), where C may
2352 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2353 // is possible and fine if either GV or C are missing.
2354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2355 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2356
2357 // If we have "(add GV, C)", pull out GV/C
2358 if (Op.getOpcode() == ISD::ADD) {
2359 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2360 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2361 if (C == 0 || GA == 0) {
2362 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2363 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2364 }
2365 if (C == 0 || GA == 0)
2366 C = 0, GA = 0;
2367 }
2368
2369 // If we find a valid operand, map to the TargetXXX version so that the
2370 // value itself doesn't get selected.
2371 if (GA) { // Either &GV or &GV+C
2372 if (ConstraintLetter != 'n') {
2373 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2374 if (C) Offs += C->getZExtValue();
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2375 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2376 Op.getValueType(), Offs));
2377 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2378 }
2379 }
2380 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2381 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2382 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2383 // gcc prints these as sign extended. Sign extend value to 64 bits
2384 // now; without this it would get ZExt'd later in
2385 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2386 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2387 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2388 return;
2389 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2390 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2391 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2392 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2393 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2394}
2395
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2396std::vector<unsigned> TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2397getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2398 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2399 return std::vector<unsigned>();
2400}
2401
2402
2403std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2404getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2405 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2406 if (Constraint[0] != '{')
2407 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2408 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2409
2410 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2411 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2412
2413 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2414 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2415 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2416 E = RI->regclass_end(); RCI != E; ++RCI) {
2417 const TargetRegisterClass *RC = *RCI;
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2418
Dan Gohmanf451cb82010-02-10 16:03:48 +0000[diff] [blame]2419 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2420 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2421 bool isLegal = false;
2422 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2423 I != E; ++I) {
2424 if (isTypeLegal(*I)) {
2425 isLegal = true;
2426 break;
2427 }
2428 }
2429
2430 if (!isLegal) continue;
2431
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2432 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2433 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2434 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2435 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2436 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2437 }
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2438
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2439 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2440}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2441
2442//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2443// Constraint Selection.
2444
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2445/// isMatchingInputConstraint - Return true of this is an input operand that is
2446/// a matching constraint like "4".
2447bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2448 assert(!ConstraintCode.empty() && "No known constraint!");
2449 return isdigit(ConstraintCode[0]);
2450}
2451
2452/// getMatchedOperand - If this is an input matching constraint, this method
2453/// returns the output operand it matches.
2454unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2455 assert(!ConstraintCode.empty() && "No known constraint!");
2456 return atoi(ConstraintCode.c_str());
2457}
2458
2459
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2460/// getConstraintGenerality - Return an integer indicating how general CT
2461/// is.
2462static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2463 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2464 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2465 case TargetLowering::C_Other:
2466 case TargetLowering::C_Unknown:
2467 return 0;
2468 case TargetLowering::C_Register:
2469 return 1;
2470 case TargetLowering::C_RegisterClass:
2471 return 2;
2472 case TargetLowering::C_Memory:
2473 return 3;
2474 }
2475}
2476
2477/// ChooseConstraint - If there are multiple different constraints that we
2478/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]2479/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2480/// Other -> immediates and magic values
2481/// Register -> one specific register
2482/// RegisterClass -> a group of regs
2483/// Memory -> memory
2484/// Ideally, we would pick the most specific constraint possible: if we have
2485/// something that fits into a register, we would pick it. The problem here
2486/// is that if we have something that could either be in a register or in
2487/// memory that use of the register could cause selection of *other*
2488/// operands to fail: they might only succeed if we pick memory. Because of
2489/// this the heuristic we use is:
2490///
2491/// 1) If there is an 'other' constraint, and if the operand is valid for
2492/// that constraint, use it. This makes us take advantage of 'i'
2493/// constraints when available.
2494/// 2) Otherwise, pick the most general constraint present. This prefers
2495/// 'm' over 'r', for example.
2496///
2497static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Evan Chengda43bcf2008-09-24 00:05:32 +0000[diff] [blame]2498 bool hasMemory, const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2499 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2500 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2501 unsigned BestIdx = 0;
2502 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2503 int BestGenerality = -1;
2504
2505 // Loop over the options, keeping track of the most general one.
2506 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2507 TargetLowering::ConstraintType CType =
2508 TLI.getConstraintType(OpInfo.Codes[i]);
2509
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2510 // If this is an 'other' constraint, see if the operand is valid for it.
2511 // For example, on X86 we might have an 'rI' constraint. If the operand
2512 // is an integer in the range [0..31] we want to use I (saving a load
2513 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2514 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2515 assert(OpInfo.Codes[i].size() == 1 &&
2516 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2517 std::vector<SDValue> ResultOps;
Evan Chengda43bcf2008-09-24 00:05:32 +0000[diff] [blame]2518 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2519 ResultOps, *DAG);
2520 if (!ResultOps.empty()) {
2521 BestType = CType;
2522 BestIdx = i;
2523 break;
2524 }
2525 }
2526
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2527 // This constraint letter is more general than the previous one, use it.
2528 int Generality = getConstraintGenerality(CType);
2529 if (Generality > BestGenerality) {
2530 BestType = CType;
2531 BestIdx = i;
2532 BestGenerality = Generality;
2533 }
2534 }
2535
2536 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2537 OpInfo.ConstraintType = BestType;
2538}
2539
2540/// ComputeConstraintToUse - Determines the constraint code and constraint
2541/// type to use for the specific AsmOperandInfo, setting
2542/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2543void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2544 SDValue Op,
Evan Chengda43bcf2008-09-24 00:05:32 +0000[diff] [blame]2545 bool hasMemory,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2546 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2547 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2548
2549 // Single-letter constraints ('r') are very common.
2550 if (OpInfo.Codes.size() == 1) {
2551 OpInfo.ConstraintCode = OpInfo.Codes[0];
2552 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2553 } else {
Evan Chengda43bcf2008-09-24 00:05:32 +0000[diff] [blame]2554 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2555 }
2556
2557 // 'X' matches anything.
2558 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2559 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2560 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]2561 // the result, which is not what we want to look at; leave them alone.
2562 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2563 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2564 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2565 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2566 }
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2567
2568 // Otherwise, try to resolve it to something we know about by looking at
2569 // the actual operand type.
2570 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2571 OpInfo.ConstraintCode = Repl;
2572 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2573 }
2574 }
2575}
2576
2577//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2578// Loop Strength Reduction hooks
2579//===----------------------------------------------------------------------===//
2580
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]2581/// isLegalAddressingMode - Return true if the addressing mode represented
2582/// by AM is legal for this target, for a load/store of the specified type.
2583bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2584 const Type *Ty) const {
2585 // The default implementation of this implements a conservative RISCy, r+r and
2586 // r+i addr mode.
2587
2588 // Allows a sign-extended 16-bit immediate field.
2589 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2590 return false;
2591
2592 // No global is ever allowed as a base.
2593 if (AM.BaseGV)
2594 return false;
2595
2596 // Only support r+r,
2597 switch (AM.Scale) {
2598 case 0: // "r+i" or just "i", depending on HasBaseReg.
2599 break;
2600 case 1:
2601 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2602 return false;
2603 // Otherwise we have r+r or r+i.
2604 break;
2605 case 2:
2606 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2607 return false;
2608 // Allow 2*r as r+r.
2609 break;
2610 }
2611
2612 return true;
2613}
2614
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2615/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2616/// return a DAG expression to select that will generate the same value by
2617/// multiplying by a magic number. See:
2618/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2619SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2620 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2621 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2622 DebugLoc dl= N->getDebugLoc();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2623
2624 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2625 // FIXME: We should be more aggressive here.
2626 if (!isTypeLegal(VT))
2627 return SDValue();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2628
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2629 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2630 APInt::ms magics = d.magic();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2631
2632 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2633 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2634 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2635 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2636 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2637 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2638 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2639 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2640 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2641 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2642 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2643 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2644 // If d > 0 and m < 0, add the numerator
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2645 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2646 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2647 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2648 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2649 }
2650 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2651 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2652 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2653 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2654 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2655 }
2656 // Shift right algebraic if shift value is nonzero
2657 if (magics.s > 0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2658 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2659 DAG.getConstant(magics.s, getShiftAmountTy()));
2660 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2661 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2662 }
2663 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2664 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2665 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2666 getShiftAmountTy()));
2667 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2668 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2669 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2670}
2671
2672/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2673/// return a DAG expression to select that will generate the same value by
2674/// multiplying by a magic number. See:
2675/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2676SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2677 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2678 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2679 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2680
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2681 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2682 // FIXME: We should be more aggressive here.
2683 if (!isTypeLegal(VT))
2684 return SDValue();
2685
2686 // FIXME: We should use a narrower constant when the upper
2687 // bits are known to be zero.
2688 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2689 APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2690
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2691 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2692 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2693 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2694 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2695 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2696 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2697 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2698 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2699 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2700 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2701 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2702 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2703 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2704 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2705
2706 if (magics.a == 0) {
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2707 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2708 "We shouldn't generate an undefined shift!");
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2709 return DAG.getNode(ISD::SRL, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2710 DAG.getConstant(magics.s, getShiftAmountTy()));
2711 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2712 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2713 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2714 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2715 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2716 DAG.getConstant(1, getShiftAmountTy()));
2717 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2718 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2719 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2720 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2721 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2722 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2723 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2724 }
2725}