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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
NAKAMURA Takumi89593932012-04-21 15:31:45 +000037#include "llvm/Support/raw_ostream.h"
38
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000039using namespace llvm;
40
Jia Liubb481f82012-02-28 07:46:26 +000041// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000042// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000043// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000045 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000046 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000047
Akira Hatanakad6bc5232011-12-05 21:26:34 +000048 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000050 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000051}
52
Akira Hatanaka648f00c2012-02-24 22:34:47 +000053static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
Chris Lattnerf0144122009-07-28 03:13:23 +000058const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::JmpLink: return "MipsISD::JmpLink";
Akira Hatanaka58d1e3f2012-10-19 20:59:39 +000061 case MipsISD::TailCall: return "MipsISD::TailCall";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000062 case MipsISD::Hi: return "MipsISD::Hi";
63 case MipsISD::Lo: return "MipsISD::Lo";
64 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000065 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000066 case MipsISD::Ret: return "MipsISD::Ret";
67 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
68 case MipsISD::FPCmp: return "MipsISD::FPCmp";
69 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
70 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
71 case MipsISD::FPRound: return "MipsISD::FPRound";
72 case MipsISD::MAdd: return "MipsISD::MAdd";
73 case MipsISD::MAddu: return "MipsISD::MAddu";
74 case MipsISD::MSub: return "MipsISD::MSub";
75 case MipsISD::MSubu: return "MipsISD::MSubu";
76 case MipsISD::DivRem: return "MipsISD::DivRem";
77 case MipsISD::DivRemU: return "MipsISD::DivRemU";
78 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
79 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000080 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000081 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000082 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000083 case MipsISD::Ext: return "MipsISD::Ext";
84 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanakab6f1dc22012-06-02 00:03:12 +000085 case MipsISD::LWL: return "MipsISD::LWL";
86 case MipsISD::LWR: return "MipsISD::LWR";
87 case MipsISD::SWL: return "MipsISD::SWL";
88 case MipsISD::SWR: return "MipsISD::SWR";
89 case MipsISD::LDL: return "MipsISD::LDL";
90 case MipsISD::LDR: return "MipsISD::LDR";
91 case MipsISD::SDL: return "MipsISD::SDL";
92 case MipsISD::SDR: return "MipsISD::SDR";
Akira Hatanaka6fad5e72012-09-21 23:52:47 +000093 case MipsISD::EXTP: return "MipsISD::EXTP";
94 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
95 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
96 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
97 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
98 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
99 case MipsISD::SHILO: return "MipsISD::SHILO";
100 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
101 case MipsISD::MULT: return "MipsISD::MULT";
102 case MipsISD::MULTU: return "MipsISD::MULTU";
103 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP";
104 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
105 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
106 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
Akira Hatanaka0f843822011-06-07 18:58:42 +0000107 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000108 }
109}
110
111MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +0000112MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +0000113 : TargetLowering(TM, new MipsTargetObjectFile()),
114 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +0000115 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
116 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000117
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000118 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000119 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +0000120 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +0000121 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000122
123 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +0000124 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000125
Akira Hatanaka95934842011-09-24 01:34:44 +0000126 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000127 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000128
Akira Hatanaka28ee4fd2012-05-31 02:59:44 +0000129 if (Subtarget->inMips16Mode()) {
130 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
Akira Hatanaka28ee4fd2012-05-31 02:59:44 +0000131 }
132
Akira Hatanakab430cec2012-09-21 23:58:31 +0000133 if (Subtarget->hasDSP()) {
134 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
135
136 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
137 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
138
139 // Expand all builtin opcodes.
140 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
141 setOperationAction(Opc, VecTys[i], Expand);
142
143 setOperationAction(ISD::LOAD, VecTys[i], Legal);
144 setOperationAction(ISD::STORE, VecTys[i], Legal);
145 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
146 }
147 }
148
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000149 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000150 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000151
152 // When dealing with single precision only, use libcalls
153 if (!Subtarget->isSingleFloat()) {
154 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000155 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000156 else
Craig Topper420761a2012-04-20 07:30:17 +0000157 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000158 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000159 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000160
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000161 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000162 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
163 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
164 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000165
Eli Friedman6055a6a2009-07-17 04:07:24 +0000166 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000167 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
168 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000169
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000170 // Used by legalize types to correctly generate the setcc result.
171 // Without this, every float setcc comes with a AND/OR with the result,
172 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000173 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000174 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000175
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000176 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000177 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000178 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000179 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
180 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::SELECT, MVT::f32, Custom);
183 setOperationAction(ISD::SELECT, MVT::f64, Custom);
184 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000185 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000187 setOperationAction(ISD::SETCC, MVT::f32, Custom);
188 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000189 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000190 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
193 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
194 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
Akira Hatanakaf934d152012-09-15 01:02:03 +0000195 if (!Subtarget->inMips16Mode()) {
196 setOperationAction(ISD::LOAD, MVT::i32, Custom);
197 setOperationAction(ISD::STORE, MVT::i32, Custom);
198 }
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000199
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000200 if (!TM.Options.NoNaNsFPMath) {
201 setOperationAction(ISD::FABS, MVT::f32, Custom);
202 setOperationAction(ISD::FABS, MVT::f64, Custom);
203 }
204
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000205 if (HasMips64) {
206 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
207 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
208 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
209 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
210 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
211 setOperationAction(ISD::SELECT, MVT::i64, Custom);
Akira Hatanaka7664f052012-06-02 00:04:42 +0000212 setOperationAction(ISD::LOAD, MVT::i64, Custom);
213 setOperationAction(ISD::STORE, MVT::i64, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000214 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000215
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000216 if (!HasMips64) {
217 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
218 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
219 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
220 }
221
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000222 setOperationAction(ISD::SDIV, MVT::i32, Expand);
223 setOperationAction(ISD::SREM, MVT::i32, Expand);
224 setOperationAction(ISD::UDIV, MVT::i32, Expand);
225 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000226 setOperationAction(ISD::SDIV, MVT::i64, Expand);
227 setOperationAction(ISD::SREM, MVT::i64, Expand);
228 setOperationAction(ISD::UDIV, MVT::i64, Expand);
229 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000230
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000231 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000232 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
233 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
234 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
235 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000236 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000237 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000238 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000239 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
240 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000241 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000242 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000243 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000244 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
245 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
247 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000248 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000249 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Akira Hatanaka1d165f12012-07-31 20:54:48 +0000250 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000252
Akira Hatanaka56633442011-09-20 23:53:09 +0000253 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000254 setOperationAction(ISD::ROTR, MVT::i32, Expand);
255
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000256 if (!Subtarget->hasMips64r2())
257 setOperationAction(ISD::ROTR, MVT::i64, Expand);
258
Owen Anderson825b72b2009-08-11 20:47:22 +0000259 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000260 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000261 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000262 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000263 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
264 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000265 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000266 setOperationAction(ISD::FLOG, MVT::f32, Expand);
267 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
268 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
269 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000270 setOperationAction(ISD::FMA, MVT::f32, Expand);
271 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000272 setOperationAction(ISD::FREM, MVT::f32, Expand);
273 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000274
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000275 if (!TM.Options.NoNaNsFPMath) {
276 setOperationAction(ISD::FNEG, MVT::f32, Expand);
277 setOperationAction(ISD::FNEG, MVT::f64, Expand);
278 }
279
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000280 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000281 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000282 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000283 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000284
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000285 setOperationAction(ISD::VAARG, MVT::Other, Expand);
286 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
287 setOperationAction(ISD::VAEND, MVT::Other, Expand);
288
Akira Hatanakab430cec2012-09-21 23:58:31 +0000289 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
290 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
291
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000292 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000293 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
294 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000295
Jia Liubb481f82012-02-28 07:46:26 +0000296 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
297 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
298 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
299 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000300
Eli Friedman26689ac2011-08-03 21:06:02 +0000301 setInsertFencesForAtomic(true);
302
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000303 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000304 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000306 }
307
Akira Hatanakac79507a2011-12-21 00:20:27 +0000308 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000309 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000310 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
311 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000312
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000313 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000314 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000315 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
316 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000317
Akira Hatanaka7664f052012-06-02 00:04:42 +0000318 if (HasMips64) {
319 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
320 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
321 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
322 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
323 }
324
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000325 setTargetDAGCombine(ISD::ADDE);
326 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000327 setTargetDAGCombine(ISD::SDIVREM);
328 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000329 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000330 setTargetDAGCombine(ISD::AND);
331 setTargetDAGCombine(ISD::OR);
Akira Hatanaka87827072012-06-13 20:33:18 +0000332 setTargetDAGCombine(ISD::ADD);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000333
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000334 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000335
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000336 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000337 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000338
Akira Hatanaka590baca2012-02-02 03:13:40 +0000339 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
340 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Akira Hatanakae193b322012-06-13 19:33:32 +0000341
342 maxStoresPerMemcpy = 16;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000343}
344
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000345bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000346 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000347
Akira Hatanakaf934d152012-09-15 01:02:03 +0000348 if (Subtarget->inMips16Mode())
349 return false;
350
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000351 switch (SVT) {
352 case MVT::i64:
353 case MVT::i32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000354 return true;
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000355 default:
356 return false;
357 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000358}
359
Duncan Sands28b77e92011-09-06 19:07:46 +0000360EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000361 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000362}
363
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000364// SelectMadd -
365// Transforms a subgraph in CurDAG if the following pattern is found:
366// (addc multLo, Lo0), (adde multHi, Hi0),
367// where,
368// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000369// Lo0: initial value of Lo register
370// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000371// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000372static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000373 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000374 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000375 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000376
377 if (ADDCNode->getOpcode() != ISD::ADDC)
378 return false;
379
380 SDValue MultHi = ADDENode->getOperand(0);
381 SDValue MultLo = ADDCNode->getOperand(0);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000382 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000383 unsigned MultOpc = MultHi.getOpcode();
384
385 // MultHi and MultLo must be generated by the same node,
386 if (MultLo.getNode() != MultNode)
387 return false;
388
389 // and it must be a multiplication.
390 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
391 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000392
393 // MultLo amd MultHi must be the first and second output of MultNode
394 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000395 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
396 return false;
397
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000398 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000399 // of the values of MultNode, in which case MultNode will be removed in later
400 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000401 // If there exist users other than ADDENode or ADDCNode, this function returns
402 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000403 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000404 // produced.
405 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
406 return false;
407
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000408 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000409 DebugLoc dl = ADDENode->getDebugLoc();
410
411 // create MipsMAdd(u) node
412 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000413
Akira Hatanaka82099682011-12-19 19:52:25 +0000414 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000415 MultNode->getOperand(0),// Factor 0
416 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000417 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000418 ADDENode->getOperand(1));// Hi0
419
420 // create CopyFromReg nodes
421 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
422 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000423 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000424 Mips::HI, MVT::i32,
425 CopyFromLo.getValue(2));
426
427 // replace uses of adde and addc here
428 if (!SDValue(ADDCNode, 0).use_empty())
429 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
430
431 if (!SDValue(ADDENode, 0).use_empty())
432 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
433
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000434 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000435}
436
437// SelectMsub -
438// Transforms a subgraph in CurDAG if the following pattern is found:
439// (addc Lo0, multLo), (sube Hi0, multHi),
440// where,
441// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000442// Lo0: initial value of Lo register
443// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000444// Return true if pattern matching was successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000445static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000446 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000447 // for the matching to be successful.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000448 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000449
450 if (SUBCNode->getOpcode() != ISD::SUBC)
451 return false;
452
453 SDValue MultHi = SUBENode->getOperand(1);
454 SDValue MultLo = SUBCNode->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000455 SDNode *MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000456 unsigned MultOpc = MultHi.getOpcode();
457
458 // MultHi and MultLo must be generated by the same node,
459 if (MultLo.getNode() != MultNode)
460 return false;
461
462 // and it must be a multiplication.
463 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
464 return false;
465
466 // MultLo amd MultHi must be the first and second output of MultNode
467 // respectively.
468 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
469 return false;
470
471 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
472 // of the values of MultNode, in which case MultNode will be removed in later
473 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000474 // If there exist users other than SUBENode or SUBCNode, this function returns
475 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000476 // instruction node rather than a pair of MULT and MSUB instructions being
477 // produced.
478 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
479 return false;
480
481 SDValue Chain = CurDAG->getEntryNode();
482 DebugLoc dl = SUBENode->getDebugLoc();
483
484 // create MipsSub(u) node
485 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
486
Akira Hatanaka82099682011-12-19 19:52:25 +0000487 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000488 MultNode->getOperand(0),// Factor 0
489 MultNode->getOperand(1),// Factor 1
490 SUBCNode->getOperand(0),// Lo0
491 SUBENode->getOperand(0));// Hi0
492
493 // create CopyFromReg nodes
494 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
495 MSub);
496 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
497 Mips::HI, MVT::i32,
498 CopyFromLo.getValue(2));
499
500 // replace uses of sube and subc here
501 if (!SDValue(SUBCNode, 0).use_empty())
502 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
503
504 if (!SDValue(SUBENode, 0).use_empty())
505 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
506
507 return true;
508}
509
Akira Hatanaka864f6602012-06-14 21:10:56 +0000510static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000511 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000512 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000513 if (DCI.isBeforeLegalize())
514 return SDValue();
515
Akira Hatanakae184fec2011-11-11 04:18:21 +0000516 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
517 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000518 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000519
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000520 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000521}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000522
Akira Hatanaka864f6602012-06-14 21:10:56 +0000523static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000524 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000525 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000526 if (DCI.isBeforeLegalize())
527 return SDValue();
528
Akira Hatanakae184fec2011-11-11 04:18:21 +0000529 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
530 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000531 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000532
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000533 return SDValue();
534}
535
Akira Hatanaka864f6602012-06-14 21:10:56 +0000536static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000537 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000538 const MipsSubtarget *Subtarget) {
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000539 if (DCI.isBeforeLegalizeOps())
540 return SDValue();
541
Akira Hatanakadda4a072011-10-03 21:06:13 +0000542 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000543 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
544 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000545 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
546 MipsISD::DivRemU;
547 DebugLoc dl = N->getDebugLoc();
548
549 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
550 N->getOperand(0), N->getOperand(1));
551 SDValue InChain = DAG.getEntryNode();
552 SDValue InGlue = DivRem;
553
554 // insert MFLO
555 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000556 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000557 InGlue);
558 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
559 InChain = CopyFromLo.getValue(1);
560 InGlue = CopyFromLo.getValue(2);
561 }
562
563 // insert MFHI
564 if (N->hasAnyUseOfValue(1)) {
565 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000566 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000567 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
568 }
569
570 return SDValue();
571}
572
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000573static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
574 switch (CC) {
575 default: llvm_unreachable("Unknown fp condition code!");
576 case ISD::SETEQ:
577 case ISD::SETOEQ: return Mips::FCOND_OEQ;
578 case ISD::SETUNE: return Mips::FCOND_UNE;
579 case ISD::SETLT:
580 case ISD::SETOLT: return Mips::FCOND_OLT;
581 case ISD::SETGT:
582 case ISD::SETOGT: return Mips::FCOND_OGT;
583 case ISD::SETLE:
584 case ISD::SETOLE: return Mips::FCOND_OLE;
585 case ISD::SETGE:
586 case ISD::SETOGE: return Mips::FCOND_OGE;
587 case ISD::SETULT: return Mips::FCOND_ULT;
588 case ISD::SETULE: return Mips::FCOND_ULE;
589 case ISD::SETUGT: return Mips::FCOND_UGT;
590 case ISD::SETUGE: return Mips::FCOND_UGE;
591 case ISD::SETUO: return Mips::FCOND_UN;
592 case ISD::SETO: return Mips::FCOND_OR;
593 case ISD::SETNE:
594 case ISD::SETONE: return Mips::FCOND_ONE;
595 case ISD::SETUEQ: return Mips::FCOND_UEQ;
596 }
597}
598
599
600// Returns true if condition code has to be inverted.
601static bool InvertFPCondCode(Mips::CondCode CC) {
602 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
603 return false;
604
Akira Hatanaka82099682011-12-19 19:52:25 +0000605 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
606 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000607
Akira Hatanaka82099682011-12-19 19:52:25 +0000608 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000609}
610
611// Creates and returns an FPCmp node from a setcc node.
612// Returns Op if setcc is not a floating point comparison.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000613static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000614 // must be a SETCC node
615 if (Op.getOpcode() != ISD::SETCC)
616 return Op;
617
618 SDValue LHS = Op.getOperand(0);
619
620 if (!LHS.getValueType().isFloatingPoint())
621 return Op;
622
623 SDValue RHS = Op.getOperand(1);
624 DebugLoc dl = Op.getDebugLoc();
625
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000626 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
627 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000628 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
629
630 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
631 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
632}
633
634// Creates and returns a CMovFPT/F node.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000635static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000636 SDValue False, DebugLoc DL) {
637 bool invert = InvertFPCondCode((Mips::CondCode)
638 cast<ConstantSDNode>(Cond.getOperand(2))
639 ->getSExtValue());
640
641 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
642 True.getValueType(), True, False, Cond);
643}
644
Akira Hatanaka864f6602012-06-14 21:10:56 +0000645static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000646 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000647 const MipsSubtarget *Subtarget) {
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000648 if (DCI.isBeforeLegalizeOps())
649 return SDValue();
650
651 SDValue SetCC = N->getOperand(0);
652
653 if ((SetCC.getOpcode() != ISD::SETCC) ||
654 !SetCC.getOperand(0).getValueType().isInteger())
655 return SDValue();
656
657 SDValue False = N->getOperand(2);
658 EVT FalseTy = False.getValueType();
659
660 if (!FalseTy.isInteger())
661 return SDValue();
662
663 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
664
665 if (!CN || CN->getZExtValue())
666 return SDValue();
667
668 const DebugLoc DL = N->getDebugLoc();
669 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
670 SDValue True = N->getOperand(1);
Akira Hatanaka864f6602012-06-14 21:10:56 +0000671
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000672 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
673 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
Akira Hatanaka864f6602012-06-14 21:10:56 +0000674
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000675 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
676}
677
Akira Hatanaka864f6602012-06-14 21:10:56 +0000678static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000679 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000680 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000681 // Pattern match EXT.
682 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
683 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000684 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000685 return SDValue();
686
687 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000688 unsigned ShiftRightOpc = ShiftRight.getOpcode();
689
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000690 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000691 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000692 return SDValue();
693
694 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000695 ConstantSDNode *CN;
696 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
697 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000698
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000699 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000700 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000701
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000702 // Op's second operand must be a shifted mask.
703 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000704 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000705 return SDValue();
706
707 // Return if the shifted mask does not start at bit 0 or the sum of its size
708 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000709 EVT ValTy = N->getValueType(0);
710 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000711 return SDValue();
712
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000713 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000714 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000715 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000716}
Jia Liubb481f82012-02-28 07:46:26 +0000717
Akira Hatanaka864f6602012-06-14 21:10:56 +0000718static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000719 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000720 const MipsSubtarget *Subtarget) {
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000721 // Pattern match INS.
722 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000723 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000724 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000725 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000726 return SDValue();
727
728 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
729 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
730 ConstantSDNode *CN;
731
732 // See if Op's first operand matches (and $src1 , mask0).
733 if (And0.getOpcode() != ISD::AND)
734 return SDValue();
735
736 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000737 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000738 return SDValue();
739
740 // See if Op's second operand matches (and (shl $src, pos), mask1).
741 if (And1.getOpcode() != ISD::AND)
742 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000743
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000744 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000745 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000746 return SDValue();
747
748 // The shift masks must have the same position and size.
749 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
750 return SDValue();
751
752 SDValue Shl = And1.getOperand(0);
753 if (Shl.getOpcode() != ISD::SHL)
754 return SDValue();
755
756 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
757 return SDValue();
758
759 unsigned Shamt = CN->getZExtValue();
760
761 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000762 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000763 EVT ValTy = N->getValueType(0);
764 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000765 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000766
Akira Hatanaka82099682011-12-19 19:52:25 +0000767 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000768 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000769 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000770}
Jia Liubb481f82012-02-28 07:46:26 +0000771
Akira Hatanaka864f6602012-06-14 21:10:56 +0000772static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
Akira Hatanaka87827072012-06-13 20:33:18 +0000773 TargetLowering::DAGCombinerInfo &DCI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000774 const MipsSubtarget *Subtarget) {
Akira Hatanaka87827072012-06-13 20:33:18 +0000775 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
776
777 if (DCI.isBeforeLegalizeOps())
778 return SDValue();
779
780 SDValue Add = N->getOperand(1);
781
782 if (Add.getOpcode() != ISD::ADD)
783 return SDValue();
784
785 SDValue Lo = Add.getOperand(1);
786
787 if ((Lo.getOpcode() != MipsISD::Lo) ||
788 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
789 return SDValue();
790
791 EVT ValTy = N->getValueType(0);
792 DebugLoc DL = N->getDebugLoc();
793
794 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
795 Add.getOperand(0));
796 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
797}
798
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000799SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000800 const {
801 SelectionDAG &DAG = DCI.DAG;
802 unsigned opc = N->getOpcode();
803
804 switch (opc) {
805 default: break;
806 case ISD::ADDE:
807 return PerformADDECombine(N, DAG, DCI, Subtarget);
808 case ISD::SUBE:
809 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000810 case ISD::SDIVREM:
811 case ISD::UDIVREM:
812 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000813 case ISD::SELECT:
Akira Hatanaka864f6602012-06-14 21:10:56 +0000814 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000815 case ISD::AND:
816 return PerformANDCombine(N, DAG, DCI, Subtarget);
817 case ISD::OR:
818 return PerformORCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka87827072012-06-13 20:33:18 +0000819 case ISD::ADD:
820 return PerformADDCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000821 }
822
823 return SDValue();
824}
825
Akira Hatanakab430cec2012-09-21 23:58:31 +0000826void
827MipsTargetLowering::LowerOperationWrapper(SDNode *N,
828 SmallVectorImpl<SDValue> &Results,
829 SelectionDAG &DAG) const {
830 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
831
832 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
833 Results.push_back(Res.getValue(I));
834}
835
836void
837MipsTargetLowering::ReplaceNodeResults(SDNode *N,
838 SmallVectorImpl<SDValue> &Results,
839 SelectionDAG &DAG) const {
840 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
841
842 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
843 Results.push_back(Res.getValue(I));
844}
845
Dan Gohman475871a2008-07-27 21:46:04 +0000846SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000847LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000848{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000849 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000850 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000851 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000852 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000853 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000854 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000855 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
856 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000857 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka3fef29d2012-07-11 19:32:27 +0000858 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000859 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000860 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000861 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000862 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000863 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakaba584fe2012-07-11 00:53:32 +0000864 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000865 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000866 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000867 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
868 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
869 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +0000870 case ISD::LOAD: return LowerLOAD(Op, DAG);
871 case ISD::STORE: return LowerSTORE(Op, DAG);
Akira Hatanakafd89e6f2012-09-27 02:05:42 +0000872 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
873 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000874 }
Dan Gohman475871a2008-07-27 21:46:04 +0000875 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000876}
877
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000878//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000879// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000880//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000881
882// AddLiveIn - This helper function adds the specified physical register to the
883// MachineFunction as a live in value. It also creates a corresponding
884// virtual register for it.
885static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000886AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000887{
888 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000889 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
890 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000891 return VReg;
892}
893
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000894// Get fp branch code (not opcode) from condition code.
895static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
896 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
897 return Mips::BRANCH_T;
898
Akira Hatanaka82099682011-12-19 19:52:25 +0000899 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
900 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000901
Akira Hatanaka82099682011-12-19 19:52:25 +0000902 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000903}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000904
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000905/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000906static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
907 DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000908 const MipsSubtarget *Subtarget,
Akira Hatanaka14487d42011-06-07 19:28:39 +0000909 const TargetInstrInfo *TII,
910 bool isFPCmp, unsigned Opc) {
911 // There is no need to expand CMov instructions if target has
912 // conditional moves.
913 if (Subtarget->hasCondMov())
914 return BB;
915
916 // To "insert" a SELECT_CC instruction, we actually have to insert the
917 // diamond control-flow pattern. The incoming instruction knows the
918 // destination vreg to set, the condition code register to branch on, the
919 // true/false values to select between, and a branch opcode to use.
920 const BasicBlock *LLVM_BB = BB->getBasicBlock();
921 MachineFunction::iterator It = BB;
922 ++It;
923
924 // thisMBB:
925 // ...
926 // TrueVal = ...
927 // setcc r1, r2, r3
928 // bNE r1, r0, copy1MBB
929 // fallthrough --> copy0MBB
930 MachineBasicBlock *thisMBB = BB;
931 MachineFunction *F = BB->getParent();
932 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
933 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
934 F->insert(It, copy0MBB);
935 F->insert(It, sinkMBB);
936
937 // Transfer the remainder of BB and its successor edges to sinkMBB.
938 sinkMBB->splice(sinkMBB->begin(), BB,
939 llvm::next(MachineBasicBlock::iterator(MI)),
940 BB->end());
941 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
942
943 // Next, add the true and fallthrough blocks as its successors.
944 BB->addSuccessor(copy0MBB);
945 BB->addSuccessor(sinkMBB);
946
947 // Emit the right instruction according to the type of the operands compared
948 if (isFPCmp)
949 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
950 else
951 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
952 .addReg(Mips::ZERO).addMBB(sinkMBB);
953
954 // copy0MBB:
955 // %FalseValue = ...
956 // # fallthrough to sinkMBB
957 BB = copy0MBB;
958
959 // Update machine-CFG edges
960 BB->addSuccessor(sinkMBB);
961
962 // sinkMBB:
963 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
964 // ...
965 BB = sinkMBB;
966
967 if (isFPCmp)
968 BuildMI(*BB, BB->begin(), dl,
969 TII->get(Mips::PHI), MI->getOperand(0).getReg())
970 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
971 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
972 else
973 BuildMI(*BB, BB->begin(), dl,
974 TII->get(Mips::PHI), MI->getOperand(0).getReg())
975 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
976 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
977
978 MI->eraseFromParent(); // The pseudo instruction is gone now.
979 return BB;
980}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000981*/
Akira Hatanaka01f70892012-09-27 02:15:57 +0000982
983MachineBasicBlock *
984MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
985 // $bb:
986 // bposge32_pseudo $vr0
987 // =>
988 // $bb:
989 // bposge32 $tbb
990 // $fbb:
991 // li $vr2, 0
992 // b $sink
993 // $tbb:
994 // li $vr1, 1
995 // $sink:
996 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
997
998 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
999 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1000 const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1001 DebugLoc DL = MI->getDebugLoc();
1002 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1003 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1004 MachineFunction *F = BB->getParent();
1005 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1006 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1007 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1008 F->insert(It, FBB);
1009 F->insert(It, TBB);
1010 F->insert(It, Sink);
1011
1012 // Transfer the remainder of BB and its successor edges to Sink.
1013 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1014 BB->end());
1015 Sink->transferSuccessorsAndUpdatePHIs(BB);
1016
1017 // Add successors.
1018 BB->addSuccessor(FBB);
1019 BB->addSuccessor(TBB);
1020 FBB->addSuccessor(Sink);
1021 TBB->addSuccessor(Sink);
1022
1023 // Insert the real bposge32 instruction to $BB.
1024 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1025
1026 // Fill $FBB.
1027 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1028 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1029 .addReg(Mips::ZERO).addImm(0);
1030 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1031
1032 // Fill $TBB.
1033 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1034 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1035 .addReg(Mips::ZERO).addImm(1);
1036
1037 // Insert phi function to $Sink.
1038 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1039 MI->getOperand(0).getReg())
1040 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1041
1042 MI->eraseFromParent(); // The pseudo instruction is gone now.
1043 return Sink;
1044}
1045
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001046MachineBasicBlock *
1047MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +00001048 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001049 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +00001050 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001051 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001052 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001053 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1054 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001055 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001056 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1057 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001058 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001059 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +00001060 case Mips::ATOMIC_LOAD_ADD_I64:
1061 case Mips::ATOMIC_LOAD_ADD_I64_P8:
1062 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001063
1064 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001065 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001066 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1067 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001068 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001069 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1070 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001071 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001072 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +00001073 case Mips::ATOMIC_LOAD_AND_I64:
1074 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +00001075 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001076
1077 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001078 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001079 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1080 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001081 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001082 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1083 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001084 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001085 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +00001086 case Mips::ATOMIC_LOAD_OR_I64:
1087 case Mips::ATOMIC_LOAD_OR_I64_P8:
1088 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001089
1090 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001091 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001092 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1093 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001094 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001095 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1096 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001097 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001098 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +00001099 case Mips::ATOMIC_LOAD_XOR_I64:
1100 case Mips::ATOMIC_LOAD_XOR_I64_P8:
1101 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001102
1103 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001104 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001105 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1106 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001107 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001108 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1109 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001110 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001111 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +00001112 case Mips::ATOMIC_LOAD_NAND_I64:
1113 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1114 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001115
1116 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001117 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001118 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1119 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001120 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001121 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1122 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001123 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001124 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +00001125 case Mips::ATOMIC_LOAD_SUB_I64:
1126 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1127 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001128
1129 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001130 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001131 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1132 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001133 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001134 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1135 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001136 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001137 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001138 case Mips::ATOMIC_SWAP_I64:
1139 case Mips::ATOMIC_SWAP_I64_P8:
1140 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001141
1142 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +00001143 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001144 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1145 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +00001146 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001147 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1148 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +00001149 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001150 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +00001151 case Mips::ATOMIC_CMP_SWAP_I64:
1152 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1153 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka01f70892012-09-27 02:15:57 +00001154 case Mips::BPOSGE32_PSEUDO:
1155 return EmitBPOSGE32(MI, BB);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001156 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001157}
1158
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001159// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1160// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1161MachineBasicBlock *
1162MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +00001163 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001164 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001165 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001166
1167 MachineFunction *MF = BB->getParent();
1168 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001169 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001170 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1171 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001172 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1173
1174 if (Size == 4) {
1175 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1176 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1177 AND = Mips::AND;
1178 NOR = Mips::NOR;
1179 ZERO = Mips::ZERO;
1180 BEQ = Mips::BEQ;
1181 }
1182 else {
1183 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1184 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1185 AND = Mips::AND64;
1186 NOR = Mips::NOR64;
1187 ZERO = Mips::ZERO_64;
1188 BEQ = Mips::BEQ64;
1189 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001190
Akira Hatanaka4061da12011-07-19 20:11:17 +00001191 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001192 unsigned Ptr = MI->getOperand(1).getReg();
1193 unsigned Incr = MI->getOperand(2).getReg();
1194
Akira Hatanaka4061da12011-07-19 20:11:17 +00001195 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1196 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1197 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001198
1199 // insert new blocks after the current block
1200 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1201 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1202 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1203 MachineFunction::iterator It = BB;
1204 ++It;
1205 MF->insert(It, loopMBB);
1206 MF->insert(It, exitMBB);
1207
1208 // Transfer the remainder of BB and its successor edges to exitMBB.
1209 exitMBB->splice(exitMBB->begin(), BB,
1210 llvm::next(MachineBasicBlock::iterator(MI)),
1211 BB->end());
1212 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1213
1214 // thisMBB:
1215 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001216 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001217 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001218 loopMBB->addSuccessor(loopMBB);
1219 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001220
1221 // loopMBB:
1222 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001223 // <binop> storeval, oldval, incr
1224 // sc success, storeval, 0(ptr)
1225 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001226 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001227 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001228 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001229 // and andres, oldval, incr
1230 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001231 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1232 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001233 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001234 // <binop> storeval, oldval, incr
1235 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001236 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001237 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001238 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001239 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1240 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001241
1242 MI->eraseFromParent(); // The instruction is gone now.
1243
Akira Hatanaka939ece12011-07-19 03:42:13 +00001244 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001245}
1246
1247MachineBasicBlock *
1248MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001249 MachineBasicBlock *BB,
1250 unsigned Size, unsigned BinOpcode,
1251 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001252 assert((Size == 1 || Size == 2) &&
1253 "Unsupported size for EmitAtomicBinaryPartial.");
1254
1255 MachineFunction *MF = BB->getParent();
1256 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1257 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1259 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001260 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1261 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001262
1263 unsigned Dest = MI->getOperand(0).getReg();
1264 unsigned Ptr = MI->getOperand(1).getReg();
1265 unsigned Incr = MI->getOperand(2).getReg();
1266
Akira Hatanaka4061da12011-07-19 20:11:17 +00001267 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1268 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001269 unsigned Mask = RegInfo.createVirtualRegister(RC);
1270 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001271 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1272 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001273 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001274 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1275 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1276 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1277 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1278 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001279 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001280 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1281 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1282 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1283 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1284 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001285
1286 // insert new blocks after the current block
1287 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1288 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001289 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001290 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1291 MachineFunction::iterator It = BB;
1292 ++It;
1293 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001294 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001295 MF->insert(It, exitMBB);
1296
1297 // Transfer the remainder of BB and its successor edges to exitMBB.
1298 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001299 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001300 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1301
Akira Hatanaka81b44112011-07-19 17:09:53 +00001302 BB->addSuccessor(loopMBB);
1303 loopMBB->addSuccessor(loopMBB);
1304 loopMBB->addSuccessor(sinkMBB);
1305 sinkMBB->addSuccessor(exitMBB);
1306
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001307 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001308 // addiu masklsb2,$0,-4 # 0xfffffffc
1309 // and alignedaddr,ptr,masklsb2
1310 // andi ptrlsb2,ptr,3
1311 // sll shiftamt,ptrlsb2,3
1312 // ori maskupper,$0,255 # 0xff
1313 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001314 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001315 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001316
1317 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001318 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1319 .addReg(Mips::ZERO).addImm(-4);
1320 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1321 .addReg(Ptr).addReg(MaskLSB2);
1322 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1323 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1324 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1325 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001326 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1327 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001328 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001329 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001330
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001331 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001332 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001333 // ll oldval,0(alignedaddr)
1334 // binop binopres,oldval,incr2
1335 // and newval,binopres,mask
1336 // and maskedoldval0,oldval,mask2
1337 // or storeval,maskedoldval0,newval
1338 // sc success,storeval,0(alignedaddr)
1339 // beq success,$0,loopMBB
1340
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001341 // atomic.swap
1342 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001343 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001344 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001345 // and maskedoldval0,oldval,mask2
1346 // or storeval,maskedoldval0,newval
1347 // sc success,storeval,0(alignedaddr)
1348 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001349
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001350 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001351 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001352 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001353 // and andres, oldval, incr2
1354 // nor binopres, $0, andres
1355 // and newval, binopres, mask
1356 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1357 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1358 .addReg(Mips::ZERO).addReg(AndRes);
1359 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001360 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001361 // <binop> binopres, oldval, incr2
1362 // and newval, binopres, mask
1363 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1364 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001365 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001366 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001367 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001368 }
Jia Liubb481f82012-02-28 07:46:26 +00001369
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001370 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001371 .addReg(OldVal).addReg(Mask2);
1372 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001373 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001374 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001375 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001376 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001377 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001378
Akira Hatanaka939ece12011-07-19 03:42:13 +00001379 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001380 // and maskedoldval1,oldval,mask
1381 // srl srlres,maskedoldval1,shiftamt
1382 // sll sllres,srlres,24
1383 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001384 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001385 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001386
Akira Hatanaka4061da12011-07-19 20:11:17 +00001387 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1388 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001389 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1390 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001391 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1392 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001393 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001394 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001395
1396 MI->eraseFromParent(); // The instruction is gone now.
1397
Akira Hatanaka939ece12011-07-19 03:42:13 +00001398 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001399}
1400
1401MachineBasicBlock *
1402MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001403 MachineBasicBlock *BB,
1404 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001405 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001406
1407 MachineFunction *MF = BB->getParent();
1408 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001409 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001410 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1411 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001412 unsigned LL, SC, ZERO, BNE, BEQ;
1413
1414 if (Size == 4) {
1415 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1416 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1417 ZERO = Mips::ZERO;
1418 BNE = Mips::BNE;
1419 BEQ = Mips::BEQ;
1420 }
1421 else {
1422 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1423 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1424 ZERO = Mips::ZERO_64;
1425 BNE = Mips::BNE64;
1426 BEQ = Mips::BEQ64;
1427 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001428
1429 unsigned Dest = MI->getOperand(0).getReg();
1430 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001431 unsigned OldVal = MI->getOperand(2).getReg();
1432 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001433
Akira Hatanaka4061da12011-07-19 20:11:17 +00001434 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001435
1436 // insert new blocks after the current block
1437 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1438 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1439 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1440 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1441 MachineFunction::iterator It = BB;
1442 ++It;
1443 MF->insert(It, loop1MBB);
1444 MF->insert(It, loop2MBB);
1445 MF->insert(It, exitMBB);
1446
1447 // Transfer the remainder of BB and its successor edges to exitMBB.
1448 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001449 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001450 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1451
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001452 // thisMBB:
1453 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001454 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001455 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001456 loop1MBB->addSuccessor(exitMBB);
1457 loop1MBB->addSuccessor(loop2MBB);
1458 loop2MBB->addSuccessor(loop1MBB);
1459 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001460
1461 // loop1MBB:
1462 // ll dest, 0(ptr)
1463 // bne dest, oldval, exitMBB
1464 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001465 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1466 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001467 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001468
1469 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001470 // sc success, newval, 0(ptr)
1471 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001472 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001473 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001474 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001475 BuildMI(BB, dl, TII->get(BEQ))
1476 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001477
1478 MI->eraseFromParent(); // The instruction is gone now.
1479
Akira Hatanaka939ece12011-07-19 03:42:13 +00001480 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001481}
1482
1483MachineBasicBlock *
1484MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001485 MachineBasicBlock *BB,
1486 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001487 assert((Size == 1 || Size == 2) &&
1488 "Unsupported size for EmitAtomicCmpSwapPartial.");
1489
1490 MachineFunction *MF = BB->getParent();
1491 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1492 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1493 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1494 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001495 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1496 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001497
1498 unsigned Dest = MI->getOperand(0).getReg();
1499 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001500 unsigned CmpVal = MI->getOperand(2).getReg();
1501 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001502
Akira Hatanaka4061da12011-07-19 20:11:17 +00001503 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1504 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001505 unsigned Mask = RegInfo.createVirtualRegister(RC);
1506 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001507 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1508 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1509 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1510 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1511 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1512 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1513 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1514 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1515 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1516 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1517 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1518 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1519 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1520 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001521
1522 // insert new blocks after the current block
1523 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1524 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1525 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001526 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001527 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1528 MachineFunction::iterator It = BB;
1529 ++It;
1530 MF->insert(It, loop1MBB);
1531 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001532 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001533 MF->insert(It, exitMBB);
1534
1535 // Transfer the remainder of BB and its successor edges to exitMBB.
1536 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001537 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001538 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1539
Akira Hatanaka81b44112011-07-19 17:09:53 +00001540 BB->addSuccessor(loop1MBB);
1541 loop1MBB->addSuccessor(sinkMBB);
1542 loop1MBB->addSuccessor(loop2MBB);
1543 loop2MBB->addSuccessor(loop1MBB);
1544 loop2MBB->addSuccessor(sinkMBB);
1545 sinkMBB->addSuccessor(exitMBB);
1546
Akira Hatanaka70564a92011-07-19 18:14:26 +00001547 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001548 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001549 // addiu masklsb2,$0,-4 # 0xfffffffc
1550 // and alignedaddr,ptr,masklsb2
1551 // andi ptrlsb2,ptr,3
1552 // sll shiftamt,ptrlsb2,3
1553 // ori maskupper,$0,255 # 0xff
1554 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001555 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001556 // andi maskedcmpval,cmpval,255
1557 // sll shiftedcmpval,maskedcmpval,shiftamt
1558 // andi maskednewval,newval,255
1559 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001560 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001561 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1562 .addReg(Mips::ZERO).addImm(-4);
1563 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1564 .addReg(Ptr).addReg(MaskLSB2);
1565 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1566 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1567 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1568 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001569 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1570 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001571 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001572 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1573 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001574 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1575 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001576 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1577 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001578 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1579 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001580
1581 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001582 // ll oldval,0(alginedaddr)
1583 // and maskedoldval0,oldval,mask
1584 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001585 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001586 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001587 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1588 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001589 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001590 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001591
1592 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001593 // and maskedoldval1,oldval,mask2
1594 // or storeval,maskedoldval1,shiftednewval
1595 // sc success,storeval,0(alignedaddr)
1596 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001597 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001598 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1599 .addReg(OldVal).addReg(Mask2);
1600 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1601 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001602 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001603 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001604 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001605 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001606
Akira Hatanaka939ece12011-07-19 03:42:13 +00001607 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001608 // srl srlres,maskedoldval0,shiftamt
1609 // sll sllres,srlres,24
1610 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001611 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001612 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001613
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001614 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1615 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001616 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1617 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001618 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001619 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001620
1621 MI->eraseFromParent(); // The instruction is gone now.
1622
Akira Hatanaka939ece12011-07-19 03:42:13 +00001623 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001624}
1625
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001626//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001627// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001628//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001629SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001630LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001631{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001632 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001633 // the block to branch to if the condition is true.
1634 SDValue Chain = Op.getOperand(0);
1635 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001636 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001637
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001638 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1639
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001640 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001641 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001642 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001643
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001644 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001645 Mips::CondCode CC =
1646 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001647 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001648
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001649 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001650 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001651}
1652
1653SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001654LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001655{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001656 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001657
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001658 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001659 if (Cond.getOpcode() != MipsISD::FPCmp)
1660 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001661
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001662 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1663 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001664}
1665
Akira Hatanaka3fef29d2012-07-11 19:32:27 +00001666SDValue MipsTargetLowering::
1667LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1668{
1669 DebugLoc DL = Op.getDebugLoc();
1670 EVT Ty = Op.getOperand(0).getValueType();
1671 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1672 Op.getOperand(0), Op.getOperand(1),
1673 Op.getOperand(4));
1674
1675 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1676 Op.getOperand(3));
1677}
1678
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001679SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1680 SDValue Cond = CreateFPCmp(DAG, Op);
1681
1682 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1683 "Floating point operand expected.");
1684
1685 SDValue True = DAG.getConstant(1, MVT::i32);
1686 SDValue False = DAG.getConstant(0, MVT::i32);
1687
1688 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1689}
1690
Dan Gohmand858e902010-04-17 15:26:15 +00001691SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1692 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001693 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001694 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001695 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001696
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001697 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001698 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001699
Akira Hatanakaafc945b2012-09-12 23:27:55 +00001700 const MipsTargetObjectFile &TLOF =
1701 (const MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001702
Chris Lattnere3736f82009-08-13 05:41:27 +00001703 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001704 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1705 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001706 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001707 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
Akira Hatanakae7338cd2012-08-22 03:18:13 +00001708 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1709 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001710 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001711 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001712 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1713 MipsII::MO_ABS_HI);
1714 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1715 MipsII::MO_ABS_LO);
1716 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1717 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001718 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001719 }
1720
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001721 EVT ValTy = Op.getValueType();
1722 bool HasGotOfst = (GV->hasInternalLinkage() ||
1723 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001724 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001725 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001726 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001727 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001728 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001729 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1730 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001731 // On functions and global targets not internal linked only
1732 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001733 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001734 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001735 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001736 HasMips64 ? MipsII::MO_GOT_OFST :
1737 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001738 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1739 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001740}
1741
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001742SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1743 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001744 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1745 // FIXME there isn't actually debug info here
1746 DebugLoc dl = Op.getDebugLoc();
1747
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001748 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001749 // %hi/%lo relocation
Reed Kotlerdfb8dbb2012-10-05 18:27:54 +00001750 SDValue BAHi =
1751 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI);
1752 SDValue BALo =
1753 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001754 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1755 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1756 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001757 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001758
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001759 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001760 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1761 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Michael Liao6c7ccaa2012-09-12 21:43:09 +00001762 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001763 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1764 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Michael Liao6c7ccaa2012-09-12 21:43:09 +00001765 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001766 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001767 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001768 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1769 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001770}
1771
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001772SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001773LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001774{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001775 // If the relocation model is PIC, use the General Dynamic TLS Model or
1776 // Local Dynamic TLS model, otherwise use the Initial Exec or
1777 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001778
1779 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1780 DebugLoc dl = GA->getDebugLoc();
1781 const GlobalValue *GV = GA->getGlobal();
1782 EVT PtrVT = getPointerTy();
1783
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001784 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1785
1786 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
Hans Wennborg70a07c72012-06-04 14:02:08 +00001787 // General Dynamic and Local Dynamic TLS Model.
1788 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1789 : MipsII::MO_TLSGD;
1790
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001791 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001792 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1793 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001794 unsigned PtrSize = PtrVT.getSizeInBits();
1795 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1796
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001797 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001798
1799 ArgListTy Args;
1800 ArgListEntry Entry;
1801 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001802 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001803 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001804
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001805 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001806 false, false, false, false, 0, CallingConv::C,
1807 /*isTailCall=*/false, /*doesNotRet=*/false,
1808 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001809 TlsGetAddr, Args, DAG, dl);
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00001810 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001811
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001812 SDValue Ret = CallResult.first;
1813
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001814 if (model != TLSModel::LocalDynamic)
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001815 return Ret;
1816
1817 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1818 MipsII::MO_DTPREL_HI);
1819 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1820 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1821 MipsII::MO_DTPREL_LO);
1822 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1823 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1824 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001825 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001826
1827 SDValue Offset;
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001828 if (model == TLSModel::InitialExec) {
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001829 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001830 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001831 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001832 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1833 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001834 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001835 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001836 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001837 } else {
1838 // Local Exec TLS Model
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001839 assert(model == TLSModel::LocalExec);
Akira Hatanakaca074792011-12-08 20:34:32 +00001840 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001841 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001842 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001843 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001844 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1845 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1846 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001847 }
1848
1849 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1850 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001851}
1852
1853SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001854LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001855{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001856 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001857 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001858 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001859 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001860 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001861 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001862
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001863 if (!IsPIC && !IsN64) {
1864 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1865 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1866 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001867 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001868 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1869 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001870 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001871 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1872 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001873 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1874 MachinePointerInfo(), false, false, false, 0);
1875 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001876 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001877
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001878 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1879 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001880}
1881
Dan Gohman475871a2008-07-27 21:46:04 +00001882SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001883LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001884{
Dan Gohman475871a2008-07-27 21:46:04 +00001885 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001886 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001887 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001888 // FIXME there isn't actually debug info here
1889 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001890
1891 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001892 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001893 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001894 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001895 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001896 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001897 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1898 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001899 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001900
Akira Hatanaka13daee32012-03-27 02:55:31 +00001901 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001902 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001903 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001904 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001905 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001906 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1907 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001908 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001909 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001910 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001911 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1912 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001913 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1914 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001915 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001916 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1917 MachinePointerInfo::getConstantPool(), false,
1918 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001919 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1920 N->getOffset(), OFSTFlag);
1921 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1922 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001923 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001924
1925 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001926}
1927
Dan Gohmand858e902010-04-17 15:26:15 +00001928SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001929 MachineFunction &MF = DAG.getMachineFunction();
1930 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1931
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001932 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001933 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1934 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001935
1936 // vastart just stores the address of the VarArgsFrameIndex slot into the
1937 // memory location argument.
1938 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001939 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001940 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001941}
Jia Liubb481f82012-02-28 07:46:26 +00001942
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001943static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1944 EVT TyX = Op.getOperand(0).getValueType();
1945 EVT TyY = Op.getOperand(1).getValueType();
1946 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1947 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1948 DebugLoc DL = Op.getDebugLoc();
1949 SDValue Res;
1950
1951 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1952 // to i32.
1953 SDValue X = (TyX == MVT::f32) ?
1954 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1955 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1956 Const1);
1957 SDValue Y = (TyY == MVT::f32) ?
1958 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1959 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1960 Const1);
1961
1962 if (HasR2) {
1963 // ext E, Y, 31, 1 ; extract bit31 of Y
1964 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1965 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1966 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1967 } else {
1968 // sll SllX, X, 1
1969 // srl SrlX, SllX, 1
1970 // srl SrlY, Y, 31
1971 // sll SllY, SrlX, 31
1972 // or Or, SrlX, SllY
1973 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1974 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1975 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1976 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1977 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1978 }
1979
1980 if (TyX == MVT::f32)
1981 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1982
1983 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1984 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1985 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001986}
1987
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001988static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1989 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1990 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1991 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1992 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1993 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001994
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001995 // Bitcast to integer nodes.
1996 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1997 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001998
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001999 if (HasR2) {
2000 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2001 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2002 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2003 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00002004
Akira Hatanaka056c51e2012-04-11 22:13:04 +00002005 if (WidthX > WidthY)
2006 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2007 else if (WidthY > WidthX)
2008 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00002009
Akira Hatanaka056c51e2012-04-11 22:13:04 +00002010 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2011 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2012 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2013 }
2014
2015 // (d)sll SllX, X, 1
2016 // (d)srl SrlX, SllX, 1
2017 // (d)srl SrlY, Y, width(Y)-1
2018 // (d)sll SllY, SrlX, width(Y)-1
2019 // or Or, SrlX, SllY
2020 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2021 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2022 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2023 DAG.getConstant(WidthY - 1, MVT::i32));
2024
2025 if (WidthX > WidthY)
2026 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2027 else if (WidthY > WidthX)
2028 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2029
2030 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2031 DAG.getConstant(WidthX - 1, MVT::i32));
2032 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2033 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00002034}
2035
Akira Hatanaka82099682011-12-19 19:52:25 +00002036SDValue
2037MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00002038 if (Subtarget->hasMips64())
2039 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00002040
Akira Hatanaka056c51e2012-04-11 22:13:04 +00002041 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00002042}
2043
Akira Hatanakac12a6e62012-04-11 22:49:04 +00002044static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2045 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2046 DebugLoc DL = Op.getDebugLoc();
2047
2048 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2049 // to i32.
2050 SDValue X = (Op.getValueType() == MVT::f32) ?
2051 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2052 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2053 Const1);
2054
2055 // Clear MSB.
2056 if (HasR2)
2057 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2058 DAG.getRegister(Mips::ZERO, MVT::i32),
2059 DAG.getConstant(31, MVT::i32), Const1, X);
2060 else {
2061 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2062 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2063 }
2064
2065 if (Op.getValueType() == MVT::f32)
2066 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2067
2068 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2069 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2070 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2071}
2072
2073static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2074 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2075 DebugLoc DL = Op.getDebugLoc();
2076
2077 // Bitcast to integer node.
2078 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2079
2080 // Clear MSB.
2081 if (HasR2)
2082 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2083 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2084 DAG.getConstant(63, MVT::i32), Const1, X);
2085 else {
2086 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2087 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2088 }
2089
2090 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2091}
2092
2093SDValue
2094MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2095 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2096 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2097
2098 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2099}
2100
Akira Hatanaka2e591472011-06-02 00:24:44 +00002101SDValue MipsTargetLowering::
2102LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00002103 // check the depth
2104 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00002105 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00002106
2107 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2108 MFI->setFrameAddressIsTaken(true);
2109 EVT VT = Op.getValueType();
2110 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00002111 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2112 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00002113 return FrameAddr;
2114}
2115
Akira Hatanakaba584fe2012-07-11 00:53:32 +00002116SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2117 SelectionDAG &DAG) const {
2118 // check the depth
2119 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2120 "Return address can be determined only for current frame.");
2121
2122 MachineFunction &MF = DAG.getMachineFunction();
2123 MachineFrameInfo *MFI = MF.getFrameInfo();
2124 EVT VT = Op.getValueType();
2125 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2126 MFI->setReturnAddressIsTaken(true);
2127
2128 // Return RA, which contains the return address. Mark it an implicit live-in.
2129 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2130 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2131}
2132
Akira Hatanakadb548262011-07-19 23:30:50 +00002133// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00002134SDValue
Akira Hatanaka864f6602012-06-14 21:10:56 +00002135MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00002136 unsigned SType = 0;
2137 DebugLoc dl = Op.getDebugLoc();
2138 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2139 DAG.getConstant(SType, MVT::i32));
2140}
2141
Eli Friedman14648462011-07-27 22:21:52 +00002142SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002143 SelectionDAG &DAG) const {
Eli Friedman14648462011-07-27 22:21:52 +00002144 // FIXME: Need pseudo-fence for 'singlethread' fences
2145 // FIXME: Set SType for weaker fences where supported/appropriate.
2146 unsigned SType = 0;
2147 DebugLoc dl = Op.getDebugLoc();
2148 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2149 DAG.getConstant(SType, MVT::i32));
2150}
2151
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002152SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002153 SelectionDAG &DAG) const {
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002154 DebugLoc DL = Op.getDebugLoc();
2155 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2156 SDValue Shamt = Op.getOperand(2);
2157
2158 // if shamt < 32:
2159 // lo = (shl lo, shamt)
2160 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2161 // else:
2162 // lo = 0
2163 // hi = (shl lo, shamt[4:0])
2164 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2165 DAG.getConstant(-1, MVT::i32));
2166 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2167 DAG.getConstant(1, MVT::i32));
2168 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2169 Not);
2170 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2171 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2172 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2173 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2174 DAG.getConstant(0x20, MVT::i32));
Akira Hatanaka864f6602012-06-14 21:10:56 +00002175 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2176 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002177 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2178
2179 SDValue Ops[2] = {Lo, Hi};
2180 return DAG.getMergeValues(Ops, 2, DL);
2181}
2182
Akira Hatanaka864f6602012-06-14 21:10:56 +00002183SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
Akira Hatanakaa284acb2012-05-09 00:55:21 +00002184 bool IsSRA) const {
2185 DebugLoc DL = Op.getDebugLoc();
2186 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2187 SDValue Shamt = Op.getOperand(2);
2188
2189 // if shamt < 32:
2190 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2191 // if isSRA:
2192 // hi = (sra hi, shamt)
2193 // else:
2194 // hi = (srl hi, shamt)
2195 // else:
2196 // if isSRA:
2197 // lo = (sra hi, shamt[4:0])
2198 // hi = (sra hi, 31)
2199 // else:
2200 // lo = (srl hi, shamt[4:0])
2201 // hi = 0
2202 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2203 DAG.getConstant(-1, MVT::i32));
2204 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2205 DAG.getConstant(1, MVT::i32));
2206 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2207 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2208 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2209 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2210 Hi, Shamt);
2211 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2212 DAG.getConstant(0x20, MVT::i32));
2213 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2214 DAG.getConstant(31, MVT::i32));
2215 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2216 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2217 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2218 ShiftRightHi);
2219
2220 SDValue Ops[2] = {Lo, Hi};
2221 return DAG.getMergeValues(Ops, 2, DL);
2222}
2223
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002224static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2225 SDValue Chain, SDValue Src, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002226 SDValue Ptr = LD->getBasePtr();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002227 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002228 EVT BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002229 DebugLoc DL = LD->getDebugLoc();
2230 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2231
2232 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002233 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002234 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002235
2236 SDValue Ops[] = { Chain, Ptr, Src };
2237 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2238 LD->getMemOperand());
2239}
2240
2241// Expand an unaligned 32 or 64-bit integer load node.
2242SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2243 LoadSDNode *LD = cast<LoadSDNode>(Op);
2244 EVT MemVT = LD->getMemoryVT();
2245
2246 // Return if load is aligned or if MemVT is neither i32 nor i64.
2247 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2248 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2249 return SDValue();
2250
2251 bool IsLittle = Subtarget->isLittle();
2252 EVT VT = Op.getValueType();
2253 ISD::LoadExtType ExtType = LD->getExtensionType();
2254 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2255
2256 assert((VT == MVT::i32) || (VT == MVT::i64));
2257
2258 // Expand
2259 // (set dst, (i64 (load baseptr)))
2260 // to
2261 // (set tmp, (ldl (add baseptr, 7), undef))
2262 // (set dst, (ldr baseptr, tmp))
2263 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2264 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2265 IsLittle ? 7 : 0);
2266 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2267 IsLittle ? 0 : 7);
2268 }
2269
2270 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2271 IsLittle ? 3 : 0);
2272 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2273 IsLittle ? 0 : 3);
2274
2275 // Expand
2276 // (set dst, (i32 (load baseptr))) or
2277 // (set dst, (i64 (sextload baseptr))) or
2278 // (set dst, (i64 (extload baseptr)))
2279 // to
2280 // (set tmp, (lwl (add baseptr, 3), undef))
2281 // (set dst, (lwr baseptr, tmp))
2282 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2283 (ExtType == ISD::EXTLOAD))
2284 return LWR;
2285
2286 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2287
2288 // Expand
2289 // (set dst, (i64 (zextload baseptr)))
2290 // to
2291 // (set tmp0, (lwl (add baseptr, 3), undef))
2292 // (set tmp1, (lwr baseptr, tmp0))
2293 // (set tmp2, (shl tmp1, 32))
2294 // (set dst, (srl tmp2, 32))
2295 DebugLoc DL = LD->getDebugLoc();
2296 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2297 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
Akira Hatanaka94ccee22012-06-04 17:46:29 +00002298 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2299 SDValue Ops[] = { SRL, LWR.getValue(1) };
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002300 return DAG.getMergeValues(Ops, 2, DL);
2301}
2302
2303static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2304 SDValue Chain, unsigned Offset) {
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002305 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2306 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002307 DebugLoc DL = SD->getDebugLoc();
2308 SDVTList VTList = DAG.getVTList(MVT::Other);
2309
2310 if (Offset)
Akira Hatanaka2bd7e532012-06-13 19:06:08 +00002311 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002312 DAG.getConstant(Offset, BasePtrVT));
Akira Hatanaka1cd0ec02012-06-02 00:03:49 +00002313
2314 SDValue Ops[] = { Chain, Value, Ptr };
2315 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2316 SD->getMemOperand());
2317}
2318
2319// Expand an unaligned 32 or 64-bit integer store node.
2320SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2321 StoreSDNode *SD = cast<StoreSDNode>(Op);
2322 EVT MemVT = SD->getMemoryVT();
2323
2324 // Return if store is aligned or if MemVT is neither i32 nor i64.
2325 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2326 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2327 return SDValue();
2328
2329 bool IsLittle = Subtarget->isLittle();
2330 SDValue Value = SD->getValue(), Chain = SD->getChain();
2331 EVT VT = Value.getValueType();
2332
2333 // Expand
2334 // (store val, baseptr) or
2335 // (truncstore val, baseptr)
2336 // to
2337 // (swl val, (add baseptr, 3))
2338 // (swr val, baseptr)
2339 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2340 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2341 IsLittle ? 3 : 0);
2342 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2343 }
2344
2345 assert(VT == MVT::i64);
2346
2347 // Expand
2348 // (store val, baseptr)
2349 // to
2350 // (sdl val, (add baseptr, 7))
2351 // (sdr val, baseptr)
2352 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2353 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2354}
2355
Akira Hatanakafd89e6f2012-09-27 02:05:42 +00002356// This function expands mips intrinsic nodes which have 64-bit input operands
2357// or output values.
2358//
2359// out64 = intrinsic-node in64
2360// =>
2361// lo = copy (extract-element (in64, 0))
2362// hi = copy (extract-element (in64, 1))
2363// mips-specific-node
2364// v0 = copy lo
2365// v1 = copy hi
2366// out64 = merge-values (v0, v1)
2367//
2368static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2369 unsigned Opc, bool HasI64In, bool HasI64Out) {
2370 DebugLoc DL = Op.getDebugLoc();
2371 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2372 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2373 SmallVector<SDValue, 3> Ops;
2374
2375 if (HasI64In) {
2376 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2377 Op->getOperand(1 + HasChainIn),
2378 DAG.getConstant(0, MVT::i32));
2379 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2380 Op->getOperand(1 + HasChainIn),
2381 DAG.getConstant(1, MVT::i32));
2382
2383 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2384 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2385
2386 Ops.push_back(Chain);
2387 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2388 Ops.push_back(Chain.getValue(1));
2389 } else {
2390 Ops.push_back(Chain);
2391 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2392 }
2393
2394 if (!HasI64Out)
2395 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2396 Ops.begin(), Ops.size());
2397
2398 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2399 Ops.begin(), Ops.size());
2400 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2401 Intr.getValue(1));
2402 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2403 OutLo.getValue(2));
2404 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2405
2406 if (!HasChainIn)
2407 return Out;
2408
2409 SDValue Vals[] = { Out, OutHi.getValue(1) };
2410 return DAG.getMergeValues(Vals, 2, DL);
2411}
2412
2413SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2414 SelectionDAG &DAG) const {
2415 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2416 default:
2417 return SDValue();
Akira Hatanaka2df483e2012-09-27 02:11:20 +00002418 case Intrinsic::mips_shilo:
2419 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2420 case Intrinsic::mips_dpau_h_qbl:
2421 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2422 case Intrinsic::mips_dpau_h_qbr:
2423 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2424 case Intrinsic::mips_dpsu_h_qbl:
2425 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2426 case Intrinsic::mips_dpsu_h_qbr:
2427 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2428 case Intrinsic::mips_dpa_w_ph:
2429 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2430 case Intrinsic::mips_dps_w_ph:
2431 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2432 case Intrinsic::mips_dpax_w_ph:
2433 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2434 case Intrinsic::mips_dpsx_w_ph:
2435 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2436 case Intrinsic::mips_mulsa_w_ph:
2437 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2438 case Intrinsic::mips_mult:
2439 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2440 case Intrinsic::mips_multu:
2441 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2442 case Intrinsic::mips_madd:
2443 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2444 case Intrinsic::mips_maddu:
2445 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2446 case Intrinsic::mips_msub:
2447 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2448 case Intrinsic::mips_msubu:
2449 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
Akira Hatanakafd89e6f2012-09-27 02:05:42 +00002450 }
2451}
2452
2453SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2454 SelectionDAG &DAG) const {
2455 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2456 default:
2457 return SDValue();
2458 case Intrinsic::mips_extp:
2459 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2460 case Intrinsic::mips_extpdp:
2461 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2462 case Intrinsic::mips_extr_w:
2463 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2464 case Intrinsic::mips_extr_r_w:
2465 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2466 case Intrinsic::mips_extr_rs_w:
2467 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2468 case Intrinsic::mips_extr_s_h:
2469 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
Akira Hatanaka2df483e2012-09-27 02:11:20 +00002470 case Intrinsic::mips_mthlip:
2471 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2472 case Intrinsic::mips_mulsaq_s_w_ph:
2473 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2474 case Intrinsic::mips_maq_s_w_phl:
2475 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2476 case Intrinsic::mips_maq_s_w_phr:
2477 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2478 case Intrinsic::mips_maq_sa_w_phl:
2479 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2480 case Intrinsic::mips_maq_sa_w_phr:
2481 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2482 case Intrinsic::mips_dpaq_s_w_ph:
2483 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2484 case Intrinsic::mips_dpsq_s_w_ph:
2485 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2486 case Intrinsic::mips_dpaq_sa_l_w:
2487 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2488 case Intrinsic::mips_dpsq_sa_l_w:
2489 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2490 case Intrinsic::mips_dpaqx_s_w_ph:
2491 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2492 case Intrinsic::mips_dpaqx_sa_w_ph:
2493 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2494 case Intrinsic::mips_dpsqx_s_w_ph:
2495 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2496 case Intrinsic::mips_dpsqx_sa_w_ph:
2497 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
Akira Hatanakafd89e6f2012-09-27 02:05:42 +00002498 }
2499}
2500
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002501//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002502// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002503//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002504
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002505//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002506// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002507// Mips O32 ABI rules:
2508// ---
2509// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002510// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002511// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002512// f64 - Only passed in two aliased f32 registers if no int reg has been used
2513// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002514// not used, it must be shadowed. If only A3 is avaiable, shadow it and
2515// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002516//
2517// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002518//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002519
Duncan Sands1e96bab2010-11-04 10:49:57 +00002520static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00002521 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002522 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2523
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002524 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002525
Craig Topperc5eaae42012-03-11 07:57:25 +00002526 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002527 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2528 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002529 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002530 Mips::F12, Mips::F14
2531 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002532 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002533 Mips::D6, Mips::D7
2534 };
2535
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002536 // ByVal Args
2537 if (ArgFlags.isByVal()) {
2538 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2539 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2540 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2541 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2542 r < std::min(IntRegsSize, NextReg); ++r)
2543 State.AllocateReg(IntRegs[r]);
2544 return false;
2545 }
2546
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002547 // Promote i8 and i16
2548 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2549 LocVT = MVT::i32;
2550 if (ArgFlags.isSExt())
2551 LocInfo = CCValAssign::SExt;
2552 else if (ArgFlags.isZExt())
2553 LocInfo = CCValAssign::ZExt;
2554 else
2555 LocInfo = CCValAssign::AExt;
2556 }
2557
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002558 unsigned Reg;
2559
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002560 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2561 // is true: function is vararg, argument is 3rd or higher, there is previous
2562 // argument which is not f32 or f64.
2563 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2564 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002565 unsigned OrigAlign = ArgFlags.getOrigAlign();
2566 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002567
2568 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002569 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002570 // If this is the first part of an i64 arg,
2571 // the allocated register must be either A0 or A2.
2572 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2573 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002574 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002575 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2576 // Allocate int register and shadow next int register. If first
2577 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002578 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2579 if (Reg == Mips::A1 || Reg == Mips::A3)
2580 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2581 State.AllocateReg(IntRegs, IntRegsSize);
2582 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002583 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2584 // we are guaranteed to find an available float register
2585 if (ValVT == MVT::f32) {
2586 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2587 // Shadow int register
2588 State.AllocateReg(IntRegs, IntRegsSize);
2589 } else {
2590 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2591 // Shadow int registers
2592 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2593 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2594 State.AllocateReg(IntRegs, IntRegsSize);
2595 State.AllocateReg(IntRegs, IntRegsSize);
2596 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002597 } else
2598 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002599
Akira Hatanakad37776d2011-05-20 21:39:54 +00002600 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
Akira Hatanaka97d9f082012-10-10 01:27:09 +00002601 unsigned Offset;
2602 if (!ArgFlags.isSRet())
2603 Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2604 else
2605 Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
Akira Hatanakad37776d2011-05-20 21:39:54 +00002606
2607 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002608 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002609 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002610 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002611
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002612 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002613}
2614
Craig Topperc5eaae42012-03-11 07:57:25 +00002615static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002616 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2617 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002618static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002619 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2620 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2621
2622static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2623 CCValAssign::LocInfo LocInfo,
2624 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2625 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2626 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2627 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2628
2629 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2630
Jia Liubb481f82012-02-28 07:46:26 +00002631 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002632 if ((Align == 16) && (FirstIdx % 2)) {
2633 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2634 ++FirstIdx;
2635 }
2636
2637 // Mark the registers allocated.
2638 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2639 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2640
2641 // Allocate space on caller's stack.
2642 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002643
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002644 if (FirstIdx < 8)
2645 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002646 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002647 else
2648 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2649
2650 return true;
2651}
2652
2653#include "MipsGenCallingConv.inc"
2654
Akira Hatanaka49617092011-11-14 19:02:54 +00002655static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002656AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002657 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2658 unsigned NumOps = Outs.size();
2659 for (unsigned i = 0; i != NumOps; ++i) {
2660 MVT ArgVT = Outs[i].VT;
2661 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2662 bool R;
2663
2664 if (Outs[i].IsFixed)
2665 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2666 else
2667 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002668
Akira Hatanaka49617092011-11-14 19:02:54 +00002669 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002670#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002671 dbgs() << "Call operand #" << i << " has unhandled type "
2672 << EVT(ArgVT).getEVTString();
2673#endif
2674 llvm_unreachable(0);
2675 }
2676 }
2677}
2678
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002679//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002680// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002681//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002682
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002683static const unsigned O32IntRegsSize = 4;
2684
Craig Topperc5eaae42012-03-11 07:57:25 +00002685static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002686 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2687};
2688
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002689// Return next O32 integer argument register.
2690static unsigned getNextIntArgReg(unsigned Reg) {
2691 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2692 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2693}
2694
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002695// Write ByVal Arg to arg registers and stack.
2696static void
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002697WriteByValArg(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002698 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002699 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002700 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002701 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002702 MVT PtrType, bool isLittle) {
2703 unsigned LocMemOffset = VA.getLocMemOffset();
2704 unsigned Offset = 0;
2705 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002706 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002707
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002708 // Copy the first 4 words of byval arg to registers A0 - A3.
2709 // FIXME: Use a stricter alignment if it enables better optimization in passes
2710 // run later.
2711 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2712 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002713 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002714 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002715 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002716 MachinePointerInfo(), false, false, false,
2717 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002718 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002719 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002720 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2721 }
2722
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002723 if (RemainingSize == 0)
2724 return;
2725
2726 // If there still is a register available for argument passing, write the
2727 // remaining part of the structure to it using subword loads and shifts.
2728 if (LocMemOffset < 4 * 4) {
2729 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2730 "There must be one to three bytes remaining.");
2731 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2732 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2733 DAG.getConstant(Offset, MVT::i32));
2734 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2735 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2736 LoadPtr, MachinePointerInfo(),
2737 MVT::getIntegerVT(LoadSize * 8), false,
2738 false, Alignment);
2739 MemOpChains.push_back(LoadVal.getValue(1));
2740
2741 // If target is big endian, shift it to the most significant half-word or
2742 // byte.
2743 if (!isLittle)
2744 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2745 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2746
2747 Offset += LoadSize;
2748 RemainingSize -= LoadSize;
2749
2750 // Read second subword if necessary.
2751 if (RemainingSize != 0) {
2752 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002753 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002754 DAG.getConstant(Offset, MVT::i32));
2755 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2756 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2757 LoadPtr, MachinePointerInfo(),
2758 MVT::i8, false, false, Alignment);
2759 MemOpChains.push_back(Subword.getValue(1));
2760 // Insert the loaded byte to LoadVal.
2761 // FIXME: Use INS if supported by target.
2762 unsigned ShiftAmt = isLittle ? 16 : 8;
2763 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2764 DAG.getConstant(ShiftAmt, MVT::i32));
2765 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2766 }
2767
2768 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2769 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2770 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002771 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002772
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002773 // Copy remaining part of byval arg using memcpy.
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002774 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2775 DAG.getConstant(Offset, MVT::i32));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002776 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr,
2777 DAG.getIntPtrConstant(LocMemOffset));
2778 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2779 DAG.getConstant(RemainingSize, MVT::i32),
2780 std::min(ByValAlign, (unsigned)4),
2781 /*isVolatile=*/false, /*AlwaysInline=*/false,
2782 MachinePointerInfo(0), MachinePointerInfo(0));
2783 MemOpChains.push_back(Chain);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002784}
2785
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002786// Copy Mips64 byVal arg to registers and stack.
2787void static
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002788PassByValArg64(SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002789 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002790 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002791 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanaka864f6602012-06-14 21:10:56 +00002792 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002793 EVT PtrTy, bool isLittle) {
2794 unsigned ByValSize = Flags.getByValSize();
2795 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2796 bool IsRegLoc = VA.isRegLoc();
2797 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2798 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002799 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002800
2801 if (!IsRegLoc)
2802 LocMemOffset = VA.getLocMemOffset();
2803 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002804 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002805 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002806 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002807
2808 // Copy double words to registers.
2809 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2810 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2811 DAG.getConstant(Offset, PtrTy));
2812 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2813 MachinePointerInfo(), false, false, false,
2814 Alignment);
2815 MemOpChains.push_back(LoadVal.getValue(1));
2816 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2817 }
2818
Jia Liubb481f82012-02-28 07:46:26 +00002819 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002820 if (!(MemCpySize = ByValSize - Offset))
2821 return;
2822
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002823 // If there is an argument register available, copy the remainder of the
2824 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002825 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002826 assert((ByValSize < Offset + 8) &&
2827 "Size of the remainder should be smaller than 8-byte.");
2828 SDValue Val;
2829 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2830 unsigned RemSize = ByValSize - Offset;
2831
2832 if (RemSize < LoadSize)
2833 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002834
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002835 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2836 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002837 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002838 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2839 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2840 false, false, Alignment);
2841 MemOpChains.push_back(LoadVal.getValue(1));
2842
2843 // Offset in number of bits from double word boundary.
2844 unsigned OffsetDW = (Offset % 8) * 8;
2845 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2846 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2847 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002848
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002849 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2850 Shift;
2851 Offset += LoadSize;
2852 Alignment = std::min(Alignment, LoadSize);
2853 }
Jia Liubb481f82012-02-28 07:46:26 +00002854
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002855 RegsToPass.push_back(std::make_pair(*Reg, Val));
2856 return;
2857 }
2858 }
2859
Akira Hatanaka16040852011-11-15 18:42:25 +00002860 assert(MemCpySize && "MemCpySize must not be zero.");
2861
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002862 // Copy remainder of byval arg to it with memcpy.
Akira Hatanaka16040852011-11-15 18:42:25 +00002863 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2864 DAG.getConstant(Offset, PtrTy));
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002865 SDValue Dst = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr,
2866 DAG.getIntPtrConstant(LocMemOffset));
2867 Chain = DAG.getMemcpy(Chain, dl, Dst, Src,
2868 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2869 /*isVolatile=*/false, /*AlwaysInline=*/false,
2870 MachinePointerInfo(0), MachinePointerInfo(0));
2871 MemOpChains.push_back(Chain);
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002872}
2873
Dan Gohman98ca4f22009-08-05 01:29:28 +00002874/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002875/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002876/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002877SDValue
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002878MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohmand858e902010-04-17 15:26:15 +00002879 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002880 SelectionDAG &DAG = CLI.DAG;
2881 DebugLoc &dl = CLI.DL;
2882 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2883 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2884 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002885 SDValue Chain = CLI.Chain;
Justin Holewinskid2ea0e12012-05-25 16:35:28 +00002886 SDValue Callee = CLI.Callee;
2887 bool &isTailCall = CLI.IsTailCall;
2888 CallingConv::ID CallConv = CLI.CallConv;
2889 bool isVarArg = CLI.IsVarArg;
2890
Evan Cheng0c439eb2010-01-27 00:07:07 +00002891 // MIPs target does not yet support tail call optimization.
2892 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002893
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002894 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002895 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002896 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002897 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002898 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002899
2900 // Analyze operands of the call, assigning locations to each operand.
2901 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002902 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002903 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002904
Akira Hatanaka777a1202012-06-13 18:06:00 +00002905 if (CallConv == CallingConv::Fast)
2906 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC);
2907 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002908 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002909 else if (HasMips64)
2910 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002911 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002912 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002913
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002914 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002915 unsigned NextStackOffset = CCInfo.getNextStackOffset();
Akira Hatanaka480eeb52012-07-26 23:27:01 +00002916 unsigned StackAlignment = TFL->getStackAlignment();
2917 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2918
2919 // Update size of the maximum argument space.
2920 // For O32, a minimum of four words (16 bytes) of argument space is
2921 // allocated.
2922 if (IsO32 && (CallConv != CallingConv::Fast))
2923 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002924
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002925 // Chain is the output chain of the last Load/Store or CopyToReg node.
2926 // ByValChain is the output chain of the last Memcpy node created for copying
2927 // byval arguments to the stack.
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002928 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002929 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2930
2931 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2932 IsN64 ? Mips::SP_64 : Mips::SP,
2933 getPointerTy());
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002934
Akira Hatanaka1d165f12012-07-31 20:54:48 +00002935 if (MipsFI->getMaxCallFrameSize() < NextStackOffset)
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002936 MipsFI->setMaxCallFrameSize(NextStackOffset);
2937
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002938 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002939 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2940 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002941
2942 // Walk the register/memloc assignments, inserting copies/loads.
2943 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002944 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002945 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002946 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002947 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2948
2949 // ByVal Arg.
2950 if (Flags.isByVal()) {
2951 assert(Flags.getByValSize() &&
2952 "ByVal args of size 0 should have been ignored by front-end.");
2953 if (IsO32)
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002954 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002955 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2956 Subtarget->isLittle());
2957 else
Akira Hatanakae2d529a2012-07-31 18:46:41 +00002958 PassByValArg64(Chain, dl, RegsToPass, MemOpChains, StackPtr,
Jia Liubb481f82012-02-28 07:46:26 +00002959 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002960 Subtarget->isLittle());
2961 continue;
2962 }
Jia Liubb481f82012-02-28 07:46:26 +00002963
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002964 // Promote the value if needed.
2965 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002966 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002967 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002968 if (VA.isRegLoc()) {
2969 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2970 (ValVT == MVT::f64 && LocVT == MVT::i64))
2971 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2972 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002973 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2974 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002975 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2976 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002977 if (!Subtarget->isLittle())
2978 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002979 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002980 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2981 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2982 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002983 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002984 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002985 }
2986 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002987 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002988 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002989 break;
2990 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002991 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002992 break;
2993 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002994 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002995 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002996 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002997
2998 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002999 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003000 if (VA.isRegLoc()) {
3001 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00003002 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003003 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003004
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003005 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00003006 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003007
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003008 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00003009 // parameter value to a stack Location
Akira Hatanakae2d529a2012-07-31 18:46:41 +00003010 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
3011 DAG.getIntPtrConstant(VA.getLocMemOffset()));
Chris Lattner8026a9d2010-09-21 17:50:43 +00003012 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00003013 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003014 }
3015
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003016 // Transform all store nodes into one single node because all store
3017 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003018 if (!MemOpChains.empty())
3019 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003020 &MemOpChains[0], MemOpChains.size());
3021
Bill Wendling056292f2008-09-16 21:48:12 +00003022 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003023 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3024 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003025 unsigned char OpFlag;
3026 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003027 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003028 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003029
3030 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003031 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
3032 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
3033 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
3034 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
3035 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003036 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003037 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003038 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003039 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003040 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3041 getPointerTy(), 0, OpFlag);
3042 }
3043
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003044 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003045 }
3046 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003047 if (IsN64 || (!IsO32 && IsPIC))
3048 OpFlag = MipsII::MO_GOT_DISP;
3049 else if (!IsPIC) // !N64 && static
3050 OpFlag = MipsII::MO_NO_FLAG;
3051 else // O32 & PIC
3052 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00003053 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3054 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003055 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003056 }
3057
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00003058 SDValue InFlag;
3059
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003060 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003061 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003062 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003063 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00003064 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
3065 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003066 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
3067 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00003068 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003069
3070 // Use GOT+LO if callee has internal linkage.
3071 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003072 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
3073 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00003074 } else
3075 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003076 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003077 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003078
Akira Hatanakae11246c2012-07-26 02:24:43 +00003079 // T9 register operand.
3080 SDValue T9;
3081
Jia Liubb481f82012-02-28 07:46:26 +00003082 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00003083 // -reloction-model=pic or it is an indirect call.
3084 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003085 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00003086 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
3087 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003088 InFlag = Chain.getValue(1);
Akira Hatanakae11246c2012-07-26 02:24:43 +00003089
3090 if (Subtarget->inMips16Mode())
3091 T9 = DAG.getRegister(T9Reg, getPointerTy());
3092 else
3093 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00003094 }
Bill Wendling056292f2008-09-16 21:48:12 +00003095
Akira Hatanaka92d4aec2012-05-12 03:19:04 +00003096 // Insert node "GP copy globalreg" before call to function.
3097 // Lazy-binding stubs require GP to point to the GOT.
3098 if (IsPICCall) {
3099 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
3100 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
3101 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
3102 }
3103
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00003104 // Build a sequence of copy-to-reg nodes chained together with token
3105 // chain and flag operands which copy the outgoing args into registers.
3106 // The InFlag in necessary since all emitted instructions must be
3107 // stuck together.
3108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3109 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3110 RegsToPass[i].second, InFlag);
3111 InFlag = Chain.getValue(1);
3112 }
3113
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003114 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003115 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003116 //
3117 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00003118 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00003119 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003120 Ops.push_back(Chain);
Akira Hatanakae11246c2012-07-26 02:24:43 +00003121 Ops.push_back(Callee);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003122
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003123 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003124 // known live into the call.
3125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3126 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3127 RegsToPass[i].second.getValueType()));
3128
Akira Hatanakae11246c2012-07-26 02:24:43 +00003129 // Add T9 register operand.
3130 if (T9.getNode())
3131 Ops.push_back(T9);
3132
Akira Hatanakab2930b92012-03-01 22:27:29 +00003133 // Add a register mask operand representing the call-preserved registers.
3134 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3135 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3136 assert(Mask && "Missing call preserved mask for calling convention");
3137 Ops.push_back(DAG.getRegisterMask(Mask));
3138
Gabor Greifba36cb52008-08-28 21:40:38 +00003139 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003140 Ops.push_back(InFlag);
3141
Dale Johannesen33c960f2009-02-04 20:06:27 +00003142 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003143 InFlag = Chain.getValue(1);
3144
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00003145 // Create the CALLSEQ_END node.
Akira Hatanaka480eeb52012-07-26 23:27:01 +00003146 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00003147 DAG.getIntPtrConstant(0, true), InFlag);
3148 InFlag = Chain.getValue(1);
3149
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003150 // Handle result values, copying them out of physregs into vregs that we
3151 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00003152 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3153 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003154}
3155
Dan Gohman98ca4f22009-08-05 01:29:28 +00003156/// LowerCallResult - Lower the result values of a call into the
3157/// appropriate copies out of appropriate physical registers.
3158SDValue
3159MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00003160 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00003161 const SmallVectorImpl<ISD::InputArg> &Ins,
3162 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00003163 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003164 // Assign locations to each value returned by this call.
3165 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00003166 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00003167 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003168
Dan Gohman98ca4f22009-08-05 01:29:28 +00003169 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003170
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003171 // Copy all of the result registers out of their specified physreg.
3172 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00003173 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00003174 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003175 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00003176 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003177 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00003178
Dan Gohman98ca4f22009-08-05 01:29:28 +00003179 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003180}
3181
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003182//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00003183// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003184//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00003185static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00003186 std::vector<SDValue> &OutChains,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00003187 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanaka864f6602012-06-14 21:10:56 +00003188 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanakab4549e12012-03-27 03:13:56 +00003189 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00003190 unsigned LocMem = VA.getLocMemOffset();
3191 unsigned FirstWord = LocMem / 4;
3192
3193 // copy register A0 - A3 to frame object
3194 for (unsigned i = 0; i < NumWords; ++i) {
3195 unsigned CurWord = FirstWord + i;
3196 if (CurWord >= O32IntRegsSize)
3197 break;
3198
3199 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00003200 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00003201 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
3202 DAG.getConstant(i * 4, MVT::i32));
3203 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00003204 StorePtr, MachinePointerInfo(FuncArg, i * 4),
3205 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00003206 OutChains.push_back(Store);
3207 }
3208}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003209
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003210// Create frame object on stack and copy registers used for byval passing to it.
3211static unsigned
3212CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
Akira Hatanaka864f6602012-06-14 21:10:56 +00003213 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3214 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003215 MachineFrameInfo *MFI, bool IsRegLoc,
3216 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00003217 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00003218 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003219 int FOOffset; // Frame object offset from virtual frame pointer.
3220
3221 if (IsRegLoc) {
3222 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
3223 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003224 }
3225 else
3226 FOOffset = VA.getLocMemOffset();
3227
3228 // Create frame object.
3229 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
3230 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
3231 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
3232 InVals.push_back(FIN);
3233
3234 // Copy arg registers.
3235 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
3236 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00003237 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003238 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
3239 DAG.getConstant(I * 8, PtrTy));
3240 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00003241 StorePtr, MachinePointerInfo(FuncArg, I * 8),
3242 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003243 OutChains.push_back(Store);
3244 }
Jia Liubb481f82012-02-28 07:46:26 +00003245
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003246 return LastFI;
3247}
3248
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003249/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003250/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00003251SDValue
3252MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00003253 CallingConv::ID CallConv,
3254 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00003255 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00003256 DebugLoc dl, SelectionDAG &DAG,
3257 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003258 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00003259 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003260 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00003261 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003262
Dan Gohman1e93df62010-04-17 14:41:14 +00003263 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003264
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003265 // Used with vargs to acumulate store chains.
3266 std::vector<SDValue> OutChains;
3267
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003268 // Assign locations to all of the incoming arguments.
3269 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00003270 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00003271 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003272
Akira Hatanaka777a1202012-06-13 18:06:00 +00003273 if (CallConv == CallingConv::Fast)
3274 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FastCC);
3275 else if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00003276 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003277 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00003278 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003279
Akira Hatanakab4549e12012-03-27 03:13:56 +00003280 Function::const_arg_iterator FuncArg =
3281 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00003282 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003283
Akira Hatanakab4549e12012-03-27 03:13:56 +00003284 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003285 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003286 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003287 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3288 bool IsRegLoc = VA.isRegLoc();
3289
3290 if (Flags.isByVal()) {
3291 assert(Flags.getByValSize() &&
3292 "ByVal args of size 0 should have been ignored by front-end.");
3293 if (IsO32) {
3294 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
3295 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
3296 true);
3297 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
3298 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00003299 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
3300 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003301 } else // N32/64
3302 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
3303 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00003304 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003305 continue;
3306 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003307
3308 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00003309 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00003310 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003311 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00003312 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003313
Owen Anderson825b72b2009-08-11 20:47:22 +00003314 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00003315 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00003316 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00003317 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003318 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003319 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003320 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00003321 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00003322 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003323 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003324
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003325 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003326 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003327 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00003328 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003329
3330 // If this is an 8 or 16-bit value, it has been passed promoted
3331 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003332 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003333 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00003334 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003335 if (VA.getLocInfo() == CCValAssign::SExt)
3336 Opcode = ISD::AssertSext;
3337 else if (VA.getLocInfo() == CCValAssign::ZExt)
3338 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00003339 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003340 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003341 DAG.getValueType(ValVT));
3342 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003343 }
3344
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003345 // Handle floating point arguments passed in integer registers.
3346 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3347 (RegVT == MVT::i64 && ValVT == MVT::f64))
3348 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3349 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3350 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3351 getNextIntArgReg(ArgReg), RC);
3352 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3353 if (!Subtarget->isLittle())
3354 std::swap(ArgValue, ArgValue2);
3355 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3356 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00003357 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003358
Dan Gohman98ca4f22009-08-05 01:29:28 +00003359 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003360 } else { // VA.isRegLoc()
3361
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003362 // sanity check
3363 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003364
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003365 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003366 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003367 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003368
3369 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00003370 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00003371 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00003372 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00003373 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003374 }
3375 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003376
3377 // The mips ABIs for returning structs by value requires that we copy
3378 // the sret argument into $v0 for the return. Save the argument into
3379 // a virtual register so that we can access it from the return points.
3380 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3381 unsigned Reg = MipsFI->getSRetReturnReg();
3382 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00003383 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003384 MipsFI->setSRetReturnReg(Reg);
3385 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00003386 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00003387 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003388 }
3389
Akira Hatanakabad53f42011-11-14 19:01:09 +00003390 if (isVarArg) {
3391 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00003392 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003393 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
3394 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00003395 const TargetRegisterClass *RC = IsO32 ?
3396 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
3397 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00003398 unsigned RegSize = RC->getSize();
3399 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
3400
3401 // Offset of the first variable argument from stack pointer.
3402 int FirstVaArgOffset;
3403
3404 if (IsO32 || (Idx == NumOfRegs)) {
3405 FirstVaArgOffset =
3406 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
3407 } else
3408 FirstVaArgOffset = RegSlotOffset;
3409
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003410 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00003411 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00003412 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003413 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00003414
Akira Hatanakabad53f42011-11-14 19:01:09 +00003415 // Copy the integer registers that have not been used for argument passing
3416 // to the argument register save area. For O32, the save area is allocated
3417 // in the caller's stack frame, while for N32/64, it is allocated in the
3418 // callee's stack frame.
3419 for (int StackOffset = RegSlotOffset;
3420 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
3421 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
3422 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3423 MVT::getIntegerVT(RegSize * 8));
3424 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00003425 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
3426 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00003427 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003428 }
3429 }
3430
Akira Hatanaka43299772011-05-20 23:22:14 +00003431 MipsFI->setLastInArgFI(LastFI);
3432
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003433 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00003434 // the size of Ins and InVals. This only happens when on varg functions
3435 if (!OutChains.empty()) {
3436 OutChains.push_back(Chain);
3437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3438 &OutChains[0], OutChains.size());
3439 }
3440
Dan Gohman98ca4f22009-08-05 01:29:28 +00003441 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003442}
3443
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003444//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003445// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003446//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003447
Akira Hatanaka97d9f082012-10-10 01:27:09 +00003448bool
3449MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3450 MachineFunction &MF, bool isVarArg,
3451 const SmallVectorImpl<ISD::OutputArg> &Outs,
3452 LLVMContext &Context) const {
3453 SmallVector<CCValAssign, 16> RVLocs;
3454 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3455 RVLocs, Context);
3456 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3457}
3458
Dan Gohman98ca4f22009-08-05 01:29:28 +00003459SDValue
3460MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00003461 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00003462 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00003463 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00003464 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00003465
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003466 // CCValAssign - represent the assignment of
3467 // the return value to a location
3468 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003469
3470 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00003471 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka864f6602012-06-14 21:10:56 +00003472 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003473
Dan Gohman98ca4f22009-08-05 01:29:28 +00003474 // Analize return values.
3475 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003476
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003477 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003478 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00003479 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003480 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003481 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003482 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003483 }
3484
Dan Gohman475871a2008-07-27 21:46:04 +00003485 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003486
3487 // Copy the result values into the output registers.
3488 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3489 CCValAssign &VA = RVLocs[i];
3490 assert(VA.isRegLoc() && "Can only return in registers!");
3491
Akira Hatanaka82099682011-12-19 19:52:25 +00003492 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003493
3494 // guarantee that all emitted copies are
3495 // stuck together, avoiding something bad
3496 Flag = Chain.getValue(1);
3497 }
3498
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003499 // The mips ABIs for returning structs by value requires that we copy
3500 // the sret argument into $v0 for the return. We saved the argument into
3501 // a virtual register in the entry block, so now we copy the value out
3502 // and into $v0.
3503 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3504 MachineFunction &MF = DAG.getMachineFunction();
3505 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3506 unsigned Reg = MipsFI->getSRetReturnReg();
3507
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003508 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00003509 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00003510 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003511
Dale Johannesena05dca42009-02-04 23:02:30 +00003512 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003513 Flag = Chain.getValue(1);
3514 }
3515
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003516 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00003517 if (Flag.getNode())
Akira Hatanaka182ef6f2012-07-10 00:19:06 +00003518 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3519
3520 // Return Void
3521 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003522}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003523
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003524//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003525// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003526//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003527
3528/// getConstraintType - Given a constraint letter, return the type of
3529/// constraint it is for this target.
3530MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003531getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003532{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003533 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003534 // GCC config/mips/constraints.md
3535 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003536 // 'd' : An address register. Equivalent to r
3537 // unless generating MIPS16 code.
3538 // 'y' : Equivalent to r; retained for
3539 // backwards compatibility.
Eric Christopher1d5a3922012-05-07 06:25:10 +00003540 // 'c' : A register suitable for use in an indirect
3541 // jump. This will always be $25 for -mabicalls.
Eric Christopheraf97f732012-05-07 06:25:19 +00003542 // 'l' : The lo register. 1 word storage.
3543 // 'x' : The hilo register pair. Double word storage.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003544 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003545 switch (Constraint[0]) {
3546 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003547 case 'd':
3548 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003549 case 'f':
Eric Christopher1d5a3922012-05-07 06:25:10 +00003550 case 'c':
Eric Christopher4adbefe2012-05-07 06:25:15 +00003551 case 'l':
Eric Christopheraf97f732012-05-07 06:25:19 +00003552 case 'x':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003553 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003554 }
3555 }
3556 return TargetLowering::getConstraintType(Constraint);
3557}
3558
John Thompson44ab89e2010-10-29 17:29:13 +00003559/// Examine constraint type and operand type and determine a weight value.
3560/// This object must already have been set up with the operand type
3561/// and the current alternative constraint selected.
3562TargetLowering::ConstraintWeight
3563MipsTargetLowering::getSingleConstraintMatchWeight(
3564 AsmOperandInfo &info, const char *constraint) const {
3565 ConstraintWeight weight = CW_Invalid;
3566 Value *CallOperandVal = info.CallOperandVal;
3567 // If we don't have a value, we can't do a match,
3568 // but allow it at the lowest weight.
3569 if (CallOperandVal == NULL)
3570 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003571 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003572 // Look at the constraint type.
3573 switch (*constraint) {
3574 default:
3575 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3576 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003577 case 'd':
3578 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003579 if (type->isIntegerTy())
3580 weight = CW_Register;
3581 break;
3582 case 'f':
3583 if (type->isFloatTy())
3584 weight = CW_Register;
3585 break;
Eric Christopher1d5a3922012-05-07 06:25:10 +00003586 case 'c': // $25 for indirect jumps
Eric Christopher4adbefe2012-05-07 06:25:15 +00003587 case 'l': // lo register
Eric Christopheraf97f732012-05-07 06:25:19 +00003588 case 'x': // hilo register pair
Eric Christopher1d5a3922012-05-07 06:25:10 +00003589 if (type->isIntegerTy())
3590 weight = CW_SpecificReg;
3591 break;
Eric Christopher50ab0392012-05-07 03:13:32 +00003592 case 'I': // signed 16 bit immediate
Eric Christophere5076d42012-05-07 03:13:42 +00003593 case 'J': // integer zero
Eric Christopherf49f8462012-05-07 05:46:29 +00003594 case 'K': // unsigned 16 bit immediate
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003595 case 'L': // signed 32 bit immediate where lower 16 bits are 0
Eric Christopher60cfc792012-05-07 05:46:43 +00003596 case 'N': // immediate in the range of -65535 to -1 (inclusive)
Eric Christopher1ce20342012-05-07 05:46:48 +00003597 case 'O': // signed 15 bit immediate (+- 16383)
Eric Christopher54412a72012-05-07 06:25:02 +00003598 case 'P': // immediate in the range of 65535 to 1 (inclusive)
Eric Christopher50ab0392012-05-07 03:13:32 +00003599 if (isa<ConstantInt>(CallOperandVal))
3600 weight = CW_Constant;
3601 break;
John Thompson44ab89e2010-10-29 17:29:13 +00003602 }
3603 return weight;
3604}
3605
Eric Christopher38d64262011-06-29 19:33:04 +00003606/// Given a register class constraint, like 'r', if this corresponds directly
3607/// to an LLVM register class, return a register of 0 and the register class
3608/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003609std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003610getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003611{
3612 if (Constraint.size() == 1) {
3613 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003614 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3615 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003616 case 'r':
Akira Hatanakaafc945b2012-09-12 23:27:55 +00003617 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3618 if (Subtarget->inMips16Mode())
3619 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
Craig Topper420761a2012-04-20 07:30:17 +00003620 return std::make_pair(0U, &Mips::CPURegsRegClass);
Akira Hatanakaafc945b2012-09-12 23:27:55 +00003621 }
Jack Carter10de0252012-07-02 23:35:23 +00003622 if (VT == MVT::i64 && !HasMips64)
3623 return std::make_pair(0U, &Mips::CPURegsRegClass);
Eric Christopher0ed1f762012-05-07 03:13:22 +00003624 if (VT == MVT::i64 && HasMips64)
3625 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3626 // This will generate an error message
3627 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003628 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003629 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003630 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003631 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3632 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003633 return std::make_pair(0U, &Mips::FGR64RegClass);
3634 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003635 }
Eric Christopher1d5a3922012-05-07 06:25:10 +00003636 break;
3637 case 'c': // register suitable for indirect jump
3638 if (VT == MVT::i32)
3639 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3640 assert(VT == MVT::i64 && "Unexpected type.");
3641 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
Eric Christopher4adbefe2012-05-07 06:25:15 +00003642 case 'l': // register suitable for indirect jump
3643 if (VT == MVT::i32)
3644 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3645 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
Eric Christopheraf97f732012-05-07 06:25:19 +00003646 case 'x': // register suitable for indirect jump
3647 // Fixme: Not triggering the use of both hi and low
3648 // This will generate an error message
3649 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003650 }
3651 }
3652 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3653}
3654
Eric Christopher50ab0392012-05-07 03:13:32 +00003655/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3656/// vector. If it is invalid, don't add anything to Ops.
3657void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3658 std::string &Constraint,
3659 std::vector<SDValue>&Ops,
3660 SelectionDAG &DAG) const {
3661 SDValue Result(0, 0);
3662
3663 // Only support length 1 constraints for now.
3664 if (Constraint.length() > 1) return;
3665
3666 char ConstraintLetter = Constraint[0];
3667 switch (ConstraintLetter) {
3668 default: break; // This will fall through to the generic implementation
3669 case 'I': // Signed 16 bit constant
3670 // If this fails, the parent routine will give an error
3671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3672 EVT Type = Op.getValueType();
3673 int64_t Val = C->getSExtValue();
3674 if (isInt<16>(Val)) {
3675 Result = DAG.getTargetConstant(Val, Type);
3676 break;
3677 }
3678 }
3679 return;
Eric Christophere5076d42012-05-07 03:13:42 +00003680 case 'J': // integer zero
3681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3682 EVT Type = Op.getValueType();
3683 int64_t Val = C->getZExtValue();
3684 if (Val == 0) {
3685 Result = DAG.getTargetConstant(0, Type);
3686 break;
3687 }
3688 }
3689 return;
Eric Christopherf49f8462012-05-07 05:46:29 +00003690 case 'K': // unsigned 16 bit immediate
3691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3692 EVT Type = Op.getValueType();
3693 uint64_t Val = (uint64_t)C->getZExtValue();
3694 if (isUInt<16>(Val)) {
3695 Result = DAG.getTargetConstant(Val, Type);
3696 break;
3697 }
3698 }
3699 return;
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003700 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3701 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3702 EVT Type = Op.getValueType();
3703 int64_t Val = C->getSExtValue();
3704 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3705 Result = DAG.getTargetConstant(Val, Type);
3706 break;
3707 }
3708 }
3709 return;
Eric Christopher60cfc792012-05-07 05:46:43 +00003710 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3712 EVT Type = Op.getValueType();
3713 int64_t Val = C->getSExtValue();
3714 if ((Val >= -65535) && (Val <= -1)) {
3715 Result = DAG.getTargetConstant(Val, Type);
3716 break;
3717 }
3718 }
3719 return;
Eric Christopher1ce20342012-05-07 05:46:48 +00003720 case 'O': // signed 15 bit immediate
3721 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3722 EVT Type = Op.getValueType();
3723 int64_t Val = C->getSExtValue();
3724 if ((isInt<15>(Val))) {
3725 Result = DAG.getTargetConstant(Val, Type);
3726 break;
3727 }
3728 }
3729 return;
Eric Christopher54412a72012-05-07 06:25:02 +00003730 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3732 EVT Type = Op.getValueType();
3733 int64_t Val = C->getSExtValue();
3734 if ((Val <= 65535) && (Val >= 1)) {
3735 Result = DAG.getTargetConstant(Val, Type);
3736 break;
3737 }
3738 }
3739 return;
Eric Christopher50ab0392012-05-07 03:13:32 +00003740 }
3741
3742 if (Result.getNode()) {
3743 Ops.push_back(Result);
3744 return;
3745 }
3746
3747 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3748}
3749
Dan Gohman6520e202008-10-18 02:06:02 +00003750bool
3751MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3752 // The Mips target isn't yet aware of offsets.
3753 return false;
3754}
Evan Chengeb2f9692009-10-27 19:56:55 +00003755
Akira Hatanakae193b322012-06-13 19:33:32 +00003756EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3757 unsigned SrcAlign, bool IsZeroVal,
3758 bool MemcpyStrSrc,
3759 MachineFunction &MF) const {
3760 if (Subtarget->hasMips64())
3761 return MVT::i64;
3762
3763 return MVT::i32;
3764}
3765
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003766bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3767 if (VT != MVT::f32 && VT != MVT::f64)
3768 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003769 if (Imm.isNegZero())
3770 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003771 return Imm.isZero();
3772}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003773
3774unsigned MipsTargetLowering::getJumpTableEncoding() const {
3775 if (IsN64)
3776 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003777
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003778 return TargetLowering::getJumpTableEncoding();
3779}