Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 43 | unsigned alignment, |
| 44 | bool map_and_fenceable); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 45 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
| 46 | struct drm_i915_fence_reg *reg); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 47 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 48 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 49 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 50 | struct drm_file *file); |
| 51 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 52 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 53 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 54 | struct drm_i915_gem_object *obj); |
| 55 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 56 | struct drm_i915_fence_reg *fence, |
| 57 | bool enable); |
| 58 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 60 | struct shrink_control *sc); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 62 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 64 | { |
| 65 | if (obj->tiling_mode) |
| 66 | i915_gem_release_mmap(obj); |
| 67 | |
| 68 | /* As we do not have an associated fence register, we will force |
| 69 | * a tiling change if we ever need to acquire one. |
| 70 | */ |
| 71 | obj->tiling_changed = false; |
| 72 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 73 | } |
| 74 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 75 | /* some bookkeeping */ |
| 76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 77 | size_t size) |
| 78 | { |
| 79 | dev_priv->mm.object_count++; |
| 80 | dev_priv->mm.object_memory += size; |
| 81 | } |
| 82 | |
| 83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 84 | size_t size) |
| 85 | { |
| 86 | dev_priv->mm.object_count--; |
| 87 | dev_priv->mm.object_memory -= size; |
| 88 | } |
| 89 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 90 | static int |
| 91 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 92 | { |
| 93 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 94 | struct completion *x = &dev_priv->error_completion; |
| 95 | unsigned long flags; |
| 96 | int ret; |
| 97 | |
| 98 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 99 | return 0; |
| 100 | |
| 101 | ret = wait_for_completion_interruptible(x); |
| 102 | if (ret) |
| 103 | return ret; |
| 104 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 105 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 106 | /* GPU is hung, bump the completion count to account for |
| 107 | * the token we just consumed so that we never hit zero and |
| 108 | * end up waiting upon a subsequent completion event that |
| 109 | * will never happen. |
| 110 | */ |
| 111 | spin_lock_irqsave(&x->wait.lock, flags); |
| 112 | x->done++; |
| 113 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 114 | } |
| 115 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 116 | } |
| 117 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 118 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 119 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 120 | int ret; |
| 121 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 122 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 123 | if (ret) |
| 124 | return ret; |
| 125 | |
| 126 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 127 | if (ret) |
| 128 | return ret; |
| 129 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 130 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 131 | return 0; |
| 132 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 133 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 134 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 135 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 136 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 137 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 138 | } |
| 139 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 140 | int |
| 141 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 142 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 143 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 144 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 145 | |
| 146 | if (args->gtt_start >= args->gtt_end || |
| 147 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 148 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 150 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 151 | if (INTEL_INFO(dev)->gen >= 5) |
| 152 | return -ENODEV; |
| 153 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 154 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 155 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 156 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 157 | mutex_unlock(&dev->struct_mutex); |
| 158 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 159 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 160 | } |
| 161 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 162 | int |
| 163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 164 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 165 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 167 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 168 | struct drm_i915_gem_object *obj; |
| 169 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 170 | |
| 171 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 172 | return -ENODEV; |
| 173 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 174 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 175 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 176 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
| 177 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 178 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 179 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 180 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 181 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 182 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 183 | return 0; |
| 184 | } |
| 185 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 186 | static int |
| 187 | i915_gem_create(struct drm_file *file, |
| 188 | struct drm_device *dev, |
| 189 | uint64_t size, |
| 190 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 191 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 192 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 193 | int ret; |
| 194 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 195 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 196 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 197 | if (size == 0) |
| 198 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 199 | |
| 200 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 201 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 202 | if (obj == NULL) |
| 203 | return -ENOMEM; |
| 204 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 205 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 206 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 207 | drm_gem_object_release(&obj->base); |
| 208 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 209 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 210 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 211 | } |
| 212 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 213 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 214 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 215 | trace_i915_gem_object_create(obj); |
| 216 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 217 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 218 | return 0; |
| 219 | } |
| 220 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 221 | int |
| 222 | i915_gem_dumb_create(struct drm_file *file, |
| 223 | struct drm_device *dev, |
| 224 | struct drm_mode_create_dumb *args) |
| 225 | { |
| 226 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 227 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 228 | args->size = args->pitch * args->height; |
| 229 | return i915_gem_create(file, dev, |
| 230 | args->size, &args->handle); |
| 231 | } |
| 232 | |
| 233 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 234 | struct drm_device *dev, |
| 235 | uint32_t handle) |
| 236 | { |
| 237 | return drm_gem_handle_delete(file, handle); |
| 238 | } |
| 239 | |
| 240 | /** |
| 241 | * Creates a new mm object and returns a handle to it. |
| 242 | */ |
| 243 | int |
| 244 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 245 | struct drm_file *file) |
| 246 | { |
| 247 | struct drm_i915_gem_create *args = data; |
| 248 | return i915_gem_create(file, dev, |
| 249 | args->size, &args->handle); |
| 250 | } |
| 251 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 252 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 253 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 254 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 255 | |
| 256 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 257 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 258 | } |
| 259 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 260 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 261 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 262 | const char *gpu_vaddr, int gpu_offset, |
| 263 | int length) |
| 264 | { |
| 265 | int ret, cpu_offset = 0; |
| 266 | |
| 267 | while (length > 0) { |
| 268 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 269 | int this_length = min(cacheline_end - gpu_offset, length); |
| 270 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 271 | |
| 272 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 273 | gpu_vaddr + swizzled_gpu_offset, |
| 274 | this_length); |
| 275 | if (ret) |
| 276 | return ret + length; |
| 277 | |
| 278 | cpu_offset += this_length; |
| 279 | gpu_offset += this_length; |
| 280 | length -= this_length; |
| 281 | } |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static inline int |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 287 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, |
| 288 | const char *cpu_vaddr, |
| 289 | int length) |
| 290 | { |
| 291 | int ret, cpu_offset = 0; |
| 292 | |
| 293 | while (length > 0) { |
| 294 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 295 | int this_length = min(cacheline_end - gpu_offset, length); |
| 296 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 297 | |
| 298 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 299 | cpu_vaddr + cpu_offset, |
| 300 | this_length); |
| 301 | if (ret) |
| 302 | return ret + length; |
| 303 | |
| 304 | cpu_offset += this_length; |
| 305 | gpu_offset += this_length; |
| 306 | length -= this_length; |
| 307 | } |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 312 | /* Per-page copy function for the shmem pread fastpath. |
| 313 | * Flushes invalid cachelines before reading the target if |
| 314 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 315 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 316 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 317 | char __user *user_data, |
| 318 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 319 | { |
| 320 | char *vaddr; |
| 321 | int ret; |
| 322 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 323 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 324 | return -EINVAL; |
| 325 | |
| 326 | vaddr = kmap_atomic(page); |
| 327 | if (needs_clflush) |
| 328 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 329 | page_length); |
| 330 | ret = __copy_to_user_inatomic(user_data, |
| 331 | vaddr + shmem_page_offset, |
| 332 | page_length); |
| 333 | kunmap_atomic(vaddr); |
| 334 | |
| 335 | return ret; |
| 336 | } |
| 337 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 338 | static void |
| 339 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 340 | bool swizzled) |
| 341 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 342 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 343 | unsigned long start = (unsigned long) addr; |
| 344 | unsigned long end = (unsigned long) addr + length; |
| 345 | |
| 346 | /* For swizzling simply ensure that we always flush both |
| 347 | * channels. Lame, but simple and it works. Swizzled |
| 348 | * pwrite/pread is far from a hotpath - current userspace |
| 349 | * doesn't use it at all. */ |
| 350 | start = round_down(start, 128); |
| 351 | end = round_up(end, 128); |
| 352 | |
| 353 | drm_clflush_virt_range((void *)start, end - start); |
| 354 | } else { |
| 355 | drm_clflush_virt_range(addr, length); |
| 356 | } |
| 357 | |
| 358 | } |
| 359 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 360 | /* Only difference to the fast-path function is that this can handle bit17 |
| 361 | * and uses non-atomic copy and kmap functions. */ |
| 362 | static int |
| 363 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 364 | char __user *user_data, |
| 365 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 366 | { |
| 367 | char *vaddr; |
| 368 | int ret; |
| 369 | |
| 370 | vaddr = kmap(page); |
| 371 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 372 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 373 | page_length, |
| 374 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 375 | |
| 376 | if (page_do_bit17_swizzling) |
| 377 | ret = __copy_to_user_swizzled(user_data, |
| 378 | vaddr, shmem_page_offset, |
| 379 | page_length); |
| 380 | else |
| 381 | ret = __copy_to_user(user_data, |
| 382 | vaddr + shmem_page_offset, |
| 383 | page_length); |
| 384 | kunmap(page); |
| 385 | |
| 386 | return ret; |
| 387 | } |
| 388 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 389 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 390 | i915_gem_shmem_pread(struct drm_device *dev, |
| 391 | struct drm_i915_gem_object *obj, |
| 392 | struct drm_i915_gem_pread *args, |
| 393 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 394 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 395 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 396 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 397 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 398 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 399 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 400 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 401 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 402 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 403 | int needs_clflush = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 404 | int release_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 406 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 407 | remain = args->size; |
| 408 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 409 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 411 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 412 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 413 | * read domain and manually flush cachelines (if required). This |
| 414 | * optimizes for the case when the gpu will dirty the data |
| 415 | * anyway again before the next pread happens. */ |
| 416 | if (obj->cache_level == I915_CACHE_NONE) |
| 417 | needs_clflush = 1; |
| 418 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 419 | if (ret) |
| 420 | return ret; |
| 421 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 422 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 423 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 424 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 425 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 426 | struct page *page; |
| 427 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 428 | /* Operation in this page |
| 429 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 430 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | * page_length = bytes to copy for this page |
| 432 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 433 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 434 | page_length = remain; |
| 435 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 436 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 437 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 438 | if (obj->pages) { |
| 439 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 440 | release_page = 0; |
| 441 | } else { |
| 442 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 443 | if (IS_ERR(page)) { |
| 444 | ret = PTR_ERR(page); |
| 445 | goto out; |
| 446 | } |
| 447 | release_page = 1; |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 448 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 449 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 450 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 451 | (page_to_phys(page) & (1 << 17)) != 0; |
| 452 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 453 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 454 | user_data, page_do_bit17_swizzling, |
| 455 | needs_clflush); |
| 456 | if (ret == 0) |
| 457 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 459 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 460 | page_cache_get(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 461 | mutex_unlock(&dev->struct_mutex); |
| 462 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 463 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 464 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 465 | /* Userspace is tricking us, but we've already clobbered |
| 466 | * its pages with the prefault and promised to write the |
| 467 | * data up to the first fault. Hence ignore any errors |
| 468 | * and just continue. */ |
| 469 | (void)ret; |
| 470 | prefaulted = 1; |
| 471 | } |
| 472 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 473 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 474 | user_data, page_do_bit17_swizzling, |
| 475 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 476 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 477 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 478 | page_cache_release(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 479 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 480 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 481 | if (release_page) |
| 482 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 483 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 484 | if (ret) { |
| 485 | ret = -EFAULT; |
| 486 | goto out; |
| 487 | } |
| 488 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 489 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 490 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 491 | offset += page_length; |
| 492 | } |
| 493 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 494 | out: |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 495 | if (hit_slowpath) { |
| 496 | /* Fixup: Kill any reinstated backing storage pages */ |
| 497 | if (obj->madv == __I915_MADV_PURGED) |
| 498 | i915_gem_object_truncate(obj); |
| 499 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 500 | |
| 501 | return ret; |
| 502 | } |
| 503 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 504 | /** |
| 505 | * Reads data from the object referenced by handle. |
| 506 | * |
| 507 | * On error, the contents of *data are undefined. |
| 508 | */ |
| 509 | int |
| 510 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 511 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 512 | { |
| 513 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 514 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 515 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 516 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 517 | if (args->size == 0) |
| 518 | return 0; |
| 519 | |
| 520 | if (!access_ok(VERIFY_WRITE, |
| 521 | (char __user *)(uintptr_t)args->data_ptr, |
| 522 | args->size)) |
| 523 | return -EFAULT; |
| 524 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 525 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 526 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 527 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 528 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 529 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 530 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 531 | ret = -ENOENT; |
| 532 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 533 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 534 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 535 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 536 | if (args->offset > obj->base.size || |
| 537 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 538 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 539 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 540 | } |
| 541 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 542 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 543 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 544 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 545 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 546 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 547 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 548 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 549 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 550 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 551 | } |
| 552 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 553 | /* This is the fast write path which cannot handle |
| 554 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 555 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 556 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 557 | static inline int |
| 558 | fast_user_write(struct io_mapping *mapping, |
| 559 | loff_t page_base, int page_offset, |
| 560 | char __user *user_data, |
| 561 | int length) |
| 562 | { |
| 563 | char *vaddr_atomic; |
| 564 | unsigned long unwritten; |
| 565 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 566 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 567 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 568 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 569 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 570 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 571 | } |
| 572 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 573 | /** |
| 574 | * This is the fast pwrite path, where we copy the data directly from the |
| 575 | * user into the GTT, uncached. |
| 576 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 577 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 578 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 579 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 580 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 581 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 582 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 583 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 584 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 585 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 586 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 587 | int page_offset, page_length, ret; |
| 588 | |
| 589 | ret = i915_gem_object_pin(obj, 0, true); |
| 590 | if (ret) |
| 591 | goto out; |
| 592 | |
| 593 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 594 | if (ret) |
| 595 | goto out_unpin; |
| 596 | |
| 597 | ret = i915_gem_object_put_fence(obj); |
| 598 | if (ret) |
| 599 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | |
| 601 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 602 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 603 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 604 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 605 | |
| 606 | while (remain > 0) { |
| 607 | /* Operation in this page |
| 608 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 609 | * page_base = page offset within aperture |
| 610 | * page_offset = offset within page |
| 611 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 612 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 613 | page_base = offset & PAGE_MASK; |
| 614 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 615 | page_length = remain; |
| 616 | if ((page_offset + remain) > PAGE_SIZE) |
| 617 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 618 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 619 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 620 | * source page isn't available. Return the error and we'll |
| 621 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 622 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 623 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 624 | page_offset, user_data, page_length)) { |
| 625 | ret = -EFAULT; |
| 626 | goto out_unpin; |
| 627 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 628 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 629 | remain -= page_length; |
| 630 | user_data += page_length; |
| 631 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 632 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 633 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 634 | out_unpin: |
| 635 | i915_gem_object_unpin(obj); |
| 636 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 637 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 638 | } |
| 639 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 640 | /* Per-page copy function for the shmem pwrite fastpath. |
| 641 | * Flushes invalid cachelines before writing to the target if |
| 642 | * needs_clflush_before is set and flushes out any written cachelines after |
| 643 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 644 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 645 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 646 | char __user *user_data, |
| 647 | bool page_do_bit17_swizzling, |
| 648 | bool needs_clflush_before, |
| 649 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 650 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 651 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 652 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 653 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 654 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 655 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 656 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 657 | vaddr = kmap_atomic(page); |
| 658 | if (needs_clflush_before) |
| 659 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 660 | page_length); |
| 661 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 662 | user_data, |
| 663 | page_length); |
| 664 | if (needs_clflush_after) |
| 665 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 666 | page_length); |
| 667 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 668 | |
| 669 | return ret; |
| 670 | } |
| 671 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 672 | /* Only difference to the fast-path function is that this can handle bit17 |
| 673 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 674 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 675 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 676 | char __user *user_data, |
| 677 | bool page_do_bit17_swizzling, |
| 678 | bool needs_clflush_before, |
| 679 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 680 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 681 | char *vaddr; |
| 682 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 683 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 684 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 685 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 686 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 687 | page_length, |
| 688 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 689 | if (page_do_bit17_swizzling) |
| 690 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 691 | user_data, |
| 692 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 693 | else |
| 694 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 695 | user_data, |
| 696 | page_length); |
| 697 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 698 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 699 | page_length, |
| 700 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 701 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 702 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 703 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 704 | } |
| 705 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 706 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 707 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 708 | struct drm_i915_gem_object *obj, |
| 709 | struct drm_i915_gem_pwrite *args, |
| 710 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 711 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 712 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 713 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 714 | loff_t offset; |
| 715 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 716 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 717 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 718 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 719 | int needs_clflush_after = 0; |
| 720 | int needs_clflush_before = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 721 | int release_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 722 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 723 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 724 | remain = args->size; |
| 725 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 726 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 727 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 728 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 729 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 730 | * write domain and manually flush cachelines (if required). This |
| 731 | * optimizes for the case when the gpu will use the data |
| 732 | * right away and we therefore have to clflush anyway. */ |
| 733 | if (obj->cache_level == I915_CACHE_NONE) |
| 734 | needs_clflush_after = 1; |
| 735 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 736 | if (ret) |
| 737 | return ret; |
| 738 | } |
| 739 | /* Same trick applies for invalidate partially written cachelines before |
| 740 | * writing. */ |
| 741 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 742 | && obj->cache_level == I915_CACHE_NONE) |
| 743 | needs_clflush_before = 1; |
| 744 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 745 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 746 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 747 | |
| 748 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 749 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 750 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 751 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 752 | /* Operation in this page |
| 753 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 754 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 755 | * page_length = bytes to copy for this page |
| 756 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 757 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 758 | |
| 759 | page_length = remain; |
| 760 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 761 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 762 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 763 | /* If we don't overwrite a cacheline completely we need to be |
| 764 | * careful to have up-to-date data by first clflushing. Don't |
| 765 | * overcomplicate things and flush the entire patch. */ |
| 766 | partial_cacheline_write = needs_clflush_before && |
| 767 | ((shmem_page_offset | page_length) |
| 768 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 769 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 770 | if (obj->pages) { |
| 771 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 772 | release_page = 0; |
| 773 | } else { |
| 774 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 775 | if (IS_ERR(page)) { |
| 776 | ret = PTR_ERR(page); |
| 777 | goto out; |
| 778 | } |
| 779 | release_page = 1; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 780 | } |
| 781 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 782 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 783 | (page_to_phys(page) & (1 << 17)) != 0; |
| 784 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 785 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 786 | user_data, page_do_bit17_swizzling, |
| 787 | partial_cacheline_write, |
| 788 | needs_clflush_after); |
| 789 | if (ret == 0) |
| 790 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 791 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 792 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 793 | page_cache_get(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 794 | mutex_unlock(&dev->struct_mutex); |
| 795 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 796 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 797 | user_data, page_do_bit17_swizzling, |
| 798 | partial_cacheline_write, |
| 799 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 800 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 801 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 802 | page_cache_release(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 803 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 804 | set_page_dirty(page); |
| 805 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 806 | if (release_page) |
| 807 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 808 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 809 | if (ret) { |
| 810 | ret = -EFAULT; |
| 811 | goto out; |
| 812 | } |
| 813 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 814 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 815 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | offset += page_length; |
| 817 | } |
| 818 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 819 | out: |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 820 | if (hit_slowpath) { |
| 821 | /* Fixup: Kill any reinstated backing storage pages */ |
| 822 | if (obj->madv == __I915_MADV_PURGED) |
| 823 | i915_gem_object_truncate(obj); |
| 824 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 825 | * domain anymore. */ |
| 826 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 827 | i915_gem_clflush_object(obj); |
| 828 | intel_gtt_chipset_flush(); |
| 829 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 830 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 831 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 832 | if (needs_clflush_after) |
| 833 | intel_gtt_chipset_flush(); |
| 834 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 835 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 836 | } |
| 837 | |
| 838 | /** |
| 839 | * Writes data to the object referenced by handle. |
| 840 | * |
| 841 | * On error, the contents of the buffer that were to be modified are undefined. |
| 842 | */ |
| 843 | int |
| 844 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 845 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 846 | { |
| 847 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 848 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 849 | int ret; |
| 850 | |
| 851 | if (args->size == 0) |
| 852 | return 0; |
| 853 | |
| 854 | if (!access_ok(VERIFY_READ, |
| 855 | (char __user *)(uintptr_t)args->data_ptr, |
| 856 | args->size)) |
| 857 | return -EFAULT; |
| 858 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 859 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 860 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 861 | if (ret) |
| 862 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 863 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 864 | ret = i915_mutex_lock_interruptible(dev); |
| 865 | if (ret) |
| 866 | return ret; |
| 867 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 868 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 869 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 870 | ret = -ENOENT; |
| 871 | goto unlock; |
| 872 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 873 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 874 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 875 | if (args->offset > obj->base.size || |
| 876 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 877 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 878 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 879 | } |
| 880 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 881 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 882 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 883 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 884 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 885 | * it would end up going through the fenced access, and we'll get |
| 886 | * different detiling behavior between reading and writing. |
| 887 | * pread/pwrite currently are reading and writing from the CPU |
| 888 | * perspective, requiring manual detiling by the client. |
| 889 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 890 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 891 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 892 | goto out; |
| 893 | } |
| 894 | |
| 895 | if (obj->gtt_space && |
Daniel Vetter | 3ae5378 | 2012-03-25 19:47:33 +0200 | [diff] [blame] | 896 | obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 897 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | ffc6297 | 2012-03-25 19:47:38 +0200 | [diff] [blame] | 898 | obj->map_and_fenceable && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 899 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 900 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 901 | /* Note that the gtt paths might fail with non-page-backed user |
| 902 | * pointers (e.g. gtt mappings when moving data between |
| 903 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 904 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 905 | |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 906 | if (ret == -EFAULT) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 907 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 908 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 909 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 910 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 911 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 912 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 913 | return ret; |
| 914 | } |
| 915 | |
| 916 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 917 | * Called when user space prepares to use an object with the CPU, either |
| 918 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 919 | */ |
| 920 | int |
| 921 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 922 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 923 | { |
| 924 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 925 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 926 | uint32_t read_domains = args->read_domains; |
| 927 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 928 | int ret; |
| 929 | |
| 930 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 931 | return -ENODEV; |
| 932 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 933 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 934 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 935 | return -EINVAL; |
| 936 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 937 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 938 | return -EINVAL; |
| 939 | |
| 940 | /* Having something in the write domain implies it's in the read |
| 941 | * domain, and only that read domain. Enforce that in the request. |
| 942 | */ |
| 943 | if (write_domain != 0 && read_domains != write_domain) |
| 944 | return -EINVAL; |
| 945 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 946 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 947 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 948 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 949 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 950 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 951 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 952 | ret = -ENOENT; |
| 953 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 954 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 955 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 956 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 957 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 958 | |
| 959 | /* Silently promote "you're not bound, there was nothing to do" |
| 960 | * to success, since the client was just asking us to |
| 961 | * make sure everything was done. |
| 962 | */ |
| 963 | if (ret == -EINVAL) |
| 964 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 965 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 966 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 967 | } |
| 968 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 969 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 970 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 971 | mutex_unlock(&dev->struct_mutex); |
| 972 | return ret; |
| 973 | } |
| 974 | |
| 975 | /** |
| 976 | * Called when user space has done writes to this buffer |
| 977 | */ |
| 978 | int |
| 979 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 980 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 981 | { |
| 982 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 983 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 984 | int ret = 0; |
| 985 | |
| 986 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 987 | return -ENODEV; |
| 988 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 989 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 990 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 991 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 992 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 993 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 994 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 995 | ret = -ENOENT; |
| 996 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 997 | } |
| 998 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 999 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1000 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1001 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1002 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1003 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1004 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1005 | mutex_unlock(&dev->struct_mutex); |
| 1006 | return ret; |
| 1007 | } |
| 1008 | |
| 1009 | /** |
| 1010 | * Maps the contents of an object, returning the address it is mapped |
| 1011 | * into. |
| 1012 | * |
| 1013 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1014 | * imply a ref on the object itself. |
| 1015 | */ |
| 1016 | int |
| 1017 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1018 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1019 | { |
| 1020 | struct drm_i915_gem_mmap *args = data; |
| 1021 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1022 | unsigned long addr; |
| 1023 | |
| 1024 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1025 | return -ENODEV; |
| 1026 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1027 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1028 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1029 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1030 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1031 | down_write(¤t->mm->mmap_sem); |
| 1032 | addr = do_mmap(obj->filp, 0, args->size, |
| 1033 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1034 | args->offset); |
| 1035 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1036 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1037 | if (IS_ERR((void *)addr)) |
| 1038 | return addr; |
| 1039 | |
| 1040 | args->addr_ptr = (uint64_t) addr; |
| 1041 | |
| 1042 | return 0; |
| 1043 | } |
| 1044 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1045 | /** |
| 1046 | * i915_gem_fault - fault a page into the GTT |
| 1047 | * vma: VMA in question |
| 1048 | * vmf: fault info |
| 1049 | * |
| 1050 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1051 | * from userspace. The fault handler takes care of binding the object to |
| 1052 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1053 | * only if needed based on whether the old reg is still valid or the object |
| 1054 | * is tiled) and inserting a new PTE into the faulting process. |
| 1055 | * |
| 1056 | * Note that the faulting process may involve evicting existing objects |
| 1057 | * from the GTT and/or fence registers to make room. So performance may |
| 1058 | * suffer if the GTT working set is large or there are few fence registers |
| 1059 | * left. |
| 1060 | */ |
| 1061 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1062 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1063 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1064 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1065 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1066 | pgoff_t page_offset; |
| 1067 | unsigned long pfn; |
| 1068 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1069 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1070 | |
| 1071 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1072 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1073 | PAGE_SHIFT; |
| 1074 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1075 | ret = i915_mutex_lock_interruptible(dev); |
| 1076 | if (ret) |
| 1077 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1078 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1079 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1080 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1081 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1082 | if (!obj->map_and_fenceable) { |
| 1083 | ret = i915_gem_object_unbind(obj); |
| 1084 | if (ret) |
| 1085 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1086 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1087 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1088 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1089 | if (ret) |
| 1090 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1091 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1092 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1093 | if (ret) |
| 1094 | goto unlock; |
| 1095 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1096 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1097 | if (!obj->has_global_gtt_mapping) |
| 1098 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1099 | |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1100 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1101 | if (ret) |
| 1102 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1103 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1104 | if (i915_gem_object_is_inactive(obj)) |
| 1105 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1106 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1107 | obj->fault_mappable = true; |
| 1108 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1109 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1110 | page_offset; |
| 1111 | |
| 1112 | /* Finally, remap it using the new GTT offset */ |
| 1113 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1114 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1115 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1116 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1117 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1118 | case -EIO: |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1119 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1120 | /* Give the error handler a chance to run and move the |
| 1121 | * objects off the GPU active list. Next time we service the |
| 1122 | * fault, we should be able to transition the page into the |
| 1123 | * GTT without touching the GPU (and so avoid further |
| 1124 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1125 | * with coherency, just lost writes. |
| 1126 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1127 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1128 | case 0: |
| 1129 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1130 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1131 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1132 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1133 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1134 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1135 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1136 | } |
| 1137 | } |
| 1138 | |
| 1139 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1140 | * i915_gem_release_mmap - remove physical page mappings |
| 1141 | * @obj: obj in question |
| 1142 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1143 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1144 | * relinquish ownership of the pages back to the system. |
| 1145 | * |
| 1146 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1147 | * object through the GTT and then lose the fence register due to |
| 1148 | * resource pressure. Similarly if the object has been moved out of the |
| 1149 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1150 | * mapping will then trigger a page fault on the next user access, allowing |
| 1151 | * fixup by i915_gem_fault(). |
| 1152 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1153 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1154 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1155 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1156 | if (!obj->fault_mappable) |
| 1157 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1158 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1159 | if (obj->base.dev->dev_mapping) |
| 1160 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1161 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1162 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1163 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1164 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1165 | } |
| 1166 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1167 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1168 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1169 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1170 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1171 | |
| 1172 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1173 | tiling_mode == I915_TILING_NONE) |
| 1174 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1175 | |
| 1176 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1177 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1178 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1179 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1180 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1181 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1182 | while (gtt_size < size) |
| 1183 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1184 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1185 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1186 | } |
| 1187 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1188 | /** |
| 1189 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1190 | * @obj: object to check |
| 1191 | * |
| 1192 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1193 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1194 | */ |
| 1195 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1196 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1197 | uint32_t size, |
| 1198 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1199 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1200 | /* |
| 1201 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1202 | * if a fence register is needed for the object. |
| 1203 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1204 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1205 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1206 | return 4096; |
| 1207 | |
| 1208 | /* |
| 1209 | * Previous chips need to be aligned to the size of the smallest |
| 1210 | * fence register that can contain the object. |
| 1211 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1212 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1213 | } |
| 1214 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1215 | /** |
| 1216 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1217 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1218 | * @dev: the device |
| 1219 | * @size: size of the object |
| 1220 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1221 | * |
| 1222 | * Return the required GTT alignment for an object, only taking into account |
| 1223 | * unfenced tiled surface requirements. |
| 1224 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1225 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1226 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1227 | uint32_t size, |
| 1228 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1229 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1230 | /* |
| 1231 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1232 | */ |
| 1233 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1234 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1235 | return 4096; |
| 1236 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1237 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1238 | * tile height. The simplest method for determining this is to reuse |
| 1239 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1240 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1241 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1242 | } |
| 1243 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1244 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1245 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1246 | struct drm_device *dev, |
| 1247 | uint32_t handle, |
| 1248 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1249 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1250 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1251 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1252 | int ret; |
| 1253 | |
| 1254 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1255 | return -ENODEV; |
| 1256 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1257 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1258 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1259 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1260 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1261 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1262 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1263 | ret = -ENOENT; |
| 1264 | goto unlock; |
| 1265 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1267 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1268 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1269 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1270 | } |
| 1271 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1272 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1273 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1274 | ret = -EINVAL; |
| 1275 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1276 | } |
| 1277 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1278 | if (!obj->base.map_list.map) { |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 1279 | ret = drm_gem_create_mmap_offset(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1280 | if (ret) |
| 1281 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1282 | } |
| 1283 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1284 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1285 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1286 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1287 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1288 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1289 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1290 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1291 | } |
| 1292 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1293 | /** |
| 1294 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1295 | * @dev: DRM device |
| 1296 | * @data: GTT mapping ioctl data |
| 1297 | * @file: GEM object info |
| 1298 | * |
| 1299 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1300 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1301 | * up so we can get faults in the handler above. |
| 1302 | * |
| 1303 | * The fault handler will take care of binding the object into the GTT |
| 1304 | * (since it may have been evicted to make room for something), allocating |
| 1305 | * a fence register, and mapping the appropriate aperture address into |
| 1306 | * userspace. |
| 1307 | */ |
| 1308 | int |
| 1309 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1310 | struct drm_file *file) |
| 1311 | { |
| 1312 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1313 | |
| 1314 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1315 | return -ENODEV; |
| 1316 | |
| 1317 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1318 | } |
| 1319 | |
| 1320 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1321 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1322 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1323 | gfp_t gfpmask) |
| 1324 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1325 | int page_count, i; |
| 1326 | struct address_space *mapping; |
| 1327 | struct inode *inode; |
| 1328 | struct page *page; |
| 1329 | |
| 1330 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1331 | * at this point until we release them. |
| 1332 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1333 | page_count = obj->base.size / PAGE_SIZE; |
| 1334 | BUG_ON(obj->pages != NULL); |
| 1335 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1336 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1337 | return -ENOMEM; |
| 1338 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1339 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1340 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1341 | gfpmask |= mapping_gfp_mask(mapping); |
| 1342 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1343 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1344 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1345 | if (IS_ERR(page)) |
| 1346 | goto err_pages; |
| 1347 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1348 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1349 | } |
| 1350 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1351 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1352 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1353 | |
| 1354 | return 0; |
| 1355 | |
| 1356 | err_pages: |
| 1357 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1358 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1359 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1360 | drm_free_large(obj->pages); |
| 1361 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1362 | return PTR_ERR(page); |
| 1363 | } |
| 1364 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1365 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1366 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1367 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1368 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1369 | int i; |
| 1370 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1371 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1372 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1373 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1374 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1375 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1376 | if (obj->madv == I915_MADV_DONTNEED) |
| 1377 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1378 | |
| 1379 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1380 | if (obj->dirty) |
| 1381 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1382 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1383 | if (obj->madv == I915_MADV_WILLNEED) |
| 1384 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1385 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1386 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1387 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1388 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1389 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1390 | drm_free_large(obj->pages); |
| 1391 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1392 | } |
| 1393 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1394 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1395 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1396 | struct intel_ring_buffer *ring, |
| 1397 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1398 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1399 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1400 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1401 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1402 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1403 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1404 | |
| 1405 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1406 | if (!obj->active) { |
| 1407 | drm_gem_object_reference(&obj->base); |
| 1408 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1409 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1410 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1411 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1412 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1413 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1414 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1415 | obj->last_rendering_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1416 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1417 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1418 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1419 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1420 | /* Bump MRU to take account of the delayed flush */ |
| 1421 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1422 | struct drm_i915_fence_reg *reg; |
| 1423 | |
| 1424 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1425 | list_move_tail(®->lru_list, |
| 1426 | &dev_priv->mm.fence_list); |
| 1427 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1428 | } |
| 1429 | } |
| 1430 | |
| 1431 | static void |
| 1432 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1433 | { |
| 1434 | list_del_init(&obj->ring_list); |
| 1435 | obj->last_rendering_seqno = 0; |
Daniel Vetter | 15a13bb | 2012-04-12 01:27:57 +0200 | [diff] [blame] | 1436 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1437 | } |
| 1438 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1439 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1440 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1441 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1442 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1443 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1444 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1445 | BUG_ON(!obj->active); |
| 1446 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1447 | |
| 1448 | i915_gem_object_move_off_active(obj); |
| 1449 | } |
| 1450 | |
| 1451 | static void |
| 1452 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1453 | { |
| 1454 | struct drm_device *dev = obj->base.dev; |
| 1455 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1456 | |
| 1457 | if (obj->pin_count != 0) |
| 1458 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); |
| 1459 | else |
| 1460 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1461 | |
| 1462 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1463 | BUG_ON(!obj->active); |
| 1464 | obj->ring = NULL; |
| 1465 | |
| 1466 | i915_gem_object_move_off_active(obj); |
| 1467 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1468 | |
| 1469 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1470 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1471 | drm_gem_object_unreference(&obj->base); |
| 1472 | |
| 1473 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1474 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1475 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1476 | /* Immediately discard the backing storage */ |
| 1477 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1478 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1479 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1480 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1481 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1482 | /* Our goal here is to return as much of the memory as |
| 1483 | * is possible back to the system as we are called from OOM. |
| 1484 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1485 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1486 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1487 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1488 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1489 | |
Chris Wilson | a14917e | 2012-02-24 21:13:38 +0000 | [diff] [blame] | 1490 | if (obj->base.map_list.map) |
| 1491 | drm_gem_free_mmap_offset(&obj->base); |
| 1492 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1493 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1494 | } |
| 1495 | |
| 1496 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1497 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1498 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1499 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1500 | } |
| 1501 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1502 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1503 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1504 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1505 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1506 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1507 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1508 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1509 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1510 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1511 | if (obj->base.write_domain & flush_domains) { |
| 1512 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1513 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1514 | obj->base.write_domain = 0; |
| 1515 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1516 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1517 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1518 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1519 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1520 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1521 | old_write_domain); |
| 1522 | } |
| 1523 | } |
| 1524 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1525 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1526 | static u32 |
| 1527 | i915_gem_get_seqno(struct drm_device *dev) |
| 1528 | { |
| 1529 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1530 | u32 seqno = dev_priv->next_seqno; |
| 1531 | |
| 1532 | /* reserve 0 for non-seqno */ |
| 1533 | if (++dev_priv->next_seqno == 0) |
| 1534 | dev_priv->next_seqno = 1; |
| 1535 | |
| 1536 | return seqno; |
| 1537 | } |
| 1538 | |
| 1539 | u32 |
| 1540 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1541 | { |
| 1542 | if (ring->outstanding_lazy_request == 0) |
| 1543 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1544 | |
| 1545 | return ring->outstanding_lazy_request; |
| 1546 | } |
| 1547 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1548 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1549 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1550 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1551 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1552 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1553 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1554 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1555 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1556 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1557 | int ret; |
| 1558 | |
| 1559 | BUG_ON(request == NULL); |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1560 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1561 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1562 | /* Record the position of the start of the request so that |
| 1563 | * should we detect the updated seqno part-way through the |
| 1564 | * GPU processing the request, we never over-estimate the |
| 1565 | * position of the head. |
| 1566 | */ |
| 1567 | request_ring_position = intel_ring_get_tail(ring); |
| 1568 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1569 | ret = ring->add_request(ring, &seqno); |
| 1570 | if (ret) |
| 1571 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1572 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1573 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1574 | |
| 1575 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1576 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1577 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1578 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1579 | was_empty = list_empty(&ring->request_list); |
| 1580 | list_add_tail(&request->list, &ring->request_list); |
| 1581 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1582 | if (file) { |
| 1583 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1584 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1585 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1586 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1587 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1588 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1589 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1590 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1591 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 1592 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1593 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1594 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1595 | if (i915_enable_hangcheck) { |
| 1596 | mod_timer(&dev_priv->hangcheck_timer, |
| 1597 | jiffies + |
| 1598 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 1599 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1600 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1601 | queue_delayed_work(dev_priv->wq, |
| 1602 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1603 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1604 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1605 | } |
| 1606 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1607 | static inline void |
| 1608 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1610 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1611 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1612 | if (!file_priv) |
| 1613 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1614 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1615 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1616 | if (request->file_priv) { |
| 1617 | list_del(&request->client_list); |
| 1618 | request->file_priv = NULL; |
| 1619 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1620 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1621 | } |
| 1622 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1623 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1624 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1625 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1626 | while (!list_empty(&ring->request_list)) { |
| 1627 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1628 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1629 | request = list_first_entry(&ring->request_list, |
| 1630 | struct drm_i915_gem_request, |
| 1631 | list); |
| 1632 | |
| 1633 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1634 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1635 | kfree(request); |
| 1636 | } |
| 1637 | |
| 1638 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1639 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1640 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1641 | obj = list_first_entry(&ring->active_list, |
| 1642 | struct drm_i915_gem_object, |
| 1643 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1645 | obj->base.write_domain = 0; |
| 1646 | list_del_init(&obj->gpu_write_list); |
| 1647 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1648 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1649 | } |
| 1650 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1651 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1652 | { |
| 1653 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1654 | int i; |
| 1655 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1656 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1657 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1658 | struct drm_i915_gem_object *obj = reg->obj; |
| 1659 | |
| 1660 | if (!obj) |
| 1661 | continue; |
| 1662 | |
| 1663 | if (obj->tiling_mode) |
| 1664 | i915_gem_release_mmap(obj); |
| 1665 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1666 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
| 1667 | reg->obj->fenced_gpu_access = false; |
| 1668 | reg->obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1669 | i915_gem_clear_fence_reg(dev, reg); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1670 | } |
| 1671 | } |
| 1672 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1673 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1674 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1676 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1677 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1678 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1679 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 1680 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1681 | |
| 1682 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1683 | * to be lost on reset along with the data, so simply move the |
| 1684 | * lost bo to the inactive list. |
| 1685 | */ |
| 1686 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1687 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1688 | struct drm_i915_gem_object, |
| 1689 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1690 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1691 | obj->base.write_domain = 0; |
| 1692 | list_del_init(&obj->gpu_write_list); |
| 1693 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1694 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1695 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1696 | /* Move everything out of the GPU domains to ensure we do any |
| 1697 | * necessary invalidation upon reuse. |
| 1698 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1699 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1700 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1701 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1702 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1703 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1704 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1705 | |
| 1706 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1707 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1708 | } |
| 1709 | |
| 1710 | /** |
| 1711 | * This function clears the request list as sequence numbers are passed. |
| 1712 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1713 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1714 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1715 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1716 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1717 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1718 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1719 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1720 | return; |
| 1721 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1722 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1723 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1724 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1725 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1726 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1727 | if (seqno >= ring->sync_seqno[i]) |
| 1728 | ring->sync_seqno[i] = 0; |
| 1729 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1730 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1731 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1732 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1733 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1734 | struct drm_i915_gem_request, |
| 1735 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1736 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1737 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1738 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1739 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1740 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1741 | /* We know the GPU must have read the request to have |
| 1742 | * sent us the seqno + interrupt, so use the position |
| 1743 | * of tail of the request to update the last known position |
| 1744 | * of the GPU head. |
| 1745 | */ |
| 1746 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1747 | |
| 1748 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1749 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1750 | kfree(request); |
| 1751 | } |
| 1752 | |
| 1753 | /* Move any buffers on the active list that are no longer referenced |
| 1754 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1755 | */ |
| 1756 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1757 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1758 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1759 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1760 | struct drm_i915_gem_object, |
| 1761 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1762 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1763 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1764 | break; |
| 1765 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1766 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1767 | i915_gem_object_move_to_flushing(obj); |
| 1768 | else |
| 1769 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1770 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1771 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1772 | if (unlikely(ring->trace_irq_seqno && |
| 1773 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1774 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1775 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1776 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1777 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1778 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1779 | } |
| 1780 | |
| 1781 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1782 | i915_gem_retire_requests(struct drm_device *dev) |
| 1783 | { |
| 1784 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1785 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1786 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1787 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1788 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1789 | |
| 1790 | /* We must be careful that during unbind() we do not |
| 1791 | * accidentally infinitely recurse into retire requests. |
| 1792 | * Currently: |
| 1793 | * retire -> free -> unbind -> wait -> retire_ring |
| 1794 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1795 | list_for_each_entry_safe(obj, next, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1796 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1797 | mm_list) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1798 | i915_gem_free_object_tail(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 1799 | } |
| 1800 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1801 | for (i = 0; i < I915_NUM_RINGS; i++) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1802 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1803 | } |
| 1804 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1805 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1806 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1807 | { |
| 1808 | drm_i915_private_t *dev_priv; |
| 1809 | struct drm_device *dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1810 | bool idle; |
| 1811 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1812 | |
| 1813 | dev_priv = container_of(work, drm_i915_private_t, |
| 1814 | mm.retire_work.work); |
| 1815 | dev = dev_priv->dev; |
| 1816 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1817 | /* Come back later if the device is busy... */ |
| 1818 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1819 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1820 | return; |
| 1821 | } |
| 1822 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1823 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1824 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1825 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1826 | * objects indefinitely. |
| 1827 | */ |
| 1828 | idle = true; |
| 1829 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 1830 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; |
| 1831 | |
| 1832 | if (!list_empty(&ring->gpu_write_list)) { |
| 1833 | struct drm_i915_gem_request *request; |
| 1834 | int ret; |
| 1835 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1836 | ret = i915_gem_flush_ring(ring, |
| 1837 | 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1838 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1839 | if (ret || request == NULL || |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1840 | i915_add_request(ring, NULL, request)) |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1841 | kfree(request); |
| 1842 | } |
| 1843 | |
| 1844 | idle &= list_empty(&ring->request_list); |
| 1845 | } |
| 1846 | |
| 1847 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1848 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1849 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1850 | mutex_unlock(&dev->struct_mutex); |
| 1851 | } |
| 1852 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1853 | /** |
| 1854 | * Waits for a sequence number to be signaled, and cleans up the |
| 1855 | * request and object lists appropriately for that event. |
| 1856 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1857 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1858 | i915_wait_request(struct intel_ring_buffer *ring, |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1859 | uint32_t seqno, |
| 1860 | bool do_retire) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1861 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1862 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1863 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1864 | int ret = 0; |
| 1865 | |
| 1866 | BUG_ON(seqno == 0); |
| 1867 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1868 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 1869 | struct completion *x = &dev_priv->error_completion; |
| 1870 | bool recovery_complete; |
| 1871 | unsigned long flags; |
| 1872 | |
| 1873 | /* Give the error handler a chance to run. */ |
| 1874 | spin_lock_irqsave(&x->wait.lock, flags); |
| 1875 | recovery_complete = x->done > 0; |
| 1876 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 1877 | |
| 1878 | return recovery_complete ? -EIO : -EAGAIN; |
| 1879 | } |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1880 | |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 1881 | if (seqno == ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1882 | struct drm_i915_gem_request *request; |
| 1883 | |
| 1884 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1885 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1886 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1887 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1888 | ret = i915_add_request(ring, NULL, request); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1889 | if (ret) { |
| 1890 | kfree(request); |
| 1891 | return ret; |
| 1892 | } |
| 1893 | |
| 1894 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1895 | } |
| 1896 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1897 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1898 | if (HAS_PCH_SPLIT(ring->dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1899 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
Jesse Barnes | 23e3f9b | 2012-03-28 13:39:39 -0700 | [diff] [blame] | 1900 | else if (IS_VALLEYVIEW(ring->dev)) |
| 1901 | ier = I915_READ(GTIER) | I915_READ(VLV_IER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1902 | else |
| 1903 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1904 | if (!ier) { |
| 1905 | DRM_ERROR("something (likely vbetool) disabled " |
| 1906 | "interrupts, re-enabling\n"); |
Chris Wilson | f01c22f | 2011-06-28 11:48:51 +0100 | [diff] [blame] | 1907 | ring->dev->driver->irq_preinstall(ring->dev); |
| 1908 | ring->dev->driver->irq_postinstall(ring->dev); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1909 | } |
| 1910 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1911 | trace_i915_gem_request_wait_begin(ring, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1912 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1913 | ring->waiting_seqno = seqno; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1914 | if (ring->irq_get(ring)) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1915 | if (dev_priv->mm.interruptible) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1916 | ret = wait_event_interruptible(ring->irq_queue, |
| 1917 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1918 | || atomic_read(&dev_priv->mm.wedged)); |
| 1919 | else |
| 1920 | wait_event(ring->irq_queue, |
| 1921 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 1922 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1923 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1924 | ring->irq_put(ring); |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 1925 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 1926 | seqno) || |
| 1927 | atomic_read(&dev_priv->mm.wedged), 3000)) |
Chris Wilson | b5ba177 | 2010-12-14 12:17:15 +0000 | [diff] [blame] | 1928 | ret = -EBUSY; |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 1929 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1930 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1931 | trace_i915_gem_request_wait_end(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1932 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1933 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 1934 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1935 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1936 | /* Directly dispatch request retiring. While we have the work queue |
| 1937 | * to handle this, the waiter on a request often wants an associated |
| 1938 | * buffer to have made it to the inactive list, and we would need |
| 1939 | * a separate wait queue to handle that. |
| 1940 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1941 | if (ret == 0 && do_retire) |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1942 | i915_gem_retire_requests_ring(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1943 | |
| 1944 | return ret; |
| 1945 | } |
| 1946 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1947 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1948 | * Ensures that all rendering to the object has completed and the object is |
| 1949 | * safe to unbind from the GTT or access from the CPU. |
| 1950 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1951 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1952 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1953 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1954 | int ret; |
| 1955 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1956 | /* This function only exists to support waiting for existing rendering, |
| 1957 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1958 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1959 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1960 | |
| 1961 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1962 | * it. |
| 1963 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1964 | if (obj->active) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 1965 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
| 1966 | true); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1967 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1968 | return ret; |
| 1969 | } |
| 1970 | |
| 1971 | return 0; |
| 1972 | } |
| 1973 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 1974 | /** |
| 1975 | * i915_gem_object_sync - sync an object to a ring. |
| 1976 | * |
| 1977 | * @obj: object which may be in use on another ring. |
| 1978 | * @to: ring we wish to use the object on. May be NULL. |
| 1979 | * |
| 1980 | * This code is meant to abstract object synchronization with the GPU. |
| 1981 | * Calling with NULL implies synchronizing the object with the CPU |
| 1982 | * rather than a particular GPU ring. |
| 1983 | * |
| 1984 | * Returns 0 if successful, else propagates up the lower layer error. |
| 1985 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 1986 | int |
| 1987 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 1988 | struct intel_ring_buffer *to) |
| 1989 | { |
| 1990 | struct intel_ring_buffer *from = obj->ring; |
| 1991 | u32 seqno; |
| 1992 | int ret, idx; |
| 1993 | |
| 1994 | if (from == NULL || to == from) |
| 1995 | return 0; |
| 1996 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 1997 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 1998 | return i915_gem_object_wait_rendering(obj); |
| 1999 | |
| 2000 | idx = intel_ring_sync_index(from, to); |
| 2001 | |
| 2002 | seqno = obj->last_rendering_seqno; |
| 2003 | if (seqno <= from->sync_seqno[idx]) |
| 2004 | return 0; |
| 2005 | |
| 2006 | if (seqno == from->outstanding_lazy_request) { |
| 2007 | struct drm_i915_gem_request *request; |
| 2008 | |
| 2009 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2010 | if (request == NULL) |
| 2011 | return -ENOMEM; |
| 2012 | |
| 2013 | ret = i915_add_request(from, NULL, request); |
| 2014 | if (ret) { |
| 2015 | kfree(request); |
| 2016 | return ret; |
| 2017 | } |
| 2018 | |
| 2019 | seqno = request->seqno; |
| 2020 | } |
| 2021 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2022 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2023 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2024 | if (!ret) |
| 2025 | from->sync_seqno[idx] = seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2026 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2027 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2028 | } |
| 2029 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2030 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2031 | { |
| 2032 | u32 old_write_domain, old_read_domains; |
| 2033 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2034 | /* Act a barrier for all accesses through the GTT */ |
| 2035 | mb(); |
| 2036 | |
| 2037 | /* Force a pagefault for domain tracking on next user access */ |
| 2038 | i915_gem_release_mmap(obj); |
| 2039 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2040 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2041 | return; |
| 2042 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2043 | old_read_domains = obj->base.read_domains; |
| 2044 | old_write_domain = obj->base.write_domain; |
| 2045 | |
| 2046 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2047 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2048 | |
| 2049 | trace_i915_gem_object_change_domain(obj, |
| 2050 | old_read_domains, |
| 2051 | old_write_domain); |
| 2052 | } |
| 2053 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2054 | /** |
| 2055 | * Unbinds an object from the GTT aperture. |
| 2056 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2057 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2058 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2059 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2060 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2061 | int ret = 0; |
| 2062 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2063 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2064 | return 0; |
| 2065 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2066 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2067 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2068 | return -EINVAL; |
| 2069 | } |
| 2070 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2071 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2072 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2073 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2074 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2075 | * should be safe and we need to cleanup or else we might |
| 2076 | * cause memory corruption through use-after-free. |
| 2077 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2078 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2079 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2080 | |
| 2081 | /* Move the object to the CPU domain to ensure that |
| 2082 | * any possible CPU writes while it's not in the GTT |
| 2083 | * are flushed when we go to remap it. |
| 2084 | */ |
| 2085 | if (ret == 0) |
| 2086 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 2087 | if (ret == -ERESTARTSYS) |
| 2088 | return ret; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2089 | if (ret) { |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2090 | /* In the event of a disaster, abandon all caches and |
| 2091 | * hope for the best. |
| 2092 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2093 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2094 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2095 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2096 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2097 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2098 | ret = i915_gem_object_put_fence(obj); |
| 2099 | if (ret == -ERESTARTSYS) |
| 2100 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2101 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2102 | trace_i915_gem_object_unbind(obj); |
| 2103 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2104 | if (obj->has_global_gtt_mapping) |
| 2105 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2106 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2107 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2108 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2109 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2110 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2111 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2112 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2113 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2114 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2115 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2116 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2117 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2118 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2119 | drm_mm_put_block(obj->gtt_space); |
| 2120 | obj->gtt_space = NULL; |
| 2121 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2122 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2123 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2124 | i915_gem_object_truncate(obj); |
| 2125 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2126 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | } |
| 2128 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2129 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2130 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2131 | uint32_t invalidate_domains, |
| 2132 | uint32_t flush_domains) |
| 2133 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2134 | int ret; |
| 2135 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2136 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2137 | return 0; |
| 2138 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2139 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2140 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2141 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2142 | if (ret) |
| 2143 | return ret; |
| 2144 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2145 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2146 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2147 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2148 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2149 | } |
| 2150 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2151 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2152 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2153 | int ret; |
| 2154 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2155 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2156 | return 0; |
| 2157 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2158 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2159 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2160 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2161 | if (ret) |
| 2162 | return ret; |
| 2163 | } |
| 2164 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2165 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
| 2166 | do_retire); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2167 | } |
| 2168 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2169 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2170 | { |
| 2171 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2172 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2173 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2174 | /* Flush everything onto the inactive list. */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2175 | for (i = 0; i < I915_NUM_RINGS; i++) { |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 2176 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2177 | if (ret) |
| 2178 | return ret; |
| 2179 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2180 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2181 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2182 | } |
| 2183 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2184 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
| 2185 | struct drm_i915_gem_object *obj) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2186 | { |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2187 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2188 | uint64_t val; |
| 2189 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2190 | if (obj) { |
| 2191 | u32 size = obj->gtt_space->size; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2192 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2193 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2194 | 0xfffff000) << 32; |
| 2195 | val |= obj->gtt_offset & 0xfffff000; |
| 2196 | val |= (uint64_t)((obj->stride / 128) - 1) << |
| 2197 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2198 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2199 | if (obj->tiling_mode == I915_TILING_Y) |
| 2200 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2201 | val |= I965_FENCE_REG_VALID; |
| 2202 | } else |
| 2203 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2204 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2205 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
| 2206 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2207 | } |
| 2208 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2209 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2210 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2211 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2212 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2213 | uint64_t val; |
| 2214 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2215 | if (obj) { |
| 2216 | u32 size = obj->gtt_space->size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2217 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2218 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2219 | 0xfffff000) << 32; |
| 2220 | val |= obj->gtt_offset & 0xfffff000; |
| 2221 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2222 | if (obj->tiling_mode == I915_TILING_Y) |
| 2223 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2224 | val |= I965_FENCE_REG_VALID; |
| 2225 | } else |
| 2226 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2227 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2228 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
| 2229 | POSTING_READ(FENCE_REG_965_0 + reg * 8); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2230 | } |
| 2231 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2232 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2233 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2234 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2235 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2236 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2237 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2238 | if (obj) { |
| 2239 | u32 size = obj->gtt_space->size; |
| 2240 | int pitch_val; |
| 2241 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2242 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2243 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2244 | (size & -size) != size || |
| 2245 | (obj->gtt_offset & (size - 1)), |
| 2246 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2247 | obj->gtt_offset, obj->map_and_fenceable, size); |
| 2248 | |
| 2249 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2250 | tile_width = 128; |
| 2251 | else |
| 2252 | tile_width = 512; |
| 2253 | |
| 2254 | /* Note: pitch better be a power of two tile widths */ |
| 2255 | pitch_val = obj->stride / tile_width; |
| 2256 | pitch_val = ffs(pitch_val) - 1; |
| 2257 | |
| 2258 | val = obj->gtt_offset; |
| 2259 | if (obj->tiling_mode == I915_TILING_Y) |
| 2260 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2261 | val |= I915_FENCE_SIZE_BITS(size); |
| 2262 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2263 | val |= I830_FENCE_REG_VALID; |
| 2264 | } else |
| 2265 | val = 0; |
| 2266 | |
| 2267 | if (reg < 8) |
| 2268 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2269 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2270 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2271 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2272 | I915_WRITE(reg, val); |
| 2273 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2274 | } |
| 2275 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2276 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2277 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2278 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2279 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2280 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2281 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2282 | if (obj) { |
| 2283 | u32 size = obj->gtt_space->size; |
| 2284 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2285 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2286 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2287 | (size & -size) != size || |
| 2288 | (obj->gtt_offset & (size - 1)), |
| 2289 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2290 | obj->gtt_offset, size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2291 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2292 | pitch_val = obj->stride / 128; |
| 2293 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2294 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2295 | val = obj->gtt_offset; |
| 2296 | if (obj->tiling_mode == I915_TILING_Y) |
| 2297 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2298 | val |= I830_FENCE_SIZE_BITS(size); |
| 2299 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2300 | val |= I830_FENCE_REG_VALID; |
| 2301 | } else |
| 2302 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2303 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2304 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2305 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2306 | } |
| 2307 | |
| 2308 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2309 | struct drm_i915_gem_object *obj) |
| 2310 | { |
| 2311 | switch (INTEL_INFO(dev)->gen) { |
| 2312 | case 7: |
| 2313 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; |
| 2314 | case 5: |
| 2315 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2316 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2317 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
| 2318 | default: break; |
| 2319 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2320 | } |
| 2321 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 2322 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2323 | struct drm_i915_fence_reg *fence) |
| 2324 | { |
| 2325 | return fence - dev_priv->fence_regs; |
| 2326 | } |
| 2327 | |
| 2328 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2329 | struct drm_i915_fence_reg *fence, |
| 2330 | bool enable) |
| 2331 | { |
| 2332 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2333 | int reg = fence_number(dev_priv, fence); |
| 2334 | |
| 2335 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 2336 | |
| 2337 | if (enable) { |
| 2338 | obj->fence_reg = reg; |
| 2339 | fence->obj = obj; |
| 2340 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2341 | } else { |
| 2342 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2343 | fence->obj = NULL; |
| 2344 | list_del_init(&fence->lru_list); |
| 2345 | } |
| 2346 | } |
| 2347 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2348 | static int |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2349 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2350 | { |
| 2351 | int ret; |
| 2352 | |
| 2353 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2354 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2355 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2356 | 0, obj->base.write_domain); |
| 2357 | if (ret) |
| 2358 | return ret; |
| 2359 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2360 | |
| 2361 | obj->fenced_gpu_access = false; |
| 2362 | } |
| 2363 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2364 | if (obj->last_fenced_seqno) { |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2365 | ret = i915_wait_request(obj->ring, |
| 2366 | obj->last_fenced_seqno, |
| 2367 | true); |
| 2368 | if (ret) |
| 2369 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2370 | |
| 2371 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2372 | } |
| 2373 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2374 | /* Ensure that all CPU reads are completed before installing a fence |
| 2375 | * and all writes before removing the fence. |
| 2376 | */ |
| 2377 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2378 | mb(); |
| 2379 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2380 | return 0; |
| 2381 | } |
| 2382 | |
| 2383 | int |
| 2384 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2385 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 2386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2387 | int ret; |
| 2388 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2389 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2390 | if (ret) |
| 2391 | return ret; |
| 2392 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 2393 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2394 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2395 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame^] | 2396 | i915_gem_object_update_fence(obj, |
| 2397 | &dev_priv->fence_regs[obj->fence_reg], |
| 2398 | false); |
| 2399 | i915_gem_object_fence_lost(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2400 | |
| 2401 | return 0; |
| 2402 | } |
| 2403 | |
| 2404 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2405 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2406 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2407 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2408 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2409 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2410 | |
| 2411 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2412 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2413 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2414 | reg = &dev_priv->fence_regs[i]; |
| 2415 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2416 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2417 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2418 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2419 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2420 | } |
| 2421 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2422 | if (avail == NULL) |
| 2423 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2424 | |
| 2425 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2426 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2427 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2428 | continue; |
| 2429 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2430 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2431 | } |
| 2432 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2433 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2434 | } |
| 2435 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2436 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2437 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2438 | * @obj: object to map through a fence reg |
| 2439 | * |
| 2440 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2441 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2442 | * This function walks the fence regs looking for a free one for @obj, |
| 2443 | * stealing one if it can't find any. |
| 2444 | * |
| 2445 | * It then sets up the reg based on the object's properties: address, pitch |
| 2446 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2447 | * |
| 2448 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2449 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2450 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2451 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2452 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2453 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2455 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2456 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2457 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2458 | if (obj->tiling_mode == I915_TILING_NONE) |
| 2459 | return i915_gem_object_put_fence(obj); |
| 2460 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2461 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2462 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2463 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2464 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2465 | |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2466 | if (obj->tiling_changed) { |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2467 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2468 | if (ret) |
| 2469 | return ret; |
| 2470 | |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2471 | goto update; |
| 2472 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2473 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2474 | return 0; |
| 2475 | } |
| 2476 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2477 | reg = i915_find_fence_reg(dev); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2478 | if (reg == NULL) |
Daniel Vetter | 39965b3 | 2011-12-14 13:57:09 +0100 | [diff] [blame] | 2479 | return -EDEADLK; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2480 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2481 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2482 | if (ret) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2483 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2484 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2485 | if (reg->obj) { |
| 2486 | struct drm_i915_gem_object *old = reg->obj; |
| 2487 | |
| 2488 | drm_gem_object_reference(&old->base); |
| 2489 | |
| 2490 | if (old->tiling_mode) |
| 2491 | i915_gem_release_mmap(old); |
| 2492 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2493 | ret = i915_gem_object_flush_fence(old); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2494 | if (ret) { |
| 2495 | drm_gem_object_unreference(&old->base); |
| 2496 | return ret; |
| 2497 | } |
| 2498 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2499 | old->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2500 | old->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2501 | |
| 2502 | drm_gem_object_unreference(&old->base); |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2503 | } |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2504 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2505 | reg->obj = obj; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2506 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
| 2507 | obj->fence_reg = reg - dev_priv->fence_regs; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2508 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2509 | update: |
| 2510 | obj->tiling_changed = false; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2511 | i915_gem_write_fence(dev, reg - dev_priv->fence_regs, obj); |
| 2512 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2513 | } |
| 2514 | |
| 2515 | /** |
| 2516 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2517 | * @obj: object to clear |
| 2518 | * |
| 2519 | * Zeroes out the fence register itself and clears out the associated |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2520 | * data structures in dev_priv and obj. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2521 | */ |
| 2522 | static void |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2523 | i915_gem_clear_fence_reg(struct drm_device *dev, |
| 2524 | struct drm_i915_fence_reg *reg) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2525 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2526 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2527 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2528 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2529 | switch (INTEL_INFO(dev)->gen) { |
Eric Anholt | 25aebfc3 | 2011-05-06 13:55:53 -0700 | [diff] [blame] | 2530 | case 7: |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2531 | case 6: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2532 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2533 | break; |
| 2534 | case 5: |
| 2535 | case 4: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2536 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2537 | break; |
| 2538 | case 3: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2539 | if (fence_reg >= 8) |
| 2540 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2541 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2542 | case 2: |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2543 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2544 | |
| 2545 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2546 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2547 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2548 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2549 | list_del_init(®->lru_list); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2550 | reg->obj = NULL; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2551 | reg->pin_count = 0; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2552 | } |
| 2553 | |
| 2554 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2555 | * Finds free space in the GTT aperture and binds the object there. |
| 2556 | */ |
| 2557 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2558 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2559 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2560 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2561 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2562 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2563 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2564 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2565 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2566 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2567 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2568 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2569 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2570 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2571 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2572 | return -EINVAL; |
| 2573 | } |
| 2574 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2575 | fence_size = i915_gem_get_gtt_size(dev, |
| 2576 | obj->base.size, |
| 2577 | obj->tiling_mode); |
| 2578 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2579 | obj->base.size, |
| 2580 | obj->tiling_mode); |
| 2581 | unfenced_alignment = |
| 2582 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2583 | obj->base.size, |
| 2584 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2585 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2586 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2587 | alignment = map_and_fenceable ? fence_alignment : |
| 2588 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2589 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2590 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2591 | return -EINVAL; |
| 2592 | } |
| 2593 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2594 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2595 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2596 | /* If the object is bigger than the entire aperture, reject it early |
| 2597 | * before evicting everything in a vain attempt to find space. |
| 2598 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2599 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2600 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2601 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2602 | return -E2BIG; |
| 2603 | } |
| 2604 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2605 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2606 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2607 | free_space = |
| 2608 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2609 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2610 | dev_priv->mm.gtt_mappable_end, |
| 2611 | 0); |
| 2612 | else |
| 2613 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2614 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2615 | |
| 2616 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2617 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2618 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2619 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2620 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2621 | dev_priv->mm.gtt_mappable_end, |
| 2622 | 0); |
| 2623 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2624 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2625 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2626 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2627 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2628 | /* If the gtt is empty and we're still having trouble |
| 2629 | * fitting our object in, we're out of memory. |
| 2630 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2631 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2632 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2633 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2634 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2635 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2636 | goto search_free; |
| 2637 | } |
| 2638 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2639 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2640 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2641 | drm_mm_put_block(obj->gtt_space); |
| 2642 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2643 | |
| 2644 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2645 | /* first try to reclaim some memory by clearing the GTT */ |
| 2646 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2647 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2648 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2649 | if (gfpmask) { |
| 2650 | gfpmask = 0; |
| 2651 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2652 | } |
| 2653 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2654 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2655 | } |
| 2656 | |
| 2657 | goto search_free; |
| 2658 | } |
| 2659 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | return ret; |
| 2661 | } |
| 2662 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2663 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2664 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2665 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2666 | drm_mm_put_block(obj->gtt_space); |
| 2667 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2668 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2669 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2670 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2671 | |
| 2672 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2673 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2674 | |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2675 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2676 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2677 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2678 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2679 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2680 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2681 | /* Assert that the object is not currently in any GPU domain. As it |
| 2682 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2683 | * a GPU cache |
| 2684 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2685 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2686 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2687 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2688 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2689 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2690 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2691 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2692 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2693 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2694 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2695 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2696 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2697 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2698 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2699 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2700 | return 0; |
| 2701 | } |
| 2702 | |
| 2703 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2704 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2705 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2706 | /* If we don't have a page list set up, then we're not pinned |
| 2707 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2708 | * again at bind time. |
| 2709 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2710 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2711 | return; |
| 2712 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2713 | /* If the GPU is snooping the contents of the CPU cache, |
| 2714 | * we do not need to manually clear the CPU cache lines. However, |
| 2715 | * the caches are only snooped when the render cache is |
| 2716 | * flushed/invalidated. As we always have to emit invalidations |
| 2717 | * and flushes when moving into and out of the RENDER domain, correct |
| 2718 | * snooping behaviour occurs naturally as the result of our domain |
| 2719 | * tracking. |
| 2720 | */ |
| 2721 | if (obj->cache_level != I915_CACHE_NONE) |
| 2722 | return; |
| 2723 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2724 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2725 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2726 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | } |
| 2728 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2729 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2730 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2731 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2732 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2733 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2734 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2735 | |
| 2736 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2737 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2738 | } |
| 2739 | |
| 2740 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2741 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2742 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2743 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2744 | uint32_t old_write_domain; |
| 2745 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2746 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2747 | return; |
| 2748 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2749 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2750 | * to it immediately go to main memory as far as we know, so there's |
| 2751 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2752 | * |
| 2753 | * However, we do have to enforce the order so that all writes through |
| 2754 | * the GTT land before any writes to the device, such as updates to |
| 2755 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2756 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2757 | wmb(); |
| 2758 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2759 | old_write_domain = obj->base.write_domain; |
| 2760 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2761 | |
| 2762 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2763 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2764 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2765 | } |
| 2766 | |
| 2767 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2768 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2769 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2770 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2771 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2772 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2773 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2774 | return; |
| 2775 | |
| 2776 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2777 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2778 | old_write_domain = obj->base.write_domain; |
| 2779 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2780 | |
| 2781 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2782 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2783 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2784 | } |
| 2785 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2786 | /** |
| 2787 | * Moves a single object to the GTT read, and possibly write domain. |
| 2788 | * |
| 2789 | * This function returns when the move is complete, including waiting on |
| 2790 | * flushes to occur. |
| 2791 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2792 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2793 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2794 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2795 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2796 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2797 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2798 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2799 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2800 | return -EINVAL; |
| 2801 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2802 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2803 | return 0; |
| 2804 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2805 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2806 | if (ret) |
| 2807 | return ret; |
| 2808 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2809 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2810 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2811 | if (ret) |
| 2812 | return ret; |
| 2813 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2814 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2815 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2816 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2817 | old_write_domain = obj->base.write_domain; |
| 2818 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2819 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2820 | /* It should now be out of any other write domains, and we can update |
| 2821 | * the domain values for our changes. |
| 2822 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2823 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2824 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2825 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2826 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2827 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2828 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2829 | } |
| 2830 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2831 | trace_i915_gem_object_change_domain(obj, |
| 2832 | old_read_domains, |
| 2833 | old_write_domain); |
| 2834 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2835 | return 0; |
| 2836 | } |
| 2837 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2838 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2839 | enum i915_cache_level cache_level) |
| 2840 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2841 | struct drm_device *dev = obj->base.dev; |
| 2842 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2843 | int ret; |
| 2844 | |
| 2845 | if (obj->cache_level == cache_level) |
| 2846 | return 0; |
| 2847 | |
| 2848 | if (obj->pin_count) { |
| 2849 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 2850 | return -EBUSY; |
| 2851 | } |
| 2852 | |
| 2853 | if (obj->gtt_space) { |
| 2854 | ret = i915_gem_object_finish_gpu(obj); |
| 2855 | if (ret) |
| 2856 | return ret; |
| 2857 | |
| 2858 | i915_gem_object_finish_gtt(obj); |
| 2859 | |
| 2860 | /* Before SandyBridge, you could not use tiling or fence |
| 2861 | * registers with snooped memory, so relinquish any fences |
| 2862 | * currently pointing to our region in the aperture. |
| 2863 | */ |
| 2864 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
| 2865 | ret = i915_gem_object_put_fence(obj); |
| 2866 | if (ret) |
| 2867 | return ret; |
| 2868 | } |
| 2869 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2870 | if (obj->has_global_gtt_mapping) |
| 2871 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2872 | if (obj->has_aliasing_ppgtt_mapping) |
| 2873 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 2874 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2875 | } |
| 2876 | |
| 2877 | if (cache_level == I915_CACHE_NONE) { |
| 2878 | u32 old_read_domains, old_write_domain; |
| 2879 | |
| 2880 | /* If we're coming from LLC cached, then we haven't |
| 2881 | * actually been tracking whether the data is in the |
| 2882 | * CPU cache or not, since we only allow one bit set |
| 2883 | * in obj->write_domain and have been skipping the clflushes. |
| 2884 | * Just set it to the CPU cache for now. |
| 2885 | */ |
| 2886 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 2887 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 2888 | |
| 2889 | old_read_domains = obj->base.read_domains; |
| 2890 | old_write_domain = obj->base.write_domain; |
| 2891 | |
| 2892 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 2893 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2894 | |
| 2895 | trace_i915_gem_object_change_domain(obj, |
| 2896 | old_read_domains, |
| 2897 | old_write_domain); |
| 2898 | } |
| 2899 | |
| 2900 | obj->cache_level = cache_level; |
| 2901 | return 0; |
| 2902 | } |
| 2903 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2904 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2905 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 2906 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 2907 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2908 | */ |
| 2909 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2910 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2911 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2912 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2913 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2914 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2915 | int ret; |
| 2916 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2917 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2918 | if (ret) |
| 2919 | return ret; |
| 2920 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 2921 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2922 | ret = i915_gem_object_sync(obj, pipelined); |
| 2923 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2924 | return ret; |
| 2925 | } |
| 2926 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 2927 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 2928 | * a result, we make sure that the pinning that is about to occur is |
| 2929 | * done with uncached PTEs. This is lowest common denominator for all |
| 2930 | * chipsets. |
| 2931 | * |
| 2932 | * However for gen6+, we could do better by using the GFDT bit instead |
| 2933 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 2934 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 2935 | */ |
| 2936 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 2937 | if (ret) |
| 2938 | return ret; |
| 2939 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2940 | /* As the user may map the buffer once pinned in the display plane |
| 2941 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 2942 | * always use map_and_fenceable for all scanout buffers. |
| 2943 | */ |
| 2944 | ret = i915_gem_object_pin(obj, alignment, true); |
| 2945 | if (ret) |
| 2946 | return ret; |
| 2947 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2948 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2949 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2950 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2951 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2952 | |
| 2953 | /* It should now be out of any other write domains, and we can update |
| 2954 | * the domain values for our changes. |
| 2955 | */ |
| 2956 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2957 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2958 | |
| 2959 | trace_i915_gem_object_change_domain(obj, |
| 2960 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2961 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2962 | |
| 2963 | return 0; |
| 2964 | } |
| 2965 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2966 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2967 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2968 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2969 | int ret; |
| 2970 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2971 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2972 | return 0; |
| 2973 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2974 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2975 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2976 | if (ret) |
| 2977 | return ret; |
| 2978 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2979 | |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 2980 | ret = i915_gem_object_wait_rendering(obj); |
| 2981 | if (ret) |
| 2982 | return ret; |
| 2983 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2984 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 2985 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 2986 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 2987 | } |
| 2988 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2989 | /** |
| 2990 | * Moves a single object to the CPU read, and possibly write domain. |
| 2991 | * |
| 2992 | * This function returns when the move is complete, including waiting on |
| 2993 | * flushes to occur. |
| 2994 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2995 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2996 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2997 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2998 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2999 | int ret; |
| 3000 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3001 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3002 | return 0; |
| 3003 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3004 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3005 | if (ret) |
| 3006 | return ret; |
| 3007 | |
Chris Wilson | f841319 | 2012-04-10 11:52:50 +0100 | [diff] [blame] | 3008 | if (write || obj->pending_gpu_write) { |
| 3009 | ret = i915_gem_object_wait_rendering(obj); |
| 3010 | if (ret) |
| 3011 | return ret; |
| 3012 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3013 | |
| 3014 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3015 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3016 | old_write_domain = obj->base.write_domain; |
| 3017 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3018 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3019 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3020 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3021 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3022 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3023 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3024 | } |
| 3025 | |
| 3026 | /* It should now be out of any other write domains, and we can update |
| 3027 | * the domain values for our changes. |
| 3028 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3029 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3030 | |
| 3031 | /* If we're writing through the CPU, then the GPU read domains will |
| 3032 | * need to be invalidated at next use. |
| 3033 | */ |
| 3034 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3035 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3036 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3037 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3038 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3039 | trace_i915_gem_object_change_domain(obj, |
| 3040 | old_read_domains, |
| 3041 | old_write_domain); |
| 3042 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3043 | return 0; |
| 3044 | } |
| 3045 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3046 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3047 | * emitted over 20 msec ago. |
| 3048 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3049 | * Note that if we were to use the current jiffies each time around the loop, |
| 3050 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3051 | * render a frame was over 20ms. |
| 3052 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3053 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3054 | * relatively low latency when blocking on a particular request to finish. |
| 3055 | */ |
| 3056 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3057 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3058 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3059 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3060 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3061 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3062 | struct drm_i915_gem_request *request; |
| 3063 | struct intel_ring_buffer *ring = NULL; |
| 3064 | u32 seqno = 0; |
| 3065 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3066 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3067 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3068 | return -EIO; |
| 3069 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3070 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3071 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3072 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3073 | break; |
| 3074 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3075 | ring = request->ring; |
| 3076 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3077 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3078 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3079 | |
| 3080 | if (seqno == 0) |
| 3081 | return 0; |
| 3082 | |
| 3083 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3084 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3085 | /* And wait for the seqno passing without holding any locks and |
| 3086 | * causing extra latency for others. This is safe as the irq |
| 3087 | * generation is designed to be run atomically and so is |
| 3088 | * lockless. |
| 3089 | */ |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3090 | if (ring->irq_get(ring)) { |
| 3091 | ret = wait_event_interruptible(ring->irq_queue, |
| 3092 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
| 3093 | || atomic_read(&dev_priv->mm.wedged)); |
| 3094 | ring->irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3095 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3096 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3097 | ret = -EIO; |
Eric Anholt | e959b5d | 2011-12-22 14:55:01 -0800 | [diff] [blame] | 3098 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
| 3099 | seqno) || |
Eric Anholt | 7ea29b1 | 2011-12-22 14:54:59 -0800 | [diff] [blame] | 3100 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
| 3101 | ret = -EBUSY; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 3102 | } |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3103 | } |
| 3104 | |
| 3105 | if (ret == 0) |
| 3106 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3107 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3108 | return ret; |
| 3109 | } |
| 3110 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3111 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3112 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3113 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3114 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3115 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3116 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3117 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3118 | int ret; |
| 3119 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3120 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3121 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3122 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3123 | if (obj->gtt_space != NULL) { |
| 3124 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3125 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3126 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3127 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3128 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3129 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3130 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3131 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3132 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3133 | ret = i915_gem_object_unbind(obj); |
| 3134 | if (ret) |
| 3135 | return ret; |
| 3136 | } |
| 3137 | } |
| 3138 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3139 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3140 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3141 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3142 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3143 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3144 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3145 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3146 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3147 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3148 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3149 | if (obj->pin_count++ == 0) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3150 | if (!obj->active) |
| 3151 | list_move_tail(&obj->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3152 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3153 | } |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3154 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3155 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3156 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3157 | return 0; |
| 3158 | } |
| 3159 | |
| 3160 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3161 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3162 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3163 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3164 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3165 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3166 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3167 | BUG_ON(obj->pin_count == 0); |
| 3168 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3169 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3170 | if (--obj->pin_count == 0) { |
| 3171 | if (!obj->active) |
| 3172 | list_move_tail(&obj->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3173 | &dev_priv->mm.inactive_list); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3174 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3175 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 3176 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3177 | } |
| 3178 | |
| 3179 | int |
| 3180 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3181 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3182 | { |
| 3183 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3184 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3185 | int ret; |
| 3186 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3187 | ret = i915_mutex_lock_interruptible(dev); |
| 3188 | if (ret) |
| 3189 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3190 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3191 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3192 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3193 | ret = -ENOENT; |
| 3194 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3195 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3196 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3197 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3198 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3199 | ret = -EINVAL; |
| 3200 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3201 | } |
| 3202 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3203 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3204 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3205 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3206 | ret = -EINVAL; |
| 3207 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3208 | } |
| 3209 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3210 | obj->user_pin_count++; |
| 3211 | obj->pin_filp = file; |
| 3212 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3213 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3214 | if (ret) |
| 3215 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3216 | } |
| 3217 | |
| 3218 | /* XXX - flush the CPU caches for pinned objects |
| 3219 | * as the X server doesn't manage domains yet |
| 3220 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3221 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3222 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3223 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3224 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3225 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3226 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3227 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3228 | } |
| 3229 | |
| 3230 | int |
| 3231 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3232 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3233 | { |
| 3234 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3235 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3236 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3237 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3238 | ret = i915_mutex_lock_interruptible(dev); |
| 3239 | if (ret) |
| 3240 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3241 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3242 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3243 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3244 | ret = -ENOENT; |
| 3245 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3246 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3247 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3248 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3249 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3250 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3251 | ret = -EINVAL; |
| 3252 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3253 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3254 | obj->user_pin_count--; |
| 3255 | if (obj->user_pin_count == 0) { |
| 3256 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3257 | i915_gem_object_unpin(obj); |
| 3258 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3259 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3260 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3261 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3262 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3263 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3264 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3265 | } |
| 3266 | |
| 3267 | int |
| 3268 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3269 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3270 | { |
| 3271 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3272 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3273 | int ret; |
| 3274 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3275 | ret = i915_mutex_lock_interruptible(dev); |
| 3276 | if (ret) |
| 3277 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3278 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3279 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3280 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3281 | ret = -ENOENT; |
| 3282 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3283 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3284 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3285 | /* Count all active objects as busy, even if they are currently not used |
| 3286 | * by the gpu. Users of this interface expect objects to eventually |
| 3287 | * become non-busy without any further actions, therefore emit any |
| 3288 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3289 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3290 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3291 | if (args->busy) { |
| 3292 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3293 | * object. Userspace calling this function indicates that it wants to |
| 3294 | * use this buffer rather sooner than later, so issuing the required |
| 3295 | * flush earlier is beneficial. |
| 3296 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3297 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3298 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3299 | 0, obj->base.write_domain); |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3300 | } else if (obj->ring->outstanding_lazy_request == |
| 3301 | obj->last_rendering_seqno) { |
| 3302 | struct drm_i915_gem_request *request; |
| 3303 | |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3304 | /* This ring is not being cleared by active usage, |
| 3305 | * so emit a request to do so. |
| 3306 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3307 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3308 | if (request) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3309 | ret = i915_add_request(obj->ring, NULL, request); |
Rakib Mullick | 457eafc | 2011-11-16 00:49:28 +0600 | [diff] [blame] | 3310 | if (ret) |
| 3311 | kfree(request); |
| 3312 | } else |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3313 | ret = -ENOMEM; |
| 3314 | } |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3315 | |
| 3316 | /* Update the active list for the hardware's current position. |
| 3317 | * Otherwise this only updates on a delayed timer or when irqs |
| 3318 | * are actually unmasked, and our working set ends up being |
| 3319 | * larger than required. |
| 3320 | */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3321 | i915_gem_retire_requests_ring(obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3322 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3323 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3324 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3325 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3326 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3327 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3328 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3329 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3330 | } |
| 3331 | |
| 3332 | int |
| 3333 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3334 | struct drm_file *file_priv) |
| 3335 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3336 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3337 | } |
| 3338 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3339 | int |
| 3340 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3341 | struct drm_file *file_priv) |
| 3342 | { |
| 3343 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3344 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3345 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3346 | |
| 3347 | switch (args->madv) { |
| 3348 | case I915_MADV_DONTNEED: |
| 3349 | case I915_MADV_WILLNEED: |
| 3350 | break; |
| 3351 | default: |
| 3352 | return -EINVAL; |
| 3353 | } |
| 3354 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3355 | ret = i915_mutex_lock_interruptible(dev); |
| 3356 | if (ret) |
| 3357 | return ret; |
| 3358 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3359 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3360 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3361 | ret = -ENOENT; |
| 3362 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3363 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3364 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3365 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3366 | ret = -EINVAL; |
| 3367 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3368 | } |
| 3369 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3370 | if (obj->madv != __I915_MADV_PURGED) |
| 3371 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3372 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3373 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3374 | if (i915_gem_object_is_purgeable(obj) && |
| 3375 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3376 | i915_gem_object_truncate(obj); |
| 3377 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3378 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3379 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3380 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3381 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3382 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3383 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3384 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3385 | } |
| 3386 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3387 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3388 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3389 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3390 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3391 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3392 | struct address_space *mapping; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3393 | |
| 3394 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3395 | if (obj == NULL) |
| 3396 | return NULL; |
| 3397 | |
| 3398 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3399 | kfree(obj); |
| 3400 | return NULL; |
| 3401 | } |
| 3402 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3403 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 3404 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3405 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3406 | i915_gem_info_add_obj(dev_priv, size); |
| 3407 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3408 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3409 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3410 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3411 | if (HAS_LLC(dev)) { |
| 3412 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3413 | * cache) for about a 10% performance improvement |
| 3414 | * compared to uncached. Graphics requests other than |
| 3415 | * display scanout are coherent with the CPU in |
| 3416 | * accessing this cache. This means in this mode we |
| 3417 | * don't need to clflush on the CPU side, and on the |
| 3418 | * GPU side we only need to flush internal caches to |
| 3419 | * get data visible to the CPU. |
| 3420 | * |
| 3421 | * However, we maintain the display planes as UC, and so |
| 3422 | * need to rebind when first used as such. |
| 3423 | */ |
| 3424 | obj->cache_level = I915_CACHE_LLC; |
| 3425 | } else |
| 3426 | obj->cache_level = I915_CACHE_NONE; |
| 3427 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3428 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3429 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3430 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3431 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3432 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3433 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3434 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3435 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3436 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3437 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3438 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3439 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3440 | } |
| 3441 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3442 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3443 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3444 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3445 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3446 | return 0; |
| 3447 | } |
| 3448 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3449 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3450 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3451 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3452 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3453 | int ret; |
| 3454 | |
| 3455 | ret = i915_gem_object_unbind(obj); |
| 3456 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3457 | list_move(&obj->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3458 | &dev_priv->mm.deferred_free_list); |
| 3459 | return; |
| 3460 | } |
| 3461 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3462 | trace_i915_gem_object_destroy(obj); |
| 3463 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3464 | if (obj->base.map_list.map) |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 3465 | drm_gem_free_mmap_offset(&obj->base); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3466 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3467 | drm_gem_object_release(&obj->base); |
| 3468 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3469 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3470 | kfree(obj->bit_17); |
| 3471 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3472 | } |
| 3473 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3474 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3475 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3476 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
| 3477 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3478 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3479 | while (obj->pin_count > 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3480 | i915_gem_object_unpin(obj); |
| 3481 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3482 | if (obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3483 | i915_gem_detach_phys_object(dev, obj); |
| 3484 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3485 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3486 | } |
| 3487 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3488 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3489 | i915_gem_idle(struct drm_device *dev) |
| 3490 | { |
| 3491 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3492 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3493 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3494 | mutex_lock(&dev->struct_mutex); |
| 3495 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3496 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3497 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3498 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3499 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3500 | |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 3501 | ret = i915_gpu_idle(dev, true); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3502 | if (ret) { |
| 3503 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3504 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3505 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3506 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3507 | /* Under UMS, be paranoid and evict. */ |
| 3508 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | 5eac3ab | 2010-10-31 08:49:47 +0000 | [diff] [blame] | 3509 | ret = i915_gem_evict_inactive(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3510 | if (ret) { |
| 3511 | mutex_unlock(&dev->struct_mutex); |
| 3512 | return ret; |
| 3513 | } |
| 3514 | } |
| 3515 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3516 | i915_gem_reset_fences(dev); |
| 3517 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3518 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3519 | * We need to replace this with a semaphore, or something. |
| 3520 | * And not confound mm.suspended! |
| 3521 | */ |
| 3522 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3523 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3524 | |
| 3525 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3526 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3527 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3528 | mutex_unlock(&dev->struct_mutex); |
| 3529 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3530 | /* Cancel the retire work handler, which should be idle now. */ |
| 3531 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3532 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3533 | return 0; |
| 3534 | } |
| 3535 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3536 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3537 | { |
| 3538 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3539 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3540 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3541 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3542 | return; |
| 3543 | |
| 3544 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3545 | DISP_TILE_SURFACE_SWIZZLING); |
| 3546 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3547 | if (IS_GEN5(dev)) |
| 3548 | return; |
| 3549 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3550 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3551 | if (IS_GEN6(dev)) |
| 3552 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
| 3553 | else |
| 3554 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
| 3555 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3556 | |
| 3557 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3558 | { |
| 3559 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3560 | uint32_t pd_offset; |
| 3561 | struct intel_ring_buffer *ring; |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3562 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 3563 | uint32_t __iomem *pd_addr; |
| 3564 | uint32_t pd_entry; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3565 | int i; |
| 3566 | |
| 3567 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3568 | return; |
| 3569 | |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3570 | |
| 3571 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); |
| 3572 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 3573 | dma_addr_t pt_addr; |
| 3574 | |
| 3575 | if (dev_priv->mm.gtt->needs_dmar) |
| 3576 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 3577 | else |
| 3578 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); |
| 3579 | |
| 3580 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 3581 | pd_entry |= GEN6_PDE_VALID; |
| 3582 | |
| 3583 | writel(pd_entry, pd_addr + i); |
| 3584 | } |
| 3585 | readl(pd_addr); |
| 3586 | |
| 3587 | pd_offset = ppgtt->pd_offset; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3588 | pd_offset /= 64; /* in cachelines, */ |
| 3589 | pd_offset <<= 16; |
| 3590 | |
| 3591 | if (INTEL_INFO(dev)->gen == 6) { |
Daniel Vetter | 48ecfa1 | 2012-04-11 20:42:40 +0200 | [diff] [blame] | 3592 | uint32_t ecochk, gab_ctl, ecobits; |
| 3593 | |
| 3594 | ecobits = I915_READ(GAC_ECO_BITS); |
| 3595 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
Daniel Vetter | be901a5 | 2012-04-11 20:42:39 +0200 | [diff] [blame] | 3596 | |
| 3597 | gab_ctl = I915_READ(GAB_CTL); |
| 3598 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
| 3599 | |
| 3600 | ecochk = I915_READ(GAM_ECOCHK); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3601 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3602 | ECOCHK_PPGTT_CACHE64B); |
| 3603 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3604 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3605 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3606 | /* GFX_MODE is per-ring on gen7+ */ |
| 3607 | } |
| 3608 | |
| 3609 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3610 | ring = &dev_priv->ring[i]; |
| 3611 | |
| 3612 | if (INTEL_INFO(dev)->gen >= 7) |
| 3613 | I915_WRITE(RING_MODE_GEN7(ring), |
| 3614 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); |
| 3615 | |
| 3616 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3617 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3618 | } |
| 3619 | } |
| 3620 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3621 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3622 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3623 | { |
| 3624 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3625 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3626 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3627 | i915_gem_init_swizzling(dev); |
| 3628 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3629 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3630 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3631 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3632 | |
| 3633 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3634 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3635 | if (ret) |
| 3636 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3637 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3638 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3639 | if (HAS_BLT(dev)) { |
| 3640 | ret = intel_init_blt_ring_buffer(dev); |
| 3641 | if (ret) |
| 3642 | goto cleanup_bsd_ring; |
| 3643 | } |
| 3644 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3645 | dev_priv->next_seqno = 1; |
| 3646 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3647 | i915_gem_init_ppgtt(dev); |
| 3648 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3649 | return 0; |
| 3650 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3651 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3652 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3653 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3654 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3655 | return ret; |
| 3656 | } |
| 3657 | |
| 3658 | void |
| 3659 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3660 | { |
| 3661 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3662 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3663 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3664 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3665 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3666 | } |
| 3667 | |
| 3668 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3669 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3670 | struct drm_file *file_priv) |
| 3671 | { |
| 3672 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3673 | int ret, i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3674 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3675 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3676 | return 0; |
| 3677 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3678 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3679 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3680 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3681 | } |
| 3682 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3683 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3684 | dev_priv->mm.suspended = 0; |
| 3685 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3686 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3687 | if (ret != 0) { |
| 3688 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3689 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3690 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3691 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3692 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3693 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3694 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3695 | for (i = 0; i < I915_NUM_RINGS; i++) { |
| 3696 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
| 3697 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
| 3698 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3699 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3700 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3701 | ret = drm_irq_install(dev); |
| 3702 | if (ret) |
| 3703 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3704 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3705 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3706 | |
| 3707 | cleanup_ringbuffer: |
| 3708 | mutex_lock(&dev->struct_mutex); |
| 3709 | i915_gem_cleanup_ringbuffer(dev); |
| 3710 | dev_priv->mm.suspended = 1; |
| 3711 | mutex_unlock(&dev->struct_mutex); |
| 3712 | |
| 3713 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3714 | } |
| 3715 | |
| 3716 | int |
| 3717 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3718 | struct drm_file *file_priv) |
| 3719 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3720 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3721 | return 0; |
| 3722 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3723 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3724 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3725 | } |
| 3726 | |
| 3727 | void |
| 3728 | i915_gem_lastclose(struct drm_device *dev) |
| 3729 | { |
| 3730 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3731 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3732 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3733 | return; |
| 3734 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3735 | ret = i915_gem_idle(dev); |
| 3736 | if (ret) |
| 3737 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3738 | } |
| 3739 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3740 | static void |
| 3741 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3742 | { |
| 3743 | INIT_LIST_HEAD(&ring->active_list); |
| 3744 | INIT_LIST_HEAD(&ring->request_list); |
| 3745 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3746 | } |
| 3747 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3748 | void |
| 3749 | i915_gem_load(struct drm_device *dev) |
| 3750 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3751 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3752 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3753 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3754 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3755 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3756 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 3757 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3758 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3759 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3760 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3761 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3762 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 3763 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3764 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3766 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3767 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3768 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3769 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3770 | if (IS_GEN3(dev)) { |
| 3771 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 3772 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 3773 | /* arb state is a masked write, so set bit + bit in mask */ |
| 3774 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 3775 | I915_WRITE(MI_ARB_STATE, tmp); |
| 3776 | } |
| 3777 | } |
| 3778 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3779 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3780 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3781 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3782 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3783 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3784 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3785 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3786 | dev_priv->num_fence_regs = 16; |
| 3787 | else |
| 3788 | dev_priv->num_fence_regs = 8; |
| 3789 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3790 | /* Initialize fence registers to zero */ |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3791 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
| 3792 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3793 | } |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3794 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3795 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3796 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3797 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3798 | dev_priv->mm.interruptible = true; |
| 3799 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3800 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3801 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3802 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3803 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3804 | |
| 3805 | /* |
| 3806 | * Create a physically contiguous memory object for this object |
| 3807 | * e.g. for cursor + overlay regs |
| 3808 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3809 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3810 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3811 | { |
| 3812 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3813 | struct drm_i915_gem_phys_object *phys_obj; |
| 3814 | int ret; |
| 3815 | |
| 3816 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3817 | return 0; |
| 3818 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3819 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3820 | if (!phys_obj) |
| 3821 | return -ENOMEM; |
| 3822 | |
| 3823 | phys_obj->id = id; |
| 3824 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3825 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3826 | if (!phys_obj->handle) { |
| 3827 | ret = -ENOMEM; |
| 3828 | goto kfree_obj; |
| 3829 | } |
| 3830 | #ifdef CONFIG_X86 |
| 3831 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3832 | #endif |
| 3833 | |
| 3834 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3835 | |
| 3836 | return 0; |
| 3837 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3838 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3839 | return ret; |
| 3840 | } |
| 3841 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3842 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3843 | { |
| 3844 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3845 | struct drm_i915_gem_phys_object *phys_obj; |
| 3846 | |
| 3847 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3848 | return; |
| 3849 | |
| 3850 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3851 | if (phys_obj->cur_obj) { |
| 3852 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3853 | } |
| 3854 | |
| 3855 | #ifdef CONFIG_X86 |
| 3856 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3857 | #endif |
| 3858 | drm_pci_free(dev, phys_obj->handle); |
| 3859 | kfree(phys_obj); |
| 3860 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3861 | } |
| 3862 | |
| 3863 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3864 | { |
| 3865 | int i; |
| 3866 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3867 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3868 | i915_gem_free_phys_object(dev, i); |
| 3869 | } |
| 3870 | |
| 3871 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3872 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3873 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3874 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3875 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3876 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3877 | int page_count; |
| 3878 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3879 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3880 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3881 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3882 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3883 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3884 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3885 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3886 | if (!IS_ERR(page)) { |
| 3887 | char *dst = kmap_atomic(page); |
| 3888 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3889 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3890 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3891 | drm_clflush_pages(&page, 1); |
| 3892 | |
| 3893 | set_page_dirty(page); |
| 3894 | mark_page_accessed(page); |
| 3895 | page_cache_release(page); |
| 3896 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3897 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3898 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3899 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3900 | obj->phys_obj->cur_obj = NULL; |
| 3901 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3902 | } |
| 3903 | |
| 3904 | int |
| 3905 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3906 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3907 | int id, |
| 3908 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3909 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3910 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3911 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3912 | int ret = 0; |
| 3913 | int page_count; |
| 3914 | int i; |
| 3915 | |
| 3916 | if (id > I915_MAX_PHYS_OBJECT) |
| 3917 | return -EINVAL; |
| 3918 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3919 | if (obj->phys_obj) { |
| 3920 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3921 | return 0; |
| 3922 | i915_gem_detach_phys_object(dev, obj); |
| 3923 | } |
| 3924 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3925 | /* create a new object */ |
| 3926 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 3927 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3928 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3929 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3930 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 3931 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3932 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3933 | } |
| 3934 | } |
| 3935 | |
| 3936 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3937 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3938 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3939 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3940 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3941 | |
| 3942 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3943 | struct page *page; |
| 3944 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3945 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3946 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3947 | if (IS_ERR(page)) |
| 3948 | return PTR_ERR(page); |
| 3949 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 3950 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3951 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3952 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 3953 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3954 | |
| 3955 | mark_page_accessed(page); |
| 3956 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3957 | } |
| 3958 | |
| 3959 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3960 | } |
| 3961 | |
| 3962 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3963 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 3964 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3965 | struct drm_i915_gem_pwrite *args, |
| 3966 | struct drm_file *file_priv) |
| 3967 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3968 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3969 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3970 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 3971 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 3972 | unsigned long unwritten; |
| 3973 | |
| 3974 | /* The physical object once assigned is fixed for the lifetime |
| 3975 | * of the obj, so we can safely drop the lock and continue |
| 3976 | * to access vaddr. |
| 3977 | */ |
| 3978 | mutex_unlock(&dev->struct_mutex); |
| 3979 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 3980 | mutex_lock(&dev->struct_mutex); |
| 3981 | if (unwritten) |
| 3982 | return -EFAULT; |
| 3983 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3984 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3985 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3986 | return 0; |
| 3987 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3988 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3989 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3990 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3991 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3992 | |
| 3993 | /* Clean up our request list when the client is going away, so that |
| 3994 | * later retire_requests won't dereference our soon-to-be-gone |
| 3995 | * file_priv. |
| 3996 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3997 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3998 | while (!list_empty(&file_priv->mm.request_list)) { |
| 3999 | struct drm_i915_gem_request *request; |
| 4000 | |
| 4001 | request = list_first_entry(&file_priv->mm.request_list, |
| 4002 | struct drm_i915_gem_request, |
| 4003 | client_list); |
| 4004 | list_del(&request->client_list); |
| 4005 | request->file_priv = NULL; |
| 4006 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4007 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4008 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4009 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4010 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4011 | i915_gpu_is_active(struct drm_device *dev) |
| 4012 | { |
| 4013 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4014 | int lists_empty; |
| 4015 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4016 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4017 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4018 | |
| 4019 | return !lists_empty; |
| 4020 | } |
| 4021 | |
| 4022 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4023 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4024 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4025 | struct drm_i915_private *dev_priv = |
| 4026 | container_of(shrinker, |
| 4027 | struct drm_i915_private, |
| 4028 | mm.inactive_shrinker); |
| 4029 | struct drm_device *dev = dev_priv->dev; |
| 4030 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4031 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4032 | int cnt; |
| 4033 | |
| 4034 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4035 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4036 | |
| 4037 | /* "fast-path" to count number of available objects */ |
| 4038 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4039 | cnt = 0; |
| 4040 | list_for_each_entry(obj, |
| 4041 | &dev_priv->mm.inactive_list, |
| 4042 | mm_list) |
| 4043 | cnt++; |
| 4044 | mutex_unlock(&dev->struct_mutex); |
| 4045 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4046 | } |
| 4047 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4048 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4049 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4050 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4051 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4052 | list_for_each_entry_safe(obj, next, |
| 4053 | &dev_priv->mm.inactive_list, |
| 4054 | mm_list) { |
| 4055 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4056 | if (i915_gem_object_unbind(obj) == 0 && |
| 4057 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4058 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4059 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4060 | } |
| 4061 | |
| 4062 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4063 | cnt = 0; |
| 4064 | list_for_each_entry_safe(obj, next, |
| 4065 | &dev_priv->mm.inactive_list, |
| 4066 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4067 | if (nr_to_scan && |
| 4068 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4069 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4070 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4071 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4072 | } |
| 4073 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4074 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4075 | /* |
| 4076 | * We are desperate for pages, so as a last resort, wait |
| 4077 | * for the GPU to finish and discard whatever we can. |
| 4078 | * This has a dramatic impact to reduce the number of |
| 4079 | * OOM-killer events whilst running the GPU aggressively. |
| 4080 | */ |
Ben Widawsky | b93f9cf | 2012-01-25 15:39:34 -0800 | [diff] [blame] | 4081 | if (i915_gpu_idle(dev, true) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4082 | goto rescan; |
| 4083 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4084 | mutex_unlock(&dev->struct_mutex); |
| 4085 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4086 | } |