Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 36 | bool |
| 37 | intel_ring_initialized(struct intel_engine_cs *ring) |
| 38 | { |
| 39 | struct drm_device *dev = ring->dev; |
| 40 | |
| 41 | if (!dev) |
| 42 | return false; |
| 43 | |
| 44 | if (i915.enable_execlists) { |
| 45 | struct intel_context *dctx = ring->default_context; |
| 46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; |
| 47 | |
| 48 | return ringbuf->obj; |
| 49 | } else |
| 50 | return ring->buffer && ring->buffer->obj; |
| 51 | } |
| 52 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 53 | int __intel_ring_space(int head, int tail, int size) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 54 | { |
| 55 | int space = head - (tail + I915_RING_FREE_SPACE); |
| 56 | if (space < 0) |
| 57 | space += size; |
| 58 | return space; |
| 59 | } |
| 60 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 61 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 62 | { |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 63 | return __intel_ring_space(ringbuf->head & HEAD_ADDR, |
| 64 | ringbuf->tail, ringbuf->size); |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 65 | } |
| 66 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 67 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 68 | { |
| 69 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 70 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
| 71 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 72 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 73 | void __intel_ring_advance(struct intel_engine_cs *ring) |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 74 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 75 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 76 | ringbuf->tail &= ringbuf->size - 1; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 77 | if (intel_ring_stopped(ring)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 78 | return; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 79 | ring->write_tail(ring, ringbuf->tail); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 82 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 83 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 84 | u32 invalidate_domains, |
| 85 | u32 flush_domains) |
| 86 | { |
| 87 | u32 cmd; |
| 88 | int ret; |
| 89 | |
| 90 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 91 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 92 | cmd |= MI_NO_WRITE_FLUSH; |
| 93 | |
| 94 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 95 | cmd |= MI_READ_FLUSH; |
| 96 | |
| 97 | ret = intel_ring_begin(ring, 2); |
| 98 | if (ret) |
| 99 | return ret; |
| 100 | |
| 101 | intel_ring_emit(ring, cmd); |
| 102 | intel_ring_emit(ring, MI_NOOP); |
| 103 | intel_ring_advance(ring); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 109 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 110 | u32 invalidate_domains, |
| 111 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 112 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 113 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 114 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 115 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 116 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 117 | /* |
| 118 | * read/write caches: |
| 119 | * |
| 120 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 121 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 122 | * also flushed at 2d versus 3d pipeline switches. |
| 123 | * |
| 124 | * read-only caches: |
| 125 | * |
| 126 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 127 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 128 | * |
| 129 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 130 | * |
| 131 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 132 | * invalidated when MI_EXE_FLUSH is set. |
| 133 | * |
| 134 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 135 | * invalidated with every MI_FLUSH. |
| 136 | * |
| 137 | * TLBs: |
| 138 | * |
| 139 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 140 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 141 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 142 | * are flushed at any MI_FLUSH. |
| 143 | */ |
| 144 | |
| 145 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 146 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 147 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 148 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 149 | cmd |= MI_EXE_FLUSH; |
| 150 | |
| 151 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 152 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 153 | cmd |= MI_INVALIDATE_ISP; |
| 154 | |
| 155 | ret = intel_ring_begin(ring, 2); |
| 156 | if (ret) |
| 157 | return ret; |
| 158 | |
| 159 | intel_ring_emit(ring, cmd); |
| 160 | intel_ring_emit(ring, MI_NOOP); |
| 161 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 162 | |
| 163 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 164 | } |
| 165 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 166 | /** |
| 167 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 168 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 169 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 170 | * |
| 171 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 172 | * produced by non-pipelined state commands), software needs to first |
| 173 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 174 | * 0. |
| 175 | * |
| 176 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 177 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 178 | * |
| 179 | * And the workaround for these two requires this workaround first: |
| 180 | * |
| 181 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 182 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 183 | * flushes. |
| 184 | * |
| 185 | * And this last workaround is tricky because of the requirements on |
| 186 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 187 | * volume 2 part 1: |
| 188 | * |
| 189 | * "1 of the following must also be set: |
| 190 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 191 | * - Depth Cache Flush Enable ([0] of DW1) |
| 192 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 193 | * - Depth Stall ([13] of DW1) |
| 194 | * - Post-Sync Operation ([13] of DW1) |
| 195 | * - Notify Enable ([8] of DW1)" |
| 196 | * |
| 197 | * The cache flushes require the workaround flush that triggered this |
| 198 | * one, so we can't use it. Depth stall would trigger the same. |
| 199 | * Post-sync nonzero is what triggered this second workaround, so we |
| 200 | * can't use that one either. Notify enable is IRQs, which aren't |
| 201 | * really our business. That leaves only stall at scoreboard. |
| 202 | */ |
| 203 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 204 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 205 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 206 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 207 | int ret; |
| 208 | |
| 209 | |
| 210 | ret = intel_ring_begin(ring, 6); |
| 211 | if (ret) |
| 212 | return ret; |
| 213 | |
| 214 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 215 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 216 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 217 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 218 | intel_ring_emit(ring, 0); /* low dword */ |
| 219 | intel_ring_emit(ring, 0); /* high dword */ |
| 220 | intel_ring_emit(ring, MI_NOOP); |
| 221 | intel_ring_advance(ring); |
| 222 | |
| 223 | ret = intel_ring_begin(ring, 6); |
| 224 | if (ret) |
| 225 | return ret; |
| 226 | |
| 227 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 228 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 229 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 230 | intel_ring_emit(ring, 0); |
| 231 | intel_ring_emit(ring, 0); |
| 232 | intel_ring_emit(ring, MI_NOOP); |
| 233 | intel_ring_advance(ring); |
| 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 239 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 240 | u32 invalidate_domains, u32 flush_domains) |
| 241 | { |
| 242 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 243 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 244 | int ret; |
| 245 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 246 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 247 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 248 | if (ret) |
| 249 | return ret; |
| 250 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 251 | /* Just flush everything. Experiments have shown that reducing the |
| 252 | * number of bits based on the write domains has little performance |
| 253 | * impact. |
| 254 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 255 | if (flush_domains) { |
| 256 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 257 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 258 | /* |
| 259 | * Ensure that any following seqno writes only happen |
| 260 | * when the render cache is indeed flushed. |
| 261 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 262 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 263 | } |
| 264 | if (invalidate_domains) { |
| 265 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 266 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 267 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 268 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 269 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 270 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 271 | /* |
| 272 | * TLB invalidate requires a post-sync write. |
| 273 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 274 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 275 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 276 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 277 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 278 | if (ret) |
| 279 | return ret; |
| 280 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 281 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 282 | intel_ring_emit(ring, flags); |
| 283 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 284 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 285 | intel_ring_advance(ring); |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 290 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 291 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 292 | { |
| 293 | int ret; |
| 294 | |
| 295 | ret = intel_ring_begin(ring, 4); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | |
| 299 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 300 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 301 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 302 | intel_ring_emit(ring, 0); |
| 303 | intel_ring_emit(ring, 0); |
| 304 | intel_ring_advance(ring); |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 309 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 310 | { |
| 311 | int ret; |
| 312 | |
| 313 | if (!ring->fbc_dirty) |
| 314 | return 0; |
| 315 | |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 316 | ret = intel_ring_begin(ring, 6); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 317 | if (ret) |
| 318 | return ret; |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 319 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
| 320 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 321 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 322 | intel_ring_emit(ring, value); |
Ville Syrjälä | 37c1d94 | 2013-11-06 23:02:20 +0200 | [diff] [blame] | 323 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
| 324 | intel_ring_emit(ring, MSG_FBC_REND_STATE); |
| 325 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 326 | intel_ring_advance(ring); |
| 327 | |
| 328 | ring->fbc_dirty = false; |
| 329 | return 0; |
| 330 | } |
| 331 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 332 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 333 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 334 | u32 invalidate_domains, u32 flush_domains) |
| 335 | { |
| 336 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 337 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 338 | int ret; |
| 339 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 340 | /* |
| 341 | * Ensure that any following seqno writes only happen when the render |
| 342 | * cache is indeed flushed. |
| 343 | * |
| 344 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 345 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 346 | * don't try to be clever and just set it unconditionally. |
| 347 | */ |
| 348 | flags |= PIPE_CONTROL_CS_STALL; |
| 349 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 350 | /* Just flush everything. Experiments have shown that reducing the |
| 351 | * number of bits based on the write domains has little performance |
| 352 | * impact. |
| 353 | */ |
| 354 | if (flush_domains) { |
| 355 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 356 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 357 | } |
| 358 | if (invalidate_domains) { |
| 359 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 360 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 361 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 362 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 363 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 364 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 365 | /* |
| 366 | * TLB invalidate requires a post-sync write. |
| 367 | */ |
| 368 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 369 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 370 | |
| 371 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 372 | * set before a pipe_control command that has the state cache |
| 373 | * invalidate bit set. */ |
| 374 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | ret = intel_ring_begin(ring, 4); |
| 378 | if (ret) |
| 379 | return ret; |
| 380 | |
| 381 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 382 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 383 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 384 | intel_ring_emit(ring, 0); |
| 385 | intel_ring_advance(ring); |
| 386 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 387 | if (!invalidate_domains && flush_domains) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 388 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 389 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 390 | return 0; |
| 391 | } |
| 392 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 393 | static int |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 394 | gen8_emit_pipe_control(struct intel_engine_cs *ring, |
| 395 | u32 flags, u32 scratch_addr) |
| 396 | { |
| 397 | int ret; |
| 398 | |
| 399 | ret = intel_ring_begin(ring, 6); |
| 400 | if (ret) |
| 401 | return ret; |
| 402 | |
| 403 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 404 | intel_ring_emit(ring, flags); |
| 405 | intel_ring_emit(ring, scratch_addr); |
| 406 | intel_ring_emit(ring, 0); |
| 407 | intel_ring_emit(ring, 0); |
| 408 | intel_ring_emit(ring, 0); |
| 409 | intel_ring_advance(ring); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 415 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 416 | u32 invalidate_domains, u32 flush_domains) |
| 417 | { |
| 418 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 419 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 420 | int ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 421 | |
| 422 | flags |= PIPE_CONTROL_CS_STALL; |
| 423 | |
| 424 | if (flush_domains) { |
| 425 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 426 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 427 | } |
| 428 | if (invalidate_domains) { |
| 429 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 430 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 431 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 432 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 433 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 434 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 435 | flags |= PIPE_CONTROL_QW_WRITE; |
| 436 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 437 | |
| 438 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ |
| 439 | ret = gen8_emit_pipe_control(ring, |
| 440 | PIPE_CONTROL_CS_STALL | |
| 441 | PIPE_CONTROL_STALL_AT_SCOREBOARD, |
| 442 | 0); |
| 443 | if (ret) |
| 444 | return ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 445 | } |
| 446 | |
Rodrigo Vivi | c5ad011 | 2014-08-04 03:51:38 -0700 | [diff] [blame] | 447 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
| 448 | if (ret) |
| 449 | return ret; |
| 450 | |
| 451 | if (!invalidate_domains && flush_domains) |
| 452 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
| 453 | |
| 454 | return 0; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 455 | } |
| 456 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 457 | static void ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 458 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 459 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 460 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 461 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 462 | } |
| 463 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 464 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 465 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 466 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 467 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 468 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 469 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 470 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
| 471 | RING_ACTHD_UDW(ring->mmio_base)); |
| 472 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
| 473 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
| 474 | else |
| 475 | acthd = I915_READ(ACTHD); |
| 476 | |
| 477 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 478 | } |
| 479 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 480 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 481 | { |
| 482 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 483 | u32 addr; |
| 484 | |
| 485 | addr = dev_priv->status_page_dmah->busaddr; |
| 486 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 487 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 488 | I915_WRITE(HWS_PGA, addr); |
| 489 | } |
| 490 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 491 | static bool stop_ring(struct intel_engine_cs *ring) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 492 | { |
| 493 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 494 | |
| 495 | if (!IS_GEN2(ring->dev)) { |
| 496 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
Daniel Vetter | 403bdd1 | 2014-08-07 16:05:39 +0200 | [diff] [blame] | 497 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 498 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 499 | /* Sometimes we observe that the idle flag is not |
| 500 | * set even though the ring is empty. So double |
| 501 | * check before giving up. |
| 502 | */ |
| 503 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) |
| 504 | return false; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 505 | } |
| 506 | } |
| 507 | |
| 508 | I915_WRITE_CTL(ring, 0); |
| 509 | I915_WRITE_HEAD(ring, 0); |
| 510 | ring->write_tail(ring, 0); |
| 511 | |
| 512 | if (!IS_GEN2(ring->dev)) { |
| 513 | (void)I915_READ_CTL(ring); |
| 514 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
| 515 | } |
| 516 | |
| 517 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
| 518 | } |
| 519 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 520 | static int init_ring_common(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 521 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 522 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 524 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 525 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 526 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 527 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 528 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 529 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 530 | if (!stop_ring(ring)) { |
| 531 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 532 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 533 | "ctl %08x head %08x tail %08x start %08x\n", |
| 534 | ring->name, |
| 535 | I915_READ_CTL(ring), |
| 536 | I915_READ_HEAD(ring), |
| 537 | I915_READ_TAIL(ring), |
| 538 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 539 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 540 | if (!stop_ring(ring)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 541 | DRM_ERROR("failed to set %s head to zero " |
| 542 | "ctl %08x head %08x tail %08x start %08x\n", |
| 543 | ring->name, |
| 544 | I915_READ_CTL(ring), |
| 545 | I915_READ_HEAD(ring), |
| 546 | I915_READ_TAIL(ring), |
| 547 | I915_READ_START(ring)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 548 | ret = -EIO; |
| 549 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 550 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 551 | } |
| 552 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 553 | if (I915_NEED_GFX_HWS(dev)) |
| 554 | intel_ring_setup_status_page(ring); |
| 555 | else |
| 556 | ring_setup_phys_status_page(ring); |
| 557 | |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 558 | /* Enforce ordering by reading HEAD register back */ |
| 559 | I915_READ_HEAD(ring); |
| 560 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 561 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 562 | * registers with the above sequence (the readback of the HEAD registers |
| 563 | * also enforces ordering), otherwise the hw might lose the new ring |
| 564 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 565 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 566 | I915_WRITE_CTL(ring, |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 567 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 568 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 569 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 570 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 571 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 572 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 573 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 574 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame] | 575 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
| 576 | ring->name, |
| 577 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, |
| 578 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), |
| 579 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 580 | ret = -EIO; |
| 581 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 582 | } |
| 583 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 584 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 585 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 586 | else { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 587 | ringbuf->head = I915_READ_HEAD(ring); |
| 588 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 589 | ringbuf->space = intel_ring_space(ringbuf); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 590 | ringbuf->last_retired_head = -1; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 591 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 592 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 593 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 594 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 595 | out: |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 596 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 597 | |
| 598 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 599 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 600 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 601 | void |
| 602 | intel_fini_pipe_control(struct intel_engine_cs *ring) |
| 603 | { |
| 604 | struct drm_device *dev = ring->dev; |
| 605 | |
| 606 | if (ring->scratch.obj == NULL) |
| 607 | return; |
| 608 | |
| 609 | if (INTEL_INFO(dev)->gen >= 5) { |
| 610 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 611 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
| 612 | } |
| 613 | |
| 614 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 615 | ring->scratch.obj = NULL; |
| 616 | } |
| 617 | |
| 618 | int |
| 619 | intel_init_pipe_control(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 620 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 621 | int ret; |
| 622 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 623 | if (ring->scratch.obj) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 624 | return 0; |
| 625 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 626 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 627 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 628 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 629 | ret = -ENOMEM; |
| 630 | goto err; |
| 631 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 632 | |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 633 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 634 | if (ret) |
| 635 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 636 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 637 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 638 | if (ret) |
| 639 | goto err_unref; |
| 640 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 641 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 642 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 643 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 644 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 645 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 646 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 647 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 648 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 649 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 650 | return 0; |
| 651 | |
| 652 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 653 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 654 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 655 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 656 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 657 | return ret; |
| 658 | } |
| 659 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 660 | static inline void intel_ring_emit_wa(struct intel_engine_cs *ring, |
| 661 | u32 addr, u32 value) |
| 662 | { |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 663 | struct drm_device *dev = ring->dev; |
| 664 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 665 | |
| 666 | if (dev_priv->num_wa_regs > I915_MAX_WA_REGS) |
| 667 | return; |
| 668 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 669 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 670 | intel_ring_emit(ring, addr); |
| 671 | intel_ring_emit(ring, value); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 672 | |
| 673 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr; |
| 674 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = (value) & 0xFFFF; |
| 675 | /* value is updated with the status of remaining bits of this |
| 676 | * register when it is read from debugfs file |
| 677 | */ |
| 678 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value; |
| 679 | dev_priv->num_wa_regs++; |
| 680 | |
| 681 | return; |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 682 | } |
| 683 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame^] | 684 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 685 | { |
| 686 | int ret; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 687 | struct drm_device *dev = ring->dev; |
| 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 689 | |
| 690 | /* |
| 691 | * workarounds applied in this fn are part of register state context, |
| 692 | * they need to be re-initialized followed by gpu reset, suspend/resume, |
| 693 | * module reload. |
| 694 | */ |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 695 | dev_priv->num_wa_regs = 0; |
| 696 | memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 697 | |
| 698 | /* |
| 699 | * update the number of dwords required based on the |
| 700 | * actual number of workarounds applied |
| 701 | */ |
| 702 | ret = intel_ring_begin(ring, 24); |
| 703 | if (ret) |
| 704 | return ret; |
| 705 | |
| 706 | /* WaDisablePartialInstShootdown:bdw */ |
| 707 | /* WaDisableThreadStallDopClockGating:bdw */ |
| 708 | /* FIXME: Unclear whether we really need this on production bdw. */ |
| 709 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, |
| 710 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
| 711 | | STALL_DOP_GATING_DISABLE)); |
| 712 | |
| 713 | /* WaDisableDopClockGating:bdw May not be needed for production */ |
| 714 | intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, |
| 715 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 716 | |
| 717 | /* |
| 718 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for |
| 719 | * pre-production hardware |
| 720 | */ |
| 721 | intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, |
| 722 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS |
| 723 | | GEN8_SAMPLER_POWER_BYPASS_DIS)); |
| 724 | |
| 725 | intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, |
| 726 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); |
| 727 | |
| 728 | intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, |
| 729 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); |
| 730 | |
| 731 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 732 | * workaround for for a possible hang in the unlikely event a TLB |
| 733 | * invalidation occurs during a PSD flush. |
| 734 | */ |
| 735 | intel_ring_emit_wa(ring, HDC_CHICKEN0, |
| 736 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); |
| 737 | |
| 738 | /* Wa4x4STCOptimizationDisable:bdw */ |
| 739 | intel_ring_emit_wa(ring, CACHE_MODE_1, |
| 740 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); |
| 741 | |
| 742 | /* |
| 743 | * BSpec recommends 8x4 when MSAA is used, |
| 744 | * however in practice 16x4 seems fastest. |
| 745 | * |
| 746 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 747 | * disable bit, which we don't touch here, but it's good |
| 748 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 749 | */ |
| 750 | intel_ring_emit_wa(ring, GEN7_GT_MODE, |
| 751 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 752 | |
| 753 | intel_ring_advance(ring); |
| 754 | |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 755 | DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n", |
| 756 | dev_priv->num_wa_regs); |
| 757 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 758 | return 0; |
| 759 | } |
| 760 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame^] | 761 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
| 762 | { |
| 763 | int ret; |
| 764 | struct drm_device *dev = ring->dev; |
| 765 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 766 | |
| 767 | /* |
| 768 | * workarounds applied in this fn are part of register state context, |
| 769 | * they need to be re-initialized followed by gpu reset, suspend/resume, |
| 770 | * module reload. |
| 771 | */ |
| 772 | dev_priv->num_wa_regs = 0; |
| 773 | memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); |
| 774 | |
| 775 | ret = intel_ring_begin(ring, 12); |
| 776 | if (ret) |
| 777 | return ret; |
| 778 | |
| 779 | /* WaDisablePartialInstShootdown:chv */ |
| 780 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, |
| 781 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); |
| 782 | |
| 783 | /* WaDisableThreadStallDopClockGating:chv */ |
| 784 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, |
| 785 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); |
| 786 | |
| 787 | /* WaDisableDopClockGating:chv (pre-production hw) */ |
| 788 | intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, |
| 789 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 790 | |
| 791 | /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ |
| 792 | intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, |
| 793 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); |
| 794 | |
| 795 | intel_ring_advance(ring); |
| 796 | |
| 797 | return 0; |
| 798 | } |
| 799 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 800 | static int init_render_ring(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 801 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 802 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 803 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 804 | int ret = init_ring_common(ring); |
Konrad Zapalowicz | 9c33baa | 2014-06-19 19:07:15 +0200 | [diff] [blame] | 805 | if (ret) |
| 806 | return ret; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 807 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 808 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 809 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 810 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 811 | |
| 812 | /* We need to disable the AsyncFlip performance optimisations in order |
| 813 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 814 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 815 | * |
Ville Syrjälä | b3f797a | 2014-04-28 14:31:09 +0300 | [diff] [blame] | 816 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 817 | */ |
| 818 | if (INTEL_INFO(dev)->gen >= 6) |
| 819 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 820 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 821 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 822 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 823 | if (INTEL_INFO(dev)->gen == 6) |
| 824 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 825 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 826 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 827 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 828 | if (IS_GEN7(dev)) |
| 829 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 830 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 831 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 832 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 833 | if (INTEL_INFO(dev)->gen >= 5) { |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 834 | ret = intel_init_pipe_control(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 835 | if (ret) |
| 836 | return ret; |
| 837 | } |
| 838 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 839 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 840 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 841 | * "If this bit is set, STCunit will have LRA as replacement |
| 842 | * policy. [...] This bit must be reset. LRA replacement |
| 843 | * policy is not supported." |
| 844 | */ |
| 845 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 846 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 847 | } |
| 848 | |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 849 | if (INTEL_INFO(dev)->gen >= 6) |
| 850 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 851 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 852 | if (HAS_L3_DPF(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 853 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 854 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 855 | return ret; |
| 856 | } |
| 857 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 858 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 859 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 860 | struct drm_device *dev = ring->dev; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 861 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 862 | |
| 863 | if (dev_priv->semaphore_obj) { |
| 864 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
| 865 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
| 866 | dev_priv->semaphore_obj = NULL; |
| 867 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 868 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 869 | intel_fini_pipe_control(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 870 | } |
| 871 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 872 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
| 873 | unsigned int num_dwords) |
| 874 | { |
| 875 | #define MBOX_UPDATE_DWORDS 8 |
| 876 | struct drm_device *dev = signaller->dev; |
| 877 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 878 | struct intel_engine_cs *waiter; |
| 879 | int i, ret, num_rings; |
| 880 | |
| 881 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 882 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 883 | #undef MBOX_UPDATE_DWORDS |
| 884 | |
| 885 | ret = intel_ring_begin(signaller, num_dwords); |
| 886 | if (ret) |
| 887 | return ret; |
| 888 | |
| 889 | for_each_ring(waiter, dev_priv, i) { |
| 890 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 891 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 892 | continue; |
| 893 | |
| 894 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
| 895 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 896 | PIPE_CONTROL_QW_WRITE | |
| 897 | PIPE_CONTROL_FLUSH_ENABLE); |
| 898 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
| 899 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
| 900 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
| 901 | intel_ring_emit(signaller, 0); |
| 902 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 903 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 904 | intel_ring_emit(signaller, 0); |
| 905 | } |
| 906 | |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, |
| 911 | unsigned int num_dwords) |
| 912 | { |
| 913 | #define MBOX_UPDATE_DWORDS 6 |
| 914 | struct drm_device *dev = signaller->dev; |
| 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 916 | struct intel_engine_cs *waiter; |
| 917 | int i, ret, num_rings; |
| 918 | |
| 919 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 920 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 921 | #undef MBOX_UPDATE_DWORDS |
| 922 | |
| 923 | ret = intel_ring_begin(signaller, num_dwords); |
| 924 | if (ret) |
| 925 | return ret; |
| 926 | |
| 927 | for_each_ring(waiter, dev_priv, i) { |
| 928 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 929 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 930 | continue; |
| 931 | |
| 932 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
| 933 | MI_FLUSH_DW_OP_STOREDW); |
| 934 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | |
| 935 | MI_FLUSH_DW_USE_GTT); |
| 936 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
| 937 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
| 938 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 939 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 940 | intel_ring_emit(signaller, 0); |
| 941 | } |
| 942 | |
| 943 | return 0; |
| 944 | } |
| 945 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 946 | static int gen6_signal(struct intel_engine_cs *signaller, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 947 | unsigned int num_dwords) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 948 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 949 | struct drm_device *dev = signaller->dev; |
| 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 951 | struct intel_engine_cs *useless; |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 952 | int i, ret, num_rings; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 953 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 954 | #define MBOX_UPDATE_DWORDS 3 |
| 955 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 956 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
| 957 | #undef MBOX_UPDATE_DWORDS |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 958 | |
| 959 | ret = intel_ring_begin(signaller, num_dwords); |
| 960 | if (ret) |
| 961 | return ret; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 962 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 963 | for_each_ring(useless, dev_priv, i) { |
| 964 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; |
| 965 | if (mbox_reg != GEN6_NOSYNC) { |
| 966 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
| 967 | intel_ring_emit(signaller, mbox_reg); |
| 968 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 969 | } |
| 970 | } |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 971 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 972 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
| 973 | if (num_rings % 2 == 0) |
| 974 | intel_ring_emit(signaller, MI_NOOP); |
| 975 | |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 976 | return 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 977 | } |
| 978 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 979 | /** |
| 980 | * gen6_add_request - Update the semaphore mailbox registers |
| 981 | * |
| 982 | * @ring - ring that is adding a request |
| 983 | * @seqno - return seqno stuck into the ring |
| 984 | * |
| 985 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 986 | * This acts like a signal in the canonical semaphore. |
| 987 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 988 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 989 | gen6_add_request(struct intel_engine_cs *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 990 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 991 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 992 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 993 | if (ring->semaphore.signal) |
| 994 | ret = ring->semaphore.signal(ring, 4); |
| 995 | else |
| 996 | ret = intel_ring_begin(ring, 4); |
| 997 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 998 | if (ret) |
| 999 | return ret; |
| 1000 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1001 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1002 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1003 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1004 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1005 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1006 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1007 | return 0; |
| 1008 | } |
| 1009 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1010 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 1011 | u32 seqno) |
| 1012 | { |
| 1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1014 | return dev_priv->last_seqno < seqno; |
| 1015 | } |
| 1016 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1017 | /** |
| 1018 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 1019 | * |
| 1020 | * @waiter - ring that is waiting |
| 1021 | * @signaller - ring which has, or will signal |
| 1022 | * @seqno - seqno which the waiter will block on |
| 1023 | */ |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1024 | |
| 1025 | static int |
| 1026 | gen8_ring_sync(struct intel_engine_cs *waiter, |
| 1027 | struct intel_engine_cs *signaller, |
| 1028 | u32 seqno) |
| 1029 | { |
| 1030 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
| 1031 | int ret; |
| 1032 | |
| 1033 | ret = intel_ring_begin(waiter, 4); |
| 1034 | if (ret) |
| 1035 | return ret; |
| 1036 | |
| 1037 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | |
| 1038 | MI_SEMAPHORE_GLOBAL_GTT | |
Ben Widawsky | bae4fcd | 2014-06-30 09:53:43 -0700 | [diff] [blame] | 1039 | MI_SEMAPHORE_POLL | |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1040 | MI_SEMAPHORE_SAD_GTE_SDD); |
| 1041 | intel_ring_emit(waiter, seqno); |
| 1042 | intel_ring_emit(waiter, |
| 1043 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1044 | intel_ring_emit(waiter, |
| 1045 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1046 | intel_ring_advance(waiter); |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1050 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1051 | gen6_ring_sync(struct intel_engine_cs *waiter, |
| 1052 | struct intel_engine_cs *signaller, |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1053 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1054 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1055 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 1056 | MI_SEMAPHORE_COMPARE | |
| 1057 | MI_SEMAPHORE_REGISTER; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1058 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
| 1059 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1060 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 1061 | /* Throughout all of the GEM code, seqno passed implies our current |
| 1062 | * seqno is >= the last seqno executed. However for hardware the |
| 1063 | * comparison is strictly greater than. |
| 1064 | */ |
| 1065 | seqno -= 1; |
| 1066 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1067 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1068 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1069 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1070 | if (ret) |
| 1071 | return ret; |
| 1072 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1073 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 1074 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1075 | intel_ring_emit(waiter, dw1 | wait_mbox); |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1076 | intel_ring_emit(waiter, seqno); |
| 1077 | intel_ring_emit(waiter, 0); |
| 1078 | intel_ring_emit(waiter, MI_NOOP); |
| 1079 | } else { |
| 1080 | intel_ring_emit(waiter, MI_NOOP); |
| 1081 | intel_ring_emit(waiter, MI_NOOP); |
| 1082 | intel_ring_emit(waiter, MI_NOOP); |
| 1083 | intel_ring_emit(waiter, MI_NOOP); |
| 1084 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1085 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1086 | |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1090 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 1091 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1092 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 1093 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1094 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 1095 | intel_ring_emit(ring__, 0); \ |
| 1096 | intel_ring_emit(ring__, 0); \ |
| 1097 | } while (0) |
| 1098 | |
| 1099 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1100 | pc_render_add_request(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1101 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1102 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1103 | int ret; |
| 1104 | |
| 1105 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 1106 | * incoherent with writes to memory, i.e. completely fubar, |
| 1107 | * so we need to use PIPE_NOTIFY instead. |
| 1108 | * |
| 1109 | * However, we also need to workaround the qword write |
| 1110 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 1111 | * memory before requesting an interrupt. |
| 1112 | */ |
| 1113 | ret = intel_ring_begin(ring, 32); |
| 1114 | if (ret) |
| 1115 | return ret; |
| 1116 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1117 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1118 | PIPE_CONTROL_WRITE_FLUSH | |
| 1119 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1120 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1121 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1122 | intel_ring_emit(ring, 0); |
| 1123 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1124 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1125 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1126 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1127 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1128 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1129 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1130 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1131 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1132 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1133 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1134 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1135 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1136 | PIPE_CONTROL_WRITE_FLUSH | |
| 1137 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1138 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1139 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1140 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1141 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1142 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1143 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1144 | return 0; |
| 1145 | } |
| 1146 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1147 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1148 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1149 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1150 | /* Workaround to force correct ordering between irq and seqno writes on |
| 1151 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 1152 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 1153 | if (!lazy_coherency) { |
| 1154 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1155 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
| 1156 | } |
| 1157 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1158 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1159 | } |
| 1160 | |
| 1161 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1162 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1163 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1164 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1165 | } |
| 1166 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1167 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1168 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1169 | { |
| 1170 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 1171 | } |
| 1172 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1173 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1174 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1175 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1176 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1177 | } |
| 1178 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1179 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1180 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1181 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1182 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1183 | } |
| 1184 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1185 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1186 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1187 | { |
| 1188 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1190 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1191 | |
| 1192 | if (!dev->irq_enabled) |
| 1193 | return false; |
| 1194 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1195 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1196 | if (ring->irq_refcount++ == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1197 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1198 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1199 | |
| 1200 | return true; |
| 1201 | } |
| 1202 | |
| 1203 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1204 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1205 | { |
| 1206 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1207 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1208 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1209 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1210 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1211 | if (--ring->irq_refcount == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1212 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1213 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1214 | } |
| 1215 | |
| 1216 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1217 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1218 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1219 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1220 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1221 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1222 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1223 | if (!dev->irq_enabled) |
| 1224 | return false; |
| 1225 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1226 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1227 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1228 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1229 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1230 | POSTING_READ(IMR); |
| 1231 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1232 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1233 | |
| 1234 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1235 | } |
| 1236 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1237 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1238 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1239 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1240 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1242 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1243 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1244 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1245 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1246 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1247 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1248 | POSTING_READ(IMR); |
| 1249 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1250 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1251 | } |
| 1252 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1253 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1254 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1255 | { |
| 1256 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1257 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1258 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1259 | |
| 1260 | if (!dev->irq_enabled) |
| 1261 | return false; |
| 1262 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1263 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1264 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1265 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1266 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1267 | POSTING_READ16(IMR); |
| 1268 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1269 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1270 | |
| 1271 | return true; |
| 1272 | } |
| 1273 | |
| 1274 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1275 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1276 | { |
| 1277 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1279 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1280 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1281 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1282 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1283 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1284 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1285 | POSTING_READ16(IMR); |
| 1286 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1287 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1288 | } |
| 1289 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1290 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1291 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1292 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1293 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1294 | u32 mmio = 0; |
| 1295 | |
| 1296 | /* The ring status page addresses are no longer next to the rest of |
| 1297 | * the ring registers as of gen7. |
| 1298 | */ |
| 1299 | if (IS_GEN7(dev)) { |
| 1300 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1301 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1302 | mmio = RENDER_HWS_PGA_GEN7; |
| 1303 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1304 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1305 | mmio = BLT_HWS_PGA_GEN7; |
| 1306 | break; |
Zhao Yakui | 77fe2ff | 2014-04-17 10:37:39 +0800 | [diff] [blame] | 1307 | /* |
| 1308 | * VCS2 actually doesn't exist on Gen7. Only shut up |
| 1309 | * gcc switch check warning |
| 1310 | */ |
| 1311 | case VCS2: |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 1312 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1313 | mmio = BSD_HWS_PGA_GEN7; |
| 1314 | break; |
Ben Widawsky | 4a3dd19 | 2013-05-28 19:22:19 -0700 | [diff] [blame] | 1315 | case VECS: |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 1316 | mmio = VEBOX_HWS_PGA_GEN7; |
| 1317 | break; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1318 | } |
| 1319 | } else if (IS_GEN6(ring->dev)) { |
| 1320 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 1321 | } else { |
Ben Widawsky | eb0d4b7 | 2013-11-07 21:40:50 -0800 | [diff] [blame] | 1322 | /* XXX: gen8 returns to sanity */ |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 1323 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 1324 | } |
| 1325 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1326 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 1327 | POSTING_READ(mmio); |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1328 | |
Damien Lespiau | dc616b8 | 2014-03-13 01:40:28 +0000 | [diff] [blame] | 1329 | /* |
| 1330 | * Flush the TLB for this page |
| 1331 | * |
| 1332 | * FIXME: These two bits have disappeared on gen8, so a question |
| 1333 | * arises: do we still need this and if so how should we go about |
| 1334 | * invalidating the TLB? |
| 1335 | */ |
| 1336 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1337 | u32 reg = RING_INSTPM(ring->mmio_base); |
Naresh Kumar Kachhi | 02f6a1e | 2014-03-12 16:39:42 +0530 | [diff] [blame] | 1338 | |
| 1339 | /* ring should be idle before issuing a sync flush*/ |
| 1340 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 1341 | |
Chris Wilson | 884020b | 2013-08-06 19:01:14 +0100 | [diff] [blame] | 1342 | I915_WRITE(reg, |
| 1343 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 1344 | INSTPM_SYNC_FLUSH)); |
| 1345 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 1346 | 1000)) |
| 1347 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 1348 | ring->name); |
| 1349 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1350 | } |
| 1351 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1352 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1353 | bsd_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1354 | u32 invalidate_domains, |
| 1355 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1356 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1357 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1358 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1359 | ret = intel_ring_begin(ring, 2); |
| 1360 | if (ret) |
| 1361 | return ret; |
| 1362 | |
| 1363 | intel_ring_emit(ring, MI_FLUSH); |
| 1364 | intel_ring_emit(ring, MI_NOOP); |
| 1365 | intel_ring_advance(ring); |
| 1366 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1367 | } |
| 1368 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1369 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1370 | i9xx_add_request(struct intel_engine_cs *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1371 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1372 | int ret; |
| 1373 | |
| 1374 | ret = intel_ring_begin(ring, 4); |
| 1375 | if (ret) |
| 1376 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1377 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1378 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1379 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1380 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1381 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1382 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1383 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1384 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1385 | } |
| 1386 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1387 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1388 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1389 | { |
| 1390 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1391 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1392 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1393 | |
| 1394 | if (!dev->irq_enabled) |
| 1395 | return false; |
| 1396 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1397 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1398 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1399 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1400 | I915_WRITE_IMR(ring, |
| 1401 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1402 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1403 | else |
| 1404 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1405 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1406 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1407 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1408 | |
| 1409 | return true; |
| 1410 | } |
| 1411 | |
| 1412 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1413 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1414 | { |
| 1415 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1416 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1417 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1418 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1419 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1420 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1421 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1422 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1423 | else |
| 1424 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1425 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1426 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1427 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1428 | } |
| 1429 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1430 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1431 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1432 | { |
| 1433 | struct drm_device *dev = ring->dev; |
| 1434 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1435 | unsigned long flags; |
| 1436 | |
| 1437 | if (!dev->irq_enabled) |
| 1438 | return false; |
| 1439 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1440 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1441 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1442 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1443 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1444 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1445 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1446 | |
| 1447 | return true; |
| 1448 | } |
| 1449 | |
| 1450 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1451 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1452 | { |
| 1453 | struct drm_device *dev = ring->dev; |
| 1454 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1455 | unsigned long flags; |
| 1456 | |
| 1457 | if (!dev->irq_enabled) |
| 1458 | return; |
| 1459 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1460 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1461 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1462 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1463 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1464 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1465 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1466 | } |
| 1467 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1468 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1469 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1470 | { |
| 1471 | struct drm_device *dev = ring->dev; |
| 1472 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1473 | unsigned long flags; |
| 1474 | |
| 1475 | if (!dev->irq_enabled) |
| 1476 | return false; |
| 1477 | |
| 1478 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1479 | if (ring->irq_refcount++ == 0) { |
| 1480 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1481 | I915_WRITE_IMR(ring, |
| 1482 | ~(ring->irq_enable_mask | |
| 1483 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1484 | } else { |
| 1485 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1486 | } |
| 1487 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1488 | } |
| 1489 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1490 | |
| 1491 | return true; |
| 1492 | } |
| 1493 | |
| 1494 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1495 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1496 | { |
| 1497 | struct drm_device *dev = ring->dev; |
| 1498 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1499 | unsigned long flags; |
| 1500 | |
| 1501 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1502 | if (--ring->irq_refcount == 0) { |
| 1503 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1504 | I915_WRITE_IMR(ring, |
| 1505 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1506 | } else { |
| 1507 | I915_WRITE_IMR(ring, ~0); |
| 1508 | } |
| 1509 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1510 | } |
| 1511 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1512 | } |
| 1513 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1514 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1515 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1516 | u64 offset, u32 length, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1517 | unsigned flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1518 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1519 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1520 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1521 | ret = intel_ring_begin(ring, 2); |
| 1522 | if (ret) |
| 1523 | return ret; |
| 1524 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1525 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1526 | MI_BATCH_BUFFER_START | |
| 1527 | MI_BATCH_GTT | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1528 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1529 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1530 | intel_ring_advance(ring); |
| 1531 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1532 | return 0; |
| 1533 | } |
| 1534 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1535 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1536 | #define I830_BATCH_LIMIT (256*1024) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1537 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1538 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1539 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1540 | unsigned flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1541 | { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1542 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1543 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1544 | if (flags & I915_DISPATCH_PINNED) { |
| 1545 | ret = intel_ring_begin(ring, 4); |
| 1546 | if (ret) |
| 1547 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1548 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1549 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1550 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1551 | intel_ring_emit(ring, offset + len - 8); |
| 1552 | intel_ring_emit(ring, MI_NOOP); |
| 1553 | intel_ring_advance(ring); |
| 1554 | } else { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1555 | u32 cs_offset = ring->scratch.gtt_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1556 | |
| 1557 | if (len > I830_BATCH_LIMIT) |
| 1558 | return -ENOSPC; |
| 1559 | |
| 1560 | ret = intel_ring_begin(ring, 9+3); |
| 1561 | if (ret) |
| 1562 | return ret; |
| 1563 | /* Blit the batch (which has now all relocs applied) to the stable batch |
| 1564 | * scratch bo area (so that the CS never stumbles over its tlb |
| 1565 | * invalidation bug) ... */ |
| 1566 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | |
| 1567 | XY_SRC_COPY_BLT_WRITE_ALPHA | |
| 1568 | XY_SRC_COPY_BLT_WRITE_RGB); |
| 1569 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); |
| 1570 | intel_ring_emit(ring, 0); |
| 1571 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); |
| 1572 | intel_ring_emit(ring, cs_offset); |
| 1573 | intel_ring_emit(ring, 0); |
| 1574 | intel_ring_emit(ring, 4096); |
| 1575 | intel_ring_emit(ring, offset); |
| 1576 | intel_ring_emit(ring, MI_FLUSH); |
| 1577 | |
| 1578 | /* ... and execute it. */ |
| 1579 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 1580 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
| 1581 | intel_ring_emit(ring, cs_offset + len - 8); |
| 1582 | intel_ring_advance(ring); |
| 1583 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1584 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1585 | return 0; |
| 1586 | } |
| 1587 | |
| 1588 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1589 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1590 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1591 | unsigned flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1592 | { |
| 1593 | int ret; |
| 1594 | |
| 1595 | ret = intel_ring_begin(ring, 2); |
| 1596 | if (ret) |
| 1597 | return ret; |
| 1598 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1599 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 1600 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1601 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1602 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1603 | return 0; |
| 1604 | } |
| 1605 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1606 | static void cleanup_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1607 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1608 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1609 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1610 | obj = ring->status_page.obj; |
| 1611 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1612 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1613 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1614 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1615 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1616 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1617 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1618 | } |
| 1619 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1620 | static int init_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1621 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1622 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1623 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1624 | if ((obj = ring->status_page.obj) == NULL) { |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1625 | unsigned flags; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1626 | int ret; |
| 1627 | |
| 1628 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 1629 | if (obj == NULL) { |
| 1630 | DRM_ERROR("Failed to allocate status page\n"); |
| 1631 | return -ENOMEM; |
| 1632 | } |
| 1633 | |
| 1634 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1635 | if (ret) |
| 1636 | goto err_unref; |
| 1637 | |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1638 | flags = 0; |
| 1639 | if (!HAS_LLC(ring->dev)) |
| 1640 | /* On g33, we cannot place HWS above 256MiB, so |
| 1641 | * restrict its pinning to the low mappable arena. |
| 1642 | * Though this restriction is not documented for |
| 1643 | * gen4, gen5, or byt, they also behave similarly |
| 1644 | * and hang if the HWS is placed at the top of the |
| 1645 | * GTT. To generalise, it appears that all !llc |
| 1646 | * platforms have issues with us placing the HWS |
| 1647 | * above the mappable region (even though we never |
| 1648 | * actualy map it). |
| 1649 | */ |
| 1650 | flags |= PIN_MAPPABLE; |
| 1651 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1652 | if (ret) { |
| 1653 | err_unref: |
| 1654 | drm_gem_object_unreference(&obj->base); |
| 1655 | return ret; |
| 1656 | } |
| 1657 | |
| 1658 | ring->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1659 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1660 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1661 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1662 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1663 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1664 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1665 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1666 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1667 | |
| 1668 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1669 | } |
| 1670 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1671 | static int init_phys_status_page(struct intel_engine_cs *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1672 | { |
| 1673 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1674 | |
| 1675 | if (!dev_priv->status_page_dmah) { |
| 1676 | dev_priv->status_page_dmah = |
| 1677 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1678 | if (!dev_priv->status_page_dmah) |
| 1679 | return -ENOMEM; |
| 1680 | } |
| 1681 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1682 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1683 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1684 | |
| 1685 | return 0; |
| 1686 | } |
| 1687 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1688 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1689 | { |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1690 | if (!ringbuf->obj) |
| 1691 | return; |
| 1692 | |
| 1693 | iounmap(ringbuf->virtual_start); |
| 1694 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
| 1695 | drm_gem_object_unreference(&ringbuf->obj->base); |
| 1696 | ringbuf->obj = NULL; |
| 1697 | } |
| 1698 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1699 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
| 1700 | struct intel_ringbuffer *ringbuf) |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1701 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1702 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1703 | struct drm_i915_gem_object *obj; |
| 1704 | int ret; |
| 1705 | |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1706 | if (ringbuf->obj) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1707 | return 0; |
| 1708 | |
| 1709 | obj = NULL; |
| 1710 | if (!HAS_LLC(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1711 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1712 | if (obj == NULL) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1713 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1714 | if (obj == NULL) |
| 1715 | return -ENOMEM; |
| 1716 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1717 | /* mark ring buffers as read-only from GPU side by default */ |
| 1718 | obj->gt_ro = 1; |
| 1719 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1720 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 1721 | if (ret) |
| 1722 | goto err_unref; |
| 1723 | |
| 1724 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1725 | if (ret) |
| 1726 | goto err_unpin; |
| 1727 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1728 | ringbuf->virtual_start = |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1729 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1730 | ringbuf->size); |
| 1731 | if (ringbuf->virtual_start == NULL) { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1732 | ret = -EINVAL; |
| 1733 | goto err_unpin; |
| 1734 | } |
| 1735 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1736 | ringbuf->obj = obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1737 | return 0; |
| 1738 | |
| 1739 | err_unpin: |
| 1740 | i915_gem_object_ggtt_unpin(obj); |
| 1741 | err_unref: |
| 1742 | drm_gem_object_unreference(&obj->base); |
| 1743 | return ret; |
| 1744 | } |
| 1745 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 1746 | static int intel_init_ring_buffer(struct drm_device *dev, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1747 | struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1748 | { |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1749 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1750 | int ret; |
| 1751 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1752 | if (ringbuf == NULL) { |
| 1753 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 1754 | if (!ringbuf) |
| 1755 | return -ENOMEM; |
| 1756 | ring->buffer = ringbuf; |
| 1757 | } |
| 1758 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1759 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1760 | INIT_LIST_HEAD(&ring->active_list); |
| 1761 | INIT_LIST_HEAD(&ring->request_list); |
Oscar Mateo | cc9130b | 2014-07-24 17:04:42 +0100 | [diff] [blame] | 1762 | INIT_LIST_HEAD(&ring->execlist_queue); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1763 | ringbuf->size = 32 * PAGE_SIZE; |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 1764 | ringbuf->ring = ring; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1765 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 1766 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 1767 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1768 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1769 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1770 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1771 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1772 | goto error; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1773 | } else { |
| 1774 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 1775 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1776 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1777 | goto error; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1778 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1779 | |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1780 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1781 | if (ret) { |
| 1782 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1783 | goto error; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1784 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1785 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1786 | /* Workaround an erratum on the i830 which causes a hang if |
| 1787 | * the TAIL pointer points to within the last 2 cachelines |
| 1788 | * of the buffer. |
| 1789 | */ |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1790 | ringbuf->effective_size = ringbuf->size; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1791 | if (IS_I830(dev) || IS_845G(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1792 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1793 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 1794 | ret = i915_cmd_parser_init_ring(ring); |
| 1795 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1796 | goto error; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 1797 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1798 | ret = ring->init(ring); |
| 1799 | if (ret) |
| 1800 | goto error; |
| 1801 | |
| 1802 | return 0; |
| 1803 | |
| 1804 | error: |
| 1805 | kfree(ringbuf); |
| 1806 | ring->buffer = NULL; |
| 1807 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1808 | } |
| 1809 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1810 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1811 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1812 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1813 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1814 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1815 | if (!intel_ring_initialized(ring)) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1816 | return; |
| 1817 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1818 | intel_stop_ring_buffer(ring); |
Ville Syrjälä | de8f0a5 | 2014-05-28 19:12:13 +0300 | [diff] [blame] | 1819 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1820 | |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1821 | intel_destroy_ringbuffer_obj(ringbuf); |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 1822 | ring->preallocated_lazy_request = NULL; |
| 1823 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1824 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1825 | if (ring->cleanup) |
| 1826 | ring->cleanup(ring); |
| 1827 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1828 | cleanup_status_page(ring); |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 1829 | |
| 1830 | i915_cmd_parser_fini_ring(ring); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1831 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1832 | kfree(ringbuf); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 1833 | ring->buffer = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1834 | } |
| 1835 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1836 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1837 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1838 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1839 | struct drm_i915_gem_request *request; |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 1840 | u32 seqno = 0; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1841 | int ret; |
| 1842 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1843 | if (ringbuf->last_retired_head != -1) { |
| 1844 | ringbuf->head = ringbuf->last_retired_head; |
| 1845 | ringbuf->last_retired_head = -1; |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1846 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1847 | ringbuf->space = intel_ring_space(ringbuf); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1848 | if (ringbuf->space >= n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1849 | return 0; |
| 1850 | } |
| 1851 | |
| 1852 | list_for_each_entry(request, &ring->request_list, list) { |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1853 | if (__intel_ring_space(request->tail, ringbuf->tail, |
| 1854 | ringbuf->size) >= n) { |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1855 | seqno = request->seqno; |
| 1856 | break; |
| 1857 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1858 | } |
| 1859 | |
| 1860 | if (seqno == 0) |
| 1861 | return -ENOSPC; |
| 1862 | |
Chris Wilson | 1f70999 | 2014-01-27 22:43:07 +0000 | [diff] [blame] | 1863 | ret = i915_wait_seqno(ring, seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1864 | if (ret) |
| 1865 | return ret; |
| 1866 | |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 1867 | i915_gem_retire_requests_ring(ring); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1868 | ringbuf->head = ringbuf->last_retired_head; |
| 1869 | ringbuf->last_retired_head = -1; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1870 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1871 | ringbuf->space = intel_ring_space(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1872 | return 0; |
| 1873 | } |
| 1874 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1875 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1876 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1877 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1878 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1879 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1880 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1881 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1882 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1883 | ret = intel_ring_wait_request(ring, n); |
| 1884 | if (ret != -ENOSPC) |
| 1885 | return ret; |
| 1886 | |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1887 | /* force the tail write in case we have been skipping them */ |
| 1888 | __intel_ring_advance(ring); |
| 1889 | |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 1890 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1891 | * leaving it early runs the risk of corrupting GEM state (due |
| 1892 | * to running on almost untested codepaths). But on resume |
| 1893 | * timers don't work yet, so prevent a complete hang in that |
| 1894 | * case by choosing an insanely large timeout. */ |
| 1895 | end = jiffies + 60 * HZ; |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1896 | |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1897 | trace_i915_ring_wait_begin(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1898 | do { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1899 | ringbuf->head = I915_READ_HEAD(ring); |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1900 | ringbuf->space = intel_ring_space(ringbuf); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1901 | if (ringbuf->space >= n) { |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1902 | ret = 0; |
| 1903 | break; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1904 | } |
| 1905 | |
Daniel Vetter | fb19e2a | 2014-02-12 23:44:34 +0100 | [diff] [blame] | 1906 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
| 1907 | dev->primary->master) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1908 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1909 | if (master_priv->sarea_priv) |
| 1910 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1911 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1912 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1913 | msleep(1); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1914 | |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1915 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
| 1916 | ret = -ERESTARTSYS; |
| 1917 | break; |
| 1918 | } |
| 1919 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1920 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 1921 | dev_priv->mm.interruptible); |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 1922 | if (ret) |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1923 | break; |
| 1924 | |
| 1925 | if (time_after(jiffies, end)) { |
| 1926 | ret = -EBUSY; |
| 1927 | break; |
| 1928 | } |
| 1929 | } while (1); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1930 | trace_i915_ring_wait_end(ring); |
Chris Wilson | dcfe050 | 2014-05-05 09:07:32 +0100 | [diff] [blame] | 1931 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1932 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1933 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1934 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1935 | { |
| 1936 | uint32_t __iomem *virt; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1937 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 1938 | int rem = ringbuf->size - ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1939 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1940 | if (ringbuf->space < rem) { |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1941 | int ret = ring_wait_for_space(ring, rem); |
| 1942 | if (ret) |
| 1943 | return ret; |
| 1944 | } |
| 1945 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1946 | virt = ringbuf->virtual_start + ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1947 | rem /= 4; |
| 1948 | while (rem--) |
| 1949 | iowrite32(MI_NOOP, virt++); |
| 1950 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1951 | ringbuf->tail = 0; |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 1952 | ringbuf->space = intel_ring_space(ringbuf); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1953 | |
| 1954 | return 0; |
| 1955 | } |
| 1956 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1957 | int intel_ring_idle(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1958 | { |
| 1959 | u32 seqno; |
| 1960 | int ret; |
| 1961 | |
| 1962 | /* We need to add any requests required to flush the objects and ring */ |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1963 | if (ring->outstanding_lazy_seqno) { |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 1964 | ret = i915_add_request(ring, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 1965 | if (ret) |
| 1966 | return ret; |
| 1967 | } |
| 1968 | |
| 1969 | /* Wait upon the last request to be completed */ |
| 1970 | if (list_empty(&ring->request_list)) |
| 1971 | return 0; |
| 1972 | |
| 1973 | seqno = list_entry(ring->request_list.prev, |
| 1974 | struct drm_i915_gem_request, |
| 1975 | list)->seqno; |
| 1976 | |
| 1977 | return i915_wait_seqno(ring, seqno); |
| 1978 | } |
| 1979 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1980 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1981 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1982 | { |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1983 | if (ring->outstanding_lazy_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1984 | return 0; |
| 1985 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 1986 | if (ring->preallocated_lazy_request == NULL) { |
| 1987 | struct drm_i915_gem_request *request; |
| 1988 | |
| 1989 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1990 | if (request == NULL) |
| 1991 | return -ENOMEM; |
| 1992 | |
| 1993 | ring->preallocated_lazy_request = request; |
| 1994 | } |
| 1995 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 1996 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 1997 | } |
| 1998 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1999 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2000 | int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2001 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2002 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2003 | int ret; |
| 2004 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2005 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2006 | ret = intel_wrap_ring_buffer(ring); |
| 2007 | if (unlikely(ret)) |
| 2008 | return ret; |
| 2009 | } |
| 2010 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2011 | if (unlikely(ringbuf->space < bytes)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2012 | ret = ring_wait_for_space(ring, bytes); |
| 2013 | if (unlikely(ret)) |
| 2014 | return ret; |
| 2015 | } |
| 2016 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2017 | return 0; |
| 2018 | } |
| 2019 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2020 | int intel_ring_begin(struct intel_engine_cs *ring, |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2021 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2022 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2023 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2024 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2025 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2026 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 2027 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 2028 | if (ret) |
| 2029 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 2030 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2031 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 2032 | if (ret) |
| 2033 | return ret; |
| 2034 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2035 | /* Preallocate the olr before touching the ring */ |
| 2036 | ret = intel_ring_alloc_seqno(ring); |
| 2037 | if (ret) |
| 2038 | return ret; |
| 2039 | |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2040 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2041 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2042 | } |
| 2043 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2044 | /* Align the ring tail to a cacheline boundary */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2045 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2046 | { |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2047 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2048 | int ret; |
| 2049 | |
| 2050 | if (num_dwords == 0) |
| 2051 | return 0; |
| 2052 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2053 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2054 | ret = intel_ring_begin(ring, num_dwords); |
| 2055 | if (ret) |
| 2056 | return ret; |
| 2057 | |
| 2058 | while (num_dwords--) |
| 2059 | intel_ring_emit(ring, MI_NOOP); |
| 2060 | |
| 2061 | intel_ring_advance(ring); |
| 2062 | |
| 2063 | return 0; |
| 2064 | } |
| 2065 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2066 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2067 | { |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2068 | struct drm_device *dev = ring->dev; |
| 2069 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2070 | |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2071 | BUG_ON(ring->outstanding_lazy_seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2072 | |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2073 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2074 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 2075 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2076 | if (HAS_VEBOX(dev)) |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 2077 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2078 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 2079 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2080 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2081 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2082 | } |
| 2083 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2084 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2085 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2086 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2087 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2088 | |
| 2089 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2090 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2091 | /* Disable notification that the ring is IDLE. The GT |
| 2092 | * will then assume that it is busy and bring it out of rc6. |
| 2093 | */ |
| 2094 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2095 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 2096 | |
| 2097 | /* Clear the context id. Here be magic! */ |
| 2098 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 2099 | |
| 2100 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2101 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2102 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 2103 | 50)) |
| 2104 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2105 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2106 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2107 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2108 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 2109 | |
| 2110 | /* Let the ring send IDLE messages to the GT again, |
| 2111 | * and so let it sleep to conserve power when idle. |
| 2112 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2113 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2114 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2115 | } |
| 2116 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2117 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2118 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2119 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2120 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2121 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2122 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2123 | ret = intel_ring_begin(ring, 4); |
| 2124 | if (ret) |
| 2125 | return ret; |
| 2126 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2127 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2128 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 2129 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2130 | /* |
| 2131 | * Bspec vol 1c.5 - video engine command streamer: |
| 2132 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2133 | * operation is complete. This bit is only valid when the |
| 2134 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2135 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2136 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2137 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
| 2138 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2139 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2140 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2141 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2142 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2143 | intel_ring_emit(ring, 0); /* value */ |
| 2144 | } else { |
| 2145 | intel_ring_emit(ring, 0); |
| 2146 | intel_ring_emit(ring, MI_NOOP); |
| 2147 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2148 | intel_ring_advance(ring); |
| 2149 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2150 | } |
| 2151 | |
| 2152 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2153 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2154 | u64 offset, u32 len, |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2155 | unsigned flags) |
| 2156 | { |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 2157 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2158 | int ret; |
| 2159 | |
| 2160 | ret = intel_ring_begin(ring, 4); |
| 2161 | if (ret) |
| 2162 | return ret; |
| 2163 | |
| 2164 | /* FIXME(BDW): Address space and security selectors. */ |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 2165 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2166 | intel_ring_emit(ring, lower_32_bits(offset)); |
| 2167 | intel_ring_emit(ring, upper_32_bits(offset)); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2168 | intel_ring_emit(ring, MI_NOOP); |
| 2169 | intel_ring_advance(ring); |
| 2170 | |
| 2171 | return 0; |
| 2172 | } |
| 2173 | |
| 2174 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2175 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2176 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2177 | unsigned flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2178 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2179 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2180 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2181 | ret = intel_ring_begin(ring, 2); |
| 2182 | if (ret) |
| 2183 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2184 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2185 | intel_ring_emit(ring, |
| 2186 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | |
| 2187 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); |
| 2188 | /* bit0-7 is the length on GEN6+ */ |
| 2189 | intel_ring_emit(ring, offset); |
| 2190 | intel_ring_advance(ring); |
| 2191 | |
| 2192 | return 0; |
| 2193 | } |
| 2194 | |
| 2195 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2196 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2197 | u64 offset, u32 len, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2198 | unsigned flags) |
| 2199 | { |
| 2200 | int ret; |
| 2201 | |
| 2202 | ret = intel_ring_begin(ring, 2); |
| 2203 | if (ret) |
| 2204 | return ret; |
| 2205 | |
| 2206 | intel_ring_emit(ring, |
| 2207 | MI_BATCH_BUFFER_START | |
| 2208 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2209 | /* bit0-7 is the length on GEN6+ */ |
| 2210 | intel_ring_emit(ring, offset); |
| 2211 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2212 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2213 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2214 | } |
| 2215 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2216 | /* Blitter support (SandyBridge+) */ |
| 2217 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2218 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2219 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2220 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2221 | struct drm_device *dev = ring->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2222 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2223 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2224 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 2225 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2226 | if (ret) |
| 2227 | return ret; |
| 2228 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2229 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2230 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 2231 | cmd += 1; |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2232 | /* |
| 2233 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 2234 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2235 | * operation is complete. This bit is only valid when the |
| 2236 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2237 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2238 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2239 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
Daniel Vetter | b3fcabb | 2012-11-04 12:24:47 +0100 | [diff] [blame] | 2240 | MI_FLUSH_DW_OP_STOREDW; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2241 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2242 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2243 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2244 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2245 | intel_ring_emit(ring, 0); /* value */ |
| 2246 | } else { |
| 2247 | intel_ring_emit(ring, 0); |
| 2248 | intel_ring_emit(ring, MI_NOOP); |
| 2249 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2250 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2251 | |
Ville Syrjälä | 9688eca | 2013-11-06 23:02:19 +0200 | [diff] [blame] | 2252 | if (IS_GEN7(dev) && !invalidate && flush) |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2253 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
| 2254 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2255 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2256 | } |
| 2257 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2258 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 2259 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2261 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2262 | struct drm_i915_gem_object *obj; |
| 2263 | int ret; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2264 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2265 | ring->name = "render ring"; |
| 2266 | ring->id = RCS; |
| 2267 | ring->mmio_base = RENDER_RING_BASE; |
| 2268 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2269 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2270 | if (i915_semaphore_is_enabled(dev)) { |
| 2271 | obj = i915_gem_alloc_object(dev, 4096); |
| 2272 | if (obj == NULL) { |
| 2273 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
| 2274 | i915.semaphores = 0; |
| 2275 | } else { |
| 2276 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2277 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); |
| 2278 | if (ret != 0) { |
| 2279 | drm_gem_object_unreference(&obj->base); |
| 2280 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
| 2281 | i915.semaphores = 0; |
| 2282 | } else |
| 2283 | dev_priv->semaphore_obj = obj; |
| 2284 | } |
| 2285 | } |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame^] | 2286 | if (IS_CHERRYVIEW(dev)) |
| 2287 | ring->init_context = chv_init_workarounds; |
| 2288 | else |
| 2289 | ring->init_context = bdw_init_workarounds; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2290 | ring->add_request = gen6_add_request; |
| 2291 | ring->flush = gen8_render_ring_flush; |
| 2292 | ring->irq_get = gen8_ring_get_irq; |
| 2293 | ring->irq_put = gen8_ring_put_irq; |
| 2294 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 2295 | ring->get_seqno = gen6_ring_get_seqno; |
| 2296 | ring->set_seqno = ring_set_seqno; |
| 2297 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2298 | WARN_ON(!dev_priv->semaphore_obj); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2299 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2300 | ring->semaphore.signal = gen8_rcs_signal; |
| 2301 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2302 | } |
| 2303 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2304 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 2305 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 2306 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 2307 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2308 | ring->irq_get = gen6_ring_get_irq; |
| 2309 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2310 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 2311 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2312 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2313 | if (i915_semaphore_is_enabled(dev)) { |
| 2314 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2315 | ring->semaphore.signal = gen6_signal; |
| 2316 | /* |
| 2317 | * The current semaphore is only applied on pre-gen8 |
| 2318 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2319 | * platform. So the semaphore between RCS and VCS2 is |
| 2320 | * initialized as INVALID. Gen8 will initialize the |
| 2321 | * sema between VCS2 and RCS later. |
| 2322 | */ |
| 2323 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2324 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 2325 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 2326 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 2327 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2328 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; |
| 2329 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; |
| 2330 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; |
| 2331 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; |
| 2332 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2333 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2334 | } else if (IS_GEN5(dev)) { |
| 2335 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2336 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2337 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2338 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2339 | ring->irq_get = gen5_ring_get_irq; |
| 2340 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2341 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 2342 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2343 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2344 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2345 | if (INTEL_INFO(dev)->gen < 4) |
| 2346 | ring->flush = gen2_render_ring_flush; |
| 2347 | else |
| 2348 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2349 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2350 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2351 | if (IS_GEN2(dev)) { |
| 2352 | ring->irq_get = i8xx_ring_get_irq; |
| 2353 | ring->irq_put = i8xx_ring_put_irq; |
| 2354 | } else { |
| 2355 | ring->irq_get = i9xx_ring_get_irq; |
| 2356 | ring->irq_put = i9xx_ring_put_irq; |
| 2357 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2358 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2359 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2360 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2361 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2362 | if (IS_HASWELL(dev)) |
| 2363 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2364 | else if (IS_GEN8(dev)) |
| 2365 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2366 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2367 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 2368 | else if (INTEL_INFO(dev)->gen >= 4) |
| 2369 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2370 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2371 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2372 | else |
| 2373 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2374 | ring->init = init_render_ring; |
| 2375 | ring->cleanup = render_ring_cleanup; |
| 2376 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2377 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 2378 | if (HAS_BROKEN_CS_TLB(dev)) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2379 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
| 2380 | if (obj == NULL) { |
| 2381 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 2382 | return -ENOMEM; |
| 2383 | } |
| 2384 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 2385 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2386 | if (ret != 0) { |
| 2387 | drm_gem_object_unreference(&obj->base); |
| 2388 | DRM_ERROR("Failed to ping batch bo\n"); |
| 2389 | return ret; |
| 2390 | } |
| 2391 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 2392 | ring->scratch.obj = obj; |
| 2393 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2394 | } |
| 2395 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2396 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2397 | } |
| 2398 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2399 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 2400 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2401 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2402 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2403 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2404 | int ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2405 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2406 | if (ringbuf == NULL) { |
| 2407 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 2408 | if (!ringbuf) |
| 2409 | return -ENOMEM; |
| 2410 | ring->buffer = ringbuf; |
| 2411 | } |
| 2412 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2413 | ring->name = "render ring"; |
| 2414 | ring->id = RCS; |
| 2415 | ring->mmio_base = RENDER_RING_BASE; |
| 2416 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2417 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 2418 | /* non-kms not supported on gen6+ */ |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2419 | ret = -ENODEV; |
| 2420 | goto err_ringbuf; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2421 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2422 | |
| 2423 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding |
| 2424 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up |
| 2425 | * the special gen5 functions. */ |
| 2426 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2427 | if (INTEL_INFO(dev)->gen < 4) |
| 2428 | ring->flush = gen2_render_ring_flush; |
| 2429 | else |
| 2430 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2431 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2432 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2433 | if (IS_GEN2(dev)) { |
| 2434 | ring->irq_get = i8xx_ring_get_irq; |
| 2435 | ring->irq_put = i8xx_ring_put_irq; |
| 2436 | } else { |
| 2437 | ring->irq_get = i9xx_ring_get_irq; |
| 2438 | ring->irq_put = i9xx_ring_put_irq; |
| 2439 | } |
Daniel Vetter | 28f0cbf | 2012-04-11 22:12:58 +0200 | [diff] [blame] | 2440 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2441 | ring->write_tail = ring_write_tail; |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2442 | if (INTEL_INFO(dev)->gen >= 4) |
| 2443 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2444 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2445 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2446 | else |
| 2447 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2448 | ring->init = init_render_ring; |
| 2449 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2450 | |
| 2451 | ring->dev = dev; |
| 2452 | INIT_LIST_HEAD(&ring->active_list); |
| 2453 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2454 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2455 | ringbuf->size = size; |
| 2456 | ringbuf->effective_size = ringbuf->size; |
Mika Kuoppala | 17f10fd | 2012-10-29 16:59:26 +0200 | [diff] [blame] | 2457 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2458 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2459 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2460 | ringbuf->virtual_start = ioremap_wc(start, size); |
| 2461 | if (ringbuf->virtual_start == NULL) { |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2462 | DRM_ERROR("can not ioremap virtual address for" |
| 2463 | " ring buffer\n"); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2464 | ret = -ENOMEM; |
| 2465 | goto err_ringbuf; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2466 | } |
| 2467 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2468 | if (!I915_NEED_GFX_HWS(dev)) { |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 2469 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2470 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2471 | goto err_vstart; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2472 | } |
| 2473 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2474 | return 0; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2475 | |
| 2476 | err_vstart: |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2477 | iounmap(ringbuf->virtual_start); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2478 | err_ringbuf: |
| 2479 | kfree(ringbuf); |
| 2480 | ring->buffer = NULL; |
| 2481 | return ret; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 2482 | } |
| 2483 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2484 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2485 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2486 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2487 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2488 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2489 | ring->name = "bsd ring"; |
| 2490 | ring->id = VCS; |
| 2491 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2492 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2493 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2494 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2495 | /* gen6 bsd needs a special wa for tail updates */ |
| 2496 | if (IS_GEN6(dev)) |
| 2497 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2498 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2499 | ring->add_request = gen6_add_request; |
| 2500 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2501 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2502 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2503 | ring->irq_enable_mask = |
| 2504 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2505 | ring->irq_get = gen8_ring_get_irq; |
| 2506 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2507 | ring->dispatch_execbuffer = |
| 2508 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2509 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2510 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2511 | ring->semaphore.signal = gen8_xcs_signal; |
| 2512 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2513 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2514 | } else { |
| 2515 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2516 | ring->irq_get = gen6_ring_get_irq; |
| 2517 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2518 | ring->dispatch_execbuffer = |
| 2519 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2520 | if (i915_semaphore_is_enabled(dev)) { |
| 2521 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2522 | ring->semaphore.signal = gen6_signal; |
| 2523 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2524 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2525 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 2526 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 2527 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2528 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; |
| 2529 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; |
| 2530 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; |
| 2531 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; |
| 2532 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2533 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2534 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2535 | } else { |
| 2536 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2537 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2538 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2539 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2540 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2541 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2542 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2543 | ring->irq_get = gen5_ring_get_irq; |
| 2544 | ring->irq_put = gen5_ring_put_irq; |
| 2545 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2546 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2547 | ring->irq_get = i9xx_ring_get_irq; |
| 2548 | ring->irq_put = i9xx_ring_put_irq; |
| 2549 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2550 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2551 | } |
| 2552 | ring->init = init_ring_common; |
| 2553 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2554 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2555 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2556 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2557 | /** |
| 2558 | * Initialize the second BSD ring for Broadwell GT3. |
| 2559 | * It is noted that this only exists on Broadwell GT3. |
| 2560 | */ |
| 2561 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) |
| 2562 | { |
| 2563 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2564 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2565 | |
| 2566 | if ((INTEL_INFO(dev)->gen != 8)) { |
| 2567 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); |
| 2568 | return -EINVAL; |
| 2569 | } |
| 2570 | |
Rodrigo Vivi | f7b6423 | 2014-07-01 02:41:36 -0700 | [diff] [blame] | 2571 | ring->name = "bsd2 ring"; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2572 | ring->id = VCS2; |
| 2573 | |
| 2574 | ring->write_tail = ring_write_tail; |
| 2575 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 2576 | ring->flush = gen6_bsd_ring_flush; |
| 2577 | ring->add_request = gen6_add_request; |
| 2578 | ring->get_seqno = gen6_ring_get_seqno; |
| 2579 | ring->set_seqno = ring_set_seqno; |
| 2580 | ring->irq_enable_mask = |
| 2581 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
| 2582 | ring->irq_get = gen8_ring_get_irq; |
| 2583 | ring->irq_put = gen8_ring_put_irq; |
| 2584 | ring->dispatch_execbuffer = |
| 2585 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2586 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2587 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2588 | ring->semaphore.signal = gen8_xcs_signal; |
| 2589 | GEN8_RING_SEMAPHORE_INIT; |
| 2590 | } |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2591 | ring->init = init_ring_common; |
| 2592 | |
| 2593 | return intel_init_ring_buffer(dev, ring); |
| 2594 | } |
| 2595 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2596 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2597 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2598 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2599 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2600 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2601 | ring->name = "blitter ring"; |
| 2602 | ring->id = BCS; |
| 2603 | |
| 2604 | ring->mmio_base = BLT_RING_BASE; |
| 2605 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2606 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2607 | ring->add_request = gen6_add_request; |
| 2608 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2609 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2610 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2611 | ring->irq_enable_mask = |
| 2612 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2613 | ring->irq_get = gen8_ring_get_irq; |
| 2614 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2615 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2616 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2617 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2618 | ring->semaphore.signal = gen8_xcs_signal; |
| 2619 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2620 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2621 | } else { |
| 2622 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2623 | ring->irq_get = gen6_ring_get_irq; |
| 2624 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2625 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2626 | if (i915_semaphore_is_enabled(dev)) { |
| 2627 | ring->semaphore.signal = gen6_signal; |
| 2628 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2629 | /* |
| 2630 | * The current semaphore is only applied on pre-gen8 |
| 2631 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2632 | * platform. So the semaphore between BCS and VCS2 is |
| 2633 | * initialized as INVALID. Gen8 will initialize the |
| 2634 | * sema between BCS and VCS2 later. |
| 2635 | */ |
| 2636 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2637 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2638 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2639 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 2640 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2641 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; |
| 2642 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; |
| 2643 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; |
| 2644 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; |
| 2645 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2646 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2647 | } |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2648 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2649 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2650 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2651 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2652 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2653 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2654 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2655 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2656 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2657 | |
| 2658 | ring->name = "video enhancement ring"; |
| 2659 | ring->id = VECS; |
| 2660 | |
| 2661 | ring->mmio_base = VEBOX_RING_BASE; |
| 2662 | ring->write_tail = ring_write_tail; |
| 2663 | ring->flush = gen6_ring_flush; |
| 2664 | ring->add_request = gen6_add_request; |
| 2665 | ring->get_seqno = gen6_ring_get_seqno; |
| 2666 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2667 | |
| 2668 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2669 | ring->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 2670 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2671 | ring->irq_get = gen8_ring_get_irq; |
| 2672 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2673 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2674 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2675 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2676 | ring->semaphore.signal = gen8_xcs_signal; |
| 2677 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2678 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2679 | } else { |
| 2680 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2681 | ring->irq_get = hsw_vebox_get_irq; |
| 2682 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2683 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2684 | if (i915_semaphore_is_enabled(dev)) { |
| 2685 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2686 | ring->semaphore.signal = gen6_signal; |
| 2687 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2688 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2689 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2690 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2691 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2692 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; |
| 2693 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; |
| 2694 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; |
| 2695 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; |
| 2696 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2697 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2698 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2699 | ring->init = init_ring_common; |
| 2700 | |
| 2701 | return intel_init_ring_buffer(dev, ring); |
| 2702 | } |
| 2703 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2704 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2705 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2706 | { |
| 2707 | int ret; |
| 2708 | |
| 2709 | if (!ring->gpu_caches_dirty) |
| 2710 | return 0; |
| 2711 | |
| 2712 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2713 | if (ret) |
| 2714 | return ret; |
| 2715 | |
| 2716 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2717 | |
| 2718 | ring->gpu_caches_dirty = false; |
| 2719 | return 0; |
| 2720 | } |
| 2721 | |
| 2722 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2723 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2724 | { |
| 2725 | uint32_t flush_domains; |
| 2726 | int ret; |
| 2727 | |
| 2728 | flush_domains = 0; |
| 2729 | if (ring->gpu_caches_dirty) |
| 2730 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2731 | |
| 2732 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2733 | if (ret) |
| 2734 | return ret; |
| 2735 | |
| 2736 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2737 | |
| 2738 | ring->gpu_caches_dirty = false; |
| 2739 | return 0; |
| 2740 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2741 | |
| 2742 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2743 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2744 | { |
| 2745 | int ret; |
| 2746 | |
| 2747 | if (!intel_ring_initialized(ring)) |
| 2748 | return; |
| 2749 | |
| 2750 | ret = intel_ring_idle(ring); |
| 2751 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 2752 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 2753 | ring->name, ret); |
| 2754 | |
| 2755 | stop_ring(ring); |
| 2756 | } |