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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Tejun Heo8c3d3d42013-05-14 11:09:50 -07004 * Maintained by: Tejun Heo <tj@kernel.org>
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04005 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020041#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050042#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090043#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090044#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040048#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090051#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010054 AHCI_PCI_BAR_STA2X11 = 0,
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -080055 AHCI_PCI_BAR_ENMOTUS = 2,
Alessandro Rubini318893e2012-01-06 13:33:39 +010056 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090057};
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Tejun Heo441577e2010-03-29 10:32:39 +090059enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
Levente Kurusa67809f82014-02-18 10:22:17 -050063 board_ahci_noncq,
Tejun Heo441577e2010-03-29 10:32:39 +090064 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020065 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090066
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090069 board_ahci_mcp77,
70 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090071 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090080 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081};
82
Jeff Garzik2dcb4072007-10-19 06:42:56 -040083static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090084static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
James Lairdcb856962013-11-19 11:06:38 +110086static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
Tejun Heoa1efdab2008-03-25 12:22:50 +090088static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090090#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090091static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090093#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
Tejun Heofad16e72010-09-21 09:25:48 +020095static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
Tejun Heo029cfd62008-03-25 12:22:49 +090099static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900101 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900102};
103
Tejun Heo029cfd62008-03-25 12:22:49 +0900104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900106 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900107};
108
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100109static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900110 /* by features */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530111 [board_ahci] = {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900112 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100113 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400114 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 .port_ops = &ahci_ops,
116 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530117 [board_ahci_ign_iferr] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100120 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400121 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900122 .port_ops = &ahci_ops,
123 },
Levente Kurusa67809f82014-02-18 10:22:17 -0500124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530131 [board_ahci_nosntf] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530138 [board_ahci_yes_fbs] = {
Tejun Heo5f173102010-07-24 16:53:48 +0200139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
Tejun Heo441577e2010-03-29 10:32:39 +0900145 /* by chipsets */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530146 [board_ahci_mcp65] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530154 [board_ahci_mcp77] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530161 [board_ahci_mcp89] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530168 [board_ahci_mv] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530176 [board_ahci_sb600] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900180 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100181 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400182 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800183 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800184 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530185 [board_ahci_sb700] = { /* for SB700 and SB800 */
Shane Huangbd172432008-06-10 15:52:04 +0800186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800187 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100188 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800189 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800190 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800191 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530192 [board_ahci_vt8251] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900194 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100195 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900196 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900197 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800198 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199};
200
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500201static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400202 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Seth Heasleyea4ace62012-01-23 16:27:30 -0800261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
James Ralston77b12bc92012-08-09 09:02:31 -0700269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
Seth Heasley29e674d2013-01-25 12:01:05 -0800277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
James Ralstonefda3322013-02-21 11:08:51 -0800293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
James Ralston151743f2013-02-08 17:34:47 -0800295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
Seth Heasley1cfc7df2013-06-19 16:36:45 -0700303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
James Ralston9f961a52013-11-04 09:24:58 -0800304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400308
Tejun Heoe34bb372007-02-26 20:24:03 +0900309 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
310 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
311 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Ben Hutchings1fefb8f2012-09-10 01:09:04 +0100312 /* JMicron 362B and 362C have an AHCI function with IDE class code */
313 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
314 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400315
316 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800317 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800318 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400324
Shane Huange2dd90b2009-07-29 11:34:49 +0800325 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800326 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huangfafe5c3d82013-06-03 18:24:10 +0800327 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
Shane Huange2dd90b2009-07-29 11:34:49 +0800328 /* AMD is using RAID class only for ahci controllers */
329 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
331
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400332 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400333 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900334 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400335
336 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900337 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900345 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400421
Jeff Garzik95916ed2006-07-29 04:10:14 -0400422 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400426
Alessandro Rubini318893e2012-01-06 13:33:39 +0100427 /* ST Microelectronics */
428 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
429
Jeff Garzikcd70c262007-07-08 02:29:42 -0400430 /* Marvell */
431 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100432 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500434 .class = PCI_CLASS_STORAGE_SATA_AHCI,
435 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200436 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
Per Jessen467b41c2011-02-08 13:54:32 +0100438 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Simon Guinote098f5c2013-12-23 13:24:35 +0100439 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
440 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
Matt Johnson642d8922012-04-27 01:42:30 -0500443 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
George Spelvinfcce9a32013-05-29 10:20:35 +0900444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600446 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
Alan Cox17c60c62012-09-04 16:07:18 +0100447 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
Myron Stowe69fd3152013-04-08 11:32:49 -0600448 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
Tejun Heo50be5e32010-11-29 15:57:14 +0100449 .driver_data = board_ahci_yes_fbs },
Samir Benmendil6d5278a2013-11-17 23:56:17 +0100450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
451 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400452
Mark Nelsonc77a0362008-10-23 14:08:16 +1100453 /* Promise */
454 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
455
Keng-Yu Linc9703762011-11-09 01:47:36 -0500456 /* Asmedia */
Alan Cox7b4f6ec2012-09-04 16:25:25 +0100457 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
458 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
459 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
460 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
Keng-Yu Linc9703762011-11-09 01:47:36 -0500461
Levente Kurusa67809f82014-02-18 10:22:17 -0500462 /*
463 * Samsung SSDs found on some macbooks. NCQ times out.
464 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
465 */
466 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
467
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -0800468 /* Enmotus */
469 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
470
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500471 /* Generic, PCI class code for AHCI */
472 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500473 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500474
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 { } /* terminate list */
476};
477
478
479static struct pci_driver ahci_pci_driver = {
480 .name = DRV_NAME,
481 .id_table = ahci_pci_tbl,
482 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900483 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900484#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900485 .suspend = ahci_pci_device_suspend,
486 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900487#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488};
489
Alan Cox5b66c822008-09-03 14:48:34 +0100490#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
491static int marvell_enable;
492#else
493static int marvell_enable = 1;
494#endif
495module_param(marvell_enable, int, 0644);
496MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
497
498
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300499static void ahci_pci_save_initial_config(struct pci_dev *pdev,
500 struct ahci_host_priv *hpriv)
501{
502 unsigned int force_port_map = 0;
503 unsigned int mask_port_map = 0;
504
505 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
506 dev_info(&pdev->dev, "JMB361 has only one port\n");
507 force_port_map = 1;
508 }
509
510 /*
511 * Temporary Marvell 6145 hack: PATA port presence
512 * is asserted through the standard AHCI port
513 * presence register, as bit 4 (counting from 0)
514 */
515 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
516 if (pdev->device == 0x6121)
517 mask_port_map = 0x3;
518 else
519 mask_port_map = 0xf;
520 dev_info(&pdev->dev,
521 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
522 }
523
Anton Vorontsov1d513352010-03-03 20:17:37 +0300524 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
525 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300526}
527
Anton Vorontsov33030402010-03-03 20:17:39 +0300528static int ahci_pci_reset_controller(struct ata_host *host)
529{
530 struct pci_dev *pdev = to_pci_dev(host->dev);
531
532 ahci_reset_controller(host);
533
Tejun Heod91542c2006-07-26 15:59:26 +0900534 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300535 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900536 u16 tmp16;
537
538 /* configure PCS */
539 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900540 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
541 tmp16 |= hpriv->port_map;
542 pci_write_config_word(pdev, 0x92, tmp16);
543 }
Tejun Heod91542c2006-07-26 15:59:26 +0900544 }
545
546 return 0;
547}
548
Anton Vorontsov781d6552010-03-03 20:17:42 +0300549static void ahci_pci_init_controller(struct ata_host *host)
550{
551 struct ahci_host_priv *hpriv = host->private_data;
552 struct pci_dev *pdev = to_pci_dev(host->dev);
553 void __iomem *port_mmio;
554 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100555 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900556
Tejun Heo417a1a62007-09-23 13:19:55 +0900557 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100558 if (pdev->device == 0x6121)
559 mv = 2;
560 else
561 mv = 4;
562 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400563
564 writel(0, port_mmio + PORT_IRQ_MASK);
565
566 /* clear port IRQ */
567 tmp = readl(port_mmio + PORT_IRQ_STAT);
568 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
569 if (tmp)
570 writel(tmp, port_mmio + PORT_IRQ_STAT);
571 }
572
Anton Vorontsov781d6552010-03-03 20:17:42 +0300573 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900574}
575
Tejun Heocc0680a2007-08-06 18:36:23 +0900576static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900577 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900578{
Tejun Heocc0680a2007-08-06 18:36:23 +0900579 struct ata_port *ap = link->ap;
Hans de Goede039ece32014-02-22 16:53:30 +0100580 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo9dadd452008-04-07 22:47:19 +0900581 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900582 int rc;
583
584 DPRINTK("ENTER\n");
585
Tejun Heo4447d352007-04-17 23:44:08 +0900586 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900587
Tejun Heocc0680a2007-08-06 18:36:23 +0900588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900589 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900590
Hans de Goede039ece32014-02-22 16:53:30 +0100591 hpriv->start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900592
593 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
594
595 /* vt8251 doesn't clear BSY on signature FIS reception,
596 * request follow-up softreset.
597 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900598 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900599}
600
Tejun Heoedc93052007-10-25 14:59:16 +0900601static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
602 unsigned long deadline)
603{
604 struct ata_port *ap = link->ap;
605 struct ahci_port_priv *pp = ap->private_data;
Hans de Goede039ece32014-02-22 16:53:30 +0100606 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heoedc93052007-10-25 14:59:16 +0900607 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
608 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900609 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900610 int rc;
611
612 ahci_stop_engine(ap);
613
614 /* clear D2H reception area to properly wait for D2H FIS */
615 ata_tf_init(link->device, &tf);
Sergei Shtylyov9bbb1b02013-06-23 01:39:39 +0400616 tf.command = ATA_BUSY;
Tejun Heoedc93052007-10-25 14:59:16 +0900617 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
618
619 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900620 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900621
Hans de Goede039ece32014-02-22 16:53:30 +0100622 hpriv->start_engine(ap);
Tejun Heoedc93052007-10-25 14:59:16 +0900623
Tejun Heoedc93052007-10-25 14:59:16 +0900624 /* The pseudo configuration device on SIMG4726 attached to
625 * ASUS P5W-DH Deluxe doesn't send signature FIS after
626 * hardreset if no device is attached to the first downstream
627 * port && the pseudo device locks up on SRST w/ PMP==0. To
628 * work around this, wait for !BSY only briefly. If BSY isn't
629 * cleared, perform CLO and proceed to IDENTIFY (achieved by
630 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
631 *
632 * Wait for two seconds. Devices attached to downstream port
633 * which can't process the following IDENTIFY after this will
634 * have to be reset again. For most cases, this should
635 * suffice while making probing snappish enough.
636 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900637 if (online) {
638 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
639 ahci_check_ready);
640 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800641 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900642 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900643 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900644}
645
Tejun Heo438ac6d2007-03-02 17:31:26 +0900646#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900647static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
648{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900649 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900650 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300651 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900652 u32 ctl;
653
Tejun Heo9b10ae82009-05-30 20:50:12 +0900654 if (mesg.event & PM_EVENT_SUSPEND &&
655 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700656 dev_err(&pdev->dev,
657 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +0900658 return -EIO;
659 }
660
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100661 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900662 /* AHCI spec rev1.1 section 8.3.3:
663 * Software must disable interrupts prior to requesting a
664 * transition of the HBA to D3 state.
665 */
666 ctl = readl(mmio + HOST_CTL);
667 ctl &= ~HOST_IRQ_EN;
668 writel(ctl, mmio + HOST_CTL);
669 readl(mmio + HOST_CTL); /* flush */
670 }
671
672 return ata_pci_device_suspend(pdev, mesg);
673}
674
675static int ahci_pci_device_resume(struct pci_dev *pdev)
676{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900677 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heoc1332872006-07-26 15:59:26 +0900678 int rc;
679
Tejun Heo553c4aa2006-12-26 19:39:50 +0900680 rc = ata_pci_device_do_resume(pdev);
681 if (rc)
682 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900683
James Lairdcb856962013-11-19 11:06:38 +1100684 /* Apple BIOS helpfully mangles the registers on resume */
685 if (is_mcp89_apple(pdev))
686 ahci_mcp89_apple_enable(pdev);
687
Tejun Heoc1332872006-07-26 15:59:26 +0900688 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300689 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900690 if (rc)
691 return rc;
692
Anton Vorontsov781d6552010-03-03 20:17:42 +0300693 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900694 }
695
Jeff Garzikcca39742006-08-24 03:19:22 -0400696 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900697
698 return 0;
699}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900700#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900701
Tejun Heo4447d352007-04-17 23:44:08 +0900702static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705
Alessandro Rubini318893e2012-01-06 13:33:39 +0100706 /*
707 * If the device fixup already set the dma_mask to some non-standard
708 * value, don't extend it here. This happens on STA2X11, for example.
709 */
710 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
711 return 0;
712
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700714 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
715 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700717 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700719 dev_err(&pdev->dev,
720 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 return rc;
722 }
723 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700725 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700727 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 return rc;
729 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700730 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700732 dev_err(&pdev->dev,
733 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 return rc;
735 }
736 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737 return 0;
738}
739
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300740static void ahci_pci_print_info(struct ata_host *host)
741{
742 struct pci_dev *pdev = to_pci_dev(host->dev);
743 u16 cc;
744 const char *scc_s;
745
746 pci_read_config_word(pdev, 0x0a, &cc);
747 if (cc == PCI_CLASS_STORAGE_IDE)
748 scc_s = "IDE";
749 else if (cc == PCI_CLASS_STORAGE_SATA)
750 scc_s = "SATA";
751 else if (cc == PCI_CLASS_STORAGE_RAID)
752 scc_s = "RAID";
753 else
754 scc_s = "unknown";
755
756 ahci_print_info(host, scc_s);
757}
758
Tejun Heoedc93052007-10-25 14:59:16 +0900759/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
760 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
761 * support PMP and the 4726 either directly exports the device
762 * attached to the first downstream port or acts as a hardware storage
763 * controller and emulate a single ATA device (can be RAID 0/1 or some
764 * other configuration).
765 *
766 * When there's no device attached to the first downstream port of the
767 * 4726, "Config Disk" appears, which is a pseudo ATA device to
768 * configure the 4726. However, ATA emulation of the device is very
769 * lame. It doesn't send signature D2H Reg FIS after the initial
770 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
771 *
772 * The following function works around the problem by always using
773 * hardreset on the port and not depending on receiving signature FIS
774 * afterward. If signature FIS isn't received soon, ATA class is
775 * assumed without follow-up softreset.
776 */
777static void ahci_p5wdh_workaround(struct ata_host *host)
778{
779 static struct dmi_system_id sysids[] = {
780 {
781 .ident = "P5W DH Deluxe",
782 .matches = {
783 DMI_MATCH(DMI_SYS_VENDOR,
784 "ASUSTEK COMPUTER INC"),
785 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
786 },
787 },
788 { }
789 };
790 struct pci_dev *pdev = to_pci_dev(host->dev);
791
792 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
793 dmi_check_system(sysids)) {
794 struct ata_port *ap = host->ports[1];
795
Joe Perchesa44fec12011-04-15 15:51:58 -0700796 dev_info(&pdev->dev,
797 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900798
799 ap->ops = &ahci_p5wdh_ops;
800 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
801 }
802}
803
James Lairdcb856962013-11-19 11:06:38 +1100804/*
805 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
806 * booting in BIOS compatibility mode. We restore the registers but not ID.
807 */
808static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
809{
810 u32 val;
811
812 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
813
814 pci_read_config_dword(pdev, 0xf8, &val);
815 val |= 1 << 0x1b;
816 /* the following changes the device ID, but appears not to affect function */
817 /* val = (val & ~0xf0000000) | 0x80000000; */
818 pci_write_config_dword(pdev, 0xf8, val);
819
820 pci_read_config_dword(pdev, 0x54c, &val);
821 val |= 1 << 0xc;
822 pci_write_config_dword(pdev, 0x54c, val);
823
824 pci_read_config_dword(pdev, 0x4a4, &val);
825 val &= 0xff;
826 val |= 0x01060100;
827 pci_write_config_dword(pdev, 0x4a4, val);
828
829 pci_read_config_dword(pdev, 0x54c, &val);
830 val &= ~(1 << 0xc);
831 pci_write_config_dword(pdev, 0x54c, val);
832
833 pci_read_config_dword(pdev, 0xf8, &val);
834 val &= ~(1 << 0x1b);
835 pci_write_config_dword(pdev, 0xf8, val);
836}
837
838static bool is_mcp89_apple(struct pci_dev *pdev)
839{
840 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
841 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
842 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
843 pdev->subsystem_device == 0xcb89;
844}
845
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900846/* only some SB600 ahci controllers can do 64bit DMA */
847static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800848{
849 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900850 /*
851 * The oldest version known to be broken is 0901 and
852 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900853 * Enable 64bit DMA on 1501 and anything newer.
854 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900855 * Please read bko#9412 for more info.
856 */
Shane Huang58a09b32009-05-27 15:04:43 +0800857 {
858 .ident = "ASUS M2A-VM",
859 .matches = {
860 DMI_MATCH(DMI_BOARD_VENDOR,
861 "ASUSTeK Computer INC."),
862 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
863 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900864 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800865 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100866 /*
867 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
868 * support 64bit DMA.
869 *
870 * BIOS versions earlier than 1.5 had the Manufacturer DMI
871 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
872 * This spelling mistake was fixed in BIOS version 1.5, so
873 * 1.5 and later have the Manufacturer as
874 * "MICRO-STAR INTERNATIONAL CO.,LTD".
875 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
876 *
877 * BIOS versions earlier than 1.9 had a Board Product Name
878 * DMI field of "MS-7376". This was changed to be
879 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
880 * match on DMI_BOARD_NAME of "MS-7376".
881 */
882 {
883 .ident = "MSI K9A2 Platinum",
884 .matches = {
885 DMI_MATCH(DMI_BOARD_VENDOR,
886 "MICRO-STAR INTER"),
887 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
888 },
889 },
Mark Nelson3c4aa912011-06-27 16:33:44 +1000890 /*
Mark Nelsonff0173c2012-06-28 12:32:14 +1000891 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
892 * 64bit DMA.
893 *
894 * This board also had the typo mentioned above in the
895 * Manufacturer DMI field (fixed in BIOS version 1.5), so
896 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
897 */
898 {
899 .ident = "MSI K9AGM2",
900 .matches = {
901 DMI_MATCH(DMI_BOARD_VENDOR,
902 "MICRO-STAR INTER"),
903 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
904 },
905 },
906 /*
Mark Nelson3c4aa912011-06-27 16:33:44 +1000907 * All BIOS versions for the Asus M3A support 64bit DMA.
908 * (all release versions from 0301 to 1206 were tested)
909 */
910 {
911 .ident = "ASUS M3A",
912 .matches = {
913 DMI_MATCH(DMI_BOARD_VENDOR,
914 "ASUSTeK Computer INC."),
915 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
916 },
917 },
Shane Huang58a09b32009-05-27 15:04:43 +0800918 { }
919 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900920 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900921 int year, month, date;
922 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800923
Tejun Heo03d783b2009-08-16 21:04:02 +0900924 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800925 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900926 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800927 return false;
928
Mark Nelsone65cc192009-11-03 20:06:48 +1100929 if (!match->driver_data)
930 goto enable_64bit;
931
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900932 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
933 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800934
Mark Nelsone65cc192009-11-03 20:06:48 +1100935 if (strcmp(buf, match->driver_data) >= 0)
936 goto enable_64bit;
937 else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700938 dev_warn(&pdev->dev,
939 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
940 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900941 return false;
942 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100943
944enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -0700945 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +1100946 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800947}
948
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100949static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
950{
951 static const struct dmi_system_id broken_systems[] = {
952 {
953 .ident = "HP Compaq nx6310",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
957 },
958 /* PCI slot number of the controller */
959 .driver_data = (void *)0x1FUL,
960 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100961 {
962 .ident = "HP Compaq 6720s",
963 .matches = {
964 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
965 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
966 },
967 /* PCI slot number of the controller */
968 .driver_data = (void *)0x1FUL,
969 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100970
971 { } /* terminate list */
972 };
973 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
974
975 if (dmi) {
976 unsigned long slot = (unsigned long)dmi->driver_data;
977 /* apply the quirk only to on-board controllers */
978 return slot == PCI_SLOT(pdev->devfn);
979 }
980
981 return false;
982}
983
Tejun Heo9b10ae82009-05-30 20:50:12 +0900984static bool ahci_broken_suspend(struct pci_dev *pdev)
985{
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
989 * to the harddisk doesn't become online after
990 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900991 *
992 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
993 *
994 * Use dates instead of versions to match as HP is
995 * apparently recycling both product and version
996 * strings.
997 *
998 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900999 */
1000 {
1001 .ident = "dv4",
1002 .matches = {
1003 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1004 DMI_MATCH(DMI_PRODUCT_NAME,
1005 "HP Pavilion dv4 Notebook PC"),
1006 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001007 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001008 },
1009 {
1010 .ident = "dv5",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1013 DMI_MATCH(DMI_PRODUCT_NAME,
1014 "HP Pavilion dv5 Notebook PC"),
1015 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001016 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001017 },
1018 {
1019 .ident = "dv6",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1022 DMI_MATCH(DMI_PRODUCT_NAME,
1023 "HP Pavilion dv6 Notebook PC"),
1024 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001025 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001026 },
1027 {
1028 .ident = "HDX18",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031 DMI_MATCH(DMI_PRODUCT_NAME,
1032 "HP HDX18 Notebook PC"),
1033 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001034 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001035 },
Tejun Heocedc9bf2010-01-28 16:04:15 +09001036 /*
1037 * Acer eMachines G725 has the same problem. BIOS
1038 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001039 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +09001040 * that we don't have much idea about. For now,
1041 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +09001042 *
1043 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +09001044 */
1045 {
1046 .ident = "G725",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1050 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001051 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +09001052 },
Tejun Heo9b10ae82009-05-30 20:50:12 +09001053 { } /* terminate list */
1054 };
1055 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +09001056 int year, month, date;
1057 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +09001058
1059 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1060 return false;
1061
Tejun Heo9deb3432010-03-16 09:50:26 +09001062 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1063 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +09001064
Tejun Heo9deb3432010-03-16 09:50:26 +09001065 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +09001066}
1067
Tejun Heo55946392009-08-04 14:30:08 +09001068static bool ahci_broken_online(struct pci_dev *pdev)
1069{
1070#define ENCODE_BUSDEVFN(bus, slot, func) \
1071 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1072 static const struct dmi_system_id sysids[] = {
1073 /*
1074 * There are several gigabyte boards which use
1075 * SIMG5723s configured as hardware RAID. Certain
1076 * 5723 firmware revisions shipped there keep the link
1077 * online but fail to answer properly to SRST or
1078 * IDENTIFY when no device is attached downstream
1079 * causing libata to retry quite a few times leading
1080 * to excessive detection delay.
1081 *
1082 * As these firmwares respond to the second reset try
1083 * with invalid device signature, considering unknown
1084 * sig as offline works around the problem acceptably.
1085 */
1086 {
1087 .ident = "EP45-DQ6",
1088 .matches = {
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "Gigabyte Technology Co., Ltd."),
1091 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1092 },
1093 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1094 },
1095 {
1096 .ident = "EP45-DS5",
1097 .matches = {
1098 DMI_MATCH(DMI_BOARD_VENDOR,
1099 "Gigabyte Technology Co., Ltd."),
1100 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1101 },
1102 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1103 },
1104 { } /* terminate list */
1105 };
1106#undef ENCODE_BUSDEVFN
1107 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1108 unsigned int val;
1109
1110 if (!dmi)
1111 return false;
1112
1113 val = (unsigned long)dmi->driver_data;
1114
1115 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1116}
1117
Jacob Pan0cf4a7d2014-04-15 22:27:11 -07001118static bool ahci_broken_devslp(struct pci_dev *pdev)
1119{
1120 /* device with broken DEVSLP but still showing SDS capability */
1121 static const struct pci_device_id ids[] = {
1122 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1123 {}
1124 };
1125
1126 return pci_match_id(ids, pdev);
1127}
1128
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001129#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09001130static void ahci_gtf_filter_workaround(struct ata_host *host)
1131{
1132 static const struct dmi_system_id sysids[] = {
1133 /*
1134 * Aspire 3810T issues a bunch of SATA enable commands
1135 * via _GTF including an invalid one and one which is
1136 * rejected by the device. Among the successful ones
1137 * is FPDMA non-zero offset enable which when enabled
1138 * only on the drive side leads to NCQ command
1139 * failures. Filter it out.
1140 */
1141 {
1142 .ident = "Aspire 3810T",
1143 .matches = {
1144 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1145 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1146 },
1147 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1148 },
1149 { }
1150 };
1151 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1152 unsigned int filter;
1153 int i;
1154
1155 if (!dmi)
1156 return;
1157
1158 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001159 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1160 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001161
1162 for (i = 0; i < host->n_ports; i++) {
1163 struct ata_port *ap = host->ports[i];
1164 struct ata_link *link;
1165 struct ata_device *dev;
1166
1167 ata_for_each_link(link, ap, EDGE)
1168 ata_for_each_dev(dev, link, ALL)
1169 dev->gtf_filter |= filter;
1170 }
1171}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001172#else
1173static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1174{}
1175#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001176
Linus Torvaldse1ba8452014-01-22 16:39:28 -08001177static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
Alexander Gordeevab0f9e72014-04-17 14:13:49 +02001178 struct ahci_host_priv *hpriv)
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001179{
Alexander Gordeevccf8f532014-04-17 14:13:50 +02001180 int rc, nvec;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001181
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001182 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1183 goto intx;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001184
Alexander Gordeevfc061d92014-01-29 14:19:43 -07001185 nvec = pci_msi_vec_count(pdev);
1186 if (nvec < 0)
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001187 goto intx;
1188
1189 /*
1190 * If number of MSIs is less than number of ports then Sharing Last
1191 * Message mode could be enforced. In this case assume that advantage
1192 * of multipe MSIs is negated and use single MSI mode instead.
1193 */
Alexander Gordeevfc061d92014-01-29 14:19:43 -07001194 if (nvec < n_ports)
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001195 goto single_msi;
1196
Alexander Gordeevccf8f532014-04-17 14:13:50 +02001197 rc = pci_enable_msi_exact(pdev, nvec);
1198 if (rc == -ENOSPC)
Alexander Gordeevfc403632014-02-14 14:27:19 -07001199 goto single_msi;
Alexander Gordeevccf8f532014-04-17 14:13:50 +02001200 else if (rc < 0)
Alexander Gordeevfc061d92014-01-29 14:19:43 -07001201 goto intx;
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001202
Alexander Gordeevab0f9e72014-04-17 14:13:49 +02001203 /* fallback to single MSI mode if the controller enforced MRSM mode */
1204 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1205 pci_disable_msi(pdev);
1206 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1207 goto single_msi;
1208 }
1209
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001210 return nvec;
1211
1212single_msi:
Alexander Gordeevfc061d92014-01-29 14:19:43 -07001213 if (pci_enable_msi(pdev))
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001214 goto intx;
1215 return 1;
1216
1217intx:
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001218 pci_intx(pdev, 1);
1219 return 0;
1220}
1221
1222/**
1223 * ahci_host_activate - start AHCI host, request IRQs and register it
1224 * @host: target ATA host
1225 * @irq: base IRQ number to request
1226 * @n_msis: number of MSIs allocated for this host
1227 * @irq_handler: irq_handler used when requesting IRQs
1228 * @irq_flags: irq_flags used when requesting IRQs
1229 *
1230 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1231 * when multiple MSIs were allocated. That is one MSI per port, starting
1232 * from @irq.
1233 *
1234 * LOCKING:
1235 * Inherited from calling layer (may sleep).
1236 *
1237 * RETURNS:
1238 * 0 on success, -errno otherwise.
1239 */
1240int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1241{
1242 int i, rc;
1243
1244 /* Sharing Last Message among several ports is not supported */
1245 if (n_msis < host->n_ports)
1246 return -EINVAL;
1247
1248 rc = ata_host_start(host);
1249 if (rc)
1250 return rc;
1251
1252 for (i = 0; i < host->n_ports; i++) {
Alexander Gordeevb29900e2013-05-22 08:53:48 +09001253 struct ahci_port_priv *pp = host->ports[i]->private_data;
1254
Alexander Gordeev2cf532f2014-04-17 18:06:15 +02001255 /* Do not receive interrupts sent by dummy ports */
1256 if (!pp) {
1257 disable_irq(irq + i);
1258 continue;
1259 }
1260
1261 rc = devm_request_threaded_irq(host->dev, irq + i,
1262 ahci_hw_interrupt,
1263 ahci_thread_fn, IRQF_SHARED,
1264 pp->irq_desc, host->ports[i]);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001265 if (rc)
1266 goto out_free_irqs;
1267 }
1268
1269 for (i = 0; i < host->n_ports; i++)
1270 ata_port_desc(host->ports[i], "irq %d", irq + i);
1271
1272 rc = ata_host_register(host, &ahci_sht);
1273 if (rc)
1274 goto out_free_all_irqs;
1275
1276 return 0;
1277
1278out_free_all_irqs:
1279 i = host->n_ports;
1280out_free_irqs:
1281 for (i--; i >= 0; i--)
1282 devm_free_irq(host->dev, irq + i, host->ports[i]);
1283
1284 return rc;
1285}
1286
Tejun Heo24dc5f32007-01-20 16:00:28 +09001287static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288{
Tejun Heoe297d992008-06-10 00:13:04 +09001289 unsigned int board_id = ent->driver_data;
1290 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001291 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001292 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001294 struct ata_host *host;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001295 int n_ports, n_msis, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001296 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297
1298 VPRINTK("ENTER\n");
1299
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001300 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001301
Joe Perches06296a12011-04-15 15:52:00 -07001302 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303
Alan Cox5b66c822008-09-03 14:48:34 +01001304 /* The AHCI driver can only drive the SATA ports, the PATA driver
1305 can drive them all so if both drivers are selected make sure
1306 AHCI stays out of the way */
1307 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1308 return -ENODEV;
1309
James Lairdcb856962013-11-19 11:06:38 +11001310 /* Apple BIOS on MCP89 prevents us using AHCI */
1311 if (is_mcp89_apple(pdev))
1312 ahci_mcp89_apple_enable(pdev);
Tejun Heoc6353b42010-06-17 11:42:22 +02001313
Mark Nelson7a022672009-11-22 12:07:41 +11001314 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1315 * At the moment, we can only use the AHCI mode. Let the users know
1316 * that for SAS drives they're out of luck.
1317 */
1318 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001319 dev_info(&pdev->dev,
1320 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001321
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001322 /* Both Connext and Enmotus devices use non-standard BARs */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001323 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1324 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001325 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1326 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001327
Tejun Heo4447d352007-04-17 23:44:08 +09001328 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001329 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330 if (rc)
1331 return rc;
1332
Tejun Heoc4f77922007-12-06 15:09:43 +09001333 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1334 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1335 u8 map;
1336
1337 /* ICH6s share the same PCI ID for both piix and ahci
1338 * modes. Enabling ahci mode while MAP indicates
1339 * combined mode is a bad idea. Yield to ata_piix.
1340 */
1341 pci_read_config_byte(pdev, ICH_MAP, &map);
1342 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001343 dev_info(&pdev->dev,
1344 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001345 return -ENODEV;
1346 }
1347 }
1348
Paul Bolle6fec8872013-12-16 11:34:21 +01001349 /* AHCI controllers often implement SFF compatible interface.
1350 * Grab all PCI BARs just in case.
1351 */
1352 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1353 if (rc == -EBUSY)
1354 pcim_pin_device(pdev);
1355 if (rc)
1356 return rc;
1357
Tejun Heo24dc5f32007-01-20 16:00:28 +09001358 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1359 if (!hpriv)
1360 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001361 hpriv->flags |= (unsigned long)pi.private_data;
1362
Tejun Heoe297d992008-06-10 00:13:04 +09001363 /* MCP65 revision A1 and A2 can't do MSI */
1364 if (board_id == board_ahci_mcp65 &&
1365 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1366 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1367
Shane Huange427fe02008-12-30 10:53:41 +08001368 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1369 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1370 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1371
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001372 /* only some SB600s can do 64bit DMA */
1373 if (ahci_sb600_enable_64bit(pdev))
1374 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001375
Alessandro Rubini318893e2012-01-06 13:33:39 +01001376 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001377
Jacob Pan0cf4a7d2014-04-15 22:27:11 -07001378 /* must set flag prior to save config in order to take effect */
1379 if (ahci_broken_devslp(pdev))
1380 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1381
Tejun Heo4447d352007-04-17 23:44:08 +09001382 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001383 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001384
Tejun Heo4447d352007-04-17 23:44:08 +09001385 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001386 if (hpriv->cap & HOST_CAP_NCQ) {
1387 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001388 /*
1389 * Auto-activate optimization is supposed to be
1390 * supported on all AHCI controllers indicating NCQ
1391 * capability, but it seems to be broken on some
1392 * chipsets including NVIDIAs.
1393 */
1394 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001395 pi.flags |= ATA_FLAG_FPDMA_AA;
Marc Carino40fb59e2013-08-24 23:22:49 -07001396
1397 /*
1398 * All AHCI controllers should be forward-compatible
1399 * with the new auxiliary field. This code should be
1400 * conditionalized if any buggy AHCI controllers are
1401 * encountered.
1402 */
1403 pi.flags |= ATA_FLAG_FPDMA_AUX;
Robert Hancock453d3132010-01-26 22:33:23 -06001404 }
Tejun Heo4447d352007-04-17 23:44:08 +09001405
Tejun Heo7d50b602007-09-23 13:19:54 +09001406 if (hpriv->cap & HOST_CAP_PMP)
1407 pi.flags |= ATA_FLAG_PMP;
1408
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001409 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001410
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001411 if (ahci_broken_system_poweroff(pdev)) {
1412 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1413 dev_info(&pdev->dev,
1414 "quirky BIOS, skipping spindown on poweroff\n");
1415 }
1416
Tejun Heo9b10ae82009-05-30 20:50:12 +09001417 if (ahci_broken_suspend(pdev)) {
1418 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001419 dev_warn(&pdev->dev,
1420 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001421 }
1422
Tejun Heo55946392009-08-04 14:30:08 +09001423 if (ahci_broken_online(pdev)) {
1424 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1425 dev_info(&pdev->dev,
1426 "online status unreliable, applying workaround\n");
1427 }
1428
Tejun Heo837f5f82008-02-06 15:13:51 +09001429 /* CAP.NP sometimes indicate the index of the last enabled
1430 * port, at other times, that of the last possible port, so
1431 * determining the maximum port number requires looking at
1432 * both CAP.NP and port_map.
1433 */
1434 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1435
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001436 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1437 if (n_msis > 1)
1438 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1439
Tejun Heo837f5f82008-02-06 15:13:51 +09001440 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001441 if (!host)
1442 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001443 host->private_data = hpriv;
1444
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001445 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001446 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001447 else
Jingoo Hand2782d92013-10-05 09:15:16 +09001448 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001449
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001450 if (pi.flags & ATA_FLAG_EM)
1451 ahci_reset_em(host);
1452
Tejun Heo4447d352007-04-17 23:44:08 +09001453 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001454 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001455
Alessandro Rubini318893e2012-01-06 13:33:39 +01001456 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1457 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001458 0x100 + ap->port_no * 0x80, "port");
1459
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001460 /* set enclosure management message type */
1461 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001462 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001463
1464
Jeff Garzikdab632e2007-05-28 08:33:01 -04001465 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001466 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001467 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001468 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469
Tejun Heoedc93052007-10-25 14:59:16 +09001470 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1471 ahci_p5wdh_workaround(host);
1472
Tejun Heof80ae7e2009-09-16 04:18:03 +09001473 /* apply gtf filter quirk */
1474 ahci_gtf_filter_workaround(host);
1475
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001477 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001479 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480
Anton Vorontsov33030402010-03-03 20:17:39 +03001481 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001482 if (rc)
1483 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001484
Anton Vorontsov781d6552010-03-03 20:17:42 +03001485 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001486 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487
Tejun Heo4447d352007-04-17 23:44:08 +09001488 pci_set_master(pdev);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001489
1490 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1491 return ahci_host_activate(host, pdev->irq, n_msis);
1492
Tejun Heo4447d352007-04-17 23:44:08 +09001493 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1494 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001495}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496
Axel Lin2fc75da2012-04-19 13:43:05 +08001497module_pci_driver(ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498
1499MODULE_AUTHOR("Jeff Garzik");
1500MODULE_DESCRIPTION("AHCI SATA low-level driver");
1501MODULE_LICENSE("GPL");
1502MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001503MODULE_VERSION(DRV_VERSION);