Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 43 | unsigned alignment, |
| 44 | bool map_and_fenceable); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 46 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 47 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 48 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 49 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 51 | struct drm_i915_gem_object *obj); |
| 52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 53 | struct drm_i915_fence_reg *fence, |
| 54 | bool enable); |
| 55 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 57 | struct shrink_control *sc); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 58 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 59 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 60 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 61 | { |
| 62 | if (obj->tiling_mode) |
| 63 | i915_gem_release_mmap(obj); |
| 64 | |
| 65 | /* As we do not have an associated fence register, we will force |
| 66 | * a tiling change if we ever need to acquire one. |
| 67 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 68 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 69 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 70 | } |
| 71 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 72 | /* some bookkeeping */ |
| 73 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 74 | size_t size) |
| 75 | { |
| 76 | dev_priv->mm.object_count++; |
| 77 | dev_priv->mm.object_memory += size; |
| 78 | } |
| 79 | |
| 80 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 81 | size_t size) |
| 82 | { |
| 83 | dev_priv->mm.object_count--; |
| 84 | dev_priv->mm.object_memory -= size; |
| 85 | } |
| 86 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 87 | static int |
| 88 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 89 | { |
| 90 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 91 | struct completion *x = &dev_priv->error_completion; |
| 92 | unsigned long flags; |
| 93 | int ret; |
| 94 | |
| 95 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 96 | return 0; |
| 97 | |
| 98 | ret = wait_for_completion_interruptible(x); |
| 99 | if (ret) |
| 100 | return ret; |
| 101 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 102 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 103 | /* GPU is hung, bump the completion count to account for |
| 104 | * the token we just consumed so that we never hit zero and |
| 105 | * end up waiting upon a subsequent completion event that |
| 106 | * will never happen. |
| 107 | */ |
| 108 | spin_lock_irqsave(&x->wait.lock, flags); |
| 109 | x->done++; |
| 110 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 111 | } |
| 112 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 113 | } |
| 114 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 115 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 116 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 117 | int ret; |
| 118 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 119 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 120 | if (ret) |
| 121 | return ret; |
| 122 | |
| 123 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 124 | if (ret) |
| 125 | return ret; |
| 126 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 127 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 128 | return 0; |
| 129 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 130 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 131 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 132 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 133 | { |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 134 | return !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 135 | } |
| 136 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 137 | int |
| 138 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 139 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 140 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 141 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 142 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 143 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 144 | return -ENODEV; |
| 145 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 146 | if (args->gtt_start >= args->gtt_end || |
| 147 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 148 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 150 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 151 | if (INTEL_INFO(dev)->gen >= 5) |
| 152 | return -ENODEV; |
| 153 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 154 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 155 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 156 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 157 | mutex_unlock(&dev->struct_mutex); |
| 158 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 159 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 160 | } |
| 161 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 162 | int |
| 163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 164 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 165 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 167 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 168 | struct drm_i915_gem_object *obj; |
| 169 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 170 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 171 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 172 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 173 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
| 174 | if (obj->pin_count) |
| 175 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 176 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 177 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 178 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 179 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 180 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 184 | static int |
| 185 | i915_gem_create(struct drm_file *file, |
| 186 | struct drm_device *dev, |
| 187 | uint64_t size, |
| 188 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 189 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 190 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 191 | int ret; |
| 192 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 193 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 194 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 195 | if (size == 0) |
| 196 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 197 | |
| 198 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 199 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 200 | if (obj == NULL) |
| 201 | return -ENOMEM; |
| 202 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 203 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 204 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 205 | drm_gem_object_release(&obj->base); |
| 206 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 207 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 208 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 209 | } |
| 210 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 211 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 212 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 213 | trace_i915_gem_object_create(obj); |
| 214 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 215 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 216 | return 0; |
| 217 | } |
| 218 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 219 | int |
| 220 | i915_gem_dumb_create(struct drm_file *file, |
| 221 | struct drm_device *dev, |
| 222 | struct drm_mode_create_dumb *args) |
| 223 | { |
| 224 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 225 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 226 | args->size = args->pitch * args->height; |
| 227 | return i915_gem_create(file, dev, |
| 228 | args->size, &args->handle); |
| 229 | } |
| 230 | |
| 231 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 232 | struct drm_device *dev, |
| 233 | uint32_t handle) |
| 234 | { |
| 235 | return drm_gem_handle_delete(file, handle); |
| 236 | } |
| 237 | |
| 238 | /** |
| 239 | * Creates a new mm object and returns a handle to it. |
| 240 | */ |
| 241 | int |
| 242 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 243 | struct drm_file *file) |
| 244 | { |
| 245 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 246 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 247 | return i915_gem_create(file, dev, |
| 248 | args->size, &args->handle); |
| 249 | } |
| 250 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 251 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 252 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 253 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 254 | |
| 255 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 256 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 257 | } |
| 258 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 259 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 260 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 261 | const char *gpu_vaddr, int gpu_offset, |
| 262 | int length) |
| 263 | { |
| 264 | int ret, cpu_offset = 0; |
| 265 | |
| 266 | while (length > 0) { |
| 267 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 268 | int this_length = min(cacheline_end - gpu_offset, length); |
| 269 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 270 | |
| 271 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 272 | gpu_vaddr + swizzled_gpu_offset, |
| 273 | this_length); |
| 274 | if (ret) |
| 275 | return ret + length; |
| 276 | |
| 277 | cpu_offset += this_length; |
| 278 | gpu_offset += this_length; |
| 279 | length -= this_length; |
| 280 | } |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 286 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 287 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 288 | int length) |
| 289 | { |
| 290 | int ret, cpu_offset = 0; |
| 291 | |
| 292 | while (length > 0) { |
| 293 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 294 | int this_length = min(cacheline_end - gpu_offset, length); |
| 295 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 296 | |
| 297 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 298 | cpu_vaddr + cpu_offset, |
| 299 | this_length); |
| 300 | if (ret) |
| 301 | return ret + length; |
| 302 | |
| 303 | cpu_offset += this_length; |
| 304 | gpu_offset += this_length; |
| 305 | length -= this_length; |
| 306 | } |
| 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 311 | /* Per-page copy function for the shmem pread fastpath. |
| 312 | * Flushes invalid cachelines before reading the target if |
| 313 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 314 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 315 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 316 | char __user *user_data, |
| 317 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 318 | { |
| 319 | char *vaddr; |
| 320 | int ret; |
| 321 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 322 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 323 | return -EINVAL; |
| 324 | |
| 325 | vaddr = kmap_atomic(page); |
| 326 | if (needs_clflush) |
| 327 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 328 | page_length); |
| 329 | ret = __copy_to_user_inatomic(user_data, |
| 330 | vaddr + shmem_page_offset, |
| 331 | page_length); |
| 332 | kunmap_atomic(vaddr); |
| 333 | |
| 334 | return ret; |
| 335 | } |
| 336 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 337 | static void |
| 338 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 339 | bool swizzled) |
| 340 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 341 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 342 | unsigned long start = (unsigned long) addr; |
| 343 | unsigned long end = (unsigned long) addr + length; |
| 344 | |
| 345 | /* For swizzling simply ensure that we always flush both |
| 346 | * channels. Lame, but simple and it works. Swizzled |
| 347 | * pwrite/pread is far from a hotpath - current userspace |
| 348 | * doesn't use it at all. */ |
| 349 | start = round_down(start, 128); |
| 350 | end = round_up(end, 128); |
| 351 | |
| 352 | drm_clflush_virt_range((void *)start, end - start); |
| 353 | } else { |
| 354 | drm_clflush_virt_range(addr, length); |
| 355 | } |
| 356 | |
| 357 | } |
| 358 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 359 | /* Only difference to the fast-path function is that this can handle bit17 |
| 360 | * and uses non-atomic copy and kmap functions. */ |
| 361 | static int |
| 362 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 363 | char __user *user_data, |
| 364 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 365 | { |
| 366 | char *vaddr; |
| 367 | int ret; |
| 368 | |
| 369 | vaddr = kmap(page); |
| 370 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 371 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 372 | page_length, |
| 373 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 374 | |
| 375 | if (page_do_bit17_swizzling) |
| 376 | ret = __copy_to_user_swizzled(user_data, |
| 377 | vaddr, shmem_page_offset, |
| 378 | page_length); |
| 379 | else |
| 380 | ret = __copy_to_user(user_data, |
| 381 | vaddr + shmem_page_offset, |
| 382 | page_length); |
| 383 | kunmap(page); |
| 384 | |
| 385 | return ret; |
| 386 | } |
| 387 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 388 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 389 | i915_gem_shmem_pread(struct drm_device *dev, |
| 390 | struct drm_i915_gem_object *obj, |
| 391 | struct drm_i915_gem_pread *args, |
| 392 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 393 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 394 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 395 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 396 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 397 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 398 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 399 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 400 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 401 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 402 | int needs_clflush = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 403 | int release_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 404 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 405 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 406 | remain = args->size; |
| 407 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 408 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 409 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 410 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 411 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 412 | * read domain and manually flush cachelines (if required). This |
| 413 | * optimizes for the case when the gpu will dirty the data |
| 414 | * anyway again before the next pread happens. */ |
| 415 | if (obj->cache_level == I915_CACHE_NONE) |
| 416 | needs_clflush = 1; |
| 417 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 418 | if (ret) |
| 419 | return ret; |
| 420 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 421 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 422 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 423 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 424 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 425 | struct page *page; |
| 426 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 427 | /* Operation in this page |
| 428 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 429 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 430 | * page_length = bytes to copy for this page |
| 431 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 432 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 433 | page_length = remain; |
| 434 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 435 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 436 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 437 | if (obj->pages) { |
| 438 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 439 | release_page = 0; |
| 440 | } else { |
| 441 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 442 | if (IS_ERR(page)) { |
| 443 | ret = PTR_ERR(page); |
| 444 | goto out; |
| 445 | } |
| 446 | release_page = 1; |
Jesper Juhl | b65552f | 2011-06-12 20:53:44 +0000 | [diff] [blame] | 447 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 448 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 449 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 450 | (page_to_phys(page) & (1 << 17)) != 0; |
| 451 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 452 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 453 | user_data, page_do_bit17_swizzling, |
| 454 | needs_clflush); |
| 455 | if (ret == 0) |
| 456 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 457 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 458 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 459 | page_cache_get(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 460 | mutex_unlock(&dev->struct_mutex); |
| 461 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 462 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 463 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 464 | /* Userspace is tricking us, but we've already clobbered |
| 465 | * its pages with the prefault and promised to write the |
| 466 | * data up to the first fault. Hence ignore any errors |
| 467 | * and just continue. */ |
| 468 | (void)ret; |
| 469 | prefaulted = 1; |
| 470 | } |
| 471 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 472 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 473 | user_data, page_do_bit17_swizzling, |
| 474 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 475 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 476 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 477 | page_cache_release(page); |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 478 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 479 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 480 | if (release_page) |
| 481 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 482 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 483 | if (ret) { |
| 484 | ret = -EFAULT; |
| 485 | goto out; |
| 486 | } |
| 487 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 488 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 489 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 490 | offset += page_length; |
| 491 | } |
| 492 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 493 | out: |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 494 | if (hit_slowpath) { |
| 495 | /* Fixup: Kill any reinstated backing storage pages */ |
| 496 | if (obj->madv == __I915_MADV_PURGED) |
| 497 | i915_gem_object_truncate(obj); |
| 498 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 499 | |
| 500 | return ret; |
| 501 | } |
| 502 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 503 | /** |
| 504 | * Reads data from the object referenced by handle. |
| 505 | * |
| 506 | * On error, the contents of *data are undefined. |
| 507 | */ |
| 508 | int |
| 509 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 510 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 511 | { |
| 512 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 513 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 514 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 515 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 516 | if (args->size == 0) |
| 517 | return 0; |
| 518 | |
| 519 | if (!access_ok(VERIFY_WRITE, |
| 520 | (char __user *)(uintptr_t)args->data_ptr, |
| 521 | args->size)) |
| 522 | return -EFAULT; |
| 523 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 524 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 525 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 526 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 527 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 528 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 529 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 530 | ret = -ENOENT; |
| 531 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 532 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 533 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 534 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 535 | if (args->offset > obj->base.size || |
| 536 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 537 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 538 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 539 | } |
| 540 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 541 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 542 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 543 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 544 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 545 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 546 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 547 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 548 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 549 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 550 | } |
| 551 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 552 | /* This is the fast write path which cannot handle |
| 553 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 554 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 555 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 556 | static inline int |
| 557 | fast_user_write(struct io_mapping *mapping, |
| 558 | loff_t page_base, int page_offset, |
| 559 | char __user *user_data, |
| 560 | int length) |
| 561 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 562 | void __iomem *vaddr_atomic; |
| 563 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 564 | unsigned long unwritten; |
| 565 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 566 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 567 | /* We can use the cpu mem copy function because this is X86. */ |
| 568 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 569 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 570 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 571 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 572 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 573 | } |
| 574 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 575 | /** |
| 576 | * This is the fast pwrite path, where we copy the data directly from the |
| 577 | * user into the GTT, uncached. |
| 578 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 579 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 580 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 581 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 582 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 583 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 584 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 585 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 586 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 587 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 588 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 589 | int page_offset, page_length, ret; |
| 590 | |
| 591 | ret = i915_gem_object_pin(obj, 0, true); |
| 592 | if (ret) |
| 593 | goto out; |
| 594 | |
| 595 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 596 | if (ret) |
| 597 | goto out_unpin; |
| 598 | |
| 599 | ret = i915_gem_object_put_fence(obj); |
| 600 | if (ret) |
| 601 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 602 | |
| 603 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 604 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 605 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 606 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 607 | |
| 608 | while (remain > 0) { |
| 609 | /* Operation in this page |
| 610 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 611 | * page_base = page offset within aperture |
| 612 | * page_offset = offset within page |
| 613 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 615 | page_base = offset & PAGE_MASK; |
| 616 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 617 | page_length = remain; |
| 618 | if ((page_offset + remain) > PAGE_SIZE) |
| 619 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 620 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 621 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 622 | * source page isn't available. Return the error and we'll |
| 623 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 624 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 625 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 626 | page_offset, user_data, page_length)) { |
| 627 | ret = -EFAULT; |
| 628 | goto out_unpin; |
| 629 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 630 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 631 | remain -= page_length; |
| 632 | user_data += page_length; |
| 633 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 635 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 636 | out_unpin: |
| 637 | i915_gem_object_unpin(obj); |
| 638 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 639 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 640 | } |
| 641 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 642 | /* Per-page copy function for the shmem pwrite fastpath. |
| 643 | * Flushes invalid cachelines before writing to the target if |
| 644 | * needs_clflush_before is set and flushes out any written cachelines after |
| 645 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 646 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 647 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 648 | char __user *user_data, |
| 649 | bool page_do_bit17_swizzling, |
| 650 | bool needs_clflush_before, |
| 651 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 652 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 653 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 654 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 655 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 656 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 657 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 658 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 659 | vaddr = kmap_atomic(page); |
| 660 | if (needs_clflush_before) |
| 661 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 662 | page_length); |
| 663 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 664 | user_data, |
| 665 | page_length); |
| 666 | if (needs_clflush_after) |
| 667 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 668 | page_length); |
| 669 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 670 | |
| 671 | return ret; |
| 672 | } |
| 673 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 674 | /* Only difference to the fast-path function is that this can handle bit17 |
| 675 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 676 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 677 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 678 | char __user *user_data, |
| 679 | bool page_do_bit17_swizzling, |
| 680 | bool needs_clflush_before, |
| 681 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 682 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 683 | char *vaddr; |
| 684 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 685 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 686 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 687 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 688 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 689 | page_length, |
| 690 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 691 | if (page_do_bit17_swizzling) |
| 692 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 693 | user_data, |
| 694 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 695 | else |
| 696 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 697 | user_data, |
| 698 | page_length); |
| 699 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 700 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 701 | page_length, |
| 702 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 703 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 704 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 705 | return ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 706 | } |
| 707 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 708 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 709 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 710 | struct drm_i915_gem_object *obj, |
| 711 | struct drm_i915_gem_pwrite *args, |
| 712 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 713 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 714 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 715 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 716 | loff_t offset; |
| 717 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 718 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 719 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 720 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 721 | int needs_clflush_after = 0; |
| 722 | int needs_clflush_before = 0; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 723 | int release_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 724 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 725 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 726 | remain = args->size; |
| 727 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 728 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 729 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 730 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 731 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 732 | * write domain and manually flush cachelines (if required). This |
| 733 | * optimizes for the case when the gpu will use the data |
| 734 | * right away and we therefore have to clflush anyway. */ |
| 735 | if (obj->cache_level == I915_CACHE_NONE) |
| 736 | needs_clflush_after = 1; |
| 737 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 738 | if (ret) |
| 739 | return ret; |
| 740 | } |
| 741 | /* Same trick applies for invalidate partially written cachelines before |
| 742 | * writing. */ |
| 743 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 744 | && obj->cache_level == I915_CACHE_NONE) |
| 745 | needs_clflush_before = 1; |
| 746 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 747 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 748 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 749 | |
| 750 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 751 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 752 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 753 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 754 | /* Operation in this page |
| 755 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 756 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 757 | * page_length = bytes to copy for this page |
| 758 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 759 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 760 | |
| 761 | page_length = remain; |
| 762 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 763 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 764 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 765 | /* If we don't overwrite a cacheline completely we need to be |
| 766 | * careful to have up-to-date data by first clflushing. Don't |
| 767 | * overcomplicate things and flush the entire patch. */ |
| 768 | partial_cacheline_write = needs_clflush_before && |
| 769 | ((shmem_page_offset | page_length) |
| 770 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 771 | |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 772 | if (obj->pages) { |
| 773 | page = obj->pages[offset >> PAGE_SHIFT]; |
| 774 | release_page = 0; |
| 775 | } else { |
| 776 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
| 777 | if (IS_ERR(page)) { |
| 778 | ret = PTR_ERR(page); |
| 779 | goto out; |
| 780 | } |
| 781 | release_page = 1; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 782 | } |
| 783 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 784 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 785 | (page_to_phys(page) & (1 << 17)) != 0; |
| 786 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 787 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 788 | user_data, page_do_bit17_swizzling, |
| 789 | partial_cacheline_write, |
| 790 | needs_clflush_after); |
| 791 | if (ret == 0) |
| 792 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 793 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 794 | hit_slowpath = 1; |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 795 | page_cache_get(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 796 | mutex_unlock(&dev->struct_mutex); |
| 797 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 798 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 799 | user_data, page_do_bit17_swizzling, |
| 800 | partial_cacheline_write, |
| 801 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 802 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 803 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 804 | page_cache_release(page); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 805 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 806 | set_page_dirty(page); |
| 807 | mark_page_accessed(page); |
Daniel Vetter | 692a576 | 2012-03-25 19:47:34 +0200 | [diff] [blame] | 808 | if (release_page) |
| 809 | page_cache_release(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 810 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 811 | if (ret) { |
| 812 | ret = -EFAULT; |
| 813 | goto out; |
| 814 | } |
| 815 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 817 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 818 | offset += page_length; |
| 819 | } |
| 820 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 821 | out: |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 822 | if (hit_slowpath) { |
| 823 | /* Fixup: Kill any reinstated backing storage pages */ |
| 824 | if (obj->madv == __I915_MADV_PURGED) |
| 825 | i915_gem_object_truncate(obj); |
| 826 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 827 | * domain anymore. */ |
| 828 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 829 | i915_gem_clflush_object(obj); |
| 830 | intel_gtt_chipset_flush(); |
| 831 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 832 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 833 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 834 | if (needs_clflush_after) |
| 835 | intel_gtt_chipset_flush(); |
| 836 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 837 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 838 | } |
| 839 | |
| 840 | /** |
| 841 | * Writes data to the object referenced by handle. |
| 842 | * |
| 843 | * On error, the contents of the buffer that were to be modified are undefined. |
| 844 | */ |
| 845 | int |
| 846 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 847 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 848 | { |
| 849 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 850 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 851 | int ret; |
| 852 | |
| 853 | if (args->size == 0) |
| 854 | return 0; |
| 855 | |
| 856 | if (!access_ok(VERIFY_READ, |
| 857 | (char __user *)(uintptr_t)args->data_ptr, |
| 858 | args->size)) |
| 859 | return -EFAULT; |
| 860 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 861 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 862 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 863 | if (ret) |
| 864 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 865 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 866 | ret = i915_mutex_lock_interruptible(dev); |
| 867 | if (ret) |
| 868 | return ret; |
| 869 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 870 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 871 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 872 | ret = -ENOENT; |
| 873 | goto unlock; |
| 874 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 875 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 876 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 877 | if (args->offset > obj->base.size || |
| 878 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 879 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 880 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 881 | } |
| 882 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 883 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 884 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 885 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 886 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 887 | * it would end up going through the fenced access, and we'll get |
| 888 | * different detiling behavior between reading and writing. |
| 889 | * pread/pwrite currently are reading and writing from the CPU |
| 890 | * perspective, requiring manual detiling by the client. |
| 891 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 892 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 893 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 894 | goto out; |
| 895 | } |
| 896 | |
| 897 | if (obj->gtt_space && |
Daniel Vetter | 3ae5378 | 2012-03-25 19:47:33 +0200 | [diff] [blame] | 898 | obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 899 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | ffc6297 | 2012-03-25 19:47:38 +0200 | [diff] [blame] | 900 | obj->map_and_fenceable && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 901 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 902 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 903 | /* Note that the gtt paths might fail with non-page-backed user |
| 904 | * pointers (e.g. gtt mappings when moving data between |
| 905 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 906 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 907 | |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 908 | if (ret == -EFAULT) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 909 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 910 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 911 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 912 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 913 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 914 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 915 | return ret; |
| 916 | } |
| 917 | |
| 918 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 919 | * Called when user space prepares to use an object with the CPU, either |
| 920 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 921 | */ |
| 922 | int |
| 923 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 924 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 925 | { |
| 926 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 927 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 928 | uint32_t read_domains = args->read_domains; |
| 929 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 930 | int ret; |
| 931 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 932 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 933 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 934 | return -EINVAL; |
| 935 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 936 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 937 | return -EINVAL; |
| 938 | |
| 939 | /* Having something in the write domain implies it's in the read |
| 940 | * domain, and only that read domain. Enforce that in the request. |
| 941 | */ |
| 942 | if (write_domain != 0 && read_domains != write_domain) |
| 943 | return -EINVAL; |
| 944 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 945 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 946 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 947 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 948 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 949 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 950 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 951 | ret = -ENOENT; |
| 952 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 953 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 954 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 955 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 956 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 957 | |
| 958 | /* Silently promote "you're not bound, there was nothing to do" |
| 959 | * to success, since the client was just asking us to |
| 960 | * make sure everything was done. |
| 961 | */ |
| 962 | if (ret == -EINVAL) |
| 963 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 964 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 965 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 966 | } |
| 967 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 968 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 969 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 970 | mutex_unlock(&dev->struct_mutex); |
| 971 | return ret; |
| 972 | } |
| 973 | |
| 974 | /** |
| 975 | * Called when user space has done writes to this buffer |
| 976 | */ |
| 977 | int |
| 978 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 979 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | { |
| 981 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 982 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 983 | int ret = 0; |
| 984 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 985 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 986 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 987 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 988 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 989 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 990 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 991 | ret = -ENOENT; |
| 992 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 993 | } |
| 994 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 995 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 996 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 997 | i915_gem_object_flush_cpu_write_domain(obj); |
| 998 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 999 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1000 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1001 | mutex_unlock(&dev->struct_mutex); |
| 1002 | return ret; |
| 1003 | } |
| 1004 | |
| 1005 | /** |
| 1006 | * Maps the contents of an object, returning the address it is mapped |
| 1007 | * into. |
| 1008 | * |
| 1009 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1010 | * imply a ref on the object itself. |
| 1011 | */ |
| 1012 | int |
| 1013 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1014 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1015 | { |
| 1016 | struct drm_i915_gem_mmap *args = data; |
| 1017 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1018 | unsigned long addr; |
| 1019 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1020 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1021 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1022 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1023 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1024 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1025 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1026 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1027 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1028 | if (IS_ERR((void *)addr)) |
| 1029 | return addr; |
| 1030 | |
| 1031 | args->addr_ptr = (uint64_t) addr; |
| 1032 | |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1036 | /** |
| 1037 | * i915_gem_fault - fault a page into the GTT |
| 1038 | * vma: VMA in question |
| 1039 | * vmf: fault info |
| 1040 | * |
| 1041 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1042 | * from userspace. The fault handler takes care of binding the object to |
| 1043 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1044 | * only if needed based on whether the old reg is still valid or the object |
| 1045 | * is tiled) and inserting a new PTE into the faulting process. |
| 1046 | * |
| 1047 | * Note that the faulting process may involve evicting existing objects |
| 1048 | * from the GTT and/or fence registers to make room. So performance may |
| 1049 | * suffer if the GTT working set is large or there are few fence registers |
| 1050 | * left. |
| 1051 | */ |
| 1052 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1053 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1054 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1055 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1056 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1057 | pgoff_t page_offset; |
| 1058 | unsigned long pfn; |
| 1059 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1060 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1061 | |
| 1062 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1063 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1064 | PAGE_SHIFT; |
| 1065 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1066 | ret = i915_mutex_lock_interruptible(dev); |
| 1067 | if (ret) |
| 1068 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1069 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1070 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1071 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1072 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1073 | if (!obj->map_and_fenceable) { |
| 1074 | ret = i915_gem_object_unbind(obj); |
| 1075 | if (ret) |
| 1076 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1077 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1078 | if (!obj->gtt_space) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1079 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1080 | if (ret) |
| 1081 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1082 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1083 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1084 | if (ret) |
| 1085 | goto unlock; |
| 1086 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1087 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1088 | if (!obj->has_global_gtt_mapping) |
| 1089 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1090 | |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1091 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1092 | if (ret) |
| 1093 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1094 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1095 | if (i915_gem_object_is_inactive(obj)) |
| 1096 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1097 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1098 | obj->fault_mappable = true; |
| 1099 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1100 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1101 | page_offset; |
| 1102 | |
| 1103 | /* Finally, remap it using the new GTT offset */ |
| 1104 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1105 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1106 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1107 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1108 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1109 | case -EIO: |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1110 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1111 | /* Give the error handler a chance to run and move the |
| 1112 | * objects off the GPU active list. Next time we service the |
| 1113 | * fault, we should be able to transition the page into the |
| 1114 | * GTT without touching the GPU (and so avoid further |
| 1115 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1116 | * with coherency, just lost writes. |
| 1117 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1118 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1119 | case 0: |
| 1120 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1121 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1122 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1123 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1124 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1125 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1126 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1127 | } |
| 1128 | } |
| 1129 | |
| 1130 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1131 | * i915_gem_release_mmap - remove physical page mappings |
| 1132 | * @obj: obj in question |
| 1133 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1134 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1135 | * relinquish ownership of the pages back to the system. |
| 1136 | * |
| 1137 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1138 | * object through the GTT and then lose the fence register due to |
| 1139 | * resource pressure. Similarly if the object has been moved out of the |
| 1140 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1141 | * mapping will then trigger a page fault on the next user access, allowing |
| 1142 | * fixup by i915_gem_fault(). |
| 1143 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1144 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1145 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1146 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1147 | if (!obj->fault_mappable) |
| 1148 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1149 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1150 | if (obj->base.dev->dev_mapping) |
| 1151 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1152 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1153 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1154 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1155 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1156 | } |
| 1157 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1158 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1159 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1160 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1161 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1162 | |
| 1163 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1164 | tiling_mode == I915_TILING_NONE) |
| 1165 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1166 | |
| 1167 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1168 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1169 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1170 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1171 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1172 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1173 | while (gtt_size < size) |
| 1174 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1175 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1176 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1177 | } |
| 1178 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1179 | /** |
| 1180 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1181 | * @obj: object to check |
| 1182 | * |
| 1183 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1184 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1185 | */ |
| 1186 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1187 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1188 | uint32_t size, |
| 1189 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1190 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1191 | /* |
| 1192 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1193 | * if a fence register is needed for the object. |
| 1194 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1195 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1196 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1197 | return 4096; |
| 1198 | |
| 1199 | /* |
| 1200 | * Previous chips need to be aligned to the size of the smallest |
| 1201 | * fence register that can contain the object. |
| 1202 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1203 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1204 | } |
| 1205 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1206 | /** |
| 1207 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1208 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1209 | * @dev: the device |
| 1210 | * @size: size of the object |
| 1211 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1212 | * |
| 1213 | * Return the required GTT alignment for an object, only taking into account |
| 1214 | * unfenced tiled surface requirements. |
| 1215 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1216 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1217 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1218 | uint32_t size, |
| 1219 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1220 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1221 | /* |
| 1222 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1223 | */ |
| 1224 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1225 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1226 | return 4096; |
| 1227 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1228 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1229 | * tile height. The simplest method for determining this is to reuse |
| 1230 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1231 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1232 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1233 | } |
| 1234 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1235 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1236 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1237 | struct drm_device *dev, |
| 1238 | uint32_t handle, |
| 1239 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1240 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1242 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1243 | int ret; |
| 1244 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1245 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1246 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1247 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1248 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1249 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1250 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1251 | ret = -ENOENT; |
| 1252 | goto unlock; |
| 1253 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1254 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1255 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1256 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1257 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1258 | } |
| 1259 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1260 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1261 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1262 | ret = -EINVAL; |
| 1263 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1264 | } |
| 1265 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1266 | if (!obj->base.map_list.map) { |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 1267 | ret = drm_gem_create_mmap_offset(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1268 | if (ret) |
| 1269 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1270 | } |
| 1271 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1272 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1273 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1274 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1275 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1276 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1277 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1278 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1279 | } |
| 1280 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1281 | /** |
| 1282 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1283 | * @dev: DRM device |
| 1284 | * @data: GTT mapping ioctl data |
| 1285 | * @file: GEM object info |
| 1286 | * |
| 1287 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1288 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1289 | * up so we can get faults in the handler above. |
| 1290 | * |
| 1291 | * The fault handler will take care of binding the object into the GTT |
| 1292 | * (since it may have been evicted to make room for something), allocating |
| 1293 | * a fence register, and mapping the appropriate aperture address into |
| 1294 | * userspace. |
| 1295 | */ |
| 1296 | int |
| 1297 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1298 | struct drm_file *file) |
| 1299 | { |
| 1300 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1301 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1302 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1303 | } |
| 1304 | |
| 1305 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1306 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1307 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1308 | gfp_t gfpmask) |
| 1309 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1310 | int page_count, i; |
| 1311 | struct address_space *mapping; |
| 1312 | struct inode *inode; |
| 1313 | struct page *page; |
| 1314 | |
| 1315 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1316 | * at this point until we release them. |
| 1317 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1318 | page_count = obj->base.size / PAGE_SIZE; |
| 1319 | BUG_ON(obj->pages != NULL); |
| 1320 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1321 | if (obj->pages == NULL) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1322 | return -ENOMEM; |
| 1323 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1324 | inode = obj->base.filp->f_path.dentry->d_inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1325 | mapping = inode->i_mapping; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1326 | gfpmask |= mapping_gfp_mask(mapping); |
| 1327 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1328 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1329 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1330 | if (IS_ERR(page)) |
| 1331 | goto err_pages; |
| 1332 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1333 | obj->pages[i] = page; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1334 | } |
| 1335 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1336 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1337 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1338 | |
| 1339 | return 0; |
| 1340 | |
| 1341 | err_pages: |
| 1342 | while (i--) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1343 | page_cache_release(obj->pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1344 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1345 | drm_free_large(obj->pages); |
| 1346 | obj->pages = NULL; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1347 | return PTR_ERR(page); |
| 1348 | } |
| 1349 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1350 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1351 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1352 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1353 | int page_count = obj->base.size / PAGE_SIZE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1354 | int i; |
| 1355 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1356 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1357 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1358 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1359 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1360 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1361 | if (obj->madv == I915_MADV_DONTNEED) |
| 1362 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1363 | |
| 1364 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1365 | if (obj->dirty) |
| 1366 | set_page_dirty(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1367 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1368 | if (obj->madv == I915_MADV_WILLNEED) |
| 1369 | mark_page_accessed(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1370 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1371 | page_cache_release(obj->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1372 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1373 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1374 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1375 | drm_free_large(obj->pages); |
| 1376 | obj->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1377 | } |
| 1378 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1379 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1380 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1381 | struct intel_ring_buffer *ring, |
| 1382 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1383 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1384 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1385 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1386 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1387 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1388 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1389 | |
| 1390 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1391 | if (!obj->active) { |
| 1392 | drm_gem_object_reference(&obj->base); |
| 1393 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1394 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1395 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1396 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1397 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1398 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1399 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1400 | obj->last_rendering_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1401 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1402 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1403 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1404 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1405 | /* Bump MRU to take account of the delayed flush */ |
| 1406 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1407 | struct drm_i915_fence_reg *reg; |
| 1408 | |
| 1409 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1410 | list_move_tail(®->lru_list, |
| 1411 | &dev_priv->mm.fence_list); |
| 1412 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1413 | } |
| 1414 | } |
| 1415 | |
| 1416 | static void |
| 1417 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) |
| 1418 | { |
| 1419 | list_del_init(&obj->ring_list); |
| 1420 | obj->last_rendering_seqno = 0; |
Daniel Vetter | 15a13bb | 2012-04-12 01:27:57 +0200 | [diff] [blame] | 1421 | obj->last_fenced_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1422 | } |
| 1423 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1424 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1425 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1426 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1427 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1428 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1429 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1430 | BUG_ON(!obj->active); |
| 1431 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1432 | |
| 1433 | i915_gem_object_move_off_active(obj); |
| 1434 | } |
| 1435 | |
| 1436 | static void |
| 1437 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1438 | { |
| 1439 | struct drm_device *dev = obj->base.dev; |
| 1440 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1441 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 1442 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1443 | |
| 1444 | BUG_ON(!list_empty(&obj->gpu_write_list)); |
| 1445 | BUG_ON(!obj->active); |
| 1446 | obj->ring = NULL; |
| 1447 | |
| 1448 | i915_gem_object_move_off_active(obj); |
| 1449 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1450 | |
| 1451 | obj->active = 0; |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 1452 | obj->pending_gpu_write = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1453 | drm_gem_object_unreference(&obj->base); |
| 1454 | |
| 1455 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1456 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1457 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1458 | /* Immediately discard the backing storage */ |
| 1459 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1460 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1461 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1462 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1463 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1464 | /* Our goal here is to return as much of the memory as |
| 1465 | * is possible back to the system as we are called from OOM. |
| 1466 | * To do this we must instruct the shmfs to drop all of its |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1467 | * backing pages, *now*. |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1468 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1469 | inode = obj->base.filp->f_path.dentry->d_inode; |
Hugh Dickins | e2377fe | 2011-06-27 16:18:19 -0700 | [diff] [blame] | 1470 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1471 | |
Chris Wilson | a14917e | 2012-02-24 21:13:38 +0000 | [diff] [blame] | 1472 | if (obj->base.map_list.map) |
| 1473 | drm_gem_free_mmap_offset(&obj->base); |
| 1474 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1475 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1476 | } |
| 1477 | |
| 1478 | static inline int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1479 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1480 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1481 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1484 | static void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1485 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
| 1486 | uint32_t flush_domains) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1487 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1488 | struct drm_i915_gem_object *obj, *next; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1489 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1490 | list_for_each_entry_safe(obj, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1491 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1492 | gpu_write_list) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1493 | if (obj->base.write_domain & flush_domains) { |
| 1494 | uint32_t old_write_domain = obj->base.write_domain; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1495 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1496 | obj->base.write_domain = 0; |
| 1497 | list_del_init(&obj->gpu_write_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1498 | i915_gem_object_move_to_active(obj, ring, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1499 | i915_gem_next_request_seqno(ring)); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1500 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1501 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1502 | obj->base.read_domains, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1503 | old_write_domain); |
| 1504 | } |
| 1505 | } |
| 1506 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1507 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1508 | static u32 |
| 1509 | i915_gem_get_seqno(struct drm_device *dev) |
| 1510 | { |
| 1511 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1512 | u32 seqno = dev_priv->next_seqno; |
| 1513 | |
| 1514 | /* reserve 0 for non-seqno */ |
| 1515 | if (++dev_priv->next_seqno == 0) |
| 1516 | dev_priv->next_seqno = 1; |
| 1517 | |
| 1518 | return seqno; |
| 1519 | } |
| 1520 | |
| 1521 | u32 |
| 1522 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1523 | { |
| 1524 | if (ring->outstanding_lazy_request == 0) |
| 1525 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1526 | |
| 1527 | return ring->outstanding_lazy_request; |
| 1528 | } |
| 1529 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1530 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1531 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1532 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1533 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1534 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1535 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1536 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1537 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1538 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1539 | int ret; |
| 1540 | |
| 1541 | BUG_ON(request == NULL); |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1542 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1543 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1544 | /* Record the position of the start of the request so that |
| 1545 | * should we detect the updated seqno part-way through the |
| 1546 | * GPU processing the request, we never over-estimate the |
| 1547 | * position of the head. |
| 1548 | */ |
| 1549 | request_ring_position = intel_ring_get_tail(ring); |
| 1550 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1551 | ret = ring->add_request(ring, &seqno); |
| 1552 | if (ret) |
| 1553 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1554 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1555 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1556 | |
| 1557 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1558 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1559 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1560 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1561 | was_empty = list_empty(&ring->request_list); |
| 1562 | list_add_tail(&request->list, &ring->request_list); |
| 1563 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1564 | if (file) { |
| 1565 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 1566 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1567 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1568 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1569 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1570 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1571 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1572 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1573 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 1574 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1575 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1576 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1577 | if (i915_enable_hangcheck) { |
| 1578 | mod_timer(&dev_priv->hangcheck_timer, |
| 1579 | jiffies + |
| 1580 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
| 1581 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1582 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1583 | queue_delayed_work(dev_priv->wq, |
| 1584 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1585 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1586 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1587 | } |
| 1588 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1589 | static inline void |
| 1590 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1591 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1592 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1593 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1594 | if (!file_priv) |
| 1595 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1596 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1597 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 1598 | if (request->file_priv) { |
| 1599 | list_del(&request->client_list); |
| 1600 | request->file_priv = NULL; |
| 1601 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1602 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1603 | } |
| 1604 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1605 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1606 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1607 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1608 | while (!list_empty(&ring->request_list)) { |
| 1609 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1610 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1611 | request = list_first_entry(&ring->request_list, |
| 1612 | struct drm_i915_gem_request, |
| 1613 | list); |
| 1614 | |
| 1615 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1616 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1617 | kfree(request); |
| 1618 | } |
| 1619 | |
| 1620 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1621 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1622 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1623 | obj = list_first_entry(&ring->active_list, |
| 1624 | struct drm_i915_gem_object, |
| 1625 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1626 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1627 | obj->base.write_domain = 0; |
| 1628 | list_del_init(&obj->gpu_write_list); |
| 1629 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1630 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1631 | } |
| 1632 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1633 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 1634 | { |
| 1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1636 | int i; |
| 1637 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1638 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1639 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1640 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1641 | i915_gem_write_fence(dev, i, NULL); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1642 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1643 | if (reg->obj) |
| 1644 | i915_gem_object_fence_lost(reg->obj); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 1645 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1646 | reg->pin_count = 0; |
| 1647 | reg->obj = NULL; |
| 1648 | INIT_LIST_HEAD(®->lru_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1649 | } |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 1650 | |
| 1651 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1652 | } |
| 1653 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1654 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1655 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1656 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1657 | struct drm_i915_gem_object *obj; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1658 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1659 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1660 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1661 | for_each_ring(ring, dev_priv, i) |
| 1662 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1663 | |
| 1664 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1665 | * to be lost on reset along with the data, so simply move the |
| 1666 | * lost bo to the inactive list. |
| 1667 | */ |
| 1668 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1669 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1670 | struct drm_i915_gem_object, |
| 1671 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1672 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1673 | obj->base.write_domain = 0; |
| 1674 | list_del_init(&obj->gpu_write_list); |
| 1675 | i915_gem_object_move_to_inactive(obj); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1676 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1677 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1678 | /* Move everything out of the GPU domains to ensure we do any |
| 1679 | * necessary invalidation upon reuse. |
| 1680 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1681 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1682 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1683 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1684 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1685 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1686 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1687 | |
| 1688 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 1689 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1690 | } |
| 1691 | |
| 1692 | /** |
| 1693 | * This function clears the request list as sequence numbers are passed. |
| 1694 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1695 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1696 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1698 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1699 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1700 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1701 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1702 | return; |
| 1703 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1704 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1706 | seqno = ring->get_seqno(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1707 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 1708 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1709 | if (seqno >= ring->sync_seqno[i]) |
| 1710 | ring->sync_seqno[i] = 0; |
| 1711 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1712 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1713 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1715 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1716 | struct drm_i915_gem_request, |
| 1717 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1718 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1719 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1720 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1721 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1722 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1723 | /* We know the GPU must have read the request to have |
| 1724 | * sent us the seqno + interrupt, so use the position |
| 1725 | * of tail of the request to update the last known position |
| 1726 | * of the GPU head. |
| 1727 | */ |
| 1728 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1729 | |
| 1730 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1731 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1732 | kfree(request); |
| 1733 | } |
| 1734 | |
| 1735 | /* Move any buffers on the active list that are no longer referenced |
| 1736 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1737 | */ |
| 1738 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1739 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1740 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1741 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1742 | struct drm_i915_gem_object, |
| 1743 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1744 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1745 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1746 | break; |
| 1747 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1748 | if (obj->base.write_domain != 0) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1749 | i915_gem_object_move_to_flushing(obj); |
| 1750 | else |
| 1751 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1752 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1753 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1754 | if (unlikely(ring->trace_irq_seqno && |
| 1755 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1756 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1757 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1758 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1759 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1760 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1761 | } |
| 1762 | |
| 1763 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1764 | i915_gem_retire_requests(struct drm_device *dev) |
| 1765 | { |
| 1766 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1767 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1768 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1769 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1770 | for_each_ring(ring, dev_priv, i) |
| 1771 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1772 | } |
| 1773 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 1774 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1775 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1776 | { |
| 1777 | drm_i915_private_t *dev_priv; |
| 1778 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1779 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1780 | bool idle; |
| 1781 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1782 | |
| 1783 | dev_priv = container_of(work, drm_i915_private_t, |
| 1784 | mm.retire_work.work); |
| 1785 | dev = dev_priv->dev; |
| 1786 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 1787 | /* Come back later if the device is busy... */ |
| 1788 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 1789 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1790 | return; |
| 1791 | } |
| 1792 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1793 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1794 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1795 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 1796 | * objects indefinitely. |
| 1797 | */ |
| 1798 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1799 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1800 | if (!list_empty(&ring->gpu_write_list)) { |
| 1801 | struct drm_i915_gem_request *request; |
| 1802 | int ret; |
| 1803 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1804 | ret = i915_gem_flush_ring(ring, |
| 1805 | 0, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1806 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1807 | if (ret || request == NULL || |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1808 | i915_add_request(ring, NULL, request)) |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1809 | kfree(request); |
| 1810 | } |
| 1811 | |
| 1812 | idle &= list_empty(&ring->request_list); |
| 1813 | } |
| 1814 | |
| 1815 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1816 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 1817 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1818 | mutex_unlock(&dev->struct_mutex); |
| 1819 | } |
| 1820 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1821 | static int |
| 1822 | i915_gem_check_wedge(struct drm_i915_private *dev_priv) |
| 1823 | { |
| 1824 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
| 1825 | |
| 1826 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 1827 | struct completion *x = &dev_priv->error_completion; |
| 1828 | bool recovery_complete; |
| 1829 | unsigned long flags; |
| 1830 | |
| 1831 | /* Give the error handler a chance to run. */ |
| 1832 | spin_lock_irqsave(&x->wait.lock, flags); |
| 1833 | recovery_complete = x->done > 0; |
| 1834 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 1835 | |
| 1836 | return recovery_complete ? -EIO : -EAGAIN; |
| 1837 | } |
| 1838 | |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
| 1842 | /* |
| 1843 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 1844 | * equal. |
| 1845 | */ |
| 1846 | static int |
| 1847 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 1848 | { |
| 1849 | int ret = 0; |
| 1850 | |
| 1851 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 1852 | |
| 1853 | if (seqno == ring->outstanding_lazy_request) { |
| 1854 | struct drm_i915_gem_request *request; |
| 1855 | |
| 1856 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 1857 | if (request == NULL) |
| 1858 | return -ENOMEM; |
| 1859 | |
| 1860 | ret = i915_add_request(ring, NULL, request); |
| 1861 | if (ret) { |
| 1862 | kfree(request); |
| 1863 | return ret; |
| 1864 | } |
| 1865 | |
| 1866 | BUG_ON(seqno != request->seqno); |
| 1867 | } |
| 1868 | |
| 1869 | return ret; |
| 1870 | } |
| 1871 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1872 | /** |
| 1873 | * __wait_seqno - wait until execution of seqno has finished |
| 1874 | * @ring: the ring expected to report seqno |
| 1875 | * @seqno: duh! |
| 1876 | * @interruptible: do an interruptible wait (normally yes) |
| 1877 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1878 | * |
| 1879 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1880 | * errno with remaining time filled in timeout argument. |
| 1881 | */ |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1882 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1883 | bool interruptible, struct timespec *timeout) |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1884 | { |
| 1885 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1886 | struct timespec before, now, wait_time={1,0}; |
| 1887 | unsigned long timeout_jiffies; |
| 1888 | long end; |
| 1889 | bool wait_forever = true; |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1890 | |
| 1891 | if (i915_seqno_passed(ring->get_seqno(ring), seqno)) |
| 1892 | return 0; |
| 1893 | |
| 1894 | trace_i915_gem_request_wait_begin(ring, seqno); |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1895 | |
| 1896 | if (timeout != NULL) { |
| 1897 | wait_time = *timeout; |
| 1898 | wait_forever = false; |
| 1899 | } |
| 1900 | |
| 1901 | timeout_jiffies = timespec_to_jiffies(&wait_time); |
| 1902 | |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1903 | if (WARN_ON(!ring->irq_get(ring))) |
| 1904 | return -ENODEV; |
| 1905 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1906 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1907 | getrawmonotonic(&before); |
| 1908 | |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1909 | #define EXIT_COND \ |
| 1910 | (i915_seqno_passed(ring->get_seqno(ring), seqno) || \ |
| 1911 | atomic_read(&dev_priv->mm.wedged)) |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1912 | do { |
| 1913 | if (interruptible) |
| 1914 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1915 | EXIT_COND, |
| 1916 | timeout_jiffies); |
| 1917 | else |
| 1918 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1919 | timeout_jiffies); |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1920 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1921 | if (atomic_read(&dev_priv->mm.wedged)) |
| 1922 | end = -EAGAIN; |
| 1923 | } while (end == 0 && wait_forever); |
| 1924 | |
| 1925 | getrawmonotonic(&now); |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1926 | |
| 1927 | ring->irq_put(ring); |
| 1928 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1929 | #undef EXIT_COND |
| 1930 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1931 | if (timeout) { |
| 1932 | struct timespec sleep_time = timespec_sub(now, before); |
| 1933 | *timeout = timespec_sub(*timeout, sleep_time); |
| 1934 | } |
| 1935 | |
| 1936 | switch (end) { |
| 1937 | case -EAGAIN: /* Wedged */ |
| 1938 | case -ERESTARTSYS: /* Signal */ |
| 1939 | return (int)end; |
| 1940 | case 0: /* Timeout */ |
| 1941 | if (timeout) |
| 1942 | set_normalized_timespec(timeout, 0, 0); |
| 1943 | return -ETIME; |
| 1944 | default: /* Completed */ |
| 1945 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 1946 | return 0; |
| 1947 | } |
Ben Widawsky | 604dd3e | 2012-04-26 16:03:03 -0700 | [diff] [blame] | 1948 | } |
| 1949 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1950 | /** |
| 1951 | * Waits for a sequence number to be signaled, and cleans up the |
| 1952 | * request and object lists appropriately for that event. |
| 1953 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1954 | int |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1955 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1956 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1957 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1958 | int ret = 0; |
| 1959 | |
| 1960 | BUG_ON(seqno == 0); |
| 1961 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1962 | ret = i915_gem_check_wedge(dev_priv); |
| 1963 | if (ret) |
| 1964 | return ret; |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1965 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 1966 | ret = i915_gem_check_olr(ring, seqno); |
| 1967 | if (ret) |
| 1968 | return ret; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1969 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 1970 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1971 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1972 | return ret; |
| 1973 | } |
| 1974 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1975 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1976 | * Ensures that all rendering to the object has completed and the object is |
| 1977 | * safe to unbind from the GTT or access from the CPU. |
| 1978 | */ |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1979 | int |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1980 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1981 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1982 | int ret; |
| 1983 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1984 | /* This function only exists to support waiting for existing rendering, |
| 1985 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1986 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1987 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1988 | |
| 1989 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1990 | * it. |
| 1991 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1992 | if (obj->active) { |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 1993 | ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1994 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1995 | return ret; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1996 | i915_gem_retire_requests_ring(obj->ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1997 | } |
| 1998 | |
| 1999 | return 0; |
| 2000 | } |
| 2001 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2002 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2003 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2004 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2005 | * |
| 2006 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2007 | * the timeout parameter. |
| 2008 | * -ETIME: object is still busy after timeout |
| 2009 | * -ERESTARTSYS: signal interrupted the wait |
| 2010 | * -ENONENT: object doesn't exist |
| 2011 | * Also possible, but rare: |
| 2012 | * -EAGAIN: GPU wedged |
| 2013 | * -ENOMEM: damn |
| 2014 | * -ENODEV: Internal IRQ fail |
| 2015 | * -E?: The add request failed |
| 2016 | * |
| 2017 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2018 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2019 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2020 | * without holding struct_mutex the object may become re-busied before this |
| 2021 | * function completes. A similar but shorter * race condition exists in the busy |
| 2022 | * ioctl |
| 2023 | */ |
| 2024 | int |
| 2025 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2026 | { |
| 2027 | struct drm_i915_gem_wait *args = data; |
| 2028 | struct drm_i915_gem_object *obj; |
| 2029 | struct intel_ring_buffer *ring = NULL; |
| 2030 | struct timespec timeout; |
| 2031 | u32 seqno = 0; |
| 2032 | int ret = 0; |
| 2033 | |
| 2034 | timeout = ns_to_timespec(args->timeout_ns); |
| 2035 | |
| 2036 | ret = i915_mutex_lock_interruptible(dev); |
| 2037 | if (ret) |
| 2038 | return ret; |
| 2039 | |
| 2040 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2041 | if (&obj->base == NULL) { |
| 2042 | mutex_unlock(&dev->struct_mutex); |
| 2043 | return -ENOENT; |
| 2044 | } |
| 2045 | |
| 2046 | /* Need to make sure the object is flushed first. This non-obvious |
| 2047 | * flush is required to enforce that (active && !olr) == no wait |
| 2048 | * necessary. |
| 2049 | */ |
| 2050 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2051 | if (ret) |
| 2052 | goto out; |
| 2053 | |
| 2054 | if (obj->active) { |
| 2055 | seqno = obj->last_rendering_seqno; |
| 2056 | ring = obj->ring; |
| 2057 | } |
| 2058 | |
| 2059 | if (seqno == 0) |
| 2060 | goto out; |
| 2061 | |
| 2062 | ret = i915_gem_check_olr(ring, seqno); |
| 2063 | if (ret) |
| 2064 | goto out; |
| 2065 | |
| 2066 | /* Do this after OLR check to make sure we make forward progress polling |
| 2067 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2068 | */ |
| 2069 | if (!args->timeout_ns) { |
| 2070 | ret = -ETIME; |
| 2071 | goto out; |
| 2072 | } |
| 2073 | |
| 2074 | drm_gem_object_unreference(&obj->base); |
| 2075 | mutex_unlock(&dev->struct_mutex); |
| 2076 | |
| 2077 | ret = __wait_seqno(ring, seqno, true, &timeout); |
| 2078 | WARN_ON(!timespec_valid(&timeout)); |
| 2079 | args->timeout_ns = timespec_to_ns(&timeout); |
| 2080 | return ret; |
| 2081 | |
| 2082 | out: |
| 2083 | drm_gem_object_unreference(&obj->base); |
| 2084 | mutex_unlock(&dev->struct_mutex); |
| 2085 | return ret; |
| 2086 | } |
| 2087 | |
| 2088 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2089 | * i915_gem_object_sync - sync an object to a ring. |
| 2090 | * |
| 2091 | * @obj: object which may be in use on another ring. |
| 2092 | * @to: ring we wish to use the object on. May be NULL. |
| 2093 | * |
| 2094 | * This code is meant to abstract object synchronization with the GPU. |
| 2095 | * Calling with NULL implies synchronizing the object with the CPU |
| 2096 | * rather than a particular GPU ring. |
| 2097 | * |
| 2098 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2099 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2100 | int |
| 2101 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2102 | struct intel_ring_buffer *to) |
| 2103 | { |
| 2104 | struct intel_ring_buffer *from = obj->ring; |
| 2105 | u32 seqno; |
| 2106 | int ret, idx; |
| 2107 | |
| 2108 | if (from == NULL || to == from) |
| 2109 | return 0; |
| 2110 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2111 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2112 | return i915_gem_object_wait_rendering(obj); |
| 2113 | |
| 2114 | idx = intel_ring_sync_index(from, to); |
| 2115 | |
| 2116 | seqno = obj->last_rendering_seqno; |
| 2117 | if (seqno <= from->sync_seqno[idx]) |
| 2118 | return 0; |
| 2119 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2120 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2121 | if (ret) |
| 2122 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2123 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2124 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2125 | if (!ret) |
| 2126 | from->sync_seqno[idx] = seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2127 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2128 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2129 | } |
| 2130 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2131 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2132 | { |
| 2133 | u32 old_write_domain, old_read_domains; |
| 2134 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2135 | /* Act a barrier for all accesses through the GTT */ |
| 2136 | mb(); |
| 2137 | |
| 2138 | /* Force a pagefault for domain tracking on next user access */ |
| 2139 | i915_gem_release_mmap(obj); |
| 2140 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2141 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2142 | return; |
| 2143 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2144 | old_read_domains = obj->base.read_domains; |
| 2145 | old_write_domain = obj->base.write_domain; |
| 2146 | |
| 2147 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2148 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2149 | |
| 2150 | trace_i915_gem_object_change_domain(obj, |
| 2151 | old_read_domains, |
| 2152 | old_write_domain); |
| 2153 | } |
| 2154 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2155 | /** |
| 2156 | * Unbinds an object from the GTT aperture. |
| 2157 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2158 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2159 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2160 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2161 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2162 | int ret = 0; |
| 2163 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2164 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2165 | return 0; |
| 2166 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2167 | if (obj->pin_count != 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2168 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2169 | return -EINVAL; |
| 2170 | } |
| 2171 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2172 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2173 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2174 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2175 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2176 | * should be safe and we need to cleanup or else we might |
| 2177 | * cause memory corruption through use-after-free. |
| 2178 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2179 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2180 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2181 | |
| 2182 | /* Move the object to the CPU domain to ensure that |
| 2183 | * any possible CPU writes while it's not in the GTT |
| 2184 | * are flushed when we go to remap it. |
| 2185 | */ |
| 2186 | if (ret == 0) |
| 2187 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 2188 | if (ret == -ERESTARTSYS) |
| 2189 | return ret; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2190 | if (ret) { |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2191 | /* In the event of a disaster, abandon all caches and |
| 2192 | * hope for the best. |
| 2193 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2194 | i915_gem_clflush_object(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2195 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2196 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2197 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2198 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2199 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2200 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2201 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2202 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2203 | trace_i915_gem_object_unbind(obj); |
| 2204 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2205 | if (obj->has_global_gtt_mapping) |
| 2206 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2207 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2208 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2209 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2210 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2211 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2212 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2213 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2214 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2215 | list_del_init(&obj->gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2216 | list_del_init(&obj->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2217 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2218 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2219 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2220 | drm_mm_put_block(obj->gtt_space); |
| 2221 | obj->gtt_space = NULL; |
| 2222 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2223 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2224 | if (i915_gem_object_is_purgeable(obj)) |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2225 | i915_gem_object_truncate(obj); |
| 2226 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2227 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2228 | } |
| 2229 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2230 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2231 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2232 | uint32_t invalidate_domains, |
| 2233 | uint32_t flush_domains) |
| 2234 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2235 | int ret; |
| 2236 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2237 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
| 2238 | return 0; |
| 2239 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2240 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
| 2241 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2242 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
| 2243 | if (ret) |
| 2244 | return ret; |
| 2245 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 2246 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
| 2247 | i915_gem_process_flushing_list(ring, flush_domains); |
| 2248 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2249 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2250 | } |
| 2251 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2252 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2253 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2254 | int ret; |
| 2255 | |
Chris Wilson | 395b70b | 2010-10-28 21:28:46 +0100 | [diff] [blame] | 2256 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2257 | return 0; |
| 2258 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2259 | if (!list_empty(&ring->gpu_write_list)) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2260 | ret = i915_gem_flush_ring(ring, |
Chris Wilson | 0ac74c6 | 2010-12-06 14:36:02 +0000 | [diff] [blame] | 2261 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2262 | if (ret) |
| 2263 | return ret; |
| 2264 | } |
| 2265 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2266 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2267 | } |
| 2268 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2269 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2270 | { |
| 2271 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2272 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2273 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2274 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2275 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2276 | for_each_ring(ring, dev_priv, i) { |
| 2277 | ret = i915_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2278 | if (ret) |
| 2279 | return ret; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2280 | |
| 2281 | /* Is the device fubar? */ |
| 2282 | if (WARN_ON(!list_empty(&ring->gpu_write_list))) |
| 2283 | return -EBUSY; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2284 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2285 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2286 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2287 | } |
| 2288 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2289 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
| 2290 | struct drm_i915_gem_object *obj) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2291 | { |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2292 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2293 | uint64_t val; |
| 2294 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2295 | if (obj) { |
| 2296 | u32 size = obj->gtt_space->size; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2297 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2298 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2299 | 0xfffff000) << 32; |
| 2300 | val |= obj->gtt_offset & 0xfffff000; |
| 2301 | val |= (uint64_t)((obj->stride / 128) - 1) << |
| 2302 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2303 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2304 | if (obj->tiling_mode == I915_TILING_Y) |
| 2305 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2306 | val |= I965_FENCE_REG_VALID; |
| 2307 | } else |
| 2308 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2309 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2310 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
| 2311 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2312 | } |
| 2313 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2314 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2315 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2316 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2317 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2318 | uint64_t val; |
| 2319 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2320 | if (obj) { |
| 2321 | u32 size = obj->gtt_space->size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2322 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2323 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2324 | 0xfffff000) << 32; |
| 2325 | val |= obj->gtt_offset & 0xfffff000; |
| 2326 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2327 | if (obj->tiling_mode == I915_TILING_Y) |
| 2328 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2329 | val |= I965_FENCE_REG_VALID; |
| 2330 | } else |
| 2331 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2332 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2333 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
| 2334 | POSTING_READ(FENCE_REG_965_0 + reg * 8); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2335 | } |
| 2336 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2337 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2338 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2339 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2340 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2341 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2342 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2343 | if (obj) { |
| 2344 | u32 size = obj->gtt_space->size; |
| 2345 | int pitch_val; |
| 2346 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2347 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2348 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2349 | (size & -size) != size || |
| 2350 | (obj->gtt_offset & (size - 1)), |
| 2351 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2352 | obj->gtt_offset, obj->map_and_fenceable, size); |
| 2353 | |
| 2354 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2355 | tile_width = 128; |
| 2356 | else |
| 2357 | tile_width = 512; |
| 2358 | |
| 2359 | /* Note: pitch better be a power of two tile widths */ |
| 2360 | pitch_val = obj->stride / tile_width; |
| 2361 | pitch_val = ffs(pitch_val) - 1; |
| 2362 | |
| 2363 | val = obj->gtt_offset; |
| 2364 | if (obj->tiling_mode == I915_TILING_Y) |
| 2365 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2366 | val |= I915_FENCE_SIZE_BITS(size); |
| 2367 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2368 | val |= I830_FENCE_REG_VALID; |
| 2369 | } else |
| 2370 | val = 0; |
| 2371 | |
| 2372 | if (reg < 8) |
| 2373 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2374 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2375 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2376 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2377 | I915_WRITE(reg, val); |
| 2378 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2379 | } |
| 2380 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2381 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2382 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2383 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2384 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2385 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2386 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2387 | if (obj) { |
| 2388 | u32 size = obj->gtt_space->size; |
| 2389 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2390 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2391 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2392 | (size & -size) != size || |
| 2393 | (obj->gtt_offset & (size - 1)), |
| 2394 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2395 | obj->gtt_offset, size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2396 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2397 | pitch_val = obj->stride / 128; |
| 2398 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2399 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2400 | val = obj->gtt_offset; |
| 2401 | if (obj->tiling_mode == I915_TILING_Y) |
| 2402 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2403 | val |= I830_FENCE_SIZE_BITS(size); |
| 2404 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2405 | val |= I830_FENCE_REG_VALID; |
| 2406 | } else |
| 2407 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2408 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2409 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2410 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2411 | } |
| 2412 | |
| 2413 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2414 | struct drm_i915_gem_object *obj) |
| 2415 | { |
| 2416 | switch (INTEL_INFO(dev)->gen) { |
| 2417 | case 7: |
| 2418 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; |
| 2419 | case 5: |
| 2420 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2421 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2422 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
| 2423 | default: break; |
| 2424 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2425 | } |
| 2426 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2427 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2428 | struct drm_i915_fence_reg *fence) |
| 2429 | { |
| 2430 | return fence - dev_priv->fence_regs; |
| 2431 | } |
| 2432 | |
| 2433 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2434 | struct drm_i915_fence_reg *fence, |
| 2435 | bool enable) |
| 2436 | { |
| 2437 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2438 | int reg = fence_number(dev_priv, fence); |
| 2439 | |
| 2440 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 2441 | |
| 2442 | if (enable) { |
| 2443 | obj->fence_reg = reg; |
| 2444 | fence->obj = obj; |
| 2445 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2446 | } else { |
| 2447 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2448 | fence->obj = NULL; |
| 2449 | list_del_init(&fence->lru_list); |
| 2450 | } |
| 2451 | } |
| 2452 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2453 | static int |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2454 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2455 | { |
| 2456 | int ret; |
| 2457 | |
| 2458 | if (obj->fenced_gpu_access) { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2459 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2460 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2461 | 0, obj->base.write_domain); |
| 2462 | if (ret) |
| 2463 | return ret; |
| 2464 | } |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2465 | |
| 2466 | obj->fenced_gpu_access = false; |
| 2467 | } |
| 2468 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2469 | if (obj->last_fenced_seqno) { |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2470 | ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2471 | if (ret) |
| 2472 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2473 | |
| 2474 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2475 | } |
| 2476 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2477 | /* Ensure that all CPU reads are completed before installing a fence |
| 2478 | * and all writes before removing the fence. |
| 2479 | */ |
| 2480 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2481 | mb(); |
| 2482 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2483 | return 0; |
| 2484 | } |
| 2485 | |
| 2486 | int |
| 2487 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2488 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2489 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2490 | int ret; |
| 2491 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2492 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2493 | if (ret) |
| 2494 | return ret; |
| 2495 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2496 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2497 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2498 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2499 | i915_gem_object_update_fence(obj, |
| 2500 | &dev_priv->fence_regs[obj->fence_reg], |
| 2501 | false); |
| 2502 | i915_gem_object_fence_lost(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2503 | |
| 2504 | return 0; |
| 2505 | } |
| 2506 | |
| 2507 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2508 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2509 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2510 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2511 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2512 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2513 | |
| 2514 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2515 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2516 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2517 | reg = &dev_priv->fence_regs[i]; |
| 2518 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2519 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2520 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2521 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2522 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2523 | } |
| 2524 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2525 | if (avail == NULL) |
| 2526 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2527 | |
| 2528 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2529 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2530 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2531 | continue; |
| 2532 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2533 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2534 | } |
| 2535 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2536 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2537 | } |
| 2538 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2539 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2540 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2541 | * @obj: object to map through a fence reg |
| 2542 | * |
| 2543 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2544 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2545 | * This function walks the fence regs looking for a free one for @obj, |
| 2546 | * stealing one if it can't find any. |
| 2547 | * |
| 2548 | * It then sets up the reg based on the object's properties: address, pitch |
| 2549 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2550 | * |
| 2551 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2552 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2553 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2554 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2555 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2556 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2557 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2558 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2559 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2560 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2561 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2562 | /* Have we updated the tiling parameters upon the object and so |
| 2563 | * will need to serialise the write to the associated fence register? |
| 2564 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2565 | if (obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2566 | ret = i915_gem_object_flush_fence(obj); |
| 2567 | if (ret) |
| 2568 | return ret; |
| 2569 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2570 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2571 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2572 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2573 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2574 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2575 | list_move_tail(®->lru_list, |
| 2576 | &dev_priv->mm.fence_list); |
| 2577 | return 0; |
| 2578 | } |
| 2579 | } else if (enable) { |
| 2580 | reg = i915_find_fence_reg(dev); |
| 2581 | if (reg == NULL) |
| 2582 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2583 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2584 | if (reg->obj) { |
| 2585 | struct drm_i915_gem_object *old = reg->obj; |
| 2586 | |
| 2587 | ret = i915_gem_object_flush_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2588 | if (ret) |
| 2589 | return ret; |
| 2590 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2591 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2592 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2593 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2594 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2595 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2596 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2597 | obj->fence_dirty = false; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2598 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2599 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2600 | } |
| 2601 | |
| 2602 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2603 | * Finds free space in the GTT aperture and binds the object there. |
| 2604 | */ |
| 2605 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2606 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2607 | unsigned alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2608 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2609 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2610 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2611 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2612 | struct drm_mm_node *free_space; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2613 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2614 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2615 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2616 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2617 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2618 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2619 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2620 | return -EINVAL; |
| 2621 | } |
| 2622 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2623 | fence_size = i915_gem_get_gtt_size(dev, |
| 2624 | obj->base.size, |
| 2625 | obj->tiling_mode); |
| 2626 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2627 | obj->base.size, |
| 2628 | obj->tiling_mode); |
| 2629 | unfenced_alignment = |
| 2630 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2631 | obj->base.size, |
| 2632 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2633 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2634 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2635 | alignment = map_and_fenceable ? fence_alignment : |
| 2636 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2637 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2638 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2639 | return -EINVAL; |
| 2640 | } |
| 2641 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2642 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2643 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2644 | /* If the object is bigger than the entire aperture, reject it early |
| 2645 | * before evicting everything in a vain attempt to find space. |
| 2646 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2647 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2648 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2649 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2650 | return -E2BIG; |
| 2651 | } |
| 2652 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2653 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2654 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2655 | free_space = |
| 2656 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2657 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2658 | dev_priv->mm.gtt_mappable_end, |
| 2659 | 0); |
| 2660 | else |
| 2661 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2662 | size, alignment, 0); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2663 | |
| 2664 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2665 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2666 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2667 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2668 | size, alignment, 0, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2669 | dev_priv->mm.gtt_mappable_end, |
| 2670 | 0); |
| 2671 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2672 | obj->gtt_space = |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2673 | drm_mm_get_block(free_space, size, alignment); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2674 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2675 | if (obj->gtt_space == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2676 | /* If the gtt is empty and we're still having trouble |
| 2677 | * fitting our object in, we're out of memory. |
| 2678 | */ |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2679 | ret = i915_gem_evict_something(dev, size, alignment, |
| 2680 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2681 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2682 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2683 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2684 | goto search_free; |
| 2685 | } |
| 2686 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2687 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2688 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2689 | drm_mm_put_block(obj->gtt_space); |
| 2690 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2691 | |
| 2692 | if (ret == -ENOMEM) { |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2693 | /* first try to reclaim some memory by clearing the GTT */ |
| 2694 | ret = i915_gem_evict_everything(dev, false); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2695 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2696 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2697 | if (gfpmask) { |
| 2698 | gfpmask = 0; |
| 2699 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2700 | } |
| 2701 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2702 | return -ENOMEM; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2703 | } |
| 2704 | |
| 2705 | goto search_free; |
| 2706 | } |
| 2707 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2708 | return ret; |
| 2709 | } |
| 2710 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2711 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2712 | if (ret) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2713 | i915_gem_object_put_pages_gtt(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2714 | drm_mm_put_block(obj->gtt_space); |
| 2715 | obj->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2716 | |
Chris Wilson | 809b633 | 2011-01-10 17:33:15 +0000 | [diff] [blame] | 2717 | if (i915_gem_evict_everything(dev, false)) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2718 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2719 | |
| 2720 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2722 | |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2723 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2724 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2725 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2726 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2727 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2728 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2729 | /* Assert that the object is not currently in any GPU domain. As it |
| 2730 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2731 | * a GPU cache |
| 2732 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2733 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2734 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2735 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2736 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2737 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2738 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2739 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2740 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2741 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2742 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2743 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2744 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2745 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2746 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2747 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2748 | return 0; |
| 2749 | } |
| 2750 | |
| 2751 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2752 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2753 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2754 | /* If we don't have a page list set up, then we're not pinned |
| 2755 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2756 | * again at bind time. |
| 2757 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2758 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2759 | return; |
| 2760 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2761 | /* If the GPU is snooping the contents of the CPU cache, |
| 2762 | * we do not need to manually clear the CPU cache lines. However, |
| 2763 | * the caches are only snooped when the render cache is |
| 2764 | * flushed/invalidated. As we always have to emit invalidations |
| 2765 | * and flushes when moving into and out of the RENDER domain, correct |
| 2766 | * snooping behaviour occurs naturally as the result of our domain |
| 2767 | * tracking. |
| 2768 | */ |
| 2769 | if (obj->cache_level != I915_CACHE_NONE) |
| 2770 | return; |
| 2771 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2772 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2773 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2774 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2775 | } |
| 2776 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2777 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2778 | static int |
Chris Wilson | 3619df0 | 2010-11-28 15:37:17 +0000 | [diff] [blame] | 2779 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2780 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2781 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2782 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2783 | |
| 2784 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2785 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2786 | } |
| 2787 | |
| 2788 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2789 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2790 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2791 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2792 | uint32_t old_write_domain; |
| 2793 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2794 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2795 | return; |
| 2796 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2797 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2798 | * to it immediately go to main memory as far as we know, so there's |
| 2799 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2800 | * |
| 2801 | * However, we do have to enforce the order so that all writes through |
| 2802 | * the GTT land before any writes to the device, such as updates to |
| 2803 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2804 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2805 | wmb(); |
| 2806 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2807 | old_write_domain = obj->base.write_domain; |
| 2808 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2809 | |
| 2810 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2811 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2812 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2813 | } |
| 2814 | |
| 2815 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2816 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2817 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2818 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2819 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2820 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2821 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2822 | return; |
| 2823 | |
| 2824 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 2825 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2826 | old_write_domain = obj->base.write_domain; |
| 2827 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2828 | |
| 2829 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2830 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2831 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2832 | } |
| 2833 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2834 | /** |
| 2835 | * Moves a single object to the GTT read, and possibly write domain. |
| 2836 | * |
| 2837 | * This function returns when the move is complete, including waiting on |
| 2838 | * flushes to occur. |
| 2839 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2840 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2841 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2842 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 2843 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2844 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2845 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2846 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2847 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2848 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2849 | return -EINVAL; |
| 2850 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 2851 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 2852 | return 0; |
| 2853 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2854 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2855 | if (ret) |
| 2856 | return ret; |
| 2857 | |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2858 | if (obj->pending_gpu_write || write) { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2859 | ret = i915_gem_object_wait_rendering(obj); |
Chris Wilson | 87ca9c8 | 2010-12-02 09:42:56 +0000 | [diff] [blame] | 2860 | if (ret) |
| 2861 | return ret; |
| 2862 | } |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2863 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2864 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2865 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2866 | old_write_domain = obj->base.write_domain; |
| 2867 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2868 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2869 | /* It should now be out of any other write domains, and we can update |
| 2870 | * the domain values for our changes. |
| 2871 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2872 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2873 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2874 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2875 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 2876 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 2877 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2878 | } |
| 2879 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2880 | trace_i915_gem_object_change_domain(obj, |
| 2881 | old_read_domains, |
| 2882 | old_write_domain); |
| 2883 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 2884 | /* And bump the LRU for this access */ |
| 2885 | if (i915_gem_object_is_inactive(obj)) |
| 2886 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 2887 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2888 | return 0; |
| 2889 | } |
| 2890 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2891 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2892 | enum i915_cache_level cache_level) |
| 2893 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2894 | struct drm_device *dev = obj->base.dev; |
| 2895 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2896 | int ret; |
| 2897 | |
| 2898 | if (obj->cache_level == cache_level) |
| 2899 | return 0; |
| 2900 | |
| 2901 | if (obj->pin_count) { |
| 2902 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 2903 | return -EBUSY; |
| 2904 | } |
| 2905 | |
| 2906 | if (obj->gtt_space) { |
| 2907 | ret = i915_gem_object_finish_gpu(obj); |
| 2908 | if (ret) |
| 2909 | return ret; |
| 2910 | |
| 2911 | i915_gem_object_finish_gtt(obj); |
| 2912 | |
| 2913 | /* Before SandyBridge, you could not use tiling or fence |
| 2914 | * registers with snooped memory, so relinquish any fences |
| 2915 | * currently pointing to our region in the aperture. |
| 2916 | */ |
| 2917 | if (INTEL_INFO(obj->base.dev)->gen < 6) { |
| 2918 | ret = i915_gem_object_put_fence(obj); |
| 2919 | if (ret) |
| 2920 | return ret; |
| 2921 | } |
| 2922 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2923 | if (obj->has_global_gtt_mapping) |
| 2924 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2925 | if (obj->has_aliasing_ppgtt_mapping) |
| 2926 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 2927 | obj, cache_level); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2928 | } |
| 2929 | |
| 2930 | if (cache_level == I915_CACHE_NONE) { |
| 2931 | u32 old_read_domains, old_write_domain; |
| 2932 | |
| 2933 | /* If we're coming from LLC cached, then we haven't |
| 2934 | * actually been tracking whether the data is in the |
| 2935 | * CPU cache or not, since we only allow one bit set |
| 2936 | * in obj->write_domain and have been skipping the clflushes. |
| 2937 | * Just set it to the CPU cache for now. |
| 2938 | */ |
| 2939 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 2940 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 2941 | |
| 2942 | old_read_domains = obj->base.read_domains; |
| 2943 | old_write_domain = obj->base.write_domain; |
| 2944 | |
| 2945 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 2946 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2947 | |
| 2948 | trace_i915_gem_object_change_domain(obj, |
| 2949 | old_read_domains, |
| 2950 | old_write_domain); |
| 2951 | } |
| 2952 | |
| 2953 | obj->cache_level = cache_level; |
| 2954 | return 0; |
| 2955 | } |
| 2956 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2957 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2958 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 2959 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 2960 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2961 | */ |
| 2962 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2963 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2964 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2965 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2966 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2967 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2968 | int ret; |
| 2969 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2970 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 2971 | if (ret) |
| 2972 | return ret; |
| 2973 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 2974 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2975 | ret = i915_gem_object_sync(obj, pipelined); |
| 2976 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2977 | return ret; |
| 2978 | } |
| 2979 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 2980 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 2981 | * a result, we make sure that the pinning that is about to occur is |
| 2982 | * done with uncached PTEs. This is lowest common denominator for all |
| 2983 | * chipsets. |
| 2984 | * |
| 2985 | * However for gen6+, we could do better by using the GFDT bit instead |
| 2986 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 2987 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 2988 | */ |
| 2989 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 2990 | if (ret) |
| 2991 | return ret; |
| 2992 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2993 | /* As the user may map the buffer once pinned in the display plane |
| 2994 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 2995 | * always use map_and_fenceable for all scanout buffers. |
| 2996 | */ |
| 2997 | ret = i915_gem_object_pin(obj, alignment, true); |
| 2998 | if (ret) |
| 2999 | return ret; |
| 3000 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3001 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3002 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3003 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3004 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3005 | |
| 3006 | /* It should now be out of any other write domains, and we can update |
| 3007 | * the domain values for our changes. |
| 3008 | */ |
| 3009 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3010 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3011 | |
| 3012 | trace_i915_gem_object_change_domain(obj, |
| 3013 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3014 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3015 | |
| 3016 | return 0; |
| 3017 | } |
| 3018 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3019 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3020 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3021 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3022 | int ret; |
| 3023 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3024 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3025 | return 0; |
| 3026 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3027 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3028 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3029 | if (ret) |
| 3030 | return ret; |
| 3031 | } |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3032 | |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3033 | ret = i915_gem_object_wait_rendering(obj); |
| 3034 | if (ret) |
| 3035 | return ret; |
| 3036 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3037 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3038 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3039 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3040 | } |
| 3041 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3042 | /** |
| 3043 | * Moves a single object to the CPU read, and possibly write domain. |
| 3044 | * |
| 3045 | * This function returns when the move is complete, including waiting on |
| 3046 | * flushes to occur. |
| 3047 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3048 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3049 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3050 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3051 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3052 | int ret; |
| 3053 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3054 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3055 | return 0; |
| 3056 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3057 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
| 3058 | if (ret) |
| 3059 | return ret; |
| 3060 | |
Chris Wilson | f841319 | 2012-04-10 11:52:50 +0100 | [diff] [blame] | 3061 | if (write || obj->pending_gpu_write) { |
| 3062 | ret = i915_gem_object_wait_rendering(obj); |
| 3063 | if (ret) |
| 3064 | return ret; |
| 3065 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3066 | |
| 3067 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3068 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3069 | old_write_domain = obj->base.write_domain; |
| 3070 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3071 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3072 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3073 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3074 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3075 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3076 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3077 | } |
| 3078 | |
| 3079 | /* It should now be out of any other write domains, and we can update |
| 3080 | * the domain values for our changes. |
| 3081 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3082 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3083 | |
| 3084 | /* If we're writing through the CPU, then the GPU read domains will |
| 3085 | * need to be invalidated at next use. |
| 3086 | */ |
| 3087 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3088 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3089 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3090 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3091 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3092 | trace_i915_gem_object_change_domain(obj, |
| 3093 | old_read_domains, |
| 3094 | old_write_domain); |
| 3095 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3096 | return 0; |
| 3097 | } |
| 3098 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3099 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3100 | * emitted over 20 msec ago. |
| 3101 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3102 | * Note that if we were to use the current jiffies each time around the loop, |
| 3103 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3104 | * render a frame was over 20ms. |
| 3105 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3106 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3107 | * relatively low latency when blocking on a particular request to finish. |
| 3108 | */ |
| 3109 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3110 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3111 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3112 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3113 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3114 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3115 | struct drm_i915_gem_request *request; |
| 3116 | struct intel_ring_buffer *ring = NULL; |
| 3117 | u32 seqno = 0; |
| 3118 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3119 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3120 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3121 | return -EIO; |
| 3122 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3123 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3124 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3125 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3126 | break; |
| 3127 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3128 | ring = request->ring; |
| 3129 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3130 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3131 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3132 | |
| 3133 | if (seqno == 0) |
| 3134 | return 0; |
| 3135 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 3136 | ret = __wait_seqno(ring, seqno, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3137 | if (ret == 0) |
| 3138 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3139 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3140 | return ret; |
| 3141 | } |
| 3142 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3143 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3144 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3145 | uint32_t alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3146 | bool map_and_fenceable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3147 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3148 | int ret; |
| 3149 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3150 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3151 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3152 | if (obj->gtt_space != NULL) { |
| 3153 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3154 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3155 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3156 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3157 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3158 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3159 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3160 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3161 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3162 | ret = i915_gem_object_unbind(obj); |
| 3163 | if (ret) |
| 3164 | return ret; |
| 3165 | } |
| 3166 | } |
| 3167 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3168 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3169 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3170 | map_and_fenceable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3171 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3172 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3173 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3174 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3175 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3176 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3177 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3178 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3179 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3180 | |
| 3181 | return 0; |
| 3182 | } |
| 3183 | |
| 3184 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3185 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3186 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3187 | BUG_ON(obj->pin_count == 0); |
| 3188 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3189 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3190 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3191 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3192 | } |
| 3193 | |
| 3194 | int |
| 3195 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3196 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3197 | { |
| 3198 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3199 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3200 | int ret; |
| 3201 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3202 | ret = i915_mutex_lock_interruptible(dev); |
| 3203 | if (ret) |
| 3204 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3205 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3206 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3207 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3208 | ret = -ENOENT; |
| 3209 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3210 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3211 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3212 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3213 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3214 | ret = -EINVAL; |
| 3215 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3216 | } |
| 3217 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3218 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3219 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3220 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3221 | ret = -EINVAL; |
| 3222 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3223 | } |
| 3224 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3225 | obj->user_pin_count++; |
| 3226 | obj->pin_filp = file; |
| 3227 | if (obj->user_pin_count == 1) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3228 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3229 | if (ret) |
| 3230 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3231 | } |
| 3232 | |
| 3233 | /* XXX - flush the CPU caches for pinned objects |
| 3234 | * as the X server doesn't manage domains yet |
| 3235 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3236 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3237 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3238 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3239 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3240 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3241 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3242 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3243 | } |
| 3244 | |
| 3245 | int |
| 3246 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3247 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3248 | { |
| 3249 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3250 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3251 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3252 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3253 | ret = i915_mutex_lock_interruptible(dev); |
| 3254 | if (ret) |
| 3255 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3256 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3257 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3258 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3259 | ret = -ENOENT; |
| 3260 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3261 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3262 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3263 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3264 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3265 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3266 | ret = -EINVAL; |
| 3267 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3268 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3269 | obj->user_pin_count--; |
| 3270 | if (obj->user_pin_count == 0) { |
| 3271 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3272 | i915_gem_object_unpin(obj); |
| 3273 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3274 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3275 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3276 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3277 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3278 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3279 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3280 | } |
| 3281 | |
| 3282 | int |
| 3283 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3284 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3285 | { |
| 3286 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3287 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3288 | int ret; |
| 3289 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3290 | ret = i915_mutex_lock_interruptible(dev); |
| 3291 | if (ret) |
| 3292 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3293 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3294 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3295 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3296 | ret = -ENOENT; |
| 3297 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3298 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3299 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3300 | /* Count all active objects as busy, even if they are currently not used |
| 3301 | * by the gpu. Users of this interface expect objects to eventually |
| 3302 | * become non-busy without any further actions, therefore emit any |
| 3303 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3304 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3305 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3306 | if (args->busy) { |
| 3307 | /* Unconditionally flush objects, even when the gpu still uses this |
| 3308 | * object. Userspace calling this function indicates that it wants to |
| 3309 | * use this buffer rather sooner than later, so issuing the required |
| 3310 | * flush earlier is beneficial. |
| 3311 | */ |
Chris Wilson | 1a1c697 | 2010-12-07 23:00:20 +0000 | [diff] [blame] | 3312 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3313 | ret = i915_gem_flush_ring(obj->ring, |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3314 | 0, obj->base.write_domain); |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 3315 | } else { |
| 3316 | ret = i915_gem_check_olr(obj->ring, |
| 3317 | obj->last_rendering_seqno); |
Chris Wilson | 7a19487 | 2010-12-07 10:38:40 +0000 | [diff] [blame] | 3318 | } |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3319 | |
| 3320 | /* Update the active list for the hardware's current position. |
| 3321 | * Otherwise this only updates on a delayed timer or when irqs |
| 3322 | * are actually unmasked, and our working set ends up being |
| 3323 | * larger than required. |
| 3324 | */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3325 | i915_gem_retire_requests_ring(obj->ring); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3326 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3327 | args->busy = obj->active; |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3328 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3329 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3330 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3331 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3332 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3333 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3334 | } |
| 3335 | |
| 3336 | int |
| 3337 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3338 | struct drm_file *file_priv) |
| 3339 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3340 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3341 | } |
| 3342 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3343 | int |
| 3344 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3345 | struct drm_file *file_priv) |
| 3346 | { |
| 3347 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3348 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3349 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3350 | |
| 3351 | switch (args->madv) { |
| 3352 | case I915_MADV_DONTNEED: |
| 3353 | case I915_MADV_WILLNEED: |
| 3354 | break; |
| 3355 | default: |
| 3356 | return -EINVAL; |
| 3357 | } |
| 3358 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3359 | ret = i915_mutex_lock_interruptible(dev); |
| 3360 | if (ret) |
| 3361 | return ret; |
| 3362 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3363 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3364 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3365 | ret = -ENOENT; |
| 3366 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3367 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3368 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3369 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3370 | ret = -EINVAL; |
| 3371 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3372 | } |
| 3373 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3374 | if (obj->madv != __I915_MADV_PURGED) |
| 3375 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3376 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3377 | /* if the object is no longer bound, discard its backing storage */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3378 | if (i915_gem_object_is_purgeable(obj) && |
| 3379 | obj->gtt_space == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3380 | i915_gem_object_truncate(obj); |
| 3381 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3382 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3383 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3384 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3385 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3386 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3387 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3388 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3389 | } |
| 3390 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3391 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3392 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3393 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3394 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3395 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3396 | struct address_space *mapping; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3397 | |
| 3398 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3399 | if (obj == NULL) |
| 3400 | return NULL; |
| 3401 | |
| 3402 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3403 | kfree(obj); |
| 3404 | return NULL; |
| 3405 | } |
| 3406 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3407 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 3408 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 3409 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3410 | i915_gem_info_add_obj(dev_priv, size); |
| 3411 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3412 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3413 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3414 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3415 | if (HAS_LLC(dev)) { |
| 3416 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3417 | * cache) for about a 10% performance improvement |
| 3418 | * compared to uncached. Graphics requests other than |
| 3419 | * display scanout are coherent with the CPU in |
| 3420 | * accessing this cache. This means in this mode we |
| 3421 | * don't need to clflush on the CPU side, and on the |
| 3422 | * GPU side we only need to flush internal caches to |
| 3423 | * get data visible to the CPU. |
| 3424 | * |
| 3425 | * However, we maintain the display planes as UC, and so |
| 3426 | * need to rebind when first used as such. |
| 3427 | */ |
| 3428 | obj->cache_level = I915_CACHE_LLC; |
| 3429 | } else |
| 3430 | obj->cache_level = I915_CACHE_NONE; |
| 3431 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 3432 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3433 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3434 | INIT_LIST_HEAD(&obj->mm_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3435 | INIT_LIST_HEAD(&obj->gtt_list); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3436 | INIT_LIST_HEAD(&obj->ring_list); |
Chris Wilson | 432e58e | 2010-11-25 19:32:06 +0000 | [diff] [blame] | 3437 | INIT_LIST_HEAD(&obj->exec_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3438 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3439 | obj->madv = I915_MADV_WILLNEED; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3440 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3441 | obj->map_and_fenceable = true; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3442 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3443 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3444 | } |
| 3445 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3446 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3447 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3448 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3449 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3450 | return 0; |
| 3451 | } |
| 3452 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3453 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3454 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3455 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3456 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3457 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3458 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3459 | trace_i915_gem_object_destroy(obj); |
| 3460 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3461 | if (obj->phys_obj) |
| 3462 | i915_gem_detach_phys_object(dev, obj); |
| 3463 | |
| 3464 | obj->pin_count = 0; |
| 3465 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
| 3466 | bool was_interruptible; |
| 3467 | |
| 3468 | was_interruptible = dev_priv->mm.interruptible; |
| 3469 | dev_priv->mm.interruptible = false; |
| 3470 | |
| 3471 | WARN_ON(i915_gem_object_unbind(obj)); |
| 3472 | |
| 3473 | dev_priv->mm.interruptible = was_interruptible; |
| 3474 | } |
| 3475 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3476 | if (obj->base.map_list.map) |
Rob Clark | b464e9a | 2011-08-10 08:09:08 -0500 | [diff] [blame] | 3477 | drm_gem_free_mmap_offset(&obj->base); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3478 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3479 | drm_gem_object_release(&obj->base); |
| 3480 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3481 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3482 | kfree(obj->bit_17); |
| 3483 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3484 | } |
| 3485 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3486 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3487 | i915_gem_idle(struct drm_device *dev) |
| 3488 | { |
| 3489 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3490 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3491 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3492 | mutex_lock(&dev->struct_mutex); |
| 3493 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3494 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3495 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3496 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3497 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3498 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3499 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3500 | if (ret) { |
| 3501 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3502 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3503 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3504 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3505 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3506 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 3507 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3508 | i915_gem_evict_everything(dev, false); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3509 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3510 | i915_gem_reset_fences(dev); |
| 3511 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3512 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3513 | * We need to replace this with a semaphore, or something. |
| 3514 | * And not confound mm.suspended! |
| 3515 | */ |
| 3516 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3517 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3518 | |
| 3519 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3520 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3521 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3522 | mutex_unlock(&dev->struct_mutex); |
| 3523 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3524 | /* Cancel the retire work handler, which should be idle now. */ |
| 3525 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3526 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3527 | return 0; |
| 3528 | } |
| 3529 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame^] | 3530 | void i915_gem_l3_remap(struct drm_device *dev) |
| 3531 | { |
| 3532 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3533 | u32 misccpctl; |
| 3534 | int i; |
| 3535 | |
| 3536 | if (!IS_IVYBRIDGE(dev)) |
| 3537 | return; |
| 3538 | |
| 3539 | if (!dev_priv->mm.l3_remap_info) |
| 3540 | return; |
| 3541 | |
| 3542 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 3543 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 3544 | POSTING_READ(GEN7_MISCCPCTL); |
| 3545 | |
| 3546 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 3547 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
| 3548 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) |
| 3549 | DRM_DEBUG("0x%x was already programmed to %x\n", |
| 3550 | GEN7_L3LOG_BASE + i, remap); |
| 3551 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) |
| 3552 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
| 3553 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); |
| 3554 | } |
| 3555 | |
| 3556 | /* Make sure all the writes land before disabling dop clock gating */ |
| 3557 | POSTING_READ(GEN7_L3LOG_BASE); |
| 3558 | |
| 3559 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 3560 | } |
| 3561 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3562 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3563 | { |
| 3564 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3565 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3566 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3567 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3568 | return; |
| 3569 | |
| 3570 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3571 | DISP_TILE_SURFACE_SWIZZLING); |
| 3572 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3573 | if (IS_GEN5(dev)) |
| 3574 | return; |
| 3575 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3576 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3577 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3578 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3579 | else |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3580 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3581 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3582 | |
| 3583 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3584 | { |
| 3585 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3586 | uint32_t pd_offset; |
| 3587 | struct intel_ring_buffer *ring; |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3588 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 3589 | uint32_t __iomem *pd_addr; |
| 3590 | uint32_t pd_entry; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3591 | int i; |
| 3592 | |
| 3593 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3594 | return; |
| 3595 | |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3596 | |
| 3597 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); |
| 3598 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 3599 | dma_addr_t pt_addr; |
| 3600 | |
| 3601 | if (dev_priv->mm.gtt->needs_dmar) |
| 3602 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 3603 | else |
| 3604 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); |
| 3605 | |
| 3606 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 3607 | pd_entry |= GEN6_PDE_VALID; |
| 3608 | |
| 3609 | writel(pd_entry, pd_addr + i); |
| 3610 | } |
| 3611 | readl(pd_addr); |
| 3612 | |
| 3613 | pd_offset = ppgtt->pd_offset; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3614 | pd_offset /= 64; /* in cachelines, */ |
| 3615 | pd_offset <<= 16; |
| 3616 | |
| 3617 | if (INTEL_INFO(dev)->gen == 6) { |
Daniel Vetter | 48ecfa1 | 2012-04-11 20:42:40 +0200 | [diff] [blame] | 3618 | uint32_t ecochk, gab_ctl, ecobits; |
| 3619 | |
| 3620 | ecobits = I915_READ(GAC_ECO_BITS); |
| 3621 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
Daniel Vetter | be901a5 | 2012-04-11 20:42:39 +0200 | [diff] [blame] | 3622 | |
| 3623 | gab_ctl = I915_READ(GAB_CTL); |
| 3624 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
| 3625 | |
| 3626 | ecochk = I915_READ(GAM_ECOCHK); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3627 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3628 | ECOCHK_PPGTT_CACHE64B); |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3629 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3630 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3631 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3632 | /* GFX_MODE is per-ring on gen7+ */ |
| 3633 | } |
| 3634 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3635 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3636 | if (INTEL_INFO(dev)->gen >= 7) |
| 3637 | I915_WRITE(RING_MODE_GEN7(ring), |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3638 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3639 | |
| 3640 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3641 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3642 | } |
| 3643 | } |
| 3644 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3645 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3646 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3647 | { |
| 3648 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3649 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3650 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame^] | 3651 | i915_gem_l3_remap(dev); |
| 3652 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3653 | i915_gem_init_swizzling(dev); |
| 3654 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3655 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3656 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3657 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3658 | |
| 3659 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3660 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3661 | if (ret) |
| 3662 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3663 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3664 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3665 | if (HAS_BLT(dev)) { |
| 3666 | ret = intel_init_blt_ring_buffer(dev); |
| 3667 | if (ret) |
| 3668 | goto cleanup_bsd_ring; |
| 3669 | } |
| 3670 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3671 | dev_priv->next_seqno = 1; |
| 3672 | |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3673 | i915_gem_init_ppgtt(dev); |
| 3674 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3675 | return 0; |
| 3676 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3677 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3678 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3679 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3680 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3681 | return ret; |
| 3682 | } |
| 3683 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 3684 | static bool |
| 3685 | intel_enable_ppgtt(struct drm_device *dev) |
| 3686 | { |
| 3687 | if (i915_enable_ppgtt >= 0) |
| 3688 | return i915_enable_ppgtt; |
| 3689 | |
| 3690 | #ifdef CONFIG_INTEL_IOMMU |
| 3691 | /* Disable ppgtt on SNB if VT-d is on. */ |
| 3692 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 3693 | return false; |
| 3694 | #endif |
| 3695 | |
| 3696 | return true; |
| 3697 | } |
| 3698 | |
| 3699 | int i915_gem_init(struct drm_device *dev) |
| 3700 | { |
| 3701 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3702 | unsigned long gtt_size, mappable_size; |
| 3703 | int ret; |
| 3704 | |
| 3705 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
| 3706 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
| 3707 | |
| 3708 | mutex_lock(&dev->struct_mutex); |
| 3709 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { |
| 3710 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
| 3711 | * aperture accordingly when using aliasing ppgtt. */ |
| 3712 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; |
| 3713 | |
| 3714 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); |
| 3715 | |
| 3716 | ret = i915_gem_init_aliasing_ppgtt(dev); |
| 3717 | if (ret) { |
| 3718 | mutex_unlock(&dev->struct_mutex); |
| 3719 | return ret; |
| 3720 | } |
| 3721 | } else { |
| 3722 | /* Let GEM Manage all of the aperture. |
| 3723 | * |
| 3724 | * However, leave one page at the end still bound to the scratch |
| 3725 | * page. There are a number of places where the hardware |
| 3726 | * apparently prefetches past the end of the object, and we've |
| 3727 | * seen multiple hangs with the GPU head pointer stuck in a |
| 3728 | * batchbuffer bound at the last page of the aperture. One page |
| 3729 | * should be enough to keep any prefetching inside of the |
| 3730 | * aperture. |
| 3731 | */ |
| 3732 | i915_gem_init_global_gtt(dev, 0, mappable_size, |
| 3733 | gtt_size); |
| 3734 | } |
| 3735 | |
| 3736 | ret = i915_gem_init_hw(dev); |
| 3737 | mutex_unlock(&dev->struct_mutex); |
| 3738 | if (ret) { |
| 3739 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 3740 | return ret; |
| 3741 | } |
| 3742 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 3743 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 3744 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3745 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 3746 | return 0; |
| 3747 | } |
| 3748 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3749 | void |
| 3750 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 3751 | { |
| 3752 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3753 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3754 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3755 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3756 | for_each_ring(ring, dev_priv, i) |
| 3757 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3758 | } |
| 3759 | |
| 3760 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3761 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 3762 | struct drm_file *file_priv) |
| 3763 | { |
| 3764 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3765 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3766 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3767 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3768 | return 0; |
| 3769 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3770 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3771 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3772 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3773 | } |
| 3774 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3775 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3776 | dev_priv->mm.suspended = 0; |
| 3777 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3778 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3779 | if (ret != 0) { |
| 3780 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3781 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 3782 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3783 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3784 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3785 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 3786 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3787 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3788 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3789 | ret = drm_irq_install(dev); |
| 3790 | if (ret) |
| 3791 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3792 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3793 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 3794 | |
| 3795 | cleanup_ringbuffer: |
| 3796 | mutex_lock(&dev->struct_mutex); |
| 3797 | i915_gem_cleanup_ringbuffer(dev); |
| 3798 | dev_priv->mm.suspended = 1; |
| 3799 | mutex_unlock(&dev->struct_mutex); |
| 3800 | |
| 3801 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3802 | } |
| 3803 | |
| 3804 | int |
| 3805 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 3806 | struct drm_file *file_priv) |
| 3807 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3808 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3809 | return 0; |
| 3810 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 3811 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 3812 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3813 | } |
| 3814 | |
| 3815 | void |
| 3816 | i915_gem_lastclose(struct drm_device *dev) |
| 3817 | { |
| 3818 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3819 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 3820 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3821 | return; |
| 3822 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3823 | ret = i915_gem_idle(dev); |
| 3824 | if (ret) |
| 3825 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3826 | } |
| 3827 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 3828 | static void |
| 3829 | init_ring_lists(struct intel_ring_buffer *ring) |
| 3830 | { |
| 3831 | INIT_LIST_HEAD(&ring->active_list); |
| 3832 | INIT_LIST_HEAD(&ring->request_list); |
| 3833 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 3834 | } |
| 3835 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3836 | void |
| 3837 | i915_gem_load(struct drm_device *dev) |
| 3838 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3839 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3840 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3841 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 3842 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3843 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 3844 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3845 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Daniel Vetter | 93a37f2 | 2010-11-05 20:24:53 +0100 | [diff] [blame] | 3846 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3847 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 3848 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 3849 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 3850 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3851 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 3852 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3853 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 3854 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3855 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 3856 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 3857 | I915_WRITE(MI_ARB_STATE, |
| 3858 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 3859 | } |
| 3860 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 3861 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 3862 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3863 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 3864 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3865 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3866 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 3867 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3868 | dev_priv->num_fence_regs = 16; |
| 3869 | else |
| 3870 | dev_priv->num_fence_regs = 8; |
| 3871 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 3872 | /* Initialize fence registers to zero */ |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 3873 | i915_gem_reset_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 3874 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3875 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3876 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3877 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 3878 | dev_priv->mm.interruptible = true; |
| 3879 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 3880 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 3881 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 3882 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3883 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3884 | |
| 3885 | /* |
| 3886 | * Create a physically contiguous memory object for this object |
| 3887 | * e.g. for cursor + overlay regs |
| 3888 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3889 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 3890 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3891 | { |
| 3892 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3893 | struct drm_i915_gem_phys_object *phys_obj; |
| 3894 | int ret; |
| 3895 | |
| 3896 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 3897 | return 0; |
| 3898 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3899 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3900 | if (!phys_obj) |
| 3901 | return -ENOMEM; |
| 3902 | |
| 3903 | phys_obj->id = id; |
| 3904 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3905 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3906 | if (!phys_obj->handle) { |
| 3907 | ret = -ENOMEM; |
| 3908 | goto kfree_obj; |
| 3909 | } |
| 3910 | #ifdef CONFIG_X86 |
| 3911 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3912 | #endif |
| 3913 | |
| 3914 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 3915 | |
| 3916 | return 0; |
| 3917 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3918 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3919 | return ret; |
| 3920 | } |
| 3921 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3922 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3923 | { |
| 3924 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3925 | struct drm_i915_gem_phys_object *phys_obj; |
| 3926 | |
| 3927 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 3928 | return; |
| 3929 | |
| 3930 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 3931 | if (phys_obj->cur_obj) { |
| 3932 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 3933 | } |
| 3934 | |
| 3935 | #ifdef CONFIG_X86 |
| 3936 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 3937 | #endif |
| 3938 | drm_pci_free(dev, phys_obj->handle); |
| 3939 | kfree(phys_obj); |
| 3940 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 3941 | } |
| 3942 | |
| 3943 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 3944 | { |
| 3945 | int i; |
| 3946 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 3947 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3948 | i915_gem_free_phys_object(dev, i); |
| 3949 | } |
| 3950 | |
| 3951 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3952 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3953 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3954 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3955 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3956 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3957 | int page_count; |
| 3958 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3959 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3960 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3961 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3962 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3963 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3964 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3965 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3966 | if (!IS_ERR(page)) { |
| 3967 | char *dst = kmap_atomic(page); |
| 3968 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 3969 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3970 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 3971 | drm_clflush_pages(&page, 1); |
| 3972 | |
| 3973 | set_page_dirty(page); |
| 3974 | mark_page_accessed(page); |
| 3975 | page_cache_release(page); |
| 3976 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3977 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3978 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 3979 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3980 | obj->phys_obj->cur_obj = NULL; |
| 3981 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3982 | } |
| 3983 | |
| 3984 | int |
| 3985 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3986 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 3987 | int id, |
| 3988 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3989 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3990 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3991 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 3992 | int ret = 0; |
| 3993 | int page_count; |
| 3994 | int i; |
| 3995 | |
| 3996 | if (id > I915_MAX_PHYS_OBJECT) |
| 3997 | return -EINVAL; |
| 3998 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3999 | if (obj->phys_obj) { |
| 4000 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4001 | return 0; |
| 4002 | i915_gem_detach_phys_object(dev, obj); |
| 4003 | } |
| 4004 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4005 | /* create a new object */ |
| 4006 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4007 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4008 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4009 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4010 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4011 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4012 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4013 | } |
| 4014 | } |
| 4015 | |
| 4016 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4017 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4018 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4019 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4020 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4021 | |
| 4022 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4023 | struct page *page; |
| 4024 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4025 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4026 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4027 | if (IS_ERR(page)) |
| 4028 | return PTR_ERR(page); |
| 4029 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4030 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4031 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4032 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4033 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4034 | |
| 4035 | mark_page_accessed(page); |
| 4036 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4040 | } |
| 4041 | |
| 4042 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4043 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4044 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4045 | struct drm_i915_gem_pwrite *args, |
| 4046 | struct drm_file *file_priv) |
| 4047 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4048 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4049 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4050 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4051 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4052 | unsigned long unwritten; |
| 4053 | |
| 4054 | /* The physical object once assigned is fixed for the lifetime |
| 4055 | * of the obj, so we can safely drop the lock and continue |
| 4056 | * to access vaddr. |
| 4057 | */ |
| 4058 | mutex_unlock(&dev->struct_mutex); |
| 4059 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4060 | mutex_lock(&dev->struct_mutex); |
| 4061 | if (unwritten) |
| 4062 | return -EFAULT; |
| 4063 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4064 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4065 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4066 | return 0; |
| 4067 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4068 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4069 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4070 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4071 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4072 | |
| 4073 | /* Clean up our request list when the client is going away, so that |
| 4074 | * later retire_requests won't dereference our soon-to-be-gone |
| 4075 | * file_priv. |
| 4076 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4077 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4078 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4079 | struct drm_i915_gem_request *request; |
| 4080 | |
| 4081 | request = list_first_entry(&file_priv->mm.request_list, |
| 4082 | struct drm_i915_gem_request, |
| 4083 | client_list); |
| 4084 | list_del(&request->client_list); |
| 4085 | request->file_priv = NULL; |
| 4086 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4087 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4088 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4089 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4090 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4091 | i915_gpu_is_active(struct drm_device *dev) |
| 4092 | { |
| 4093 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4094 | int lists_empty; |
| 4095 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4096 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4097 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4098 | |
| 4099 | return !lists_empty; |
| 4100 | } |
| 4101 | |
| 4102 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4103 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4104 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4105 | struct drm_i915_private *dev_priv = |
| 4106 | container_of(shrinker, |
| 4107 | struct drm_i915_private, |
| 4108 | mm.inactive_shrinker); |
| 4109 | struct drm_device *dev = dev_priv->dev; |
| 4110 | struct drm_i915_gem_object *obj, *next; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4111 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4112 | int cnt; |
| 4113 | |
| 4114 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4115 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4116 | |
| 4117 | /* "fast-path" to count number of available objects */ |
| 4118 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4119 | cnt = 0; |
| 4120 | list_for_each_entry(obj, |
| 4121 | &dev_priv->mm.inactive_list, |
| 4122 | mm_list) |
| 4123 | cnt++; |
| 4124 | mutex_unlock(&dev->struct_mutex); |
| 4125 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4126 | } |
| 4127 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4128 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4129 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4130 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4131 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4132 | list_for_each_entry_safe(obj, next, |
| 4133 | &dev_priv->mm.inactive_list, |
| 4134 | mm_list) { |
| 4135 | if (i915_gem_object_is_purgeable(obj)) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4136 | if (i915_gem_object_unbind(obj) == 0 && |
| 4137 | --nr_to_scan == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4138 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4139 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4140 | } |
| 4141 | |
| 4142 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4143 | cnt = 0; |
| 4144 | list_for_each_entry_safe(obj, next, |
| 4145 | &dev_priv->mm.inactive_list, |
| 4146 | mm_list) { |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4147 | if (nr_to_scan && |
| 4148 | i915_gem_object_unbind(obj) == 0) |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4149 | nr_to_scan--; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 4150 | else |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4151 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4152 | } |
| 4153 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4154 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4155 | /* |
| 4156 | * We are desperate for pages, so as a last resort, wait |
| 4157 | * for the GPU to finish and discard whatever we can. |
| 4158 | * This has a dramatic impact to reduce the number of |
| 4159 | * OOM-killer events whilst running the GPU aggressively. |
| 4160 | */ |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4161 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4162 | goto rescan; |
| 4163 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4164 | mutex_unlock(&dev->struct_mutex); |
| 4165 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4166 | } |