blob: 461bf53709f5ca47c5f492daebd34af22d828aee [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000072#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010073
Dave Airliec2142712009-09-22 08:50:10 +100074#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075#include "radeon_mode.h"
76#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020077
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020089extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100091extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020092extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040093extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040094extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -050095extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -040096extern int radeon_msi;
Christian König3368ff02012-05-02 15:11:21 +020097extern int radeon_lockup_timeout;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098
99/*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
Jerome Glissebb635562012-05-09 15:34:46 +0200103#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100105/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glissebb635562012-05-09 15:34:46 +0200106#define RADEON_IB_POOL_SIZE 16
107#define RADEON_DEBUGFS_MAX_COMPONENTS 32
108#define RADEONFB_CONN_LIMIT 4
109#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200110
Alex Deucher1b370782011-11-17 20:13:28 -0500111/* max number of rings */
Alex Deucher4d756582012-09-27 15:08:35 -0400112#define RADEON_NUM_RINGS 4
Jerome Glissebb635562012-05-09 15:34:46 +0200113
114/* fence seq are set to this number when signaled */
115#define RADEON_FENCE_SIGNALED_SEQ 0LL
Alex Deucher1b370782011-11-17 20:13:28 -0500116
117/* internal ring indices */
118/* r1xx+ has gfx CP ring */
Jerome Glissebb635562012-05-09 15:34:46 +0200119#define RADEON_RING_TYPE_GFX_INDEX 0
Alex Deucher1b370782011-11-17 20:13:28 -0500120
121/* cayman has 2 compute CP rings */
Jerome Glissebb635562012-05-09 15:34:46 +0200122#define CAYMAN_RING_TYPE_CP1_INDEX 1
123#define CAYMAN_RING_TYPE_CP2_INDEX 2
Alex Deucher1b370782011-11-17 20:13:28 -0500124
Alex Deucher4d756582012-09-27 15:08:35 -0400125/* R600+ has an async dma ring */
126#define R600_RING_TYPE_DMA_INDEX 3
127
Jerome Glisse721604a2012-01-05 22:11:05 -0500128/* hardcode those limit for now */
Christian Königca19f212012-09-11 16:09:59 +0200129#define RADEON_VA_IB_OFFSET (1 << 20)
Jerome Glissebb635562012-05-09 15:34:46 +0200130#define RADEON_VA_RESERVED_SIZE (8 << 20)
131#define RADEON_IB_VM_MAX_SIZE (64 << 10)
Jerome Glisse721604a2012-01-05 22:11:05 -0500132
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200133/*
134 * Errata workarounds.
135 */
136enum radeon_pll_errata {
137 CHIP_ERRATA_R300_CG = 0x00000001,
138 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
139 CHIP_ERRATA_PLL_DELAY = 0x00000004
140};
141
142
143struct radeon_device;
144
145
146/*
147 * BIOS.
148 */
149bool radeon_get_bios(struct radeon_device *rdev);
150
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500151/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000152 * Dummy page
153 */
154struct radeon_dummy_page {
155 struct page *page;
156 dma_addr_t addr;
157};
158int radeon_dummy_page_init(struct radeon_device *rdev);
159void radeon_dummy_page_fini(struct radeon_device *rdev);
160
161
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200162/*
163 * Clocks
164 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200165struct radeon_clock {
166 struct radeon_pll p1pll;
167 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500168 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200169 struct radeon_pll spll;
170 struct radeon_pll mpll;
171 /* 10 Khz units */
172 uint32_t default_mclk;
173 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500174 uint32_t default_dispclk;
175 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400176 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200177};
178
Rafał Miłecki74338742009-11-03 00:53:02 +0100179/*
180 * Power management
181 */
182int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500183void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100184void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400185void radeon_pm_suspend(struct radeon_device *rdev);
186void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500187void radeon_combios_get_power_modes(struct radeon_device *rdev);
188void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400189void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucherf8920342010-06-30 12:02:03 -0400190void rs690_pm_info(struct radeon_device *rdev);
Alex Deucher20d391d2011-02-01 16:12:34 -0500191extern int rv6xx_get_temp(struct radeon_device *rdev);
192extern int rv770_get_temp(struct radeon_device *rdev);
193extern int evergreen_get_temp(struct radeon_device *rdev);
194extern int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher1bd47d22012-03-20 17:18:10 -0400195extern int si_get_temp(struct radeon_device *rdev);
Jerome Glisse285484e2011-12-16 17:03:42 -0500196extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
197 unsigned *bankh, unsigned *mtaspect,
198 unsigned *tile_split);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000199
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200200/*
201 * Fences.
202 */
203struct radeon_fence_driver {
204 uint32_t scratch_reg;
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000205 uint64_t gpu_addr;
206 volatile uint32_t *cpu_addr;
Christian König68e250b2012-05-10 15:57:31 +0200207 /* sync_seq is protected by ring emission lock */
208 uint64_t sync_seq[RADEON_NUM_RINGS];
Jerome Glissebb635562012-05-09 15:34:46 +0200209 atomic64_t last_seq;
Christian König36abaca2012-05-02 15:11:13 +0200210 unsigned long last_activity;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100211 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212};
213
214struct radeon_fence {
215 struct radeon_device *rdev;
216 struct kref kref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200217 /* protected by radeon_fence.lock */
Jerome Glissebb635562012-05-09 15:34:46 +0200218 uint64_t seq;
Alex Deucher74652802011-08-25 13:39:48 -0400219 /* RB, DMA, etc. */
Jerome Glissebb635562012-05-09 15:34:46 +0200220 unsigned ring;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200221};
222
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000223int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
224int radeon_fence_driver_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200225void radeon_fence_driver_fini(struct radeon_device *rdev);
Christian König876dc9f2012-05-08 14:24:01 +0200226int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Alex Deucher74652802011-08-25 13:39:48 -0400227void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228bool radeon_fence_signaled(struct radeon_fence *fence);
229int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Christian König8a47cc92012-05-09 15:34:48 +0200230int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
Christian König7ecc45e2012-06-29 11:33:12 +0200231void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
Jerome Glisse0085c9502012-05-09 15:34:55 +0200232int radeon_fence_wait_any(struct radeon_device *rdev,
233 struct radeon_fence **fences,
234 bool intr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
236void radeon_fence_unref(struct radeon_fence **fence);
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200237unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Christian König68e250b2012-05-10 15:57:31 +0200238bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
239void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
240static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
241 struct radeon_fence *b)
242{
243 if (!a) {
244 return b;
245 }
246
247 if (!b) {
248 return a;
249 }
250
251 BUG_ON(a->ring != b->ring);
252
253 if (a->seq > b->seq) {
254 return a;
255 } else {
256 return b;
257 }
258}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200259
Christian Königee60e292012-08-09 16:21:08 +0200260static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
261 struct radeon_fence *b)
262{
263 if (!a) {
264 return false;
265 }
266
267 if (!b) {
268 return true;
269 }
270
271 BUG_ON(a->ring != b->ring);
272
273 return a->seq < b->seq;
274}
275
Dave Airliee024e112009-06-24 09:48:08 +1000276/*
277 * Tiling registers
278 */
279struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100280 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000281};
282
283#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200284
285/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100286 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200287 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100288struct radeon_mman {
289 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000290 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100291 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100292 bool mem_global_referenced;
293 bool initialized;
Jerome Glisse4c788672009-11-20 14:29:23 +0100294};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295
Jerome Glisse721604a2012-01-05 22:11:05 -0500296/* bo virtual address in a specific vm */
297struct radeon_bo_va {
Christian Könige971bd52012-09-11 16:10:04 +0200298 /* protected by bo being reserved */
Jerome Glisse721604a2012-01-05 22:11:05 -0500299 struct list_head bo_list;
Jerome Glisse721604a2012-01-05 22:11:05 -0500300 uint64_t soffset;
301 uint64_t eoffset;
302 uint32_t flags;
303 bool valid;
Christian Könige971bd52012-09-11 16:10:04 +0200304 unsigned ref_count;
305
306 /* protected by vm mutex */
307 struct list_head vm_list;
308
309 /* constant after initialization */
310 struct radeon_vm *vm;
311 struct radeon_bo *bo;
Jerome Glisse721604a2012-01-05 22:11:05 -0500312};
313
Jerome Glisse4c788672009-11-20 14:29:23 +0100314struct radeon_bo {
315 /* Protected by gem.mutex */
316 struct list_head list;
317 /* Protected by tbo.reserved */
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100318 u32 placements[3];
319 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100320 struct ttm_buffer_object tbo;
321 struct ttm_bo_kmap_obj kmap;
322 unsigned pin_count;
323 void *kptr;
324 u32 tiling_flags;
325 u32 pitch;
326 int surface_reg;
Jerome Glisse721604a2012-01-05 22:11:05 -0500327 /* list of all virtual address to which this bo
328 * is associated to
329 */
330 struct list_head va;
Jerome Glisse4c788672009-11-20 14:29:23 +0100331 /* Constant after initialization */
332 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100333 struct drm_gem_object gem_base;
Dave Airlie63bc6202012-05-31 13:52:53 +0100334
335 struct ttm_bo_kmap_obj dma_buf_vmap;
336 int vmapping_count;
Jerome Glisse4c788672009-11-20 14:29:23 +0100337};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100338#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100339
340struct radeon_bo_list {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000341 struct ttm_validate_buffer tv;
Jerome Glisse4c788672009-11-20 14:29:23 +0100342 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200343 uint64_t gpu_offset;
344 unsigned rdomain;
345 unsigned wdomain;
Jerome Glisse4c788672009-11-20 14:29:23 +0100346 u32 tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200347};
348
Jerome Glisseb15ba512011-11-15 11:48:34 -0500349/* sub-allocation manager, it has to be protected by another lock.
350 * By conception this is an helper for other part of the driver
351 * like the indirect buffer or semaphore, which both have their
352 * locking.
353 *
354 * Principe is simple, we keep a list of sub allocation in offset
355 * order (first entry has offset == 0, last entry has the highest
356 * offset).
357 *
358 * When allocating new object we first check if there is room at
359 * the end total_size - (last_object_offset + last_object_size) >=
360 * alloc_size. If so we allocate new object there.
361 *
362 * When there is not enough room at the end, we start waiting for
363 * each sub object until we reach object_offset+object_size >=
364 * alloc_size, this object then become the sub object we return.
365 *
366 * Alignment can't be bigger than page size.
367 *
368 * Hole are not considered for allocation to keep things simple.
369 * Assumption is that there won't be hole (all object on same
370 * alignment).
371 */
372struct radeon_sa_manager {
Christian Königbfb38d32012-07-11 21:07:57 +0200373 wait_queue_head_t wq;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500374 struct radeon_bo *bo;
Christian Königc3b7fe82012-05-09 15:34:56 +0200375 struct list_head *hole;
376 struct list_head flist[RADEON_NUM_RINGS];
377 struct list_head olist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500378 unsigned size;
379 uint64_t gpu_addr;
380 void *cpu_ptr;
381 uint32_t domain;
382};
383
384struct radeon_sa_bo;
385
386/* sub-allocation buffer */
387struct radeon_sa_bo {
Christian Königc3b7fe82012-05-09 15:34:56 +0200388 struct list_head olist;
389 struct list_head flist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500390 struct radeon_sa_manager *manager;
Christian Könige6661a92012-05-09 15:34:52 +0200391 unsigned soffset;
392 unsigned eoffset;
Christian König557017a2012-05-09 15:34:54 +0200393 struct radeon_fence *fence;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500394};
395
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200396/*
397 * GEM objects.
398 */
399struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100400 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200401 struct list_head objects;
402};
403
404int radeon_gem_init(struct radeon_device *rdev);
405void radeon_gem_fini(struct radeon_device *rdev);
406int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100407 int alignment, int initial_domain,
408 bool discardable, bool kernel,
409 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200410
Dave Airlieff72145b2011-02-07 12:16:14 +1000411int radeon_mode_dumb_create(struct drm_file *file_priv,
412 struct drm_device *dev,
413 struct drm_mode_create_dumb *args);
414int radeon_mode_dumb_mmap(struct drm_file *filp,
415 struct drm_device *dev,
416 uint32_t handle, uint64_t *offset_p);
417int radeon_mode_dumb_destroy(struct drm_file *file_priv,
418 struct drm_device *dev,
419 uint32_t handle);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200420
421/*
Jerome Glissec1341e52011-12-21 12:13:47 -0500422 * Semaphores.
423 */
Jerome Glissec1341e52011-12-21 12:13:47 -0500424/* everything here is constant */
425struct radeon_semaphore {
Jerome Glissea8c05942012-05-09 15:34:57 +0200426 struct radeon_sa_bo *sa_bo;
427 signed waiters;
Jerome Glissec1341e52011-12-21 12:13:47 -0500428 uint64_t gpu_addr;
Jerome Glissec1341e52011-12-21 12:13:47 -0500429};
430
Jerome Glissec1341e52011-12-21 12:13:47 -0500431int radeon_semaphore_create(struct radeon_device *rdev,
432 struct radeon_semaphore **semaphore);
433void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
434 struct radeon_semaphore *semaphore);
435void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
436 struct radeon_semaphore *semaphore);
Christian König8f676c42012-05-02 15:11:18 +0200437int radeon_semaphore_sync_rings(struct radeon_device *rdev,
438 struct radeon_semaphore *semaphore,
Christian König220907d2012-05-10 16:46:43 +0200439 int signaler, int waiter);
Jerome Glissec1341e52011-12-21 12:13:47 -0500440void radeon_semaphore_free(struct radeon_device *rdev,
Christian König220907d2012-05-10 16:46:43 +0200441 struct radeon_semaphore **semaphore,
Jerome Glissea8c05942012-05-09 15:34:57 +0200442 struct radeon_fence *fence);
Jerome Glissec1341e52011-12-21 12:13:47 -0500443
444/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200445 * GART structures, functions & helpers
446 */
447struct radeon_mc;
448
Matt Turnera77f1712009-10-14 00:34:41 -0400449#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000450#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400451#define RADEON_GPU_PAGE_SHIFT 12
Jerome Glisse721604a2012-01-05 22:11:05 -0500452#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
Matt Turnera77f1712009-10-14 00:34:41 -0400453
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200454struct radeon_gart {
455 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400456 struct radeon_bo *robj;
457 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200458 unsigned num_gpu_pages;
459 unsigned num_cpu_pages;
460 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200461 struct page **pages;
462 dma_addr_t *pages_addr;
463 bool ready;
464};
465
466int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
467void radeon_gart_table_ram_free(struct radeon_device *rdev);
468int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
469void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400470int radeon_gart_table_vram_pin(struct radeon_device *rdev);
471void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200472int radeon_gart_init(struct radeon_device *rdev);
473void radeon_gart_fini(struct radeon_device *rdev);
474void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
475 int pages);
476int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500477 int pages, struct page **pagelist,
478 dma_addr_t *dma_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400479void radeon_gart_restore(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200480
481
482/*
483 * GPU MC structures, functions & helpers
484 */
485struct radeon_mc {
486 resource_size_t aper_size;
487 resource_size_t aper_base;
488 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000489 /* for some chips with <= 32MB we need to lie
490 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000491 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000492 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000493 u64 gtt_size;
494 u64 gtt_start;
495 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000496 u64 vram_start;
497 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200498 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000499 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200500 int vram_mtrr;
501 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000502 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400503 u64 gtt_base_align;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200504};
505
Alex Deucher06b64762010-01-05 11:27:29 -0500506bool radeon_combios_sideport_present(struct radeon_device *rdev);
507bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200508
509/*
510 * GPU scratch registers structures, functions & helpers
511 */
512struct radeon_scratch {
513 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400514 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200515 bool free[32];
516 uint32_t reg[32];
517};
518
519int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
520void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
521
522
523/*
524 * IRQS.
525 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500526
527struct radeon_unpin_work {
528 struct work_struct work;
529 struct radeon_device *rdev;
530 int crtc_id;
531 struct radeon_fence *fence;
532 struct drm_pending_vblank_event *event;
533 struct radeon_bo *old_rbo;
534 u64 new_crtc_base;
535};
536
537struct r500_irq_stat_regs {
538 u32 disp_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400539 u32 hdmi0_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500540};
541
542struct r600_irq_stat_regs {
543 u32 disp_int;
544 u32 disp_int_cont;
545 u32 disp_int_cont2;
546 u32 d1grph_int;
547 u32 d2grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400548 u32 hdmi0_status;
549 u32 hdmi1_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500550};
551
552struct evergreen_irq_stat_regs {
553 u32 disp_int;
554 u32 disp_int_cont;
555 u32 disp_int_cont2;
556 u32 disp_int_cont3;
557 u32 disp_int_cont4;
558 u32 disp_int_cont5;
559 u32 d1grph_int;
560 u32 d2grph_int;
561 u32 d3grph_int;
562 u32 d4grph_int;
563 u32 d5grph_int;
564 u32 d6grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400565 u32 afmt_status1;
566 u32 afmt_status2;
567 u32 afmt_status3;
568 u32 afmt_status4;
569 u32 afmt_status5;
570 u32 afmt_status6;
Alex Deucher6f34be52010-11-21 10:59:01 -0500571};
572
573union radeon_irq_stat_regs {
574 struct r500_irq_stat_regs r500;
575 struct r600_irq_stat_regs r600;
576 struct evergreen_irq_stat_regs evergreen;
577};
578
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400579#define RADEON_MAX_HPD_PINS 6
580#define RADEON_MAX_CRTCS 6
Alex Deucherf122c612012-03-30 08:59:57 -0400581#define RADEON_MAX_AFMT_BLOCKS 6
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400582
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200583struct radeon_irq {
Christian Koenigfb982572012-05-17 01:33:30 +0200584 bool installed;
585 spinlock_t lock;
Christian Koenig736fc372012-05-17 19:52:00 +0200586 atomic_t ring_int[RADEON_NUM_RINGS];
Christian Koenigfb982572012-05-17 01:33:30 +0200587 bool crtc_vblank_int[RADEON_MAX_CRTCS];
Christian Koenig736fc372012-05-17 19:52:00 +0200588 atomic_t pflip[RADEON_MAX_CRTCS];
Christian Koenigfb982572012-05-17 01:33:30 +0200589 wait_queue_head_t vblank_queue;
590 bool hpd[RADEON_MAX_HPD_PINS];
Christian Koenigfb982572012-05-17 01:33:30 +0200591 bool afmt[RADEON_MAX_AFMT_BLOCKS];
592 union radeon_irq_stat_regs stat_regs;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200593};
594
595int radeon_irq_kms_init(struct radeon_device *rdev);
596void radeon_irq_kms_fini(struct radeon_device *rdev);
Alex Deucher1b370782011-11-17 20:13:28 -0500597void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
598void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
Alex Deucher6f34be52010-11-21 10:59:01 -0500599void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
600void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Christian Koenigfb982572012-05-17 01:33:30 +0200601void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
602void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
603void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
604void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200605
606/*
Christian Könige32eb502011-10-23 12:56:27 +0200607 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200608 */
Alex Deucher74652802011-08-25 13:39:48 -0400609
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200610struct radeon_ib {
Jerome Glisse68470ae2012-05-09 15:35:00 +0200611 struct radeon_sa_bo *sa_bo;
612 uint32_t length_dw;
613 uint64_t gpu_addr;
614 uint32_t *ptr;
Christian König876dc9f2012-05-08 14:24:01 +0200615 int ring;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200616 struct radeon_fence *fence;
Christian König4bf3dd92012-08-06 18:57:44 +0200617 struct radeon_vm *vm;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200618 bool is_const_ib;
Christian König220907d2012-05-10 16:46:43 +0200619 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
Jerome Glisse68470ae2012-05-09 15:35:00 +0200620 struct radeon_semaphore *semaphore;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200621};
622
Christian Könige32eb502011-10-23 12:56:27 +0200623struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100624 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200625 volatile uint32_t *ring;
626 unsigned rptr;
Christian König5596a9d2011-10-13 12:48:45 +0200627 unsigned rptr_offs;
628 unsigned rptr_reg;
Christian König45df6802012-07-06 16:22:55 +0200629 unsigned rptr_save_reg;
Alex Deucher89d35802012-07-17 14:02:31 -0400630 u64 next_rptr_gpu_addr;
631 volatile u32 *next_rptr_cpu_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200632 unsigned wptr;
633 unsigned wptr_old;
Christian König5596a9d2011-10-13 12:48:45 +0200634 unsigned wptr_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200635 unsigned ring_size;
636 unsigned ring_free_dw;
637 int count_dw;
Christian König069211e2012-05-02 15:11:20 +0200638 unsigned long last_activity;
639 unsigned last_rptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200640 uint64_t gpu_addr;
641 uint32_t align_mask;
642 uint32_t ptr_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200643 bool ready;
Alex Deucher78c55602011-11-17 14:25:56 -0500644 u32 ptr_reg_shift;
645 u32 ptr_reg_mask;
646 u32 nop;
Alex Deucher8b25ed32012-07-17 14:02:30 -0400647 u32 idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200648};
649
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500650/*
Jerome Glisse721604a2012-01-05 22:11:05 -0500651 * VM
652 */
Christian Königee60e292012-08-09 16:21:08 +0200653
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200654/* maximum number of VMIDs */
Christian Königee60e292012-08-09 16:21:08 +0200655#define RADEON_NUM_VM 16
656
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200657/* defines number of bits in page table versus page directory,
658 * a page is 4KB so we have 12 bits offset, 9 bits in the page
659 * table and the remaining 19 bits are in the page directory */
660#define RADEON_VM_BLOCK_SIZE 9
661
662/* number of entries in page table */
663#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
664
Jerome Glisse721604a2012-01-05 22:11:05 -0500665struct radeon_vm {
666 struct list_head list;
667 struct list_head va;
Christian Königee60e292012-08-09 16:21:08 +0200668 unsigned id;
Christian König90a51a32012-10-09 13:31:17 +0200669
670 /* contains the page directory */
671 struct radeon_sa_bo *page_directory;
672 uint64_t pd_gpu_addr;
673
674 /* array of page tables, one for each page directory entry */
675 struct radeon_sa_bo **page_tables;
676
Jerome Glisse721604a2012-01-05 22:11:05 -0500677 struct mutex mutex;
678 /* last fence for cs using this vm */
679 struct radeon_fence *fence;
Christian König9b40e5d2012-08-08 12:22:43 +0200680 /* last flush or NULL if we still need to flush */
681 struct radeon_fence *last_flush;
Jerome Glisse721604a2012-01-05 22:11:05 -0500682};
683
Jerome Glisse721604a2012-01-05 22:11:05 -0500684struct radeon_vm_manager {
Christian König36ff39c2012-05-09 10:07:08 +0200685 struct mutex lock;
Jerome Glisse721604a2012-01-05 22:11:05 -0500686 struct list_head lru_vm;
Christian Königee60e292012-08-09 16:21:08 +0200687 struct radeon_fence *active[RADEON_NUM_VM];
Jerome Glisse721604a2012-01-05 22:11:05 -0500688 struct radeon_sa_manager sa_manager;
689 uint32_t max_pfn;
Jerome Glisse721604a2012-01-05 22:11:05 -0500690 /* number of VMIDs */
691 unsigned nvm;
692 /* vram base address for page table entry */
693 u64 vram_base_offset;
Alex Deucher67e915e2012-01-06 09:38:15 -0500694 /* is vm enabled? */
695 bool enabled;
Jerome Glisse721604a2012-01-05 22:11:05 -0500696};
697
698/*
699 * file private structure
700 */
701struct radeon_fpriv {
702 struct radeon_vm vm;
703};
704
705/*
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500706 * R6xx+ IH ring
707 */
708struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100709 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500710 volatile uint32_t *ring;
711 unsigned rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500712 unsigned ring_size;
713 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500714 uint32_t ptr_mask;
Christian Koenigc20dc362012-05-16 21:45:24 +0200715 atomic_t lock;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500716 bool enabled;
717};
718
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400719struct r600_blit_cp_primitives {
720 void (*set_render_target)(struct radeon_device *rdev, int format,
721 int w, int h, u64 gpu_addr);
722 void (*cp_set_surface_sync)(struct radeon_device *rdev,
723 u32 sync_type, u32 size,
724 u64 mc_addr);
725 void (*set_shaders)(struct radeon_device *rdev);
726 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
727 void (*set_tex_resource)(struct radeon_device *rdev,
728 int format, int w, int h, int pitch,
Alex Deucher9bb77032011-10-22 10:07:09 -0400729 u64 gpu_addr, u32 size);
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400730 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
731 int x2, int y2);
732 void (*draw_auto)(struct radeon_device *rdev);
733 void (*set_default_state)(struct radeon_device *rdev);
734};
735
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000736struct r600_blit {
Jerome Glisse4c788672009-11-20 14:29:23 +0100737 struct radeon_bo *shader_obj;
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400738 struct r600_blit_cp_primitives primitives;
739 int max_dim;
740 int ring_size_common;
741 int ring_size_per_loop;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000742 u64 shader_gpu_addr;
743 u32 vs_offset, ps_offset;
744 u32 state_offset;
745 u32 state_len;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000746};
747
Alex Deucher347e7592012-03-20 17:18:21 -0400748/*
749 * SI RLC stuff
750 */
751struct si_rlc {
752 /* for power gating */
753 struct radeon_bo *save_restore_obj;
754 uint64_t save_restore_gpu_addr;
755 /* for clear state */
756 struct radeon_bo *clear_state_obj;
757 uint64_t clear_state_gpu_addr;
758};
759
Jerome Glisse69e130a2011-12-21 12:13:46 -0500760int radeon_ib_get(struct radeon_device *rdev, int ring,
Christian König4bf3dd92012-08-06 18:57:44 +0200761 struct radeon_ib *ib, struct radeon_vm *vm,
762 unsigned size);
Jerome Glissef2e39222012-05-09 15:35:02 +0200763void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4ef72562012-07-13 13:06:00 +0200764int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
765 struct radeon_ib *const_ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200766int radeon_ib_pool_init(struct radeon_device *rdev);
767void radeon_ib_pool_fini(struct radeon_device *rdev);
Christian König7bd560e2012-05-02 15:11:12 +0200768int radeon_ib_ring_tests(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200769/* Ring access between begin & end cannot sleep */
Alex Deucher89d35802012-07-17 14:02:31 -0400770bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
771 struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200772void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
773int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
774int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
775void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
776void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königd6999bc2012-05-09 15:34:45 +0200777void radeon_ring_undo(struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200778void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
779int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian König7b9ef162012-05-02 15:11:23 +0200780void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König069211e2012-05-02 15:11:20 +0200781void radeon_ring_lockup_update(struct radeon_ring *ring);
782bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König55d7c222012-07-09 11:52:44 +0200783unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
784 uint32_t **data);
785int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
786 unsigned size, uint32_t *data);
Christian Könige32eb502011-10-23 12:56:27 +0200787int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Alex Deucher78c55602011-11-17 14:25:56 -0500788 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
789 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
Christian Könige32eb502011-10-23 12:56:27 +0200790void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200791
792
Alex Deucher4d756582012-09-27 15:08:35 -0400793/* r600 async dma */
794void r600_dma_stop(struct radeon_device *rdev);
795int r600_dma_resume(struct radeon_device *rdev);
796void r600_dma_fini(struct radeon_device *rdev);
797
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200798/*
799 * CS.
800 */
801struct radeon_cs_reloc {
802 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100803 struct radeon_bo *robj;
804 struct radeon_bo_list lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200805 uint32_t handle;
806 uint32_t flags;
807};
808
809struct radeon_cs_chunk {
810 uint32_t chunk_id;
811 uint32_t length_dw;
Jerome Glisse721604a2012-01-05 22:11:05 -0500812 int kpage_idx[2];
813 uint32_t *kpage[2];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200814 uint32_t *kdata;
Jerome Glisse721604a2012-01-05 22:11:05 -0500815 void __user *user_ptr;
816 int last_copied_page;
817 int last_page_index;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200818};
819
820struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +0100821 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200822 struct radeon_device *rdev;
823 struct drm_file *filp;
824 /* chunks */
825 unsigned nchunks;
826 struct radeon_cs_chunk *chunks;
827 uint64_t *chunks_array;
828 /* IB */
829 unsigned idx;
830 /* relocations */
831 unsigned nrelocs;
832 struct radeon_cs_reloc *relocs;
833 struct radeon_cs_reloc **relocs_ptr;
834 struct list_head validated;
835 /* indices of various chunks */
836 int chunk_ib_idx;
837 int chunk_relocs_idx;
Jerome Glisse721604a2012-01-05 22:11:05 -0500838 int chunk_flags_idx;
Alex Deucherdfcf5f32012-03-20 17:18:14 -0400839 int chunk_const_ib_idx;
Jerome Glissef2e39222012-05-09 15:35:02 +0200840 struct radeon_ib ib;
841 struct radeon_ib const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200842 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000843 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +0200844 int parser_error;
Jerome Glisse721604a2012-01-05 22:11:05 -0500845 u32 cs_flags;
846 u32 ring;
847 s32 priority;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200848};
849
Dave Airlie513bcb42009-09-23 16:56:27 +1000850extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
Andi Kleence580fa2011-10-13 16:08:47 -0700851extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
Dave Airlie513bcb42009-09-23 16:56:27 +1000852
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200853struct radeon_cs_packet {
854 unsigned idx;
855 unsigned type;
856 unsigned reg;
857 unsigned opcode;
858 int count;
859 unsigned one_reg_wr;
860};
861
862typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
863 struct radeon_cs_packet *pkt,
864 unsigned idx, unsigned reg);
865typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
866 struct radeon_cs_packet *pkt);
867
868
869/*
870 * AGP
871 */
872int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +1000873void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +0200874void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200875void radeon_agp_fini(struct radeon_device *rdev);
876
877
878/*
879 * Writeback
880 */
881struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +0100882 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200883 volatile uint32_t *wb;
884 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -0400885 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400886 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200887};
888
Alex Deucher724c80e2010-08-27 18:25:25 -0400889#define RADEON_WB_SCRATCH_OFFSET 0
Alex Deucher89d35802012-07-17 14:02:31 -0400890#define RADEON_WB_RING0_NEXT_RPTR 256
Alex Deucher724c80e2010-08-27 18:25:25 -0400891#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -0500892#define RADEON_WB_CP1_RPTR_OFFSET 1280
893#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher4d756582012-09-27 15:08:35 -0400894#define R600_WB_DMA_RPTR_OFFSET 1792
Alex Deucher724c80e2010-08-27 18:25:25 -0400895#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherd0f8a852010-09-04 05:04:34 -0400896#define R600_WB_EVENT_OFFSET 3072
Alex Deucher724c80e2010-08-27 18:25:25 -0400897
Jerome Glissec93bb852009-07-13 21:04:08 +0200898/**
899 * struct radeon_pm - power management datas
900 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
901 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
902 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
903 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
904 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
905 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
906 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
907 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
908 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300909 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +0200910 * @needed_bandwidth: current bandwidth needs
911 *
912 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300913 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +0200914 * Equation between gpu/memory clock and available bandwidth is hw dependent
915 * (type of memory, bus size, efficiency, ...)
916 */
Alex Deucherce8f5372010-05-07 15:10:16 -0400917
918enum radeon_pm_method {
919 PM_METHOD_PROFILE,
920 PM_METHOD_DYNPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +0100921};
Alex Deucherce8f5372010-05-07 15:10:16 -0400922
923enum radeon_dynpm_state {
924 DYNPM_STATE_DISABLED,
925 DYNPM_STATE_MINIMUM,
926 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +0000927 DYNPM_STATE_ACTIVE,
928 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -0400929};
930enum radeon_dynpm_action {
931 DYNPM_ACTION_NONE,
932 DYNPM_ACTION_MINIMUM,
933 DYNPM_ACTION_DOWNCLOCK,
934 DYNPM_ACTION_UPCLOCK,
935 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +0100936};
Alex Deucher56278a82009-12-28 13:58:44 -0500937
938enum radeon_voltage_type {
939 VOLTAGE_NONE = 0,
940 VOLTAGE_GPIO,
941 VOLTAGE_VDDC,
942 VOLTAGE_SW
943};
944
Alex Deucher0ec0e742009-12-23 13:21:58 -0500945enum radeon_pm_state_type {
946 POWER_STATE_TYPE_DEFAULT,
947 POWER_STATE_TYPE_POWERSAVE,
948 POWER_STATE_TYPE_BATTERY,
949 POWER_STATE_TYPE_BALANCED,
950 POWER_STATE_TYPE_PERFORMANCE,
951};
952
Alex Deucherce8f5372010-05-07 15:10:16 -0400953enum radeon_pm_profile_type {
954 PM_PROFILE_DEFAULT,
955 PM_PROFILE_AUTO,
956 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -0400957 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -0400958 PM_PROFILE_HIGH,
959};
960
961#define PM_PROFILE_DEFAULT_IDX 0
962#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -0400963#define PM_PROFILE_MID_SH_IDX 2
964#define PM_PROFILE_HIGH_SH_IDX 3
965#define PM_PROFILE_LOW_MH_IDX 4
966#define PM_PROFILE_MID_MH_IDX 5
967#define PM_PROFILE_HIGH_MH_IDX 6
968#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -0400969
970struct radeon_pm_profile {
971 int dpms_off_ps_idx;
972 int dpms_on_ps_idx;
973 int dpms_off_cm_idx;
974 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -0500975};
976
Alex Deucher21a81222010-07-02 12:58:16 -0400977enum radeon_int_thermal_type {
978 THERMAL_TYPE_NONE,
979 THERMAL_TYPE_RV6XX,
980 THERMAL_TYPE_RV770,
981 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -0500982 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -0500983 THERMAL_TYPE_NI,
Alex Deucher14607d02012-03-20 17:18:09 -0400984 THERMAL_TYPE_SI,
Alex Deucher21a81222010-07-02 12:58:16 -0400985};
986
Alex Deucher56278a82009-12-28 13:58:44 -0500987struct radeon_voltage {
988 enum radeon_voltage_type type;
989 /* gpio voltage */
990 struct radeon_gpio_rec gpio;
991 u32 delay; /* delay in usec from voltage drop to sclk change */
992 bool active_high; /* voltage drop is active when bit is high */
993 /* VDDC voltage */
994 u8 vddc_id; /* index into vddc voltage table */
995 u8 vddci_id; /* index into vddci voltage table */
996 bool vddci_enabled;
997 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -0400998 u16 voltage;
999 /* evergreen+ vddci */
1000 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -05001001};
1002
Alex Deucherd7311172010-05-03 01:13:14 -04001003/* clock mode flags */
1004#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1005
Alex Deucher56278a82009-12-28 13:58:44 -05001006struct radeon_pm_clock_info {
1007 /* memory clock */
1008 u32 mclk;
1009 /* engine clock */
1010 u32 sclk;
1011 /* voltage info */
1012 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -04001013 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -05001014 u32 flags;
1015};
1016
Alex Deuchera48b9b42010-04-22 14:03:55 -04001017/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -04001018#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -04001019
Alex Deucher56278a82009-12-28 13:58:44 -05001020struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -05001021 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -04001022 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -05001023 /* number of valid clock modes in this power state */
1024 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -05001025 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001026 /* standardized state flags */
1027 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -04001028 u32 misc; /* vbios specific flags */
1029 u32 misc2; /* vbios specific flags */
1030 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -05001031};
1032
Rafał Miłecki27459322010-02-11 22:16:36 +00001033/*
1034 * Some modes are overclocked by very low value, accept them
1035 */
1036#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1037
Jerome Glissec93bb852009-07-13 21:04:08 +02001038struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +01001039 struct mutex mutex;
Christian Königdb7fce32012-05-11 14:57:18 +02001040 /* write locked while reprogramming mclk */
1041 struct rw_semaphore mclk_lock;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001042 u32 active_crtcs;
1043 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +01001044 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +01001045 bool vblank_sync;
Jerome Glissec93bb852009-07-13 21:04:08 +02001046 fixed20_12 max_bandwidth;
1047 fixed20_12 igp_sideport_mclk;
1048 fixed20_12 igp_system_mclk;
1049 fixed20_12 igp_ht_link_clk;
1050 fixed20_12 igp_ht_link_width;
1051 fixed20_12 k8_bandwidth;
1052 fixed20_12 sideport_bandwidth;
1053 fixed20_12 ht_bandwidth;
1054 fixed20_12 core_bandwidth;
1055 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -04001056 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +02001057 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -05001058 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -05001059 /* number of valid power states */
1060 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001061 int current_power_state_index;
1062 int current_clock_mode_index;
1063 int requested_power_state_index;
1064 int requested_clock_mode_index;
1065 int default_power_state_index;
1066 u32 current_sclk;
1067 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001068 u16 current_vddc;
1069 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -05001070 u32 default_sclk;
1071 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001072 u16 default_vddc;
1073 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -05001074 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -04001075 /* selected pm method */
1076 enum radeon_pm_method pm_method;
1077 /* dynpm power management */
1078 struct delayed_work dynpm_idle_work;
1079 enum radeon_dynpm_state dynpm_state;
1080 enum radeon_dynpm_action dynpm_planned_action;
1081 unsigned long dynpm_action_timeout;
1082 bool dynpm_can_upclock;
1083 bool dynpm_can_downclock;
1084 /* profile-based power management */
1085 enum radeon_pm_profile_type profile;
1086 int profile_index;
1087 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -04001088 /* internal thermal controller on rv6xx+ */
1089 enum radeon_int_thermal_type int_thermal_type;
1090 struct device *int_hwmon_dev;
Jerome Glissec93bb852009-07-13 21:04:08 +02001091};
1092
Alex Deuchera4c9e2e2011-11-04 10:09:41 -04001093int radeon_pm_get_type_index(struct radeon_device *rdev,
1094 enum radeon_pm_state_type ps_type,
1095 int instance);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001096
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001097struct r600_audio {
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001098 int channels;
1099 int rate;
1100 int bits_per_sample;
1101 u8 status_bits;
1102 u8 category_code;
1103};
1104
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001105/*
1106 * Benchmarking
1107 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -04001108void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001109
1110
1111/*
Michel Dänzerecc0b322009-07-21 11:23:57 +02001112 * Testing
1113 */
1114void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +02001115void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02001116 struct radeon_ring *cpA,
1117 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +02001118void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001119
1120
1121/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001122 * Debugfs
1123 */
Christian König4d8bf9a2011-10-24 14:54:54 +02001124struct radeon_debugfs {
1125 struct drm_info_list *files;
1126 unsigned num_files;
1127};
1128
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001129int radeon_debugfs_add_files(struct radeon_device *rdev,
1130 struct drm_info_list *files,
1131 unsigned nfiles);
1132int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001133
1134
1135/*
1136 * ASIC specific functions.
1137 */
1138struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +02001139 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001140 void (*fini)(struct radeon_device *rdev);
1141 int (*resume)(struct radeon_device *rdev);
1142 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +10001143 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Jerome Glissea2d07b72010-03-09 14:45:11 +00001144 int (*asic_reset)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001145 /* ioctl hw specific callback. Some hw might want to perform special
1146 * operation on specific ioctl. For instance on wait idle some hw
1147 * might want to perform and HDP flush through MMIO as it seems that
1148 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1149 * through ring.
1150 */
1151 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1152 /* check if 3D engine is idle */
1153 bool (*gui_idle)(struct radeon_device *rdev);
1154 /* wait for mc_idle */
1155 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1156 /* gart */
Alex Deucherc5b3b852012-02-23 17:53:46 -05001157 struct {
1158 void (*tlb_flush)(struct radeon_device *rdev);
1159 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1160 } gart;
Christian König05b07142012-08-06 20:21:10 +02001161 struct {
1162 int (*init)(struct radeon_device *rdev);
1163 void (*fini)(struct radeon_device *rdev);
Christian König2a6f1ab2012-08-11 15:00:30 +02001164
1165 u32 pt_ring_index;
Christian Königdce34bf2012-09-17 19:36:18 +02001166 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
1167 uint64_t addr, unsigned count,
1168 uint32_t incr, uint32_t flags);
Christian König05b07142012-08-06 20:21:10 +02001169 } vm;
Alex Deucher54e88e02012-02-23 18:10:29 -05001170 /* ring specific callbacks */
Christian König4c87bc22011-10-19 19:02:21 +02001171 struct {
1172 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse721604a2012-01-05 22:11:05 -05001173 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4c87bc22011-10-19 19:02:21 +02001174 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Christian Könige32eb502011-10-23 12:56:27 +02001175 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König4c87bc22011-10-19 19:02:21 +02001176 struct radeon_semaphore *semaphore, bool emit_wait);
Christian Königeb0c19c2012-02-23 15:18:44 +01001177 int (*cs_parse)(struct radeon_cs_parser *p);
Alex Deucherf7128122012-02-23 17:53:45 -05001178 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1179 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1180 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
Christian König312c4a82012-05-02 15:11:09 +02001181 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher498522b2012-10-02 14:43:38 -04001182 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König4c87bc22011-10-19 19:02:21 +02001183 } ring[RADEON_NUM_RINGS];
Alex Deucher54e88e02012-02-23 18:10:29 -05001184 /* irqs */
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001185 struct {
1186 int (*set)(struct radeon_device *rdev);
1187 int (*process)(struct radeon_device *rdev);
1188 } irq;
Alex Deucher54e88e02012-02-23 18:10:29 -05001189 /* displays */
Alex Deucherc79a49c2012-02-23 17:53:47 -05001190 struct {
1191 /* display watermarks */
1192 void (*bandwidth_update)(struct radeon_device *rdev);
1193 /* get frame count */
1194 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1195 /* wait for vblank */
1196 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001197 /* set backlight level */
1198 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -04001199 /* get backlight level */
1200 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
Alex Deucherc79a49c2012-02-23 17:53:47 -05001201 } display;
Alex Deucher54e88e02012-02-23 18:10:29 -05001202 /* copy functions for bo handling */
Alex Deucher27cd7762012-02-23 17:53:42 -05001203 struct {
1204 int (*blit)(struct radeon_device *rdev,
1205 uint64_t src_offset,
1206 uint64_t dst_offset,
1207 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001208 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001209 u32 blit_ring_index;
1210 int (*dma)(struct radeon_device *rdev,
1211 uint64_t src_offset,
1212 uint64_t dst_offset,
1213 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001214 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001215 u32 dma_ring_index;
1216 /* method used for bo copy */
1217 int (*copy)(struct radeon_device *rdev,
1218 uint64_t src_offset,
1219 uint64_t dst_offset,
1220 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001221 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001222 /* ring used for bo copies */
1223 u32 copy_ring_index;
1224 } copy;
Alex Deucher54e88e02012-02-23 18:10:29 -05001225 /* surfaces */
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001226 struct {
1227 int (*set_reg)(struct radeon_device *rdev, int reg,
1228 uint32_t tiling_flags, uint32_t pitch,
1229 uint32_t offset, uint32_t obj_size);
1230 void (*clear_reg)(struct radeon_device *rdev, int reg);
1231 } surface;
Alex Deucher54e88e02012-02-23 18:10:29 -05001232 /* hotplug detect */
Alex Deucher901ea572012-02-23 17:53:39 -05001233 struct {
1234 void (*init)(struct radeon_device *rdev);
1235 void (*fini)(struct radeon_device *rdev);
1236 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1237 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1238 } hpd;
Alex Deucherce8f5372010-05-07 15:10:16 -04001239 /* power management */
Alex Deuchera02fa392012-02-23 17:53:41 -05001240 struct {
1241 void (*misc)(struct radeon_device *rdev);
1242 void (*prepare)(struct radeon_device *rdev);
1243 void (*finish)(struct radeon_device *rdev);
1244 void (*init_profile)(struct radeon_device *rdev);
1245 void (*get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher798bcf72012-02-23 17:53:48 -05001246 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1247 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1248 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1249 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1250 int (*get_pcie_lanes)(struct radeon_device *rdev);
1251 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1252 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Alex Deuchera02fa392012-02-23 17:53:41 -05001253 } pm;
Alex Deucher6f34be52010-11-21 10:59:01 -05001254 /* pageflipping */
Alex Deucher0f9e0062012-02-23 17:53:40 -05001255 struct {
1256 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1257 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1258 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1259 } pflip;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001260};
1261
Jerome Glisse21f9a432009-09-11 15:55:33 +02001262/*
1263 * Asic structures
1264 */
Dave Airlie551ebd82009-09-01 15:25:57 +10001265struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001266 const unsigned *reg_safe_bm;
1267 unsigned reg_safe_bm_size;
1268 u32 hdp_cntl;
Dave Airlie551ebd82009-09-01 15:25:57 +10001269};
1270
Jerome Glisse21f9a432009-09-11 15:55:33 +02001271struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001272 const unsigned *reg_safe_bm;
1273 unsigned reg_safe_bm_size;
1274 u32 resync_scratch;
1275 u32 hdp_cntl;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001276};
1277
1278struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001279 unsigned max_pipes;
1280 unsigned max_tile_pipes;
1281 unsigned max_simds;
1282 unsigned max_backends;
1283 unsigned max_gprs;
1284 unsigned max_threads;
1285 unsigned max_stack_entries;
1286 unsigned max_hw_contexts;
1287 unsigned max_gs_threads;
1288 unsigned sx_max_export_size;
1289 unsigned sx_max_export_pos_size;
1290 unsigned sx_max_export_smx_size;
1291 unsigned sq_num_cf_insts;
1292 unsigned tiling_nbanks;
1293 unsigned tiling_npipes;
1294 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001295 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001296 unsigned backend_map;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001297};
1298
1299struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001300 unsigned max_pipes;
1301 unsigned max_tile_pipes;
1302 unsigned max_simds;
1303 unsigned max_backends;
1304 unsigned max_gprs;
1305 unsigned max_threads;
1306 unsigned max_stack_entries;
1307 unsigned max_hw_contexts;
1308 unsigned max_gs_threads;
1309 unsigned sx_max_export_size;
1310 unsigned sx_max_export_pos_size;
1311 unsigned sx_max_export_smx_size;
1312 unsigned sq_num_cf_insts;
1313 unsigned sx_num_of_sets;
1314 unsigned sc_prim_fifo_size;
1315 unsigned sc_hiz_tile_fifo_size;
1316 unsigned sc_earlyz_tile_fifo_fize;
1317 unsigned tiling_nbanks;
1318 unsigned tiling_npipes;
1319 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001320 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001321 unsigned backend_map;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001322};
1323
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001324struct evergreen_asic {
1325 unsigned num_ses;
1326 unsigned max_pipes;
1327 unsigned max_tile_pipes;
1328 unsigned max_simds;
1329 unsigned max_backends;
1330 unsigned max_gprs;
1331 unsigned max_threads;
1332 unsigned max_stack_entries;
1333 unsigned max_hw_contexts;
1334 unsigned max_gs_threads;
1335 unsigned sx_max_export_size;
1336 unsigned sx_max_export_pos_size;
1337 unsigned sx_max_export_smx_size;
1338 unsigned sq_num_cf_insts;
1339 unsigned sx_num_of_sets;
1340 unsigned sc_prim_fifo_size;
1341 unsigned sc_hiz_tile_fifo_size;
1342 unsigned sc_earlyz_tile_fifo_size;
1343 unsigned tiling_nbanks;
1344 unsigned tiling_npipes;
1345 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001346 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001347 unsigned backend_map;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001348};
1349
Alex Deucherfecf1d02011-03-02 20:07:29 -05001350struct cayman_asic {
1351 unsigned max_shader_engines;
1352 unsigned max_pipes_per_simd;
1353 unsigned max_tile_pipes;
1354 unsigned max_simds_per_se;
1355 unsigned max_backends_per_se;
1356 unsigned max_texture_channel_caches;
1357 unsigned max_gprs;
1358 unsigned max_threads;
1359 unsigned max_gs_threads;
1360 unsigned max_stack_entries;
1361 unsigned sx_num_of_sets;
1362 unsigned sx_max_export_size;
1363 unsigned sx_max_export_pos_size;
1364 unsigned sx_max_export_smx_size;
1365 unsigned max_hw_contexts;
1366 unsigned sq_num_cf_insts;
1367 unsigned sc_prim_fifo_size;
1368 unsigned sc_hiz_tile_fifo_size;
1369 unsigned sc_earlyz_tile_fifo_size;
1370
1371 unsigned num_shader_engines;
1372 unsigned num_shader_pipes_per_simd;
1373 unsigned num_tile_pipes;
1374 unsigned num_simds_per_se;
1375 unsigned num_backends_per_se;
1376 unsigned backend_disable_mask_per_asic;
1377 unsigned backend_map;
1378 unsigned num_texture_channel_caches;
1379 unsigned mem_max_burst_length_bytes;
1380 unsigned mem_row_size_in_kb;
1381 unsigned shader_engine_tile_size;
1382 unsigned num_gpus;
1383 unsigned multi_gpu_tile_size;
1384
1385 unsigned tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -05001386};
1387
Alex Deucher0a96d722012-03-20 17:18:11 -04001388struct si_asic {
1389 unsigned max_shader_engines;
Alex Deucher0a96d722012-03-20 17:18:11 -04001390 unsigned max_tile_pipes;
Alex Deucher1a8ca752012-06-01 18:58:22 -04001391 unsigned max_cu_per_sh;
1392 unsigned max_sh_per_se;
Alex Deucher0a96d722012-03-20 17:18:11 -04001393 unsigned max_backends_per_se;
1394 unsigned max_texture_channel_caches;
1395 unsigned max_gprs;
1396 unsigned max_gs_threads;
1397 unsigned max_hw_contexts;
1398 unsigned sc_prim_fifo_size_frontend;
1399 unsigned sc_prim_fifo_size_backend;
1400 unsigned sc_hiz_tile_fifo_size;
1401 unsigned sc_earlyz_tile_fifo_size;
1402
Alex Deucher0a96d722012-03-20 17:18:11 -04001403 unsigned num_tile_pipes;
1404 unsigned num_backends_per_se;
1405 unsigned backend_disable_mask_per_asic;
1406 unsigned backend_map;
1407 unsigned num_texture_channel_caches;
1408 unsigned mem_max_burst_length_bytes;
1409 unsigned mem_row_size_in_kb;
1410 unsigned shader_engine_tile_size;
1411 unsigned num_gpus;
1412 unsigned multi_gpu_tile_size;
1413
1414 unsigned tile_config;
Alex Deucher0a96d722012-03-20 17:18:11 -04001415};
1416
Jerome Glisse068a1172009-06-17 13:28:30 +02001417union radeon_asic_config {
1418 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10001419 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001420 struct r600_asic r600;
1421 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001422 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05001423 struct cayman_asic cayman;
Alex Deucher0a96d722012-03-20 17:18:11 -04001424 struct si_asic si;
Jerome Glisse068a1172009-06-17 13:28:30 +02001425};
1426
Daniel Vetter0a10c852010-03-11 21:19:14 +00001427/*
1428 * asic initizalization from radeon_asic.c
1429 */
1430void radeon_agp_disable(struct radeon_device *rdev);
1431int radeon_asic_init(struct radeon_device *rdev);
1432
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001433
1434/*
1435 * IOCTL.
1436 */
1437int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1438 struct drm_file *filp);
1439int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1440 struct drm_file *filp);
1441int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1442 struct drm_file *file_priv);
1443int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv);
1445int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1446 struct drm_file *file_priv);
1447int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *file_priv);
1449int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *filp);
1451int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1452 struct drm_file *filp);
1453int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1454 struct drm_file *filp);
1455int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1456 struct drm_file *filp);
Jerome Glisse721604a2012-01-05 22:11:05 -05001457int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1458 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001459int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10001460int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1461 struct drm_file *filp);
1462int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1463 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001464
Alex Deucher16cdf042011-10-28 10:30:02 -04001465/* VRAM scratch page for HDP bug, default vram page */
1466struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001467 struct radeon_bo *robj;
1468 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04001469 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001470};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001471
Luca Tettamantifd64ca82012-08-16 11:11:18 -04001472/*
1473 * ACPI
1474 */
1475struct radeon_atif_notification_cfg {
1476 bool enabled;
1477 int command_code;
1478};
1479
1480struct radeon_atif_notifications {
1481 bool display_switch;
1482 bool expansion_mode_change;
1483 bool thermal_state;
1484 bool forced_power_state;
1485 bool system_power_state;
1486 bool display_conf_change;
1487 bool px_gfx_switch;
1488 bool brightness_change;
1489 bool dgpu_display_event;
1490};
1491
1492struct radeon_atif_functions {
1493 bool system_params;
1494 bool sbios_requests;
1495 bool select_active_disp;
1496 bool lid_state;
1497 bool get_tv_standard;
1498 bool set_tv_standard;
1499 bool get_panel_expansion_mode;
1500 bool set_panel_expansion_mode;
1501 bool temperature_change;
1502 bool graphics_device_types;
1503};
1504
1505struct radeon_atif {
1506 struct radeon_atif_notifications notifications;
1507 struct radeon_atif_functions functions;
1508 struct radeon_atif_notification_cfg notification_cfg;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001509 struct radeon_encoder *encoder_for_bl;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04001510};
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001511
Alex Deuchere3a15922012-08-16 11:13:43 -04001512struct radeon_atcs_functions {
1513 bool get_ext_state;
1514 bool pcie_perf_req;
1515 bool pcie_dev_rdy;
1516 bool pcie_bus_width;
1517};
1518
1519struct radeon_atcs {
1520 struct radeon_atcs_functions functions;
1521};
1522
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001523/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001524 * Core structure, functions and helpers.
1525 */
1526typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1527typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1528
1529struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001530 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001531 struct drm_device *ddev;
1532 struct pci_dev *pdev;
Jerome Glissedee53e72012-07-02 12:45:19 -04001533 struct rw_semaphore exclusive_lock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001534 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02001535 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001536 enum radeon_family family;
1537 unsigned long flags;
1538 int usec_timeout;
1539 enum radeon_pll_errata pll_errata;
1540 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04001541 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001542 int disp_priority;
1543 /* BIOS */
1544 uint8_t *bios;
1545 bool is_atom_bios;
1546 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01001547 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001548 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10001549 resource_size_t rmmio_base;
1550 resource_size_t rmmio_size;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001551 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001552 radeon_rreg_t mc_rreg;
1553 radeon_wreg_t mc_wreg;
1554 radeon_rreg_t pll_rreg;
1555 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10001556 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001557 radeon_rreg_t pciep_rreg;
1558 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04001559 /* io port */
1560 void __iomem *rio_mem;
1561 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001562 struct radeon_clock clock;
1563 struct radeon_mc mc;
1564 struct radeon_gart gart;
1565 struct radeon_mode_info mode_info;
1566 struct radeon_scratch scratch;
1567 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04001568 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Jerome Glisse0085c9502012-05-09 15:34:55 +02001569 wait_queue_head_t fence_queue;
Christian Königd6999bc2012-05-09 15:34:45 +02001570 struct mutex ring_lock;
Christian Könige32eb502011-10-23 12:56:27 +02001571 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glissec507f7e2012-05-09 15:34:58 +02001572 bool ib_pool_ready;
1573 struct radeon_sa_manager ring_tmp_bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001574 struct radeon_irq irq;
1575 struct radeon_asic *asic;
1576 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02001577 struct radeon_pm pm;
Yang Zhaof657c2a2009-09-15 12:21:01 +10001578 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001579 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001580 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001581 bool shutdown;
1582 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10001583 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02001584 bool accel_working;
Dave Airliee024e112009-06-24 09:48:08 +10001585 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001586 const struct firmware *me_fw; /* all family ME firmware */
1587 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001588 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05001589 const struct firmware *mc_fw; /* NI MC firmware */
Alex Deucher0f0de062012-03-20 17:18:17 -04001590 const struct firmware *ce_fw; /* SI CE firmware */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001591 struct r600_blit r600_blit;
Alex Deucher16cdf042011-10-28 10:30:02 -04001592 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04001593 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001594 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucher347e7592012-03-20 17:18:21 -04001595 struct si_rlc rlc;
Alex Deucherd4877cf2009-12-04 16:56:37 -05001596 struct work_struct hotplug_work;
Alex Deucherf122c612012-03-30 08:59:57 -04001597 struct work_struct audio_work;
Alex Deucher18917b62010-02-01 16:02:25 -05001598 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05001599 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Rafał Miłecki3299de92012-05-14 21:25:57 +02001600 bool audio_enabled;
1601 struct r600_audio audio_status; /* audio stuff */
Alex Deucherce8f5372010-05-07 15:10:16 -04001602 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001603 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10001604 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001605 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04001606 /* i2c buses */
1607 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02001608 /* debugfs */
1609 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1610 unsigned debugfs_count;
Jerome Glisse721604a2012-01-05 22:11:05 -05001611 /* virtual memory */
1612 struct radeon_vm_manager vm_manager;
Marek Olšák6759a0a2012-08-09 16:34:17 +02001613 struct mutex gpu_clock_mutex;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04001614 /* ACPI interface */
1615 struct radeon_atif atif;
Alex Deuchere3a15922012-08-16 11:13:43 -04001616 struct radeon_atcs atcs;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001617};
1618
1619int radeon_device_init(struct radeon_device *rdev,
1620 struct drm_device *ddev,
1621 struct pci_dev *pdev,
1622 uint32_t flags);
1623void radeon_device_fini(struct radeon_device *rdev);
1624int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1625
Andi Kleen6fcbef72011-10-13 16:08:42 -07001626uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1627void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1628u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1629void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04001630
Jerome Glisse4c788672009-11-20 14:29:23 +01001631/*
1632 * Cast helper
1633 */
1634#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001635
1636/*
1637 * Registers read & write functions.
1638 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001639#define RREG8(reg) readb((rdev->rmmio) + (reg))
1640#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1641#define RREG16(reg) readw((rdev->rmmio) + (reg))
1642#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Dave Airliede1b2892009-08-12 18:43:14 +10001643#define RREG32(reg) r100_mm_rreg(rdev, (reg))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001644#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
Dave Airliede1b2892009-08-12 18:43:14 +10001645#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001646#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1647#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1648#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1649#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1650#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1651#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10001652#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1653#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Rafał Miłeckiaa5120d2010-02-18 20:24:28 +00001654#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1655#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001656#define WREG32_P(reg, val, mask) \
1657 do { \
1658 uint32_t tmp_ = RREG32(reg); \
1659 tmp_ &= (mask); \
1660 tmp_ |= ((val) & ~(mask)); \
1661 WREG32(reg, tmp_); \
1662 } while (0)
1663#define WREG32_PLL_P(reg, val, mask) \
1664 do { \
1665 uint32_t tmp_ = RREG32_PLL(reg); \
1666 tmp_ &= (mask); \
1667 tmp_ |= ((val) & ~(mask)); \
1668 WREG32_PLL(reg, tmp_); \
1669 } while (0)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001670#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
Alex Deucher351a52a2010-06-30 11:52:50 -04001671#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1672#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001673
Dave Airliede1b2892009-08-12 18:43:14 +10001674/*
1675 * Indirect registers accessor
1676 */
1677static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1678{
1679 uint32_t r;
1680
1681 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1682 r = RREG32(RADEON_PCIE_DATA);
1683 return r;
1684}
1685
1686static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1687{
1688 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1689 WREG32(RADEON_PCIE_DATA, (v));
1690}
1691
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001692void r100_pll_errata_after_index(struct radeon_device *rdev);
1693
1694
1695/*
1696 * ASICs helpers.
1697 */
Dave Airlieb995e432009-07-14 02:02:32 +10001698#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1699 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001700#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1701 (rdev->family == CHIP_RV200) || \
1702 (rdev->family == CHIP_RS100) || \
1703 (rdev->family == CHIP_RS200) || \
1704 (rdev->family == CHIP_RV250) || \
1705 (rdev->family == CHIP_RV280) || \
1706 (rdev->family == CHIP_RS300))
1707#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1708 (rdev->family == CHIP_RV350) || \
1709 (rdev->family == CHIP_R350) || \
1710 (rdev->family == CHIP_RV380) || \
1711 (rdev->family == CHIP_R420) || \
1712 (rdev->family == CHIP_R423) || \
1713 (rdev->family == CHIP_RV410) || \
1714 (rdev->family == CHIP_RS400) || \
1715 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05001716#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1717 (rdev->ddev->pdev->device == 0x9443) || \
1718 (rdev->ddev->pdev->device == 0x944B) || \
1719 (rdev->ddev->pdev->device == 0x9506) || \
1720 (rdev->ddev->pdev->device == 0x9509) || \
1721 (rdev->ddev->pdev->device == 0x950F) || \
1722 (rdev->ddev->pdev->device == 0x689C) || \
1723 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001724#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05001725#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1726 (rdev->family == CHIP_RS690) || \
1727 (rdev->family == CHIP_RS740) || \
1728 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001729#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1730#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05001731#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05001732#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1733 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05001734#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Alex Deucher8848f752012-03-20 17:18:28 -04001735#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1736#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1737 (rdev->flags & RADEON_IS_IGP))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001738
1739/*
1740 * BIOS helpers.
1741 */
1742#define RBIOS8(i) (rdev->bios[i])
1743#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1744#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1745
1746int radeon_combios_init(struct radeon_device *rdev);
1747void radeon_combios_fini(struct radeon_device *rdev);
1748int radeon_atombios_init(struct radeon_device *rdev);
1749void radeon_atombios_fini(struct radeon_device *rdev);
1750
1751
1752/*
1753 * RING helpers.
1754 */
Andi Kleence580fa2011-10-13 16:08:47 -07001755#if DRM_DEBUG_CODE == 0
Christian Könige32eb502011-10-23 12:56:27 +02001756static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001757{
Christian Könige32eb502011-10-23 12:56:27 +02001758 ring->ring[ring->wptr++] = v;
1759 ring->wptr &= ring->ptr_mask;
1760 ring->count_dw--;
1761 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001762}
Andi Kleence580fa2011-10-13 16:08:47 -07001763#else
1764/* With debugging this is just too big to inline */
Christian Könige32eb502011-10-23 12:56:27 +02001765void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
Andi Kleence580fa2011-10-13 16:08:47 -07001766#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001767
1768/*
1769 * ASICs macro.
1770 */
Jerome Glisse068a1172009-06-17 13:28:30 +02001771#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001772#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1773#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1774#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Christian Königeb0c19c2012-02-23 15:18:44 +01001775#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10001776#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Jerome Glissea2d07b72010-03-09 14:45:11 +00001777#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Alex Deucherc5b3b852012-02-23 17:53:46 -05001778#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1779#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
Christian König05b07142012-08-06 20:21:10 +02001780#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1781#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
Christian Königdce34bf2012-09-17 19:36:18 +02001782#define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
Alex Deucherf7128122012-02-23 17:53:45 -05001783#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1784#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1785#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
Christian König4c87bc22011-10-19 19:02:21 +02001786#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
Jerome Glisse721604a2012-01-05 22:11:05 -05001787#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
Christian König312c4a82012-05-02 15:11:09 +02001788#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
Alex Deucher498522b2012-10-02 14:43:38 -04001789#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001790#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1791#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
Alex Deucherc79a49c2012-02-23 17:53:47 -05001792#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001793#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
Alex Deucher6d92f812012-09-14 09:59:26 -04001794#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
Christian König4c87bc22011-10-19 19:02:21 +02001795#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1796#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Alex Deucher27cd7762012-02-23 17:53:42 -05001797#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1798#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1799#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1800#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1801#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1802#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
Alex Deucher798bcf72012-02-23 17:53:48 -05001803#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1804#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1805#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1806#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1807#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1808#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1809#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001810#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1811#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
Alex Deucherc79a49c2012-02-23 17:53:47 -05001812#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
Alex Deucher901ea572012-02-23 17:53:39 -05001813#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1814#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1815#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1816#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
Alex Deucherdef9ba92010-04-22 12:39:58 -04001817#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera02fa392012-02-23 17:53:41 -05001818#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1819#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1820#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1821#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1822#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
Alex Deucher69b62ad2012-08-03 11:50:54 -04001823#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1824#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1825#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1826#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1827#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001828
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001829/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001830/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001831extern int radeon_gpu_reset(struct radeon_device *rdev);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001832extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001833extern int radeon_modeset_init(struct radeon_device *rdev);
1834extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001835extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04001836extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04001837extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10001838extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001839extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001840extern void radeon_wb_fini(struct radeon_device *rdev);
1841extern int radeon_wb_init(struct radeon_device *rdev);
1842extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001843extern void radeon_surface_init(struct radeon_device *rdev);
1844extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001845extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001846extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01001847extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01001848extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glissed594e462010-02-17 21:54:29 +00001849extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1850extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001851extern int radeon_resume_kms(struct drm_device *dev);
1852extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
Dave Airlie53595332011-03-14 09:47:24 +10001853extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001854
Daniel Vetter3574dda2011-02-18 17:59:19 +01001855/*
Jerome Glisse721604a2012-01-05 22:11:05 -05001856 * vm
1857 */
1858int radeon_vm_manager_init(struct radeon_device *rdev);
1859void radeon_vm_manager_fini(struct radeon_device *rdev);
Christian Königd72d43c2012-10-09 13:31:18 +02001860void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
Jerome Glisse721604a2012-01-05 22:11:05 -05001861void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
Christian Königddf03f52012-08-09 20:02:28 +02001862int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
Christian König13e55c32012-10-09 13:31:19 +02001863void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
Christian Königee60e292012-08-09 16:21:08 +02001864struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1865 struct radeon_vm *vm, int ring);
1866void radeon_vm_fence(struct radeon_device *rdev,
1867 struct radeon_vm *vm,
1868 struct radeon_fence *fence);
Christian Königdce34bf2012-09-17 19:36:18 +02001869uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
Jerome Glisse721604a2012-01-05 22:11:05 -05001870int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1871 struct radeon_vm *vm,
1872 struct radeon_bo *bo,
1873 struct ttm_mem_reg *mem);
1874void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1875 struct radeon_bo *bo);
Christian König421ca7a2012-09-11 16:10:00 +02001876struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1877 struct radeon_bo *bo);
Christian Könige971bd52012-09-11 16:10:04 +02001878struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1879 struct radeon_vm *vm,
1880 struct radeon_bo *bo);
1881int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1882 struct radeon_bo_va *bo_va,
1883 uint64_t offset,
1884 uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -05001885int radeon_vm_bo_rmv(struct radeon_device *rdev,
Christian Könige971bd52012-09-11 16:10:04 +02001886 struct radeon_bo_va *bo_va);
Jerome Glisse721604a2012-01-05 22:11:05 -05001887
Alex Deucherf122c612012-03-30 08:59:57 -04001888/* audio */
1889void r600_audio_update_hdmi(struct work_struct *work);
Jerome Glisse721604a2012-01-05 22:11:05 -05001890
1891/*
Alex Deucher16cdf042011-10-28 10:30:02 -04001892 * R600 vram scratch functions
1893 */
1894int r600_vram_scratch_init(struct radeon_device *rdev);
1895void r600_vram_scratch_fini(struct radeon_device *rdev);
1896
1897/*
Jerome Glisse285484e2011-12-16 17:03:42 -05001898 * r600 cs checking helper
1899 */
1900unsigned r600_mip_minify(unsigned size, unsigned level);
1901bool r600_fmt_is_valid_color(u32 format);
1902bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1903int r600_fmt_get_blocksize(u32 format);
1904int r600_fmt_get_nblocksx(u32 format, u32 w);
1905int r600_fmt_get_nblocksy(u32 format, u32 h);
1906
1907/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01001908 * r600 functions used by radeon_encoder.c
1909 */
Rafał Miłecki1b688d082012-04-30 15:44:54 +02001910struct radeon_hdmi_acr {
1911 u32 clock;
1912
1913 int n_32khz;
1914 int cts_32khz;
1915
1916 int n_44_1khz;
1917 int cts_44_1khz;
1918
1919 int n_48khz;
1920 int cts_48khz;
1921
1922};
1923
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02001924extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1925
Rafał Miłecki2cd6218c2010-03-08 22:14:01 +00001926extern void r600_hdmi_enable(struct drm_encoder *encoder);
1927extern void r600_hdmi_disable(struct drm_encoder *encoder);
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001928extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher416a2bd2012-05-31 19:00:25 -04001929extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1930 u32 tiling_pipe_num,
1931 u32 max_rb_num,
1932 u32 total_max_rb_num,
1933 u32 enabled_rb_mask);
Alex Deucherfe251e22010-03-24 13:36:43 -04001934
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02001935/*
1936 * evergreen functions used by radeon_encoder.c
1937 */
1938
1939extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1940
Alex Deucher0af62b02011-01-06 21:19:31 -05001941extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05001942extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05001943
Alex Deucherc4917072012-07-31 17:14:35 -04001944/* radeon_acpi.c */
1945#if defined(CONFIG_ACPI)
1946extern int radeon_acpi_init(struct radeon_device *rdev);
1947extern void radeon_acpi_fini(struct radeon_device *rdev);
1948#else
1949static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1950static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1951#endif
Alberto Miloned7a29522010-07-06 11:40:24 -04001952
Jerome Glisse4c788672009-11-20 14:29:23 +01001953#include "radeon_object.h"
1954
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001955#endif