blob: 21d8a20d9920445b6e7b6dd7276639ad8344ef49 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Akshay Joshi0206e352011-08-16 15:34:10 -040044bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020045static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010046static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080047
48typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040049 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080058} intel_clock_t;
59
60typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040061 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080062} intel_range_t;
63
64typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040065 int dot_limit;
66 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080067} intel_p2_t;
68
69#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080070typedef struct intel_limit intel_limit_t;
71struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040072 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
Ville Syrjäläf4808ab2013-02-28 19:19:44 +020074 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080092};
Jesse Barnes79e53942008-11-07 14:24:08 -080093
Jesse Barnes2377b742010-07-07 14:06:43 -070094/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
Daniel Vetterd2acd212012-10-20 20:57:43 +020097int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
Ma Lingd4906092009-03-18 20:13:27 +0800107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +0800111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800115
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800120static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700124
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
Chris Wilson021357a2010-09-07 20:54:59 +0100130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
Chris Wilson8b99e682010-10-13 09:59:17 +0100133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100138}
139
Keith Packarde4b36692009-06-05 19:22:17 -0700140static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800151 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800165 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700166};
Eric Anholt273e27c2011-03-30 13:01:10 -0700167
Keith Packarde4b36692009-06-05 19:22:17 -0700168static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800179 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800193 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700194};
195
Eric Anholt273e27c2011-03-30 13:01:10 -0700196
Keith Packarde4b36692009-06-05 19:22:17 -0700197static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800209 },
Ma Lingd4906092009-03-18 20:13:27 +0800210 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800224 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800238 },
Ma Lingd4906092009-03-18 20:13:27 +0800239 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800253 },
Ma Lingd4906092009-03-18 20:13:27 +0800254 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700267 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700269};
270
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500271static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700274 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700277 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800284 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700285};
286
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500287static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800298 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700299};
300
Eric Anholt273e27c2011-03-30 13:01:10 -0700301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800306static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800317 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700318};
319
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800320static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800345 .find_pll = intel_g4x_find_best_PLL,
346};
347
Eric Anholt273e27c2011-03-30 13:01:10 -0700348/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400357 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400371 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700387 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400388 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800389};
390
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
Vijay Purushothaman17dc9252012-09-27 19:13:09 +0530407 .vco = { .min = 4000000, .max = 5994000},
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700422 .n = { .min = 1, .max = 7 },
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530423 .m = { .min = 22, .max = 450 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
Jesse Barnes57f350b2012-03-28 13:39:25 -0700433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
Daniel Vetter09153002012-12-12 14:06:44 +0100435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
Jesse Barnes57f350b2012-03-28 13:39:25 -0700436
Jesse Barnes57f350b2012-03-28 13:39:25 -0700437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
Daniel Vetter09153002012-12-12 14:06:44 +0100439 return 0;
Jesse Barnes57f350b2012-03-28 13:39:25 -0700440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
Daniel Vetter09153002012-12-12 14:06:44 +0100447 return 0;
Jesse Barnes57f350b2012-03-28 13:39:25 -0700448 }
Jesse Barnes57f350b2012-03-28 13:39:25 -0700449
Daniel Vetter09153002012-12-12 14:06:44 +0100450 return I915_READ(DPIO_DATA);
Jesse Barnes57f350b2012-03-28 13:39:25 -0700451}
452
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
Daniel Vetter09153002012-12-12 14:06:44 +0100456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700457
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
Daniel Vetter09153002012-12-12 14:06:44 +0100460 return;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700469}
470
Jesse Barnes57f350b2012-03-28 13:39:25 -0700471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
Chris Wilson1b894b52010-12-14 20:04:54 +0000482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800484{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800485 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800486 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100489 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000490 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000495 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Jani Nikula547dc042012-11-02 11:24:03 +0200501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Zhao Yakui45476682009-12-31 16:06:04 +0800502 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800503 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800504 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800505
506 return limit;
507}
508
Ma Ling044c7c42009-03-18 20:13:23 +0800509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100515 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700516 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800517 else
Keith Packarde4b36692009-06-05 19:22:17 -0700518 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700521 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700523 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700525 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800526 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700527 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800528
529 return limit;
530}
531
Chris Wilson1b894b52010-12-14 20:04:54 +0000532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
Eric Anholtbad720f2009-10-22 16:11:14 -0700537 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000538 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800539 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800540 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500541 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500543 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800544 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500545 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700560 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800561 else
Keith Packarde4b36692009-06-05 19:22:17 -0700562 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800563 }
564 return limit;
565}
566
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800569{
Shaohua Li21778322009-02-23 15:19:16 +0800570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800580 return;
581 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
Jesse Barnes79e53942008-11-07 14:24:08 -0800588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800592{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100593 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100594 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800595
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100598 return true;
599
600 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800601}
602
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
Chris Wilson1b894b52010-12-14 20:04:54 +0000609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800612{
Jesse Barnes79e53942008-11-07 14:24:08 -0800613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400614 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800615 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400616 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400618 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400620 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400622 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800623 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400624 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800625 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400626 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400628 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400633 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800634
635 return true;
636}
637
Ma Lingd4906092009-03-18 20:13:27 +0800638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800642
Jesse Barnes79e53942008-11-07 14:24:08 -0800643{
644 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800646 int err = target;
647
Daniel Vettera210b022012-11-26 17:22:08 +0100648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800649 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800653 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100654 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
Akshay Joshi0206e352011-08-16 15:34:10 -0400665 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800666
Zhao Yakui42158662009-11-20 11:24:18 +0800667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800678 int this_err;
679
Shaohua Li21778322009-02-23 15:19:16 +0800680 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
Ma Lingd4906092009-03-18 20:13:27 +0800701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800705{
706 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800707 intel_clock_t clock;
708 int max_n;
709 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800715 int lvds_reg;
716
Eric Anholtc619eed2010-01-28 16:45:52 -0800717 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
Daniel Vetter1974cad2012-11-26 17:22:09 +0100721 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200734 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200736 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
Shaohua Li21778322009-02-23 15:19:16 +0800745 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800748 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000752
753 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800764 return found;
765}
Ma Lingd4906092009-03-18 20:13:27 +0800766
Zhenyu Wang2c072452009-06-05 15:38:42 +0800767static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800774
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700798{
Chris Wilson5eddb702010-09-11 13:48:45 +0100799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700819}
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
Alan Coxaf447bd2012-07-25 13:49:18 +0100831 flag = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700888
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
Paulo Zanonia928d532012-05-04 17:18:15 -0300898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800918{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700919 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800920 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700921
Paulo Zanonia928d532012-05-04 17:18:15 -0300922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
Chris Wilson300387c2010-09-05 20:25:43 +0100927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700943 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
Keith Packardab7ad7f2010-10-03 00:33:06 -0700950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100965 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700966 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700972
Keith Packardab7ad7f2010-10-03 00:33:06 -0700973 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200974 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700975
Keith Packardab7ad7f2010-10-03 00:33:06 -0700976 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200979 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700980 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300981 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100982 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
Paulo Zanoni837ba002012-05-04 17:18:14 -0300985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
Keith Packardab7ad7f2010-10-03 00:33:06 -0700990 /* Wait for the display line to settle */
991 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300992 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700993 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -0300994 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
Daniel Vetter284637d2012-07-09 09:51:57 +0200997 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700998 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800999}
1000
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
Damien Lespiauc36346e2012-12-13 16:09:03 +00001013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
Jesse Barnesb24e7172011-01-04 15:09:30 -08001046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
Jesse Barnes040484a2011-01-03 12:14:26 -08001069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
Chris Wilson92b27b02012-05-20 18:10:50 +01001071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001074{
Jesse Barnes040484a2011-01-03 12:14:26 -08001075 u32 val;
1076 bool cur_state;
1077
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
Chris Wilson92b27b02012-05-20 18:10:50 +01001083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001085 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001086
Chris Wilson92b27b02012-05-20 18:10:50 +01001087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
Chris Wilson92b27b02012-05-20 18:10:50 +01001098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001110 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001111}
Chris Wilson92b27b02012-05-20 18:10:50 +01001112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
Jesse Barnes040484a2011-01-03 12:14:26 -08001114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001123
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001127 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001169 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001170 return;
1171
Jesse Barnes040484a2011-01-03 12:14:26 -08001172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
Jesse Barnesea0760c2011-01-04 15:09:32 -08001188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001194 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001214 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001215}
1216
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001219{
1220 int reg;
1221 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001222 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001225
Daniel Vetter8e636782012-01-22 01:36:48 +01001226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
Paulo Zanoni69310162013-01-29 16:35:19 -02001230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001241 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001242}
1243
Chris Wilson931872f2012-01-16 23:01:13 +00001244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246{
1247 int reg;
1248 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001249 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001257}
1258
Chris Wilson931872f2012-01-16 23:01:13 +00001259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
Jesse Barnesb24e7172011-01-04 15:09:30 -08001262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
Jesse Barnes19ec1352011-02-02 12:28:02 -08001269 /* Planes are fixed to pipes on ILK+ */
Jesse Barnesda6ecc52013-03-08 10:46:00 -08001270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
Adam Jackson28c057942011-10-07 14:38:42 -04001271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001276 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001277 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001278
Jesse Barnesb24e7172011-01-04 15:09:30 -08001279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001288 }
1289}
1290
Jesse Barnes19332d72013-03-28 09:55:38 -07001291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
Jesse Barnes92f25842011-01-04 15:09:34 -08001310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
Jesse Barnes92f25842011-01-04 15:09:34 -08001320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001339}
1340
Keith Packard4e634382011-08-06 10:39:45 -07001341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
Keith Packard1519b992011-08-06 10:35:34 -07001359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001362 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001367 return false;
1368 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
Jesse Barnes291906f2011-02-02 12:28:03 -08001406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001407 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001408{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001409 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001412 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001413
Daniel Vetter75c5da22012-09-10 21:58:29 +02001414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001416 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001422 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001425 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001426
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001428 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001429 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001437
Keith Packardf0575e92011-07-25 22:12:43 -07001438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001445 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001446 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001452 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001453
Paulo Zanonie2debe92013-02-18 19:00:27 -03001454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001457}
1458
Jesse Barnesb24e7172011-01-04 15:09:30 -08001459/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
Thomas Richter7434a252012-07-18 19:22:30 +02001469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001528/* SBI access */
1529static void
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001532{
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001533 u32 tmp;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001534
Daniel Vetter09153002012-12-12 14:06:44 +01001535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001536
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
Daniel Vetter09153002012-12-12 14:06:44 +01001540 return;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001541 }
1542
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001551
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
Daniel Vetter09153002012-12-12 14:06:44 +01001555 return;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001556 }
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001557}
1558
1559static u32
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001562{
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001563 u32 value = 0;
Daniel Vetter09153002012-12-12 14:06:44 +01001564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001565
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
Daniel Vetter09153002012-12-12 14:06:44 +01001569 return 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001570 }
1571
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001579
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
Daniel Vetter09153002012-12-12 14:06:44 +01001583 return 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001584 }
1585
Daniel Vetter09153002012-12-12 14:06:44 +01001586 return I915_READ(SBI_DATA);
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001587}
1588
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001589/**
Paulo Zanonib6b4e182012-10-31 18:12:38 -02001590 * ironlake_enable_pch_pll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
Paulo Zanonib6b4e182012-10-31 18:12:38 -02001597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001598{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Chris Wilson48da64a2012-05-13 20:16:12 +01001600 struct intel_pch_pll *pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001601 int reg;
1602 u32 val;
1603
Chris Wilson48da64a2012-05-13 20:16:12 +01001604 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001605 BUG_ON(dev_priv->info->gen < 5);
Chris Wilson48da64a2012-05-13 20:16:12 +01001606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001620 if (pll->active++ && pll->on) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001621 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001633
1634 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001635}
1636
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001638{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001641 int reg;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001642 u32 val;
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001643
Jesse Barnes92f25842011-01-04 15:09:34 -08001644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001646 if (pll == NULL)
1647 return;
1648
Chris Wilson48da64a2012-05-13 20:16:12 +01001649 if (WARN_ON(pll->refcount == 0))
1650 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001651
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
1655
Chris Wilson48da64a2012-05-13 20:16:12 +01001656 if (WARN_ON(pll->active == 0)) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001657 assert_pch_pll_disabled(dev_priv, pll, NULL);
Chris Wilson48da64a2012-05-13 20:16:12 +01001658 return;
1659 }
1660
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001661 if (--pll->active) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001662 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001663 return;
1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
Jesse Barnes92f25842011-01-04 15:09:34 -08001667
1668 /* Make sure transcoder isn't still depending on us */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001670
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001671 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001677
1678 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001679}
1680
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001683{
Daniel Vetter23670b322012-11-01 09:15:30 +01001684 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetter23670b322012-11-01 09:15:30 +01001686 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
Chris Wilson92b27b02012-05-20 18:10:50 +01001692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
Daniel Vetter23670b322012-11-01 09:15:30 +01001700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001707 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001708
Jesse Barnes040484a2011-01-03 12:14:26 -08001709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001711 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001720 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001729 else
1730 val |= TRANS_PROGRESSIVE;
1731
Jesse Barnes040484a2011-01-03 12:14:26 -08001732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001738 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001739{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001740 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001745 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001748
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001754 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001756
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001759 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001760 else
1761 val |= TRANS_PROGRESSIVE;
1762
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001766}
1767
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001770{
Daniel Vetter23670b322012-11-01 09:15:30 +01001771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
Jesse Barnes291906f2011-02-02 12:28:03 -08001778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
Jesse Barnes040484a2011-01-03 12:14:26 -08001781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Daniel Vetter23670b322012-11-01 09:15:30 +01001788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001796}
1797
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001799{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001800 u32 val;
1801
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001802 val = I915_READ(_TRANSACONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001803 val &= ~TRANS_ENABLE;
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001804 I915_WRITE(_TRANSACONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001805 /* wait for PCH transcoder off, transcoder state */
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001812 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001813}
1814
1815/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001816 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001831{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001834 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001835 int reg;
1836 u32 val;
1837
Paulo Zanoni681e5812012-12-06 11:12:38 -02001838 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
Jesse Barnesb24e7172011-01-04 15:09:30 -08001843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001859
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001860 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001861 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001870 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001894 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001900 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001901 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
Keith Packardd74362c2011-07-28 14:47:14 -07001909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001914 enum plane plane)
1915{
Damien Lespiau14f86142012-10-29 15:24:49 +00001916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
Keith Packardd74362c2011-07-28 14:47:14 -07001920}
1921
Jesse Barnesb24e7172011-01-04 15:09:30 -08001922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001945 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
Jesse Barnesb24e7172011-01-04 15:09:30 -08001949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
Chris Wilson693db182013-03-05 14:52:39 +00001973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
Chris Wilson127bd2a2010-07-23 23:32:05 +01001982int
Chris Wilson48b956c2010-09-14 12:50:34 +01001983intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001984 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001985 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001986{
Chris Wilsonce453d82011-02-21 14:43:56 +00001987 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001988 u32 alignment;
1989 int ret;
1990
Chris Wilson05394f32010-11-08 19:18:58 +00001991 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001992 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001995 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
Chris Wilson693db182013-03-05 14:52:39 +00002012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
Chris Wilsonce453d82011-02-21 14:43:56 +00002020 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002022 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002023 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
Chris Wilson06d98132012-04-17 15:31:24 +01002030 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002031 if (ret)
2032 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002033
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002034 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002035
Chris Wilsonce453d82011-02-21 14:43:56 +00002036 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002037 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002038
2039err_unpin:
2040 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002041err_interruptible:
2042 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002043 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002044}
2045
Chris Wilson1690e1e2011-12-14 13:57:08 +01002046void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047{
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050}
2051
Daniel Vetterc2c75132012-07-05 12:17:30 +02002052/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002054unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002058{
Chris Wilsonbc752862013-02-21 20:04:31 +00002059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002061
Chris Wilsonbc752862013-02-21 20:04:31 +00002062 tile_rows = *y / 8;
2063 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002064
Chris Wilsonbc752862013-02-21 20:04:31 +00002065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002077}
2078
Jesse Barnes17638cd2011-06-24 12:19:23 -07002079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002086 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002087 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002088 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002089 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002090 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002103
Chris Wilson5eddb702010-09-11 13:48:45 +01002104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002110 dspcntr |= DISPPLANE_8BPP;
2111 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002115 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002134 break;
2135 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002136 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002137 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002138
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002139 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002140 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
Chris Wilson5eddb702010-09-11 13:48:45 +01002146 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002147
Daniel Vettere506a0c2012-07-05 12:17:29 +02002148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002149
Daniel Vetterc2c75132012-07-05 12:17:30 +02002150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002157 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002158 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002163 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002167 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002168 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02002169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002170 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002171
Jesse Barnes17638cd2011-06-24 12:19:23 -07002172 return 0;
2173}
2174
2175static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177{
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002184 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002191 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002207 dspcntr |= DISPPLANE_8BPP;
2208 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002211 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002227 break;
2228 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002229 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
Daniel Vettere506a0c2012-07-05 12:17:29 +02002242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002243 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002247 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002248
Daniel Vettere506a0c2012-07-05 12:17:29 +02002249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002260 POSTING_READ(reg);
2261
2262 return 0;
2263}
2264
2265/* Assume fb object is pinned & idle & fenced and just update base pointers */
2266static int
2267intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269{
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002272
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002275 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002276
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002277 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002278}
2279
Ville Syrjälä96a02912013-02-18 19:08:49 +02002280void intel_display_handle_reset(struct drm_device *dev)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316}
2317
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002318static int
Chris Wilson14667a42012-04-03 17:58:35 +01002319intel_finish_fb(struct drm_framebuffer *old_fb)
2320{
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
Chris Wilson14667a42012-04-03 17:58:35 +01002326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339}
2340
Ville Syrjälä198598d2012-10-31 17:50:24 +02002341static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342{
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366}
2367
Chris Wilson14667a42012-04-03 17:58:35 +01002368static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002369intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002370 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002371{
2372 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002373 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002375 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002376 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002377
2378 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002379 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002380 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002381 return 0;
2382 }
2383
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Eugeni Dodonov5826eca2012-05-09 15:37:12 -03002385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002387 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002388 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002389 }
2390
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002391 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002392 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002393 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002394 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002397 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002398 return ret;
2399 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002400
Daniel Vetter94352cf2012-07-05 22:51:56 +02002401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002402 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002404 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002405 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002406 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002407 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002408
Daniel Vetter94352cf2012-07-05 22:51:56 +02002409 old_fb = crtc->fb;
2410 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002411 crtc->x = x;
2412 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002413
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002417 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002418
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002419 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002420 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002421
Ville Syrjälä198598d2012-10-31 17:50:24 +02002422 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002423
2424 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002425}
2426
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002427static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428{
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002438 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002444 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002466}
2467
Daniel Vetter01a415f2012-10-27 15:58:40 +02002468static void ivb_modeset_global_resources(struct drm_device *dev)
2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489}
2490
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002491/* The FDI link training functions for ILK/Ibexpeak. */
2492static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493{
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002498 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002499 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002500
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
Adam Jacksone1a44742010-06-25 15:32:14 -04002505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002513 udelay(150);
2514
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002515 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002523
Chris Wilson5eddb702010-09-11 13:48:45 +01002524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002531 udelay(150);
2532
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002533 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002537
Chris Wilson5eddb702010-09-11 13:48:45 +01002538 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002539 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002540 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002546 break;
2547 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002548 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002549 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002550 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002551
2552 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002557 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002558
Chris Wilson5eddb702010-09-11 13:48:45 +01002559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002566 udelay(150);
2567
Chris Wilson5eddb702010-09-11 13:48:45 +01002568 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002569 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002570 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002578 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002579 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002580 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002581
2582 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002583
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002584}
2585
Akshay Joshi0206e352011-08-16 15:34:10 -04002586static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591};
2592
2593/* The FDI link training functions for SNB/Cougarpoint. */
2594static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595{
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002600 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002601
Adam Jacksone1a44742010-06-25 15:32:14 -04002602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002611 udelay(150);
2612
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002613 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002624
Daniel Vetterd74cf322012-10-26 10:58:13 +02002625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
Chris Wilson5eddb702010-09-11 13:48:45 +01002628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002640 udelay(150);
2641
Akshay Joshi0206e352011-08-16 15:34:10 -04002642 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002650 udelay(500);
2651
Sean Paulfa37d392012-03-02 12:53:39 -05002652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002662 }
Sean Paulfa37d392012-03-02 12:53:39 -05002663 if (retry < 5)
2664 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002665 }
2666 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002667 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002668
2669 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002679 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002680
Chris Wilson5eddb702010-09-11 13:48:45 +01002681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002693 udelay(150);
2694
Akshay Joshi0206e352011-08-16 15:34:10 -04002695 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002703 udelay(500);
2704
Sean Paulfa37d392012-03-02 12:53:39 -05002705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002715 }
Sean Paulfa37d392012-03-02 12:53:39 -05002716 if (retry < 5)
2717 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002718 }
2719 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002720 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723}
2724
Jesse Barnes357555c2011-04-28 15:09:55 -07002725/* Manual link training for Ivy Bridge A0 parts */
2726static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727{
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
Daniel Vetter01a415f2012-10-27 15:58:40 +02002745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
Jesse Barnes357555c2011-04-28 15:09:55 -07002748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002757 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
Daniel Vetterd74cf322012-10-26 10:58:13 +02002760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
Jesse Barnes357555c2011-04-28 15:09:55 -07002763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002768 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
Akshay Joshi0206e352011-08-16 15:34:10 -04002774 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
Akshay Joshi0206e352011-08-16 15:34:10 -04002816 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840}
2841
Daniel Vetter88cefb62012-08-12 19:27:14 +02002842static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002843{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002844 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002845 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002846 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002847 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002848
Jesse Barnesc64e3112010-09-10 11:27:03 -07002849
Jesse Barnes0e23b992010-09-10 11:10:00 -07002850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01002856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002866 udelay(200);
2867
Paulo Zanoni20749732012-11-23 15:30:38 -02002868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002873
Paulo Zanoni20749732012-11-23 15:30:38 -02002874 POSTING_READ(reg);
2875 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002876 }
2877}
2878
Daniel Vetter88cefb62012-08-12 19:27:14 +02002879static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880{
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906}
2907
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002908static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002934 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959}
2960
Chris Wilson5bb61642012-09-27 21:25:58 +01002961static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962{
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä10d83732013-01-29 18:13:34 +02002965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5bb61642012-09-27 21:25:58 +01002966 unsigned long flags;
2967 bool pending;
2968
Ville Syrjälä10d83732013-01-29 18:13:34 +02002969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
Chris Wilson5bb61642012-09-27 21:25:58 +01002971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978}
2979
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002980static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981{
Chris Wilson0f911282012-04-17 10:05:38 +01002982 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002983 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002984
2985 if (crtc->fb == NULL)
2986 return;
2987
Daniel Vetter2c10d572012-12-20 21:24:07 +01002988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
Chris Wilson5bb61642012-09-27 21:25:58 +01002990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
Chris Wilson0f911282012-04-17 10:05:38 +01002993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002996}
2997
Paulo Zanonifc316cb2012-10-25 10:37:43 -02002998static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999{
3000 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001}
3002
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003003/* Program iCLKIP clock to the desired frequency */
3004static void lpt_program_iclkip(struct drm_crtc *crtc)
3005{
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009 u32 temp;
3010
Daniel Vetter09153002012-12-12 14:06:44 +01003011 mutex_lock(&dev_priv->dpio_lock);
3012
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003013 /* It is necessary to ungate the pixclk gate prior to programming
3014 * the divisors, and gate it back when it is done.
3015 */
3016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3017
3018 /* Disable SSCCTL */
3019 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003020 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3021 SBI_SSCCTL_DISABLE,
3022 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003023
3024 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3025 if (crtc->mode.clock == 20000) {
3026 auxdiv = 1;
3027 divsel = 0x41;
3028 phaseinc = 0x20;
3029 } else {
3030 /* The iCLK virtual clock root frequency is in MHz,
3031 * but the crtc->mode.clock in in KHz. To get the divisors,
3032 * it is necessary to divide one by another, so we
3033 * convert the virtual clock precision to KHz here for higher
3034 * precision.
3035 */
3036 u32 iclk_virtual_root_freq = 172800 * 1000;
3037 u32 iclk_pi_range = 64;
3038 u32 desired_divisor, msb_divisor_value, pi_value;
3039
3040 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3041 msb_divisor_value = desired_divisor / iclk_pi_range;
3042 pi_value = desired_divisor % iclk_pi_range;
3043
3044 auxdiv = 0;
3045 divsel = msb_divisor_value - 2;
3046 phaseinc = pi_value;
3047 }
3048
3049 /* This should not happen with any sane values */
3050 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3051 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3053 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3054
3055 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3056 crtc->mode.clock,
3057 auxdiv,
3058 divsel,
3059 phasedir,
3060 phaseinc);
3061
3062 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003063 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003064 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3065 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3066 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3068 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3069 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003070 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003071
3072 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003073 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003074 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003076 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003077
3078 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003079 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003080 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003081 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003082
3083 /* Wait for initialization time */
3084 udelay(24);
3085
3086 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003087
3088 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003089}
3090
Jesse Barnesf67a5592011-01-05 10:31:48 -08003091/*
3092 * Enable PCH resources required for PCH ports:
3093 * - PCH PLLs
3094 * - FDI training & RX/TX
3095 * - update transcoder timings
3096 * - DP transcoding bits
3097 * - transcoder
3098 */
3099static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003100{
3101 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3104 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003105 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003106
Chris Wilsone7e164d2012-05-11 09:21:25 +01003107 assert_transcoder_disabled(dev_priv, pipe);
3108
Daniel Vettercd986ab2012-10-26 10:58:12 +02003109 /* Write the TU size bits before fdi link training, so that error
3110 * detection works. */
3111 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3112 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3113
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003114 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003115 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003116
Daniel Vetter572deb32012-10-27 18:46:14 +02003117 /* XXX: pch pll's can be enabled any time before we enable the PCH
3118 * transcoder, and we actually should do this to not upset any PCH
3119 * transcoder that already use the clock when we share it.
3120 *
3121 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3122 * unconditionally resets the pll - we need that to have the right LVDS
3123 * enable sequence. */
Paulo Zanonib6b4e182012-10-31 18:12:38 -02003124 ironlake_enable_pch_pll(intel_crtc);
Chris Wilson6f13b7b2012-05-13 09:54:09 +01003125
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003126 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003127 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003128
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003129 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003130 switch (pipe) {
3131 default:
3132 case 0:
3133 temp |= TRANSA_DPLL_ENABLE;
3134 sel = TRANSA_DPLLB_SEL;
3135 break;
3136 case 1:
3137 temp |= TRANSB_DPLL_ENABLE;
3138 sel = TRANSB_DPLLB_SEL;
3139 break;
3140 case 2:
3141 temp |= TRANSC_DPLL_ENABLE;
3142 sel = TRANSC_DPLLB_SEL;
3143 break;
Jesse Barnesd64311a2011-10-12 15:01:33 -07003144 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003145 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3146 temp |= sel;
3147 else
3148 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003149 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003150 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003151
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003152 /* set transcoder timing, panel must allow it */
3153 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01003154 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3155 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3156 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3157
3158 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3159 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3160 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003161 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003162
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003163 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003164
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003165 /* For PCH DP, enable TRANS_DP_CTL */
3166 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003167 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3168 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003169 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003170 reg = TRANS_DP_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003173 TRANS_DP_SYNC_MASK |
3174 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003175 temp |= (TRANS_DP_OUTPUT_ENABLE |
3176 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003177 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003178
3179 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003180 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003181 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003182 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003183
3184 switch (intel_trans_dp_port_sel(crtc)) {
3185 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003186 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003187 break;
3188 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003189 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003190 break;
3191 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003192 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003193 break;
3194 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003195 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003196 }
3197
Chris Wilson5eddb702010-09-11 13:48:45 +01003198 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003199 }
3200
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003201 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003202}
3203
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003204static void lpt_pch_enable(struct drm_crtc *crtc)
3205{
3206 struct drm_device *dev = crtc->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003209 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003210
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003211 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003212
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003213 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003214
Paulo Zanoni0540e482012-10-31 18:12:40 -02003215 /* Set transcoder timing. */
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003216 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3217 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3218 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003219
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003220 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003224
Paulo Zanoni937bb612012-10-31 18:12:47 -02003225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003226}
3227
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003228static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3229{
3230 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3231
3232 if (pll == NULL)
3233 return;
3234
3235 if (pll->refcount == 0) {
3236 WARN(1, "bad PCH PLL refcount\n");
3237 return;
3238 }
3239
3240 --pll->refcount;
3241 intel_crtc->pch_pll = NULL;
3242}
3243
3244static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3245{
3246 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3247 struct intel_pch_pll *pll;
3248 int i;
3249
3250 pll = intel_crtc->pch_pll;
3251 if (pll) {
3252 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3253 intel_crtc->base.base.id, pll->pll_reg);
3254 goto prepare;
3255 }
3256
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003257 if (HAS_PCH_IBX(dev_priv->dev)) {
3258 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3259 i = intel_crtc->pipe;
3260 pll = &dev_priv->pch_plls[i];
3261
3262 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3263 intel_crtc->base.base.id, pll->pll_reg);
3264
3265 goto found;
3266 }
3267
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003268 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3269 pll = &dev_priv->pch_plls[i];
3270
3271 /* Only want to check enabled timings first */
3272 if (pll->refcount == 0)
3273 continue;
3274
3275 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3276 fp == I915_READ(pll->fp0_reg)) {
3277 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3278 intel_crtc->base.base.id,
3279 pll->pll_reg, pll->refcount, pll->active);
3280
3281 goto found;
3282 }
3283 }
3284
3285 /* Ok no matching timings, maybe there's a free one? */
3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3288 if (pll->refcount == 0) {
3289 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3290 intel_crtc->base.base.id, pll->pll_reg);
3291 goto found;
3292 }
3293 }
3294
3295 return NULL;
3296
3297found:
3298 intel_crtc->pch_pll = pll;
3299 pll->refcount++;
3300 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3301prepare: /* separate function? */
3302 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003303
Chris Wilsone04c7352012-05-02 20:43:56 +01003304 /* Wait for the clocks to stabilize before rewriting the regs */
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003306 POSTING_READ(pll->pll_reg);
3307 udelay(150);
Chris Wilsone04c7352012-05-02 20:43:56 +01003308
3309 I915_WRITE(pll->fp0_reg, fp);
3310 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003311 pll->on = false;
3312 return pll;
3313}
3314
Jesse Barnesd4270e52011-10-11 10:43:02 -07003315void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3316{
3317 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003318 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003319 u32 temp;
3320
3321 temp = I915_READ(dslreg);
3322 udelay(500);
3323 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003324 if (wait_for(I915_READ(dslreg) != temp, 5))
3325 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3326 }
3327}
3328
Jesse Barnesf67a5592011-01-05 10:31:48 -08003329static void ironlake_crtc_enable(struct drm_crtc *crtc)
3330{
3331 struct drm_device *dev = crtc->dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003334 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003335 int pipe = intel_crtc->pipe;
3336 int plane = intel_crtc->plane;
3337 u32 temp;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003338
Daniel Vetter08a48462012-07-02 11:43:47 +02003339 WARN_ON(!crtc->enabled);
3340
Jesse Barnesf67a5592011-01-05 10:31:48 -08003341 if (intel_crtc->active)
3342 return;
3343
3344 intel_crtc->active = true;
3345 intel_update_watermarks(dev);
3346
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3348 temp = I915_READ(PCH_LVDS);
3349 if ((temp & LVDS_PORT_EN) == 0)
3350 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3351 }
3352
Jesse Barnesf67a5592011-01-05 10:31:48 -08003353
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003354 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003355 /* Note: FDI PLL enabling _must_ be done before we enable the
3356 * cpu pipes, hence this is separate from all the other fdi/pch
3357 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003358 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003359 } else {
3360 assert_fdi_tx_disabled(dev_priv, pipe);
3361 assert_fdi_rx_disabled(dev_priv, pipe);
3362 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003363
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 if (encoder->pre_enable)
3366 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003367
3368 /* Enable panel fitting for LVDS */
3369 if (dev_priv->pch_pf_size &&
Jani Nikula547dc042012-11-02 11:24:03 +02003370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnesf67a5592011-01-05 10:31:48 -08003372 /* Force use of hard-coded filter coefficients
3373 * as some pre-programmed values are broken,
3374 * e.g. x201.
3375 */
Paulo Zanoni13888d72012-11-20 13:27:41 -02003376 if (IS_IVYBRIDGE(dev))
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378 PF_PIPE_SEL_IVB(pipe));
3379 else
3380 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003381 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3382 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003383 }
3384
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003391 intel_enable_pipe(dev_priv, pipe,
3392 intel_crtc->config.has_pch_encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003393 intel_enable_plane(dev_priv, plane, pipe);
3394
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003395 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003396 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003397
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003398 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003399 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003400 mutex_unlock(&dev->struct_mutex);
3401
Chris Wilson6b383a72010-09-13 13:54:26 +01003402 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003403
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003406
3407 if (HAS_PCH_CPT(dev))
3408 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003409
3410 /*
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3416 * happening.
3417 */
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003419}
3420
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003421static void haswell_crtc_enable(struct drm_crtc *crtc)
3422{
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003429
3430 WARN_ON(!crtc->enabled);
3431
3432 if (intel_crtc->active)
3433 return;
3434
3435 intel_crtc->active = true;
3436 intel_update_watermarks(dev);
3437
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003438 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02003439 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003440
3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 if (encoder->pre_enable)
3443 encoder->pre_enable(encoder);
3444
Paulo Zanoni1f544382012-10-24 11:32:00 -02003445 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003446
Paulo Zanoni1f544382012-10-24 11:32:00 -02003447 /* Enable panel fitting for eDP */
Jani Nikula547dc042012-11-02 11:24:03 +02003448 if (dev_priv->pch_pf_size &&
3449 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003450 /* Force use of hard-coded filter coefficients
3451 * as some pre-programmed values are broken,
3452 * e.g. x201.
3453 */
Paulo Zanoni54075a72012-11-20 13:27:42 -02003454 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3455 PF_PIPE_SEL_IVB(pipe));
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003456 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3457 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3458 }
3459
3460 /*
3461 * On ILK+ LUT must be loaded before the pipe is running but with
3462 * clocks enabled
3463 */
3464 intel_crtc_load_lut(crtc);
3465
Paulo Zanoni1f544382012-10-24 11:32:00 -02003466 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00003467 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003468
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003469 intel_enable_pipe(dev_priv, pipe,
3470 intel_crtc->config.has_pch_encoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003471 intel_enable_plane(dev_priv, plane, pipe);
3472
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003473 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003474 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003475
3476 mutex_lock(&dev->struct_mutex);
3477 intel_update_fbc(dev);
3478 mutex_unlock(&dev->struct_mutex);
3479
3480 intel_crtc_update_cursor(crtc, true);
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->enable(encoder);
3484
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003485 /*
3486 * There seems to be a race in PCH platform hw (at least on some
3487 * outputs) where an enabled pipe still completes any pageflip right
3488 * away (as if the pipe is off) instead of waiting for vblank. As soon
3489 * as the first vblank happend, everything works as expected. Hence just
3490 * wait for one vblank before returning to avoid strange things
3491 * happening.
3492 */
3493 intel_wait_for_vblank(dev, intel_crtc->pipe);
3494}
3495
Jesse Barnes6be4a602010-09-10 10:26:01 -07003496static void ironlake_crtc_disable(struct drm_crtc *crtc)
3497{
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003501 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003502 int pipe = intel_crtc->pipe;
3503 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003504 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003505
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003506
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003507 if (!intel_crtc->active)
3508 return;
3509
Daniel Vetterea9d7582012-07-10 10:42:52 +02003510 for_each_encoder_on_crtc(dev, crtc, encoder)
3511 encoder->disable(encoder);
3512
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003513 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003514 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003515 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003516
Jesse Barnesb24e7172011-01-04 15:09:30 -08003517 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003518
Chris Wilson973d04f2011-07-08 12:22:37 +01003519 if (dev_priv->cfb_plane == plane)
3520 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003521
Jesse Barnesb24e7172011-01-04 15:09:30 -08003522 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003523
Jesse Barnes6be4a602010-09-10 10:26:01 -07003524 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003525 I915_WRITE(PF_CTL(pipe), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003527
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->post_disable)
3530 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003531
Chris Wilson5eddb702010-09-11 13:48:45 +01003532 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003533
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003534 ironlake_disable_pch_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003535
3536 if (HAS_PCH_CPT(dev)) {
3537 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003538 reg = TRANS_DP_CTL(pipe);
3539 temp = I915_READ(reg);
3540 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003541 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003542 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003543
3544 /* disable DPLL_SEL */
3545 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003546 switch (pipe) {
3547 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003548 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003549 break;
3550 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003551 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003552 break;
3553 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003554 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003555 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003556 break;
3557 default:
3558 BUG(); /* wtf */
3559 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003560 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003561 }
3562
3563 /* disable PCH DPLL */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003564 intel_disable_pch_pll(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003565
Daniel Vetter88cefb62012-08-12 19:27:14 +02003566 ironlake_fdi_pll_disable(intel_crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +01003567
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003568 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003569 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003570
3571 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003572 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003573 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003574}
3575
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003576static void haswell_crtc_disable(struct drm_crtc *crtc)
3577{
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581 struct intel_encoder *encoder;
3582 int pipe = intel_crtc->pipe;
3583 int plane = intel_crtc->plane;
Paulo Zanoniad80a812012-10-24 16:06:19 -02003584 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoni83616632012-10-23 18:29:54 -02003585 bool is_pch_port;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003586
3587 if (!intel_crtc->active)
3588 return;
3589
Paulo Zanoni83616632012-10-23 18:29:54 -02003590 is_pch_port = haswell_crtc_driving_pch(crtc);
3591
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003592 for_each_encoder_on_crtc(dev, crtc, encoder)
3593 encoder->disable(encoder);
3594
3595 intel_crtc_wait_for_pending_flips(crtc);
3596 drm_vblank_off(dev, pipe);
3597 intel_crtc_update_cursor(crtc, false);
3598
3599 intel_disable_plane(dev_priv, plane, pipe);
3600
3601 if (dev_priv->cfb_plane == plane)
3602 intel_disable_fbc(dev);
3603
3604 intel_disable_pipe(dev_priv, pipe);
3605
Paulo Zanoniad80a812012-10-24 16:06:19 -02003606 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003607
3608 /* Disable PF */
3609 I915_WRITE(PF_CTL(pipe), 0);
3610 I915_WRITE(PF_WIN_SZ(pipe), 0);
3611
Paulo Zanoni1f544382012-10-24 11:32:00 -02003612 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003613
3614 for_each_encoder_on_crtc(dev, crtc, encoder)
3615 if (encoder->post_disable)
3616 encoder->post_disable(encoder);
3617
Paulo Zanoni83616632012-10-23 18:29:54 -02003618 if (is_pch_port) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003619 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003620 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003621 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003622
3623 intel_crtc->active = false;
3624 intel_update_watermarks(dev);
3625
3626 mutex_lock(&dev->struct_mutex);
3627 intel_update_fbc(dev);
3628 mutex_unlock(&dev->struct_mutex);
3629}
3630
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003631static void ironlake_crtc_off(struct drm_crtc *crtc)
3632{
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 intel_put_pch_pll(intel_crtc);
3635}
3636
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003637static void haswell_crtc_off(struct drm_crtc *crtc)
3638{
Paulo Zanonia5c961d2012-10-24 15:59:34 -02003639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3640
3641 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3642 * start using it. */
Daniel Vetter1a240d42012-11-29 22:18:51 +01003643 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02003644
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003645 intel_ddi_put_crtc_pll(crtc);
3646}
3647
Daniel Vetter02e792f2009-09-15 22:57:34 +02003648static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3649{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003650 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003651 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003652 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003653
Chris Wilson23f09ce2010-08-12 13:53:37 +01003654 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003655 dev_priv->mm.interruptible = false;
3656 (void) intel_overlay_switch_off(intel_crtc->overlay);
3657 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003658 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003659 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003660
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003661 /* Let userspace switch the overlay on again. In most cases userspace
3662 * has to recompute where to put it anyway.
3663 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003664}
3665
Egbert Eich61bc95c2013-03-04 09:24:38 -05003666/**
3667 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3668 * cursor plane briefly if not already running after enabling the display
3669 * plane.
3670 * This workaround avoids occasional blank screens when self refresh is
3671 * enabled.
3672 */
3673static void
3674g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3675{
3676 u32 cntl = I915_READ(CURCNTR(pipe));
3677
3678 if ((cntl & CURSOR_MODE) == 0) {
3679 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3680
3681 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3682 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3683 intel_wait_for_vblank(dev_priv->dev, pipe);
3684 I915_WRITE(CURCNTR(pipe), cntl);
3685 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3686 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3687 }
3688}
3689
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003690static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003691{
3692 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003695 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003696 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003697 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003698
Daniel Vetter08a48462012-07-02 11:43:47 +02003699 WARN_ON(!crtc->enabled);
3700
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003705 intel_update_watermarks(dev);
3706
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003707 intel_enable_pll(dev_priv, pipe);
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02003708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
Jesse Barnes040484a2011-01-03 12:14:26 -08003713 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003714 intel_enable_plane(dev_priv, plane, pipe);
Egbert Eich61bc95c2013-03-04 09:24:38 -05003715 if (IS_G4X(dev))
3716 g4x_fixup_plane(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003717
3718 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003719 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003720
3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003723 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003724
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003727}
3728
3729static void i9xx_crtc_disable(struct drm_crtc *crtc)
3730{
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003734 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003735 int pipe = intel_crtc->pipe;
3736 int plane = intel_crtc->plane;
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003737 u32 pctl;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003738
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003739
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003740 if (!intel_crtc->active)
3741 return;
3742
Daniel Vetterea9d7582012-07-10 10:42:52 +02003743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003746 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003749 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003750 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003751
Chris Wilson973d04f2011-07-08 12:22:37 +01003752 if (dev_priv->cfb_plane == plane)
3753 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003754
Jesse Barnesb24e7172011-01-04 15:09:30 -08003755 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003756 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003757
3758 /* Disable pannel fitter if it is on this pipe. */
3759 pctl = I915_READ(PFIT_CONTROL);
3760 if ((pctl & PFIT_ENABLE) &&
3761 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3762 I915_WRITE(PFIT_CONTROL, 0);
3763
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003764 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003765
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003766 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003767 intel_update_fbc(dev);
3768 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003769}
3770
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003771static void i9xx_crtc_off(struct drm_crtc *crtc)
3772{
3773}
3774
Daniel Vetter976f8a22012-07-08 22:34:21 +02003775static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3776 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003777{
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_master_private *master_priv;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003782
3783 if (!dev->primary->master)
3784 return;
3785
3786 master_priv = dev->primary->master->driver_priv;
3787 if (!master_priv->sarea_priv)
3788 return;
3789
Jesse Barnes79e53942008-11-07 14:24:08 -08003790 switch (pipe) {
3791 case 0:
3792 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 case 1:
3796 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3797 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3798 break;
3799 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003800 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003801 break;
3802 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003803}
3804
Daniel Vetter976f8a22012-07-08 22:34:21 +02003805/**
3806 * Sets the power management mode of the pipe and plane.
3807 */
3808void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01003809{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003810 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003811 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003812 struct intel_encoder *intel_encoder;
3813 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003814
Daniel Vetter976f8a22012-07-08 22:34:21 +02003815 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3816 enable |= intel_encoder->connectors_active;
3817
3818 if (enable)
3819 dev_priv->display.crtc_enable(crtc);
3820 else
3821 dev_priv->display.crtc_disable(crtc);
3822
3823 intel_crtc_update_sarea(crtc, enable);
3824}
3825
Daniel Vetter976f8a22012-07-08 22:34:21 +02003826static void intel_crtc_disable(struct drm_crtc *crtc)
3827{
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_connector *connector;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08003831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003832
3833 /* crtc should still be enabled when we disable it. */
3834 WARN_ON(!crtc->enabled);
3835
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08003836 intel_crtc->eld_vld = false;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003837 dev_priv->display.crtc_disable(crtc);
3838 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003839 dev_priv->display.off(crtc);
3840
Chris Wilson931872f2012-01-16 23:01:13 +00003841 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3842 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003843
3844 if (crtc->fb) {
3845 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003846 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003847 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003848 crtc->fb = NULL;
3849 }
3850
3851 /* Update computed state. */
3852 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3853 if (!connector->encoder || !connector->encoder->crtc)
3854 continue;
3855
3856 if (connector->encoder->crtc != crtc)
3857 continue;
3858
3859 connector->dpms = DRM_MODE_DPMS_OFF;
3860 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003861 }
3862}
3863
Daniel Vettera261b242012-07-26 19:21:47 +02003864void intel_modeset_disable(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003865{
Daniel Vettera261b242012-07-26 19:21:47 +02003866 struct drm_crtc *crtc;
3867
3868 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3869 if (crtc->enabled)
3870 intel_crtc_disable(crtc);
3871 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003872}
3873
Chris Wilsonea5b2132010-08-04 13:50:23 +01003874void intel_encoder_destroy(struct drm_encoder *encoder)
3875{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003876 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003877
Chris Wilsonea5b2132010-08-04 13:50:23 +01003878 drm_encoder_cleanup(encoder);
3879 kfree(intel_encoder);
3880}
3881
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003882/* Simple dpms helper for encodres with just one connector, no cloning and only
3883 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3884 * state of the entire output pipe. */
3885void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3886{
3887 if (mode == DRM_MODE_DPMS_ON) {
3888 encoder->connectors_active = true;
3889
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003890 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003891 } else {
3892 encoder->connectors_active = false;
3893
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003894 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003895 }
3896}
3897
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003898/* Cross check the actual hw state with our own modeset state tracking (and it's
3899 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02003900static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003901{
3902 if (connector->get_hw_state(connector)) {
3903 struct intel_encoder *encoder = connector->encoder;
3904 struct drm_crtc *crtc;
3905 bool encoder_enabled;
3906 enum pipe pipe;
3907
3908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3909 connector->base.base.id,
3910 drm_get_connector_name(&connector->base));
3911
3912 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3913 "wrong connector dpms state\n");
3914 WARN(connector->base.encoder != &encoder->base,
3915 "active connector not linked to encoder\n");
3916 WARN(!encoder->connectors_active,
3917 "encoder->connectors_active not set\n");
3918
3919 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3920 WARN(!encoder_enabled, "encoder not enabled\n");
3921 if (WARN_ON(!encoder->base.crtc))
3922 return;
3923
3924 crtc = encoder->base.crtc;
3925
3926 WARN(!crtc->enabled, "crtc not enabled\n");
3927 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3928 WARN(pipe != to_intel_crtc(crtc)->pipe,
3929 "encoder active on the wrong pipe\n");
3930 }
3931}
3932
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003933/* Even simpler default implementation, if there's really no special case to
3934 * consider. */
3935void intel_connector_dpms(struct drm_connector *connector, int mode)
3936{
3937 struct intel_encoder *encoder = intel_attached_encoder(connector);
3938
3939 /* All the simple cases only support two dpms states. */
3940 if (mode != DRM_MODE_DPMS_ON)
3941 mode = DRM_MODE_DPMS_OFF;
3942
3943 if (mode == connector->dpms)
3944 return;
3945
3946 connector->dpms = mode;
3947
3948 /* Only need to change hw state when actually enabled */
3949 if (encoder->base.crtc)
3950 intel_encoder_dpms(encoder, mode);
3951 else
Daniel Vetter8af6cf82012-07-10 09:50:11 +02003952 WARN_ON(encoder->connectors_active != false);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003953
Daniel Vetterb9805142012-08-31 17:37:33 +02003954 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003955}
3956
Daniel Vetterf0947c32012-07-02 13:10:34 +02003957/* Simple connector->get_hw_state implementation for encoders that support only
3958 * one connector and no cloning and hence the encoder state determines the state
3959 * of the connector. */
3960bool intel_connector_get_hw_state(struct intel_connector *connector)
3961{
Daniel Vetter24929352012-07-02 20:28:59 +02003962 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02003963 struct intel_encoder *encoder = connector->encoder;
3964
3965 return encoder->get_hw_state(encoder, &pipe);
3966}
3967
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01003968static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3969 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08003970{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003971 struct drm_device *dev = crtc->dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01003972 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01003973
Eric Anholtbad720f2009-10-22 16:11:14 -07003974 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003975 /* FDI link clock is fixed at 2.7G */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01003976 if (pipe_config->requested_mode.clock * 3
3977 > IRONLAKE_FDI_FREQ * 4)
Jesse Barnes2377b742010-07-07 14:06:43 -07003978 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003979 }
Chris Wilson89749352010-09-12 18:25:19 +01003980
Daniel Vetterf9bef082012-04-15 19:53:19 +02003981 /* All interlaced capable intel hw wants timings in frames. Note though
3982 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3983 * timings, so we need to be careful not to clobber these.*/
Daniel Vetter7ae89232013-03-27 00:44:52 +01003984 if (!pipe_config->timings_set)
Daniel Vetterf9bef082012-04-15 19:53:19 +02003985 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01003986
Chris Wilson44f46b422012-06-21 13:19:59 +03003987 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3988 * with a hsync front porch of 0.
3989 */
3990 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3991 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3992 return false;
3993
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01003994 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3995 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3996 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3997 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3998 * for lvds. */
3999 pipe_config->pipe_bpp = 8*3;
4000 }
4001
Jesse Barnes79e53942008-11-07 14:24:08 -08004002 return true;
4003}
4004
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07004005static int valleyview_get_display_clock_speed(struct drm_device *dev)
4006{
4007 return 400000; /* FIXME */
4008}
4009
Jesse Barnese70236a2009-09-21 10:42:27 -07004010static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08004011{
Jesse Barnese70236a2009-09-21 10:42:27 -07004012 return 400000;
4013}
Jesse Barnes79e53942008-11-07 14:24:08 -08004014
Jesse Barnese70236a2009-09-21 10:42:27 -07004015static int i915_get_display_clock_speed(struct drm_device *dev)
4016{
4017 return 333000;
4018}
Jesse Barnes79e53942008-11-07 14:24:08 -08004019
Jesse Barnese70236a2009-09-21 10:42:27 -07004020static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4021{
4022 return 200000;
4023}
Jesse Barnes79e53942008-11-07 14:24:08 -08004024
Jesse Barnese70236a2009-09-21 10:42:27 -07004025static int i915gm_get_display_clock_speed(struct drm_device *dev)
4026{
4027 u16 gcfgc = 0;
4028
4029 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4030
4031 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08004032 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07004033 else {
4034 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4035 case GC_DISPLAY_CLOCK_333_MHZ:
4036 return 333000;
4037 default:
4038 case GC_DISPLAY_CLOCK_190_200_MHZ:
4039 return 190000;
4040 }
4041 }
4042}
Jesse Barnes79e53942008-11-07 14:24:08 -08004043
Jesse Barnese70236a2009-09-21 10:42:27 -07004044static int i865_get_display_clock_speed(struct drm_device *dev)
4045{
4046 return 266000;
4047}
4048
4049static int i855_get_display_clock_speed(struct drm_device *dev)
4050{
4051 u16 hpllcc = 0;
4052 /* Assume that the hardware is in the high speed state. This
4053 * should be the default.
4054 */
4055 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4056 case GC_CLOCK_133_200:
4057 case GC_CLOCK_100_200:
4058 return 200000;
4059 case GC_CLOCK_166_250:
4060 return 250000;
4061 case GC_CLOCK_100_133:
4062 return 133000;
4063 }
4064
4065 /* Shouldn't happen */
4066 return 0;
4067}
4068
4069static int i830_get_display_clock_speed(struct drm_device *dev)
4070{
4071 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004072}
4073
Zhenyu Wang2c072452009-06-05 15:38:42 +08004074static void
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004075intel_reduce_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004076{
4077 while (*num > 0xffffff || *den > 0xffffff) {
4078 *num >>= 1;
4079 *den >>= 1;
4080 }
4081}
4082
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004083void
4084intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4085 int pixel_clock, int link_clock,
4086 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004087{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004088 m_n->tu = 64;
Chris Wilson22ed1112010-12-04 01:01:29 +00004089 m_n->gmch_m = bits_per_pixel * pixel_clock;
4090 m_n->gmch_n = link_clock * nlanes * 8;
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004091 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
Chris Wilson22ed1112010-12-04 01:01:29 +00004092 m_n->link_m = pixel_clock;
4093 m_n->link_n = link_clock;
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004094 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004095}
4096
Chris Wilsona7615032011-01-12 17:04:08 +00004097static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4098{
Keith Packard72bbe582011-09-26 16:09:45 -07004099 if (i915_panel_use_ssc >= 0)
4100 return i915_panel_use_ssc != 0;
4101 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004102 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004103}
4104
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004105static int vlv_get_refclk(struct drm_crtc *crtc)
4106{
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 int refclk = 27000; /* for DP & HDMI */
4110
4111 return 100000; /* only one validated so far */
4112
4113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4114 refclk = 96000;
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4116 if (intel_panel_use_ssc(dev_priv))
4117 refclk = 100000;
4118 else
4119 refclk = 96000;
4120 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4121 refclk = 100000;
4122 }
4123
4124 return refclk;
4125}
4126
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004127static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 int refclk;
4132
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004133 if (IS_VALLEYVIEW(dev)) {
4134 refclk = vlv_get_refclk(crtc);
4135 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004136 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4137 refclk = dev_priv->lvds_ssc_freq * 1000;
4138 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4139 refclk / 1000);
4140 } else if (!IS_GEN2(dev)) {
4141 refclk = 96000;
4142 } else {
4143 refclk = 48000;
4144 }
4145
4146 return refclk;
4147}
4148
4149static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4150 intel_clock_t *clock)
4151{
4152 /* SDVO TV has fixed PLL values depend on its clock range,
4153 this mirrors vbios setting. */
4154 if (adjusted_mode->clock >= 100000
4155 && adjusted_mode->clock < 140500) {
4156 clock->p1 = 2;
4157 clock->p2 = 10;
4158 clock->n = 3;
4159 clock->m1 = 16;
4160 clock->m2 = 8;
4161 } else if (adjusted_mode->clock >= 140500
4162 && adjusted_mode->clock <= 200000) {
4163 clock->p1 = 1;
4164 clock->p2 = 10;
4165 clock->n = 6;
4166 clock->m1 = 12;
4167 clock->m2 = 8;
4168 }
4169}
4170
Jesse Barnesa7516a02011-12-15 12:30:37 -08004171static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4172 intel_clock_t *clock,
4173 intel_clock_t *reduced_clock)
4174{
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int pipe = intel_crtc->pipe;
4179 u32 fp, fp2 = 0;
4180
4181 if (IS_PINEVIEW(dev)) {
4182 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4183 if (reduced_clock)
4184 fp2 = (1 << reduced_clock->n) << 16 |
4185 reduced_clock->m1 << 8 | reduced_clock->m2;
4186 } else {
4187 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4188 if (reduced_clock)
4189 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4190 reduced_clock->m2;
4191 }
4192
4193 I915_WRITE(FP0(pipe), fp);
4194
4195 intel_crtc->lowfreq_avail = false;
4196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197 reduced_clock && i915_powersave) {
4198 I915_WRITE(FP1(pipe), fp2);
4199 intel_crtc->lowfreq_avail = true;
4200 } else {
4201 I915_WRITE(FP1(pipe), fp);
4202 }
4203}
4204
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004205static void intel_dp_set_m_n(struct intel_crtc *crtc)
4206{
4207 if (crtc->config.has_pch_encoder)
4208 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4209 else
4210 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4211}
4212
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004213static void vlv_update_pll(struct drm_crtc *crtc,
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004214 intel_clock_t *clock, intel_clock_t *reduced_clock,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304215 int num_connectors)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004216{
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4221 u32 dpll, mdiv, pdiv;
4222 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304223 bool is_sdvo;
4224 u32 temp;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004225
Daniel Vetter09153002012-12-12 14:06:44 +01004226 mutex_lock(&dev_priv->dpio_lock);
4227
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304228 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4229 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4230
4231 dpll = DPLL_VGA_MODE_DIS;
4232 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4233 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4234 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4235
4236 I915_WRITE(DPLL(pipe), dpll);
4237 POSTING_READ(DPLL(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004238
4239 bestn = clock->n;
4240 bestm1 = clock->m1;
4241 bestm2 = clock->m2;
4242 bestp1 = clock->p1;
4243 bestp2 = clock->p2;
4244
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304245 /*
4246 * In Valleyview PLL and program lane counter registers are exposed
4247 * through DPIO interface
4248 */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004249 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4250 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4251 mdiv |= ((bestn << DPIO_N_SHIFT));
4252 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4253 mdiv |= (1 << DPIO_K_SHIFT);
4254 mdiv |= DPIO_ENABLE_CALIBRATION;
4255 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4256
4257 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4258
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304259 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004260 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304261 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4262 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004263 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4264
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304265 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004266
4267 dpll |= DPLL_VCO_ENABLE;
4268 I915_WRITE(DPLL(pipe), dpll);
4269 POSTING_READ(DPLL(pipe));
4270 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4271 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4272
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304273 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004274
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004275 if (intel_crtc->config.has_dp_encoder)
4276 intel_dp_set_m_n(intel_crtc);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304277
4278 I915_WRITE(DPLL(pipe), dpll);
4279
4280 /* Wait for the clocks to stabilize. */
4281 POSTING_READ(DPLL(pipe));
4282 udelay(150);
4283
4284 temp = 0;
4285 if (is_sdvo) {
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004286 temp = 0;
4287 if (intel_crtc->config.pixel_multiplier > 1) {
4288 temp = (intel_crtc->config.pixel_multiplier - 1)
4289 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4290 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004291 }
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304292 I915_WRITE(DPLL_MD(pipe), temp);
4293 POSTING_READ(DPLL_MD(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004294
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304295 /* Now program lane control registers */
4296 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4297 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4298 {
4299 temp = 0x1000C4;
4300 if(pipe == 1)
4301 temp |= (1 << 21);
4302 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4303 }
4304 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4305 {
4306 temp = 0x1000C4;
4307 if(pipe == 1)
4308 temp |= (1 << 21);
4309 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4310 }
Daniel Vetter09153002012-12-12 14:06:44 +01004311
4312 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004313}
4314
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004315static void i9xx_update_pll(struct drm_crtc *crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004316 intel_clock_t *clock, intel_clock_t *reduced_clock,
4317 int num_connectors)
4318{
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterdafd2262012-11-26 17:22:07 +01004322 struct intel_encoder *encoder;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004323 int pipe = intel_crtc->pipe;
4324 u32 dpll;
4325 bool is_sdvo;
4326
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304327 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4328
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004329 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4330 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4331
4332 dpll = DPLL_VGA_MODE_DIS;
4333
4334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4335 dpll |= DPLLB_MODE_LVDS;
4336 else
4337 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004338
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004339 if (is_sdvo) {
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004340 if ((intel_crtc->config.pixel_multiplier > 1) &&
4341 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4342 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4343 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004344 }
4345 dpll |= DPLL_DVO_HIGH_SPEED;
4346 }
4347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4348 dpll |= DPLL_DVO_HIGH_SPEED;
4349
4350 /* compute bitmask from p1 value */
4351 if (IS_PINEVIEW(dev))
4352 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4353 else {
4354 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4355 if (IS_G4X(dev) && reduced_clock)
4356 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4357 }
4358 switch (clock->p2) {
4359 case 5:
4360 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4361 break;
4362 case 7:
4363 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4364 break;
4365 case 10:
4366 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4367 break;
4368 case 14:
4369 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4370 break;
4371 }
4372 if (INTEL_INFO(dev)->gen >= 4)
4373 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4374
4375 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4376 dpll |= PLL_REF_INPUT_TVCLKINBC;
4377 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4378 /* XXX: just matching BIOS for now */
4379 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4380 dpll |= 3;
4381 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4382 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4383 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4384 else
4385 dpll |= PLL_REF_INPUT_DREFCLK;
4386
4387 dpll |= DPLL_VCO_ENABLE;
4388 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4389 POSTING_READ(DPLL(pipe));
4390 udelay(150);
4391
Daniel Vetterdafd2262012-11-26 17:22:07 +01004392 for_each_encoder_on_crtc(dev, crtc, encoder)
4393 if (encoder->pre_pll_enable)
4394 encoder->pre_pll_enable(encoder);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004395
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004396 if (intel_crtc->config.has_dp_encoder)
4397 intel_dp_set_m_n(intel_crtc);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004398
4399 I915_WRITE(DPLL(pipe), dpll);
4400
4401 /* Wait for the clocks to stabilize. */
4402 POSTING_READ(DPLL(pipe));
4403 udelay(150);
4404
4405 if (INTEL_INFO(dev)->gen >= 4) {
4406 u32 temp = 0;
4407 if (is_sdvo) {
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004408 temp = 0;
4409 if (intel_crtc->config.pixel_multiplier > 1) {
4410 temp = (intel_crtc->config.pixel_multiplier - 1)
4411 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4412 }
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004413 }
4414 I915_WRITE(DPLL_MD(pipe), temp);
4415 } else {
4416 /* The pixel multiplier can only be updated once the
4417 * DPLL is enabled and the clocks are stable.
4418 *
4419 * So write it again.
4420 */
4421 I915_WRITE(DPLL(pipe), dpll);
4422 }
4423}
4424
4425static void i8xx_update_pll(struct drm_crtc *crtc,
4426 struct drm_display_mode *adjusted_mode,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304427 intel_clock_t *clock, intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004428 int num_connectors)
4429{
4430 struct drm_device *dev = crtc->dev;
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterdafd2262012-11-26 17:22:07 +01004433 struct intel_encoder *encoder;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004434 int pipe = intel_crtc->pipe;
4435 u32 dpll;
4436
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304437 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4438
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004439 dpll = DPLL_VGA_MODE_DIS;
4440
4441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4442 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4443 } else {
4444 if (clock->p1 == 2)
4445 dpll |= PLL_P1_DIVIDE_BY_TWO;
4446 else
4447 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4448 if (clock->p2 == 4)
4449 dpll |= PLL_P2_DIVIDE_BY_4;
4450 }
4451
Daniel Vetter83f377a2013-02-22 00:53:05 +01004452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004453 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4454 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4455 else
4456 dpll |= PLL_REF_INPUT_DREFCLK;
4457
4458 dpll |= DPLL_VCO_ENABLE;
4459 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4460 POSTING_READ(DPLL(pipe));
4461 udelay(150);
4462
Daniel Vetterdafd2262012-11-26 17:22:07 +01004463 for_each_encoder_on_crtc(dev, crtc, encoder)
4464 if (encoder->pre_pll_enable)
4465 encoder->pre_pll_enable(encoder);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004466
Daniel Vetter5b5896e2012-09-11 12:37:55 +02004467 I915_WRITE(DPLL(pipe), dpll);
4468
4469 /* Wait for the clocks to stabilize. */
4470 POSTING_READ(DPLL(pipe));
4471 udelay(150);
4472
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004473 /* The pixel multiplier can only be updated once the
4474 * DPLL is enabled and the clocks are stable.
4475 *
4476 * So write it again.
4477 */
4478 I915_WRITE(DPLL(pipe), dpll);
4479}
4480
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004481static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4482 struct drm_display_mode *mode,
4483 struct drm_display_mode *adjusted_mode)
4484{
4485 struct drm_device *dev = intel_crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 enum pipe pipe = intel_crtc->pipe;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004488 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004489 uint32_t vsyncshift;
4490
4491 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4492 /* the chip adds 2 halflines automatically */
4493 adjusted_mode->crtc_vtotal -= 1;
4494 adjusted_mode->crtc_vblank_end -= 1;
4495 vsyncshift = adjusted_mode->crtc_hsync_start
4496 - adjusted_mode->crtc_htotal / 2;
4497 } else {
4498 vsyncshift = 0;
4499 }
4500
4501 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004502 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004503
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004504 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004505 (adjusted_mode->crtc_hdisplay - 1) |
4506 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004507 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004508 (adjusted_mode->crtc_hblank_start - 1) |
4509 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004510 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004511 (adjusted_mode->crtc_hsync_start - 1) |
4512 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4513
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004514 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004515 (adjusted_mode->crtc_vdisplay - 1) |
4516 ((adjusted_mode->crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004517 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004518 (adjusted_mode->crtc_vblank_start - 1) |
4519 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004520 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004521 (adjusted_mode->crtc_vsync_start - 1) |
4522 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4523
Paulo Zanonib5e508d2012-10-24 11:34:43 -02004524 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4525 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4526 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4527 * bits. */
4528 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4529 (pipe == PIPE_B || pipe == PIPE_C))
4530 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4531
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004532 /* pipesrc controls the size that is scaled from, which should
4533 * always be the user's requested size.
4534 */
4535 I915_WRITE(PIPESRC(pipe),
4536 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4537}
4538
Eric Anholtf564048e2011-03-30 13:01:02 -07004539static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07004540 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004541 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004542{
4543 struct drm_device *dev = crtc->dev;
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004546 struct drm_display_mode *adjusted_mode =
4547 &intel_crtc->config.adjusted_mode;
4548 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08004549 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004550 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004551 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004552 intel_clock_t clock, reduced_clock;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004553 u32 dspcntr, pipeconf;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004554 bool ok, has_reduced_clock = false, is_sdvo = false;
4555 bool is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004556 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004557 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004558 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004559
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004560 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004561 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004562 case INTEL_OUTPUT_LVDS:
4563 is_lvds = true;
4564 break;
4565 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004566 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004567 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004568 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004569 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004570 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004571 case INTEL_OUTPUT_TVOUT:
4572 is_tv = true;
4573 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004574 case INTEL_OUTPUT_DISPLAYPORT:
4575 is_dp = true;
4576 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004577 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004578
Eric Anholtc751ce42010-03-25 11:48:48 -07004579 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004580 }
4581
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004582 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004583
Ma Lingd4906092009-03-18 20:13:27 +08004584 /*
4585 * Returns a set of divisors for the desired target clock with the given
4586 * refclk, or FALSE. The returned values represent the clock equation:
4587 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4588 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004589 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004590 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4591 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004592 if (!ok) {
4593 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004594 return -EINVAL;
4595 }
4596
4597 /* Ensure that the cursor is valid for the new mode before changing... */
4598 intel_crtc_update_cursor(crtc, true);
4599
4600 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004601 /*
4602 * Ensure we match the reduced clock's P to the target clock.
4603 * If the clocks don't match, we can't switch the display clock
4604 * by using the FP0/FP1. In such case we will disable the LVDS
4605 * downclock feature.
4606 */
Eric Anholtf564048e2011-03-30 13:01:02 -07004607 has_reduced_clock = limit->find_pll(limit, crtc,
4608 dev_priv->lvds_downclock,
4609 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004610 &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004611 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004612 }
4613
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004614 if (is_sdvo && is_tv)
4615 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004616
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004617 if (IS_GEN2(dev))
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304618 i8xx_update_pll(crtc, adjusted_mode, &clock,
4619 has_reduced_clock ? &reduced_clock : NULL,
4620 num_connectors);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004621 else if (IS_VALLEYVIEW(dev))
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004622 vlv_update_pll(crtc, &clock,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304623 has_reduced_clock ? &reduced_clock : NULL,
4624 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004625 else
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004626 i9xx_update_pll(crtc, &clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004627 has_reduced_clock ? &reduced_clock : NULL,
4628 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004629
4630 /* setup pipeconf */
4631 pipeconf = I915_READ(PIPECONF(pipe));
4632
4633 /* Set up the display plane register */
4634 dspcntr = DISPPLANE_GAMMA_ENABLE;
4635
Jesse Barnesda6ecc52013-03-08 10:46:00 -08004636 if (!IS_VALLEYVIEW(dev)) {
4637 if (pipe == 0)
4638 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4639 else
4640 dspcntr |= DISPPLANE_SEL_PIPE_B;
4641 }
Eric Anholtf564048e2011-03-30 13:01:02 -07004642
4643 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4644 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4645 * core speed.
4646 *
4647 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4648 * pipe == 0 check?
4649 */
4650 if (mode->clock >
4651 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4652 pipeconf |= PIPECONF_DOUBLE_WIDE;
4653 else
4654 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4655 }
4656
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004657 /* default to 8bpc */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004658 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004659 if (is_dp) {
Daniel Vetter965e0c42013-03-27 00:44:57 +01004660 if (intel_crtc->config.dither) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004661 pipeconf |= PIPECONF_6BPC |
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004662 PIPECONF_DITHER_EN |
4663 PIPECONF_DITHER_TYPE_SP;
4664 }
4665 }
4666
Gajanan Bhat19c03922012-09-27 19:13:07 +05304667 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
Daniel Vetter965e0c42013-03-27 00:44:57 +01004668 if (intel_crtc->config.dither) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004669 pipeconf |= PIPECONF_6BPC |
Gajanan Bhat19c03922012-09-27 19:13:07 +05304670 PIPECONF_ENABLE |
4671 I965_PIPECONF_ACTIVE;
4672 }
4673 }
4674
Eric Anholtf564048e2011-03-30 13:01:02 -07004675 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4676 drm_mode_debug_printmodeline(mode);
4677
Jesse Barnesa7516a02011-12-15 12:30:37 -08004678 if (HAS_PIPE_CXSR(dev)) {
4679 if (intel_crtc->lowfreq_avail) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004680 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4681 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004682 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07004683 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4684 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4685 }
4686 }
4687
Keith Packard617cf882012-02-08 13:53:38 -08004688 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Daniel Vetterdbb02572012-01-28 14:49:23 +01004689 if (!IS_GEN2(dev) &&
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004690 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Eric Anholtf564048e2011-03-30 13:01:02 -07004691 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004692 else
Keith Packard617cf882012-02-08 13:53:38 -08004693 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004694
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004695 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Eric Anholtf564048e2011-03-30 13:01:02 -07004696
4697 /* pipesrc and dspsize control the size that is scaled from,
4698 * which should always be the user's requested size.
4699 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004700 I915_WRITE(DSPSIZE(plane),
4701 ((mode->vdisplay - 1) << 16) |
4702 (mode->hdisplay - 1));
4703 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004704
Eric Anholtf564048e2011-03-30 13:01:02 -07004705 I915_WRITE(PIPECONF(pipe), pipeconf);
4706 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004707 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004708
4709 intel_wait_for_vblank(dev, pipe);
4710
Eric Anholtf564048e2011-03-30 13:01:02 -07004711 I915_WRITE(DSPCNTR(plane), dspcntr);
4712 POSTING_READ(DSPCNTR(plane));
4713
Daniel Vetter94352cf2012-07-05 22:51:56 +02004714 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07004715
4716 intel_update_watermarks(dev);
4717
Eric Anholtf564048e2011-03-30 13:01:02 -07004718 return ret;
4719}
4720
Paulo Zanonidde86e22012-12-01 12:04:25 -02004721static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004722{
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004725 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004726 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004727 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004728 bool has_cpu_edp = false;
4729 bool has_pch_edp = false;
4730 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004731 bool has_ck505 = false;
4732 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004733
4734 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004735 list_for_each_entry(encoder, &mode_config->encoder_list,
4736 base.head) {
4737 switch (encoder->type) {
4738 case INTEL_OUTPUT_LVDS:
4739 has_panel = true;
4740 has_lvds = true;
4741 break;
4742 case INTEL_OUTPUT_EDP:
4743 has_panel = true;
4744 if (intel_encoder_is_pch_edp(&encoder->base))
4745 has_pch_edp = true;
4746 else
4747 has_cpu_edp = true;
4748 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004749 }
4750 }
4751
Keith Packard99eb6a02011-09-26 14:29:12 -07004752 if (HAS_PCH_IBX(dev)) {
4753 has_ck505 = dev_priv->display_clock_mode;
4754 can_ssc = has_ck505;
4755 } else {
4756 has_ck505 = false;
4757 can_ssc = true;
4758 }
4759
4760 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4761 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4762 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004763
4764 /* Ironlake: try to setup display ref clock before DPLL
4765 * enabling. This is only under driver's control after
4766 * PCH B stepping, previous chipset stepping should be
4767 * ignoring this setting.
4768 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004769 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004770
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004771 /* As we must carefully and slowly disable/enable each source in turn,
4772 * compute the final state we want first and check if we need to
4773 * make any changes at all.
4774 */
4775 final = val;
4776 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07004777 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004778 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07004779 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004780 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4781
4782 final &= ~DREF_SSC_SOURCE_MASK;
4783 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4784 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004785
Keith Packard199e5d72011-09-22 12:01:57 -07004786 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004787 final |= DREF_SSC_SOURCE_ENABLE;
4788
4789 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4790 final |= DREF_SSC1_ENABLE;
4791
4792 if (has_cpu_edp) {
4793 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4794 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4795 else
4796 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4797 } else
4798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4799 } else {
4800 final |= DREF_SSC_SOURCE_DISABLE;
4801 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4802 }
4803
4804 if (final == val)
4805 return;
4806
4807 /* Always enable nonspread source */
4808 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4809
4810 if (has_ck505)
4811 val |= DREF_NONSPREAD_CK505_ENABLE;
4812 else
4813 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4814
4815 if (has_panel) {
4816 val &= ~DREF_SSC_SOURCE_MASK;
4817 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004818
Keith Packard199e5d72011-09-22 12:01:57 -07004819 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07004820 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004821 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004822 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02004823 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004824 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004825
4826 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004827 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07004828 POSTING_READ(PCH_DREF_CONTROL);
4829 udelay(200);
4830
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004831 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004832
4833 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07004834 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07004835 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004836 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004837 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004838 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07004839 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004840 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004841 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004842 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004843
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004844 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07004845 POSTING_READ(PCH_DREF_CONTROL);
4846 udelay(200);
4847 } else {
4848 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4849
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004850 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07004851
4852 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004853 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004854
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004855 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07004856 POSTING_READ(PCH_DREF_CONTROL);
4857 udelay(200);
4858
4859 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004860 val &= ~DREF_SSC_SOURCE_MASK;
4861 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004862
4863 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004864 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004865
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004866 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004867 POSTING_READ(PCH_DREF_CONTROL);
4868 udelay(200);
4869 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004870
4871 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004872}
4873
Paulo Zanonidde86e22012-12-01 12:04:25 -02004874/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4875static void lpt_init_pch_refclk(struct drm_device *dev)
4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct drm_mode_config *mode_config = &dev->mode_config;
4879 struct intel_encoder *encoder;
4880 bool has_vga = false;
4881 bool is_sdv = false;
4882 u32 tmp;
4883
4884 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4885 switch (encoder->type) {
4886 case INTEL_OUTPUT_ANALOG:
4887 has_vga = true;
4888 break;
4889 }
4890 }
4891
4892 if (!has_vga)
4893 return;
4894
Daniel Vetterc00db242013-01-22 15:33:27 +01004895 mutex_lock(&dev_priv->dpio_lock);
4896
Paulo Zanonidde86e22012-12-01 12:04:25 -02004897 /* XXX: Rip out SDV support once Haswell ships for real. */
4898 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4899 is_sdv = true;
4900
4901 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4902 tmp &= ~SBI_SSCCTL_DISABLE;
4903 tmp |= SBI_SSCCTL_PATHALT;
4904 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4905
4906 udelay(24);
4907
4908 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4909 tmp &= ~SBI_SSCCTL_PATHALT;
4910 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4911
4912 if (!is_sdv) {
4913 tmp = I915_READ(SOUTH_CHICKEN2);
4914 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4915 I915_WRITE(SOUTH_CHICKEN2, tmp);
4916
4917 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4918 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4919 DRM_ERROR("FDI mPHY reset assert timeout\n");
4920
4921 tmp = I915_READ(SOUTH_CHICKEN2);
4922 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4923 I915_WRITE(SOUTH_CHICKEN2, tmp);
4924
4925 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4926 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4927 100))
4928 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4929 }
4930
4931 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4932 tmp &= ~(0xFF << 24);
4933 tmp |= (0x12 << 24);
4934 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4935
4936 if (!is_sdv) {
4937 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4938 tmp &= ~(0x3 << 6);
4939 tmp |= (1 << 6) | (1 << 0);
4940 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4941 }
4942
4943 if (is_sdv) {
4944 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4945 tmp |= 0x7FFF;
4946 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4947 }
4948
4949 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4950 tmp |= (1 << 11);
4951 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4952
4953 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4954 tmp |= (1 << 11);
4955 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4956
4957 if (is_sdv) {
4958 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4959 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4960 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4961
4962 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4963 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4964 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4965
4966 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4967 tmp |= (0x3F << 8);
4968 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4969
4970 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4971 tmp |= (0x3F << 8);
4972 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4973 }
4974
4975 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4976 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4977 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4978
4979 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4980 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4981 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4982
4983 if (!is_sdv) {
4984 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4985 tmp &= ~(7 << 13);
4986 tmp |= (5 << 13);
4987 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4988
4989 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4990 tmp &= ~(7 << 13);
4991 tmp |= (5 << 13);
4992 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4993 }
4994
4995 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4996 tmp &= ~0xFF;
4997 tmp |= 0x1C;
4998 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4999
5000 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5001 tmp &= ~0xFF;
5002 tmp |= 0x1C;
5003 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5004
5005 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5006 tmp &= ~(0xFF << 16);
5007 tmp |= (0x1C << 16);
5008 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5011 tmp &= ~(0xFF << 16);
5012 tmp |= (0x1C << 16);
5013 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5014
5015 if (!is_sdv) {
5016 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5017 tmp |= (1 << 27);
5018 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5019
5020 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5021 tmp |= (1 << 27);
5022 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5023
5024 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5025 tmp &= ~(0xF << 28);
5026 tmp |= (4 << 28);
5027 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5028
5029 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5030 tmp &= ~(0xF << 28);
5031 tmp |= (4 << 28);
5032 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5033 }
5034
5035 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5036 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5037 tmp |= SBI_DBUFF0_ENABLE;
5038 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01005039
5040 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005041}
5042
5043/*
5044 * Initialize reference clocks when the driver loads
5045 */
5046void intel_init_pch_refclk(struct drm_device *dev)
5047{
5048 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5049 ironlake_init_pch_refclk(dev);
5050 else if (HAS_PCH_LPT(dev))
5051 lpt_init_pch_refclk(dev);
5052}
5053
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005054static int ironlake_get_refclk(struct drm_crtc *crtc)
5055{
5056 struct drm_device *dev = crtc->dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005059 struct intel_encoder *edp_encoder = NULL;
5060 int num_connectors = 0;
5061 bool is_lvds = false;
5062
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005063 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005064 switch (encoder->type) {
5065 case INTEL_OUTPUT_LVDS:
5066 is_lvds = true;
5067 break;
5068 case INTEL_OUTPUT_EDP:
5069 edp_encoder = encoder;
5070 break;
5071 }
5072 num_connectors++;
5073 }
5074
5075 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5076 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5077 dev_priv->lvds_ssc_freq);
5078 return dev_priv->lvds_ssc_freq * 1000;
5079 }
5080
5081 return 120000;
5082}
5083
Paulo Zanonic8203562012-09-12 10:06:29 -03005084static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5085 struct drm_display_mode *adjusted_mode,
5086 bool dither)
5087{
5088 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5090 int pipe = intel_crtc->pipe;
5091 uint32_t val;
5092
5093 val = I915_READ(PIPECONF(pipe));
5094
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005095 val &= ~PIPECONF_BPC_MASK;
Daniel Vetter965e0c42013-03-27 00:44:57 +01005096 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03005097 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005098 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005099 break;
5100 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005101 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005102 break;
5103 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005104 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005105 break;
5106 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005107 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005108 break;
5109 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005110 /* Case prevented by intel_choose_pipe_bpp_dither. */
5111 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005112 }
5113
5114 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5115 if (dither)
5116 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5117
5118 val &= ~PIPECONF_INTERLACE_MASK;
5119 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5120 val |= PIPECONF_INTERLACED_ILK;
5121 else
5122 val |= PIPECONF_PROGRESSIVE;
5123
Daniel Vetter50f3b012013-03-27 00:44:56 +01005124 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005125 val |= PIPECONF_COLOR_RANGE_SELECT;
5126 else
5127 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5128
Paulo Zanonic8203562012-09-12 10:06:29 -03005129 I915_WRITE(PIPECONF(pipe), val);
5130 POSTING_READ(PIPECONF(pipe));
5131}
5132
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005133/*
5134 * Set up the pipe CSC unit.
5135 *
5136 * Currently only full range RGB to limited range RGB conversion
5137 * is supported, but eventually this should handle various
5138 * RGB<->YCbCr scenarios as well.
5139 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01005140static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005141{
5142 struct drm_device *dev = crtc->dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5145 int pipe = intel_crtc->pipe;
5146 uint16_t coeff = 0x7800; /* 1.0 */
5147
5148 /*
5149 * TODO: Check what kind of values actually come out of the pipe
5150 * with these coeff/postoff values and adjust to get the best
5151 * accuracy. Perhaps we even need to take the bpc value into
5152 * consideration.
5153 */
5154
Daniel Vetter50f3b012013-03-27 00:44:56 +01005155 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005156 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5157
5158 /*
5159 * GY/GU and RY/RU should be the other way around according
5160 * to BSpec, but reality doesn't agree. Just set them up in
5161 * a way that results in the correct picture.
5162 */
5163 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5164 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5165
5166 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5167 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5168
5169 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5170 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5171
5172 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5173 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5174 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5175
5176 if (INTEL_INFO(dev)->gen > 6) {
5177 uint16_t postoff = 0;
5178
Daniel Vetter50f3b012013-03-27 00:44:56 +01005179 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005180 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5181
5182 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5183 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5184 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5185
5186 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5187 } else {
5188 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5189
Daniel Vetter50f3b012013-03-27 00:44:56 +01005190 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005191 mode |= CSC_BLACK_SCREEN_OFFSET;
5192
5193 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5194 }
5195}
5196
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005197static void haswell_set_pipeconf(struct drm_crtc *crtc,
5198 struct drm_display_mode *adjusted_mode,
5199 bool dither)
5200{
5201 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005203 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005204 uint32_t val;
5205
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005206 val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005207
5208 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5209 if (dither)
5210 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5211
5212 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5213 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5214 val |= PIPECONF_INTERLACED_ILK;
5215 else
5216 val |= PIPECONF_PROGRESSIVE;
5217
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005218 I915_WRITE(PIPECONF(cpu_transcoder), val);
5219 POSTING_READ(PIPECONF(cpu_transcoder));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005220}
5221
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005222static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5223 struct drm_display_mode *adjusted_mode,
5224 intel_clock_t *clock,
5225 bool *has_reduced_clock,
5226 intel_clock_t *reduced_clock)
5227{
5228 struct drm_device *dev = crtc->dev;
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230 struct intel_encoder *intel_encoder;
5231 int refclk;
5232 const intel_limit_t *limit;
5233 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5234
5235 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5236 switch (intel_encoder->type) {
5237 case INTEL_OUTPUT_LVDS:
5238 is_lvds = true;
5239 break;
5240 case INTEL_OUTPUT_SDVO:
5241 case INTEL_OUTPUT_HDMI:
5242 is_sdvo = true;
5243 if (intel_encoder->needs_tv_clock)
5244 is_tv = true;
5245 break;
5246 case INTEL_OUTPUT_TVOUT:
5247 is_tv = true;
5248 break;
5249 }
5250 }
5251
5252 refclk = ironlake_get_refclk(crtc);
5253
5254 /*
5255 * Returns a set of divisors for the desired target clock with the given
5256 * refclk, or FALSE. The returned values represent the clock equation:
5257 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5258 */
5259 limit = intel_limit(crtc, refclk);
5260 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5261 clock);
5262 if (!ret)
5263 return false;
5264
5265 if (is_lvds && dev_priv->lvds_downclock_avail) {
5266 /*
5267 * Ensure we match the reduced clock's P to the target clock.
5268 * If the clocks don't match, we can't switch the display clock
5269 * by using the FP0/FP1. In such case we will disable the LVDS
5270 * downclock feature.
5271 */
5272 *has_reduced_clock = limit->find_pll(limit, crtc,
5273 dev_priv->lvds_downclock,
5274 refclk,
5275 clock,
5276 reduced_clock);
5277 }
5278
5279 if (is_sdvo && is_tv)
5280 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5281
5282 return true;
5283}
5284
Daniel Vetter01a415f2012-10-27 15:58:40 +02005285static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5286{
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288 uint32_t temp;
5289
5290 temp = I915_READ(SOUTH_CHICKEN1);
5291 if (temp & FDI_BC_BIFURCATION_SELECT)
5292 return;
5293
5294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5295 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5296
5297 temp |= FDI_BC_BIFURCATION_SELECT;
5298 DRM_DEBUG_KMS("enabling fdi C rx\n");
5299 I915_WRITE(SOUTH_CHICKEN1, temp);
5300 POSTING_READ(SOUTH_CHICKEN1);
5301}
5302
5303static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5304{
5305 struct drm_device *dev = intel_crtc->base.dev;
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct intel_crtc *pipe_B_crtc =
5308 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5309
5310 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5311 intel_crtc->pipe, intel_crtc->fdi_lanes);
5312 if (intel_crtc->fdi_lanes > 4) {
5313 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5314 intel_crtc->pipe, intel_crtc->fdi_lanes);
5315 /* Clamp lanes to avoid programming the hw with bogus values. */
5316 intel_crtc->fdi_lanes = 4;
5317
5318 return false;
5319 }
5320
Ben Widawsky7eb552a2013-03-13 14:05:41 -07005321 if (INTEL_INFO(dev)->num_pipes == 2)
Daniel Vetter01a415f2012-10-27 15:58:40 +02005322 return true;
5323
5324 switch (intel_crtc->pipe) {
5325 case PIPE_A:
5326 return true;
5327 case PIPE_B:
5328 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5329 intel_crtc->fdi_lanes > 2) {
5330 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5331 intel_crtc->pipe, intel_crtc->fdi_lanes);
5332 /* Clamp lanes to avoid programming the hw with bogus values. */
5333 intel_crtc->fdi_lanes = 2;
5334
5335 return false;
5336 }
5337
5338 if (intel_crtc->fdi_lanes > 2)
5339 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5340 else
5341 cpt_enable_fdi_bc_bifurcation(dev);
5342
5343 return true;
5344 case PIPE_C:
5345 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5346 if (intel_crtc->fdi_lanes > 2) {
5347 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5348 intel_crtc->pipe, intel_crtc->fdi_lanes);
5349 /* Clamp lanes to avoid programming the hw with bogus values. */
5350 intel_crtc->fdi_lanes = 2;
5351
5352 return false;
5353 }
5354 } else {
5355 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5356 return false;
5357 }
5358
5359 cpt_enable_fdi_bc_bifurcation(dev);
5360
5361 return true;
5362 default:
5363 BUG();
5364 }
5365}
5366
Paulo Zanonid4b19312012-11-29 11:29:32 -02005367int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5368{
5369 /*
5370 * Account for spread spectrum to avoid
5371 * oversubscribing the link. Max center spread
5372 * is 2.5%; use 5% for safety's sake.
5373 */
5374 u32 bps = target_clock * bpp * 21 / 20;
5375 return bps / (link_bw * 8) + 1;
5376}
5377
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005378void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5379 struct intel_link_m_n *m_n)
5380{
5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383 int pipe = crtc->pipe;
5384
5385 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5386 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5387 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5388 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5389}
5390
5391void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5392 struct intel_link_m_n *m_n)
5393{
5394 struct drm_device *dev = crtc->base.dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 int pipe = crtc->pipe;
5397 enum transcoder transcoder = crtc->cpu_transcoder;
5398
5399 if (INTEL_INFO(dev)->gen >= 5) {
5400 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5401 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5402 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5403 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5404 } else {
5405 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5406 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5407 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5408 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5409 }
5410}
5411
5412static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08005413{
5414 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08005415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005416 struct drm_display_mode *adjusted_mode =
5417 &intel_crtc->config.adjusted_mode;
5418 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005419 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
Daniel Vettere69d0bc2012-11-29 15:59:36 +01005420 struct intel_link_m_n m_n = {0};
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005421 int target_clock, lane, link_bw;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005422 bool is_dp = false, is_cpu_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005423
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005424 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5425 switch (intel_encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005426 case INTEL_OUTPUT_DISPLAYPORT:
5427 is_dp = true;
5428 break;
5429 case INTEL_OUTPUT_EDP:
Jesse Barnese3aef172012-04-10 11:58:03 -07005430 is_dp = true;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005431 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnese3aef172012-04-10 11:58:03 -07005432 is_cpu_edp = true;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005433 edp_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005434 break;
5435 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005436 }
5437
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005438 /* FDI is a binary signal running at ~2.7GHz, encoding
5439 * each output octet as 10 bits. The actual frequency
5440 * is stored as a divider into a 100MHz clock, and the
5441 * mode pixel clock is stored in units of 1KHz.
5442 * Hence the bw of each lane in terms of the mode signal
5443 * is:
5444 */
5445 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005446
Daniel Vetter94bf2ce2012-06-04 18:39:19 +02005447 /* [e]DP over FDI requires target mode clock instead of link clock. */
5448 if (edp_encoder)
5449 target_clock = intel_edp_target_clock(edp_encoder, mode);
5450 else if (is_dp)
5451 target_clock = mode->clock;
5452 else
5453 target_clock = adjusted_mode->clock;
5454
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005455 lane = ironlake_get_lanes_required(target_clock, link_bw,
5456 intel_crtc->config.pipe_bpp);
Eric Anholt8febb292011-03-30 13:01:07 -07005457
5458 intel_crtc->fdi_lanes = lane;
5459
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005460 if (intel_crtc->config.pixel_multiplier > 1)
5461 link_bw *= intel_crtc->config.pixel_multiplier;
Daniel Vetter965e0c42013-03-27 00:44:57 +01005462 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5463 link_bw, &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07005464
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005465 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005466}
5467
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005468static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005469 intel_clock_t *clock, u32 fp)
5470{
5471 struct drm_crtc *crtc = &intel_crtc->base;
5472 struct drm_device *dev = crtc->dev;
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 struct intel_encoder *intel_encoder;
5475 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005476 int factor, num_connectors = 0;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005477 bool is_lvds = false, is_sdvo = false, is_tv = false;
5478 bool is_dp = false, is_cpu_edp = false;
5479
5480 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5481 switch (intel_encoder->type) {
5482 case INTEL_OUTPUT_LVDS:
5483 is_lvds = true;
5484 break;
5485 case INTEL_OUTPUT_SDVO:
5486 case INTEL_OUTPUT_HDMI:
5487 is_sdvo = true;
5488 if (intel_encoder->needs_tv_clock)
5489 is_tv = true;
5490 break;
5491 case INTEL_OUTPUT_TVOUT:
5492 is_tv = true;
5493 break;
5494 case INTEL_OUTPUT_DISPLAYPORT:
5495 is_dp = true;
5496 break;
5497 case INTEL_OUTPUT_EDP:
5498 is_dp = true;
5499 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5500 is_cpu_edp = true;
5501 break;
5502 }
5503
5504 num_connectors++;
5505 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005506
Chris Wilsonc1858122010-12-03 21:35:48 +00005507 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005508 factor = 21;
5509 if (is_lvds) {
5510 if ((intel_panel_use_ssc(dev_priv) &&
5511 dev_priv->lvds_ssc_freq == 100) ||
Daniel Vetter1974cad2012-11-26 17:22:09 +01005512 intel_is_dual_link_lvds(dev))
Eric Anholt8febb292011-03-30 13:01:07 -07005513 factor = 25;
5514 } else if (is_sdvo && is_tv)
5515 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005516
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005517 if (clock->m < factor * clock->n)
Eric Anholt8febb292011-03-30 13:01:07 -07005518 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005519
Chris Wilson5eddb702010-09-11 13:48:45 +01005520 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005521
Eric Anholta07d6782011-03-30 13:01:08 -07005522 if (is_lvds)
5523 dpll |= DPLLB_MODE_LVDS;
5524 else
5525 dpll |= DPLLB_MODE_DAC_SERIAL;
5526 if (is_sdvo) {
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005527 if (intel_crtc->config.pixel_multiplier > 1) {
5528 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5529 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08005530 }
Eric Anholta07d6782011-03-30 13:01:08 -07005531 dpll |= DPLL_DVO_HIGH_SPEED;
5532 }
Jesse Barnese3aef172012-04-10 11:58:03 -07005533 if (is_dp && !is_cpu_edp)
Eric Anholta07d6782011-03-30 13:01:08 -07005534 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005535
Eric Anholta07d6782011-03-30 13:01:08 -07005536 /* compute bitmask from p1 value */
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005537 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005538 /* also FPA1 */
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005539 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005540
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005541 switch (clock->p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07005542 case 5:
5543 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5544 break;
5545 case 7:
5546 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5547 break;
5548 case 10:
5549 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5550 break;
5551 case 14:
5552 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5553 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005554 }
5555
5556 if (is_sdvo && is_tv)
5557 dpll |= PLL_REF_INPUT_TVCLKINBC;
5558 else if (is_tv)
5559 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005560 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08005561 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00005562 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005563 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08005564 else
5565 dpll |= PLL_REF_INPUT_DREFCLK;
5566
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005567 return dpll;
5568}
5569
Jesse Barnes79e53942008-11-07 14:24:08 -08005570static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08005571 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005572 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005573{
5574 struct drm_device *dev = crtc->dev;
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005577 struct drm_display_mode *adjusted_mode =
5578 &intel_crtc->config.adjusted_mode;
5579 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08005580 int pipe = intel_crtc->pipe;
5581 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005582 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005583 intel_clock_t clock, reduced_clock;
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005584 u32 dpll, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005585 bool ok, has_reduced_clock = false;
5586 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005587 struct intel_encoder *encoder;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005588 int ret;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005589 bool dither, fdi_config_ok;
Jesse Barnes79e53942008-11-07 14:24:08 -08005590
5591 for_each_encoder_on_crtc(dev, crtc, encoder) {
5592 switch (encoder->type) {
5593 case INTEL_OUTPUT_LVDS:
5594 is_lvds = true;
5595 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005596 case INTEL_OUTPUT_DISPLAYPORT:
5597 is_dp = true;
5598 break;
5599 case INTEL_OUTPUT_EDP:
5600 is_dp = true;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005601 if (!intel_encoder_is_pch_edp(&encoder->base))
Jesse Barnes79e53942008-11-07 14:24:08 -08005602 is_cpu_edp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005603 break;
5604 }
5605
5606 num_connectors++;
5607 }
5608
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005609 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5610 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5611
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005612 intel_crtc->cpu_transcoder = pipe;
5613
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005614 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5615 &has_reduced_clock, &reduced_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005616 if (!ok) {
5617 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5618 return -EINVAL;
5619 }
5620
5621 /* Ensure that the cursor is valid for the new mode before changing... */
5622 intel_crtc_update_cursor(crtc, true);
5623
Jesse Barnes79e53942008-11-07 14:24:08 -08005624 /* determine panel color depth */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01005625 dither = intel_crtc->config.dither;
Paulo Zanonic8203562012-09-12 10:06:29 -03005626 if (is_lvds && dev_priv->lvds_dither)
5627 dither = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005628
Jesse Barnes79e53942008-11-07 14:24:08 -08005629 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5630 if (has_reduced_clock)
5631 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5632 reduced_clock.m2;
5633
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005634 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005635
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07005636 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005637 drm_mode_debug_printmodeline(mode);
5638
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005639 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5640 if (!is_cpu_edp) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005641 struct intel_pch_pll *pll;
Chris Wilson5eddb702010-09-11 13:48:45 +01005642
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005643 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5644 if (pll == NULL) {
5645 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5646 pipe);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005647 return -EINVAL;
5648 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005649 } else
5650 intel_put_pch_pll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005651
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005652 if (intel_crtc->config.has_dp_encoder)
5653 intel_dp_set_m_n(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005654
Daniel Vetterdafd2262012-11-26 17:22:07 +01005655 for_each_encoder_on_crtc(dev, crtc, encoder)
5656 if (encoder->pre_pll_enable)
5657 encoder->pre_pll_enable(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08005658
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005659 if (intel_crtc->pch_pll) {
5660 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005661
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005662 /* Wait for the clocks to stabilize. */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005663 POSTING_READ(intel_crtc->pch_pll->pll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005664 udelay(150);
5665
Eric Anholt8febb292011-03-30 13:01:07 -07005666 /* The pixel multiplier can only be updated once the
5667 * DPLL is enabled and the clocks are stable.
5668 *
5669 * So write it again.
5670 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005671 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005672 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005673
Chris Wilson5eddb702010-09-11 13:48:45 +01005674 intel_crtc->lowfreq_avail = false;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005675 if (intel_crtc->pch_pll) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07005676 if (is_lvds && has_reduced_clock && i915_powersave) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005677 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005678 intel_crtc->lowfreq_avail = true;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005679 } else {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005680 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005681 }
5682 }
5683
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005684 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005685
Daniel Vetter01a415f2012-10-27 15:58:40 +02005686 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5687 * ironlake_check_fdi_lanes. */
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005688 intel_crtc->fdi_lanes = 0;
5689 if (intel_crtc->config.has_pch_encoder)
5690 ironlake_fdi_set_m_n(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01005691
Daniel Vetter01a415f2012-10-27 15:58:40 +02005692 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005693
Paulo Zanonic8203562012-09-12 10:06:29 -03005694 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
Jesse Barnes79e53942008-11-07 14:24:08 -08005695
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005696 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005697
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005698 /* Set up the display plane register */
5699 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005700 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005701
Daniel Vetter94352cf2012-07-05 22:51:56 +02005702 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005703
5704 intel_update_watermarks(dev);
5705
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03005706 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5707
Daniel Vetter01a415f2012-10-27 15:58:40 +02005708 return fdi_config_ok ? ret : -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005709}
5710
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005711static void haswell_modeset_global_resources(struct drm_device *dev)
5712{
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 bool enable = false;
5715 struct intel_crtc *crtc;
5716 struct intel_encoder *encoder;
5717
5718 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5719 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5720 enable = true;
5721 /* XXX: Should check for edp transcoder here, but thanks to init
5722 * sequence that's not yet available. Just in case desktop eDP
5723 * on PORT D is possible on haswell, too. */
5724 }
5725
5726 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5727 base.head) {
5728 if (encoder->type != INTEL_OUTPUT_EDP &&
5729 encoder->connectors_active)
5730 enable = true;
5731 }
5732
5733 /* Even the eDP panel fitter is outside the always-on well. */
5734 if (dev_priv->pch_pf_size)
5735 enable = true;
5736
5737 intel_set_power_well(dev, enable);
5738}
5739
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005740static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005741 int x, int y,
5742 struct drm_framebuffer *fb)
5743{
5744 struct drm_device *dev = crtc->dev;
5745 struct drm_i915_private *dev_priv = dev->dev_private;
5746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005747 struct drm_display_mode *adjusted_mode =
5748 &intel_crtc->config.adjusted_mode;
5749 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005750 int pipe = intel_crtc->pipe;
5751 int plane = intel_crtc->plane;
5752 int num_connectors = 0;
Daniel Vettered7ef432012-12-06 14:24:21 +01005753 bool is_dp = false, is_cpu_edp = false;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005754 struct intel_encoder *encoder;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005755 int ret;
5756 bool dither;
5757
5758 for_each_encoder_on_crtc(dev, crtc, encoder) {
5759 switch (encoder->type) {
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005760 case INTEL_OUTPUT_DISPLAYPORT:
5761 is_dp = true;
5762 break;
5763 case INTEL_OUTPUT_EDP:
5764 is_dp = true;
5765 if (!intel_encoder_is_pch_edp(&encoder->base))
5766 is_cpu_edp = true;
5767 break;
5768 }
5769
5770 num_connectors++;
5771 }
5772
Daniel Vetterbba21812013-03-22 10:53:40 +01005773 if (is_cpu_edp)
5774 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5775 else
5776 intel_crtc->cpu_transcoder = pipe;
5777
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005778 /* We are not sure yet this won't happen. */
5779 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5780 INTEL_PCH_TYPE(dev));
5781
5782 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5783 num_connectors, pipe_name(pipe));
5784
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005785 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
Paulo Zanoni1ce42922012-10-05 12:06:01 -03005786 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5787
5788 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5789
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005790 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5791 return -EINVAL;
5792
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005793 /* Ensure that the cursor is valid for the new mode before changing... */
5794 intel_crtc_update_cursor(crtc, true);
5795
5796 /* determine panel color depth */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01005797 dither = intel_crtc->config.dither;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005798
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005799 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5800 drm_mode_debug_printmodeline(mode);
5801
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005802 if (intel_crtc->config.has_dp_encoder)
5803 intel_dp_set_m_n(intel_crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005804
5805 intel_crtc->lowfreq_avail = false;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005806
5807 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5808
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005809 if (intel_crtc->config.has_pch_encoder)
5810 ironlake_fdi_set_m_n(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005811
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005812 haswell_set_pipeconf(crtc, adjusted_mode, dither);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005813
Daniel Vetter50f3b012013-03-27 00:44:56 +01005814 intel_set_pipe_csc(crtc);
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005815
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005816 /* Set up the display plane register */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005817 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005818 POSTING_READ(DSPCNTR(plane));
5819
5820 ret = intel_pipe_set_base(crtc, x, y, fb);
5821
5822 intel_update_watermarks(dev);
5823
5824 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5825
Jesse Barnes79e53942008-11-07 14:24:08 -08005826 return ret;
5827}
5828
Eric Anholtf564048e2011-03-30 13:01:02 -07005829static int intel_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005830 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005831 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07005832{
5833 struct drm_device *dev = crtc->dev;
5834 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9256aa12012-10-31 19:26:13 +01005835 struct drm_encoder_helper_funcs *encoder_funcs;
5836 struct intel_encoder *encoder;
Eric Anholt0b701d22011-03-30 13:01:03 -07005837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005838 struct drm_display_mode *adjusted_mode =
5839 &intel_crtc->config.adjusted_mode;
5840 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Eric Anholt0b701d22011-03-30 13:01:03 -07005841 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005842 int ret;
5843
Eric Anholt0b701d22011-03-30 13:01:03 -07005844 drm_vblank_pre_modeset(dev, pipe);
5845
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005846 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5847
Jesse Barnes79e53942008-11-07 14:24:08 -08005848 drm_vblank_post_modeset(dev, pipe);
5849
Daniel Vetter9256aa12012-10-31 19:26:13 +01005850 if (ret != 0)
5851 return ret;
5852
5853 for_each_encoder_on_crtc(dev, crtc, encoder) {
5854 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5855 encoder->base.base.id,
5856 drm_get_encoder_name(&encoder->base),
5857 mode->base.id, mode->name);
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005858 if (encoder->mode_set) {
5859 encoder->mode_set(encoder);
5860 } else {
5861 encoder_funcs = encoder->base.helper_private;
5862 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5863 }
Daniel Vetter9256aa12012-10-31 19:26:13 +01005864 }
5865
5866 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005867}
5868
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005869static bool intel_eld_uptodate(struct drm_connector *connector,
5870 int reg_eldv, uint32_t bits_eldv,
5871 int reg_elda, uint32_t bits_elda,
5872 int reg_edid)
5873{
5874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5875 uint8_t *eld = connector->eld;
5876 uint32_t i;
5877
5878 i = I915_READ(reg_eldv);
5879 i &= bits_eldv;
5880
5881 if (!eld[0])
5882 return !i;
5883
5884 if (!i)
5885 return false;
5886
5887 i = I915_READ(reg_elda);
5888 i &= ~bits_elda;
5889 I915_WRITE(reg_elda, i);
5890
5891 for (i = 0; i < eld[2]; i++)
5892 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5893 return false;
5894
5895 return true;
5896}
5897
Wu Fengguange0dac652011-09-05 14:25:34 +08005898static void g4x_write_eld(struct drm_connector *connector,
5899 struct drm_crtc *crtc)
5900{
5901 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5902 uint8_t *eld = connector->eld;
5903 uint32_t eldv;
5904 uint32_t len;
5905 uint32_t i;
5906
5907 i = I915_READ(G4X_AUD_VID_DID);
5908
5909 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5910 eldv = G4X_ELDV_DEVCL_DEVBLC;
5911 else
5912 eldv = G4X_ELDV_DEVCTG;
5913
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005914 if (intel_eld_uptodate(connector,
5915 G4X_AUD_CNTL_ST, eldv,
5916 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5917 G4X_HDMIW_HDMIEDID))
5918 return;
5919
Wu Fengguange0dac652011-09-05 14:25:34 +08005920 i = I915_READ(G4X_AUD_CNTL_ST);
5921 i &= ~(eldv | G4X_ELD_ADDR);
5922 len = (i >> 9) & 0x1f; /* ELD buffer size */
5923 I915_WRITE(G4X_AUD_CNTL_ST, i);
5924
5925 if (!eld[0])
5926 return;
5927
5928 len = min_t(uint8_t, eld[2], len);
5929 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5930 for (i = 0; i < len; i++)
5931 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5932
5933 i = I915_READ(G4X_AUD_CNTL_ST);
5934 i |= eldv;
5935 I915_WRITE(G4X_AUD_CNTL_ST, i);
5936}
5937
Wang Xingchao83358c852012-08-16 22:43:37 +08005938static void haswell_write_eld(struct drm_connector *connector,
5939 struct drm_crtc *crtc)
5940{
5941 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5942 uint8_t *eld = connector->eld;
5943 struct drm_device *dev = crtc->dev;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08005944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Wang Xingchao83358c852012-08-16 22:43:37 +08005945 uint32_t eldv;
5946 uint32_t i;
5947 int len;
5948 int pipe = to_intel_crtc(crtc)->pipe;
5949 int tmp;
5950
5951 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5952 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5953 int aud_config = HSW_AUD_CFG(pipe);
5954 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5955
5956
5957 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5958
5959 /* Audio output enable */
5960 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5961 tmp = I915_READ(aud_cntrl_st2);
5962 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5963 I915_WRITE(aud_cntrl_st2, tmp);
5964
5965 /* Wait for 1 vertical blank */
5966 intel_wait_for_vblank(dev, pipe);
5967
5968 /* Set ELD valid state */
5969 tmp = I915_READ(aud_cntrl_st2);
5970 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5971 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5972 I915_WRITE(aud_cntrl_st2, tmp);
5973 tmp = I915_READ(aud_cntrl_st2);
5974 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5975
5976 /* Enable HDMI mode */
5977 tmp = I915_READ(aud_config);
5978 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5979 /* clear N_programing_enable and N_value_index */
5980 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5981 I915_WRITE(aud_config, tmp);
5982
5983 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5984
5985 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08005986 intel_crtc->eld_vld = true;
Wang Xingchao83358c852012-08-16 22:43:37 +08005987
5988 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5989 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5990 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5991 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5992 } else
5993 I915_WRITE(aud_config, 0);
5994
5995 if (intel_eld_uptodate(connector,
5996 aud_cntrl_st2, eldv,
5997 aud_cntl_st, IBX_ELD_ADDRESS,
5998 hdmiw_hdmiedid))
5999 return;
6000
6001 i = I915_READ(aud_cntrl_st2);
6002 i &= ~eldv;
6003 I915_WRITE(aud_cntrl_st2, i);
6004
6005 if (!eld[0])
6006 return;
6007
6008 i = I915_READ(aud_cntl_st);
6009 i &= ~IBX_ELD_ADDRESS;
6010 I915_WRITE(aud_cntl_st, i);
6011 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6012 DRM_DEBUG_DRIVER("port num:%d\n", i);
6013
6014 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6015 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6016 for (i = 0; i < len; i++)
6017 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6018
6019 i = I915_READ(aud_cntrl_st2);
6020 i |= eldv;
6021 I915_WRITE(aud_cntrl_st2, i);
6022
6023}
6024
Wu Fengguange0dac652011-09-05 14:25:34 +08006025static void ironlake_write_eld(struct drm_connector *connector,
6026 struct drm_crtc *crtc)
6027{
6028 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6029 uint8_t *eld = connector->eld;
6030 uint32_t eldv;
6031 uint32_t i;
6032 int len;
6033 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006034 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08006035 int aud_cntl_st;
6036 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08006037 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08006038
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08006039 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006040 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6041 aud_config = IBX_AUD_CFG(pipe);
6042 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006043 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006044 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006045 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6046 aud_config = CPT_AUD_CFG(pipe);
6047 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006048 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006049 }
6050
Wang Xingchao9b138a82012-08-09 16:52:18 +08006051 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08006052
6053 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08006054 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08006055 if (!i) {
6056 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6057 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006058 eldv = IBX_ELD_VALIDB;
6059 eldv |= IBX_ELD_VALIDB << 4;
6060 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08006061 } else {
6062 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006063 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08006064 }
6065
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006066 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6067 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6068 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06006069 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6070 } else
6071 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006072
6073 if (intel_eld_uptodate(connector,
6074 aud_cntrl_st2, eldv,
6075 aud_cntl_st, IBX_ELD_ADDRESS,
6076 hdmiw_hdmiedid))
6077 return;
6078
Wu Fengguange0dac652011-09-05 14:25:34 +08006079 i = I915_READ(aud_cntrl_st2);
6080 i &= ~eldv;
6081 I915_WRITE(aud_cntrl_st2, i);
6082
6083 if (!eld[0])
6084 return;
6085
Wu Fengguange0dac652011-09-05 14:25:34 +08006086 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006087 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08006088 I915_WRITE(aud_cntl_st, i);
6089
6090 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6091 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6092 for (i = 0; i < len; i++)
6093 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6094
6095 i = I915_READ(aud_cntrl_st2);
6096 i |= eldv;
6097 I915_WRITE(aud_cntrl_st2, i);
6098}
6099
6100void intel_write_eld(struct drm_encoder *encoder,
6101 struct drm_display_mode *mode)
6102{
6103 struct drm_crtc *crtc = encoder->crtc;
6104 struct drm_connector *connector;
6105 struct drm_device *dev = encoder->dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 connector = drm_select_eld(encoder, mode);
6109 if (!connector)
6110 return;
6111
6112 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6113 connector->base.id,
6114 drm_get_connector_name(connector),
6115 connector->encoder->base.id,
6116 drm_get_encoder_name(connector->encoder));
6117
6118 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6119
6120 if (dev_priv->display.write_eld)
6121 dev_priv->display.write_eld(connector, crtc);
6122}
6123
Jesse Barnes79e53942008-11-07 14:24:08 -08006124/** Loads the palette/gamma unit for the CRTC with the prepared values */
6125void intel_crtc_load_lut(struct drm_crtc *crtc)
6126{
6127 struct drm_device *dev = crtc->dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006130 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006131 int i;
6132
6133 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00006134 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08006135 return;
6136
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006137 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07006138 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006139 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006140
Jesse Barnes79e53942008-11-07 14:24:08 -08006141 for (i = 0; i < 256; i++) {
6142 I915_WRITE(palreg + 4 * i,
6143 (intel_crtc->lut_r[i] << 16) |
6144 (intel_crtc->lut_g[i] << 8) |
6145 intel_crtc->lut_b[i]);
6146 }
6147}
6148
Chris Wilson560b85b2010-08-07 11:01:38 +01006149static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6150{
6151 struct drm_device *dev = crtc->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154 bool visible = base != 0;
6155 u32 cntl;
6156
6157 if (intel_crtc->cursor_visible == visible)
6158 return;
6159
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006160 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01006161 if (visible) {
6162 /* On these chipsets we can only modify the base whilst
6163 * the cursor is disabled.
6164 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006165 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006166
6167 cntl &= ~(CURSOR_FORMAT_MASK);
6168 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6169 cntl |= CURSOR_ENABLE |
6170 CURSOR_GAMMA_ENABLE |
6171 CURSOR_FORMAT_ARGB;
6172 } else
6173 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006174 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006175
6176 intel_crtc->cursor_visible = visible;
6177}
6178
6179static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6180{
6181 struct drm_device *dev = crtc->dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184 int pipe = intel_crtc->pipe;
6185 bool visible = base != 0;
6186
6187 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08006188 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01006189 if (base) {
6190 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6191 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6192 cntl |= pipe << 28; /* Connect to correct pipe */
6193 } else {
6194 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6195 cntl |= CURSOR_MODE_DISABLE;
6196 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006197 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006198
6199 intel_crtc->cursor_visible = visible;
6200 }
6201 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006202 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006203}
6204
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006205static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6206{
6207 struct drm_device *dev = crtc->dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 int pipe = intel_crtc->pipe;
6211 bool visible = base != 0;
6212
6213 if (intel_crtc->cursor_visible != visible) {
6214 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6215 if (base) {
6216 cntl &= ~CURSOR_MODE;
6217 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6218 } else {
6219 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6220 cntl |= CURSOR_MODE_DISABLE;
6221 }
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006222 if (IS_HASWELL(dev))
6223 cntl |= CURSOR_PIPE_CSC_ENABLE;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006224 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6225
6226 intel_crtc->cursor_visible = visible;
6227 }
6228 /* and commit changes on next vblank */
6229 I915_WRITE(CURBASE_IVB(pipe), base);
6230}
6231
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006232/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01006233static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6234 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006235{
6236 struct drm_device *dev = crtc->dev;
6237 struct drm_i915_private *dev_priv = dev->dev_private;
6238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6239 int pipe = intel_crtc->pipe;
6240 int x = intel_crtc->cursor_x;
6241 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01006242 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006243 bool visible;
6244
6245 pos = 0;
6246
Chris Wilson6b383a72010-09-13 13:54:26 +01006247 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006248 base = intel_crtc->cursor_addr;
6249 if (x > (int) crtc->fb->width)
6250 base = 0;
6251
6252 if (y > (int) crtc->fb->height)
6253 base = 0;
6254 } else
6255 base = 0;
6256
6257 if (x < 0) {
6258 if (x + intel_crtc->cursor_width < 0)
6259 base = 0;
6260
6261 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6262 x = -x;
6263 }
6264 pos |= x << CURSOR_X_SHIFT;
6265
6266 if (y < 0) {
6267 if (y + intel_crtc->cursor_height < 0)
6268 base = 0;
6269
6270 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6271 y = -y;
6272 }
6273 pos |= y << CURSOR_Y_SHIFT;
6274
6275 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006276 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006277 return;
6278
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03006279 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006280 I915_WRITE(CURPOS_IVB(pipe), pos);
6281 ivb_update_cursor(crtc, base);
6282 } else {
6283 I915_WRITE(CURPOS(pipe), pos);
6284 if (IS_845G(dev) || IS_I865G(dev))
6285 i845_update_cursor(crtc, base);
6286 else
6287 i9xx_update_cursor(crtc, base);
6288 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006289}
6290
Jesse Barnes79e53942008-11-07 14:24:08 -08006291static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006292 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006293 uint32_t handle,
6294 uint32_t width, uint32_t height)
6295{
6296 struct drm_device *dev = crtc->dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006299 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006300 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006301 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006302
Jesse Barnes79e53942008-11-07 14:24:08 -08006303 /* if we want to turn off the cursor ignore width and height */
6304 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006305 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006306 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006307 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006308 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006309 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006310 }
6311
6312 /* Currently we only support 64x64 cursors */
6313 if (width != 64 || height != 64) {
6314 DRM_ERROR("we currently only support 64x64 cursors\n");
6315 return -EINVAL;
6316 }
6317
Chris Wilson05394f32010-11-08 19:18:58 +00006318 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006319 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006320 return -ENOENT;
6321
Chris Wilson05394f32010-11-08 19:18:58 +00006322 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006323 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006324 ret = -ENOMEM;
6325 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006326 }
6327
Dave Airlie71acb5e2008-12-30 20:31:46 +10006328 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006329 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006330 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00006331 unsigned alignment;
6332
Chris Wilsond9e86c02010-11-10 16:40:20 +00006333 if (obj->tiling_mode) {
6334 DRM_ERROR("cursor cannot be tiled\n");
6335 ret = -EINVAL;
6336 goto fail_locked;
6337 }
6338
Chris Wilson693db182013-03-05 14:52:39 +00006339 /* Note that the w/a also requires 2 PTE of padding following
6340 * the bo. We currently fill all unused PTE with the shadow
6341 * page and so we should always have valid PTE following the
6342 * cursor preventing the VT-d warning.
6343 */
6344 alignment = 0;
6345 if (need_vtd_wa(dev))
6346 alignment = 64*1024;
6347
6348 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006349 if (ret) {
6350 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006351 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006352 }
6353
Chris Wilsond9e86c02010-11-10 16:40:20 +00006354 ret = i915_gem_object_put_fence(obj);
6355 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006356 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006357 goto fail_unpin;
6358 }
6359
Chris Wilson05394f32010-11-08 19:18:58 +00006360 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006361 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006362 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006363 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006364 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6365 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006366 if (ret) {
6367 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006368 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006369 }
Chris Wilson05394f32010-11-08 19:18:58 +00006370 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006371 }
6372
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006373 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006374 I915_WRITE(CURSIZE, (height << 12) | width);
6375
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006376 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006377 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006378 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006379 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006380 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6381 } else
6382 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006383 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006384 }
Jesse Barnes80824002009-09-10 15:28:06 -07006385
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006386 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006387
6388 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006389 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006390 intel_crtc->cursor_width = width;
6391 intel_crtc->cursor_height = height;
6392
Chris Wilson6b383a72010-09-13 13:54:26 +01006393 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006394
Jesse Barnes79e53942008-11-07 14:24:08 -08006395 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006396fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006397 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006398fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006399 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006400fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006401 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006402 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006403}
6404
6405static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6406{
Jesse Barnes79e53942008-11-07 14:24:08 -08006407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006408
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006409 intel_crtc->cursor_x = x;
6410 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006411
Chris Wilson6b383a72010-09-13 13:54:26 +01006412 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08006413
6414 return 0;
6415}
6416
6417/** Sets the color ramps on behalf of RandR */
6418void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6419 u16 blue, int regno)
6420{
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422
6423 intel_crtc->lut_r[regno] = red >> 8;
6424 intel_crtc->lut_g[regno] = green >> 8;
6425 intel_crtc->lut_b[regno] = blue >> 8;
6426}
6427
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006428void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6429 u16 *blue, int regno)
6430{
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432
6433 *red = intel_crtc->lut_r[regno] << 8;
6434 *green = intel_crtc->lut_g[regno] << 8;
6435 *blue = intel_crtc->lut_b[regno] << 8;
6436}
6437
Jesse Barnes79e53942008-11-07 14:24:08 -08006438static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006439 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006440{
James Simmons72034252010-08-03 01:33:19 +01006441 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006443
James Simmons72034252010-08-03 01:33:19 +01006444 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006445 intel_crtc->lut_r[i] = red[i] >> 8;
6446 intel_crtc->lut_g[i] = green[i] >> 8;
6447 intel_crtc->lut_b[i] = blue[i] >> 8;
6448 }
6449
6450 intel_crtc_load_lut(crtc);
6451}
6452
Jesse Barnes79e53942008-11-07 14:24:08 -08006453/* VESA 640x480x72Hz mode to set on the pipe */
6454static struct drm_display_mode load_detect_mode = {
6455 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6456 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6457};
6458
Chris Wilsond2dff872011-04-19 08:36:26 +01006459static struct drm_framebuffer *
6460intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006461 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01006462 struct drm_i915_gem_object *obj)
6463{
6464 struct intel_framebuffer *intel_fb;
6465 int ret;
6466
6467 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6468 if (!intel_fb) {
6469 drm_gem_object_unreference_unlocked(&obj->base);
6470 return ERR_PTR(-ENOMEM);
6471 }
6472
6473 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6474 if (ret) {
6475 drm_gem_object_unreference_unlocked(&obj->base);
6476 kfree(intel_fb);
6477 return ERR_PTR(ret);
6478 }
6479
6480 return &intel_fb->base;
6481}
6482
6483static u32
6484intel_framebuffer_pitch_for_width(int width, int bpp)
6485{
6486 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6487 return ALIGN(pitch, 64);
6488}
6489
6490static u32
6491intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6492{
6493 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6494 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6495}
6496
6497static struct drm_framebuffer *
6498intel_framebuffer_create_for_mode(struct drm_device *dev,
6499 struct drm_display_mode *mode,
6500 int depth, int bpp)
6501{
6502 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00006503 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01006504
6505 obj = i915_gem_alloc_object(dev,
6506 intel_framebuffer_size_for_mode(mode, bpp));
6507 if (obj == NULL)
6508 return ERR_PTR(-ENOMEM);
6509
6510 mode_cmd.width = mode->hdisplay;
6511 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006512 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6513 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00006514 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01006515
6516 return intel_framebuffer_create(dev, &mode_cmd, obj);
6517}
6518
6519static struct drm_framebuffer *
6520mode_fits_in_fbdev(struct drm_device *dev,
6521 struct drm_display_mode *mode)
6522{
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 struct drm_i915_gem_object *obj;
6525 struct drm_framebuffer *fb;
6526
6527 if (dev_priv->fbdev == NULL)
6528 return NULL;
6529
6530 obj = dev_priv->fbdev->ifb.obj;
6531 if (obj == NULL)
6532 return NULL;
6533
6534 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006535 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6536 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006537 return NULL;
6538
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006539 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006540 return NULL;
6541
6542 return fb;
6543}
6544
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006545bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01006546 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006547 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006548{
6549 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006550 struct intel_encoder *intel_encoder =
6551 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08006552 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006553 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006554 struct drm_crtc *crtc = NULL;
6555 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02006556 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006557 int i = -1;
6558
Chris Wilsond2dff872011-04-19 08:36:26 +01006559 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6560 connector->base.id, drm_get_connector_name(connector),
6561 encoder->base.id, drm_get_encoder_name(encoder));
6562
Jesse Barnes79e53942008-11-07 14:24:08 -08006563 /*
6564 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006565 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006566 * - if the connector already has an assigned crtc, use it (but make
6567 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006568 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006569 * - try to find the first unused crtc that can drive this connector,
6570 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006571 */
6572
6573 /* See if we already have a CRTC for this connector */
6574 if (encoder->crtc) {
6575 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006576
Daniel Vetter7b240562012-12-12 00:35:33 +01006577 mutex_lock(&crtc->mutex);
6578
Daniel Vetter24218aa2012-08-12 19:27:11 +02006579 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006580 old->load_detect_temp = false;
6581
6582 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006583 if (connector->dpms != DRM_MODE_DPMS_ON)
6584 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01006585
Chris Wilson71731882011-04-19 23:10:58 +01006586 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006587 }
6588
6589 /* Find an unused one (if possible) */
6590 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6591 i++;
6592 if (!(encoder->possible_crtcs & (1 << i)))
6593 continue;
6594 if (!possible_crtc->enabled) {
6595 crtc = possible_crtc;
6596 break;
6597 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006598 }
6599
6600 /*
6601 * If we didn't find an unused CRTC, don't use any.
6602 */
6603 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006604 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6605 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006606 }
6607
Daniel Vetter7b240562012-12-12 00:35:33 +01006608 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02006609 intel_encoder->new_crtc = to_intel_crtc(crtc);
6610 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006611
6612 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006613 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006614 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006615 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006616
Chris Wilson64927112011-04-20 07:25:26 +01006617 if (!mode)
6618 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006619
Chris Wilsond2dff872011-04-19 08:36:26 +01006620 /* We need a framebuffer large enough to accommodate all accesses
6621 * that the plane may generate whilst we perform load detection.
6622 * We can not rely on the fbcon either being present (we get called
6623 * during its initialisation to detect all boot displays, or it may
6624 * not even exist) or that it is large enough to satisfy the
6625 * requested mode.
6626 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02006627 fb = mode_fits_in_fbdev(dev, mode);
6628 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006629 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006630 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6631 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01006632 } else
6633 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006634 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006635 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter7b240562012-12-12 00:35:33 +01006636 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006637 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006638 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006639
Chris Wilsonc0c36b942012-12-19 16:08:43 +00006640 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006641 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006642 if (old->release_fb)
6643 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter7b240562012-12-12 00:35:33 +01006644 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006645 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006646 }
Chris Wilson71731882011-04-19 23:10:58 +01006647
Jesse Barnes79e53942008-11-07 14:24:08 -08006648 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006649 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01006650 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006651}
6652
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006653void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01006654 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006655{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006656 struct intel_encoder *intel_encoder =
6657 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01006658 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01006659 struct drm_crtc *crtc = encoder->crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -08006660
Chris Wilsond2dff872011-04-19 08:36:26 +01006661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6662 connector->base.id, drm_get_connector_name(connector),
6663 encoder->base.id, drm_get_encoder_name(encoder));
6664
Chris Wilson8261b192011-04-19 23:18:09 +01006665 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02006666 to_intel_connector(connector)->new_encoder = NULL;
6667 intel_encoder->new_crtc = NULL;
6668 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01006669
Daniel Vetter36206362012-12-10 20:42:17 +01006670 if (old->release_fb) {
6671 drm_framebuffer_unregister_private(old->release_fb);
6672 drm_framebuffer_unreference(old->release_fb);
6673 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006674
Daniel Vetter67c96402013-01-23 16:25:09 +00006675 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01006676 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006677 }
6678
Eric Anholtc751ce42010-03-25 11:48:48 -07006679 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006680 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6681 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01006682
6683 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08006684}
6685
6686/* Returns the clock of the currently programmed mode of the given pipe. */
6687static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6688{
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006692 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006693 u32 fp;
6694 intel_clock_t clock;
6695
6696 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006697 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006698 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006699 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006700
6701 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006702 if (IS_PINEVIEW(dev)) {
6703 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6704 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006705 } else {
6706 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6707 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6708 }
6709
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006710 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006711 if (IS_PINEVIEW(dev))
6712 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6713 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006714 else
6715 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006716 DPLL_FPA01_P1_POST_DIV_SHIFT);
6717
6718 switch (dpll & DPLL_MODE_MASK) {
6719 case DPLLB_MODE_DAC_SERIAL:
6720 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6721 5 : 10;
6722 break;
6723 case DPLLB_MODE_LVDS:
6724 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6725 7 : 14;
6726 break;
6727 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006728 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006729 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6730 return 0;
6731 }
6732
6733 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08006734 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006735 } else {
6736 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6737
6738 if (is_lvds) {
6739 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6740 DPLL_FPA01_P1_POST_DIV_SHIFT);
6741 clock.p2 = 14;
6742
6743 if ((dpll & PLL_REF_INPUT_MASK) ==
6744 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6745 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08006746 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006747 } else
Shaohua Li21778322009-02-23 15:19:16 +08006748 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006749 } else {
6750 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6751 clock.p1 = 2;
6752 else {
6753 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6754 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6755 }
6756 if (dpll & PLL_P2_DIVIDE_BY_4)
6757 clock.p2 = 4;
6758 else
6759 clock.p2 = 2;
6760
Shaohua Li21778322009-02-23 15:19:16 +08006761 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006762 }
6763 }
6764
6765 /* XXX: It would be nice to validate the clocks, but we can't reuse
6766 * i830PllIsValid() because it relies on the xf86_config connector
6767 * configuration being accurate, which it isn't necessarily.
6768 */
6769
6770 return clock.dot;
6771}
6772
6773/** Returns the currently programmed mode of the given pipe. */
6774struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6775 struct drm_crtc *crtc)
6776{
Jesse Barnes548f2452011-02-17 10:40:53 -08006777 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006779 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006780 struct drm_display_mode *mode;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006781 int htot = I915_READ(HTOTAL(cpu_transcoder));
6782 int hsync = I915_READ(HSYNC(cpu_transcoder));
6783 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6784 int vsync = I915_READ(VSYNC(cpu_transcoder));
Jesse Barnes79e53942008-11-07 14:24:08 -08006785
6786 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6787 if (!mode)
6788 return NULL;
6789
6790 mode->clock = intel_crtc_clock_get(dev, crtc);
6791 mode->hdisplay = (htot & 0xffff) + 1;
6792 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6793 mode->hsync_start = (hsync & 0xffff) + 1;
6794 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6795 mode->vdisplay = (vtot & 0xffff) + 1;
6796 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6797 mode->vsync_start = (vsync & 0xffff) + 1;
6798 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6799
6800 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006801
6802 return mode;
6803}
6804
Daniel Vetter3dec0092010-08-20 21:40:52 +02006805static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006806{
6807 struct drm_device *dev = crtc->dev;
6808 drm_i915_private_t *dev_priv = dev->dev_private;
6809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006811 int dpll_reg = DPLL(pipe);
6812 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006813
Eric Anholtbad720f2009-10-22 16:11:14 -07006814 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006815 return;
6816
6817 if (!dev_priv->lvds_downclock_avail)
6818 return;
6819
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006820 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006821 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006822 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006823
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006824 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006825
6826 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6827 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006828 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006829
Jesse Barnes652c3932009-08-17 13:31:43 -07006830 dpll = I915_READ(dpll_reg);
6831 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006832 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006833 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006834}
6835
6836static void intel_decrease_pllclock(struct drm_crtc *crtc)
6837{
6838 struct drm_device *dev = crtc->dev;
6839 drm_i915_private_t *dev_priv = dev->dev_private;
6840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006841
Eric Anholtbad720f2009-10-22 16:11:14 -07006842 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006843 return;
6844
6845 if (!dev_priv->lvds_downclock_avail)
6846 return;
6847
6848 /*
6849 * Since this is called by a timer, we should never get here in
6850 * the manual case.
6851 */
6852 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01006853 int pipe = intel_crtc->pipe;
6854 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02006855 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01006856
Zhao Yakui44d98a62009-10-09 11:39:40 +08006857 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006858
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006859 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006860
Chris Wilson074b5e12012-05-02 12:07:06 +01006861 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006862 dpll |= DISPLAY_RATE_SELECT_FPA1;
6863 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006864 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006865 dpll = I915_READ(dpll_reg);
6866 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08006867 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006868 }
6869
6870}
6871
Chris Wilsonf047e392012-07-21 12:31:41 +01006872void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07006873{
Chris Wilsonf047e392012-07-21 12:31:41 +01006874 i915_update_gfx_val(dev->dev_private);
6875}
6876
6877void intel_mark_idle(struct drm_device *dev)
6878{
Chris Wilson725a5b52013-01-08 11:02:57 +00006879 struct drm_crtc *crtc;
6880
6881 if (!i915_powersave)
6882 return;
6883
6884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6885 if (!crtc->fb)
6886 continue;
6887
6888 intel_decrease_pllclock(crtc);
6889 }
Chris Wilsonf047e392012-07-21 12:31:41 +01006890}
6891
6892void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6893{
6894 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07006895 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07006896
6897 if (!i915_powersave)
6898 return;
6899
Jesse Barnes652c3932009-08-17 13:31:43 -07006900 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006901 if (!crtc->fb)
6902 continue;
6903
Chris Wilsonf047e392012-07-21 12:31:41 +01006904 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6905 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006906 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006907}
6908
Jesse Barnes79e53942008-11-07 14:24:08 -08006909static void intel_crtc_destroy(struct drm_crtc *crtc)
6910{
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006912 struct drm_device *dev = crtc->dev;
6913 struct intel_unpin_work *work;
6914 unsigned long flags;
6915
6916 spin_lock_irqsave(&dev->event_lock, flags);
6917 work = intel_crtc->unpin_work;
6918 intel_crtc->unpin_work = NULL;
6919 spin_unlock_irqrestore(&dev->event_lock, flags);
6920
6921 if (work) {
6922 cancel_work_sync(&work->work);
6923 kfree(work);
6924 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006925
6926 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006927
Jesse Barnes79e53942008-11-07 14:24:08 -08006928 kfree(intel_crtc);
6929}
6930
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006931static void intel_unpin_work_fn(struct work_struct *__work)
6932{
6933 struct intel_unpin_work *work =
6934 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00006935 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006936
Chris Wilsonb4a98e52012-11-01 09:26:26 +00006937 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01006938 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00006939 drm_gem_object_unreference(&work->pending_flip_obj->base);
6940 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006941
Chris Wilsonb4a98e52012-11-01 09:26:26 +00006942 intel_update_fbc(dev);
6943 mutex_unlock(&dev->struct_mutex);
6944
6945 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6946 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6947
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006948 kfree(work);
6949}
6950
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006951static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01006952 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006953{
6954 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006957 unsigned long flags;
6958
6959 /* Ignore early vblank irqs */
6960 if (intel_crtc == NULL)
6961 return;
6962
6963 spin_lock_irqsave(&dev->event_lock, flags);
6964 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00006965
6966 /* Ensure we don't miss a work->pending update ... */
6967 smp_rmb();
6968
6969 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006970 spin_unlock_irqrestore(&dev->event_lock, flags);
6971 return;
6972 }
6973
Chris Wilsone7d841c2012-12-03 11:36:30 +00006974 /* and that the unpin work is consistent wrt ->pending. */
6975 smp_rmb();
6976
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006977 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006978
Rob Clark45a066e2012-10-08 14:50:40 -05006979 if (work->event)
6980 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006981
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006982 drm_vblank_put(dev, intel_crtc->pipe);
6983
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006984 spin_unlock_irqrestore(&dev->event_lock, flags);
6985
Daniel Vetter2c10d572012-12-20 21:24:07 +01006986 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00006987
6988 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006989
6990 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006991}
6992
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006993void intel_finish_page_flip(struct drm_device *dev, int pipe)
6994{
6995 drm_i915_private_t *dev_priv = dev->dev_private;
6996 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6997
Mario Kleiner49b14a52010-12-09 07:00:07 +01006998 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006999}
7000
7001void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7002{
7003 drm_i915_private_t *dev_priv = dev->dev_private;
7004 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7005
Mario Kleiner49b14a52010-12-09 07:00:07 +01007006 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007007}
7008
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007009void intel_prepare_page_flip(struct drm_device *dev, int plane)
7010{
7011 drm_i915_private_t *dev_priv = dev->dev_private;
7012 struct intel_crtc *intel_crtc =
7013 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7014 unsigned long flags;
7015
Chris Wilsone7d841c2012-12-03 11:36:30 +00007016 /* NB: An MMIO update of the plane base pointer will also
7017 * generate a page-flip completion irq, i.e. every modeset
7018 * is also accompanied by a spurious intel_prepare_page_flip().
7019 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007020 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007021 if (intel_crtc->unpin_work)
7022 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007023 spin_unlock_irqrestore(&dev->event_lock, flags);
7024}
7025
Chris Wilsone7d841c2012-12-03 11:36:30 +00007026inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7027{
7028 /* Ensure that the work item is consistent when activating it ... */
7029 smp_wmb();
7030 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7031 /* and that it is marked active as soon as the irq could fire. */
7032 smp_wmb();
7033}
7034
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007035static int intel_gen2_queue_flip(struct drm_device *dev,
7036 struct drm_crtc *crtc,
7037 struct drm_framebuffer *fb,
7038 struct drm_i915_gem_object *obj)
7039{
7040 struct drm_i915_private *dev_priv = dev->dev_private;
7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007042 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007043 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007044 int ret;
7045
Daniel Vetter6d90c952012-04-26 23:28:05 +02007046 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007047 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007048 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007049
Daniel Vetter6d90c952012-04-26 23:28:05 +02007050 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007051 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007052 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007053
7054 /* Can't queue multiple flips, so wait for the previous
7055 * one to finish before executing the next.
7056 */
7057 if (intel_crtc->plane)
7058 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7059 else
7060 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007061 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7062 intel_ring_emit(ring, MI_NOOP);
7063 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7064 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7065 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007066 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007067 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00007068
7069 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007070 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007071 return 0;
7072
7073err_unpin:
7074 intel_unpin_fb_obj(obj);
7075err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007076 return ret;
7077}
7078
7079static int intel_gen3_queue_flip(struct drm_device *dev,
7080 struct drm_crtc *crtc,
7081 struct drm_framebuffer *fb,
7082 struct drm_i915_gem_object *obj)
7083{
7084 struct drm_i915_private *dev_priv = dev->dev_private;
7085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007086 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007087 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007088 int ret;
7089
Daniel Vetter6d90c952012-04-26 23:28:05 +02007090 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007091 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007092 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007093
Daniel Vetter6d90c952012-04-26 23:28:05 +02007094 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007095 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007096 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007097
7098 if (intel_crtc->plane)
7099 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7100 else
7101 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007102 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7103 intel_ring_emit(ring, MI_NOOP);
7104 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007107 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007108 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007109
Chris Wilsone7d841c2012-12-03 11:36:30 +00007110 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007111 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007112 return 0;
7113
7114err_unpin:
7115 intel_unpin_fb_obj(obj);
7116err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007117 return ret;
7118}
7119
7120static int intel_gen4_queue_flip(struct drm_device *dev,
7121 struct drm_crtc *crtc,
7122 struct drm_framebuffer *fb,
7123 struct drm_i915_gem_object *obj)
7124{
7125 struct drm_i915_private *dev_priv = dev->dev_private;
7126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7127 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007128 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007129 int ret;
7130
Daniel Vetter6d90c952012-04-26 23:28:05 +02007131 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007132 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007133 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007134
Daniel Vetter6d90c952012-04-26 23:28:05 +02007135 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007136 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007137 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007138
7139 /* i965+ uses the linear or tiled offsets from the
7140 * Display Registers (which do not change across a page-flip)
7141 * so we need only reprogram the base address.
7142 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02007143 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7144 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7145 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007146 intel_ring_emit(ring,
7147 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7148 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007149
7150 /* XXX Enabling the panel-fitter across page-flip is so far
7151 * untested on non-native modes, so ignore it for now.
7152 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7153 */
7154 pf = 0;
7155 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007156 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007157
7158 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007159 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007160 return 0;
7161
7162err_unpin:
7163 intel_unpin_fb_obj(obj);
7164err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007165 return ret;
7166}
7167
7168static int intel_gen6_queue_flip(struct drm_device *dev,
7169 struct drm_crtc *crtc,
7170 struct drm_framebuffer *fb,
7171 struct drm_i915_gem_object *obj)
7172{
7173 struct drm_i915_private *dev_priv = dev->dev_private;
7174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007175 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007176 uint32_t pf, pipesrc;
7177 int ret;
7178
Daniel Vetter6d90c952012-04-26 23:28:05 +02007179 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007180 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007181 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007182
Daniel Vetter6d90c952012-04-26 23:28:05 +02007183 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007184 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007185 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007186
Daniel Vetter6d90c952012-04-26 23:28:05 +02007187 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7188 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7189 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007190 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007191
Chris Wilson99d9acd2012-04-17 20:37:00 +01007192 /* Contrary to the suggestions in the documentation,
7193 * "Enable Panel Fitter" does not seem to be required when page
7194 * flipping with a non-native mode, and worse causes a normal
7195 * modeset to fail.
7196 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7197 */
7198 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007199 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007200 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007201
7202 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007203 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007204 return 0;
7205
7206err_unpin:
7207 intel_unpin_fb_obj(obj);
7208err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007209 return ret;
7210}
7211
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007212/*
7213 * On gen7 we currently use the blit ring because (in early silicon at least)
7214 * the render ring doesn't give us interrpts for page flip completion, which
7215 * means clients will hang after the first flip is queued. Fortunately the
7216 * blit ring generates interrupts properly, so use it instead.
7217 */
7218static int intel_gen7_queue_flip(struct drm_device *dev,
7219 struct drm_crtc *crtc,
7220 struct drm_framebuffer *fb,
7221 struct drm_i915_gem_object *obj)
7222{
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007226 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007227 int ret;
7228
7229 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7230 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007231 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007232
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007233 switch(intel_crtc->plane) {
7234 case PLANE_A:
7235 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7236 break;
7237 case PLANE_B:
7238 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7239 break;
7240 case PLANE_C:
7241 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7242 break;
7243 default:
7244 WARN_ONCE(1, "unknown plane in flip command\n");
7245 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03007246 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007247 }
7248
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007249 ret = intel_ring_begin(ring, 4);
7250 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007251 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007252
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007253 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007254 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02007255 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007256 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00007257
7258 intel_mark_page_flip_active(intel_crtc);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007259 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007260 return 0;
7261
7262err_unpin:
7263 intel_unpin_fb_obj(obj);
7264err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007265 return ret;
7266}
7267
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007268static int intel_default_queue_flip(struct drm_device *dev,
7269 struct drm_crtc *crtc,
7270 struct drm_framebuffer *fb,
7271 struct drm_i915_gem_object *obj)
7272{
7273 return -ENODEV;
7274}
7275
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007276static int intel_crtc_page_flip(struct drm_crtc *crtc,
7277 struct drm_framebuffer *fb,
7278 struct drm_pending_vblank_event *event)
7279{
7280 struct drm_device *dev = crtc->dev;
7281 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007282 struct drm_framebuffer *old_fb = crtc->fb;
7283 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007286 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007287 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007288
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03007289 /* Can't change pixel format via MI display flips. */
7290 if (fb->pixel_format != crtc->fb->pixel_format)
7291 return -EINVAL;
7292
7293 /*
7294 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7295 * Note that pitch changes could also affect these register.
7296 */
7297 if (INTEL_INFO(dev)->gen > 3 &&
7298 (fb->offsets[0] != crtc->fb->offsets[0] ||
7299 fb->pitches[0] != crtc->fb->pitches[0]))
7300 return -EINVAL;
7301
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007302 work = kzalloc(sizeof *work, GFP_KERNEL);
7303 if (work == NULL)
7304 return -ENOMEM;
7305
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007306 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007307 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007308 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007309 INIT_WORK(&work->work, intel_unpin_work_fn);
7310
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007311 ret = drm_vblank_get(dev, intel_crtc->pipe);
7312 if (ret)
7313 goto free_work;
7314
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007315 /* We borrow the event spin lock for protecting unpin_work */
7316 spin_lock_irqsave(&dev->event_lock, flags);
7317 if (intel_crtc->unpin_work) {
7318 spin_unlock_irqrestore(&dev->event_lock, flags);
7319 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007320 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01007321
7322 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007323 return -EBUSY;
7324 }
7325 intel_crtc->unpin_work = work;
7326 spin_unlock_irqrestore(&dev->event_lock, flags);
7327
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007328 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7329 flush_workqueue(dev_priv->wq);
7330
Chris Wilson79158102012-05-23 11:13:58 +01007331 ret = i915_mutex_lock_interruptible(dev);
7332 if (ret)
7333 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007334
Jesse Barnes75dfca82010-02-10 15:09:44 -08007335 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007336 drm_gem_object_reference(&work->old_fb_obj->base);
7337 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007338
7339 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007340
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007341 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007342
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007343 work->enable_stall_check = true;
7344
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007345 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02007346 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007347
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007348 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7349 if (ret)
7350 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007351
Chris Wilson7782de32011-07-08 12:22:41 +01007352 intel_disable_fbc(dev);
Chris Wilsonf047e392012-07-21 12:31:41 +01007353 intel_mark_fb_busy(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007354 mutex_unlock(&dev->struct_mutex);
7355
Jesse Barnese5510fa2010-07-01 16:48:37 -07007356 trace_i915_flip_request(intel_crtc->plane, obj);
7357
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007358 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007359
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007360cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007361 atomic_dec(&intel_crtc->unpin_work_count);
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007362 crtc->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007363 drm_gem_object_unreference(&work->old_fb_obj->base);
7364 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007365 mutex_unlock(&dev->struct_mutex);
7366
Chris Wilson79158102012-05-23 11:13:58 +01007367cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01007368 spin_lock_irqsave(&dev->event_lock, flags);
7369 intel_crtc->unpin_work = NULL;
7370 spin_unlock_irqrestore(&dev->event_lock, flags);
7371
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007372 drm_vblank_put(dev, intel_crtc->pipe);
7373free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01007374 kfree(work);
7375
7376 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007377}
7378
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007379static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007380 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7381 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007382};
7383
Daniel Vetter6ed0f792012-07-08 19:41:43 +02007384bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7385{
7386 struct intel_encoder *other_encoder;
7387 struct drm_crtc *crtc = &encoder->new_crtc->base;
7388
7389 if (WARN_ON(!crtc))
7390 return false;
7391
7392 list_for_each_entry(other_encoder,
7393 &crtc->dev->mode_config.encoder_list,
7394 base.head) {
7395
7396 if (&other_encoder->new_crtc->base != crtc ||
7397 encoder == other_encoder)
7398 continue;
7399 else
7400 return true;
7401 }
7402
7403 return false;
7404}
7405
Daniel Vetter50f56112012-07-02 09:35:43 +02007406static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7407 struct drm_crtc *crtc)
7408{
7409 struct drm_device *dev;
7410 struct drm_crtc *tmp;
7411 int crtc_mask = 1;
7412
7413 WARN(!crtc, "checking null crtc?\n");
7414
7415 dev = crtc->dev;
7416
7417 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7418 if (tmp == crtc)
7419 break;
7420 crtc_mask <<= 1;
7421 }
7422
7423 if (encoder->possible_crtcs & crtc_mask)
7424 return true;
7425 return false;
7426}
7427
Daniel Vetter9a935852012-07-05 22:34:27 +02007428/**
7429 * intel_modeset_update_staged_output_state
7430 *
7431 * Updates the staged output configuration state, e.g. after we've read out the
7432 * current hw state.
7433 */
7434static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7435{
7436 struct intel_encoder *encoder;
7437 struct intel_connector *connector;
7438
7439 list_for_each_entry(connector, &dev->mode_config.connector_list,
7440 base.head) {
7441 connector->new_encoder =
7442 to_intel_encoder(connector->base.encoder);
7443 }
7444
7445 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7446 base.head) {
7447 encoder->new_crtc =
7448 to_intel_crtc(encoder->base.crtc);
7449 }
7450}
7451
7452/**
7453 * intel_modeset_commit_output_state
7454 *
7455 * This function copies the stage display pipe configuration to the real one.
7456 */
7457static void intel_modeset_commit_output_state(struct drm_device *dev)
7458{
7459 struct intel_encoder *encoder;
7460 struct intel_connector *connector;
7461
7462 list_for_each_entry(connector, &dev->mode_config.connector_list,
7463 base.head) {
7464 connector->base.encoder = &connector->new_encoder->base;
7465 }
7466
7467 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7468 base.head) {
7469 encoder->base.crtc = &encoder->new_crtc->base;
7470 }
7471}
7472
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007473static int
7474pipe_config_set_bpp(struct drm_crtc *crtc,
7475 struct drm_framebuffer *fb,
7476 struct intel_crtc_config *pipe_config)
7477{
7478 struct drm_device *dev = crtc->dev;
7479 struct drm_connector *connector;
7480 int bpp;
7481
Daniel Vetterd42264b2013-03-28 16:38:08 +01007482 switch (fb->pixel_format) {
7483 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007484 bpp = 8*3; /* since we go through a colormap */
7485 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007486 case DRM_FORMAT_XRGB1555:
7487 case DRM_FORMAT_ARGB1555:
7488 /* checked in intel_framebuffer_init already */
7489 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7490 return -EINVAL;
7491 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007492 bpp = 6*3; /* min is 18bpp */
7493 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007494 case DRM_FORMAT_XBGR8888:
7495 case DRM_FORMAT_ABGR8888:
7496 /* checked in intel_framebuffer_init already */
7497 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7498 return -EINVAL;
7499 case DRM_FORMAT_XRGB8888:
7500 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007501 bpp = 8*3;
7502 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007503 case DRM_FORMAT_XRGB2101010:
7504 case DRM_FORMAT_ARGB2101010:
7505 case DRM_FORMAT_XBGR2101010:
7506 case DRM_FORMAT_ABGR2101010:
7507 /* checked in intel_framebuffer_init already */
7508 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01007509 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007510 bpp = 10*3;
7511 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01007512 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007513 default:
7514 DRM_DEBUG_KMS("unsupported depth\n");
7515 return -EINVAL;
7516 }
7517
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007518 pipe_config->pipe_bpp = bpp;
7519
7520 /* Clamp display bpp to EDID value */
7521 list_for_each_entry(connector, &dev->mode_config.connector_list,
7522 head) {
7523 if (connector->encoder && connector->encoder->crtc != crtc)
7524 continue;
7525
7526 /* Don't use an invalid EDID bpc value */
7527 if (connector->display_info.bpc &&
7528 connector->display_info.bpc * 3 < bpp) {
7529 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7530 bpp, connector->display_info.bpc*3);
7531 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7532 }
7533 }
7534
7535 return bpp;
7536}
7537
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007538static struct intel_crtc_config *
7539intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007540 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007541 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02007542{
7543 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02007544 struct drm_encoder_helper_funcs *encoder_funcs;
7545 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007546 struct intel_crtc_config *pipe_config;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007547 int plane_bpp;
Daniel Vetter7758a112012-07-08 19:40:39 +02007548
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007549 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7550 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02007551 return ERR_PTR(-ENOMEM);
7552
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007553 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7554 drm_mode_copy(&pipe_config->requested_mode, mode);
7555
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007556 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7557 if (plane_bpp < 0)
7558 goto fail;
7559
Daniel Vetter7758a112012-07-08 19:40:39 +02007560 /* Pass our mode to the connectors and the CRTC to give them a chance to
7561 * adjust it according to limitations or connector properties, and also
7562 * a chance to reject the mode entirely.
7563 */
7564 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7565 base.head) {
7566
7567 if (&encoder->new_crtc->base != crtc)
7568 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01007569
7570 if (encoder->compute_config) {
7571 if (!(encoder->compute_config(encoder, pipe_config))) {
7572 DRM_DEBUG_KMS("Encoder config failure\n");
7573 goto fail;
7574 }
7575
7576 continue;
7577 }
7578
Daniel Vetter7758a112012-07-08 19:40:39 +02007579 encoder_funcs = encoder->base.helper_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007580 if (!(encoder_funcs->mode_fixup(&encoder->base,
7581 &pipe_config->requested_mode,
7582 &pipe_config->adjusted_mode))) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007583 DRM_DEBUG_KMS("Encoder fixup failed\n");
7584 goto fail;
7585 }
7586 }
7587
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007588 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007589 DRM_DEBUG_KMS("CRTC fixup failed\n");
7590 goto fail;
7591 }
7592 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7593
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007594 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7595 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7596 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7597
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007598 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02007599fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007600 kfree(pipe_config);
Daniel Vetter7758a112012-07-08 19:40:39 +02007601 return ERR_PTR(-EINVAL);
7602}
7603
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007604/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7605 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7606static void
7607intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7608 unsigned *prepare_pipes, unsigned *disable_pipes)
7609{
7610 struct intel_crtc *intel_crtc;
7611 struct drm_device *dev = crtc->dev;
7612 struct intel_encoder *encoder;
7613 struct intel_connector *connector;
7614 struct drm_crtc *tmp_crtc;
7615
7616 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7617
7618 /* Check which crtcs have changed outputs connected to them, these need
7619 * to be part of the prepare_pipes mask. We don't (yet) support global
7620 * modeset across multiple crtcs, so modeset_pipes will only have one
7621 * bit set at most. */
7622 list_for_each_entry(connector, &dev->mode_config.connector_list,
7623 base.head) {
7624 if (connector->base.encoder == &connector->new_encoder->base)
7625 continue;
7626
7627 if (connector->base.encoder) {
7628 tmp_crtc = connector->base.encoder->crtc;
7629
7630 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7631 }
7632
7633 if (connector->new_encoder)
7634 *prepare_pipes |=
7635 1 << connector->new_encoder->new_crtc->pipe;
7636 }
7637
7638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7639 base.head) {
7640 if (encoder->base.crtc == &encoder->new_crtc->base)
7641 continue;
7642
7643 if (encoder->base.crtc) {
7644 tmp_crtc = encoder->base.crtc;
7645
7646 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7647 }
7648
7649 if (encoder->new_crtc)
7650 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7651 }
7652
7653 /* Check for any pipes that will be fully disabled ... */
7654 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7655 base.head) {
7656 bool used = false;
7657
7658 /* Don't try to disable disabled crtcs. */
7659 if (!intel_crtc->base.enabled)
7660 continue;
7661
7662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7663 base.head) {
7664 if (encoder->new_crtc == intel_crtc)
7665 used = true;
7666 }
7667
7668 if (!used)
7669 *disable_pipes |= 1 << intel_crtc->pipe;
7670 }
7671
7672
7673 /* set_mode is also used to update properties on life display pipes. */
7674 intel_crtc = to_intel_crtc(crtc);
7675 if (crtc->enabled)
7676 *prepare_pipes |= 1 << intel_crtc->pipe;
7677
7678 /* We only support modeset on one single crtc, hence we need to do that
7679 * only for the passed in crtc iff we change anything else than just
7680 * disable crtcs.
7681 *
7682 * This is actually not true, to be fully compatible with the old crtc
7683 * helper we automatically disable _any_ output (i.e. doesn't need to be
7684 * connected to the crtc we're modesetting on) if it's disconnected.
7685 * Which is a rather nutty api (since changed the output configuration
7686 * without userspace's explicit request can lead to confusion), but
7687 * alas. Hence we currently need to modeset on all pipes we prepare. */
7688 if (*prepare_pipes)
7689 *modeset_pipes = *prepare_pipes;
7690
7691 /* ... and mask these out. */
7692 *modeset_pipes &= ~(*disable_pipes);
7693 *prepare_pipes &= ~(*disable_pipes);
7694}
7695
Daniel Vetterea9d7582012-07-10 10:42:52 +02007696static bool intel_crtc_in_use(struct drm_crtc *crtc)
7697{
7698 struct drm_encoder *encoder;
7699 struct drm_device *dev = crtc->dev;
7700
7701 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7702 if (encoder->crtc == crtc)
7703 return true;
7704
7705 return false;
7706}
7707
7708static void
7709intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7710{
7711 struct intel_encoder *intel_encoder;
7712 struct intel_crtc *intel_crtc;
7713 struct drm_connector *connector;
7714
7715 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7716 base.head) {
7717 if (!intel_encoder->base.crtc)
7718 continue;
7719
7720 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7721
7722 if (prepare_pipes & (1 << intel_crtc->pipe))
7723 intel_encoder->connectors_active = false;
7724 }
7725
7726 intel_modeset_commit_output_state(dev);
7727
7728 /* Update computed state. */
7729 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7730 base.head) {
7731 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7732 }
7733
7734 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7735 if (!connector->encoder || !connector->encoder->crtc)
7736 continue;
7737
7738 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7739
7740 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02007741 struct drm_property *dpms_property =
7742 dev->mode_config.dpms_property;
7743
Daniel Vetterea9d7582012-07-10 10:42:52 +02007744 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05007745 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02007746 dpms_property,
7747 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02007748
7749 intel_encoder = to_intel_encoder(connector->encoder);
7750 intel_encoder->connectors_active = true;
7751 }
7752 }
7753
7754}
7755
Daniel Vetter25c5b262012-07-08 22:08:04 +02007756#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7757 list_for_each_entry((intel_crtc), \
7758 &(dev)->mode_config.crtc_list, \
7759 base.head) \
7760 if (mask & (1 <<(intel_crtc)->pipe)) \
7761
Daniel Vetterb9805142012-08-31 17:37:33 +02007762void
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007763intel_modeset_check_state(struct drm_device *dev)
7764{
7765 struct intel_crtc *crtc;
7766 struct intel_encoder *encoder;
7767 struct intel_connector *connector;
7768
7769 list_for_each_entry(connector, &dev->mode_config.connector_list,
7770 base.head) {
7771 /* This also checks the encoder/connector hw state with the
7772 * ->get_hw_state callbacks. */
7773 intel_connector_check_state(connector);
7774
7775 WARN(&connector->new_encoder->base != connector->base.encoder,
7776 "connector's staged encoder doesn't match current encoder\n");
7777 }
7778
7779 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7780 base.head) {
7781 bool enabled = false;
7782 bool active = false;
7783 enum pipe pipe, tracked_pipe;
7784
7785 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7786 encoder->base.base.id,
7787 drm_get_encoder_name(&encoder->base));
7788
7789 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7790 "encoder's stage crtc doesn't match current crtc\n");
7791 WARN(encoder->connectors_active && !encoder->base.crtc,
7792 "encoder's active_connectors set, but no crtc\n");
7793
7794 list_for_each_entry(connector, &dev->mode_config.connector_list,
7795 base.head) {
7796 if (connector->base.encoder != &encoder->base)
7797 continue;
7798 enabled = true;
7799 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7800 active = true;
7801 }
7802 WARN(!!encoder->base.crtc != enabled,
7803 "encoder's enabled state mismatch "
7804 "(expected %i, found %i)\n",
7805 !!encoder->base.crtc, enabled);
7806 WARN(active && !encoder->base.crtc,
7807 "active encoder with no crtc\n");
7808
7809 WARN(encoder->connectors_active != active,
7810 "encoder's computed active state doesn't match tracked active state "
7811 "(expected %i, found %i)\n", active, encoder->connectors_active);
7812
7813 active = encoder->get_hw_state(encoder, &pipe);
7814 WARN(active != encoder->connectors_active,
7815 "encoder's hw state doesn't match sw tracking "
7816 "(expected %i, found %i)\n",
7817 encoder->connectors_active, active);
7818
7819 if (!encoder->base.crtc)
7820 continue;
7821
7822 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7823 WARN(active && pipe != tracked_pipe,
7824 "active encoder's pipe doesn't match"
7825 "(expected %i, found %i)\n",
7826 tracked_pipe, pipe);
7827
7828 }
7829
7830 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7831 base.head) {
7832 bool enabled = false;
7833 bool active = false;
7834
7835 DRM_DEBUG_KMS("[CRTC:%d]\n",
7836 crtc->base.base.id);
7837
7838 WARN(crtc->active && !crtc->base.enabled,
7839 "active crtc, but not enabled in sw tracking\n");
7840
7841 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7842 base.head) {
7843 if (encoder->base.crtc != &crtc->base)
7844 continue;
7845 enabled = true;
7846 if (encoder->connectors_active)
7847 active = true;
7848 }
7849 WARN(active != crtc->active,
7850 "crtc's computed active state doesn't match tracked active state "
7851 "(expected %i, found %i)\n", active, crtc->active);
7852 WARN(enabled != crtc->base.enabled,
7853 "crtc's computed enabled state doesn't match tracked enabled state "
7854 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7855
7856 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7857 }
7858}
7859
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007860int intel_set_mode(struct drm_crtc *crtc,
7861 struct drm_display_mode *mode,
7862 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02007863{
7864 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02007865 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007866 struct drm_display_mode *saved_mode, *saved_hwmode;
7867 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +02007868 struct intel_crtc *intel_crtc;
7869 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007870 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +02007871
Tim Gardner3ac18232012-12-07 07:54:26 -07007872 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007873 if (!saved_mode)
7874 return -ENOMEM;
Tim Gardner3ac18232012-12-07 07:54:26 -07007875 saved_hwmode = saved_mode + 1;
Daniel Vettera6778b32012-07-02 09:56:42 +02007876
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007877 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02007878 &prepare_pipes, &disable_pipes);
7879
Tim Gardner3ac18232012-12-07 07:54:26 -07007880 *saved_hwmode = crtc->hwmode;
7881 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007882
Daniel Vetter25c5b262012-07-08 22:08:04 +02007883 /* Hack: Because we don't (yet) support global modeset on multiple
7884 * crtcs, we don't keep track of the new mode for more than one crtc.
7885 * Hence simply check whether any bit is set in modeset_pipes in all the
7886 * pieces of code that are not yet converted to deal with mutliple crtcs
7887 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007888 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007889 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007890 if (IS_ERR(pipe_config)) {
7891 ret = PTR_ERR(pipe_config);
7892 pipe_config = NULL;
7893
Tim Gardner3ac18232012-12-07 07:54:26 -07007894 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +02007895 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007896 }
7897
Daniel Vetter460da9162013-03-27 00:44:51 +01007898 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7899 modeset_pipes, prepare_pipes, disable_pipes);
7900
7901 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7902 intel_crtc_disable(&intel_crtc->base);
7903
Daniel Vetterea9d7582012-07-10 10:42:52 +02007904 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7905 if (intel_crtc->base.enabled)
7906 dev_priv->display.crtc_disable(&intel_crtc->base);
7907 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007908
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02007909 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7910 * to set it here already despite that we pass it down the callchain.
7911 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007912 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +02007913 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007914 /* mode_set/enable/disable functions rely on a correct pipe
7915 * config. */
7916 to_intel_crtc(crtc)->config = *pipe_config;
7917 }
Daniel Vetter7758a112012-07-08 19:40:39 +02007918
Daniel Vetterea9d7582012-07-10 10:42:52 +02007919 /* Only after disabling all output pipelines that will be changed can we
7920 * update the the output configuration. */
7921 intel_modeset_update_state(dev, prepare_pipes);
7922
Daniel Vetter47fab732012-10-26 10:58:18 +02007923 if (dev_priv->display.modeset_global_resources)
7924 dev_priv->display.modeset_global_resources(dev);
7925
Daniel Vettera6778b32012-07-02 09:56:42 +02007926 /* Set up the DPLL and any encoders state that needs to adjust or depend
7927 * on the DPLL.
7928 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007929 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007930 ret = intel_crtc_mode_set(&intel_crtc->base,
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007931 x, y, fb);
7932 if (ret)
7933 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02007934 }
7935
7936 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007937 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7938 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02007939
Daniel Vetter25c5b262012-07-08 22:08:04 +02007940 if (modeset_pipes) {
7941 /* Store real post-adjustment hardware mode. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007942 crtc->hwmode = pipe_config->adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007943
Daniel Vetter25c5b262012-07-08 22:08:04 +02007944 /* Calculate and store various constants which
7945 * are later needed by vblank and swap-completion
7946 * timestamping. They are derived from true hwmode.
7947 */
7948 drm_calc_timestamping_constants(crtc);
7949 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007950
7951 /* FIXME: add subpixel order */
7952done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007953 if (ret && crtc->enabled) {
Tim Gardner3ac18232012-12-07 07:54:26 -07007954 crtc->hwmode = *saved_hwmode;
7955 crtc->mode = *saved_mode;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007956 } else {
7957 intel_modeset_check_state(dev);
Daniel Vettera6778b32012-07-02 09:56:42 +02007958 }
7959
Tim Gardner3ac18232012-12-07 07:54:26 -07007960out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007961 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -07007962 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +02007963 return ret;
7964}
7965
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007966void intel_crtc_restore_mode(struct drm_crtc *crtc)
7967{
7968 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7969}
7970
Daniel Vetter25c5b262012-07-08 22:08:04 +02007971#undef for_each_intel_crtc_masked
7972
Daniel Vetterd9e55602012-07-04 22:16:09 +02007973static void intel_set_config_free(struct intel_set_config *config)
7974{
7975 if (!config)
7976 return;
7977
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007978 kfree(config->save_connector_encoders);
7979 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02007980 kfree(config);
7981}
7982
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007983static int intel_set_config_save_state(struct drm_device *dev,
7984 struct intel_set_config *config)
7985{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007986 struct drm_encoder *encoder;
7987 struct drm_connector *connector;
7988 int count;
7989
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007990 config->save_encoder_crtcs =
7991 kcalloc(dev->mode_config.num_encoder,
7992 sizeof(struct drm_crtc *), GFP_KERNEL);
7993 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007994 return -ENOMEM;
7995
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007996 config->save_connector_encoders =
7997 kcalloc(dev->mode_config.num_connector,
7998 sizeof(struct drm_encoder *), GFP_KERNEL);
7999 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008000 return -ENOMEM;
8001
8002 /* Copy data. Note that driver private data is not affected.
8003 * Should anything bad happen only the expected state is
8004 * restored, not the drivers personal bookkeeping.
8005 */
8006 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008008 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008009 }
8010
8011 count = 0;
8012 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008013 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008014 }
8015
8016 return 0;
8017}
8018
8019static void intel_set_config_restore_state(struct drm_device *dev,
8020 struct intel_set_config *config)
8021{
Daniel Vetter9a935852012-07-05 22:34:27 +02008022 struct intel_encoder *encoder;
8023 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008024 int count;
8025
8026 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008027 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8028 encoder->new_crtc =
8029 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008030 }
8031
8032 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008033 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8034 connector->new_encoder =
8035 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008036 }
8037}
8038
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008039static void
8040intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8041 struct intel_set_config *config)
8042{
8043
8044 /* We should be able to check here if the fb has the same properties
8045 * and then just flip_or_move it */
8046 if (set->crtc->fb != set->fb) {
8047 /* If we have no fb then treat it as a full mode set */
8048 if (set->crtc->fb == NULL) {
8049 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8050 config->mode_changed = true;
8051 } else if (set->fb == NULL) {
8052 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +01008053 } else if (set->fb->pixel_format !=
8054 set->crtc->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008055 config->mode_changed = true;
8056 } else
8057 config->fb_changed = true;
8058 }
8059
Daniel Vetter835c5872012-07-10 18:11:08 +02008060 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008061 config->fb_changed = true;
8062
8063 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8064 DRM_DEBUG_KMS("modes are different, full mode set\n");
8065 drm_mode_debug_printmodeline(&set->crtc->mode);
8066 drm_mode_debug_printmodeline(set->mode);
8067 config->mode_changed = true;
8068 }
8069}
8070
Daniel Vetter2e431052012-07-04 22:42:15 +02008071static int
Daniel Vetter9a935852012-07-05 22:34:27 +02008072intel_modeset_stage_output_state(struct drm_device *dev,
8073 struct drm_mode_set *set,
8074 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02008075{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008076 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02008077 struct intel_connector *connector;
8078 struct intel_encoder *encoder;
Daniel Vetter2e431052012-07-04 22:42:15 +02008079 int count, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02008080
Damien Lespiau9abdda72013-02-13 13:29:23 +00008081 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +02008082 * of connectors. For paranoia, double-check this. */
8083 WARN_ON(!set->fb && (set->num_connectors != 0));
8084 WARN_ON(set->fb && (set->num_connectors == 0));
8085
Daniel Vetter50f56112012-07-02 09:35:43 +02008086 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008087 list_for_each_entry(connector, &dev->mode_config.connector_list,
8088 base.head) {
8089 /* Otherwise traverse passed in connector list and get encoders
8090 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008091 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008092 if (set->connectors[ro] == &connector->base) {
8093 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02008094 break;
8095 }
8096 }
8097
Daniel Vetter9a935852012-07-05 22:34:27 +02008098 /* If we disable the crtc, disable all its connectors. Also, if
8099 * the connector is on the changing crtc but not on the new
8100 * connector list, disable it. */
8101 if ((!set->fb || ro == set->num_connectors) &&
8102 connector->base.encoder &&
8103 connector->base.encoder->crtc == set->crtc) {
8104 connector->new_encoder = NULL;
8105
8106 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8107 connector->base.base.id,
8108 drm_get_connector_name(&connector->base));
8109 }
8110
8111
8112 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008113 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008114 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008115 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008116 }
8117 /* connector->new_encoder is now updated for all connectors. */
8118
8119 /* Update crtc of enabled connectors. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008120 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008121 list_for_each_entry(connector, &dev->mode_config.connector_list,
8122 base.head) {
8123 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02008124 continue;
8125
Daniel Vetter9a935852012-07-05 22:34:27 +02008126 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02008127
8128 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008129 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02008130 new_crtc = set->crtc;
8131 }
8132
8133 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02008134 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8135 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008136 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02008137 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008138 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8139
8140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8141 connector->base.base.id,
8142 drm_get_connector_name(&connector->base),
8143 new_crtc->base.id);
8144 }
8145
8146 /* Check for any encoders that needs to be disabled. */
8147 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8148 base.head) {
8149 list_for_each_entry(connector,
8150 &dev->mode_config.connector_list,
8151 base.head) {
8152 if (connector->new_encoder == encoder) {
8153 WARN_ON(!connector->new_encoder->new_crtc);
8154
8155 goto next_encoder;
8156 }
8157 }
8158 encoder->new_crtc = NULL;
8159next_encoder:
8160 /* Only now check for crtc changes so we don't miss encoders
8161 * that will be disabled. */
8162 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008163 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008164 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008165 }
8166 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008167 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008168
Daniel Vetter2e431052012-07-04 22:42:15 +02008169 return 0;
8170}
8171
8172static int intel_crtc_set_config(struct drm_mode_set *set)
8173{
8174 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02008175 struct drm_mode_set save_set;
8176 struct intel_set_config *config;
8177 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02008178
Daniel Vetter8d3e3752012-07-05 16:09:09 +02008179 BUG_ON(!set);
8180 BUG_ON(!set->crtc);
8181 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02008182
Daniel Vetter7e53f3a2013-01-21 10:52:17 +01008183 /* Enforce sane interface api - has been abused by the fb helper. */
8184 BUG_ON(!set->mode && set->fb);
8185 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +02008186
Daniel Vetter2e431052012-07-04 22:42:15 +02008187 if (set->fb) {
8188 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8189 set->crtc->base.id, set->fb->base.id,
8190 (int)set->num_connectors, set->x, set->y);
8191 } else {
8192 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02008193 }
8194
8195 dev = set->crtc->dev;
8196
8197 ret = -ENOMEM;
8198 config = kzalloc(sizeof(*config), GFP_KERNEL);
8199 if (!config)
8200 goto out_config;
8201
8202 ret = intel_set_config_save_state(dev, config);
8203 if (ret)
8204 goto out_config;
8205
8206 save_set.crtc = set->crtc;
8207 save_set.mode = &set->crtc->mode;
8208 save_set.x = set->crtc->x;
8209 save_set.y = set->crtc->y;
8210 save_set.fb = set->crtc->fb;
8211
8212 /* Compute whether we need a full modeset, only an fb base update or no
8213 * change at all. In the future we might also check whether only the
8214 * mode changed, e.g. for LVDS where we only change the panel fitter in
8215 * such cases. */
8216 intel_set_config_compute_mode_changes(set, config);
8217
Daniel Vetter9a935852012-07-05 22:34:27 +02008218 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02008219 if (ret)
8220 goto fail;
8221
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008222 if (config->mode_changed) {
Daniel Vetter87f1faa2012-07-05 23:36:17 +02008223 if (set->mode) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008224 DRM_DEBUG_KMS("attempting to set mode from"
8225 " userspace\n");
8226 drm_mode_debug_printmodeline(set->mode);
Daniel Vetter87f1faa2012-07-05 23:36:17 +02008227 }
8228
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008229 ret = intel_set_mode(set->crtc, set->mode,
8230 set->x, set->y, set->fb);
8231 if (ret) {
8232 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8233 set->crtc->base.id, ret);
Daniel Vetter87f1faa2012-07-05 23:36:17 +02008234 goto fail;
8235 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008236 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +02008237 intel_crtc_wait_for_pending_flips(set->crtc);
8238
Daniel Vetter4f660f42012-07-02 09:47:37 +02008239 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02008240 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02008241 }
8242
Daniel Vetterd9e55602012-07-04 22:16:09 +02008243 intel_set_config_free(config);
8244
Daniel Vetter50f56112012-07-02 09:35:43 +02008245 return 0;
8246
8247fail:
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008248 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008249
8250 /* Try to restore the config */
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008251 if (config->mode_changed &&
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008252 intel_set_mode(save_set.crtc, save_set.mode,
8253 save_set.x, save_set.y, save_set.fb))
Daniel Vetter50f56112012-07-02 09:35:43 +02008254 DRM_ERROR("failed to restore config after modeset failure\n");
8255
Daniel Vetterd9e55602012-07-04 22:16:09 +02008256out_config:
8257 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008258 return ret;
8259}
8260
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008261static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008262 .cursor_set = intel_crtc_cursor_set,
8263 .cursor_move = intel_crtc_cursor_move,
8264 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02008265 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008266 .destroy = intel_crtc_destroy,
8267 .page_flip = intel_crtc_page_flip,
8268};
8269
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008270static void intel_cpu_pll_init(struct drm_device *dev)
8271{
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008272 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008273 intel_ddi_pll_init(dev);
8274}
8275
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008276static void intel_pch_pll_init(struct drm_device *dev)
8277{
8278 drm_i915_private_t *dev_priv = dev->dev_private;
8279 int i;
8280
8281 if (dev_priv->num_pch_pll == 0) {
8282 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8283 return;
8284 }
8285
8286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8287 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8288 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8289 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8290 }
8291}
8292
Hannes Ederb358d0a2008-12-18 21:18:47 +01008293static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08008294{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008295 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008296 struct intel_crtc *intel_crtc;
8297 int i;
8298
8299 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8300 if (intel_crtc == NULL)
8301 return;
8302
8303 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8304
8305 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08008306 for (i = 0; i < 256; i++) {
8307 intel_crtc->lut_r[i] = i;
8308 intel_crtc->lut_g[i] = i;
8309 intel_crtc->lut_b[i] = i;
8310 }
8311
Jesse Barnes80824002009-09-10 15:28:06 -07008312 /* Swap pipes & planes for FBC on pre-965 */
8313 intel_crtc->pipe = pipe;
8314 intel_crtc->plane = pipe;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02008315 intel_crtc->cpu_transcoder = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01008316 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008317 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01008318 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07008319 }
8320
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008321 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8322 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8323 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8324 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8325
Jesse Barnes79e53942008-11-07 14:24:08 -08008326 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08008327}
8328
Carl Worth08d7b3d2009-04-29 14:43:54 -07008329int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00008330 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07008331{
Carl Worth08d7b3d2009-04-29 14:43:54 -07008332 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02008333 struct drm_mode_object *drmmode_obj;
8334 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008335
Daniel Vetter1cff8f62012-04-24 09:55:08 +02008336 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8337 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008338
Daniel Vetterc05422d2009-08-11 16:05:30 +02008339 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8340 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07008341
Daniel Vetterc05422d2009-08-11 16:05:30 +02008342 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07008343 DRM_ERROR("no such CRTC id\n");
8344 return -EINVAL;
8345 }
8346
Daniel Vetterc05422d2009-08-11 16:05:30 +02008347 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8348 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008349
Daniel Vetterc05422d2009-08-11 16:05:30 +02008350 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008351}
8352
Daniel Vetter66a92782012-07-12 20:08:18 +02008353static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008354{
Daniel Vetter66a92782012-07-12 20:08:18 +02008355 struct drm_device *dev = encoder->base.dev;
8356 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008357 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008358 int entry = 0;
8359
Daniel Vetter66a92782012-07-12 20:08:18 +02008360 list_for_each_entry(source_encoder,
8361 &dev->mode_config.encoder_list, base.head) {
8362
8363 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008364 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02008365
8366 /* Intel hw has only one MUX where enocoders could be cloned. */
8367 if (encoder->cloneable && source_encoder->cloneable)
8368 index_mask |= (1 << entry);
8369
Jesse Barnes79e53942008-11-07 14:24:08 -08008370 entry++;
8371 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01008372
Jesse Barnes79e53942008-11-07 14:24:08 -08008373 return index_mask;
8374}
8375
Chris Wilson4d302442010-12-14 19:21:29 +00008376static bool has_edp_a(struct drm_device *dev)
8377{
8378 struct drm_i915_private *dev_priv = dev->dev_private;
8379
8380 if (!IS_MOBILE(dev))
8381 return false;
8382
8383 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8384 return false;
8385
8386 if (IS_GEN5(dev) &&
8387 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8388 return false;
8389
8390 return true;
8391}
8392
Jesse Barnes79e53942008-11-07 14:24:08 -08008393static void intel_setup_outputs(struct drm_device *dev)
8394{
Eric Anholt725e30a2009-01-22 13:01:02 -08008395 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008396 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008397 bool dpd_is_edp = false;
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00008398 bool has_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08008399
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00008400 has_lvds = intel_lvds_init(dev);
Chris Wilsonc5d1b512010-11-29 18:00:23 +00008401 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8402 /* disable the panel fitter on everything but LVDS */
8403 I915_WRITE(PFIT_CONTROL, 0);
8404 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008405
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008406 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
Paulo Zanoni79935fc2012-11-20 13:27:40 -02008407 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008408
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008409 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03008410 int found;
8411
8412 /* Haswell uses DDI functions to detect digital outputs */
8413 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8414 /* DDI A only supports eDP */
8415 if (found)
8416 intel_ddi_init(dev, PORT_A);
8417
8418 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8419 * register */
8420 found = I915_READ(SFUSE_STRAP);
8421
8422 if (found & SFUSE_STRAP_DDIB_DETECTED)
8423 intel_ddi_init(dev, PORT_B);
8424 if (found & SFUSE_STRAP_DDIC_DETECTED)
8425 intel_ddi_init(dev, PORT_C);
8426 if (found & SFUSE_STRAP_DDID_DETECTED)
8427 intel_ddi_init(dev, PORT_D);
8428 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008429 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +02008430 dpd_is_edp = intel_dpd_is_edp(dev);
8431
8432 if (has_edp_a(dev))
8433 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008434
Paulo Zanonidc0fa712013-02-19 16:21:46 -03008435 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08008436 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01008437 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008438 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -03008439 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008440 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008441 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008442 }
8443
Paulo Zanonidc0fa712013-02-19 16:21:46 -03008444 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03008445 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008446
Paulo Zanonidc0fa712013-02-19 16:21:46 -03008447 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03008448 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008449
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008450 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008451 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008452
Daniel Vetter270b3042012-10-27 15:52:05 +02008453 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008454 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008455 } else if (IS_VALLEYVIEW(dev)) {
Gajanan Bhat19c03922012-09-27 19:13:07 +05308456 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
Ville Syrjälä67cfc202013-01-25 21:44:44 +02008457 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8458 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +05308459
Paulo Zanonidc0fa712013-02-19 16:21:46 -03008460 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
Paulo Zanonie2debe92013-02-18 19:00:27 -03008461 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8462 PORT_B);
Ville Syrjälä67cfc202013-01-25 21:44:44 +02008463 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8464 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008465 }
Zhenyu Wang103a1962009-11-27 11:44:36 +08008466 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08008467 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08008468
Paulo Zanonie2debe92013-02-18 19:00:27 -03008469 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008470 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03008471 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008472 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8473 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03008474 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008475 }
Ma Ling27185ae2009-08-24 13:50:23 +08008476
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008477 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8478 DRM_DEBUG_KMS("probing DP_B\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008479 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008480 }
Eric Anholt725e30a2009-01-22 13:01:02 -08008481 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04008482
8483 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04008484
Paulo Zanonie2debe92013-02-18 19:00:27 -03008485 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008486 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03008487 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008488 }
Ma Ling27185ae2009-08-24 13:50:23 +08008489
Paulo Zanonie2debe92013-02-18 19:00:27 -03008490 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +08008491
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008492 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8493 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03008494 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008495 }
8496 if (SUPPORTS_INTEGRATED_DP(dev)) {
8497 DRM_DEBUG_KMS("probing DP_C\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008498 intel_dp_init(dev, DP_C, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008499 }
Eric Anholt725e30a2009-01-22 13:01:02 -08008500 }
Ma Ling27185ae2009-08-24 13:50:23 +08008501
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008502 if (SUPPORTS_INTEGRATED_DP(dev) &&
8503 (I915_READ(DP_D) & DP_DETECTED)) {
8504 DRM_DEBUG_KMS("probing DP_D\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008505 intel_dp_init(dev, DP_D, PORT_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008506 }
Eric Anholtbad720f2009-10-22 16:11:14 -07008507 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08008508 intel_dvo_init(dev);
8509
Zhenyu Wang103a1962009-11-27 11:44:36 +08008510 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08008511 intel_tv_init(dev);
8512
Chris Wilson4ef69c72010-09-09 15:14:28 +01008513 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8514 encoder->base.possible_crtcs = encoder->crtc_mask;
8515 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02008516 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08008517 }
Chris Wilson47356eb2011-01-11 17:06:04 +00008518
Paulo Zanonidde86e22012-12-01 12:04:25 -02008519 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +02008520
8521 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008522}
8523
8524static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8525{
8526 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08008527
8528 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008529 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008530
8531 kfree(intel_fb);
8532}
8533
8534static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00008535 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008536 unsigned int *handle)
8537{
8538 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008539 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008540
Chris Wilson05394f32010-11-08 19:18:58 +00008541 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08008542}
8543
8544static const struct drm_framebuffer_funcs intel_fb_funcs = {
8545 .destroy = intel_user_framebuffer_destroy,
8546 .create_handle = intel_user_framebuffer_create_handle,
8547};
8548
Dave Airlie38651672010-03-30 05:34:13 +00008549int intel_framebuffer_init(struct drm_device *dev,
8550 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008551 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00008552 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08008553{
Jesse Barnes79e53942008-11-07 14:24:08 -08008554 int ret;
8555
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008556 if (obj->tiling_mode == I915_TILING_Y) {
8557 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +01008558 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008559 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008560
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008561 if (mode_cmd->pitches[0] & 63) {
8562 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8563 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +01008564 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008565 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008566
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008567 /* FIXME <= Gen4 stride limits are bit unclear */
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008568 if (mode_cmd->pitches[0] > 32768) {
8569 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8570 mode_cmd->pitches[0]);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008571 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008572 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008573
8574 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008575 mode_cmd->pitches[0] != obj->stride) {
8576 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8577 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008578 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008579 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008580
Ville Syrjälä57779d02012-10-31 17:50:14 +02008581 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008582 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +02008583 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +02008584 case DRM_FORMAT_RGB565:
8585 case DRM_FORMAT_XRGB8888:
8586 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02008587 break;
8588 case DRM_FORMAT_XRGB1555:
8589 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008590 if (INTEL_INFO(dev)->gen > 3) {
8591 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008592 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008593 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02008594 break;
8595 case DRM_FORMAT_XBGR8888:
8596 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02008597 case DRM_FORMAT_XRGB2101010:
8598 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02008599 case DRM_FORMAT_XBGR2101010:
8600 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008601 if (INTEL_INFO(dev)->gen < 4) {
8602 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008603 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008604 }
Jesse Barnesb5626742011-06-24 12:19:27 -07008605 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02008606 case DRM_FORMAT_YUYV:
8607 case DRM_FORMAT_UYVY:
8608 case DRM_FORMAT_YVYU:
8609 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008610 if (INTEL_INFO(dev)->gen < 5) {
8611 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008612 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008613 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008614 break;
8615 default:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008616 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01008617 return -EINVAL;
8618 }
8619
Ville Syrjälä90f9a332012-10-31 17:50:19 +02008620 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8621 if (mode_cmd->offsets[0] != 0)
8622 return -EINVAL;
8623
Daniel Vetterc7d73f62012-12-13 23:38:38 +01008624 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8625 intel_fb->obj = obj;
8626
Jesse Barnes79e53942008-11-07 14:24:08 -08008627 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8628 if (ret) {
8629 DRM_ERROR("framebuffer init failed %d\n", ret);
8630 return ret;
8631 }
8632
Jesse Barnes79e53942008-11-07 14:24:08 -08008633 return 0;
8634}
8635
Jesse Barnes79e53942008-11-07 14:24:08 -08008636static struct drm_framebuffer *
8637intel_user_framebuffer_create(struct drm_device *dev,
8638 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008639 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08008640{
Chris Wilson05394f32010-11-08 19:18:58 +00008641 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008642
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008643 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8644 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00008645 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01008646 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08008647
Chris Wilsond2dff872011-04-19 08:36:26 +01008648 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08008649}
8650
Jesse Barnes79e53942008-11-07 14:24:08 -08008651static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08008652 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00008653 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08008654};
8655
Jesse Barnese70236a2009-09-21 10:42:27 -07008656/* Set up chip specific display functions */
8657static void intel_init_display(struct drm_device *dev)
8658{
8659 struct drm_i915_private *dev_priv = dev->dev_private;
8660
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008661 if (HAS_DDI(dev)) {
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008662 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02008663 dev_priv->display.crtc_enable = haswell_crtc_enable;
8664 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008665 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008666 dev_priv->display.update_plane = ironlake_update_plane;
8667 } else if (HAS_PCH_SPLIT(dev)) {
Eric Anholtf564048e2011-03-30 13:01:02 -07008668 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008669 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8670 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008671 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008672 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008673 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07008674 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008675 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8676 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008677 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008678 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008679 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008680
Jesse Barnese70236a2009-09-21 10:42:27 -07008681 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07008682 if (IS_VALLEYVIEW(dev))
8683 dev_priv->display.get_display_clock_speed =
8684 valleyview_get_display_clock_speed;
8685 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07008686 dev_priv->display.get_display_clock_speed =
8687 i945_get_display_clock_speed;
8688 else if (IS_I915G(dev))
8689 dev_priv->display.get_display_clock_speed =
8690 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008691 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008692 dev_priv->display.get_display_clock_speed =
8693 i9xx_misc_get_display_clock_speed;
8694 else if (IS_I915GM(dev))
8695 dev_priv->display.get_display_clock_speed =
8696 i915gm_get_display_clock_speed;
8697 else if (IS_I865G(dev))
8698 dev_priv->display.get_display_clock_speed =
8699 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02008700 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008701 dev_priv->display.get_display_clock_speed =
8702 i855_get_display_clock_speed;
8703 else /* 852, 830 */
8704 dev_priv->display.get_display_clock_speed =
8705 i830_get_display_clock_speed;
8706
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008707 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01008708 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008709 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008710 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08008711 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008712 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008713 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07008714 } else if (IS_IVYBRIDGE(dev)) {
8715 /* FIXME: detect B0+ stepping and use auto training */
8716 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008717 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +02008718 dev_priv->display.modeset_global_resources =
8719 ivb_modeset_global_resources;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03008720 } else if (IS_HASWELL(dev)) {
8721 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08008722 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02008723 dev_priv->display.modeset_global_resources =
8724 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -02008725 }
Jesse Barnes6067aae2011-04-28 15:04:31 -07008726 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08008727 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07008728 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008729
8730 /* Default just returns -ENODEV to indicate unsupported */
8731 dev_priv->display.queue_flip = intel_default_queue_flip;
8732
8733 switch (INTEL_INFO(dev)->gen) {
8734 case 2:
8735 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8736 break;
8737
8738 case 3:
8739 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8740 break;
8741
8742 case 4:
8743 case 5:
8744 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8745 break;
8746
8747 case 6:
8748 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8749 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008750 case 7:
8751 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8752 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008753 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008754}
8755
Jesse Barnesb690e962010-07-19 13:53:12 -07008756/*
8757 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8758 * resume, or other times. This quirk makes sure that's the case for
8759 * affected systems.
8760 */
Akshay Joshi0206e352011-08-16 15:34:10 -04008761static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07008762{
8763 struct drm_i915_private *dev_priv = dev->dev_private;
8764
8765 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008766 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008767}
8768
Keith Packard435793d2011-07-12 14:56:22 -07008769/*
8770 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8771 */
8772static void quirk_ssc_force_disable(struct drm_device *dev)
8773{
8774 struct drm_i915_private *dev_priv = dev->dev_private;
8775 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008776 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07008777}
8778
Carsten Emde4dca20e2012-03-15 15:56:26 +01008779/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01008780 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8781 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01008782 */
8783static void quirk_invert_brightness(struct drm_device *dev)
8784{
8785 struct drm_i915_private *dev_priv = dev->dev_private;
8786 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008787 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008788}
8789
8790struct intel_quirk {
8791 int device;
8792 int subsystem_vendor;
8793 int subsystem_device;
8794 void (*hook)(struct drm_device *dev);
8795};
8796
Egbert Eich5f85f1762012-10-14 15:46:38 +02008797/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8798struct intel_dmi_quirk {
8799 void (*hook)(struct drm_device *dev);
8800 const struct dmi_system_id (*dmi_id_list)[];
8801};
8802
8803static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8804{
8805 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8806 return 1;
8807}
8808
8809static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8810 {
8811 .dmi_id_list = &(const struct dmi_system_id[]) {
8812 {
8813 .callback = intel_dmi_reverse_brightness,
8814 .ident = "NCR Corporation",
8815 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8816 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8817 },
8818 },
8819 { } /* terminating entry */
8820 },
8821 .hook = quirk_invert_brightness,
8822 },
8823};
8824
Ben Widawskyc43b5632012-04-16 14:07:40 -07008825static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07008826 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04008827 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07008828
Jesse Barnesb690e962010-07-19 13:53:12 -07008829 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8830 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8831
Jesse Barnesb690e962010-07-19 13:53:12 -07008832 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8833 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8834
Daniel Vetterccd0d362012-10-10 23:13:59 +02008835 /* 830/845 need to leave pipe A & dpll A up */
Jesse Barnesb690e962010-07-19 13:53:12 -07008836 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02008837 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07008838
8839 /* Lenovo U160 cannot use SSC on LVDS */
8840 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02008841
8842 /* Sony Vaio Y cannot use SSC on LVDS */
8843 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01008844
8845 /* Acer Aspire 5734Z must invert backlight brightness */
8846 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jani Nikula1ffff602013-01-22 12:50:34 +02008847
8848 /* Acer/eMachines G725 */
8849 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
Jani Nikula01e3a8f2013-01-22 12:50:35 +02008850
8851 /* Acer/eMachines e725 */
8852 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
Jani Nikula5559eca2013-01-22 12:50:36 +02008853
8854 /* Acer/Packard Bell NCL20 */
8855 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
Daniel Vetterac4199e2013-02-15 18:35:30 +01008856
8857 /* Acer Aspire 4736Z */
8858 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07008859};
8860
8861static void intel_init_quirks(struct drm_device *dev)
8862{
8863 struct pci_dev *d = dev->pdev;
8864 int i;
8865
8866 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8867 struct intel_quirk *q = &intel_quirks[i];
8868
8869 if (d->device == q->device &&
8870 (d->subsystem_vendor == q->subsystem_vendor ||
8871 q->subsystem_vendor == PCI_ANY_ID) &&
8872 (d->subsystem_device == q->subsystem_device ||
8873 q->subsystem_device == PCI_ANY_ID))
8874 q->hook(dev);
8875 }
Egbert Eich5f85f1762012-10-14 15:46:38 +02008876 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8877 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8878 intel_dmi_quirks[i].hook(dev);
8879 }
Jesse Barnesb690e962010-07-19 13:53:12 -07008880}
8881
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008882/* Disable the VGA plane that we never use */
8883static void i915_disable_vga(struct drm_device *dev)
8884{
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02008887 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008888
8889 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07008890 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008891 sr1 = inb(VGA_SR_DATA);
8892 outb(sr1 | 1<<5, VGA_SR_DATA);
8893 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8894 udelay(300);
8895
8896 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8897 POSTING_READ(vga_reg);
8898}
8899
Daniel Vetterf8175862012-04-10 15:50:11 +02008900void intel_modeset_init_hw(struct drm_device *dev)
8901{
Paulo Zanonifa42e232013-01-25 16:59:11 -02008902 intel_init_power_well(dev);
Eugeni Dodonov0232e922012-07-06 15:42:36 -03008903
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03008904 intel_prepare_ddi(dev);
8905
Daniel Vetterf8175862012-04-10 15:50:11 +02008906 intel_init_clock_gating(dev);
8907
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008908 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02008909 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008910 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02008911}
8912
Jesse Barnes79e53942008-11-07 14:24:08 -08008913void intel_modeset_init(struct drm_device *dev)
8914{
Jesse Barnes652c3932009-08-17 13:31:43 -07008915 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07008916 int i, j, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008917
8918 drm_mode_config_init(dev);
8919
8920 dev->mode_config.min_width = 0;
8921 dev->mode_config.min_height = 0;
8922
Dave Airlie019d96c2011-09-29 16:20:42 +01008923 dev->mode_config.preferred_depth = 24;
8924 dev->mode_config.prefer_shadow = 1;
8925
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02008926 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08008927
Jesse Barnesb690e962010-07-19 13:53:12 -07008928 intel_init_quirks(dev);
8929
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03008930 intel_init_pm(dev);
8931
Jesse Barnese70236a2009-09-21 10:42:27 -07008932 intel_init_display(dev);
8933
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008934 if (IS_GEN2(dev)) {
8935 dev->mode_config.max_width = 2048;
8936 dev->mode_config.max_height = 2048;
8937 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07008938 dev->mode_config.max_width = 4096;
8939 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08008940 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008941 dev->mode_config.max_width = 8192;
8942 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08008943 }
Ben Widawsky5d4545a2013-01-17 12:45:15 -08008944 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008945
Zhao Yakui28c97732009-10-09 11:39:41 +08008946 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -07008947 INTEL_INFO(dev)->num_pipes,
8948 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08008949
Ben Widawsky7eb552a2013-03-13 14:05:41 -07008950 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008951 intel_crtc_init(dev, i);
Jesse Barnes7f1f3852013-04-02 11:22:20 -07008952 for (j = 0; j < dev_priv->num_plane; j++) {
8953 ret = intel_plane_init(dev, i, j);
8954 if (ret)
8955 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
8956 i, j, ret);
8957 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008958 }
8959
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008960 intel_cpu_pll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008961 intel_pch_pll_init(dev);
8962
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008963 /* Just disable it once at startup */
8964 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008965 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00008966
8967 /* Just in case the BIOS is doing something questionable. */
8968 intel_disable_fbc(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01008969}
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008970
Daniel Vetter24929352012-07-02 20:28:59 +02008971static void
8972intel_connector_break_all_links(struct intel_connector *connector)
8973{
8974 connector->base.dpms = DRM_MODE_DPMS_OFF;
8975 connector->base.encoder = NULL;
8976 connector->encoder->connectors_active = false;
8977 connector->encoder->base.crtc = NULL;
8978}
8979
Daniel Vetter7fad7982012-07-04 17:51:47 +02008980static void intel_enable_pipe_a(struct drm_device *dev)
8981{
8982 struct intel_connector *connector;
8983 struct drm_connector *crt = NULL;
8984 struct intel_load_detect_pipe load_detect_temp;
8985
8986 /* We can't just switch on the pipe A, we need to set things up with a
8987 * proper mode and output configuration. As a gross hack, enable pipe A
8988 * by enabling the load detect pipe once. */
8989 list_for_each_entry(connector,
8990 &dev->mode_config.connector_list,
8991 base.head) {
8992 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8993 crt = &connector->base;
8994 break;
8995 }
8996 }
8997
8998 if (!crt)
8999 return;
9000
9001 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9002 intel_release_load_detect_pipe(crt, &load_detect_temp);
9003
9004
9005}
9006
Daniel Vetterfa555832012-10-10 23:14:00 +02009007static bool
9008intel_check_plane_mapping(struct intel_crtc *crtc)
9009{
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009012 u32 reg, val;
9013
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009014 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +02009015 return true;
9016
9017 reg = DSPCNTR(!crtc->plane);
9018 val = I915_READ(reg);
9019
9020 if ((val & DISPLAY_PLANE_ENABLE) &&
9021 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9022 return false;
9023
9024 return true;
9025}
9026
Daniel Vetter24929352012-07-02 20:28:59 +02009027static void intel_sanitize_crtc(struct intel_crtc *crtc)
9028{
9029 struct drm_device *dev = crtc->base.dev;
9030 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009031 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +02009032
Daniel Vetter24929352012-07-02 20:28:59 +02009033 /* Clear any frame start delays used for debugging left by the BIOS */
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009034 reg = PIPECONF(crtc->cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +02009035 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9036
9037 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +02009038 * disable the crtc (and hence change the state) if it is wrong. Note
9039 * that gen4+ has a fixed plane -> pipe mapping. */
9040 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +02009041 struct intel_connector *connector;
9042 bool plane;
9043
Daniel Vetter24929352012-07-02 20:28:59 +02009044 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9045 crtc->base.base.id);
9046
9047 /* Pipe has the wrong plane attached and the plane is active.
9048 * Temporarily change the plane mapping and disable everything
9049 * ... */
9050 plane = crtc->plane;
9051 crtc->plane = !plane;
9052 dev_priv->display.crtc_disable(&crtc->base);
9053 crtc->plane = plane;
9054
9055 /* ... and break all links. */
9056 list_for_each_entry(connector, &dev->mode_config.connector_list,
9057 base.head) {
9058 if (connector->encoder->base.crtc != &crtc->base)
9059 continue;
9060
9061 intel_connector_break_all_links(connector);
9062 }
9063
9064 WARN_ON(crtc->active);
9065 crtc->base.enabled = false;
9066 }
Daniel Vetter24929352012-07-02 20:28:59 +02009067
Daniel Vetter7fad7982012-07-04 17:51:47 +02009068 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9069 crtc->pipe == PIPE_A && !crtc->active) {
9070 /* BIOS forgot to enable pipe A, this mostly happens after
9071 * resume. Force-enable the pipe to fix this, the update_dpms
9072 * call below we restore the pipe to the right state, but leave
9073 * the required bits on. */
9074 intel_enable_pipe_a(dev);
9075 }
9076
Daniel Vetter24929352012-07-02 20:28:59 +02009077 /* Adjust the state of the output pipe according to whether we
9078 * have active connectors/encoders. */
9079 intel_crtc_update_dpms(&crtc->base);
9080
9081 if (crtc->active != crtc->base.enabled) {
9082 struct intel_encoder *encoder;
9083
9084 /* This can happen either due to bugs in the get_hw_state
9085 * functions or because the pipe is force-enabled due to the
9086 * pipe A quirk. */
9087 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9088 crtc->base.base.id,
9089 crtc->base.enabled ? "enabled" : "disabled",
9090 crtc->active ? "enabled" : "disabled");
9091
9092 crtc->base.enabled = crtc->active;
9093
9094 /* Because we only establish the connector -> encoder ->
9095 * crtc links if something is active, this means the
9096 * crtc is now deactivated. Break the links. connector
9097 * -> encoder links are only establish when things are
9098 * actually up, hence no need to break them. */
9099 WARN_ON(crtc->active);
9100
9101 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9102 WARN_ON(encoder->connectors_active);
9103 encoder->base.crtc = NULL;
9104 }
9105 }
9106}
9107
9108static void intel_sanitize_encoder(struct intel_encoder *encoder)
9109{
9110 struct intel_connector *connector;
9111 struct drm_device *dev = encoder->base.dev;
9112
9113 /* We need to check both for a crtc link (meaning that the
9114 * encoder is active and trying to read from a pipe) and the
9115 * pipe itself being active. */
9116 bool has_active_crtc = encoder->base.crtc &&
9117 to_intel_crtc(encoder->base.crtc)->active;
9118
9119 if (encoder->connectors_active && !has_active_crtc) {
9120 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9121 encoder->base.base.id,
9122 drm_get_encoder_name(&encoder->base));
9123
9124 /* Connector is active, but has no active pipe. This is
9125 * fallout from our resume register restoring. Disable
9126 * the encoder manually again. */
9127 if (encoder->base.crtc) {
9128 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9129 encoder->base.base.id,
9130 drm_get_encoder_name(&encoder->base));
9131 encoder->disable(encoder);
9132 }
9133
9134 /* Inconsistent output/port/pipe state happens presumably due to
9135 * a bug in one of the get_hw_state functions. Or someplace else
9136 * in our code, like the register restore mess on resume. Clamp
9137 * things to off as a safer default. */
9138 list_for_each_entry(connector,
9139 &dev->mode_config.connector_list,
9140 base.head) {
9141 if (connector->encoder != encoder)
9142 continue;
9143
9144 intel_connector_break_all_links(connector);
9145 }
9146 }
9147 /* Enabled encoders without active connectors will be fixed in
9148 * the crtc fixup. */
9149}
9150
Daniel Vetter44cec742013-01-25 17:53:21 +01009151void i915_redisable_vga(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009152{
9153 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02009154 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009155
9156 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9157 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
Ville Syrjälä209d5212013-01-25 21:44:48 +02009158 i915_disable_vga(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009159 }
9160}
9161
Daniel Vetter24929352012-07-02 20:28:59 +02009162/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9163 * and i915 state tracking structures. */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009164void intel_modeset_setup_hw_state(struct drm_device *dev,
9165 bool force_restore)
Daniel Vetter24929352012-07-02 20:28:59 +02009166{
9167 struct drm_i915_private *dev_priv = dev->dev_private;
9168 enum pipe pipe;
9169 u32 tmp;
Jesse Barnesb5644d02013-03-26 13:25:27 -07009170 struct drm_plane *plane;
Daniel Vetter24929352012-07-02 20:28:59 +02009171 struct intel_crtc *crtc;
9172 struct intel_encoder *encoder;
9173 struct intel_connector *connector;
9174
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009175 if (HAS_DDI(dev)) {
Paulo Zanonie28d54c2012-10-24 16:09:25 -02009176 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9177
9178 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9179 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9180 case TRANS_DDI_EDP_INPUT_A_ON:
9181 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9182 pipe = PIPE_A;
9183 break;
9184 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9185 pipe = PIPE_B;
9186 break;
9187 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9188 pipe = PIPE_C;
9189 break;
Damien Lespiauaaa148e2013-03-07 15:30:26 +00009190 default:
9191 /* A bogus value has been programmed, disable
9192 * the transcoder */
9193 WARN(1, "Bogus eDP source %08x\n", tmp);
9194 intel_ddi_disable_transcoder_func(dev_priv,
9195 TRANSCODER_EDP);
9196 goto setup_pipes;
Paulo Zanonie28d54c2012-10-24 16:09:25 -02009197 }
9198
9199 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9200 crtc->cpu_transcoder = TRANSCODER_EDP;
9201
9202 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9203 pipe_name(pipe));
9204 }
9205 }
9206
Damien Lespiauaaa148e2013-03-07 15:30:26 +00009207setup_pipes:
Daniel Vetter24929352012-07-02 20:28:59 +02009208 for_each_pipe(pipe) {
9209 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9210
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009211 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
Daniel Vetter24929352012-07-02 20:28:59 +02009212 if (tmp & PIPECONF_ENABLE)
9213 crtc->active = true;
9214 else
9215 crtc->active = false;
9216
9217 crtc->base.enabled = crtc->active;
9218
9219 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9220 crtc->base.base.id,
9221 crtc->active ? "enabled" : "disabled");
9222 }
9223
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009224 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009225 intel_ddi_setup_hw_pll_state(dev);
9226
Daniel Vetter24929352012-07-02 20:28:59 +02009227 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9228 base.head) {
9229 pipe = 0;
9230
9231 if (encoder->get_hw_state(encoder, &pipe)) {
9232 encoder->base.crtc =
9233 dev_priv->pipe_to_crtc_mapping[pipe];
9234 } else {
9235 encoder->base.crtc = NULL;
9236 }
9237
9238 encoder->connectors_active = false;
9239 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9240 encoder->base.base.id,
9241 drm_get_encoder_name(&encoder->base),
9242 encoder->base.crtc ? "enabled" : "disabled",
9243 pipe);
9244 }
9245
9246 list_for_each_entry(connector, &dev->mode_config.connector_list,
9247 base.head) {
9248 if (connector->get_hw_state(connector)) {
9249 connector->base.dpms = DRM_MODE_DPMS_ON;
9250 connector->encoder->connectors_active = true;
9251 connector->base.encoder = &connector->encoder->base;
9252 } else {
9253 connector->base.dpms = DRM_MODE_DPMS_OFF;
9254 connector->base.encoder = NULL;
9255 }
9256 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9257 connector->base.base.id,
9258 drm_get_connector_name(&connector->base),
9259 connector->base.encoder ? "enabled" : "disabled");
9260 }
9261
9262 /* HW state is read out, now we need to sanitize this mess. */
9263 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9264 base.head) {
9265 intel_sanitize_encoder(encoder);
9266 }
9267
9268 for_each_pipe(pipe) {
9269 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9270 intel_sanitize_crtc(crtc);
9271 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009272
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009273 if (force_restore) {
9274 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -07009275 struct drm_crtc *crtc =
9276 dev_priv->pipe_to_crtc_mapping[pipe];
9277 intel_crtc_restore_mode(crtc);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009278 }
Jesse Barnesb5644d02013-03-26 13:25:27 -07009279 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9280 intel_plane_restore(plane);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009281
9282 i915_redisable_vga(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009283 } else {
9284 intel_modeset_update_staged_output_state(dev);
9285 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009286
9287 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +02009288
9289 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009290}
9291
9292void intel_modeset_gem_init(struct drm_device *dev)
9293{
Chris Wilson1833b132012-05-09 11:56:28 +01009294 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02009295
9296 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02009297
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009298 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -08009299}
9300
9301void intel_modeset_cleanup(struct drm_device *dev)
9302{
Jesse Barnes652c3932009-08-17 13:31:43 -07009303 struct drm_i915_private *dev_priv = dev->dev_private;
9304 struct drm_crtc *crtc;
9305 struct intel_crtc *intel_crtc;
9306
Keith Packardf87ea762010-10-03 19:36:26 -07009307 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07009308 mutex_lock(&dev->struct_mutex);
9309
Jesse Barnes723bfd72010-10-07 16:01:13 -07009310 intel_unregister_dsm_handler();
9311
9312
Jesse Barnes652c3932009-08-17 13:31:43 -07009313 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9314 /* Skip inactive CRTCs */
9315 if (!crtc->fb)
9316 continue;
9317
9318 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02009319 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07009320 }
9321
Chris Wilson973d04f2011-07-08 12:22:37 +01009322 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07009323
Daniel Vetter8090c6b2012-06-24 16:42:32 +02009324 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00009325
Daniel Vetter930ebb42012-06-29 23:32:16 +02009326 ironlake_teardown_rc6(dev);
9327
Jesse Barnes57f350b2012-03-28 13:39:25 -07009328 if (IS_VALLEYVIEW(dev))
9329 vlv_init_dpio(dev);
9330
Kristian Høgsberg69341a52009-11-11 12:19:17 -05009331 mutex_unlock(&dev->struct_mutex);
9332
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009333 /* Disable the irq before mode object teardown, for the irq might
9334 * enqueue unpin/hotplug work. */
9335 drm_irq_uninstall(dev);
9336 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02009337 cancel_work_sync(&dev_priv->rps.work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009338
Chris Wilson1630fe72011-07-08 12:22:42 +01009339 /* flush any delayed tasks or pending work */
9340 flush_scheduled_work();
9341
Jesse Barnes79e53942008-11-07 14:24:08 -08009342 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +01009343
9344 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009345}
9346
Dave Airlie28d52042009-09-21 14:33:58 +10009347/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08009348 * Return which encoder is currently attached for connector.
9349 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01009350struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08009351{
Chris Wilsondf0e9242010-09-09 16:20:55 +01009352 return &intel_attached_encoder(connector)->base;
9353}
Jesse Barnes79e53942008-11-07 14:24:08 -08009354
Chris Wilsondf0e9242010-09-09 16:20:55 +01009355void intel_connector_attach_encoder(struct intel_connector *connector,
9356 struct intel_encoder *encoder)
9357{
9358 connector->encoder = encoder;
9359 drm_mode_connector_attach_encoder(&connector->base,
9360 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009361}
Dave Airlie28d52042009-09-21 14:33:58 +10009362
9363/*
9364 * set vga decode state - true == enable VGA decode
9365 */
9366int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9367{
9368 struct drm_i915_private *dev_priv = dev->dev_private;
9369 u16 gmch_ctrl;
9370
9371 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9372 if (state)
9373 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9374 else
9375 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9376 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9377 return 0;
9378}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009379
9380#ifdef CONFIG_DEBUG_FS
9381#include <linux/seq_file.h>
9382
9383struct intel_display_error_state {
9384 struct intel_cursor_error_state {
9385 u32 control;
9386 u32 position;
9387 u32 base;
9388 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +01009389 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009390
9391 struct intel_pipe_error_state {
9392 u32 conf;
9393 u32 source;
9394
9395 u32 htotal;
9396 u32 hblank;
9397 u32 hsync;
9398 u32 vtotal;
9399 u32 vblank;
9400 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +01009401 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009402
9403 struct intel_plane_error_state {
9404 u32 control;
9405 u32 stride;
9406 u32 size;
9407 u32 pos;
9408 u32 addr;
9409 u32 surface;
9410 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +01009411 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009412};
9413
9414struct intel_display_error_state *
9415intel_display_capture_error_state(struct drm_device *dev)
9416{
Akshay Joshi0206e352011-08-16 15:34:10 -04009417 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009418 struct intel_display_error_state *error;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009419 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009420 int i;
9421
9422 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9423 if (error == NULL)
9424 return NULL;
9425
Damien Lespiau52331302012-08-15 19:23:25 +01009426 for_each_pipe(i) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009427 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9428
Paulo Zanonia18c4c32013-03-06 20:03:12 -03009429 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9430 error->cursor[i].control = I915_READ(CURCNTR(i));
9431 error->cursor[i].position = I915_READ(CURPOS(i));
9432 error->cursor[i].base = I915_READ(CURBASE(i));
9433 } else {
9434 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9435 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9436 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9437 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009438
9439 error->plane[i].control = I915_READ(DSPCNTR(i));
9440 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -03009441 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -03009442 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -03009443 error->plane[i].pos = I915_READ(DSPPOS(i));
9444 }
Paulo Zanonica291362013-03-06 20:03:14 -03009445 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9446 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009447 if (INTEL_INFO(dev)->gen >= 4) {
9448 error->plane[i].surface = I915_READ(DSPSURF(i));
9449 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9450 }
9451
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009452 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009453 error->pipe[i].source = I915_READ(PIPESRC(i));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02009454 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9455 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9456 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9457 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9458 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9459 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009460 }
9461
9462 return error;
9463}
9464
9465void
9466intel_display_print_error_state(struct seq_file *m,
9467 struct drm_device *dev,
9468 struct intel_display_error_state *error)
9469{
9470 int i;
9471
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009472 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Damien Lespiau52331302012-08-15 19:23:25 +01009473 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009474 seq_printf(m, "Pipe [%d]:\n", i);
9475 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9476 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9477 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9478 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9479 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9480 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9481 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9482 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9483
9484 seq_printf(m, "Plane [%d]:\n", i);
9485 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9486 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -03009487 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -03009488 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
Paulo Zanoni80ca3782013-03-22 14:20:57 -03009489 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9490 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -03009491 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Paulo Zanonica291362013-03-06 20:03:14 -03009492 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009493 if (INTEL_INFO(dev)->gen >= 4) {
9494 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9495 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9496 }
9497
9498 seq_printf(m, "Cursor [%d]:\n", i);
9499 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9500 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9501 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9502 }
9503}
9504#endif