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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 46dcb57e18884099ca6ad2aebb81fd7e1513c1f6 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 5c09db28607341259474715e8833346c735e035d [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]29#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]30#include "llvm/Support/MathExtras.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]31using namespace llvm;
32
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]33namespace llvm {
34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
40
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
44 else
45 return TLSModel::GeneralDynamic;
46 } else {
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
49 else
50 return TLSModel::InitialExec;
51 }
52}
53}
54
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]55/// InitLibcallNames - Set default libcall names.
56///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]57static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]58 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]61 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]62 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]65 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]66 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]69 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]70 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]74 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]75 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]76 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]79 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]80 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]81 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]84 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]85 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]86 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]89 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]90 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]91 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]94 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]99 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]103 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]107 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]115 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]116 Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]297}
298
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]299/// InitLibcallCallingConvs - Set default libcall CallingConvs.
300///
301static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
303 CCs[i] = CallingConv::C;
304 }
305}
306
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]307/// getFPEXT - Return the FPEXT_*_* value for the given types, or
308/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]310 if (OpVT == MVT::f32) {
311 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]312 return FPEXT_F32_F64;
313 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]314
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]315 return UNKNOWN_LIBCALL;
316}
317
318/// getFPROUND - Return the FPROUND_*_* value for the given types, or
319/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]321 if (RetVT == MVT::f32) {
322 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]323 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]324 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]325 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]326 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]327 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]328 } else if (RetVT == MVT::f64) {
329 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]330 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]331 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]332 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]333 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]334
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]335 return UNKNOWN_LIBCALL;
336}
337
338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
339/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]341 if (OpVT == MVT::f32) {
342 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]343 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]344 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]345 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]346 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]347 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]348 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]349 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]351 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]352 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]353 if (RetVT == MVT::i8)
354 return FPTOSINT_F64_I8;
355 if (RetVT == MVT::i16)
356 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]358 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]359 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]360 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]361 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]363 } else if (OpVT == MVT::f80) {
364 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]365 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]366 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]367 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]368 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]369 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 } else if (OpVT == MVT::ppcf128) {
371 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]372 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]374 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_PPCF128_I128;
377 }
378 return UNKNOWN_LIBCALL;
379}
380
381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
382/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]384 if (OpVT == MVT::f32) {
385 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]386 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]387 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]388 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]389 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]390 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]391 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]392 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]393 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]396 if (RetVT == MVT::i8)
397 return FPTOUINT_F64_I8;
398 if (RetVT == MVT::i16)
399 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]400 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]406 } else if (OpVT == MVT::f80) {
407 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]408 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]409 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]410 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]411 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]412 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 } else if (OpVT == MVT::ppcf128) {
414 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]415 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]417 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_PPCF128_I128;
420 }
421 return UNKNOWN_LIBCALL;
422}
423
424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
425/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]427 if (OpVT == MVT::i32) {
428 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]429 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]430 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]431 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]432 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]433 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]434 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]435 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]436 } else if (OpVT == MVT::i64) {
437 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]438 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]439 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]440 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]441 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]442 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]443 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 } else if (OpVT == MVT::i128) {
446 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]447 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]448 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]449 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]451 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]452 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]453 return SINTTOFP_I128_PPCF128;
454 }
455 return UNKNOWN_LIBCALL;
456}
457
458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
459/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]461 if (OpVT == MVT::i32) {
462 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]463 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]464 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]465 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]466 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]469 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]470 } else if (OpVT == MVT::i64) {
471 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]472 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]473 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]474 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]475 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]478 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]479 } else if (OpVT == MVT::i128) {
480 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]481 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]482 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]483 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]484 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]485 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]486 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]487 return UINTTOFP_I128_PPCF128;
488 }
489 return UNKNOWN_LIBCALL;
490}
491
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]492/// InitCmpLibcallCCs - Set default comparison libcall CC.
493///
494static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
498 CCs[RTLIB::UNE_F32] = ISD::SETNE;
499 CCs[RTLIB::UNE_F64] = ISD::SETNE;
500 CCs[RTLIB::OGE_F32] = ISD::SETGE;
501 CCs[RTLIB::OGE_F64] = ISD::SETGE;
502 CCs[RTLIB::OLT_F32] = ISD::SETLT;
503 CCs[RTLIB::OLT_F64] = ISD::SETLT;
504 CCs[RTLIB::OLE_F32] = ISD::SETLE;
505 CCs[RTLIB::OLE_F64] = ISD::SETLE;
506 CCs[RTLIB::OGT_F32] = ISD::SETGT;
507 CCs[RTLIB::OGT_F64] = ISD::SETGT;
508 CCs[RTLIB::UO_F32] = ISD::SETNE;
509 CCs[RTLIB::UO_F64] = ISD::SETNE;
510 CCs[RTLIB::O_F32] = ISD::SETEQ;
511 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]512}
513
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]514/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]515TargetLowering::TargetLowering(const TargetMachine &tm,
516 const TargetLoweringObjectFile *tlof)
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]518 // All operations default to being supported.
519 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]520 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]523 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]524
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]525 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]527 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]528 for (unsigned IM = (unsigned)ISD::PRE_INC;
529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]532 }
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]533
534 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]537 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]538
539 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]541
542 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]543 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]544 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]548
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]549 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]550 setOperationAction(ISD::FLOG , MVT::f64, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
552 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
553 setOperationAction(ISD::FEXP , MVT::f64, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
555 setOperationAction(ISD::FLOG , MVT::f32, Expand);
556 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
557 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
558 setOperationAction(ISD::FEXP , MVT::f32, Expand);
559 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]560
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]561 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]562 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]563
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]564 IsLittleEndian = TD->isLittleEndian();
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]569 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]570 UseUnderscoreSetJmp = false;
571 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]572 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]573 IntDivIsCheap = false;
574 Pow2DivIsCheap = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]575 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]576 ExceptionPointerRegister = 0;
577 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]578 BooleanContents = UndefinedBooleanContent;
Evan Cheng211ffa12010-05-19 20:19:50 +0000[diff] [blame]579 SchedPreferenceInfo = Sched::Latency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]580 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]581 JumpBufAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]582 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]583 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]584 ShouldFoldAtomicFences = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]585
586 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]587 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]588 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]589}
590
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]591TargetLowering::~TargetLowering() {
592 delete &TLOF;
593}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]594
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]595/// canOpTrap - Returns true if the operation can trap for the value type.
596/// VT must be a legal type.
597bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
598 assert(isTypeLegal(VT));
599 switch (Op) {
600 default:
601 return false;
602 case ISD::FDIV:
603 case ISD::FREM:
604 case ISD::SDIV:
605 case ISD::UDIV:
606 case ISD::SREM:
607 case ISD::UREM:
608 return true;
609 }
610}
611
612
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]613static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]614 unsigned &NumIntermediates,
615 EVT &RegisterVT,
616 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]617 // Figure out the right, legal destination reg to copy into.
618 unsigned NumElts = VT.getVectorNumElements();
619 MVT EltTy = VT.getVectorElementType();
620
621 unsigned NumVectorRegs = 1;
622
623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
624 // could break down into LHS/RHS like LegalizeDAG does.
625 if (!isPowerOf2_32(NumElts)) {
626 NumVectorRegs = NumElts;
627 NumElts = 1;
628 }
629
630 // Divide the input until we get to a supported size. This will always
631 // end with a scalar if the target doesn't support vectors.
632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
633 NumElts >>= 1;
634 NumVectorRegs <<= 1;
635 }
636
637 NumIntermediates = NumVectorRegs;
638
639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
640 if (!TLI->isTypeLegal(NewVT))
641 NewVT = EltTy;
642 IntermediateVT = NewVT;
643
644 EVT DestVT = TLI->getRegisterType(NewVT);
645 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]646 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]648
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]649 // Otherwise, promotion or legal types use the same number of registers as
650 // the vector decimated to the appropriate level.
651 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]652}
653
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame^]654/// isLegalRC - Return true if the value types that can be represented by the
655/// specified register class are all legal.
656bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
657 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
658 I != E; ++I) {
659 if (isTypeLegal(*I))
660 return true;
661 }
662 return false;
663}
664
665/// hasLegalSuperRegRegClasses - Return true if the specified register class
666/// has one or more super-reg register classes that are legal.
667bool TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) {
668 if (*RC->superregclasses_begin() == 0)
669 return false;
670 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
671 E = RC->superregclasses_end(); I != E; ++I) {
672 const TargetRegisterClass *RRC = *I;
673 if (isLegalRC(RRC))
674 return true;
675 }
676 return false;
677}
678
679/// findRepresentativeClass - Return the largest legal super-reg register class
680/// of the specified register class.
681const TargetRegisterClass *
682TargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) {
683 if (!RC) return 0;
684
685 const TargetRegisterClass *BestRC = RC;
686 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
687 E = RC->superregclasses_end(); I != E; ++I) {
688 const TargetRegisterClass *RRC = *I;
689 if (RRC->isASubClass() || !isLegalRC(RRC))
690 continue;
691 if (!hasLegalSuperRegRegClasses(RRC))
692 return RRC;
693 BestRC = RRC;
694 }
695 return BestRC;
696}
697
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]698/// computeRegisterProperties - Once all of the register classes are added,
699/// this allows us to compute derived properties we expose.
700void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]701 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]702 "Too many value types for ValueTypeActions to hold!");
703
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]704 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]705 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]706 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]707 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]708 }
709 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]710 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]711
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]712 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]713 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]714 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]715 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]716
717 // Every integer value type larger than this largest register takes twice as
718 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]719 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]720 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
721 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]722 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]723 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]724 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
725 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]726 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]727 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]728
729 // Inspect all of the ValueType's smaller than the largest integer
730 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]731 unsigned LegalIntReg = LargestIntReg;
732 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]733 IntReg >= (unsigned)MVT::i1; --IntReg) {
734 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]735 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]736 LegalIntReg = IntReg;
737 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]738 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]739 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]740 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]741 }
742 }
743
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]744 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]745 if (!isTypeLegal(MVT::ppcf128)) {
746 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
747 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
748 TransformToType[MVT::ppcf128] = MVT::f64;
749 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]750 }
751
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]752 // Decide how to handle f64. If the target does not have native f64 support,
753 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]754 if (!isTypeLegal(MVT::f64)) {
755 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
756 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
757 TransformToType[MVT::f64] = MVT::i64;
758 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]759 }
760
761 // Decide how to handle f32. If the target does not have native support for
762 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]763 if (!isTypeLegal(MVT::f32)) {
764 if (isTypeLegal(MVT::f64)) {
765 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
766 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
767 TransformToType[MVT::f32] = MVT::f64;
768 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]769 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]770 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
771 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
772 TransformToType[MVT::f32] = MVT::i32;
773 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]774 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]775 }
Nate Begeman4ef3b812005-11-22 01:29:36 +0000[diff] [blame]776
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]777 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]778 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
779 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]780 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]781 if (isTypeLegal(VT)) continue;
782
783 MVT IntermediateVT;
784 EVT RegisterVT;
785 unsigned NumIntermediates;
786 NumRegistersForVT[i] =
787 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
788 RegisterVT, this);
789 RegisterTypeForVT[i] = RegisterVT;
790
791 // Determine if there is a legal wider type.
792 bool IsLegalWiderType = false;
793 EVT EltVT = VT.getVectorElementType();
794 unsigned NElts = VT.getVectorNumElements();
795 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
796 EVT SVT = (MVT::SimpleValueType)nVT;
797 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
798 SVT.getVectorNumElements() > NElts && NElts != 1) {
799 TransformToType[i] = SVT;
800 ValueTypeActions.setTypeAction(VT, Promote);
801 IsLegalWiderType = true;
802 break;
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]803 }
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]804 }
805 if (!IsLegalWiderType) {
806 EVT NVT = VT.getPow2VectorType();
807 if (NVT == VT) {
808 // Type is already a power of 2. The default action is to split.
809 TransformToType[i] = MVT::Other;
810 ValueTypeActions.setTypeAction(VT, Expand);
811 } else {
812 TransformToType[i] = NVT;
813 ValueTypeActions.setTypeAction(VT, Promote);
Mon P Wang87c8a8f2008-12-18 20:03:17 +0000[diff] [blame]814 }
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]815 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]816 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame^]817
818 // Determine the 'representative' register class for each value type.
819 // An representative register class is the largest (meaning one which is
820 // not a sub-register class / subreg register class) legal register class for
821 // a group of value types. For example, on i386, i8, i16, and i32
822 // representative would be GR32; while on x86_64 it's GR64.
823 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
824 RepRegClassForVT[i] = findRepresentativeClass(RegClassForVT[i]);
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]825}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]826
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]827const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
828 return NULL;
829}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]830
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]831
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]832MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]833 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]834}
835
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]836MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
837 return MVT::i32; // return the default value
838}
839
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]840/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]841/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
842/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
843/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]844///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]845/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]846/// register. It also returns the VT and quantity of the intermediate values
847/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]848///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]849unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]850 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]851 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]852 EVT &RegisterVT) const {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]853 // Figure out the right, legal destination reg to copy into.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]854 unsigned NumElts = VT.getVectorNumElements();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]855 EVT EltTy = VT.getVectorElementType();
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]856
857 unsigned NumVectorRegs = 1;
858
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]859 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
860 // could break down into LHS/RHS like LegalizeDAG does.
861 if (!isPowerOf2_32(NumElts)) {
862 NumVectorRegs = NumElts;
863 NumElts = 1;
864 }
865
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]866 // Divide the input until we get to a supported size. This will always
867 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]868 while (NumElts > 1 && !isTypeLegal(
869 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]870 NumElts >>= 1;
871 NumVectorRegs <<= 1;
872 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]873
874 NumIntermediates = NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]875
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]876 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]877 if (!isTypeLegal(NewVT))
878 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]879 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]880
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]881 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]882 RegisterVT = DestVT;
Duncan Sands8e4eb092008-06-08 20:54:56 +0000[diff] [blame]883 if (DestVT.bitsLT(NewVT)) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]884 // Value is expanded, e.g. i64 -> i16.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]885 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]886 } else {
887 // Otherwise, promotion or legal types use the same number of registers as
888 // the vector decimated to the appropriate level.
Chris Lattner79227e22006-03-31 00:46:36 +0000[diff] [blame]889 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]890 }
891
Evan Chenge9b3da12006-05-17 18:10:06 +0000[diff] [blame]892 return 1;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]893}
894
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]895/// Get the EVTs and ArgFlags collections that represent the legalized return
896/// type of the given function. This does not require a DAG or a return value,
897/// and is suitable for use before any DAGs for the function are constructed.
898/// TODO: Move this out of TargetLowering.cpp.
899void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
900 SmallVectorImpl<ISD::OutputArg> &Outs,
901 const TargetLowering &TLI,
902 SmallVectorImpl<uint64_t> *Offsets) {
903 SmallVector<EVT, 4> ValueVTs;
904 ComputeValueVTs(TLI, ReturnType, ValueVTs);
905 unsigned NumValues = ValueVTs.size();
906 if (NumValues == 0) return;
907 unsigned Offset = 0;
908
909 for (unsigned j = 0, f = NumValues; j != f; ++j) {
910 EVT VT = ValueVTs[j];
911 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
912
913 if (attr & Attribute::SExt)
914 ExtendKind = ISD::SIGN_EXTEND;
915 else if (attr & Attribute::ZExt)
916 ExtendKind = ISD::ZERO_EXTEND;
917
918 // FIXME: C calling convention requires the return type to be promoted to
919 // at least 32-bit. But this is not necessary for non-C calling
920 // conventions. The frontend should mark functions whose return values
921 // require promoting with signext or zeroext attributes.
922 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
923 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
924 if (VT.bitsLT(MinVT))
925 VT = MinVT;
926 }
927
928 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
929 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
930 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
931 PartVT.getTypeForEVT(ReturnType->getContext()));
932
933 // 'inreg' on function refers to return value
934 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
935 if (attr & Attribute::InReg)
936 Flags.setInReg();
937
938 // Propagate extension type if any
939 if (attr & Attribute::SExt)
940 Flags.setSExt();
941 else if (attr & Attribute::ZExt)
942 Flags.setZExt();
943
944 for (unsigned i = 0; i < NumParts; ++i) {
945 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
946 if (Offsets) {
947 Offsets->push_back(Offset);
948 Offset += PartSize;
949 }
950 }
951 }
952}
953
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]954/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]955/// function arguments in the caller parameter area. This is the actual
956/// alignment, not its logarithm.
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]957unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]958 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]959}
960
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]961/// getJumpTableEncoding - Return the entry encoding for a jump table in the
962/// current function. The returned value is a member of the
963/// MachineJumpTableInfo::JTEntryKind enum.
964unsigned TargetLowering::getJumpTableEncoding() const {
965 // In non-pic modes, just use the address of a block.
966 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
967 return MachineJumpTableInfo::EK_BlockAddress;
968
969 // In PIC mode, if the target supports a GPRel32 directive, use it.
970 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
971 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
972
973 // Otherwise, use a label difference.
974 return MachineJumpTableInfo::EK_LabelDifference32;
975}
976
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]977SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
978 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]979 // If our PIC model is GP relative, use the global offset table as the base.
980 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]981 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]982 return Table;
983}
984
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]985/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
986/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
987/// MCExpr.
988const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]989TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
990 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]991 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]992 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]993}
994
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]995bool
996TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
997 // Assume that everything is safe in static mode.
998 if (getTargetMachine().getRelocationModel() == Reloc::Static)
999 return true;
1000
1001 // In dynamic-no-pic mode, assume that known defined values are safe.
1002 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1003 GA &&
1004 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1005 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1006 return true;
1007
1008 // Otherwise assume nothing is safe.
1009 return false;
1010}
1011
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1012//===----------------------------------------------------------------------===//
1013// Optimization Methods
1014//===----------------------------------------------------------------------===//
1015
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1016/// ShrinkDemandedConstant - Check to see if the specified operand of the
1017/// specified instruction is a constant integer. If so, check to see if there
1018/// are any bits set in the constant that are not demanded. If so, shrink the
1019/// constant and return true.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1020bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1021 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1022 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1023
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1024 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1025 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1026 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1027 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1028 case ISD::AND:
1029 case ISD::OR: {
1030 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1031 if (!C) return false;
1032
1033 if (Op.getOpcode() == ISD::XOR &&
1034 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1035 return false;
1036
1037 // if we can expand it to have all bits set, do it
1038 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1039 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1040 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1041 DAG.getConstant(Demanded &
1042 C->getAPIntValue(),
1043 VT));
1044 return CombineTo(Op, New);
1045 }
1046
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1047 break;
1048 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1049 }
1050
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1051 return false;
1052}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1053
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1054/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1055/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1056/// cast, but it could be generalized for targets with other types of
1057/// implicit widening casts.
1058bool
1059TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1060 unsigned BitWidth,
1061 const APInt &Demanded,
1062 DebugLoc dl) {
1063 assert(Op.getNumOperands() == 2 &&
1064 "ShrinkDemandedOp only supports binary operators!");
1065 assert(Op.getNode()->getNumValues() == 1 &&
1066 "ShrinkDemandedOp only supports nodes with one result!");
1067
1068 // Don't do this if the node has another user, which may require the
1069 // full value.
1070 if (!Op.getNode()->hasOneUse())
1071 return false;
1072
1073 // Search for the smallest integer type with free casts to and from
1074 // Op's type. For expedience, just check power-of-2 integer types.
1075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1076 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1077 if (!isPowerOf2_32(SmallVTBits))
1078 SmallVTBits = NextPowerOf2(SmallVTBits);
1079 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1080 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1081 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1082 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1083 // We found a type with free casts.
1084 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1085 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1086 Op.getNode()->getOperand(0)),
1087 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1088 Op.getNode()->getOperand(1)));
1089 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1090 return CombineTo(Op, Z);
1091 }
1092 }
1093 return false;
1094}
1095
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1096/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1097/// DemandedMask bits of the result of Op are ever used downstream. If we can
1098/// use this information to simplify Op, create a new simplified DAG node and
1099/// return true, returning the original and new nodes in Old and New. Otherwise,
1100/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1101/// the expression (used to simplify the caller). The KnownZero/One bits may
1102/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1103bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1104 const APInt &DemandedMask,
1105 APInt &KnownZero,
1106 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1107 TargetLoweringOpt &TLO,
1108 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1109 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1110 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1111 "Mask size mismatches value type size!");
1112 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1113 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1114
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1115 // Don't know anything.
1116 KnownZero = KnownOne = APInt(BitWidth, 0);
1117
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1118 // Other users may use these bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1119 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1120 if (Depth != 0) {
1121 // If not at the root, Just compute the KnownZero/KnownOne bits to
1122 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1123 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1124 return false;
1125 }
1126 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1127 // just set the NewMask to all bits.
1128 NewMask = APInt::getAllOnesValue(BitWidth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1129 } else if (DemandedMask == 0) {
1130 // Not demanding any bits from Op.
1131 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1132 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1133 return false;
1134 } else if (Depth == 6) { // Limit search depth.
1135 return false;
1136 }
1137
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1138 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1139 switch (Op.getOpcode()) {
1140 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1141 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1142 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1143 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1144 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1145 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1146 // If the RHS is a constant, check to see if the LHS would be zero without
1147 // using the bits from the RHS. Below, we use knowledge about the RHS to
1148 // simplify the LHS, here we're using information from the LHS to simplify
1149 // the RHS.
1150 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1151 APInt LHSZero, LHSOne;
1152 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1153 LHSZero, LHSOne, Depth+1);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1154 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1155 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1156 return TLO.CombineTo(Op, Op.getOperand(0));
1157 // If any of the set bits in the RHS are known zero on the LHS, shrink
1158 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1159 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1160 return true;
1161 }
1162
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1163 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1164 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1165 return true;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1166 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1167 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1168 KnownZero2, KnownOne2, TLO, Depth+1))
1169 return true;
1170 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1171
1172 // If all of the demanded bits are known one on one side, return the other.
1173 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1174 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1175 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1176 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1177 return TLO.CombineTo(Op, Op.getOperand(1));
1178 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1179 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1180 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1181 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1182 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1183 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1184 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1185 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1186 return true;
1187
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1188 // Output known-1 bits are only known if set in both the LHS & RHS.
1189 KnownOne &= KnownOne2;
1190 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1191 KnownZero |= KnownZero2;
1192 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1193 case ISD::OR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1194 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1195 KnownOne, TLO, Depth+1))
1196 return true;
1197 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1198 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1199 KnownZero2, KnownOne2, TLO, Depth+1))
1200 return true;
1201 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1202
1203 // If all of the demanded bits are known zero on one side, return the other.
1204 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1205 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1206 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1207 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1208 return TLO.CombineTo(Op, Op.getOperand(1));
1209 // If all of the potentially set bits on one side are known to be set on
1210 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1211 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1212 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1213 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1214 return TLO.CombineTo(Op, Op.getOperand(1));
1215 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1216 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1217 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1218 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1219 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1220 return true;
1221
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222 // Output known-0 bits are only known if clear in both the LHS & RHS.
1223 KnownZero &= KnownZero2;
1224 // Output known-1 are known to be set if set in either the LHS | RHS.
1225 KnownOne |= KnownOne2;
1226 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1227 case ISD::XOR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1229 KnownOne, TLO, Depth+1))
1230 return true;
1231 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1232 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1233 KnownOne2, TLO, Depth+1))
1234 return true;
1235 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1236
1237 // If all of the demanded bits are known zero on one side, return the other.
1238 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1239 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1240 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1241 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1242 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1243 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1244 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1245 return true;
1246
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1247 // If all of the unknown bits are known to be zero on one side or the other
1248 // (but not both) turn this into an *inclusive* or.
1249 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1250 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1251 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1252 Op.getOperand(0),
1253 Op.getOperand(1)));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1254
1255 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1256 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1257 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1258 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1259
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1260 // If all of the demanded bits on one side are known, and all of the set
1261 // bits on that side are also known to be set on the other side, turn this
1262 // into an AND, as we know the bits will be cleared.
1263 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1264 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1265 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1266 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1267 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1268 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1269 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1270 }
1271 }
1272
1273 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1274 // for XOR, we prefer to force bits to 1 if they will make a -1.
1275 // if we can't force bits, try to shrink constant
1276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1277 APInt Expanded = C->getAPIntValue() | (~NewMask);
1278 // if we can expand it to have all bits set, do it
1279 if (Expanded.isAllOnesValue()) {
1280 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1281 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1282 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1283 TLO.DAG.getConstant(Expanded, VT));
1284 return TLO.CombineTo(Op, New);
1285 }
1286 // if it already has all the bits set, nothing to change
1287 // but don't shrink either!
1288 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1289 return true;
1290 }
1291 }
1292
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1293 KnownZero = KnownZeroOut;
1294 KnownOne = KnownOneOut;
1295 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1296 case ISD::SELECT:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1297 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1298 KnownOne, TLO, Depth+1))
1299 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1300 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1301 KnownOne2, TLO, Depth+1))
1302 return true;
1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1304 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1305
1306 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1307 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1308 return true;
1309
1310 // Only known if known in both the LHS and RHS.
1311 KnownOne &= KnownOne2;
1312 KnownZero &= KnownZero2;
1313 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1314 case ISD::SELECT_CC:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1315 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1316 KnownOne, TLO, Depth+1))
1317 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1318 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1319 KnownOne2, TLO, Depth+1))
1320 return true;
1321 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1322 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1323
1324 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1325 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1326 return true;
1327
1328 // Only known if known in both the LHS and RHS.
1329 KnownOne &= KnownOne2;
1330 KnownZero &= KnownZero2;
1331 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1332 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1333 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1334 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1335 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1336
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1337 // If the shift count is an invalid immediate, don't do anything.
1338 if (ShAmt >= BitWidth)
1339 break;
1340
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1341 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1342 // single shift. We can do this if the bottom bits (which are shifted
1343 // out) are never demanded.
1344 if (InOp.getOpcode() == ISD::SRL &&
1345 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1346 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1347 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1348 unsigned Opc = ISD::SHL;
1349 int Diff = ShAmt-C1;
1350 if (Diff < 0) {
1351 Diff = -Diff;
1352 Opc = ISD::SRL;
1353 }
1354
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1355 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1356 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1357 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1358 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1359 InOp.getOperand(0), NewSA));
1360 }
1361 }
1362
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1363 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1364 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1365 return true;
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1366 KnownZero <<= SA->getZExtValue();
1367 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1368 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1369 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1370 }
1371 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1372 case ISD::SRL:
1373 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1374 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1375 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1376 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1377 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1378
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1379 // If the shift count is an invalid immediate, don't do anything.
1380 if (ShAmt >= BitWidth)
1381 break;
1382
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1383 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1384 // single shift. We can do this if the top bits (which are shifted out)
1385 // are never demanded.
1386 if (InOp.getOpcode() == ISD::SHL &&
1387 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1388 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1389 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1390 unsigned Opc = ISD::SRL;
1391 int Diff = ShAmt-C1;
1392 if (Diff < 0) {
1393 Diff = -Diff;
1394 Opc = ISD::SHL;
1395 }
1396
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1397 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1398 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1399 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1400 InOp.getOperand(0), NewSA));
1401 }
1402 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1403
1404 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1405 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1406 KnownZero, KnownOne, TLO, Depth+1))
1407 return true;
1408 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1409 KnownZero = KnownZero.lshr(ShAmt);
1410 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1411
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1412 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1413 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1414 }
1415 break;
1416 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1417 // If this is an arithmetic shift right and only the low-bit is set, we can
1418 // always convert this into a logical shr, even if the shift amount is
1419 // variable. The low bit of the shift cannot be an input sign bit unless
1420 // the shift amount is >= the size of the datatype, which is undefined.
1421 if (DemandedMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1422 return TLO.CombineTo(Op,
1423 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1424 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1425
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1426 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1427 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1428 unsigned ShAmt = SA->getZExtValue();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1429
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1430 // If the shift count is an invalid immediate, don't do anything.
1431 if (ShAmt >= BitWidth)
1432 break;
1433
1434 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1435
1436 // If any of the demanded bits are produced by the sign extension, we also
1437 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1438 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1439 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1440 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1441
1442 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1443 KnownZero, KnownOne, TLO, Depth+1))
1444 return true;
1445 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1446 KnownZero = KnownZero.lshr(ShAmt);
1447 KnownOne = KnownOne.lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1448
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1449 // Handle the sign bit, adjusted to where it is now in the mask.
1450 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1451
1452 // If the input sign bit is known to be zero, or if none of the top bits
1453 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1454 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1455 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1456 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1457 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1458 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1459 KnownOne |= HighBits;
1460 }
1461 }
1462 break;
1463 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1464 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1465
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1466 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1467 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1468 APInt NewBits =
1469 APInt::getHighBitsSet(BitWidth,
1470 BitWidth - EVT.getScalarType().getSizeInBits()) &
1471 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1472
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1473 // If none of the extended bits are demanded, eliminate the sextinreg.
1474 if (NewBits == 0)
1475 return TLO.CombineTo(Op, Op.getOperand(0));
1476
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1477 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1478 InSignBit.zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1479 APInt InputDemandedBits =
1480 APInt::getLowBitsSet(BitWidth,
1481 EVT.getScalarType().getSizeInBits()) &
1482 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1483
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1484 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1485 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1486 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1487
1488 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1489 KnownZero, KnownOne, TLO, Depth+1))
1490 return true;
1491 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1492
1493 // If the sign bit of the input is known set or clear, then we know the
1494 // top bits of the result.
1495
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1496 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1497 if (KnownZero.intersects(InSignBit))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1498 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1499 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1500
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1501 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1502 KnownOne |= NewBits;
1503 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1504 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1505 KnownZero &= ~NewBits;
1506 KnownOne &= ~NewBits;
1507 }
1508 break;
1509 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1510 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1511 unsigned OperandBitWidth =
1512 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1513 APInt InMask = NewMask;
1514 InMask.trunc(OperandBitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1515
1516 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1517 APInt NewBits =
1518 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1519 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1521 Op.getValueType(),
1522 Op.getOperand(0)));
1523
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1524 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1525 KnownZero, KnownOne, TLO, Depth+1))
1526 return true;
1527 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1528 KnownZero.zext(BitWidth);
1529 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1530 KnownZero |= NewBits;
1531 break;
1532 }
1533 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1534 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1535 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1536 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1537 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1538 APInt NewBits = ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1539
1540 // If none of the top bits are demanded, convert this into an any_extend.
1541 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1542 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1543 Op.getValueType(),
1544 Op.getOperand(0)));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1545
1546 // Since some of the sign extended bits are demanded, we know that the sign
1547 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1548 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1549 InDemandedBits |= InSignBit;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1550 InDemandedBits.trunc(InBits);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1551
1552 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1553 KnownOne, TLO, Depth+1))
1554 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1555 KnownZero.zext(BitWidth);
1556 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1557
1558 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1559 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1560 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1561 Op.getValueType(),
1562 Op.getOperand(0)));
1563
1564 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1565 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1566 KnownOne |= NewBits;
1567 KnownZero &= ~NewBits;
1568 } else { // Otherwise, top bits aren't known.
1569 KnownOne &= ~NewBits;
1570 KnownZero &= ~NewBits;
1571 }
1572 break;
1573 }
1574 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1575 unsigned OperandBitWidth =
1576 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1577 APInt InMask = NewMask;
1578 InMask.trunc(OperandBitWidth);
1579 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1580 KnownZero, KnownOne, TLO, Depth+1))
1581 return true;
1582 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1583 KnownZero.zext(BitWidth);
1584 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1585 break;
1586 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1587 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1588 // Simplify the input, using demanded bit information, and compute the known
1589 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1590 unsigned OperandBitWidth =
1591 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1592 APInt TruncMask = NewMask;
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1593 TruncMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1594 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1595 KnownZero, KnownOne, TLO, Depth+1))
1596 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1597 KnownZero.trunc(BitWidth);
1598 KnownOne.trunc(BitWidth);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1599
1600 // If the input is only used by this truncate, see if we can shrink it based
1601 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1602 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1603 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1604 switch (In.getOpcode()) {
1605 default: break;
1606 case ISD::SRL:
1607 // Shrink SRL by a constant if none of the high bits shifted in are
1608 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1609 if (TLO.LegalTypes() &&
1610 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1611 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1612 // undesirable.
1613 break;
1614 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1615 if (!ShAmt)
1616 break;
1617 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1618 OperandBitWidth - BitWidth);
1619 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1620 HighBits.trunc(BitWidth);
1621
1622 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1623 // None of the shifted in bits are needed. Add a truncate of the
1624 // shift input, then shift it.
1625 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1626 Op.getValueType(),
1627 In.getOperand(0));
1628 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1629 Op.getValueType(),
1630 NewTrunc,
1631 In.getOperand(1)));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1632 }
1633 break;
1634 }
1635 }
1636
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1637 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1638 break;
1639 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1640 case ISD::AssertZext: {
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1641 // Demand all the bits of the input that are demanded in the output.
1642 // The low bits are obvious; the high bits are demanded because we're
1643 // asserting that they're zero here.
1644 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1645 KnownZero, KnownOne, TLO, Depth+1))
1646 return true;
1647 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1648
1649 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1650 APInt InMask = APInt::getLowBitsSet(BitWidth,
1651 VT.getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1652 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1653 break;
1654 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1655 case ISD::BIT_CONVERT:
1656#if 0
1657 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1658 // is demanded, turn this into a FGETSIGN.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1659 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1660 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1661 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1662 // Only do this xform if FGETSIGN is valid or if before legalize.
1663 if (!TLO.AfterLegalize ||
1664 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1665 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1666 // place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1667 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1668 Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1669 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1670 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1671 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1672 Sign, ShAmt));
1673 }
1674 }
1675#endif
1676 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1677 case ISD::ADD:
1678 case ISD::MUL:
1679 case ISD::SUB: {
1680 // Add, Sub, and Mul don't demand any bits in positions beyond that
1681 // of the highest bit demanded of them.
1682 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1683 BitWidth - NewMask.countLeadingZeros());
1684 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1685 KnownOne2, TLO, Depth+1))
1686 return true;
1687 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1688 KnownOne2, TLO, Depth+1))
1689 return true;
1690 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1691 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1692 return true;
1693 }
1694 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1695 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1696 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1697 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1698 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1699 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1700
1701 // If we know the value of all of the demanded bits, return this as a
1702 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1703 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1704 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1705
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1706 return false;
1707}
1708
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1709/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1710/// in Mask are known to be either zero or one and return them in the
1711/// KnownZero/KnownOne bitsets.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1712void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1713 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1714 APInt &KnownZero,
1715 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1716 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1717 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1718 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1719 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1720 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1721 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1722 "Should use MaskedValueIsZero if you don't know whether Op"
1723 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1724 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1725}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1726
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1727/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1728/// targets that want to expose additional information about sign bits to the
1729/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1730unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1731 unsigned Depth) const {
1732 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1733 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1734 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1735 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1736 "Should use ComputeNumSignBits if you don't know whether Op"
1737 " is a target node!");
1738 return 1;
1739}
1740
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1741/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1742/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1743/// determine which bit is set.
1744///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1745static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1746 // A left-shift of a constant one will have exactly one bit set, because
1747 // shifting the bit off the end is undefined.
1748 if (Val.getOpcode() == ISD::SHL)
1749 if (ConstantSDNode *C =
1750 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1751 if (C->getAPIntValue() == 1)
1752 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1753
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1754 // Similarly, a right-shift of a constant sign-bit will have exactly
1755 // one bit set.
1756 if (Val.getOpcode() == ISD::SRL)
1757 if (ConstantSDNode *C =
1758 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1759 if (C->getAPIntValue().isSignBit())
1760 return true;
1761
1762 // More could be done here, though the above checks are enough
1763 // to handle some common cases.
1764
1765 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1766 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1767 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1768 APInt Mask = APInt::getAllOnesValue(BitWidth);
1769 APInt KnownZero, KnownOne;
1770 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1771 return (KnownZero.countPopulation() == BitWidth - 1) &&
1772 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1773}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1774
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1775/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1776/// and cc. If it is unable to simplify it, return a null SDValue.
1777SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1778TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1779 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1780 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1781 SelectionDAG &DAG = DCI.DAG;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1782 LLVMContext &Context = *DAG.getContext();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1783
1784 // These setcc operations always fold.
1785 switch (Cond) {
1786 default: break;
1787 case ISD::SETFALSE:
1788 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1789 case ISD::SETTRUE:
1790 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1791 }
1792
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1793 if (isa<ConstantSDNode>(N0.getNode())) {
1794 // Ensure that the constant occurs on the RHS, and fold constant
1795 // comparisons.
1796 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1797 }
1798
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1799 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1800 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1801
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1802 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1803 // equality comparison, then we're just comparing whether X itself is
1804 // zero.
1805 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1806 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1807 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1808 const APInt &ShAmt
1809 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1810 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1811 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1812 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1813 // (srl (ctlz x), 5) == 0 -> X != 0
1814 // (srl (ctlz x), 5) != 1 -> X != 0
1815 Cond = ISD::SETNE;
1816 } else {
1817 // (srl (ctlz x), 5) != 0 -> X == 0
1818 // (srl (ctlz x), 5) == 1 -> X == 0
1819 Cond = ISD::SETEQ;
1820 }
1821 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1822 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1823 Zero, Cond);
1824 }
1825 }
1826
1827 // If the LHS is '(and load, const)', the RHS is 0,
1828 // the test is for equality or unsigned, and all 1 bits of the const are
1829 // in the same partial word, see if we can shorten the load.
1830 if (DCI.isBeforeLegalize() &&
1831 N0.getOpcode() == ISD::AND && C1 == 0 &&
1832 N0.getNode()->hasOneUse() &&
1833 isa<LoadSDNode>(N0.getOperand(0)) &&
1834 N0.getOperand(0).getNode()->hasOneUse() &&
1835 isa<ConstantSDNode>(N0.getOperand(1))) {
1836 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1837 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1838 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1839 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1840 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1841 unsigned maskWidth = origWidth;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1842 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1843 // 8 bits, but have to be careful...
1844 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1845 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1846 const APInt &Mask =
1847 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1848 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1849 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1850 for (unsigned offset=0; offset<origWidth/width; offset++) {
1851 if ((newMask & Mask) == Mask) {
1852 if (!TD->isLittleEndian())
1853 bestOffset = (origWidth/width - offset - 1) * (width/8);
1854 else
1855 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1856 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1857 bestWidth = width;
1858 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1859 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1860 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1861 }
1862 }
1863 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1864 if (bestWidth) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1865 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1866 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1867 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1868 SDValue Ptr = Lod->getBasePtr();
1869 if (bestOffset != 0)
1870 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1871 DAG.getConstant(bestOffset, PtrType));
1872 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1873 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1874 Lod->getSrcValue(),
1875 Lod->getSrcValueOffset() + bestOffset,
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]1876 false, false, NewAlign);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1877 return DAG.getSetCC(dl, VT,
1878 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1879 DAG.getConstant(bestMask.trunc(bestWidth),
1880 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1881 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1882 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1883 }
1884 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1885
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1886 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1887 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1888 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1889
1890 // If the comparison constant has bits in the upper part, the
1891 // zero-extended value could never match.
1892 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1893 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1894 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1895 case ISD::SETUGT:
1896 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1897 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1898 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1899 case ISD::SETULE:
1900 case ISD::SETNE: return DAG.getConstant(1, VT);
1901 case ISD::SETGT:
1902 case ISD::SETGE:
1903 // True if the sign bit of C1 is set.
1904 return DAG.getConstant(C1.isNegative(), VT);
1905 case ISD::SETLT:
1906 case ISD::SETLE:
1907 // True if the sign bit of C1 isn't set.
1908 return DAG.getConstant(C1.isNonNegative(), VT);
1909 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]1910 break;
1911 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1912 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1913
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1914 // Otherwise, we can perform the comparison with the low bits.
1915 switch (Cond) {
1916 case ISD::SETEQ:
1917 case ISD::SETNE:
1918 case ISD::SETUGT:
1919 case ISD::SETUGE:
1920 case ISD::SETULT:
1921 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1922 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1923 if (DCI.isBeforeLegalizeOps() ||
1924 (isOperationLegal(ISD::SETCC, newVT) &&
1925 getCondCodeAction(Cond, newVT)==Legal))
1926 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1927 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1928 Cond);
1929 break;
1930 }
1931 default:
1932 break; // todo, be more careful with signed comparisons
1933 }
1934 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1935 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1936 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1937 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1938 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1939 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1940
1941 // If the extended part has any inconsistent bits, it cannot ever
1942 // compare equal. In other words, they have to be all ones or all
1943 // zeros.
1944 APInt ExtBits =
1945 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1946 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1947 return DAG.getConstant(Cond == ISD::SETNE, VT);
1948
1949 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1950 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1951 if (Op0Ty == ExtSrcTy) {
1952 ZextOp = N0.getOperand(0);
1953 } else {
1954 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1955 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1956 DAG.getConstant(Imm, Op0Ty));
1957 }
1958 if (!DCI.isCalledByLegalizer())
1959 DCI.AddToWorklist(ZextOp.getNode());
1960 // Otherwise, make this a use of a zext.
1961 return DAG.getSetCC(dl, VT, ZextOp,
1962 DAG.getConstant(C1 & APInt::getLowBitsSet(
1963 ExtDstTyBits,
1964 ExtSrcTyBits),
1965 ExtDstTy),
1966 Cond);
1967 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1968 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1969 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1970 if (N0.getOpcode() == ISD::SETCC &&
1971 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1972 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1973 if (TrueWhenTrue)
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1974 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1975 // Invert the condition.
1976 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1977 CC = ISD::getSetCCInverse(CC,
1978 N0.getOperand(0).getValueType().isInteger());
1979 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1980 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1981
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1982 if ((N0.getOpcode() == ISD::XOR ||
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1983 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1984 N0.getOperand(0).getOpcode() == ISD::XOR &&
1985 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1986 isa<ConstantSDNode>(N0.getOperand(1)) &&
1987 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1988 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1989 // can only do this if the top bits are known zero.
1990 unsigned BitWidth = N0.getValueSizeInBits();
1991 if (DAG.MaskedValueIsZero(N0,
1992 APInt::getHighBitsSet(BitWidth,
1993 BitWidth-1))) {
1994 // Okay, get the un-inverted input value.
1995 SDValue Val;
1996 if (N0.getOpcode() == ISD::XOR)
1997 Val = N0.getOperand(0);
1998 else {
1999 assert(N0.getOpcode() == ISD::AND &&
2000 N0.getOperand(0).getOpcode() == ISD::XOR);
2001 // ((X^1)&1)^1 -> X & 1
2002 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2003 N0.getOperand(0).getOperand(0),
2004 N0.getOperand(1));
2005 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2006
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2007 return DAG.getSetCC(dl, VT, Val, N1,
2008 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2009 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2010 } else if (N1C->getAPIntValue() == 1 &&
2011 (VT == MVT::i1 ||
2012 getBooleanContents() == ZeroOrOneBooleanContent)) {
2013 SDValue Op0 = N0;
2014 if (Op0.getOpcode() == ISD::TRUNCATE)
2015 Op0 = Op0.getOperand(0);
2016
2017 if ((Op0.getOpcode() == ISD::XOR) &&
2018 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2019 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2020 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2021 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2022 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2023 Cond);
2024 } else if (Op0.getOpcode() == ISD::AND &&
2025 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2026 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2027 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2028 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2029 Op0 = DAG.getNode(ISD::AND, dl, VT,
2030 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2031 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2032 else if (Op0.getValueType().bitsLT(VT))
2033 Op0 = DAG.getNode(ISD::AND, dl, VT,
2034 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2035 DAG.getConstant(1, VT));
2036
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2037 return DAG.getSetCC(dl, VT, Op0,
2038 DAG.getConstant(0, Op0.getValueType()),
2039 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2040 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2041 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2042 }
2043
2044 APInt MinVal, MaxVal;
2045 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2046 if (ISD::isSignedIntSetCC(Cond)) {
2047 MinVal = APInt::getSignedMinValue(OperandBitSize);
2048 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2049 } else {
2050 MinVal = APInt::getMinValue(OperandBitSize);
2051 MaxVal = APInt::getMaxValue(OperandBitSize);
2052 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2053
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2054 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2055 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2056 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2057 // X >= C0 --> X > (C0-1)
2058 return DAG.getSetCC(dl, VT, N0,
2059 DAG.getConstant(C1-1, N1.getValueType()),
2060 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2061 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2062
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2063 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2064 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2065 // X <= C0 --> X < (C0+1)
2066 return DAG.getSetCC(dl, VT, N0,
2067 DAG.getConstant(C1+1, N1.getValueType()),
2068 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2069 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2070
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2071 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2072 return DAG.getConstant(0, VT); // X < MIN --> false
2073 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2074 return DAG.getConstant(1, VT); // X >= MIN --> true
2075 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2076 return DAG.getConstant(0, VT); // X > MAX --> false
2077 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2078 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2079
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2080 // Canonicalize setgt X, Min --> setne X, Min
2081 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2082 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2083 // Canonicalize setlt X, Max --> setne X, Max
2084 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2085 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2086
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2087 // If we have setult X, 1, turn it into seteq X, 0
2088 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2089 return DAG.getSetCC(dl, VT, N0,
2090 DAG.getConstant(MinVal, N0.getValueType()),
2091 ISD::SETEQ);
2092 // If we have setugt X, Max-1, turn it into seteq X, Max
2093 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2094 return DAG.getSetCC(dl, VT, N0,
2095 DAG.getConstant(MaxVal, N0.getValueType()),
2096 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2097
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2098 // If we have "setcc X, C0", check to see if we can shrink the immediate
2099 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2100
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2101 // SETUGT X, SINTMAX -> SETLT X, 0
2102 if (Cond == ISD::SETUGT &&
2103 C1 == APInt::getSignedMaxValue(OperandBitSize))
2104 return DAG.getSetCC(dl, VT, N0,
2105 DAG.getConstant(0, N1.getValueType()),
2106 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2107
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2108 // SETULT X, SINTMIN -> SETGT X, -1
2109 if (Cond == ISD::SETULT &&
2110 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2111 SDValue ConstMinusOne =
2112 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2113 N1.getValueType());
2114 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2115 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2116
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2117 // Fold bit comparisons when we can.
2118 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2119 (VT == N0.getValueType() ||
2120 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2121 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2122 if (ConstantSDNode *AndRHS =
2123 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2124 EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2125 getPointerTy() : getShiftAmountTy();
2126 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2127 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2128 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2129 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2130 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2131 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2132 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2133 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2134 // (X & 8) == 8 --> (X & 8) >> 3
2135 // Perform the xform if C1 is a single bit.
2136 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2137 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2138 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2139 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2140 }
2141 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2142 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2143 }
2144
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2145 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2146 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2147 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2148 if (O.getNode()) return O;
2149 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2150 // If the RHS of an FP comparison is a constant, simplify it away in
2151 // some cases.
2152 if (CFP->getValueAPF().isNaN()) {
2153 // If an operand is known to be a nan, we can fold it.
2154 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2155 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2156 case 0: // Known false.
2157 return DAG.getConstant(0, VT);
2158 case 1: // Known true.
2159 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2160 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2161 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2162 }
2163 }
2164
2165 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2166 // constant if knowing that the operand is non-nan is enough. We prefer to
2167 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2168 // materialize 0.0.
2169 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2170 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2171
2172 // If the condition is not legal, see if we can find an equivalent one
2173 // which is legal.
2174 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2175 // If the comparison was an awkward floating-point == or != and one of
2176 // the comparison operands is infinity or negative infinity, convert the
2177 // condition to a less-awkward <= or >=.
2178 if (CFP->getValueAPF().isInfinity()) {
2179 if (CFP->getValueAPF().isNegative()) {
2180 if (Cond == ISD::SETOEQ &&
2181 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2182 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2183 if (Cond == ISD::SETUEQ &&
2184 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2185 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2186 if (Cond == ISD::SETUNE &&
2187 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2188 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2189 if (Cond == ISD::SETONE &&
2190 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2191 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2192 } else {
2193 if (Cond == ISD::SETOEQ &&
2194 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2195 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2196 if (Cond == ISD::SETUEQ &&
2197 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2198 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2199 if (Cond == ISD::SETUNE &&
2200 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2201 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2202 if (Cond == ISD::SETONE &&
2203 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2204 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2205 }
2206 }
2207 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2208 }
2209
2210 if (N0 == N1) {
2211 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2212 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2213 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2214 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2215 if (UOF == 2) // FP operators that are undefined on NaNs.
2216 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2217 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2218 return DAG.getConstant(UOF, VT);
2219 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2220 // if it is not already.
2221 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2222 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2223 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2224 }
2225
2226 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2227 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2228 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2229 N0.getOpcode() == ISD::XOR) {
2230 // Simplify (X+Y) == (X+Z) --> Y == Z
2231 if (N0.getOpcode() == N1.getOpcode()) {
2232 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2233 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2234 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2235 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2236 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2237 // If X op Y == Y op X, try other combinations.
2238 if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2239 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2240 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2241 if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2242 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2243 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2244 }
2245 }
2246
2247 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2248 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2249 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2250 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2251 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2252 DAG.getConstant(RHSC->getAPIntValue()-
2253 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2254 N0.getValueType()), Cond);
2255 }
2256
2257 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2258 if (N0.getOpcode() == ISD::XOR)
2259 // If we know that all of the inverted bits are zero, don't bother
2260 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2261 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2262 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2263 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2264 DAG.getConstant(LHSR->getAPIntValue() ^
2265 RHSC->getAPIntValue(),
2266 N0.getValueType()),
2267 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2268 }
2269
2270 // Turn (C1-X) == C2 --> X == C1-C2
2271 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2272 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2273 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2274 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2275 DAG.getConstant(SUBC->getAPIntValue() -
2276 RHSC->getAPIntValue(),
2277 N0.getValueType()),
2278 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2279 }
2280 }
2281 }
2282
2283 // Simplify (X+Z) == X --> Z == 0
2284 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2285 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2286 DAG.getConstant(0, N0.getValueType()), Cond);
2287 if (N0.getOperand(1) == N1) {
2288 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2289 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2290 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2291 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2292 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2293 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2294 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2295 N1,
2296 DAG.getConstant(1, getShiftAmountTy()));
2297 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2298 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2299 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2300 }
2301 }
2302 }
2303
2304 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2305 N1.getOpcode() == ISD::XOR) {
2306 // Simplify X == (X+Z) --> Z == 0
2307 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2308 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2309 DAG.getConstant(0, N1.getValueType()), Cond);
2310 } else if (N1.getOperand(1) == N0) {
2311 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2312 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2313 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2314 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2315 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2316 // X == (Z-X) --> X<<1 == Z
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2317 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2318 DAG.getConstant(1, getShiftAmountTy()));
2319 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2320 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2321 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2322 }
2323 }
2324 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2325
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2326 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2327 // Note that where y is variable and is known to have at most
2328 // one bit set (for example, if it is z&1) we cannot do this;
2329 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2330 if (N0.getOpcode() == ISD::AND)
2331 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2332 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2333 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2334 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2335 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2336 }
2337 }
2338 if (N1.getOpcode() == ISD::AND)
2339 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2340 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2341 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2342 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2343 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2344 }
2345 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2346 }
2347
2348 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2349 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2350 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2351 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2352 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2353 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2354 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2355 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2356 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2357 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2358 break;
2359 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2360 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2361 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2362 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2363 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2364 Temp = DAG.getNOT(dl, N0, MVT::i1);
2365 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2366 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2367 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2368 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2369 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2370 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2371 Temp = DAG.getNOT(dl, N1, MVT::i1);
2372 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2373 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2374 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2375 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2376 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2377 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2378 Temp = DAG.getNOT(dl, N0, MVT::i1);
2379 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2380 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2381 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2382 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2383 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2384 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2385 Temp = DAG.getNOT(dl, N1, MVT::i1);
2386 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2387 break;
2388 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2389 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2390 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2391 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2392 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2393 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2394 }
2395 return N0;
2396 }
2397
2398 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2399 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2400}
2401
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2402/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2403/// node is a GlobalAddress + offset.
Dan Gohman46510a72010-04-15 01:51:59 +0000[diff] [blame]2404bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2405 int64_t &Offset) const {
2406 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2407 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2408 GA = GASD->getGlobal();
2409 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2410 return true;
2411 }
2412
2413 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2414 SDValue N1 = N->getOperand(0);
2415 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2416 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2417 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2418 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2419 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2420 return true;
2421 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2422 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2423 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2424 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2425 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2426 return true;
2427 }
2428 }
2429 }
2430 return false;
2431}
2432
2433
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2434SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2435PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2436 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2437 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2438}
2439
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2440//===----------------------------------------------------------------------===//
2441// Inline Assembler Implementation Methods
2442//===----------------------------------------------------------------------===//
2443
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2444
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2445TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2446TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2447 // FIXME: lots more standard ones to handle.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2448 if (Constraint.size() == 1) {
2449 switch (Constraint[0]) {
2450 default: break;
2451 case 'r': return C_RegisterClass;
2452 case 'm': // memory
2453 case 'o': // offsetable
2454 case 'V': // not offsetable
2455 return C_Memory;
2456 case 'i': // Simple Integer or Relocatable Constant
2457 case 'n': // Simple Integer
2458 case 's': // Relocatable Constant
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2459 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2460 case 'I': // Target registers.
2461 case 'J':
2462 case 'K':
2463 case 'L':
2464 case 'M':
2465 case 'N':
2466 case 'O':
2467 case 'P':
2468 return C_Other;
2469 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2470 }
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2471
2472 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2473 Constraint[Constraint.size()-1] == '}')
2474 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2475 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2476}
2477
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2478/// LowerXConstraint - try to replace an X constraint, which matches anything,
2479/// with another that has more specific requirements based on the type of the
2480/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2481const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2482 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2483 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2484 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2485 return "f"; // works for many targets
2486 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2487}
2488
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2489/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2490/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2491void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2492 char ConstraintLetter,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2493 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2494 SelectionDAG &DAG) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2495 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2496 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2497 case 'X': // Allows any operand; labels (basic block) use this.
2498 if (Op.getOpcode() == ISD::BasicBlock) {
2499 Ops.push_back(Op);
2500 return;
2501 }
2502 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2503 case 'i': // Simple Integer or Relocatable Constant
2504 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2505 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2506 // These operands are interested in values of the form (GV+C), where C may
2507 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2508 // is possible and fine if either GV or C are missing.
2509 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2510 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2511
2512 // If we have "(add GV, C)", pull out GV/C
2513 if (Op.getOpcode() == ISD::ADD) {
2514 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2515 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2516 if (C == 0 || GA == 0) {
2517 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2518 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2519 }
2520 if (C == 0 || GA == 0)
2521 C = 0, GA = 0;
2522 }
2523
2524 // If we find a valid operand, map to the TargetXXX version so that the
2525 // value itself doesn't get selected.
2526 if (GA) { // Either &GV or &GV+C
2527 if (ConstraintLetter != 'n') {
2528 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2529 if (C) Offs += C->getZExtValue();
Devang Patel0d881da2010-07-06 22:08:15 +0000[diff] [blame]2530 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2531 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2532 Op.getValueType(), Offs));
2533 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2534 }
2535 }
2536 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2537 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2538 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2539 // gcc prints these as sign extended. Sign extend value to 64 bits
2540 // now; without this it would get ZExt'd later in
2541 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2542 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2543 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2544 return;
2545 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2546 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2547 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2548 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2549 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2550}
2551
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2552std::vector<unsigned> TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2553getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2554 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2555 return std::vector<unsigned>();
2556}
2557
2558
2559std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2560getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2561 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2562 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2563 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2564 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2565
2566 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2567 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2568
2569 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2570 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2571 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2572 E = RI->regclass_end(); RCI != E; ++RCI) {
2573 const TargetRegisterClass *RC = *RCI;
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2574
Dan Gohmanf451cb82010-02-10 16:03:48 +0000[diff] [blame]2575 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2576 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2577 bool isLegal = false;
2578 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2579 I != E; ++I) {
2580 if (isTypeLegal(*I)) {
2581 isLegal = true;
2582 break;
2583 }
2584 }
2585
2586 if (!isLegal) continue;
2587
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2588 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2589 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2590 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2591 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2592 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2593 }
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2594
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2595 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2596}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2597
2598//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2599// Constraint Selection.
2600
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2601/// isMatchingInputConstraint - Return true of this is an input operand that is
2602/// a matching constraint like "4".
2603bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2604 assert(!ConstraintCode.empty() && "No known constraint!");
2605 return isdigit(ConstraintCode[0]);
2606}
2607
2608/// getMatchedOperand - If this is an input matching constraint, this method
2609/// returns the output operand it matches.
2610unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2611 assert(!ConstraintCode.empty() && "No known constraint!");
2612 return atoi(ConstraintCode.c_str());
2613}
2614
2615
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2616/// getConstraintGenerality - Return an integer indicating how general CT
2617/// is.
2618static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2619 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2620 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2621 case TargetLowering::C_Other:
2622 case TargetLowering::C_Unknown:
2623 return 0;
2624 case TargetLowering::C_Register:
2625 return 1;
2626 case TargetLowering::C_RegisterClass:
2627 return 2;
2628 case TargetLowering::C_Memory:
2629 return 3;
2630 }
2631}
2632
2633/// ChooseConstraint - If there are multiple different constraints that we
2634/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]2635/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2636/// Other -> immediates and magic values
2637/// Register -> one specific register
2638/// RegisterClass -> a group of regs
2639/// Memory -> memory
2640/// Ideally, we would pick the most specific constraint possible: if we have
2641/// something that fits into a register, we would pick it. The problem here
2642/// is that if we have something that could either be in a register or in
2643/// memory that use of the register could cause selection of *other*
2644/// operands to fail: they might only succeed if we pick memory. Because of
2645/// this the heuristic we use is:
2646///
2647/// 1) If there is an 'other' constraint, and if the operand is valid for
2648/// that constraint, use it. This makes us take advantage of 'i'
2649/// constraints when available.
2650/// 2) Otherwise, pick the most general constraint present. This prefers
2651/// 'm' over 'r', for example.
2652///
2653static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2654 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2655 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2656 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2657 unsigned BestIdx = 0;
2658 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2659 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2660
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2661 // Loop over the options, keeping track of the most general one.
2662 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2663 TargetLowering::ConstraintType CType =
2664 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2665
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2666 // If this is an 'other' constraint, see if the operand is valid for it.
2667 // For example, on X86 we might have an 'rI' constraint. If the operand
2668 // is an integer in the range [0..31] we want to use I (saving a load
2669 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2670 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2671 assert(OpInfo.Codes[i].size() == 1 &&
2672 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2673 std::vector<SDValue> ResultOps;
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2674 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2675 ResultOps, *DAG);
2676 if (!ResultOps.empty()) {
2677 BestType = CType;
2678 BestIdx = i;
2679 break;
2680 }
2681 }
2682
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2683 // Things with matching constraints can only be registers, per gcc
2684 // documentation. This mainly affects "g" constraints.
2685 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2686 continue;
2687
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2688 // This constraint letter is more general than the previous one, use it.
2689 int Generality = getConstraintGenerality(CType);
2690 if (Generality > BestGenerality) {
2691 BestType = CType;
2692 BestIdx = i;
2693 BestGenerality = Generality;
2694 }
2695 }
2696
2697 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2698 OpInfo.ConstraintType = BestType;
2699}
2700
2701/// ComputeConstraintToUse - Determines the constraint code and constraint
2702/// type to use for the specific AsmOperandInfo, setting
2703/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2704void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2705 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2706 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2707 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2708
2709 // Single-letter constraints ('r') are very common.
2710 if (OpInfo.Codes.size() == 1) {
2711 OpInfo.ConstraintCode = OpInfo.Codes[0];
2712 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2713 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2714 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2715 }
2716
2717 // 'X' matches anything.
2718 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2719 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2720 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]2721 // the result, which is not what we want to look at; leave them alone.
2722 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2723 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2724 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2725 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2726 }
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2727
2728 // Otherwise, try to resolve it to something we know about by looking at
2729 // the actual operand type.
2730 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2731 OpInfo.ConstraintCode = Repl;
2732 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2733 }
2734 }
2735}
2736
2737//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2738// Loop Strength Reduction hooks
2739//===----------------------------------------------------------------------===//
2740
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]2741/// isLegalAddressingMode - Return true if the addressing mode represented
2742/// by AM is legal for this target, for a load/store of the specified type.
2743bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2744 const Type *Ty) const {
2745 // The default implementation of this implements a conservative RISCy, r+r and
2746 // r+i addr mode.
2747
2748 // Allows a sign-extended 16-bit immediate field.
2749 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2750 return false;
2751
2752 // No global is ever allowed as a base.
2753 if (AM.BaseGV)
2754 return false;
2755
2756 // Only support r+r,
2757 switch (AM.Scale) {
2758 case 0: // "r+i" or just "i", depending on HasBaseReg.
2759 break;
2760 case 1:
2761 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2762 return false;
2763 // Otherwise we have r+r or r+i.
2764 break;
2765 case 2:
2766 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2767 return false;
2768 // Allow 2*r as r+r.
2769 break;
2770 }
2771
2772 return true;
2773}
2774
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2775/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2776/// return a DAG expression to select that will generate the same value by
2777/// multiplying by a magic number. See:
2778/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2779SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2780 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2781 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2782 DebugLoc dl= N->getDebugLoc();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2783
2784 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2785 // FIXME: We should be more aggressive here.
2786 if (!isTypeLegal(VT))
2787 return SDValue();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2788
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2789 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2790 APInt::ms magics = d.magic();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2791
2792 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2793 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2794 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2795 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2796 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2797 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2798 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2799 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2800 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2801 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2802 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2803 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2804 // If d > 0 and m < 0, add the numerator
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2805 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2806 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2807 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2808 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2809 }
2810 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2811 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2812 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2813 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2814 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2815 }
2816 // Shift right algebraic if shift value is nonzero
2817 if (magics.s > 0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2818 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2819 DAG.getConstant(magics.s, getShiftAmountTy()));
2820 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2821 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2822 }
2823 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2824 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2825 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2826 getShiftAmountTy()));
2827 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2828 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2829 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2830}
2831
2832/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2833/// return a DAG expression to select that will generate the same value by
2834/// multiplying by a magic number. See:
2835/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2836SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2837 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2838 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2839 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2840
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2841 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2842 // FIXME: We should be more aggressive here.
2843 if (!isTypeLegal(VT))
2844 return SDValue();
2845
2846 // FIXME: We should use a narrower constant when the upper
2847 // bits are known to be zero.
2848 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2849 APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2850
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2851 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2852 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2853 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2854 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2855 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2856 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2857 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2858 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2859 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2860 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2861 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2862 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2863 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2864 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2865
2866 if (magics.a == 0) {
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2867 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2868 "We shouldn't generate an undefined shift!");
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2869 return DAG.getNode(ISD::SRL, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2870 DAG.getConstant(magics.s, getShiftAmountTy()));
2871 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2872 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2873 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2874 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2875 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2876 DAG.getConstant(1, getShiftAmountTy()));
2877 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2878 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2879 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2880 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2881 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2882 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2883 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2884 }
2885}