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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Tejun Heo8c3d3d42013-05-14 11:09:50 -07004 * Maintained by: Tejun Heo <tj@kernel.org>
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04005 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020041#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050042#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090043#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090044#include <linux/gfp.h>
Robert Richteree2aad42015-06-05 19:49:25 +020045#include <linux/msi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010055 AHCI_PCI_BAR_STA2X11 = 0,
Robert Richterb7ae1282015-06-05 19:49:26 +020056 AHCI_PCI_BAR_CAVIUM = 0,
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -080057 AHCI_PCI_BAR_ENMOTUS = 2,
Alessandro Rubini318893e2012-01-06 13:33:39 +010058 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090059};
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Tejun Heo441577e2010-03-29 10:32:39 +090061enum board_ids {
62 /* board IDs by feature in alphabetical order */
63 board_ahci,
64 board_ahci_ign_iferr,
Tejun Heo66a7cbc2014-10-27 10:22:56 -040065 board_ahci_nomsi,
Levente Kurusa67809f82014-02-18 10:22:17 -050066 board_ahci_noncq,
Tejun Heo441577e2010-03-29 10:32:39 +090067 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020068 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090069
70 /* board IDs for specific chipsets in alphabetical order */
Dan Williamsdbfe8ef2015-05-08 15:23:55 -040071 board_ahci_avn,
Tejun Heo441577e2010-03-29 10:32:39 +090072 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090073 board_ahci_mcp77,
74 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090075 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090084 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085};
86
Jeff Garzik2dcb4072007-10-19 06:42:56 -040087static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Mika Westerberg02e53292016-02-18 10:54:17 +020088static void ahci_remove_one(struct pci_dev *dev);
Tejun Heoa1efdab2008-03-25 12:22:50 +090089static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
Dan Williamsdbfe8ef2015-05-08 15:23:55 -040091static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
James Lairdcb856962013-11-19 11:06:38 +110093static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
94static bool is_mcp89_apple(struct pci_dev *pdev);
Tejun Heoa1efdab2008-03-25 12:22:50 +090095static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
Mika Westerberg02e53292016-02-18 10:54:17 +020097#ifdef CONFIG_PM
98static int ahci_pci_device_runtime_suspend(struct device *dev);
99static int ahci_pci_device_runtime_resume(struct device *dev);
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200100#ifdef CONFIG_PM_SLEEP
101static int ahci_pci_device_suspend(struct device *dev);
102static int ahci_pci_device_resume(struct device *dev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900103#endif
Mika Westerberg02e53292016-02-18 10:54:17 +0200104#endif /* CONFIG_PM */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
Tejun Heofad16e72010-09-21 09:25:48 +0200106static struct scsi_host_template ahci_sht = {
107 AHCI_SHT("ahci"),
108};
109
Tejun Heo029cfd62008-03-25 12:22:49 +0900110static struct ata_port_operations ahci_vt8251_ops = {
111 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900112 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900113};
114
Tejun Heo029cfd62008-03-25 12:22:49 +0900115static struct ata_port_operations ahci_p5wdh_ops = {
116 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900117 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900118};
119
Dan Williamsdbfe8ef2015-05-08 15:23:55 -0400120static struct ata_port_operations ahci_avn_ops = {
121 .inherits = &ahci_ops,
122 .hardreset = ahci_avn_hardreset,
123};
124
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100125static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900126 /* by features */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530127 [board_ahci] = {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900128 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100129 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400130 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 .port_ops = &ahci_ops,
132 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530133 [board_ahci_ign_iferr] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900134 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
135 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100136 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400137 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900138 .port_ops = &ahci_ops,
139 },
Tejun Heo66a7cbc2014-10-27 10:22:56 -0400140 [board_ahci_nomsi] = {
141 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
Levente Kurusa67809f82014-02-18 10:22:17 -0500147 [board_ahci_noncq] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530154 [board_ahci_nosntf] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900155 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530161 [board_ahci_yes_fbs] = {
Tejun Heo5f173102010-07-24 16:53:48 +0200162 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
Tejun Heo441577e2010-03-29 10:32:39 +0900168 /* by chipsets */
Dan Williamsdbfe8ef2015-05-08 15:23:55 -0400169 [board_ahci_avn] = {
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_avn_ops,
174 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530175 [board_ahci_mcp65] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900176 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100178 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530183 [board_ahci_mcp77] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
189 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530190 [board_ahci_mcp89] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900191 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900192 .flags = AHCI_FLAG_COMMON,
193 .pio_mask = ATA_PIO4,
194 .udma_mask = ATA_UDMA6,
195 .port_ops = &ahci_ops,
196 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530197 [board_ahci_mv] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900198 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
199 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300200 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900201 .pio_mask = ATA_PIO4,
202 .udma_mask = ATA_UDMA6,
203 .port_ops = &ahci_ops,
204 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530205 [board_ahci_sb600] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900206 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900207 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
208 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900209 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100210 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400211 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800212 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800213 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530214 [board_ahci_sb700] = { /* for SB700 and SB800 */
Shane Huangbd172432008-06-10 15:52:04 +0800215 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800216 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100217 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800218 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800219 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800220 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530221 [board_ahci_vt8251] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900222 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900223 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100224 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900225 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900226 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800227 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228};
229
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500230static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400231 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400232 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
233 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
234 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
235 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
236 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900237 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400238 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
239 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
240 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
241 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900242 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800243 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900244 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
245 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
246 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
247 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
248 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
249 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
250 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
252 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
253 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
255 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
256 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
257 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
258 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400259 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
260 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800261 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500262 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800263 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500264 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
265 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700266 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700267 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500268 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700269 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700270 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500271 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Alexandra Yates342decf2016-02-05 15:27:49 -0800272 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800292 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
293 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
294 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
295 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
296 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
297 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700298 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
299 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
300 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800301 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800302 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700303 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
304 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
305 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
306 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
307 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
308 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700309 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Seth Heasleyea4ace62012-01-23 16:27:30 -0800310 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
311 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
312 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
313 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
314 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
316 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
317 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
James Ralston77b12bc92012-08-09 09:02:31 -0700318 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
319 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
320 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
322 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
323 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
324 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
Seth Heasley29e674d2013-01-25 12:01:05 -0800326 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
327 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
328 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
330 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
Dan Williamsdbfe8ef2015-05-08 15:23:55 -0400334 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
335 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
336 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
340 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
341 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
James Ralstonefda3322013-02-21 11:08:51 -0800342 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
James Ralston151743f2013-02-08 17:34:47 -0800344 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
345 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
349 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
350 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
Seth Heasley1cfc7df2013-06-19 16:36:45 -0700352 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
James Ralston9f961a52013-11-04 09:24:58 -0800353 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
354 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
James Ralston1b071a02014-08-27 14:29:07 -0700357 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
358 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
359 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
361 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
362 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
363 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
364 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
Devin Ryles249cd0a2014-11-07 17:59:05 -0500365 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
366 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
367 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
Charles_Rose@Dell.comc5967b72015-11-06 14:18:56 -0600368 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
James Ralston690000b2014-10-13 15:16:38 -0700369 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
James Ralston690000b2014-10-13 15:16:38 -0700370 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
Charles_Rose@Dell.comc5967b72015-11-06 14:18:56 -0600371 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
James Ralston690000b2014-10-13 15:16:38 -0700372 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
373 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
Alexandra Yates4d92f002015-11-16 11:22:16 -0500374 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
Alexandra Yatesf5bdd662016-02-17 19:36:20 -0800375 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
Alexandra Yates4d92f002015-11-16 11:22:16 -0500376 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
Alexandra Yatesf5bdd662016-02-17 19:36:20 -0800377 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
Alexandra Yates4d92f002015-11-16 11:22:16 -0500378 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
Alexandra Yates4d92f002015-11-16 11:22:16 -0500379 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
Alexandra Yatesf5bdd662016-02-17 19:36:20 -0800380 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
Alexandra Yates4d92f002015-11-16 11:22:16 -0500382 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
Alexandra Yates4d92f002015-11-16 11:22:16 -0500383 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
Alexandra Yatesf5bdd662016-02-17 19:36:20 -0800384 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400386
Tejun Heoe34bb372007-02-26 20:24:03 +0900387 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
388 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
389 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Ben Hutchings1fefb8f2012-09-10 01:09:04 +0100390 /* JMicron 362B and 362C have an AHCI function with IDE class code */
391 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
392 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
Zhang Rui91f15fb2015-08-24 15:27:11 -0500393 /* May need to update quirk_jmicron_async_suspend() for additions */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400394
395 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800396 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800397 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
398 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
399 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400403
Shane Huange2dd90b2009-07-29 11:34:49 +0800404 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800405 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huangfafe5c3d82013-06-03 18:24:10 +0800406 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
Shane Huange2dd90b2009-07-29 11:34:49 +0800407 /* AMD is using RAID class only for ahci controllers */
408 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
409 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
410
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400411 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400412 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900413 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400414
415 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900416 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900424 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400500
Jeff Garzik95916ed2006-07-29 04:10:14 -0400501 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900502 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
503 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
504 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400505
Alessandro Rubini318893e2012-01-06 13:33:39 +0100506 /* ST Microelectronics */
507 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
508
Jeff Garzikcd70c262007-07-08 02:29:42 -0400509 /* Marvell */
510 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100511 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600512 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500513 .class = PCI_CLASS_STORAGE_SATA_AHCI,
514 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200515 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600516 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
Per Jessen467b41c2011-02-08 13:54:32 +0100517 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Simon Guinote098f5c2013-12-23 13:24:35 +0100518 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
519 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
520 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600521 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
Matt Johnson642d8922012-04-27 01:42:30 -0500522 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
George Spelvinfcce9a32013-05-29 10:20:35 +0900523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
Murali Karicheric5edfff2014-09-05 13:21:00 -0400524 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
George Spelvinfcce9a32013-05-29 10:20:35 +0900526 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
Alan Cox17c60c62012-09-04 16:07:18 +0100528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
Andreas Schrägle754a2922014-05-24 16:35:43 +0200529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
530 .driver_data = board_ahci_yes_fbs },
Johannes Thumshirna40cf3f2015-10-20 09:31:22 +0200531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
532 .driver_data = board_ahci_yes_fbs },
Myron Stowe69fd3152013-04-08 11:32:49 -0600533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
Tejun Heo50be5e32010-11-29 15:57:14 +0100534 .driver_data = board_ahci_yes_fbs },
Samir Benmendil6d5278a2013-11-17 23:56:17 +0100535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
536 .driver_data = board_ahci_yes_fbs },
Jérôme Carreterod2518362014-06-03 14:56:25 -0400537 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
538 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400539
Mark Nelsonc77a0362008-10-23 14:08:16 +1100540 /* Promise */
541 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
Romain Degezb32bfc02014-07-11 18:08:13 +0200542 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
Mark Nelsonc77a0362008-10-23 14:08:16 +1100543
Keng-Yu Linc9703762011-11-09 01:47:36 -0500544 /* Asmedia */
Alan Cox7b4f6ec2012-09-04 16:25:25 +0100545 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
546 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
547 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
548 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
Keng-Yu Linc9703762011-11-09 01:47:36 -0500549
Levente Kurusa67809f82014-02-18 10:22:17 -0500550 /*
Tejun Heo66a7cbc2014-10-27 10:22:56 -0400551 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
552 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
Levente Kurusa67809f82014-02-18 10:22:17 -0500553 */
Tejun Heo66a7cbc2014-10-27 10:22:56 -0400554 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
Tejun Heo2b21ef02014-12-04 13:13:28 -0500555 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
Levente Kurusa67809f82014-02-18 10:22:17 -0500556
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -0800557 /* Enmotus */
558 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
559
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500560 /* Generic, PCI class code for AHCI */
561 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500562 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564 { } /* terminate list */
565};
566
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200567static const struct dev_pm_ops ahci_pci_pm_ops = {
568 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
Mika Westerberg02e53292016-02-18 10:54:17 +0200569 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
570 ahci_pci_device_runtime_resume, NULL)
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200571};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572
573static struct pci_driver ahci_pci_driver = {
574 .name = DRV_NAME,
575 .id_table = ahci_pci_tbl,
576 .probe = ahci_init_one,
Mika Westerberg02e53292016-02-18 10:54:17 +0200577 .remove = ahci_remove_one,
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200578 .driver = {
579 .pm = &ahci_pci_pm_ops,
580 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581};
582
Javier Martinez Canillas5219d652016-05-18 16:11:28 -0400583#if IS_ENABLED(CONFIG_PATA_MARVELL)
Alan Cox5b66c822008-09-03 14:48:34 +0100584static int marvell_enable;
585#else
586static int marvell_enable = 1;
587#endif
588module_param(marvell_enable, int, 0644);
589MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
590
591
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300592static void ahci_pci_save_initial_config(struct pci_dev *pdev,
593 struct ahci_host_priv *hpriv)
594{
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300595 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
596 dev_info(&pdev->dev, "JMB361 has only one port\n");
Antoine Tenart9a23c1d2014-11-03 09:56:11 +0100597 hpriv->force_port_map = 1;
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300598 }
599
600 /*
601 * Temporary Marvell 6145 hack: PATA port presence
602 * is asserted through the standard AHCI port
603 * presence register, as bit 4 (counting from 0)
604 */
605 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
606 if (pdev->device == 0x6121)
Antoine Tenart9a23c1d2014-11-03 09:56:11 +0100607 hpriv->mask_port_map = 0x3;
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300608 else
Antoine Tenart9a23c1d2014-11-03 09:56:11 +0100609 hpriv->mask_port_map = 0xf;
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300610 dev_info(&pdev->dev,
611 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
612 }
613
Antoine Ténart725c7b52014-07-30 20:13:56 +0200614 ahci_save_initial_config(&pdev->dev, hpriv);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300615}
616
Anton Vorontsov33030402010-03-03 20:17:39 +0300617static int ahci_pci_reset_controller(struct ata_host *host)
618{
619 struct pci_dev *pdev = to_pci_dev(host->dev);
620
621 ahci_reset_controller(host);
622
Tejun Heod91542c2006-07-26 15:59:26 +0900623 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300624 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900625 u16 tmp16;
626
627 /* configure PCS */
628 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900629 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
630 tmp16 |= hpriv->port_map;
631 pci_write_config_word(pdev, 0x92, tmp16);
632 }
Tejun Heod91542c2006-07-26 15:59:26 +0900633 }
634
635 return 0;
636}
637
Anton Vorontsov781d6552010-03-03 20:17:42 +0300638static void ahci_pci_init_controller(struct ata_host *host)
639{
640 struct ahci_host_priv *hpriv = host->private_data;
641 struct pci_dev *pdev = to_pci_dev(host->dev);
642 void __iomem *port_mmio;
643 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100644 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900645
Tejun Heo417a1a62007-09-23 13:19:55 +0900646 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100647 if (pdev->device == 0x6121)
648 mv = 2;
649 else
650 mv = 4;
651 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400652
653 writel(0, port_mmio + PORT_IRQ_MASK);
654
655 /* clear port IRQ */
656 tmp = readl(port_mmio + PORT_IRQ_STAT);
657 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
658 if (tmp)
659 writel(tmp, port_mmio + PORT_IRQ_STAT);
660 }
661
Anton Vorontsov781d6552010-03-03 20:17:42 +0300662 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900663}
664
Tejun Heocc0680a2007-08-06 18:36:23 +0900665static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900666 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900667{
Tejun Heocc0680a2007-08-06 18:36:23 +0900668 struct ata_port *ap = link->ap;
Hans de Goede039ece32014-02-22 16:53:30 +0100669 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo9dadd452008-04-07 22:47:19 +0900670 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900671 int rc;
672
673 DPRINTK("ENTER\n");
674
Tejun Heo4447d352007-04-17 23:44:08 +0900675 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900676
Tejun Heocc0680a2007-08-06 18:36:23 +0900677 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900678 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900679
Hans de Goede039ece32014-02-22 16:53:30 +0100680 hpriv->start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900681
682 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
683
684 /* vt8251 doesn't clear BSY on signature FIS reception,
685 * request follow-up softreset.
686 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900687 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900688}
689
Tejun Heoedc93052007-10-25 14:59:16 +0900690static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
691 unsigned long deadline)
692{
693 struct ata_port *ap = link->ap;
694 struct ahci_port_priv *pp = ap->private_data;
Hans de Goede039ece32014-02-22 16:53:30 +0100695 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heoedc93052007-10-25 14:59:16 +0900696 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
697 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900698 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900699 int rc;
700
701 ahci_stop_engine(ap);
702
703 /* clear D2H reception area to properly wait for D2H FIS */
704 ata_tf_init(link->device, &tf);
Sergei Shtylyov9bbb1b02013-06-23 01:39:39 +0400705 tf.command = ATA_BUSY;
Tejun Heoedc93052007-10-25 14:59:16 +0900706 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
707
708 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900709 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900710
Hans de Goede039ece32014-02-22 16:53:30 +0100711 hpriv->start_engine(ap);
Tejun Heoedc93052007-10-25 14:59:16 +0900712
Tejun Heoedc93052007-10-25 14:59:16 +0900713 /* The pseudo configuration device on SIMG4726 attached to
714 * ASUS P5W-DH Deluxe doesn't send signature FIS after
715 * hardreset if no device is attached to the first downstream
716 * port && the pseudo device locks up on SRST w/ PMP==0. To
717 * work around this, wait for !BSY only briefly. If BSY isn't
718 * cleared, perform CLO and proceed to IDENTIFY (achieved by
719 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
720 *
721 * Wait for two seconds. Devices attached to downstream port
722 * which can't process the following IDENTIFY after this will
723 * have to be reset again. For most cases, this should
724 * suffice while making probing snappish enough.
725 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900726 if (online) {
727 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
728 ahci_check_ready);
729 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800730 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900731 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900732 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900733}
734
Dan Williamsdbfe8ef2015-05-08 15:23:55 -0400735/*
736 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
737 *
738 * It has been observed with some SSDs that the timing of events in the
739 * link synchronization phase can leave the port in a state that can not
740 * be recovered by a SATA-hard-reset alone. The failing signature is
741 * SStatus.DET stuck at 1 ("Device presence detected but Phy
742 * communication not established"). It was found that unloading and
743 * reloading the driver when this problem occurs allows the drive
744 * connection to be recovered (DET advanced to 0x3). The critical
745 * component of reloading the driver is that the port state machines are
746 * reset by bouncing "port enable" in the AHCI PCS configuration
747 * register. So, reproduce that effect by bouncing a port whenever we
748 * see DET==1 after a reset.
749 */
750static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
751 unsigned long deadline)
752{
753 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
754 struct ata_port *ap = link->ap;
755 struct ahci_port_priv *pp = ap->private_data;
756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
758 unsigned long tmo = deadline - jiffies;
759 struct ata_taskfile tf;
760 bool online;
761 int rc, i;
762
763 DPRINTK("ENTER\n");
764
765 ahci_stop_engine(ap);
766
767 for (i = 0; i < 2; i++) {
768 u16 val;
769 u32 sstatus;
770 int port = ap->port_no;
771 struct ata_host *host = ap->host;
772 struct pci_dev *pdev = to_pci_dev(host->dev);
773
774 /* clear D2H reception area to properly wait for D2H FIS */
775 ata_tf_init(link->device, &tf);
776 tf.command = ATA_BUSY;
777 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
778
779 rc = sata_link_hardreset(link, timing, deadline, &online,
780 ahci_check_ready);
781
782 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
783 (sstatus & 0xf) != 1)
784 break;
785
786 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
787 port);
788
789 pci_read_config_word(pdev, 0x92, &val);
790 val &= ~(1 << port);
791 pci_write_config_word(pdev, 0x92, val);
792 ata_msleep(ap, 1000);
793 val |= 1 << port;
794 pci_write_config_word(pdev, 0x92, val);
795 deadline += tmo;
796 }
797
798 hpriv->start_engine(ap);
799
800 if (online)
801 *class = ahci_dev_classify(ap);
802
803 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
804 return rc;
805}
806
807
Mika Westerberg02e53292016-02-18 10:54:17 +0200808#ifdef CONFIG_PM
809static void ahci_pci_disable_interrupts(struct ata_host *host)
Tejun Heoc1332872006-07-26 15:59:26 +0900810{
Tejun Heo9b10ae82009-05-30 20:50:12 +0900811 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300812 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900813 u32 ctl;
814
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200815 /* AHCI spec rev1.1 section 8.3.3:
816 * Software must disable interrupts prior to requesting a
817 * transition of the HBA to D3 state.
818 */
819 ctl = readl(mmio + HOST_CTL);
820 ctl &= ~HOST_IRQ_EN;
821 writel(ctl, mmio + HOST_CTL);
822 readl(mmio + HOST_CTL); /* flush */
Mika Westerberg02e53292016-02-18 10:54:17 +0200823}
Tejun Heoc1332872006-07-26 15:59:26 +0900824
Mika Westerberg02e53292016-02-18 10:54:17 +0200825static int ahci_pci_device_runtime_suspend(struct device *dev)
826{
827 struct pci_dev *pdev = to_pci_dev(dev);
828 struct ata_host *host = pci_get_drvdata(pdev);
829
830 ahci_pci_disable_interrupts(host);
831 return 0;
832}
833
834static int ahci_pci_device_runtime_resume(struct device *dev)
835{
836 struct pci_dev *pdev = to_pci_dev(dev);
837 struct ata_host *host = pci_get_drvdata(pdev);
838 int rc;
839
840 rc = ahci_pci_reset_controller(host);
841 if (rc)
842 return rc;
843 ahci_pci_init_controller(host);
844 return 0;
845}
846
847#ifdef CONFIG_PM_SLEEP
848static int ahci_pci_device_suspend(struct device *dev)
849{
850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct ata_host *host = pci_get_drvdata(pdev);
852 struct ahci_host_priv *hpriv = host->private_data;
853
854 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
855 dev_err(&pdev->dev,
856 "BIOS update required for suspend/resume\n");
857 return -EIO;
858 }
859
860 ahci_pci_disable_interrupts(host);
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200861 return ata_host_suspend(host, PMSG_SUSPEND);
Tejun Heoc1332872006-07-26 15:59:26 +0900862}
863
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200864static int ahci_pci_device_resume(struct device *dev)
Tejun Heoc1332872006-07-26 15:59:26 +0900865{
Mika Westerbergf1d848f2016-02-18 10:54:15 +0200866 struct pci_dev *pdev = to_pci_dev(dev);
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900867 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heoc1332872006-07-26 15:59:26 +0900868 int rc;
869
James Lairdcb856962013-11-19 11:06:38 +1100870 /* Apple BIOS helpfully mangles the registers on resume */
871 if (is_mcp89_apple(pdev))
872 ahci_mcp89_apple_enable(pdev);
873
Tejun Heoc1332872006-07-26 15:59:26 +0900874 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300875 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900876 if (rc)
877 return rc;
878
Anton Vorontsov781d6552010-03-03 20:17:42 +0300879 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900880 }
881
Jeff Garzikcca39742006-08-24 03:19:22 -0400882 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900883
884 return 0;
885}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900886#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900887
Mika Westerberg02e53292016-02-18 10:54:17 +0200888#endif /* CONFIG_PM */
889
Tejun Heo4447d352007-04-17 23:44:08 +0900890static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893
Alessandro Rubini318893e2012-01-06 13:33:39 +0100894 /*
895 * If the device fixup already set the dma_mask to some non-standard
896 * value, don't extend it here. This happens on STA2X11, for example.
897 */
898 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
899 return 0;
900
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 if (using_dac &&
Quentin Lambertc54c7192015-04-08 14:34:10 +0200902 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
903 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904 if (rc) {
Quentin Lambertc54c7192015-04-08 14:34:10 +0200905 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700907 dev_err(&pdev->dev,
908 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909 return rc;
910 }
911 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 } else {
Quentin Lambertc54c7192015-04-08 14:34:10 +0200913 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700915 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916 return rc;
917 }
Quentin Lambertc54c7192015-04-08 14:34:10 +0200918 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700920 dev_err(&pdev->dev,
921 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 return rc;
923 }
924 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 return 0;
926}
927
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300928static void ahci_pci_print_info(struct ata_host *host)
929{
930 struct pci_dev *pdev = to_pci_dev(host->dev);
931 u16 cc;
932 const char *scc_s;
933
934 pci_read_config_word(pdev, 0x0a, &cc);
935 if (cc == PCI_CLASS_STORAGE_IDE)
936 scc_s = "IDE";
937 else if (cc == PCI_CLASS_STORAGE_SATA)
938 scc_s = "SATA";
939 else if (cc == PCI_CLASS_STORAGE_RAID)
940 scc_s = "RAID";
941 else
942 scc_s = "unknown";
943
944 ahci_print_info(host, scc_s);
945}
946
Tejun Heoedc93052007-10-25 14:59:16 +0900947/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
948 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
949 * support PMP and the 4726 either directly exports the device
950 * attached to the first downstream port or acts as a hardware storage
951 * controller and emulate a single ATA device (can be RAID 0/1 or some
952 * other configuration).
953 *
954 * When there's no device attached to the first downstream port of the
955 * 4726, "Config Disk" appears, which is a pseudo ATA device to
956 * configure the 4726. However, ATA emulation of the device is very
957 * lame. It doesn't send signature D2H Reg FIS after the initial
958 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
959 *
960 * The following function works around the problem by always using
961 * hardreset on the port and not depending on receiving signature FIS
962 * afterward. If signature FIS isn't received soon, ATA class is
963 * assumed without follow-up softreset.
964 */
965static void ahci_p5wdh_workaround(struct ata_host *host)
966{
Mathias Krause1bd06862014-08-31 10:57:09 +0200967 static const struct dmi_system_id sysids[] = {
Tejun Heoedc93052007-10-25 14:59:16 +0900968 {
969 .ident = "P5W DH Deluxe",
970 .matches = {
971 DMI_MATCH(DMI_SYS_VENDOR,
972 "ASUSTEK COMPUTER INC"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
974 },
975 },
976 { }
977 };
978 struct pci_dev *pdev = to_pci_dev(host->dev);
979
980 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
981 dmi_check_system(sysids)) {
982 struct ata_port *ap = host->ports[1];
983
Joe Perchesa44fec12011-04-15 15:51:58 -0700984 dev_info(&pdev->dev,
985 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900986
987 ap->ops = &ahci_p5wdh_ops;
988 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
989 }
990}
991
James Lairdcb856962013-11-19 11:06:38 +1100992/*
993 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
994 * booting in BIOS compatibility mode. We restore the registers but not ID.
995 */
996static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
997{
998 u32 val;
999
1000 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1001
1002 pci_read_config_dword(pdev, 0xf8, &val);
1003 val |= 1 << 0x1b;
1004 /* the following changes the device ID, but appears not to affect function */
1005 /* val = (val & ~0xf0000000) | 0x80000000; */
1006 pci_write_config_dword(pdev, 0xf8, val);
1007
1008 pci_read_config_dword(pdev, 0x54c, &val);
1009 val |= 1 << 0xc;
1010 pci_write_config_dword(pdev, 0x54c, val);
1011
1012 pci_read_config_dword(pdev, 0x4a4, &val);
1013 val &= 0xff;
1014 val |= 0x01060100;
1015 pci_write_config_dword(pdev, 0x4a4, val);
1016
1017 pci_read_config_dword(pdev, 0x54c, &val);
1018 val &= ~(1 << 0xc);
1019 pci_write_config_dword(pdev, 0x54c, val);
1020
1021 pci_read_config_dword(pdev, 0xf8, &val);
1022 val &= ~(1 << 0x1b);
1023 pci_write_config_dword(pdev, 0xf8, val);
1024}
1025
1026static bool is_mcp89_apple(struct pci_dev *pdev)
1027{
1028 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1029 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1030 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1031 pdev->subsystem_device == 0xcb89;
1032}
1033
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001034/* only some SB600 ahci controllers can do 64bit DMA */
1035static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +08001036{
1037 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +09001038 /*
1039 * The oldest version known to be broken is 0901 and
1040 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001041 * Enable 64bit DMA on 1501 and anything newer.
1042 *
Tejun Heo03d783b2009-08-16 21:04:02 +09001043 * Please read bko#9412 for more info.
1044 */
Shane Huang58a09b32009-05-27 15:04:43 +08001045 {
1046 .ident = "ASUS M2A-VM",
1047 .matches = {
1048 DMI_MATCH(DMI_BOARD_VENDOR,
1049 "ASUSTeK Computer INC."),
1050 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1051 },
Tejun Heo03d783b2009-08-16 21:04:02 +09001052 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +08001053 },
Mark Nelsone65cc192009-11-03 20:06:48 +11001054 /*
1055 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1056 * support 64bit DMA.
1057 *
1058 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1059 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1060 * This spelling mistake was fixed in BIOS version 1.5, so
1061 * 1.5 and later have the Manufacturer as
1062 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1063 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1064 *
1065 * BIOS versions earlier than 1.9 had a Board Product Name
1066 * DMI field of "MS-7376". This was changed to be
1067 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1068 * match on DMI_BOARD_NAME of "MS-7376".
1069 */
1070 {
1071 .ident = "MSI K9A2 Platinum",
1072 .matches = {
1073 DMI_MATCH(DMI_BOARD_VENDOR,
1074 "MICRO-STAR INTER"),
1075 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1076 },
1077 },
Mark Nelson3c4aa912011-06-27 16:33:44 +10001078 /*
Mark Nelsonff0173c2012-06-28 12:32:14 +10001079 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1080 * 64bit DMA.
1081 *
1082 * This board also had the typo mentioned above in the
1083 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1084 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1085 */
1086 {
1087 .ident = "MSI K9AGM2",
1088 .matches = {
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "MICRO-STAR INTER"),
1091 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1092 },
1093 },
1094 /*
Mark Nelson3c4aa912011-06-27 16:33:44 +10001095 * All BIOS versions for the Asus M3A support 64bit DMA.
1096 * (all release versions from 0301 to 1206 were tested)
1097 */
1098 {
1099 .ident = "ASUS M3A",
1100 .matches = {
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "ASUSTeK Computer INC."),
1103 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1104 },
1105 },
Shane Huang58a09b32009-05-27 15:04:43 +08001106 { }
1107 };
Tejun Heo03d783b2009-08-16 21:04:02 +09001108 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001109 int year, month, date;
1110 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +08001111
Tejun Heo03d783b2009-08-16 21:04:02 +09001112 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +08001113 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +09001114 !match)
Shane Huang58a09b32009-05-27 15:04:43 +08001115 return false;
1116
Mark Nelsone65cc192009-11-03 20:06:48 +11001117 if (!match->driver_data)
1118 goto enable_64bit;
1119
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001120 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1121 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +08001122
Mark Nelsone65cc192009-11-03 20:06:48 +11001123 if (strcmp(buf, match->driver_data) >= 0)
1124 goto enable_64bit;
1125 else {
Joe Perchesa44fec12011-04-15 15:51:58 -07001126 dev_warn(&pdev->dev,
1127 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1128 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001129 return false;
1130 }
Mark Nelsone65cc192009-11-03 20:06:48 +11001131
1132enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -07001133 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +11001134 return true;
Shane Huang58a09b32009-05-27 15:04:43 +08001135}
1136
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001137static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1138{
1139 static const struct dmi_system_id broken_systems[] = {
1140 {
1141 .ident = "HP Compaq nx6310",
1142 .matches = {
1143 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1144 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1145 },
1146 /* PCI slot number of the controller */
1147 .driver_data = (void *)0x1FUL,
1148 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +01001149 {
1150 .ident = "HP Compaq 6720s",
1151 .matches = {
1152 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1153 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1154 },
1155 /* PCI slot number of the controller */
1156 .driver_data = (void *)0x1FUL,
1157 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001158
1159 { } /* terminate list */
1160 };
1161 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1162
1163 if (dmi) {
1164 unsigned long slot = (unsigned long)dmi->driver_data;
1165 /* apply the quirk only to on-board controllers */
1166 return slot == PCI_SLOT(pdev->devfn);
1167 }
1168
1169 return false;
1170}
1171
Tejun Heo9b10ae82009-05-30 20:50:12 +09001172static bool ahci_broken_suspend(struct pci_dev *pdev)
1173{
1174 static const struct dmi_system_id sysids[] = {
1175 /*
1176 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1177 * to the harddisk doesn't become online after
1178 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +09001179 *
1180 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1181 *
1182 * Use dates instead of versions to match as HP is
1183 * apparently recycling both product and version
1184 * strings.
1185 *
1186 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +09001187 */
1188 {
1189 .ident = "dv4",
1190 .matches = {
1191 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1192 DMI_MATCH(DMI_PRODUCT_NAME,
1193 "HP Pavilion dv4 Notebook PC"),
1194 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001195 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001196 },
1197 {
1198 .ident = "dv5",
1199 .matches = {
1200 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1201 DMI_MATCH(DMI_PRODUCT_NAME,
1202 "HP Pavilion dv5 Notebook PC"),
1203 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001204 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001205 },
1206 {
1207 .ident = "dv6",
1208 .matches = {
1209 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1210 DMI_MATCH(DMI_PRODUCT_NAME,
1211 "HP Pavilion dv6 Notebook PC"),
1212 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001213 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001214 },
1215 {
1216 .ident = "HDX18",
1217 .matches = {
1218 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1219 DMI_MATCH(DMI_PRODUCT_NAME,
1220 "HP HDX18 Notebook PC"),
1221 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001222 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001223 },
Tejun Heocedc9bf2010-01-28 16:04:15 +09001224 /*
1225 * Acer eMachines G725 has the same problem. BIOS
1226 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001227 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +09001228 * that we don't have much idea about. For now,
1229 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +09001230 *
1231 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +09001232 */
1233 {
1234 .ident = "G725",
1235 .matches = {
1236 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1237 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1238 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001239 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +09001240 },
Tejun Heo9b10ae82009-05-30 20:50:12 +09001241 { } /* terminate list */
1242 };
1243 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +09001244 int year, month, date;
1245 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +09001246
1247 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1248 return false;
1249
Tejun Heo9deb3432010-03-16 09:50:26 +09001250 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1251 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +09001252
Tejun Heo9deb3432010-03-16 09:50:26 +09001253 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +09001254}
1255
Tejun Heo55946392009-08-04 14:30:08 +09001256static bool ahci_broken_online(struct pci_dev *pdev)
1257{
1258#define ENCODE_BUSDEVFN(bus, slot, func) \
1259 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1260 static const struct dmi_system_id sysids[] = {
1261 /*
1262 * There are several gigabyte boards which use
1263 * SIMG5723s configured as hardware RAID. Certain
1264 * 5723 firmware revisions shipped there keep the link
1265 * online but fail to answer properly to SRST or
1266 * IDENTIFY when no device is attached downstream
1267 * causing libata to retry quite a few times leading
1268 * to excessive detection delay.
1269 *
1270 * As these firmwares respond to the second reset try
1271 * with invalid device signature, considering unknown
1272 * sig as offline works around the problem acceptably.
1273 */
1274 {
1275 .ident = "EP45-DQ6",
1276 .matches = {
1277 DMI_MATCH(DMI_BOARD_VENDOR,
1278 "Gigabyte Technology Co., Ltd."),
1279 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1280 },
1281 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1282 },
1283 {
1284 .ident = "EP45-DS5",
1285 .matches = {
1286 DMI_MATCH(DMI_BOARD_VENDOR,
1287 "Gigabyte Technology Co., Ltd."),
1288 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1289 },
1290 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1291 },
1292 { } /* terminate list */
1293 };
1294#undef ENCODE_BUSDEVFN
1295 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1296 unsigned int val;
1297
1298 if (!dmi)
1299 return false;
1300
1301 val = (unsigned long)dmi->driver_data;
1302
1303 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1304}
1305
Jacob Pan0cf4a7d2014-04-15 22:27:11 -07001306static bool ahci_broken_devslp(struct pci_dev *pdev)
1307{
1308 /* device with broken DEVSLP but still showing SDS capability */
1309 static const struct pci_device_id ids[] = {
1310 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1311 {}
1312 };
1313
1314 return pci_match_id(ids, pdev);
1315}
1316
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001317#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09001318static void ahci_gtf_filter_workaround(struct ata_host *host)
1319{
1320 static const struct dmi_system_id sysids[] = {
1321 /*
1322 * Aspire 3810T issues a bunch of SATA enable commands
1323 * via _GTF including an invalid one and one which is
1324 * rejected by the device. Among the successful ones
1325 * is FPDMA non-zero offset enable which when enabled
1326 * only on the drive side leads to NCQ command
1327 * failures. Filter it out.
1328 */
1329 {
1330 .ident = "Aspire 3810T",
1331 .matches = {
1332 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1333 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1334 },
1335 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1336 },
1337 { }
1338 };
1339 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1340 unsigned int filter;
1341 int i;
1342
1343 if (!dmi)
1344 return;
1345
1346 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001347 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1348 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001349
1350 for (i = 0; i < host->n_ports; i++) {
1351 struct ata_port *ap = host->ports[i];
1352 struct ata_link *link;
1353 struct ata_device *dev;
1354
1355 ata_for_each_link(link, ap, EDGE)
1356 ata_for_each_dev(dev, link, ALL)
1357 dev->gtf_filter |= filter;
1358 }
1359}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001360#else
1361static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1362{}
1363#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001364
Sui Chenb59ec702017-05-09 07:47:22 -05001365/*
1366 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1367 * as DUMMY, or detected but eventually get a "link down" and never get up
1368 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1369 * port_map may hold a value of 0x00.
1370 *
1371 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1372 * and can significantly reduce the occurrence of the problem.
1373 *
1374 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1375 */
1376static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1377 struct pci_dev *pdev)
1378{
1379 static const struct dmi_system_id sysids[] = {
1380 {
1381 .ident = "Acer Switch Alpha 12",
1382 .matches = {
1383 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1384 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1385 },
1386 },
1387 { }
1388 };
1389
1390 if (dmi_check_system(sysids)) {
1391 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1392 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1393 hpriv->port_map = 0x7;
1394 hpriv->cap = 0xC734FF02;
1395 }
1396 }
1397}
1398
Tirumalesh Chalamarlad243bed2016-02-16 12:08:49 -08001399#ifdef CONFIG_ARM64
1400/*
1401 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1402 * Workaround is to make sure all pending IRQs are served before leaving
1403 * handler.
1404 */
1405static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1406{
1407 struct ata_host *host = dev_instance;
1408 struct ahci_host_priv *hpriv;
1409 unsigned int rc = 0;
1410 void __iomem *mmio;
1411 u32 irq_stat, irq_masked;
1412 unsigned int handled = 1;
1413
1414 VPRINTK("ENTER\n");
1415 hpriv = host->private_data;
1416 mmio = hpriv->mmio;
1417 irq_stat = readl(mmio + HOST_IRQ_STAT);
1418 if (!irq_stat)
1419 return IRQ_NONE;
1420
1421 do {
1422 irq_masked = irq_stat & hpriv->port_map;
1423 spin_lock(&host->lock);
1424 rc = ahci_handle_port_intr(host, irq_masked);
1425 if (!rc)
1426 handled = 0;
1427 writel(irq_stat, mmio + HOST_IRQ_STAT);
1428 irq_stat = readl(mmio + HOST_IRQ_STAT);
1429 spin_unlock(&host->lock);
1430 } while (irq_stat);
1431 VPRINTK("EXIT\n");
1432
1433 return IRQ_RETVAL(handled);
1434}
1435#endif
1436
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001437static int ahci_get_irq_vector(struct ata_host *host, int port)
Robert Richteree2aad42015-06-05 19:49:25 +02001438{
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001439 return pci_irq_vector(to_pci_dev(host->dev), port);
Robert Richteree2aad42015-06-05 19:49:25 +02001440}
1441
Robert Richtera1c82312015-05-31 13:55:17 +02001442static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1443 struct ahci_host_priv *hpriv)
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001444{
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001445 int nvec;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001446
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001447 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
Robert Richtera1c82312015-05-31 13:55:17 +02001448 return -ENODEV;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001449
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001450 /*
1451 * If number of MSIs is less than number of ports then Sharing Last
1452 * Message mode could be enforced. In this case assume that advantage
1453 * of multipe MSIs is negated and use single MSI mode instead.
1454 */
Christoph Hellwig17a51f12016-10-18 09:00:52 +02001455 if (n_ports > 1) {
1456 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1457 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1458 if (nvec > 0) {
1459 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1460 hpriv->get_irq_vector = ahci_get_irq_vector;
1461 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1462 return nvec;
1463 }
Alexander Gordeev7b92b4f2013-12-30 08:28:14 +01001464
Christoph Hellwig17a51f12016-10-18 09:00:52 +02001465 /*
1466 * Fallback to single MSI mode if the controller
1467 * enforced MRSM mode.
1468 */
1469 printk(KERN_INFO
1470 "ahci: MRSM is on, fallback to single MSI\n");
1471 pci_free_irq_vectors(pdev);
1472 }
Christoph Hellwiga478b092016-10-20 17:15:41 +02001473 }
Robert Richtera1c82312015-05-31 13:55:17 +02001474
Dan Williamsd684a902015-11-11 16:27:33 -08001475 /*
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001476 * If the host is not capable of supporting per-port vectors, fall
1477 * back to single MSI before finally attempting single MSI-X.
Dan Williamsd684a902015-11-11 16:27:33 -08001478 */
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001479 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1480 if (nvec == 1)
Dan Williamsd684a902015-11-11 16:27:33 -08001481 return nvec;
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001482 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001483}
1484
Tejun Heo24dc5f32007-01-20 16:00:28 +09001485static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486{
Tejun Heoe297d992008-06-10 00:13:04 +09001487 unsigned int board_id = ent->driver_data;
1488 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001489 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001490 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001492 struct ata_host *host;
Alexander Gordeevc3ebd6a2014-09-25 15:13:21 +02001493 int n_ports, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001494 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495
1496 VPRINTK("ENTER\n");
1497
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001498 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001499
Joe Perches06296a12011-04-15 15:52:00 -07001500 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001501
Alan Cox5b66c822008-09-03 14:48:34 +01001502 /* The AHCI driver can only drive the SATA ports, the PATA driver
1503 can drive them all so if both drivers are selected make sure
1504 AHCI stays out of the way */
1505 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1506 return -ENODEV;
1507
James Lairdcb856962013-11-19 11:06:38 +11001508 /* Apple BIOS on MCP89 prevents us using AHCI */
1509 if (is_mcp89_apple(pdev))
1510 ahci_mcp89_apple_enable(pdev);
Tejun Heoc6353b42010-06-17 11:42:22 +02001511
Mark Nelson7a022672009-11-22 12:07:41 +11001512 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1513 * At the moment, we can only use the AHCI mode. Let the users know
1514 * that for SAS drives they're out of luck.
1515 */
1516 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001517 dev_info(&pdev->dev,
1518 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001519
Robert Richterb7ae1282015-06-05 19:49:26 +02001520 /* Some devices use non-standard BARs */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001521 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1522 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001523 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1524 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
Robert Richterb7ae1282015-06-05 19:49:26 +02001525 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1526 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001527
Tejun Heo4447d352007-04-17 23:44:08 +09001528 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001529 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530 if (rc)
1531 return rc;
1532
Tejun Heoc4f77922007-12-06 15:09:43 +09001533 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1534 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1535 u8 map;
1536
1537 /* ICH6s share the same PCI ID for both piix and ahci
1538 * modes. Enabling ahci mode while MAP indicates
1539 * combined mode is a bad idea. Yield to ata_piix.
1540 */
1541 pci_read_config_byte(pdev, ICH_MAP, &map);
1542 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001543 dev_info(&pdev->dev,
1544 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001545 return -ENODEV;
1546 }
1547 }
1548
Paul Bolle6fec8872013-12-16 11:34:21 +01001549 /* AHCI controllers often implement SFF compatible interface.
1550 * Grab all PCI BARs just in case.
1551 */
1552 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1553 if (rc == -EBUSY)
1554 pcim_pin_device(pdev);
1555 if (rc)
1556 return rc;
1557
Tejun Heo24dc5f32007-01-20 16:00:28 +09001558 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1559 if (!hpriv)
1560 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001561 hpriv->flags |= (unsigned long)pi.private_data;
1562
Tejun Heoe297d992008-06-10 00:13:04 +09001563 /* MCP65 revision A1 and A2 can't do MSI */
1564 if (board_id == board_ahci_mcp65 &&
1565 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1566 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1567
Shane Huange427fe02008-12-30 10:53:41 +08001568 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1569 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1570 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1571
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001572 /* only some SB600s can do 64bit DMA */
1573 if (ahci_sb600_enable_64bit(pdev))
1574 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001575
Alessandro Rubini318893e2012-01-06 13:33:39 +01001576 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001577
Jacob Pan0cf4a7d2014-04-15 22:27:11 -07001578 /* must set flag prior to save config in order to take effect */
1579 if (ahci_broken_devslp(pdev))
1580 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1581
Tirumalesh Chalamarlad243bed2016-02-16 12:08:49 -08001582#ifdef CONFIG_ARM64
1583 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1584 hpriv->irq_handler = ahci_thunderx_irq_handler;
1585#endif
1586
Tejun Heo4447d352007-04-17 23:44:08 +09001587 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001588 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589
Tejun Heo4447d352007-04-17 23:44:08 +09001590 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001591 if (hpriv->cap & HOST_CAP_NCQ) {
1592 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001593 /*
1594 * Auto-activate optimization is supposed to be
1595 * supported on all AHCI controllers indicating NCQ
1596 * capability, but it seems to be broken on some
1597 * chipsets including NVIDIAs.
1598 */
1599 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001600 pi.flags |= ATA_FLAG_FPDMA_AA;
Marc Carino40fb59e2013-08-24 23:22:49 -07001601
1602 /*
1603 * All AHCI controllers should be forward-compatible
1604 * with the new auxiliary field. This code should be
1605 * conditionalized if any buggy AHCI controllers are
1606 * encountered.
1607 */
1608 pi.flags |= ATA_FLAG_FPDMA_AUX;
Robert Hancock453d3132010-01-26 22:33:23 -06001609 }
Tejun Heo4447d352007-04-17 23:44:08 +09001610
Tejun Heo7d50b602007-09-23 13:19:54 +09001611 if (hpriv->cap & HOST_CAP_PMP)
1612 pi.flags |= ATA_FLAG_PMP;
1613
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001614 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001615
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001616 if (ahci_broken_system_poweroff(pdev)) {
1617 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1618 dev_info(&pdev->dev,
1619 "quirky BIOS, skipping spindown on poweroff\n");
1620 }
1621
Tejun Heo9b10ae82009-05-30 20:50:12 +09001622 if (ahci_broken_suspend(pdev)) {
1623 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001624 dev_warn(&pdev->dev,
1625 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001626 }
1627
Tejun Heo55946392009-08-04 14:30:08 +09001628 if (ahci_broken_online(pdev)) {
1629 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1630 dev_info(&pdev->dev,
1631 "online status unreliable, applying workaround\n");
1632 }
1633
Sui Chenb59ec702017-05-09 07:47:22 -05001634
1635 /* Acer SA5-271 workaround modifies private_data */
1636 acer_sa5_271_workaround(hpriv, pdev);
1637
Tejun Heo837f5f82008-02-06 15:13:51 +09001638 /* CAP.NP sometimes indicate the index of the last enabled
1639 * port, at other times, that of the last possible port, so
1640 * determining the maximum port number requires looking at
1641 * both CAP.NP and port_map.
1642 */
1643 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1644
1645 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001646 if (!host)
1647 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001648 host->private_data = hpriv;
Christoph Hellwig0b9e29882016-09-05 17:21:45 +02001649
1650 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1651 /* legacy intx interrupts */
1652 pci_intx(pdev, 1);
1653 }
Christoph Hellwig0ce57f82016-10-25 14:04:34 +02001654 hpriv->irq = pci_irq_vector(pdev, 0);
Robert Richter21bfd1a2015-05-31 13:55:18 +02001655
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001656 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001657 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001658 else
Jingoo Hand2782d92013-10-05 09:15:16 +09001659 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001660
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001661 if (pi.flags & ATA_FLAG_EM)
1662 ahci_reset_em(host);
1663
Tejun Heo4447d352007-04-17 23:44:08 +09001664 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001665 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001666
Alessandro Rubini318893e2012-01-06 13:33:39 +01001667 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1668 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001669 0x100 + ap->port_no * 0x80, "port");
1670
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001671 /* set enclosure management message type */
1672 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001673 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001674
1675
Jeff Garzikdab632e2007-05-28 08:33:01 -04001676 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001677 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001678 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001679 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680
Tejun Heoedc93052007-10-25 14:59:16 +09001681 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1682 ahci_p5wdh_workaround(host);
1683
Tejun Heof80ae7e2009-09-16 04:18:03 +09001684 /* apply gtf filter quirk */
1685 ahci_gtf_filter_workaround(host);
1686
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001688 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001690 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691
Anton Vorontsov33030402010-03-03 20:17:39 +03001692 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001693 if (rc)
1694 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001695
Anton Vorontsov781d6552010-03-03 20:17:42 +03001696 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001697 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698
Tejun Heo4447d352007-04-17 23:44:08 +09001699 pci_set_master(pdev);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001700
Mika Westerberg02e53292016-02-18 10:54:17 +02001701 rc = ahci_host_activate(host, &ahci_sht);
1702 if (rc)
1703 return rc;
1704
1705 pm_runtime_put_noidle(&pdev->dev);
1706 return 0;
1707}
1708
1709static void ahci_remove_one(struct pci_dev *pdev)
1710{
1711 pm_runtime_get_noresume(&pdev->dev);
1712 ata_pci_remove_one(pdev);
Jeff Garzik907f4672005-05-12 15:03:42 -04001713}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714
Axel Lin2fc75da2012-04-19 13:43:05 +08001715module_pci_driver(ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716
1717MODULE_AUTHOR("Jeff Garzik");
1718MODULE_DESCRIPTION("AHCI SATA low-level driver");
1719MODULE_LICENSE("GPL");
1720MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001721MODULE_VERSION(DRV_VERSION);