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gerrit-public.fairphone.software / platform / external / llvm / a0c48eb8f69bcb619a2c2cc0044375bb4171cebe / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: ce4587b7d7c6013236e5f9c37cddf924ededb9cd [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]12#include "ARM.h"
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]13#include "ARMSubtarget.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]14#include "MCTargetDesc/ARMAddressingModes.h"
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]15#include "MCTargetDesc/ARMMCExpr.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]16#include "MCTargetDesc/ARMBaseInfo.h"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]17#include "llvm/MC/EDInstInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]18#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]19#include "llvm/MC/MCInstrDesc.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]22#include "llvm/MC/MCDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
28
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]29using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]30
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37 /// Constructor - Initializes the disassembler.
38 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]39 ARMDisassembler(const MCSubtargetInfo &STI) :
40 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]41 }
42
43 ~ARMDisassembler() {
44 }
45
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
48 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]49 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]50 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]51 raw_ostream &vStream,
52 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]53
54 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]55 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62 /// Constructor - Initializes the disassembler.
63 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]64 ThumbDisassembler(const MCSubtargetInfo &STI) :
65 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]66 }
67
68 ~ThumbDisassembler() {
69 }
70
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
73 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]74 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]75 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]76 raw_ostream &vStream,
77 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]78
79 /// getEDInfo - See MCDisassembler.
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]80 const EDInstInfo *getEDInfo() const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]81private:
82 mutable std::vector<unsigned> ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]83 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]84 void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]88static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]89 switch (In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
92 return true;
93 case MCDisassembler::SoftFail:
94 Out = In;
95 return true;
96 case MCDisassembler::Fail:
97 Out = In;
98 return false;
99 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]100 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]101}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]102
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]103
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]107 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]112 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]114 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]116 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]118 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]120 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]122 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]128 uint64_t Address, const void *Decoder);
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]129static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
130 uint64_t Address, const void *Decoder);
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]131static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
132 unsigned RegNo, uint64_t Address,
133 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]134
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]135static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]137static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]138 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]139static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]140 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]141static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]142 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]143static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]145static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]146 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]147
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]148static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]149 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]150static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]151 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]152static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]153 unsigned Insn,
154 uint64_t Address,
155 const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]156static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]157 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]158static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]159 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]160static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]161 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]162static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]163 uint64_t Address, const void *Decoder);
164
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]165static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]166 unsigned Insn,
167 uint64_t Adddress,
168 const void *Decoder);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]169static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
170 uint64_t Address, const void *Decoder);
171static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
172 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]173static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]174 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]175static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]176 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]177static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]178 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]179static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]180 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]181static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]182 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]183static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]184 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]185static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]186 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]187static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]188 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]189static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]190 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]191static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]192 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]193static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]194 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]195static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]196 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]197static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]198 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]199static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]201static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]203static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]204 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]205static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]206 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]207static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]209static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]211static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]213static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]215static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]216 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]217static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]218 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]219static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]220 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]221static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]222 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]223static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]224 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]225static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]226 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]227static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]228 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]229static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]230 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]231static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]232 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]233static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]234 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]235static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]236 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]237static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]238 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]239static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]240 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]241static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]242 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]243static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]244 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]245static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]246 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]247static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]248 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]249static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]250 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]251static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]252 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]253static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]254 uint64_t Address, const void *Decoder);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]255static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
256 uint64_t Address, const void *Decoder);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]257static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
258 uint64_t Address, const void *Decoder);
259static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
260 uint64_t Address, const void *Decoder);
261
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]262
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]263static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]264 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]265static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]266 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]267static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]268 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]269static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]270 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]271static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]272 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]273static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]274 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]275static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]276 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]277static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]278 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]279static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]280 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]281static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]282 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]283static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]284 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]285static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]286 uint64_t Address, const void *Decoder);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]287static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
288 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]289static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]290 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]291static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]292 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]293static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]294 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]295static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]296 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]297static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]298 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]299static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]300 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]301static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]302 uint64_t Address, const void *Decoder);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]303static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
304 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]305static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]306 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]307static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]308 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]309static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]310 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]311static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]312 uint64_t Address, const void *Decoder);
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]313static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]314 uint64_t Address, const void *Decoder);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]315static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
316 uint64_t Address, const void *Decoder);
317static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
318 uint64_t Address, const void *Decoder);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]319static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
320 uint64_t Address, const void *Decoder);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]321static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]323static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
325
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]326
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327
328#include "ARMGenDisassemblerTables.inc"
329#include "ARMGenInstrInfo.inc"
Oscar Fuentes38e13902010-09-28 11:48:19 +0000[diff] [blame]330#include "ARMGenEDInfo.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]331
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]332static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
333 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]334}
335
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]336static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
337 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]338}
339
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]340const EDInstInfo *ARMDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]341 return instInfoARM;
342}
343
Benjamin Kramer88b6fc02012-02-11 14:51:07 +0000[diff] [blame]344const EDInstInfo *ThumbDisassembler::getEDInfo() const {
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]345 return instInfoARM;
346}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]348DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]349 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]350 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]351 raw_ostream &os,
352 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]353 CommentStream = &cs;
354
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint8_t bytes[4];
356
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
359
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]360 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
362 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]363 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]364 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365
366 // Encoded as a small-endian 32-bit word in the stream.
367 uint32_t insn = (bytes[3] << 24) |
368 (bytes[2] << 16) |
369 (bytes[1] << 8) |
370 (bytes[0] << 0);
371
372 // Calling the auto-generated decoder function.
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]374 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]375 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]376 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]377 }
378
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]379 // VFP and NEON instructions, similarly, are shared between ARM
380 // and Thumb modes.
381 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]382 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]383 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]384 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]385 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]386 }
387
388 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]390 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]391 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]392 // Add a fake predicate operand, because we share these instruction
393 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]394 if (!DecodePredicateOperand(MI, 0xE, Address, this))
395 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]396 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]397 }
398
399 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]401 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]402 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]403 // Add a fake predicate operand, because we share these instruction
404 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]405 if (!DecodePredicateOperand(MI, 0xE, Address, this))
406 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]407 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]408 }
409
410 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]412 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]413 Size = 4;
414 // Add a fake predicate operand, because we share these instruction
415 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]416 if (!DecodePredicateOperand(MI, 0xE, Address, this))
417 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]418 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]419 }
420
421 MI.clear();
422
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]423 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]424 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]425}
426
427namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]428extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]429}
430
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]431/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
432/// immediate Value in the MCInst. The immediate Value has had any PC
433/// adjustment made by the caller. If the instruction is a branch instruction
434/// then isBranch is true, else false. If the getOpInfo() function was set as
435/// part of the setupForSymbolicDisassembly() call then that function is called
436/// to get any symbolic information at the Address for this instruction. If
437/// that returns non-zero then the symbolic information it returns is used to
438/// create an MCExpr and that is added as an operand to the MCInst. If
439/// getOpInfo() returns zero and isBranch is true then a symbol look up for
440/// Value is done and if a symbol is found an MCExpr is created with that, else
441/// an MCExpr with Value is created. This function returns true if it adds an
442/// operand to the MCInst and false otherwise.
443static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
444 bool isBranch, uint64_t InstSize,
445 MCInst &MI, const void *Decoder) {
446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]448 struct LLVMOpInfo1 SymbolicOp;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]450 SymbolicOp.Value = Value;
451 void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]452
453 if (!getOpInfo ||
454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
455 // Clear SymbolicOp.Value from above and also all other fields.
456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
458 if (!SymbolLookUp)
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]459 return false;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]460 uint64_t ReferenceType;
461 if (isBranch)
462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
463 else
464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
465 const char *ReferenceName;
466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
467 &ReferenceName);
468 if (Name) {
469 SymbolicOp.AddSymbol.Name = Name;
470 SymbolicOp.AddSymbol.Present = true;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]471 }
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]472 // For branches always create an MCExpr so it gets printed as hex address.
473 else if (isBranch) {
474 SymbolicOp.Value = Value;
475 }
476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
478 if (!Name && !isBranch)
479 return false;
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]480 }
481
482 MCContext *Ctx = Dis->getMCContext();
483 const MCExpr *Add = NULL;
484 if (SymbolicOp.AddSymbol.Present) {
485 if (SymbolicOp.AddSymbol.Name) {
486 StringRef Name(SymbolicOp.AddSymbol.Name);
487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
488 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
489 } else {
490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
491 }
492 }
493
494 const MCExpr *Sub = NULL;
495 if (SymbolicOp.SubtractSymbol.Present) {
496 if (SymbolicOp.SubtractSymbol.Name) {
497 StringRef Name(SymbolicOp.SubtractSymbol.Name);
498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
500 } else {
501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
502 }
503 }
504
505 const MCExpr *Off = NULL;
506 if (SymbolicOp.Value != 0)
507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
508
509 const MCExpr *Expr;
510 if (Sub) {
511 const MCExpr *LHS;
512 if (Add)
513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
514 else
515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
516 if (Off != 0)
517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
518 else
519 Expr = LHS;
520 } else if (Add) {
521 if (Off != 0)
522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
523 else
524 Expr = Add;
525 } else {
526 if (Off != 0)
527 Expr = Off;
528 else
529 Expr = MCConstantExpr::Create(0, *Ctx);
530 }
531
532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
537 MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]538 else
Craig Topperbc219812012-02-07 02:50:20 +0000[diff] [blame]539 llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]540
541 return true;
542}
543
544/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
545/// referenced by a load instruction with the base register that is the Pc.
546/// These can often be values in a literal pool near the Address of the
547/// instruction. The Address of the instruction and its immediate Value are
548/// used as a possible literal pool entry. The SymbolLookUp call back will
549/// return the name of a symbol referenced by the the literal pool's entry if
550/// the referenced address is that of a symbol. Or it will return a pointer to
551/// a literal 'C' string if the referenced address of the literal pool's entry
552/// is an address into a section with 'C' string literals.
553static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]554 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
557 if (SymbolLookUp) {
558 void *DisInfo = Dis->getDisInfoBlock();
559 uint64_t ReferenceType;
560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
561 const char *ReferenceName;
562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
566 }
567}
568
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]569// Thumb1 instructions don't have explicit S bits. Rather, they
570// implicitly set CPSR. Since it's not represented in the encoding, the
571// auto-generated decoder won't inject the CPSR operand. We need to fix
572// that as a post-pass.
573static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]576 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]577 for (unsigned i = 0; i < NumOps; ++i, ++I) {
578 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]580 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
582 return;
583 }
584 }
585
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]587}
588
589// Most Thumb instructions don't have explicit predicates in the
590// encoding, but rather get their predicates from IT context. We need
591// to fix up the predicate operands using this context information as a
592// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]593MCDisassembler::DecodeStatus
594ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]595 MCDisassembler::DecodeStatus S = Success;
596
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]597 // A few instructions actually have predicates encoded in them. Don't
598 // try to overwrite it if we're seeing one of those.
599 switch (MI.getOpcode()) {
600 case ARM::tBcc:
601 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]602 case ARM::tCBZ:
603 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]604 case ARM::tCPS:
605 case ARM::t2CPS3p:
606 case ARM::t2CPS2p:
607 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]608 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]609 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]610 // Some instructions (mostly conditional branches) are not
611 // allowed in IT blocks.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]612 if (!ITBlock.empty())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]613 S = SoftFail;
614 else
615 return Success;
616 break;
617 case ARM::tB:
618 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]619 case ARM::t2TBB:
620 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]621 // Some instructions (mostly unconditional branches) can
622 // only appears at the end of, or outside of, an IT.
623 if (ITBlock.size() > 1)
624 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]625 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]626 default:
627 break;
628 }
629
630 // If we're in an IT block, base the predicate on that. Otherwise,
631 // assume a predicate of AL.
632 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]633 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]634 CC = ITBlock.back();
Owen Anderson9bd655d2011-08-26 06:19:51 +0000[diff] [blame]635 if (CC == 0xF)
636 CC = ARMCC::AL;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 ITBlock.pop_back();
638 } else
639 CC = ARMCC::AL;
640
641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]643 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]644 for (unsigned i = 0; i < NumOps; ++i, ++I) {
645 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]646 if (OpInfo[i].isPredicate()) {
647 I = MI.insert(I, MCOperand::CreateImm(CC));
648 ++I;
649 if (CC == ARMCC::AL)
650 MI.insert(I, MCOperand::CreateReg(0));
651 else
652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]653 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]654 }
655 }
656
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]657 I = MI.insert(I, MCOperand::CreateImm(CC));
658 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]659 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]660 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]661 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]663
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]664 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]665}
666
667// Thumb VFP instructions are a special case. Because we share their
668// encodings between ARM and Thumb modes, and they are predicable in ARM
669// mode, the auto-generated decoder will give them an (incorrect)
670// predicate operand. We need to rewrite these operands based on the IT
671// context as a post-pass.
672void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
673 unsigned CC;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]674 if (!ITBlock.empty()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]675 CC = ITBlock.back();
676 ITBlock.pop_back();
677 } else
678 CC = ARMCC::AL;
679
680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
681 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]684 if (OpInfo[i].isPredicate() ) {
685 I->setImm(CC);
686 ++I;
687 if (CC == ARMCC::AL)
688 I->setReg(0);
689 else
690 I->setReg(ARM::CPSR);
691 return;
692 }
693 }
694}
695
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]696DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]697 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]698 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]699 raw_ostream &os,
700 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]701 CommentStream = &cs;
702
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]703 uint8_t bytes[4];
704
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]705 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
707
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 // We want to read exactly 2 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
710 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]711 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]712 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]713
714 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]716 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]717 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]718 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]719 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]720 }
721
722 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]724 if (result) {
725 Size = 2;
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]726 bool InITBlock = !ITBlock.empty();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]727 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]728 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]729 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]730 }
731
732 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]734 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]735 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]736
737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
738 // the Thumb predicate.
739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
740 result = MCDisassembler::SoftFail;
741
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]742 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]743
744 // If we find an IT instruction, we need to parse its condition
745 // code and mask operands so that we can apply them correctly
746 // to the subsequent instructions.
747 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]748
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]749 // (3 - the number of trailing zeros) is the number of then / else.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]750 unsigned firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]751 unsigned Mask = MI.getOperand(1).getImm();
752 unsigned CondBit0 = Mask >> 4 & 1;
753 unsigned NumTZ = CountTrailingZeros_32(Mask);
754 assert(NumTZ <= 3 && "Invalid IT mask!");
755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
756 bool T = ((Mask >> Pos) & 1) == CondBit0;
757 if (T)
758 ITBlock.insert(ITBlock.begin(), firstcond);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]759 else
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]761 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]762
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]763 ITBlock.push_back(firstcond);
764 }
765
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]766 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]767 }
768
769 // We want to read exactly 4 bytes of data.
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
771 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]772 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]773 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]774
775 uint32_t insn32 = (bytes[3] << 8) |
776 (bytes[2] << 0) |
777 (bytes[1] << 24) |
778 (bytes[0] << 16);
779 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]781 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]782 Size = 4;
783 bool InITBlock = ITBlock.size();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]784 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]785 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]786 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]787 }
788
789 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]791 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]792 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]793 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]794 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]795 }
796
797 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]799 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]800 Size = 4;
801 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]802 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]803 }
804
805 MI.clear();
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]807 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]808 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]809 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]810 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]811 }
812
813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
814 MI.clear();
815 uint32_t NEONLdStInsn = insn32;
816 NEONLdStInsn &= 0xF0FFFFFF;
817 NEONLdStInsn |= 0x04000000;
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]819 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]820 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]821 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]822 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]823 }
824 }
825
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]827 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]828 uint32_t NEONDataInsn = insn32;
829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]833 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]834 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]835 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]836 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]837 }
838 }
839
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]840 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]841 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]842}
843
844
845extern "C" void LLVMInitializeARMDisassembler() {
846 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
847 createARMDisassembler);
848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
849 createThumbDisassembler);
850}
851
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]852static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]853 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
854 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
855 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
856 ARM::R12, ARM::SP, ARM::LR, ARM::PC
857};
858
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]859static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]860 uint64_t Address, const void *Decoder) {
861 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]862 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]863
864 unsigned Register = GPRDecoderTable[RegNo];
865 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]866 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]867}
868
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]869static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]870DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
871 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]872 DecodeStatus S = MCDisassembler::Success;
873
874 if (RegNo == 15)
875 S = MCDisassembler::SoftFail;
876
877 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
878
879 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]880}
881
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]882static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]883 uint64_t Address, const void *Decoder) {
884 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]885 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
887}
888
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]889static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]890 uint64_t Address, const void *Decoder) {
891 unsigned Register = 0;
892 switch (RegNo) {
893 case 0:
894 Register = ARM::R0;
895 break;
896 case 1:
897 Register = ARM::R1;
898 break;
899 case 2:
900 Register = ARM::R2;
901 break;
902 case 3:
903 Register = ARM::R3;
904 break;
905 case 9:
906 Register = ARM::R9;
907 break;
908 case 12:
909 Register = ARM::R12;
910 break;
911 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]912 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]913 }
914
915 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]916 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]917}
918
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]919static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]920 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]921 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
923}
924
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]925static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]926 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
927 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
928 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
929 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
930 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
931 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
932 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
933 ARM::S28, ARM::S29, ARM::S30, ARM::S31
934};
935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]936static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]937 uint64_t Address, const void *Decoder) {
938 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]939 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]940
941 unsigned Register = SPRDecoderTable[RegNo];
942 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]943 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]944}
945
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]946static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
948 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
949 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
950 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
951 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
952 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
953 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
954 ARM::D28, ARM::D29, ARM::D30, ARM::D31
955};
956
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]957static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 uint64_t Address, const void *Decoder) {
959 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]960 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]961
962 unsigned Register = DPRDecoderTable[RegNo];
963 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]964 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]965}
966
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]967static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]968 uint64_t Address, const void *Decoder) {
969 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]970 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]971 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
972}
973
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]974static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]975DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
976 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]977 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]979 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
980}
981
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]982static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]983 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
984 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
985 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
986 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
987};
988
989
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]990static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]991 uint64_t Address, const void *Decoder) {
992 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]993 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]994 RegNo >>= 1;
995
996 unsigned Register = QPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]998 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]999}
1000
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1001static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]1002 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1003 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1004 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1005 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1006 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1007 ARM::Q15
1008};
1009
1010static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
1011 uint64_t Address, const void *Decoder) {
1012 if (RegNo > 30)
1013 return MCDisassembler::Fail;
1014
1015 unsigned Register = DPairDecoderTable[RegNo];
1016 Inst.addOperand(MCOperand::CreateReg(Register));
1017 return MCDisassembler::Success;
1018}
1019
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]1020static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]1021 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1022 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1023 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1024 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1025 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1026 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1027 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1028 ARM::D28_D30, ARM::D29_D31
1029};
1030
1031static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
1032 unsigned RegNo,
1033 uint64_t Address,
1034 const void *Decoder) {
1035 if (RegNo > 29)
1036 return MCDisassembler::Fail;
1037
1038 unsigned Register = DPairSpacedDecoderTable[RegNo];
1039 Inst.addOperand(MCOperand::CreateReg(Register));
1040 return MCDisassembler::Success;
1041}
1042
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1043static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1044 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1045 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1046 // AL predicate is not allowed on Thumb1 branches.
1047 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1048 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1049 Inst.addOperand(MCOperand::CreateImm(Val));
1050 if (Val == ARMCC::AL) {
1051 Inst.addOperand(MCOperand::CreateReg(0));
1052 } else
1053 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1054 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1055}
1056
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1057static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1058 uint64_t Address, const void *Decoder) {
1059 if (Val)
1060 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1061 else
1062 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1063 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1064}
1065
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1066static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1067 uint64_t Address, const void *Decoder) {
1068 uint32_t imm = Val & 0xFF;
1069 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1070 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1071 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1072 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1073}
1074
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1075static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1076 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1077 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1078
1079 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1080 unsigned type = fieldFromInstruction32(Val, 5, 2);
1081 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1082
1083 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1085 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1086
1087 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1088 switch (type) {
1089 case 0:
1090 Shift = ARM_AM::lsl;
1091 break;
1092 case 1:
1093 Shift = ARM_AM::lsr;
1094 break;
1095 case 2:
1096 Shift = ARM_AM::asr;
1097 break;
1098 case 3:
1099 Shift = ARM_AM::ror;
1100 break;
1101 }
1102
1103 if (Shift == ARM_AM::ror && imm == 0)
1104 Shift = ARM_AM::rrx;
1105
1106 unsigned Op = Shift | (imm << 3);
1107 Inst.addOperand(MCOperand::CreateImm(Op));
1108
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1109 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1110}
1111
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1112static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1113 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1114 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1115
1116 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1117 unsigned type = fieldFromInstruction32(Val, 5, 2);
1118 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1119
1120 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1122 return MCDisassembler::Fail;
1123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1124 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1125
1126 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1127 switch (type) {
1128 case 0:
1129 Shift = ARM_AM::lsl;
1130 break;
1131 case 1:
1132 Shift = ARM_AM::lsr;
1133 break;
1134 case 2:
1135 Shift = ARM_AM::asr;
1136 break;
1137 case 3:
1138 Shift = ARM_AM::ror;
1139 break;
1140 }
1141
1142 Inst.addOperand(MCOperand::CreateImm(Shift));
1143
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1144 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1145}
1146
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1147static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1148 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1149 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1150
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1151 bool writebackLoad = false;
1152 unsigned writebackReg = 0;
1153 switch (Inst.getOpcode()) {
1154 default:
1155 break;
1156 case ARM::LDMIA_UPD:
1157 case ARM::LDMDB_UPD:
1158 case ARM::LDMIB_UPD:
1159 case ARM::LDMDA_UPD:
1160 case ARM::t2LDMIA_UPD:
1161 case ARM::t2LDMDB_UPD:
1162 writebackLoad = true;
1163 writebackReg = Inst.getOperand(0).getReg();
1164 break;
1165 }
1166
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1167 // Empty register lists are not allowed.
Owen Anderson244006d2011-11-02 17:46:18 +0000[diff] [blame]1168 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1169 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1170 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1171 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1172 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1173 // Writeback not allowed if Rn is in the target list.
1174 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1175 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1176 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1177 }
1178
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1179 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180}
1181
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1182static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1184 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1185
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1186 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1187 unsigned regs = Val & 0xFF;
1188
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1189 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1190 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1191 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1192 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1193 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1194 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1195
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1196 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1197}
1198
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1199static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1200 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1201 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1202
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1203 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1204 unsigned regs = (Val & 0xFF) / 2;
1205
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1206 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1207 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1208 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1209 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1210 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1211 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1212
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1213 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1214}
1215
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1216static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1217 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1218 // This operand encodes a mask of contiguous zeros between a specified MSB
1219 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1220 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1221 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1222 // create the final mask.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1223 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1224 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1225
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1226 DecodeStatus S = MCDisassembler::Success;
1227 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1228
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1229 uint32_t msb_mask = 0xFFFFFFFF;
1230 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1231 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1232
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1233 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1234 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1235}
1236
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1237static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1238 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1239 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1240
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1241 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1242 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1243 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1244 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1245 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1246 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1247
1248 switch (Inst.getOpcode()) {
1249 case ARM::LDC_OFFSET:
1250 case ARM::LDC_PRE:
1251 case ARM::LDC_POST:
1252 case ARM::LDC_OPTION:
1253 case ARM::LDCL_OFFSET:
1254 case ARM::LDCL_PRE:
1255 case ARM::LDCL_POST:
1256 case ARM::LDCL_OPTION:
1257 case ARM::STC_OFFSET:
1258 case ARM::STC_PRE:
1259 case ARM::STC_POST:
1260 case ARM::STC_OPTION:
1261 case ARM::STCL_OFFSET:
1262 case ARM::STCL_PRE:
1263 case ARM::STCL_POST:
1264 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1265 case ARM::t2LDC_OFFSET:
1266 case ARM::t2LDC_PRE:
1267 case ARM::t2LDC_POST:
1268 case ARM::t2LDC_OPTION:
1269 case ARM::t2LDCL_OFFSET:
1270 case ARM::t2LDCL_PRE:
1271 case ARM::t2LDCL_POST:
1272 case ARM::t2LDCL_OPTION:
1273 case ARM::t2STC_OFFSET:
1274 case ARM::t2STC_PRE:
1275 case ARM::t2STC_POST:
1276 case ARM::t2STC_OPTION:
1277 case ARM::t2STCL_OFFSET:
1278 case ARM::t2STCL_PRE:
1279 case ARM::t2STCL_POST:
1280 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1281 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1282 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1283 break;
1284 default:
1285 break;
1286 }
1287
1288 Inst.addOperand(MCOperand::CreateImm(coproc));
1289 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1291 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1292
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1293 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1294 case ARM::t2LDC2_OFFSET:
1295 case ARM::t2LDC2L_OFFSET:
1296 case ARM::t2LDC2_PRE:
1297 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1298 case ARM::t2STC2_OFFSET:
1299 case ARM::t2STC2L_OFFSET:
1300 case ARM::t2STC2_PRE:
1301 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1302 case ARM::LDC2_OFFSET:
1303 case ARM::LDC2L_OFFSET:
1304 case ARM::LDC2_PRE:
1305 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1306 case ARM::STC2_OFFSET:
1307 case ARM::STC2L_OFFSET:
1308 case ARM::STC2_PRE:
1309 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1310 case ARM::t2LDC_OFFSET:
1311 case ARM::t2LDCL_OFFSET:
1312 case ARM::t2LDC_PRE:
1313 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1314 case ARM::t2STC_OFFSET:
1315 case ARM::t2STCL_OFFSET:
1316 case ARM::t2STC_PRE:
1317 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1318 case ARM::LDC_OFFSET:
1319 case ARM::LDCL_OFFSET:
1320 case ARM::LDC_PRE:
1321 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1322 case ARM::STC_OFFSET:
1323 case ARM::STCL_OFFSET:
1324 case ARM::STC_PRE:
1325 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1326 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1327 Inst.addOperand(MCOperand::CreateImm(imm));
1328 break;
1329 case ARM::t2LDC2_POST:
1330 case ARM::t2LDC2L_POST:
1331 case ARM::t2STC2_POST:
1332 case ARM::t2STC2L_POST:
1333 case ARM::LDC2_POST:
1334 case ARM::LDC2L_POST:
1335 case ARM::STC2_POST:
1336 case ARM::STC2L_POST:
1337 case ARM::t2LDC_POST:
1338 case ARM::t2LDCL_POST:
1339 case ARM::t2STC_POST:
1340 case ARM::t2STCL_POST:
1341 case ARM::LDC_POST:
1342 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1343 case ARM::STC_POST:
1344 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1345 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1346 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1347 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1348 // The 'option' variant doesn't encode 'U' in the immediate since
1349 // the immediate is unsigned [0,255].
1350 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1351 break;
1352 }
1353
1354 switch (Inst.getOpcode()) {
1355 case ARM::LDC_OFFSET:
1356 case ARM::LDC_PRE:
1357 case ARM::LDC_POST:
1358 case ARM::LDC_OPTION:
1359 case ARM::LDCL_OFFSET:
1360 case ARM::LDCL_PRE:
1361 case ARM::LDCL_POST:
1362 case ARM::LDCL_OPTION:
1363 case ARM::STC_OFFSET:
1364 case ARM::STC_PRE:
1365 case ARM::STC_POST:
1366 case ARM::STC_OPTION:
1367 case ARM::STCL_OFFSET:
1368 case ARM::STCL_PRE:
1369 case ARM::STCL_POST:
1370 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1372 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1373 break;
1374 default:
1375 break;
1376 }
1377
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1378 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1379}
1380
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1381static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1382DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1383 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1384 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1385
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1387 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1388 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1389 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1390 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1391 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1392 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1393 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1394
1395 // On stores, the writeback operand precedes Rt.
1396 switch (Inst.getOpcode()) {
1397 case ARM::STR_POST_IMM:
1398 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1399 case ARM::STRB_POST_IMM:
1400 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1401 case ARM::STRT_POST_REG:
1402 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1403 case ARM::STRBT_POST_REG:
1404 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1406 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1407 break;
1408 default:
1409 break;
1410 }
1411
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1413 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1414
1415 // On loads, the writeback operand comes after Rt.
1416 switch (Inst.getOpcode()) {
1417 case ARM::LDR_POST_IMM:
1418 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1419 case ARM::LDRB_POST_IMM:
1420 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421 case ARM::LDRBT_POST_REG:
1422 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1423 case ARM::LDRT_POST_REG:
1424 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1426 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1427 break;
1428 default:
1429 break;
1430 }
1431
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1433 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1434
1435 ARM_AM::AddrOpc Op = ARM_AM::add;
1436 if (!fieldFromInstruction32(Insn, 23, 1))
1437 Op = ARM_AM::sub;
1438
1439 bool writeback = (P == 0) || (W == 1);
1440 unsigned idx_mode = 0;
1441 if (P && writeback)
1442 idx_mode = ARMII::IndexModePre;
1443 else if (!P && writeback)
1444 idx_mode = ARMII::IndexModePost;
1445
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1446 if (writeback && (Rn == 15 || Rn == Rt))
1447 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1448
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1449 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1451 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1452 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1453 switch( fieldFromInstruction32(Insn, 5, 2)) {
1454 case 0:
1455 Opc = ARM_AM::lsl;
1456 break;
1457 case 1:
1458 Opc = ARM_AM::lsr;
1459 break;
1460 case 2:
1461 Opc = ARM_AM::asr;
1462 break;
1463 case 3:
1464 Opc = ARM_AM::ror;
1465 break;
1466 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1467 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468 }
1469 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1470 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1471
1472 Inst.addOperand(MCOperand::CreateImm(imm));
1473 } else {
1474 Inst.addOperand(MCOperand::CreateReg(0));
1475 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1476 Inst.addOperand(MCOperand::CreateImm(tmp));
1477 }
1478
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1480 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1481
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1482 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1483}
1484
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1485static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1486 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1487 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1488
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1489 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1490 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1491 unsigned type = fieldFromInstruction32(Val, 5, 2);
1492 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1493 unsigned U = fieldFromInstruction32(Val, 12, 1);
1494
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1495 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1496 switch (type) {
1497 case 0:
1498 ShOp = ARM_AM::lsl;
1499 break;
1500 case 1:
1501 ShOp = ARM_AM::lsr;
1502 break;
1503 case 2:
1504 ShOp = ARM_AM::asr;
1505 break;
1506 case 3:
1507 ShOp = ARM_AM::ror;
1508 break;
1509 }
1510
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512 return MCDisassembler::Fail;
1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1514 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1515 unsigned shift;
1516 if (U)
1517 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1518 else
1519 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1520 Inst.addOperand(MCOperand::CreateImm(shift));
1521
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1522 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1523}
1524
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1525static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1526DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1527 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1528 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1529
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1530 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1532 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1533 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1534 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1535 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1536 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1537 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1538 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1539
1540 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1541
1542 // For {LD,ST}RD, Rt must be even, else undefined.
1543 switch (Inst.getOpcode()) {
1544 case ARM::STRD:
1545 case ARM::STRD_PRE:
1546 case ARM::STRD_POST:
1547 case ARM::LDRD:
1548 case ARM::LDRD_PRE:
1549 case ARM::LDRD_POST:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1550 if (Rt & 0x1) return MCDisassembler::Fail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1551 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1552 default:
1553 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1554 }
1555
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1556 if (writeback) { // Writeback
1557 if (P)
1558 U |= ARMII::IndexModePre << 9;
1559 else
1560 U |= ARMII::IndexModePost << 9;
1561
1562 // On stores, the writeback operand precedes Rt.
1563 switch (Inst.getOpcode()) {
1564 case ARM::STRD:
1565 case ARM::STRD_PRE:
1566 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1567 case ARM::STRH:
1568 case ARM::STRH_PRE:
1569 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1571 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1572 break;
1573 default:
1574 break;
1575 }
1576 }
1577
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1579 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1580 switch (Inst.getOpcode()) {
1581 case ARM::STRD:
1582 case ARM::STRD_PRE:
1583 case ARM::STRD_POST:
1584 case ARM::LDRD:
1585 case ARM::LDRD_PRE:
1586 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1588 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1589 break;
1590 default:
1591 break;
1592 }
1593
1594 if (writeback) {
1595 // On loads, the writeback operand comes after Rt.
1596 switch (Inst.getOpcode()) {
1597 case ARM::LDRD:
1598 case ARM::LDRD_PRE:
1599 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1600 case ARM::LDRH:
1601 case ARM::LDRH_PRE:
1602 case ARM::LDRH_POST:
1603 case ARM::LDRSH:
1604 case ARM::LDRSH_PRE:
1605 case ARM::LDRSH_POST:
1606 case ARM::LDRSB:
1607 case ARM::LDRSB_PRE:
1608 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1609 case ARM::LDRHTr:
1610 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1612 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1613 break;
1614 default:
1615 break;
1616 }
1617 }
1618
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1620 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1621
1622 if (type) {
1623 Inst.addOperand(MCOperand::CreateReg(0));
1624 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1625 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1627 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1628 Inst.addOperand(MCOperand::CreateImm(U));
1629 }
1630
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1631 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1632 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1633
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1634 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1635}
1636
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1637static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1638 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1639 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1640
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1641 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1642 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1643
1644 switch (mode) {
1645 case 0:
1646 mode = ARM_AM::da;
1647 break;
1648 case 1:
1649 mode = ARM_AM::ia;
1650 break;
1651 case 2:
1652 mode = ARM_AM::db;
1653 break;
1654 case 3:
1655 mode = ARM_AM::ib;
1656 break;
1657 }
1658
1659 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1661 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1662
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1663 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1664}
1665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1666static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1667 unsigned Insn,
1668 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1669 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1670
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1671 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1672 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1673 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1674
1675 if (pred == 0xF) {
1676 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1677 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1678 Inst.setOpcode(ARM::RFEDA);
1679 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1680 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1681 Inst.setOpcode(ARM::RFEDA_UPD);
1682 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1683 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1684 Inst.setOpcode(ARM::RFEDB);
1685 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1686 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1687 Inst.setOpcode(ARM::RFEDB_UPD);
1688 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1689 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690 Inst.setOpcode(ARM::RFEIA);
1691 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1692 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1693 Inst.setOpcode(ARM::RFEIA_UPD);
1694 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1695 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1696 Inst.setOpcode(ARM::RFEIB);
1697 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1698 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1699 Inst.setOpcode(ARM::RFEIB_UPD);
1700 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1701 case ARM::STMDA:
1702 Inst.setOpcode(ARM::SRSDA);
1703 break;
1704 case ARM::STMDA_UPD:
1705 Inst.setOpcode(ARM::SRSDA_UPD);
1706 break;
1707 case ARM::STMDB:
1708 Inst.setOpcode(ARM::SRSDB);
1709 break;
1710 case ARM::STMDB_UPD:
1711 Inst.setOpcode(ARM::SRSDB_UPD);
1712 break;
1713 case ARM::STMIA:
1714 Inst.setOpcode(ARM::SRSIA);
1715 break;
1716 case ARM::STMIA_UPD:
1717 Inst.setOpcode(ARM::SRSIA_UPD);
1718 break;
1719 case ARM::STMIB:
1720 Inst.setOpcode(ARM::SRSIB);
1721 break;
1722 case ARM::STMIB_UPD:
1723 Inst.setOpcode(ARM::SRSIB_UPD);
1724 break;
1725 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1726 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1727 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1728
1729 // For stores (which become SRS's, the only operand is the mode.
1730 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1731 Inst.addOperand(
1732 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1733 return S;
1734 }
1735
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1736 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1737 }
1738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1740 return MCDisassembler::Fail;
1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1742 return MCDisassembler::Fail; // Tied
1743 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1744 return MCDisassembler::Fail;
1745 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1746 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1747
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1748 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1749}
1750
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1751static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1752 uint64_t Address, const void *Decoder) {
1753 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1754 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1755 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1756 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1757
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1758 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1759
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1760 // imod == '01' --> UNPREDICTABLE
1761 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1762 // return failure here. The '01' imod value is unprintable, so there's
1763 // nothing useful we could do even if we returned UNPREDICTABLE.
1764
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1765 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1766
1767 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1768 Inst.setOpcode(ARM::CPS3p);
1769 Inst.addOperand(MCOperand::CreateImm(imod));
1770 Inst.addOperand(MCOperand::CreateImm(iflags));
1771 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1772 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1773 Inst.setOpcode(ARM::CPS2p);
1774 Inst.addOperand(MCOperand::CreateImm(imod));
1775 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1776 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1777 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1778 Inst.setOpcode(ARM::CPS1p);
1779 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1780 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1781 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1782 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1783 Inst.setOpcode(ARM::CPS1p);
1784 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1785 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1786 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1787
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1788 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1789}
1790
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1791static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1792 uint64_t Address, const void *Decoder) {
1793 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1794 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1795 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1796 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1797
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1798 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1799
1800 // imod == '01' --> UNPREDICTABLE
1801 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1802 // return failure here. The '01' imod value is unprintable, so there's
1803 // nothing useful we could do even if we returned UNPREDICTABLE.
1804
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1805 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1806
1807 if (imod && M) {
1808 Inst.setOpcode(ARM::t2CPS3p);
1809 Inst.addOperand(MCOperand::CreateImm(imod));
1810 Inst.addOperand(MCOperand::CreateImm(iflags));
1811 Inst.addOperand(MCOperand::CreateImm(mode));
1812 } else if (imod && !M) {
1813 Inst.setOpcode(ARM::t2CPS2p);
1814 Inst.addOperand(MCOperand::CreateImm(imod));
1815 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1816 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1817 } else if (!imod && M) {
1818 Inst.setOpcode(ARM::t2CPS1p);
1819 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1820 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1821 } else {
1822 // imod == '00' && M == '0' --> UNPREDICTABLE
1823 Inst.setOpcode(ARM::t2CPS1p);
1824 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1825 S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1826 }
1827
1828 return S;
1829}
1830
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1831static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1832 uint64_t Address, const void *Decoder) {
1833 DecodeStatus S = MCDisassembler::Success;
1834
1835 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1836 unsigned imm = 0;
1837
1838 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1839 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1840 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1841 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1842
1843 if (Inst.getOpcode() == ARM::t2MOVTi16)
1844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848
1849 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1850 Inst.addOperand(MCOperand::CreateImm(imm));
1851
1852 return S;
1853}
1854
1855static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1856 uint64_t Address, const void *Decoder) {
1857 DecodeStatus S = MCDisassembler::Success;
1858
1859 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1860 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1861 unsigned imm = 0;
1862
1863 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1864 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1865
1866 if (Inst.getOpcode() == ARM::MOVTi16)
1867 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1868 return MCDisassembler::Fail;
1869 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1870 return MCDisassembler::Fail;
1871
1872 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1873 Inst.addOperand(MCOperand::CreateImm(imm));
1874
1875 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1876 return MCDisassembler::Fail;
1877
1878 return S;
1879}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1881static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1882 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1883 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1884
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1885 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1886 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1887 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1888 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1889 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1890
1891 if (pred == 0xF)
1892 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1893
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1895 return MCDisassembler::Fail;
1896 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1897 return MCDisassembler::Fail;
1898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1899 return MCDisassembler::Fail;
1900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1901 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1903 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1904 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1905
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1906 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1907}
1908
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1909static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1910 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1911 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1912
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1913 unsigned add = fieldFromInstruction32(Val, 12, 1);
1914 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1915 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1916
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1918 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1919
1920 if (!add) imm *= -1;
1921 if (imm == 0 && !add) imm = INT32_MIN;
1922 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1923 if (Rn == 15)
1924 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1925
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1926 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1927}
1928
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1929static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1930 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1931 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1932
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1933 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1934 unsigned U = fieldFromInstruction32(Val, 8, 1);
1935 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1936
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1938 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1939
1940 if (U)
1941 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1942 else
1943 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1944
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1945 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1946}
1947
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1948static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1949 uint64_t Address, const void *Decoder) {
1950 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1951}
1952
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1953static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1954DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1956 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1957
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1958 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1959 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1960
1961 if (pred == 0xF) {
1962 Inst.setOpcode(ARM::BLXi);
1963 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1965 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1967 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1968 }
1969
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]1970 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1971 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1972 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1973 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1974 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1975
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1976 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1977}
1978
1979
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1980static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1981 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1982 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1983
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1984 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1985 unsigned align = fieldFromInstruction32(Val, 4, 2);
1986
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1988 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1989 if (!align)
1990 Inst.addOperand(MCOperand::CreateImm(0));
1991 else
1992 Inst.addOperand(MCOperand::CreateImm(4 << align));
1993
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1994 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1995}
1996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1997static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1998 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1999 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2000
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2001 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2002 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2003 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2004 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2005 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2006 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2007
2008 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2009 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2010 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2011 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2012 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2013 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2014 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2015 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2016 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2017 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2018 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2019 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2020 return MCDisassembler::Fail;
2021 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2022 case ARM::VLD2b16:
2023 case ARM::VLD2b32:
2024 case ARM::VLD2b8:
2025 case ARM::VLD2b16wb_fixed:
2026 case ARM::VLD2b16wb_register:
2027 case ARM::VLD2b32wb_fixed:
2028 case ARM::VLD2b32wb_register:
2029 case ARM::VLD2b8wb_fixed:
2030 case ARM::VLD2b8wb_register:
2031 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2032 return MCDisassembler::Fail;
2033 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2034 default:
2035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2036 return MCDisassembler::Fail;
2037 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2038
2039 // Second output register
2040 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2041 case ARM::VLD3d8:
2042 case ARM::VLD3d16:
2043 case ARM::VLD3d32:
2044 case ARM::VLD3d8_UPD:
2045 case ARM::VLD3d16_UPD:
2046 case ARM::VLD3d32_UPD:
2047 case ARM::VLD4d8:
2048 case ARM::VLD4d16:
2049 case ARM::VLD4d32:
2050 case ARM::VLD4d8_UPD:
2051 case ARM::VLD4d16_UPD:
2052 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2054 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2055 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2056 case ARM::VLD3q8:
2057 case ARM::VLD3q16:
2058 case ARM::VLD3q32:
2059 case ARM::VLD3q8_UPD:
2060 case ARM::VLD3q16_UPD:
2061 case ARM::VLD3q32_UPD:
2062 case ARM::VLD4q8:
2063 case ARM::VLD4q16:
2064 case ARM::VLD4q32:
2065 case ARM::VLD4q8_UPD:
2066 case ARM::VLD4q16_UPD:
2067 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2069 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2070 default:
2071 break;
2072 }
2073
2074 // Third output register
2075 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2076 case ARM::VLD3d8:
2077 case ARM::VLD3d16:
2078 case ARM::VLD3d32:
2079 case ARM::VLD3d8_UPD:
2080 case ARM::VLD3d16_UPD:
2081 case ARM::VLD3d32_UPD:
2082 case ARM::VLD4d8:
2083 case ARM::VLD4d16:
2084 case ARM::VLD4d32:
2085 case ARM::VLD4d8_UPD:
2086 case ARM::VLD4d16_UPD:
2087 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2089 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2090 break;
2091 case ARM::VLD3q8:
2092 case ARM::VLD3q16:
2093 case ARM::VLD3q32:
2094 case ARM::VLD3q8_UPD:
2095 case ARM::VLD3q16_UPD:
2096 case ARM::VLD3q32_UPD:
2097 case ARM::VLD4q8:
2098 case ARM::VLD4q16:
2099 case ARM::VLD4q32:
2100 case ARM::VLD4q8_UPD:
2101 case ARM::VLD4q16_UPD:
2102 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2104 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2105 break;
2106 default:
2107 break;
2108 }
2109
2110 // Fourth output register
2111 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2112 case ARM::VLD4d8:
2113 case ARM::VLD4d16:
2114 case ARM::VLD4d32:
2115 case ARM::VLD4d8_UPD:
2116 case ARM::VLD4d16_UPD:
2117 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2118 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2119 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2120 break;
2121 case ARM::VLD4q8:
2122 case ARM::VLD4q16:
2123 case ARM::VLD4q32:
2124 case ARM::VLD4q8_UPD:
2125 case ARM::VLD4q16_UPD:
2126 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2128 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2129 break;
2130 default:
2131 break;
2132 }
2133
2134 // Writeback operand
2135 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2136 case ARM::VLD1d8wb_fixed:
2137 case ARM::VLD1d16wb_fixed:
2138 case ARM::VLD1d32wb_fixed:
2139 case ARM::VLD1d64wb_fixed:
2140 case ARM::VLD1d8wb_register:
2141 case ARM::VLD1d16wb_register:
2142 case ARM::VLD1d32wb_register:
2143 case ARM::VLD1d64wb_register:
2144 case ARM::VLD1q8wb_fixed:
2145 case ARM::VLD1q16wb_fixed:
2146 case ARM::VLD1q32wb_fixed:
2147 case ARM::VLD1q64wb_fixed:
2148 case ARM::VLD1q8wb_register:
2149 case ARM::VLD1q16wb_register:
2150 case ARM::VLD1q32wb_register:
2151 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2152 case ARM::VLD1d8Twb_fixed:
2153 case ARM::VLD1d8Twb_register:
2154 case ARM::VLD1d16Twb_fixed:
2155 case ARM::VLD1d16Twb_register:
2156 case ARM::VLD1d32Twb_fixed:
2157 case ARM::VLD1d32Twb_register:
2158 case ARM::VLD1d64Twb_fixed:
2159 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2160 case ARM::VLD1d8Qwb_fixed:
2161 case ARM::VLD1d8Qwb_register:
2162 case ARM::VLD1d16Qwb_fixed:
2163 case ARM::VLD1d16Qwb_register:
2164 case ARM::VLD1d32Qwb_fixed:
2165 case ARM::VLD1d32Qwb_register:
2166 case ARM::VLD1d64Qwb_fixed:
2167 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2168 case ARM::VLD2d8wb_fixed:
2169 case ARM::VLD2d16wb_fixed:
2170 case ARM::VLD2d32wb_fixed:
2171 case ARM::VLD2q8wb_fixed:
2172 case ARM::VLD2q16wb_fixed:
2173 case ARM::VLD2q32wb_fixed:
2174 case ARM::VLD2d8wb_register:
2175 case ARM::VLD2d16wb_register:
2176 case ARM::VLD2d32wb_register:
2177 case ARM::VLD2q8wb_register:
2178 case ARM::VLD2q16wb_register:
2179 case ARM::VLD2q32wb_register:
2180 case ARM::VLD2b8wb_fixed:
2181 case ARM::VLD2b16wb_fixed:
2182 case ARM::VLD2b32wb_fixed:
2183 case ARM::VLD2b8wb_register:
2184 case ARM::VLD2b16wb_register:
2185 case ARM::VLD2b32wb_register:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2186 case ARM::VLD3d8_UPD:
2187 case ARM::VLD3d16_UPD:
2188 case ARM::VLD3d32_UPD:
2189 case ARM::VLD3q8_UPD:
2190 case ARM::VLD3q16_UPD:
2191 case ARM::VLD3q32_UPD:
2192 case ARM::VLD4d8_UPD:
2193 case ARM::VLD4d16_UPD:
2194 case ARM::VLD4d32_UPD:
2195 case ARM::VLD4q8_UPD:
2196 case ARM::VLD4q16_UPD:
2197 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2198 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2199 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2200 break;
2201 default:
2202 break;
2203 }
2204
2205 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2206 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2207 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2208
2209 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2210 switch (Inst.getOpcode()) {
2211 default:
2212 // The below have been updated to have explicit am6offset split
2213 // between fixed and register offset. For those instructions not
2214 // yet updated, we need to add an additional reg0 operand for the
2215 // fixed variant.
2216 //
2217 // The fixed offset encodes as Rm == 0xd, so we check for that.
2218 if (Rm == 0xd) {
2219 Inst.addOperand(MCOperand::CreateReg(0));
2220 break;
2221 }
2222 // Fall through to handle the register offset variant.
2223 case ARM::VLD1d8wb_fixed:
2224 case ARM::VLD1d16wb_fixed:
2225 case ARM::VLD1d32wb_fixed:
2226 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2227 case ARM::VLD1d8Twb_fixed:
2228 case ARM::VLD1d16Twb_fixed:
2229 case ARM::VLD1d32Twb_fixed:
2230 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2231 case ARM::VLD1d8Qwb_fixed:
2232 case ARM::VLD1d16Qwb_fixed:
2233 case ARM::VLD1d32Qwb_fixed:
2234 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2235 case ARM::VLD1d8wb_register:
2236 case ARM::VLD1d16wb_register:
2237 case ARM::VLD1d32wb_register:
2238 case ARM::VLD1d64wb_register:
2239 case ARM::VLD1q8wb_fixed:
2240 case ARM::VLD1q16wb_fixed:
2241 case ARM::VLD1q32wb_fixed:
2242 case ARM::VLD1q64wb_fixed:
2243 case ARM::VLD1q8wb_register:
2244 case ARM::VLD1q16wb_register:
2245 case ARM::VLD1q32wb_register:
2246 case ARM::VLD1q64wb_register:
2247 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2248 // variant encodes Rm == 0xf. Anything else is a register offset post-
2249 // increment and we need to add the register operand to the instruction.
2250 if (Rm != 0xD && Rm != 0xF &&
2251 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2252 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2253 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2254 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2255
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2256 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2257}
2258
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2259static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2260 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2261 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2262
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2263 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2264 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2265 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2267 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2269
2270 // Writeback Operand
2271 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2272 case ARM::VST1d8wb_fixed:
2273 case ARM::VST1d16wb_fixed:
2274 case ARM::VST1d32wb_fixed:
2275 case ARM::VST1d64wb_fixed:
2276 case ARM::VST1d8wb_register:
2277 case ARM::VST1d16wb_register:
2278 case ARM::VST1d32wb_register:
2279 case ARM::VST1d64wb_register:
2280 case ARM::VST1q8wb_fixed:
2281 case ARM::VST1q16wb_fixed:
2282 case ARM::VST1q32wb_fixed:
2283 case ARM::VST1q64wb_fixed:
2284 case ARM::VST1q8wb_register:
2285 case ARM::VST1q16wb_register:
2286 case ARM::VST1q32wb_register:
2287 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2288 case ARM::VST1d8Twb_fixed:
2289 case ARM::VST1d16Twb_fixed:
2290 case ARM::VST1d32Twb_fixed:
2291 case ARM::VST1d64Twb_fixed:
2292 case ARM::VST1d8Twb_register:
2293 case ARM::VST1d16Twb_register:
2294 case ARM::VST1d32Twb_register:
2295 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2296 case ARM::VST1d8Qwb_fixed:
2297 case ARM::VST1d16Qwb_fixed:
2298 case ARM::VST1d32Qwb_fixed:
2299 case ARM::VST1d64Qwb_fixed:
2300 case ARM::VST1d8Qwb_register:
2301 case ARM::VST1d16Qwb_register:
2302 case ARM::VST1d32Qwb_register:
2303 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2304 case ARM::VST2d8wb_fixed:
2305 case ARM::VST2d16wb_fixed:
2306 case ARM::VST2d32wb_fixed:
2307 case ARM::VST2d8wb_register:
2308 case ARM::VST2d16wb_register:
2309 case ARM::VST2d32wb_register:
2310 case ARM::VST2q8wb_fixed:
2311 case ARM::VST2q16wb_fixed:
2312 case ARM::VST2q32wb_fixed:
2313 case ARM::VST2q8wb_register:
2314 case ARM::VST2q16wb_register:
2315 case ARM::VST2q32wb_register:
2316 case ARM::VST2b8wb_fixed:
2317 case ARM::VST2b16wb_fixed:
2318 case ARM::VST2b32wb_fixed:
2319 case ARM::VST2b8wb_register:
2320 case ARM::VST2b16wb_register:
2321 case ARM::VST2b32wb_register:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2322 Inst.addOperand(MCOperand::CreateImm(0));
2323 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2324 case ARM::VST3d8_UPD:
2325 case ARM::VST3d16_UPD:
2326 case ARM::VST3d32_UPD:
2327 case ARM::VST3q8_UPD:
2328 case ARM::VST3q16_UPD:
2329 case ARM::VST3q32_UPD:
2330 case ARM::VST4d8_UPD:
2331 case ARM::VST4d16_UPD:
2332 case ARM::VST4d32_UPD:
2333 case ARM::VST4q8_UPD:
2334 case ARM::VST4q16_UPD:
2335 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2336 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2337 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2338 break;
2339 default:
2340 break;
2341 }
2342
2343 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2344 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2345 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2346
2347 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2348 switch (Inst.getOpcode()) {
2349 default:
2350 if (Rm == 0xD)
2351 Inst.addOperand(MCOperand::CreateReg(0));
2352 else if (Rm != 0xF) {
2353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2354 return MCDisassembler::Fail;
2355 }
2356 break;
2357 case ARM::VST1d8wb_fixed:
2358 case ARM::VST1d16wb_fixed:
2359 case ARM::VST1d32wb_fixed:
2360 case ARM::VST1d64wb_fixed:
2361 case ARM::VST1q8wb_fixed:
2362 case ARM::VST1q16wb_fixed:
2363 case ARM::VST1q32wb_fixed:
2364 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2365 case ARM::VST1d8Twb_fixed:
2366 case ARM::VST1d16Twb_fixed:
2367 case ARM::VST1d32Twb_fixed:
2368 case ARM::VST1d64Twb_fixed:
2369 case ARM::VST1d8Qwb_fixed:
2370 case ARM::VST1d16Qwb_fixed:
2371 case ARM::VST1d32Qwb_fixed:
2372 case ARM::VST1d64Qwb_fixed:
2373 case ARM::VST2d8wb_fixed:
2374 case ARM::VST2d16wb_fixed:
2375 case ARM::VST2d32wb_fixed:
2376 case ARM::VST2q8wb_fixed:
2377 case ARM::VST2q16wb_fixed:
2378 case ARM::VST2q32wb_fixed:
2379 case ARM::VST2b8wb_fixed:
2380 case ARM::VST2b16wb_fixed:
2381 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2382 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2383 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2384
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2385
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2386 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2387 switch (Inst.getOpcode()) {
2388 case ARM::VST1q16:
2389 case ARM::VST1q32:
2390 case ARM::VST1q64:
2391 case ARM::VST1q8:
2392 case ARM::VST1q16wb_fixed:
2393 case ARM::VST1q16wb_register:
2394 case ARM::VST1q32wb_fixed:
2395 case ARM::VST1q32wb_register:
2396 case ARM::VST1q64wb_fixed:
2397 case ARM::VST1q64wb_register:
2398 case ARM::VST1q8wb_fixed:
2399 case ARM::VST1q8wb_register:
2400 case ARM::VST2d16:
2401 case ARM::VST2d32:
2402 case ARM::VST2d8:
2403 case ARM::VST2d16wb_fixed:
2404 case ARM::VST2d16wb_register:
2405 case ARM::VST2d32wb_fixed:
2406 case ARM::VST2d32wb_register:
2407 case ARM::VST2d8wb_fixed:
2408 case ARM::VST2d8wb_register:
2409 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2410 return MCDisassembler::Fail;
2411 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2412 case ARM::VST2b16:
2413 case ARM::VST2b32:
2414 case ARM::VST2b8:
2415 case ARM::VST2b16wb_fixed:
2416 case ARM::VST2b16wb_register:
2417 case ARM::VST2b32wb_fixed:
2418 case ARM::VST2b32wb_register:
2419 case ARM::VST2b8wb_fixed:
2420 case ARM::VST2b8wb_register:
2421 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2422 return MCDisassembler::Fail;
2423 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2424 default:
2425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2426 return MCDisassembler::Fail;
2427 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2428
2429 // Second input register
2430 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2431 case ARM::VST3d8:
2432 case ARM::VST3d16:
2433 case ARM::VST3d32:
2434 case ARM::VST3d8_UPD:
2435 case ARM::VST3d16_UPD:
2436 case ARM::VST3d32_UPD:
2437 case ARM::VST4d8:
2438 case ARM::VST4d16:
2439 case ARM::VST4d32:
2440 case ARM::VST4d8_UPD:
2441 case ARM::VST4d16_UPD:
2442 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2443 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2444 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2445 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2446 case ARM::VST3q8:
2447 case ARM::VST3q16:
2448 case ARM::VST3q32:
2449 case ARM::VST3q8_UPD:
2450 case ARM::VST3q16_UPD:
2451 case ARM::VST3q32_UPD:
2452 case ARM::VST4q8:
2453 case ARM::VST4q16:
2454 case ARM::VST4q32:
2455 case ARM::VST4q8_UPD:
2456 case ARM::VST4q16_UPD:
2457 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2458 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2459 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2460 break;
2461 default:
2462 break;
2463 }
2464
2465 // Third input register
2466 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2467 case ARM::VST3d8:
2468 case ARM::VST3d16:
2469 case ARM::VST3d32:
2470 case ARM::VST3d8_UPD:
2471 case ARM::VST3d16_UPD:
2472 case ARM::VST3d32_UPD:
2473 case ARM::VST4d8:
2474 case ARM::VST4d16:
2475 case ARM::VST4d32:
2476 case ARM::VST4d8_UPD:
2477 case ARM::VST4d16_UPD:
2478 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2479 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2480 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2481 break;
2482 case ARM::VST3q8:
2483 case ARM::VST3q16:
2484 case ARM::VST3q32:
2485 case ARM::VST3q8_UPD:
2486 case ARM::VST3q16_UPD:
2487 case ARM::VST3q32_UPD:
2488 case ARM::VST4q8:
2489 case ARM::VST4q16:
2490 case ARM::VST4q32:
2491 case ARM::VST4q8_UPD:
2492 case ARM::VST4q16_UPD:
2493 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2494 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2495 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2496 break;
2497 default:
2498 break;
2499 }
2500
2501 // Fourth input register
2502 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2503 case ARM::VST4d8:
2504 case ARM::VST4d16:
2505 case ARM::VST4d32:
2506 case ARM::VST4d8_UPD:
2507 case ARM::VST4d16_UPD:
2508 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2509 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2510 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2511 break;
2512 case ARM::VST4q8:
2513 case ARM::VST4q16:
2514 case ARM::VST4q32:
2515 case ARM::VST4q8_UPD:
2516 case ARM::VST4q16_UPD:
2517 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2518 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2519 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2520 break;
2521 default:
2522 break;
2523 }
2524
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2525 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2526}
2527
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2528static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2529 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2530 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2531
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2532 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2533 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2535 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2536 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2537 unsigned size = fieldFromInstruction32(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2538
2539 align *= (1 << size);
2540
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2541 switch (Inst.getOpcode()) {
2542 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2543 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2544 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2545 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2546 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2547 return MCDisassembler::Fail;
2548 break;
2549 default:
2550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2551 return MCDisassembler::Fail;
2552 break;
2553 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2554 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2556 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2557 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2558
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2560 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2561 Inst.addOperand(MCOperand::CreateImm(align));
2562
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2563 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2564 // variant encodes Rm == 0xf. Anything else is a register offset post-
2565 // increment and we need to add the register operand to the instruction.
2566 if (Rm != 0xD && Rm != 0xF &&
2567 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2568 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2569
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2570 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2571}
2572
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2573static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2574 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2575 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2576
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2577 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2578 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2579 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2580 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2581 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2582 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2583 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2584 align *= 2*size;
2585
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2586 switch (Inst.getOpcode()) {
2587 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2588 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2589 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2590 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2591 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2592 return MCDisassembler::Fail;
2593 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2594 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2595 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2596 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2597 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2598 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2599 return MCDisassembler::Fail;
2600 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2601 default:
2602 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2603 return MCDisassembler::Fail;
2604 break;
2605 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2606
2607 if (Rm != 0xF)
2608 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2609
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2611 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2612 Inst.addOperand(MCOperand::CreateImm(align));
2613
2614 if (Rm == 0xD)
2615 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2616 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2618 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2619 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2620
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2621 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2622 return MCDisassembler::Fail;
2623
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2624 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2625}
2626
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2627static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2628 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2629 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2630
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2631 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2632 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2633 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2634 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2635 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2636
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2638 return MCDisassembler::Fail;
2639 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2640 return MCDisassembler::Fail;
2641 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2642 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2643 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2645 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2646 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2649 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2650 Inst.addOperand(MCOperand::CreateImm(0));
2651
2652 if (Rm == 0xD)
2653 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2654 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2656 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2657 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2658
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2659 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2660}
2661
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2663 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2664 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2665
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2666 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2667 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2668 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2669 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2670 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2671 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2672 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2673
2674 if (size == 0x3) {
2675 size = 4;
2676 align = 16;
2677 } else {
2678 if (size == 2) {
2679 size = 1 << size;
2680 align *= 8;
2681 } else {
2682 size = 1 << size;
2683 align *= 4*size;
2684 }
2685 }
2686
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2688 return MCDisassembler::Fail;
2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2690 return MCDisassembler::Fail;
2691 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2692 return MCDisassembler::Fail;
2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2694 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2695 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2697 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2698 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2699
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2701 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2702 Inst.addOperand(MCOperand::CreateImm(align));
2703
2704 if (Rm == 0xD)
2705 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2706 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2708 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2709 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2710
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2711 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2712}
2713
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2714static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2715DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2716 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2717 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2718
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2719 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2720 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2721 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2722 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2723 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2724 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2725 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2726 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2727
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2728 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2729 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2730 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2731 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2732 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2733 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2734 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2735
2736 Inst.addOperand(MCOperand::CreateImm(imm));
2737
2738 switch (Inst.getOpcode()) {
2739 case ARM::VORRiv4i16:
2740 case ARM::VORRiv2i32:
2741 case ARM::VBICiv4i16:
2742 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2744 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2745 break;
2746 case ARM::VORRiv8i16:
2747 case ARM::VORRiv4i32:
2748 case ARM::VBICiv8i16:
2749 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2750 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2751 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2752 break;
2753 default:
2754 break;
2755 }
2756
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2757 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2758}
2759
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2761 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2762 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2763
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2764 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2765 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2766 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2767 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2768 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2769
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2770 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2771 return MCDisassembler::Fail;
2772 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2773 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2774 Inst.addOperand(MCOperand::CreateImm(8 << size));
2775
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2776 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2777}
2778
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2779static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2780 uint64_t Address, const void *Decoder) {
2781 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2782 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2783}
2784
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2785static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2786 uint64_t Address, const void *Decoder) {
2787 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2788 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2789}
2790
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2791static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2792 uint64_t Address, const void *Decoder) {
2793 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2794 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2795}
2796
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2797static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798 uint64_t Address, const void *Decoder) {
2799 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2800 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2801}
2802
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2803static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2804 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2805 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2806
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2807 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2808 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2809 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2810 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2811 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2812 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2813 unsigned op = fieldFromInstruction32(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2814
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2815 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2816 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2817 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2819 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2820 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2821
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2822 switch (Inst.getOpcode()) {
2823 case ARM::VTBL2:
2824 case ARM::VTBX2:
2825 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2826 return MCDisassembler::Fail;
2827 break;
2828 default:
2829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2830 return MCDisassembler::Fail;
2831 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2832
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2834 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2835
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2836 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2837}
2838
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2839static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2840 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2841 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2842
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2843 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2844 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2845
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2846 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2847 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2848
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2849 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2850 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2851 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2852 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2853 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2854 case ARM::tADDrSPi:
2855 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2856 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2857 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2858
2859 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2860 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2861}
2862
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2863static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2864 uint64_t Address, const void *Decoder) {
2865 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2866 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2867}
2868
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2869static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2870 uint64_t Address, const void *Decoder) {
2871 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2872 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2873}
2874
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2875static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2876 uint64_t Address, const void *Decoder) {
2877 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2878 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2879}
2880
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2881static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2882 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2883 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2884
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2885 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2886 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2887
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2888 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2889 return MCDisassembler::Fail;
2890 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2891 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2892
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2893 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894}
2895
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2896static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2897 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2898 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2901 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2902
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2903 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2904 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2905 Inst.addOperand(MCOperand::CreateImm(imm));
2906
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2907 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2908}
2909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2910static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2911 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2912 unsigned imm = Val << 2;
2913
2914 Inst.addOperand(MCOperand::CreateImm(imm));
2915 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2916
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2917 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2918}
2919
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2920static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2921 uint64_t Address, const void *Decoder) {
2922 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]2923 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2924
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2925 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2926}
2927
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2928static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2929 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2930 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2931
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2932 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2933 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2934 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2935
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2937 return MCDisassembler::Fail;
2938 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2939 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940 Inst.addOperand(MCOperand::CreateImm(imm));
2941
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2942 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943}
2944
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2945static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2948
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2949 switch (Inst.getOpcode()) {
2950 case ARM::t2PLDs:
2951 case ARM::t2PLDWs:
2952 case ARM::t2PLIs:
2953 break;
2954 default: {
2955 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]2956 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2957 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]2958 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2959 }
2960
2961 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2962 if (Rn == 0xF) {
2963 switch (Inst.getOpcode()) {
2964 case ARM::t2LDRBs:
2965 Inst.setOpcode(ARM::t2LDRBpci);
2966 break;
2967 case ARM::t2LDRHs:
2968 Inst.setOpcode(ARM::t2LDRHpci);
2969 break;
2970 case ARM::t2LDRSHs:
2971 Inst.setOpcode(ARM::t2LDRSHpci);
2972 break;
2973 case ARM::t2LDRSBs:
2974 Inst.setOpcode(ARM::t2LDRSBpci);
2975 break;
2976 case ARM::t2PLDs:
2977 Inst.setOpcode(ARM::t2PLDi12);
2978 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2979 break;
2980 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2981 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2982 }
2983
2984 int imm = fieldFromInstruction32(Insn, 0, 12);
2985 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2986 Inst.addOperand(MCOperand::CreateImm(imm));
2987
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2988 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2989 }
2990
2991 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2992 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2993 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2994 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2995 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2996
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2997 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2998}
2999
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3000static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3001 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3002 int imm = Val & 0xFF;
3003 if (!(Val & 0x100)) imm *= -1;
3004 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3005
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3006 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3007}
3008
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3009static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3010 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3011 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3012
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3013 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3014 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3015
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3017 return MCDisassembler::Fail;
3018 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3019 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3020
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3021 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3022}
3023
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3024static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
3025 uint64_t Address, const void *Decoder) {
3026 DecodeStatus S = MCDisassembler::Success;
3027
3028 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3029 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3030
3031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3032 return MCDisassembler::Fail;
3033
3034 Inst.addOperand(MCOperand::CreateImm(imm));
3035
3036 return S;
3037}
3038
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3039static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3040 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3041 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3042 if (Val == 0)
3043 imm = INT32_MIN;
3044 else if (!(Val & 0x100))
3045 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3046 Inst.addOperand(MCOperand::CreateImm(imm));
3047
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3048 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3049}
3050
3051
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3052static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3053 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3054 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3055
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3056 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3057 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3058
3059 // Some instructions always use an additive offset.
3060 switch (Inst.getOpcode()) {
3061 case ARM::t2LDRT:
3062 case ARM::t2LDRBT:
3063 case ARM::t2LDRHT:
3064 case ARM::t2LDRSBT:
3065 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3066 case ARM::t2STRT:
3067 case ARM::t2STRBT:
3068 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069 imm |= 0x100;
3070 break;
3071 default:
3072 break;
3073 }
3074
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3078 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3079
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3080 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3081}
3082
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3083static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
3084 uint64_t Address, const void *Decoder) {
3085 DecodeStatus S = MCDisassembler::Success;
3086
3087 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3088 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3089 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3090 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3091 addr |= Rn << 9;
3092 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3093
3094 if (!load) {
3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3096 return MCDisassembler::Fail;
3097 }
3098
Owen Andersone4f2df92011-09-16 22:42:36 +0000[diff] [blame]3099 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3100 return MCDisassembler::Fail;
3101
3102 if (load) {
3103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3104 return MCDisassembler::Fail;
3105 }
3106
3107 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3108 return MCDisassembler::Fail;
3109
3110 return S;
3111}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3112
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3113static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3114 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3115 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3116
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3117 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3118 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3119
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3121 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3122 Inst.addOperand(MCOperand::CreateImm(imm));
3123
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3124 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3125}
3126
3127
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3128static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3129 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3131
3132 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3133 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3134 Inst.addOperand(MCOperand::CreateImm(imm));
3135
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3136 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3137}
3138
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3139static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3140 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3141 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3142
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3143 if (Inst.getOpcode() == ARM::tADDrSP) {
3144 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3145 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3146
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3148 return MCDisassembler::Fail;
3149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3150 return MCDisassembler::Fail;
Owen Anderson99906832011-08-25 18:30:18 +0000[diff] [blame]3151 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3152 } else if (Inst.getOpcode() == ARM::tADDspr) {
3153 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3154
3155 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3156 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3158 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3159 }
3160
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3161 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3162}
3163
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3164static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3165 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3166 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3167 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3168
3169 Inst.addOperand(MCOperand::CreateImm(imod));
3170 Inst.addOperand(MCOperand::CreateImm(flags));
3171
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3172 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3173}
3174
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3175static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3176 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3177 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3178 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3179 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3180
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3182 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3183 Inst.addOperand(MCOperand::CreateImm(add));
3184
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3185 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3186}
3187
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3188static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3189 uint64_t Address, const void *Decoder) {
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3190 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3191 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3192 true, 4, Inst, Decoder))
3193 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3194 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3195}
3196
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3197static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3198 uint64_t Address, const void *Decoder) {
3199 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3200 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3201
3202 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3203 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3204}
3205
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3206static DecodeStatus
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3207DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3208 uint64_t Address, const void *Decoder) {
3209 DecodeStatus S = MCDisassembler::Success;
3210
3211 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3213
3214 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3216 return MCDisassembler::Fail;
3217 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3218 return MCDisassembler::Fail;
3219 return S;
3220}
3221
3222static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3223DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3224 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3225 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3226
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3227 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3228 if (pred == 0xE || pred == 0xF) {
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3229 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3230 switch (opc) {
3231 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3232 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3233 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3234 Inst.setOpcode(ARM::t2DSB);
3235 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3236 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3237 Inst.setOpcode(ARM::t2DMB);
3238 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3239 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3240 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3241 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3242 }
3243
3244 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3245 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3246 }
3247
3248 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3249 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3250 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3251 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3252 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3253
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3254 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3255 return MCDisassembler::Fail;
3256 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3257 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3258
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3259 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3260}
3261
3262// Decode a shifted immediate operand. These basically consist
3263// of an 8-bit value, and a 4-bit directive that specifies either
3264// a splat operation or a rotation.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3265static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3266 uint64_t Address, const void *Decoder) {
3267 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3268 if (ctrl == 0) {
3269 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3270 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3271 switch (byte) {
3272 case 0:
3273 Inst.addOperand(MCOperand::CreateImm(imm));
3274 break;
3275 case 1:
3276 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3277 break;
3278 case 2:
3279 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3280 break;
3281 case 3:
3282 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3283 (imm << 8) | imm));
3284 break;
3285 }
3286 } else {
3287 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3288 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3289 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3290 Inst.addOperand(MCOperand::CreateImm(imm));
3291 }
3292
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3293 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3294}
3295
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3296static DecodeStatus
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3297DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3298 uint64_t Address, const void *Decoder){
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3299 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3300 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3301}
3302
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3303static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3304 uint64_t Address, const void *Decoder){
Kevin Enderby09433032012-02-27 18:15:15 +0000[diff] [blame]3305 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3306 true, 4, Inst, Decoder))
3307 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3308 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3309}
3310
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3311static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3312 uint64_t Address, const void *Decoder) {
3313 switch (Val) {
3314 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3315 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3316 case 0xF: // SY
3317 case 0xE: // ST
3318 case 0xB: // ISH
3319 case 0xA: // ISHST
3320 case 0x7: // NSH
3321 case 0x6: // NSHST
3322 case 0x3: // OSH
3323 case 0x2: // OSHST
3324 break;
3325 }
3326
3327 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3328 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3329}
3330
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3331static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3332 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3333 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3334 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3335 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3336}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3337
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3338static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3339 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3340 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3341
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3342 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3343 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3344 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3345
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3346 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3347
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3349 return MCDisassembler::Fail;
3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3351 return MCDisassembler::Fail;
3352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3353 return MCDisassembler::Fail;
3354 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3355 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3356
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3357 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3358}
3359
3360
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3361static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3362 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3363 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3364
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3365 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3366 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3367 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
Owen Andersonadf2b092011-08-11 22:08:38 +0000[diff] [blame]3368 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3369
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3370 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3371 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3372
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3373 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3374 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3375
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3377 return MCDisassembler::Fail;
3378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3379 return MCDisassembler::Fail;
3380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3381 return MCDisassembler::Fail;
3382 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3383 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3384
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3385 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3386}
3387
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3388static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3389 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3390 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3391
3392 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3393 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3394 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3395 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3396 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3397 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3398
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3399 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3400
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3402 return MCDisassembler::Fail;
3403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3404 return MCDisassembler::Fail;
3405 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3406 return MCDisassembler::Fail;
3407 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3408 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3409
3410 return S;
3411}
3412
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3413static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3414 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3415 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3416
3417 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3418 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3419 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3420 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3421 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3422 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3423 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3424
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3425 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3426 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3427
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3429 return MCDisassembler::Fail;
3430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3431 return MCDisassembler::Fail;
3432 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3433 return MCDisassembler::Fail;
3434 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3435 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3436
3437 return S;
3438}
3439
3440
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3441static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3442 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3443 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3444
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3445 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3446 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3447 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3448 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3449 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3450 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3451
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3452 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3453
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3455 return MCDisassembler::Fail;
3456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3457 return MCDisassembler::Fail;
3458 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3459 return MCDisassembler::Fail;
3460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3461 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3462
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3463 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3464}
3465
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3466static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3467 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3468 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3469
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3470 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3471 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3472 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3473 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3474 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3475 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3476
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3477 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3478
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3480 return MCDisassembler::Fail;
3481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3482 return MCDisassembler::Fail;
3483 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3484 return MCDisassembler::Fail;
3485 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3486 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3487
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3488 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3489}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3490
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3491static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3492 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3493 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3494
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3495 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3496 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3498 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3499 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3500
3501 unsigned align = 0;
3502 unsigned index = 0;
3503 switch (size) {
3504 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3505 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3506 case 0:
3507 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3508 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3509 index = fieldFromInstruction32(Insn, 5, 3);
3510 break;
3511 case 1:
3512 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3513 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3514 index = fieldFromInstruction32(Insn, 6, 2);
3515 if (fieldFromInstruction32(Insn, 4, 1))
3516 align = 2;
3517 break;
3518 case 2:
3519 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3520 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3521 index = fieldFromInstruction32(Insn, 7, 1);
3522 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3523 align = 4;
3524 }
3525
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3527 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3528 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3530 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3531 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3533 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3534 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3535 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3536 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3538 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3539 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3540 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3541 }
3542
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3544 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3545 Inst.addOperand(MCOperand::CreateImm(index));
3546
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3547 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3548}
3549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3550static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3551 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3552 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3553
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3554 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3556 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3557 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3558 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3559
3560 unsigned align = 0;
3561 unsigned index = 0;
3562 switch (size) {
3563 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3564 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3565 case 0:
3566 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3567 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3568 index = fieldFromInstruction32(Insn, 5, 3);
3569 break;
3570 case 1:
3571 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3572 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3573 index = fieldFromInstruction32(Insn, 6, 2);
3574 if (fieldFromInstruction32(Insn, 4, 1))
3575 align = 2;
3576 break;
3577 case 2:
3578 if (fieldFromInstruction32(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3579 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3580 index = fieldFromInstruction32(Insn, 7, 1);
3581 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3582 align = 4;
3583 }
3584
3585 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3587 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3588 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3589 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3590 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3591 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3592 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3593 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3595 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3596 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3597 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3598 }
3599
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3601 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3602 Inst.addOperand(MCOperand::CreateImm(index));
3603
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3604 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3605}
3606
3607
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3608static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3609 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3610 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3611
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3612 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3613 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3614 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3615 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3616 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3617
3618 unsigned align = 0;
3619 unsigned index = 0;
3620 unsigned inc = 1;
3621 switch (size) {
3622 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3623 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3624 case 0:
3625 index = fieldFromInstruction32(Insn, 5, 3);
3626 if (fieldFromInstruction32(Insn, 4, 1))
3627 align = 2;
3628 break;
3629 case 1:
3630 index = fieldFromInstruction32(Insn, 6, 2);
3631 if (fieldFromInstruction32(Insn, 4, 1))
3632 align = 4;
3633 if (fieldFromInstruction32(Insn, 5, 1))
3634 inc = 2;
3635 break;
3636 case 2:
3637 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3638 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3639 index = fieldFromInstruction32(Insn, 7, 1);
3640 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3641 align = 8;
3642 if (fieldFromInstruction32(Insn, 6, 1))
3643 inc = 2;
3644 break;
3645 }
3646
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3648 return MCDisassembler::Fail;
3649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3650 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3651 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3653 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3654 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3656 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3657 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3658 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3659 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3661 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3662 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3663 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664 }
3665
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3666 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3669 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3670 Inst.addOperand(MCOperand::CreateImm(index));
3671
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3672 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3673}
3674
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3675static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3676 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3677 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3678
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3679 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3680 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3681 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3682 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3683 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3684
3685 unsigned align = 0;
3686 unsigned index = 0;
3687 unsigned inc = 1;
3688 switch (size) {
3689 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3690 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3691 case 0:
3692 index = fieldFromInstruction32(Insn, 5, 3);
3693 if (fieldFromInstruction32(Insn, 4, 1))
3694 align = 2;
3695 break;
3696 case 1:
3697 index = fieldFromInstruction32(Insn, 6, 2);
3698 if (fieldFromInstruction32(Insn, 4, 1))
3699 align = 4;
3700 if (fieldFromInstruction32(Insn, 5, 1))
3701 inc = 2;
3702 break;
3703 case 2:
3704 if (fieldFromInstruction32(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3705 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3706 index = fieldFromInstruction32(Insn, 7, 1);
3707 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3708 align = 8;
3709 if (fieldFromInstruction32(Insn, 6, 1))
3710 inc = 2;
3711 break;
3712 }
3713
3714 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3716 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3717 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3719 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3720 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3721 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3722 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3724 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3725 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3726 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3727 }
3728
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3732 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3733 Inst.addOperand(MCOperand::CreateImm(index));
3734
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3735 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3736}
3737
3738
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3739static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3740 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3741 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3742
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3743 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3744 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3745 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3746 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3747 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3748
3749 unsigned align = 0;
3750 unsigned index = 0;
3751 unsigned inc = 1;
3752 switch (size) {
3753 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3754 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3755 case 0:
3756 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3757 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3758 index = fieldFromInstruction32(Insn, 5, 3);
3759 break;
3760 case 1:
3761 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3762 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3763 index = fieldFromInstruction32(Insn, 6, 2);
3764 if (fieldFromInstruction32(Insn, 5, 1))
3765 inc = 2;
3766 break;
3767 case 2:
3768 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3769 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3770 index = fieldFromInstruction32(Insn, 7, 1);
3771 if (fieldFromInstruction32(Insn, 6, 1))
3772 inc = 2;
3773 break;
3774 }
3775
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3777 return MCDisassembler::Fail;
3778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3779 return MCDisassembler::Fail;
3780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3781 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3782
3783 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3785 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3786 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3788 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3789 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3790 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3791 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3793 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3794 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3795 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3796 }
3797
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3799 return MCDisassembler::Fail;
3800 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3803 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3804 Inst.addOperand(MCOperand::CreateImm(index));
3805
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3806 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3807}
3808
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3809static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3810 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3811 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3812
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3813 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3814 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3815 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3816 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3817 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3818
3819 unsigned align = 0;
3820 unsigned index = 0;
3821 unsigned inc = 1;
3822 switch (size) {
3823 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3824 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3825 case 0:
3826 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3827 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3828 index = fieldFromInstruction32(Insn, 5, 3);
3829 break;
3830 case 1:
3831 if (fieldFromInstruction32(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3832 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 index = fieldFromInstruction32(Insn, 6, 2);
3834 if (fieldFromInstruction32(Insn, 5, 1))
3835 inc = 2;
3836 break;
3837 case 2:
3838 if (fieldFromInstruction32(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3839 return MCDisassembler::Fail; // UNDEFINED
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3840 index = fieldFromInstruction32(Insn, 7, 1);
3841 if (fieldFromInstruction32(Insn, 6, 1))
3842 inc = 2;
3843 break;
3844 }
3845
3846 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3848 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3849 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3851 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3852 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3853 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3854 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3856 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3857 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3858 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3859 }
3860
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3862 return MCDisassembler::Fail;
3863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3864 return MCDisassembler::Fail;
3865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3866 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3867 Inst.addOperand(MCOperand::CreateImm(index));
3868
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3869 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3870}
3871
3872
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3873static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3874 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3875 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3876
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3877 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3878 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3879 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3880 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3881 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3882
3883 unsigned align = 0;
3884 unsigned index = 0;
3885 unsigned inc = 1;
3886 switch (size) {
3887 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3888 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3889 case 0:
3890 if (fieldFromInstruction32(Insn, 4, 1))
3891 align = 4;
3892 index = fieldFromInstruction32(Insn, 5, 3);
3893 break;
3894 case 1:
3895 if (fieldFromInstruction32(Insn, 4, 1))
3896 align = 8;
3897 index = fieldFromInstruction32(Insn, 6, 2);
3898 if (fieldFromInstruction32(Insn, 5, 1))
3899 inc = 2;
3900 break;
3901 case 2:
3902 if (fieldFromInstruction32(Insn, 4, 2))
3903 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3904 index = fieldFromInstruction32(Insn, 7, 1);
3905 if (fieldFromInstruction32(Insn, 6, 1))
3906 inc = 2;
3907 break;
3908 }
3909
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3911 return MCDisassembler::Fail;
3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3913 return MCDisassembler::Fail;
3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3915 return MCDisassembler::Fail;
3916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3917 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3918
3919 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3921 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3922 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3924 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3925 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3926 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3927 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3929 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3930 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3931 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3932 }
3933
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3935 return MCDisassembler::Fail;
3936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3937 return MCDisassembler::Fail;
3938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3939 return MCDisassembler::Fail;
3940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3941 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3942 Inst.addOperand(MCOperand::CreateImm(index));
3943
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3944 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3945}
3946
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3947static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3948 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3949 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3950
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3952 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3955 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3956
3957 unsigned align = 0;
3958 unsigned index = 0;
3959 unsigned inc = 1;
3960 switch (size) {
3961 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3962 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3963 case 0:
3964 if (fieldFromInstruction32(Insn, 4, 1))
3965 align = 4;
3966 index = fieldFromInstruction32(Insn, 5, 3);
3967 break;
3968 case 1:
3969 if (fieldFromInstruction32(Insn, 4, 1))
3970 align = 8;
3971 index = fieldFromInstruction32(Insn, 6, 2);
3972 if (fieldFromInstruction32(Insn, 5, 1))
3973 inc = 2;
3974 break;
3975 case 2:
3976 if (fieldFromInstruction32(Insn, 4, 2))
3977 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3978 index = fieldFromInstruction32(Insn, 7, 1);
3979 if (fieldFromInstruction32(Insn, 6, 1))
3980 inc = 2;
3981 break;
3982 }
3983
3984 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3985 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3986 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3987 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3989 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3990 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3991 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3992 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3994 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3995 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3996 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3997 }
3998
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4000 return MCDisassembler::Fail;
4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4002 return MCDisassembler::Fail;
4003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4004 return MCDisassembler::Fail;
4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4006 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4007 Inst.addOperand(MCOperand::CreateImm(index));
4008
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4009 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4010}
4011
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4012static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4013 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4014 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4015 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4016 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4018 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4019 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4020
4021 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4022 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4023
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4024 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4025 return MCDisassembler::Fail;
4026 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4027 return MCDisassembler::Fail;
4028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4029 return MCDisassembler::Fail;
4030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4031 return MCDisassembler::Fail;
4032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4033 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4034
4035 return S;
4036}
4037
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4038static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4039 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4040 DecodeStatus S = MCDisassembler::Success;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4041 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4042 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4043 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4044 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4045 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4046
4047 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4048 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4049
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4051 return MCDisassembler::Fail;
4052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4053 return MCDisassembler::Fail;
4054 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4055 return MCDisassembler::Fail;
4056 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4057 return MCDisassembler::Fail;
4058 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4059 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4060
4061 return S;
4062}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4063
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4064static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4065 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4066 DecodeStatus S = MCDisassembler::Success;
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4067 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4068 // The InstPrinter needs to have the low bit of the predicate in
4069 // the mask operand to be able to print it properly.
4070 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4071
4072 if (pred == 0xF) {
4073 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4074 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4075 }
4076
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4077 if ((mask & 0xF) == 0) {
4078 // Preserve the high bit of the mask, which is the low bit of
4079 // the predicate.
4080 mask &= 0x10;
4081 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4082 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4083 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4084
4085 Inst.addOperand(MCOperand::CreateImm(pred));
4086 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4087 return S;
4088}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4089
4090static DecodeStatus
4091DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4092 uint64_t Address, const void *Decoder) {
4093 DecodeStatus S = MCDisassembler::Success;
4094
4095 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4096 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4097 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4098 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4099 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4100 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4101 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4102 bool writeback = (W == 1) | (P == 0);
4103
4104 addr |= (U << 8) | (Rn << 9);
4105
4106 if (writeback && (Rn == Rt || Rn == Rt2))
4107 Check(S, MCDisassembler::SoftFail);
4108 if (Rt == Rt2)
4109 Check(S, MCDisassembler::SoftFail);
4110
4111 // Rt
4112 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4113 return MCDisassembler::Fail;
4114 // Rt2
4115 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 // Writeback operand
4118 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4119 return MCDisassembler::Fail;
4120 // addr
4121 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4122 return MCDisassembler::Fail;
4123
4124 return S;
4125}
4126
4127static DecodeStatus
4128DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4129 uint64_t Address, const void *Decoder) {
4130 DecodeStatus S = MCDisassembler::Success;
4131
4132 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4133 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4134 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4135 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4136 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4137 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4138 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4139 bool writeback = (W == 1) | (P == 0);
4140
4141 addr |= (U << 8) | (Rn << 9);
4142
4143 if (writeback && (Rn == Rt || Rn == Rt2))
4144 Check(S, MCDisassembler::SoftFail);
4145
4146 // Writeback operand
4147 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4148 return MCDisassembler::Fail;
4149 // Rt
4150 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4151 return MCDisassembler::Fail;
4152 // Rt2
4153 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4154 return MCDisassembler::Fail;
4155 // addr
4156 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4157 return MCDisassembler::Fail;
4158
4159 return S;
4160}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4161
4162static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4163 uint64_t Address, const void *Decoder) {
4164 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4165 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4166 if (sign1 != sign2) return MCDisassembler::Fail;
4167
4168 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4169 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4170 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4171 Val |= sign1 << 12;
4172 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4173
4174 return MCDisassembler::Success;
4175}
4176
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4177static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4178 uint64_t Address,
4179 const void *Decoder) {
4180 DecodeStatus S = MCDisassembler::Success;
4181
4182 // Shift of "asr #32" is not allowed in Thumb2 mode.
4183 if (Val == 0x20) S = MCDisassembler::SoftFail;
4184 Inst.addOperand(MCOperand::CreateImm(Val));
4185 return S;
4186}
4187
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4188static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4189 uint64_t Address, const void *Decoder) {
4190 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4191 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4193 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4194
4195 if (pred == 0xF)
4196 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4197
4198 DecodeStatus S = MCDisassembler::Success;
4199 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4200 return MCDisassembler::Fail;
4201 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4202 return MCDisassembler::Fail;
4203 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4204 return MCDisassembler::Fail;
4205 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4206 return MCDisassembler::Fail;
4207
4208 return S;
4209}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4210
4211static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
4212 uint64_t Address, const void *Decoder) {
4213 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4214 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4215 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4216 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4217 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4218 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4219
4220 DecodeStatus S = MCDisassembler::Success;
4221
4222 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4223 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4224 Inst.setOpcode(ARM::VMOVv2f32);
4225 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4226 }
4227
4228 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4229
4230 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4235
4236 return S;
4237}
4238
4239static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
4240 uint64_t Address, const void *Decoder) {
4241 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4242 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4243 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4244 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4245 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4246 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4247
4248 DecodeStatus S = MCDisassembler::Success;
4249
4250 // VMOVv4f32 is ambiguous with these decodings.
4251 if (!(imm & 0x38) && cmode == 0xF) {
4252 Inst.setOpcode(ARM::VMOVv4f32);
4253 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4254 }
4255
4256 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4257
4258 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4259 return MCDisassembler::Fail;
4260 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4261 return MCDisassembler::Fail;
4262 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4263
4264 return S;
4265}