Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 38 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 39 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
| 43 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 44 | bool map_and_fenceable, |
| 45 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 47 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 48 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 49 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 50 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 52 | struct drm_i915_gem_object *obj); |
| 53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 54 | struct drm_i915_fence_reg *fence, |
| 55 | bool enable); |
| 56 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 58 | struct shrink_control *sc); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 62 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 64 | { |
| 65 | if (obj->tiling_mode) |
| 66 | i915_gem_release_mmap(obj); |
| 67 | |
| 68 | /* As we do not have an associated fence register, we will force |
| 69 | * a tiling change if we ever need to acquire one. |
| 70 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 71 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 72 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 73 | } |
| 74 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 75 | /* some bookkeeping */ |
| 76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 77 | size_t size) |
| 78 | { |
| 79 | dev_priv->mm.object_count++; |
| 80 | dev_priv->mm.object_memory += size; |
| 81 | } |
| 82 | |
| 83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 84 | size_t size) |
| 85 | { |
| 86 | dev_priv->mm.object_count--; |
| 87 | dev_priv->mm.object_memory -= size; |
| 88 | } |
| 89 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 90 | static int |
| 91 | i915_gem_wait_for_error(struct drm_device *dev) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 92 | { |
| 93 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 94 | struct completion *x = &dev_priv->error_completion; |
| 95 | unsigned long flags; |
| 96 | int ret; |
| 97 | |
| 98 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 99 | return 0; |
| 100 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 101 | /* |
| 102 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 103 | * userspace. If it takes that long something really bad is going on and |
| 104 | * we should simply try to bail out and fail as gracefully as possible. |
| 105 | */ |
| 106 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); |
| 107 | if (ret == 0) { |
| 108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 109 | return -EIO; |
| 110 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 111 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 112 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 113 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 114 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 115 | /* GPU is hung, bump the completion count to account for |
| 116 | * the token we just consumed so that we never hit zero and |
| 117 | * end up waiting upon a subsequent completion event that |
| 118 | * will never happen. |
| 119 | */ |
| 120 | spin_lock_irqsave(&x->wait.lock, flags); |
| 121 | x->done++; |
| 122 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 123 | } |
| 124 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 125 | } |
| 126 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 128 | { |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 129 | int ret; |
| 130 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 131 | ret = i915_gem_wait_for_error(dev); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 132 | if (ret) |
| 133 | return ret; |
| 134 | |
| 135 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 136 | if (ret) |
| 137 | return ret; |
| 138 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 139 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 140 | return 0; |
| 141 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 142 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 143 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 144 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 145 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 146 | return obj->gtt_space && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 147 | } |
| 148 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 149 | int |
| 150 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 151 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 152 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 153 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 154 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 156 | return -ENODEV; |
| 157 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 158 | if (args->gtt_start >= args->gtt_end || |
| 159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 160 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 161 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 162 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 163 | if (INTEL_INFO(dev)->gen >= 5) |
| 164 | return -ENODEV; |
| 165 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 166 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 167 | i915_gem_init_global_gtt(dev, args->gtt_start, |
| 168 | args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 169 | mutex_unlock(&dev->struct_mutex); |
| 170 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 171 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 172 | } |
| 173 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 174 | int |
| 175 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 176 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 177 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 179 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 180 | struct drm_i915_gem_object *obj; |
| 181 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 182 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 183 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 184 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 185 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 186 | if (obj->pin_count) |
| 187 | pinned += obj->gtt_space->size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 188 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 189 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 190 | args->aper_size = dev_priv->mm.gtt_total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 191 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 192 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 193 | return 0; |
| 194 | } |
| 195 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 196 | static int |
| 197 | i915_gem_create(struct drm_file *file, |
| 198 | struct drm_device *dev, |
| 199 | uint64_t size, |
| 200 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 201 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 202 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 203 | int ret; |
| 204 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 205 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 206 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 207 | if (size == 0) |
| 208 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 209 | |
| 210 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 211 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 212 | if (obj == NULL) |
| 213 | return -ENOMEM; |
| 214 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 215 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 216 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 217 | drm_gem_object_release(&obj->base); |
| 218 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 219 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 220 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 221 | } |
| 222 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 223 | /* drop reference from allocate - handle holds it now */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 224 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 225 | trace_i915_gem_object_create(obj); |
| 226 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 227 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 228 | return 0; |
| 229 | } |
| 230 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 231 | int |
| 232 | i915_gem_dumb_create(struct drm_file *file, |
| 233 | struct drm_device *dev, |
| 234 | struct drm_mode_create_dumb *args) |
| 235 | { |
| 236 | /* have to work out size/pitch and return them */ |
Chris Wilson | ed0291f | 2011-03-19 08:21:45 +0000 | [diff] [blame] | 237 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 238 | args->size = args->pitch * args->height; |
| 239 | return i915_gem_create(file, dev, |
| 240 | args->size, &args->handle); |
| 241 | } |
| 242 | |
| 243 | int i915_gem_dumb_destroy(struct drm_file *file, |
| 244 | struct drm_device *dev, |
| 245 | uint32_t handle) |
| 246 | { |
| 247 | return drm_gem_handle_delete(file, handle); |
| 248 | } |
| 249 | |
| 250 | /** |
| 251 | * Creates a new mm object and returns a handle to it. |
| 252 | */ |
| 253 | int |
| 254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 255 | struct drm_file *file) |
| 256 | { |
| 257 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 258 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 259 | return i915_gem_create(file, dev, |
| 260 | args->size, &args->handle); |
| 261 | } |
| 262 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 263 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 264 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 265 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 266 | |
| 267 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 268 | obj->tiling_mode != I915_TILING_NONE; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 271 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 272 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 273 | const char *gpu_vaddr, int gpu_offset, |
| 274 | int length) |
| 275 | { |
| 276 | int ret, cpu_offset = 0; |
| 277 | |
| 278 | while (length > 0) { |
| 279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 280 | int this_length = min(cacheline_end - gpu_offset, length); |
| 281 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 282 | |
| 283 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 284 | gpu_vaddr + swizzled_gpu_offset, |
| 285 | this_length); |
| 286 | if (ret) |
| 287 | return ret + length; |
| 288 | |
| 289 | cpu_offset += this_length; |
| 290 | gpu_offset += this_length; |
| 291 | length -= this_length; |
| 292 | } |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 298 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 299 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 300 | int length) |
| 301 | { |
| 302 | int ret, cpu_offset = 0; |
| 303 | |
| 304 | while (length > 0) { |
| 305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 306 | int this_length = min(cacheline_end - gpu_offset, length); |
| 307 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 308 | |
| 309 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 310 | cpu_vaddr + cpu_offset, |
| 311 | this_length); |
| 312 | if (ret) |
| 313 | return ret + length; |
| 314 | |
| 315 | cpu_offset += this_length; |
| 316 | gpu_offset += this_length; |
| 317 | length -= this_length; |
| 318 | } |
| 319 | |
| 320 | return 0; |
| 321 | } |
| 322 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 323 | /* Per-page copy function for the shmem pread fastpath. |
| 324 | * Flushes invalid cachelines before reading the target if |
| 325 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 326 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 327 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 328 | char __user *user_data, |
| 329 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 330 | { |
| 331 | char *vaddr; |
| 332 | int ret; |
| 333 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 334 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 335 | return -EINVAL; |
| 336 | |
| 337 | vaddr = kmap_atomic(page); |
| 338 | if (needs_clflush) |
| 339 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 340 | page_length); |
| 341 | ret = __copy_to_user_inatomic(user_data, |
| 342 | vaddr + shmem_page_offset, |
| 343 | page_length); |
| 344 | kunmap_atomic(vaddr); |
| 345 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 346 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 347 | } |
| 348 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 349 | static void |
| 350 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 351 | bool swizzled) |
| 352 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 353 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 354 | unsigned long start = (unsigned long) addr; |
| 355 | unsigned long end = (unsigned long) addr + length; |
| 356 | |
| 357 | /* For swizzling simply ensure that we always flush both |
| 358 | * channels. Lame, but simple and it works. Swizzled |
| 359 | * pwrite/pread is far from a hotpath - current userspace |
| 360 | * doesn't use it at all. */ |
| 361 | start = round_down(start, 128); |
| 362 | end = round_up(end, 128); |
| 363 | |
| 364 | drm_clflush_virt_range((void *)start, end - start); |
| 365 | } else { |
| 366 | drm_clflush_virt_range(addr, length); |
| 367 | } |
| 368 | |
| 369 | } |
| 370 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 371 | /* Only difference to the fast-path function is that this can handle bit17 |
| 372 | * and uses non-atomic copy and kmap functions. */ |
| 373 | static int |
| 374 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 375 | char __user *user_data, |
| 376 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 377 | { |
| 378 | char *vaddr; |
| 379 | int ret; |
| 380 | |
| 381 | vaddr = kmap(page); |
| 382 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 383 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 384 | page_length, |
| 385 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 386 | |
| 387 | if (page_do_bit17_swizzling) |
| 388 | ret = __copy_to_user_swizzled(user_data, |
| 389 | vaddr, shmem_page_offset, |
| 390 | page_length); |
| 391 | else |
| 392 | ret = __copy_to_user(user_data, |
| 393 | vaddr + shmem_page_offset, |
| 394 | page_length); |
| 395 | kunmap(page); |
| 396 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 397 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 398 | } |
| 399 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 401 | i915_gem_shmem_pread(struct drm_device *dev, |
| 402 | struct drm_i915_gem_object *obj, |
| 403 | struct drm_i915_gem_pread *args, |
| 404 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 406 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 407 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 408 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 409 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 410 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 411 | int hit_slowpath = 0; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 412 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 413 | int needs_clflush = 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 414 | struct scatterlist *sg; |
| 415 | int i; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 418 | remain = args->size; |
| 419 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 421 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 423 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 424 | * read domain and manually flush cachelines (if required). This |
| 425 | * optimizes for the case when the gpu will dirty the data |
| 426 | * anyway again before the next pread happens. */ |
| 427 | if (obj->cache_level == I915_CACHE_NONE) |
| 428 | needs_clflush = 1; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 429 | if (obj->gtt_space) { |
| 430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
| 431 | if (ret) |
| 432 | return ret; |
| 433 | } |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 434 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 435 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 436 | ret = i915_gem_object_get_pages(obj); |
| 437 | if (ret) |
| 438 | return ret; |
| 439 | |
| 440 | i915_gem_object_pin_pages(obj); |
| 441 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 442 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 443 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 444 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 445 | struct page *page; |
| 446 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 447 | if (i < offset >> PAGE_SHIFT) |
| 448 | continue; |
| 449 | |
| 450 | if (remain <= 0) |
| 451 | break; |
| 452 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 453 | /* Operation in this page |
| 454 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 455 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 456 | * page_length = bytes to copy for this page |
| 457 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 458 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 459 | page_length = remain; |
| 460 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 461 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 462 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 463 | page = sg_page(sg); |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 464 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 465 | (page_to_phys(page) & (1 << 17)) != 0; |
| 466 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 467 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 468 | user_data, page_do_bit17_swizzling, |
| 469 | needs_clflush); |
| 470 | if (ret == 0) |
| 471 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 472 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 473 | hit_slowpath = 1; |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 474 | mutex_unlock(&dev->struct_mutex); |
| 475 | |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 476 | if (!prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 478 | /* Userspace is tricking us, but we've already clobbered |
| 479 | * its pages with the prefault and promised to write the |
| 480 | * data up to the first fault. Hence ignore any errors |
| 481 | * and just continue. */ |
| 482 | (void)ret; |
| 483 | prefaulted = 1; |
| 484 | } |
| 485 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 487 | user_data, page_do_bit17_swizzling, |
| 488 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 489 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 490 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 491 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 492 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 493 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 494 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 495 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 496 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 497 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 498 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 499 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 500 | offset += page_length; |
| 501 | } |
| 502 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 503 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 504 | i915_gem_object_unpin_pages(obj); |
| 505 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 506 | if (hit_slowpath) { |
| 507 | /* Fixup: Kill any reinstated backing storage pages */ |
| 508 | if (obj->madv == __I915_MADV_PURGED) |
| 509 | i915_gem_object_truncate(obj); |
| 510 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 511 | |
| 512 | return ret; |
| 513 | } |
| 514 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 515 | /** |
| 516 | * Reads data from the object referenced by handle. |
| 517 | * |
| 518 | * On error, the contents of *data are undefined. |
| 519 | */ |
| 520 | int |
| 521 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 522 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 523 | { |
| 524 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 525 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 526 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 527 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 528 | if (args->size == 0) |
| 529 | return 0; |
| 530 | |
| 531 | if (!access_ok(VERIFY_WRITE, |
| 532 | (char __user *)(uintptr_t)args->data_ptr, |
| 533 | args->size)) |
| 534 | return -EFAULT; |
| 535 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 536 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 537 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 538 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 539 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 541 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 542 | ret = -ENOENT; |
| 543 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 544 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 545 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 546 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 547 | if (args->offset > obj->base.size || |
| 548 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 549 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 550 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 551 | } |
| 552 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 553 | /* prime objects have no backing filp to GEM pread/pwrite |
| 554 | * pages from. |
| 555 | */ |
| 556 | if (!obj->base.filp) { |
| 557 | ret = -EINVAL; |
| 558 | goto out; |
| 559 | } |
| 560 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 561 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 562 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 563 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 564 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 565 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 566 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 567 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 568 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 569 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 570 | } |
| 571 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 572 | /* This is the fast write path which cannot handle |
| 573 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 574 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 575 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 576 | static inline int |
| 577 | fast_user_write(struct io_mapping *mapping, |
| 578 | loff_t page_base, int page_offset, |
| 579 | char __user *user_data, |
| 580 | int length) |
| 581 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 582 | void __iomem *vaddr_atomic; |
| 583 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 584 | unsigned long unwritten; |
| 585 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 586 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 587 | /* We can use the cpu mem copy function because this is X86. */ |
| 588 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 589 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 590 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 591 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 592 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 593 | } |
| 594 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 595 | /** |
| 596 | * This is the fast pwrite path, where we copy the data directly from the |
| 597 | * user into the GTT, uncached. |
| 598 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 599 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 600 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 601 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 602 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 603 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 604 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 605 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 606 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 607 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 608 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 609 | int page_offset, page_length, ret; |
| 610 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 611 | ret = i915_gem_object_pin(obj, 0, true, true); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 612 | if (ret) |
| 613 | goto out; |
| 614 | |
| 615 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 616 | if (ret) |
| 617 | goto out_unpin; |
| 618 | |
| 619 | ret = i915_gem_object_put_fence(obj); |
| 620 | if (ret) |
| 621 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 622 | |
| 623 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 624 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 625 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 626 | offset = obj->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 627 | |
| 628 | while (remain > 0) { |
| 629 | /* Operation in this page |
| 630 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 631 | * page_base = page offset within aperture |
| 632 | * page_offset = offset within page |
| 633 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 635 | page_base = offset & PAGE_MASK; |
| 636 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 637 | page_length = remain; |
| 638 | if ((page_offset + remain) > PAGE_SIZE) |
| 639 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 640 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 641 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 642 | * source page isn't available. Return the error and we'll |
| 643 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 644 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 645 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 646 | page_offset, user_data, page_length)) { |
| 647 | ret = -EFAULT; |
| 648 | goto out_unpin; |
| 649 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 650 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 651 | remain -= page_length; |
| 652 | user_data += page_length; |
| 653 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 654 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 656 | out_unpin: |
| 657 | i915_gem_object_unpin(obj); |
| 658 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 659 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 660 | } |
| 661 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 662 | /* Per-page copy function for the shmem pwrite fastpath. |
| 663 | * Flushes invalid cachelines before writing to the target if |
| 664 | * needs_clflush_before is set and flushes out any written cachelines after |
| 665 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 666 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 667 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 668 | char __user *user_data, |
| 669 | bool page_do_bit17_swizzling, |
| 670 | bool needs_clflush_before, |
| 671 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 672 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 673 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 674 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 675 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 676 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 677 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 678 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 679 | vaddr = kmap_atomic(page); |
| 680 | if (needs_clflush_before) |
| 681 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 682 | page_length); |
| 683 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 684 | user_data, |
| 685 | page_length); |
| 686 | if (needs_clflush_after) |
| 687 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 688 | page_length); |
| 689 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 690 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 691 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 692 | } |
| 693 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 694 | /* Only difference to the fast-path function is that this can handle bit17 |
| 695 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 696 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 697 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 698 | char __user *user_data, |
| 699 | bool page_do_bit17_swizzling, |
| 700 | bool needs_clflush_before, |
| 701 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 702 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 703 | char *vaddr; |
| 704 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 705 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 706 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 707 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 708 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 709 | page_length, |
| 710 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 711 | if (page_do_bit17_swizzling) |
| 712 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 713 | user_data, |
| 714 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 715 | else |
| 716 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 717 | user_data, |
| 718 | page_length); |
| 719 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 720 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 721 | page_length, |
| 722 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 723 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 724 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 725 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 726 | } |
| 727 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 728 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 729 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 730 | struct drm_i915_gem_object *obj, |
| 731 | struct drm_i915_gem_pwrite *args, |
| 732 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 733 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 734 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 735 | loff_t offset; |
| 736 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 737 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 738 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 739 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 740 | int needs_clflush_after = 0; |
| 741 | int needs_clflush_before = 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 742 | int i; |
| 743 | struct scatterlist *sg; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 744 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 745 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 746 | remain = args->size; |
| 747 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 748 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 749 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 750 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 751 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 752 | * write domain and manually flush cachelines (if required). This |
| 753 | * optimizes for the case when the gpu will use the data |
| 754 | * right away and we therefore have to clflush anyway. */ |
| 755 | if (obj->cache_level == I915_CACHE_NONE) |
| 756 | needs_clflush_after = 1; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 757 | if (obj->gtt_space) { |
| 758 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 759 | if (ret) |
| 760 | return ret; |
| 761 | } |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 762 | } |
| 763 | /* Same trick applies for invalidate partially written cachelines before |
| 764 | * writing. */ |
| 765 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) |
| 766 | && obj->cache_level == I915_CACHE_NONE) |
| 767 | needs_clflush_before = 1; |
| 768 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 769 | ret = i915_gem_object_get_pages(obj); |
| 770 | if (ret) |
| 771 | return ret; |
| 772 | |
| 773 | i915_gem_object_pin_pages(obj); |
| 774 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 775 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 776 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 778 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 779 | struct page *page; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 780 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 781 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 782 | if (i < offset >> PAGE_SHIFT) |
| 783 | continue; |
| 784 | |
| 785 | if (remain <= 0) |
| 786 | break; |
| 787 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 788 | /* Operation in this page |
| 789 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 790 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 791 | * page_length = bytes to copy for this page |
| 792 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 793 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 794 | |
| 795 | page_length = remain; |
| 796 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 797 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 798 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 799 | /* If we don't overwrite a cacheline completely we need to be |
| 800 | * careful to have up-to-date data by first clflushing. Don't |
| 801 | * overcomplicate things and flush the entire patch. */ |
| 802 | partial_cacheline_write = needs_clflush_before && |
| 803 | ((shmem_page_offset | page_length) |
| 804 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 805 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 806 | page = sg_page(sg); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 807 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 808 | (page_to_phys(page) & (1 << 17)) != 0; |
| 809 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 810 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 811 | user_data, page_do_bit17_swizzling, |
| 812 | partial_cacheline_write, |
| 813 | needs_clflush_after); |
| 814 | if (ret == 0) |
| 815 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 816 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 817 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 818 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 819 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 820 | user_data, page_do_bit17_swizzling, |
| 821 | partial_cacheline_write, |
| 822 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 823 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 824 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 825 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 826 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 827 | set_page_dirty(page); |
| 828 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 829 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 830 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 831 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 832 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 833 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 834 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 835 | offset += page_length; |
| 836 | } |
| 837 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 838 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 839 | i915_gem_object_unpin_pages(obj); |
| 840 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 841 | if (hit_slowpath) { |
| 842 | /* Fixup: Kill any reinstated backing storage pages */ |
| 843 | if (obj->madv == __I915_MADV_PURGED) |
| 844 | i915_gem_object_truncate(obj); |
| 845 | /* and flush dirty cachelines in case the object isn't in the cpu write |
| 846 | * domain anymore. */ |
| 847 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 848 | i915_gem_clflush_object(obj); |
| 849 | intel_gtt_chipset_flush(); |
| 850 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 851 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 852 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 853 | if (needs_clflush_after) |
| 854 | intel_gtt_chipset_flush(); |
| 855 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 856 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 857 | } |
| 858 | |
| 859 | /** |
| 860 | * Writes data to the object referenced by handle. |
| 861 | * |
| 862 | * On error, the contents of the buffer that were to be modified are undefined. |
| 863 | */ |
| 864 | int |
| 865 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 866 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 867 | { |
| 868 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 869 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 870 | int ret; |
| 871 | |
| 872 | if (args->size == 0) |
| 873 | return 0; |
| 874 | |
| 875 | if (!access_ok(VERIFY_READ, |
| 876 | (char __user *)(uintptr_t)args->data_ptr, |
| 877 | args->size)) |
| 878 | return -EFAULT; |
| 879 | |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 880 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 881 | args->size); |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 882 | if (ret) |
| 883 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 884 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 885 | ret = i915_mutex_lock_interruptible(dev); |
| 886 | if (ret) |
| 887 | return ret; |
| 888 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 889 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 890 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 891 | ret = -ENOENT; |
| 892 | goto unlock; |
| 893 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 894 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 895 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 896 | if (args->offset > obj->base.size || |
| 897 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 898 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 899 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 900 | } |
| 901 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 902 | /* prime objects have no backing filp to GEM pread/pwrite |
| 903 | * pages from. |
| 904 | */ |
| 905 | if (!obj->base.filp) { |
| 906 | ret = -EINVAL; |
| 907 | goto out; |
| 908 | } |
| 909 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 910 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 911 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 912 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 913 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 914 | * it would end up going through the fenced access, and we'll get |
| 915 | * different detiling behavior between reading and writing. |
| 916 | * pread/pwrite currently are reading and writing from the CPU |
| 917 | * perspective, requiring manual detiling by the client. |
| 918 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 919 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 920 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 921 | goto out; |
| 922 | } |
| 923 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 924 | if (obj->cache_level == I915_CACHE_NONE && |
Daniel Vetter | c07496f | 2012-04-13 15:51:51 +0200 | [diff] [blame] | 925 | obj->tiling_mode == I915_TILING_NONE && |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 926 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 927 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 928 | /* Note that the gtt paths might fail with non-page-backed user |
| 929 | * pointers (e.g. gtt mappings when moving data between |
| 930 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 931 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 932 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 933 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 934 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 935 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 936 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 937 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 938 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 939 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 940 | return ret; |
| 941 | } |
| 942 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 943 | int |
| 944 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, |
| 945 | bool interruptible) |
| 946 | { |
| 947 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 948 | struct completion *x = &dev_priv->error_completion; |
| 949 | bool recovery_complete; |
| 950 | unsigned long flags; |
| 951 | |
| 952 | /* Give the error handler a chance to run. */ |
| 953 | spin_lock_irqsave(&x->wait.lock, flags); |
| 954 | recovery_complete = x->done > 0; |
| 955 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 956 | |
| 957 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 958 | * -EIO unconditionally for these. */ |
| 959 | if (!interruptible) |
| 960 | return -EIO; |
| 961 | |
| 962 | /* Recovery complete, but still wedged means reset failure. */ |
| 963 | if (recovery_complete) |
| 964 | return -EIO; |
| 965 | |
| 966 | return -EAGAIN; |
| 967 | } |
| 968 | |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | /* |
| 973 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 974 | * equal. |
| 975 | */ |
| 976 | static int |
| 977 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 978 | { |
| 979 | int ret; |
| 980 | |
| 981 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 982 | |
| 983 | ret = 0; |
| 984 | if (seqno == ring->outstanding_lazy_request) |
| 985 | ret = i915_add_request(ring, NULL, NULL); |
| 986 | |
| 987 | return ret; |
| 988 | } |
| 989 | |
| 990 | /** |
| 991 | * __wait_seqno - wait until execution of seqno has finished |
| 992 | * @ring: the ring expected to report seqno |
| 993 | * @seqno: duh! |
| 994 | * @interruptible: do an interruptible wait (normally yes) |
| 995 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 996 | * |
| 997 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 998 | * errno with remaining time filled in timeout argument. |
| 999 | */ |
| 1000 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
| 1001 | bool interruptible, struct timespec *timeout) |
| 1002 | { |
| 1003 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 1004 | struct timespec before, now, wait_time={1,0}; |
| 1005 | unsigned long timeout_jiffies; |
| 1006 | long end; |
| 1007 | bool wait_forever = true; |
| 1008 | int ret; |
| 1009 | |
| 1010 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1011 | return 0; |
| 1012 | |
| 1013 | trace_i915_gem_request_wait_begin(ring, seqno); |
| 1014 | |
| 1015 | if (timeout != NULL) { |
| 1016 | wait_time = *timeout; |
| 1017 | wait_forever = false; |
| 1018 | } |
| 1019 | |
| 1020 | timeout_jiffies = timespec_to_jiffies(&wait_time); |
| 1021 | |
| 1022 | if (WARN_ON(!ring->irq_get(ring))) |
| 1023 | return -ENODEV; |
| 1024 | |
| 1025 | /* Record current time in case interrupted by signal, or wedged * */ |
| 1026 | getrawmonotonic(&before); |
| 1027 | |
| 1028 | #define EXIT_COND \ |
| 1029 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
| 1030 | atomic_read(&dev_priv->mm.wedged)) |
| 1031 | do { |
| 1032 | if (interruptible) |
| 1033 | end = wait_event_interruptible_timeout(ring->irq_queue, |
| 1034 | EXIT_COND, |
| 1035 | timeout_jiffies); |
| 1036 | else |
| 1037 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, |
| 1038 | timeout_jiffies); |
| 1039 | |
| 1040 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
| 1041 | if (ret) |
| 1042 | end = ret; |
| 1043 | } while (end == 0 && wait_forever); |
| 1044 | |
| 1045 | getrawmonotonic(&now); |
| 1046 | |
| 1047 | ring->irq_put(ring); |
| 1048 | trace_i915_gem_request_wait_end(ring, seqno); |
| 1049 | #undef EXIT_COND |
| 1050 | |
| 1051 | if (timeout) { |
| 1052 | struct timespec sleep_time = timespec_sub(now, before); |
| 1053 | *timeout = timespec_sub(*timeout, sleep_time); |
| 1054 | } |
| 1055 | |
| 1056 | switch (end) { |
| 1057 | case -EIO: |
| 1058 | case -EAGAIN: /* Wedged */ |
| 1059 | case -ERESTARTSYS: /* Signal */ |
| 1060 | return (int)end; |
| 1061 | case 0: /* Timeout */ |
| 1062 | if (timeout) |
| 1063 | set_normalized_timespec(timeout, 0, 0); |
| 1064 | return -ETIME; |
| 1065 | default: /* Completed */ |
| 1066 | WARN_ON(end < 0); /* We're not aware of other errors */ |
| 1067 | return 0; |
| 1068 | } |
| 1069 | } |
| 1070 | |
| 1071 | /** |
| 1072 | * Waits for a sequence number to be signaled, and cleans up the |
| 1073 | * request and object lists appropriately for that event. |
| 1074 | */ |
| 1075 | int |
| 1076 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
| 1077 | { |
| 1078 | struct drm_device *dev = ring->dev; |
| 1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1080 | bool interruptible = dev_priv->mm.interruptible; |
| 1081 | int ret; |
| 1082 | |
| 1083 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1084 | BUG_ON(seqno == 0); |
| 1085 | |
| 1086 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
| 1087 | if (ret) |
| 1088 | return ret; |
| 1089 | |
| 1090 | ret = i915_gem_check_olr(ring, seqno); |
| 1091 | if (ret) |
| 1092 | return ret; |
| 1093 | |
| 1094 | return __wait_seqno(ring, seqno, interruptible, NULL); |
| 1095 | } |
| 1096 | |
| 1097 | /** |
| 1098 | * Ensures that all rendering to the object has completed and the object is |
| 1099 | * safe to unbind from the GTT or access from the CPU. |
| 1100 | */ |
| 1101 | static __must_check int |
| 1102 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1103 | bool readonly) |
| 1104 | { |
| 1105 | struct intel_ring_buffer *ring = obj->ring; |
| 1106 | u32 seqno; |
| 1107 | int ret; |
| 1108 | |
| 1109 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1110 | if (seqno == 0) |
| 1111 | return 0; |
| 1112 | |
| 1113 | ret = i915_wait_seqno(ring, seqno); |
| 1114 | if (ret) |
| 1115 | return ret; |
| 1116 | |
| 1117 | i915_gem_retire_requests_ring(ring); |
| 1118 | |
| 1119 | /* Manually manage the write flush as we may have not yet |
| 1120 | * retired the buffer. |
| 1121 | */ |
| 1122 | if (obj->last_write_seqno && |
| 1123 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
| 1124 | obj->last_write_seqno = 0; |
| 1125 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1126 | } |
| 1127 | |
| 1128 | return 0; |
| 1129 | } |
| 1130 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1131 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1132 | * as the object state may change during this call. |
| 1133 | */ |
| 1134 | static __must_check int |
| 1135 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
| 1136 | bool readonly) |
| 1137 | { |
| 1138 | struct drm_device *dev = obj->base.dev; |
| 1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1140 | struct intel_ring_buffer *ring = obj->ring; |
| 1141 | u32 seqno; |
| 1142 | int ret; |
| 1143 | |
| 1144 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1145 | BUG_ON(!dev_priv->mm.interruptible); |
| 1146 | |
| 1147 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1148 | if (seqno == 0) |
| 1149 | return 0; |
| 1150 | |
| 1151 | ret = i915_gem_check_wedge(dev_priv, true); |
| 1152 | if (ret) |
| 1153 | return ret; |
| 1154 | |
| 1155 | ret = i915_gem_check_olr(ring, seqno); |
| 1156 | if (ret) |
| 1157 | return ret; |
| 1158 | |
| 1159 | mutex_unlock(&dev->struct_mutex); |
| 1160 | ret = __wait_seqno(ring, seqno, true, NULL); |
| 1161 | mutex_lock(&dev->struct_mutex); |
| 1162 | |
| 1163 | i915_gem_retire_requests_ring(ring); |
| 1164 | |
| 1165 | /* Manually manage the write flush as we may have not yet |
| 1166 | * retired the buffer. |
| 1167 | */ |
| 1168 | if (obj->last_write_seqno && |
| 1169 | i915_seqno_passed(seqno, obj->last_write_seqno)) { |
| 1170 | obj->last_write_seqno = 0; |
| 1171 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1172 | } |
| 1173 | |
| 1174 | return ret; |
| 1175 | } |
| 1176 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1177 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1178 | * Called when user space prepares to use an object with the CPU, either |
| 1179 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1180 | */ |
| 1181 | int |
| 1182 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1183 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1184 | { |
| 1185 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1186 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1187 | uint32_t read_domains = args->read_domains; |
| 1188 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1189 | int ret; |
| 1190 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1191 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1192 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1193 | return -EINVAL; |
| 1194 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1195 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1196 | return -EINVAL; |
| 1197 | |
| 1198 | /* Having something in the write domain implies it's in the read |
| 1199 | * domain, and only that read domain. Enforce that in the request. |
| 1200 | */ |
| 1201 | if (write_domain != 0 && read_domains != write_domain) |
| 1202 | return -EINVAL; |
| 1203 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1204 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1205 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1206 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1207 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1208 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1209 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1210 | ret = -ENOENT; |
| 1211 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1212 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1213 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1214 | /* Try to flush the object off the GPU without holding the lock. |
| 1215 | * We will repeat the flush holding the lock in the normal manner |
| 1216 | * to catch cases where we are gazumped. |
| 1217 | */ |
| 1218 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); |
| 1219 | if (ret) |
| 1220 | goto unref; |
| 1221 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1222 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1223 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1224 | |
| 1225 | /* Silently promote "you're not bound, there was nothing to do" |
| 1226 | * to success, since the client was just asking us to |
| 1227 | * make sure everything was done. |
| 1228 | */ |
| 1229 | if (ret == -EINVAL) |
| 1230 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1231 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1232 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1233 | } |
| 1234 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1235 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1236 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1237 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1238 | mutex_unlock(&dev->struct_mutex); |
| 1239 | return ret; |
| 1240 | } |
| 1241 | |
| 1242 | /** |
| 1243 | * Called when user space has done writes to this buffer |
| 1244 | */ |
| 1245 | int |
| 1246 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1247 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1248 | { |
| 1249 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1250 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1251 | int ret = 0; |
| 1252 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1253 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1254 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1255 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1256 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1257 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1258 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1259 | ret = -ENOENT; |
| 1260 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1261 | } |
| 1262 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1263 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1264 | if (obj->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1265 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1267 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1268 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1269 | mutex_unlock(&dev->struct_mutex); |
| 1270 | return ret; |
| 1271 | } |
| 1272 | |
| 1273 | /** |
| 1274 | * Maps the contents of an object, returning the address it is mapped |
| 1275 | * into. |
| 1276 | * |
| 1277 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1278 | * imply a ref on the object itself. |
| 1279 | */ |
| 1280 | int |
| 1281 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1282 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1283 | { |
| 1284 | struct drm_i915_gem_mmap *args = data; |
| 1285 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1286 | unsigned long addr; |
| 1287 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1288 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1289 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1290 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1291 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1292 | /* prime objects have no backing filp to GEM mmap |
| 1293 | * pages from. |
| 1294 | */ |
| 1295 | if (!obj->filp) { |
| 1296 | drm_gem_object_unreference_unlocked(obj); |
| 1297 | return -EINVAL; |
| 1298 | } |
| 1299 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1300 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1301 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1302 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1303 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1304 | if (IS_ERR((void *)addr)) |
| 1305 | return addr; |
| 1306 | |
| 1307 | args->addr_ptr = (uint64_t) addr; |
| 1308 | |
| 1309 | return 0; |
| 1310 | } |
| 1311 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1312 | /** |
| 1313 | * i915_gem_fault - fault a page into the GTT |
| 1314 | * vma: VMA in question |
| 1315 | * vmf: fault info |
| 1316 | * |
| 1317 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1318 | * from userspace. The fault handler takes care of binding the object to |
| 1319 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1320 | * only if needed based on whether the old reg is still valid or the object |
| 1321 | * is tiled) and inserting a new PTE into the faulting process. |
| 1322 | * |
| 1323 | * Note that the faulting process may involve evicting existing objects |
| 1324 | * from the GTT and/or fence registers to make room. So performance may |
| 1325 | * suffer if the GTT working set is large or there are few fence registers |
| 1326 | * left. |
| 1327 | */ |
| 1328 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1329 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1330 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1331 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1332 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1333 | pgoff_t page_offset; |
| 1334 | unsigned long pfn; |
| 1335 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1336 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1337 | |
| 1338 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1339 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1340 | PAGE_SHIFT; |
| 1341 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1342 | ret = i915_mutex_lock_interruptible(dev); |
| 1343 | if (ret) |
| 1344 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1345 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1346 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1347 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1348 | /* Now bind it into the GTT if needed */ |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1349 | if (!obj->map_and_fenceable) { |
| 1350 | ret = i915_gem_object_unbind(obj); |
| 1351 | if (ret) |
| 1352 | goto unlock; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1353 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1354 | if (!obj->gtt_space) { |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 1355 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1356 | if (ret) |
| 1357 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1358 | |
Eric Anholt | e92d03b | 2011-06-14 16:43:09 -0700 | [diff] [blame] | 1359 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1360 | if (ret) |
| 1361 | goto unlock; |
| 1362 | } |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame] | 1363 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1364 | if (!obj->has_global_gtt_mapping) |
| 1365 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 1366 | |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 1367 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1368 | if (ret) |
| 1369 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1370 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1371 | if (i915_gem_object_is_inactive(obj)) |
| 1372 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1373 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1374 | obj->fault_mappable = true; |
| 1375 | |
Daniel Vetter | dd2757f | 2012-06-07 15:55:57 +0200 | [diff] [blame] | 1376 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1377 | page_offset; |
| 1378 | |
| 1379 | /* Finally, remap it using the new GTT offset */ |
| 1380 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1381 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1382 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1383 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1384 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1385 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1386 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1387 | * chance to clean up the mess. Otherwise return the proper |
| 1388 | * SIGBUS. */ |
| 1389 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 1390 | return VM_FAULT_SIGBUS; |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1391 | case -EAGAIN: |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1392 | /* Give the error handler a chance to run and move the |
| 1393 | * objects off the GPU active list. Next time we service the |
| 1394 | * fault, we should be able to transition the page into the |
| 1395 | * GTT without touching the GPU (and so avoid further |
| 1396 | * EIO/EGAIN). If the GPU is wedged, then there is no issue |
| 1397 | * with coherency, just lost writes. |
| 1398 | */ |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1399 | set_need_resched(); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1400 | case 0: |
| 1401 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1402 | case -EINTR: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1403 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1404 | case -ENOMEM: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1405 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1406 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1407 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1408 | } |
| 1409 | } |
| 1410 | |
| 1411 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1412 | * i915_gem_release_mmap - remove physical page mappings |
| 1413 | * @obj: obj in question |
| 1414 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1415 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1416 | * relinquish ownership of the pages back to the system. |
| 1417 | * |
| 1418 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1419 | * object through the GTT and then lose the fence register due to |
| 1420 | * resource pressure. Similarly if the object has been moved out of the |
| 1421 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1422 | * mapping will then trigger a page fault on the next user access, allowing |
| 1423 | * fixup by i915_gem_fault(). |
| 1424 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1425 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1426 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1427 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1428 | if (!obj->fault_mappable) |
| 1429 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1430 | |
Chris Wilson | f6e4788 | 2011-03-20 21:09:12 +0000 | [diff] [blame] | 1431 | if (obj->base.dev->dev_mapping) |
| 1432 | unmap_mapping_range(obj->base.dev->dev_mapping, |
| 1433 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
| 1434 | obj->base.size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1435 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1436 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1437 | } |
| 1438 | |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1439 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1440 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1441 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1442 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1443 | |
| 1444 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1445 | tiling_mode == I915_TILING_NONE) |
| 1446 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1447 | |
| 1448 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1449 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1450 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1451 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1452 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1453 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1454 | while (gtt_size < size) |
| 1455 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1456 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1457 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1458 | } |
| 1459 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1460 | /** |
| 1461 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1462 | * @obj: object to check |
| 1463 | * |
| 1464 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1465 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1466 | */ |
| 1467 | static uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1468 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
| 1469 | uint32_t size, |
| 1470 | int tiling_mode) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1471 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1472 | /* |
| 1473 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1474 | * if a fence register is needed for the object. |
| 1475 | */ |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1476 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1477 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1478 | return 4096; |
| 1479 | |
| 1480 | /* |
| 1481 | * Previous chips need to be aligned to the size of the smallest |
| 1482 | * fence register that can contain the object. |
| 1483 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1484 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1485 | } |
| 1486 | |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1487 | /** |
| 1488 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
| 1489 | * unfenced object |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1490 | * @dev: the device |
| 1491 | * @size: size of the object |
| 1492 | * @tiling_mode: tiling mode of the object |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1493 | * |
| 1494 | * Return the required GTT alignment for an object, only taking into account |
| 1495 | * unfenced tiled surface requirements. |
| 1496 | */ |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 1497 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1498 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
| 1499 | uint32_t size, |
| 1500 | int tiling_mode) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1501 | { |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1502 | /* |
| 1503 | * Minimum alignment is 4k (GTT page size) for sane hw. |
| 1504 | */ |
| 1505 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1506 | tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1507 | return 4096; |
| 1508 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1509 | /* Previous hardware however needs to be aligned to a power-of-two |
| 1510 | * tile height. The simplest method for determining this is to reuse |
| 1511 | * the power-of-tile object size. |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1512 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1513 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1514 | } |
| 1515 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1516 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1517 | { |
| 1518 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1519 | int ret; |
| 1520 | |
| 1521 | if (obj->base.map_list.map) |
| 1522 | return 0; |
| 1523 | |
| 1524 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1525 | if (ret != -ENOSPC) |
| 1526 | return ret; |
| 1527 | |
| 1528 | /* Badly fragmented mmap space? The only way we can recover |
| 1529 | * space is by destroying unwanted objects. We can't randomly release |
| 1530 | * mmap_offsets as userspace expects them to be persistent for the |
| 1531 | * lifetime of the objects. The closest we can is to release the |
| 1532 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1533 | * which prevents userspace from ever using that object again. |
| 1534 | */ |
| 1535 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1536 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1537 | if (ret != -ENOSPC) |
| 1538 | return ret; |
| 1539 | |
| 1540 | i915_gem_shrink_all(dev_priv); |
| 1541 | return drm_gem_create_mmap_offset(&obj->base); |
| 1542 | } |
| 1543 | |
| 1544 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1545 | { |
| 1546 | if (!obj->base.map_list.map) |
| 1547 | return; |
| 1548 | |
| 1549 | drm_gem_free_mmap_offset(&obj->base); |
| 1550 | } |
| 1551 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1552 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1553 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1554 | struct drm_device *dev, |
| 1555 | uint32_t handle, |
| 1556 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1557 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1558 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1559 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1560 | int ret; |
| 1561 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1562 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1563 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1564 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1565 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1566 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1567 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1568 | ret = -ENOENT; |
| 1569 | goto unlock; |
| 1570 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1571 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1572 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1573 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1574 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1575 | } |
| 1576 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1577 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1578 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1579 | ret = -EINVAL; |
| 1580 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1581 | } |
| 1582 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1583 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1584 | if (ret) |
| 1585 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1586 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1587 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1588 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1589 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1590 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1591 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1592 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1593 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1594 | } |
| 1595 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1596 | /** |
| 1597 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1598 | * @dev: DRM device |
| 1599 | * @data: GTT mapping ioctl data |
| 1600 | * @file: GEM object info |
| 1601 | * |
| 1602 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1603 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1604 | * up so we can get faults in the handler above. |
| 1605 | * |
| 1606 | * The fault handler will take care of binding the object into the GTT |
| 1607 | * (since it may have been evicted to make room for something), allocating |
| 1608 | * a fence register, and mapping the appropriate aperture address into |
| 1609 | * userspace. |
| 1610 | */ |
| 1611 | int |
| 1612 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1613 | struct drm_file *file) |
| 1614 | { |
| 1615 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1616 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1617 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1618 | } |
| 1619 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1620 | /* Immediately discard the backing storage */ |
| 1621 | static void |
| 1622 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1623 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1624 | struct inode *inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1625 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1626 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1627 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1628 | if (obj->base.filp == NULL) |
| 1629 | return; |
| 1630 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1631 | /* Our goal here is to return as much of the memory as |
| 1632 | * is possible back to the system as we are called from OOM. |
| 1633 | * To do this we must instruct the shmfs to drop all of its |
| 1634 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1635 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1636 | inode = obj->base.filp->f_path.dentry->d_inode; |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1637 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1638 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1639 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1640 | } |
| 1641 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1642 | static inline int |
| 1643 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1644 | { |
| 1645 | return obj->madv == I915_MADV_DONTNEED; |
| 1646 | } |
| 1647 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1648 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1649 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1650 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1651 | int page_count = obj->base.size / PAGE_SIZE; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1652 | struct scatterlist *sg; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1653 | int ret, i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1654 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1655 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1656 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1657 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1658 | if (ret) { |
| 1659 | /* In the event of a disaster, abandon all caches and |
| 1660 | * hope for the best. |
| 1661 | */ |
| 1662 | WARN_ON(ret != -EIO); |
| 1663 | i915_gem_clflush_object(obj); |
| 1664 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1665 | } |
| 1666 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1667 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1668 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1669 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1670 | if (obj->madv == I915_MADV_DONTNEED) |
| 1671 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1672 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1673 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
| 1674 | struct page *page = sg_page(sg); |
| 1675 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1676 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1677 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1678 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1679 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1680 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1681 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1682 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1683 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1684 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1685 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1686 | sg_free_table(obj->pages); |
| 1687 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1688 | } |
| 1689 | |
| 1690 | static int |
| 1691 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1692 | { |
| 1693 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1694 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1695 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1696 | return 0; |
| 1697 | |
| 1698 | BUG_ON(obj->gtt_space); |
| 1699 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1700 | if (obj->pages_pin_count) |
| 1701 | return -EBUSY; |
| 1702 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1703 | ops->put_pages(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1704 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1705 | |
| 1706 | list_del(&obj->gtt_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1707 | if (i915_gem_object_is_purgeable(obj)) |
| 1708 | i915_gem_object_truncate(obj); |
| 1709 | |
| 1710 | return 0; |
| 1711 | } |
| 1712 | |
| 1713 | static long |
| 1714 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 1715 | { |
| 1716 | struct drm_i915_gem_object *obj, *next; |
| 1717 | long count = 0; |
| 1718 | |
| 1719 | list_for_each_entry_safe(obj, next, |
| 1720 | &dev_priv->mm.unbound_list, |
| 1721 | gtt_list) { |
| 1722 | if (i915_gem_object_is_purgeable(obj) && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1723 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1724 | count += obj->base.size >> PAGE_SHIFT; |
| 1725 | if (count >= target) |
| 1726 | return count; |
| 1727 | } |
| 1728 | } |
| 1729 | |
| 1730 | list_for_each_entry_safe(obj, next, |
| 1731 | &dev_priv->mm.inactive_list, |
| 1732 | mm_list) { |
| 1733 | if (i915_gem_object_is_purgeable(obj) && |
| 1734 | i915_gem_object_unbind(obj) == 0 && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1735 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1736 | count += obj->base.size >> PAGE_SHIFT; |
| 1737 | if (count >= target) |
| 1738 | return count; |
| 1739 | } |
| 1740 | } |
| 1741 | |
| 1742 | return count; |
| 1743 | } |
| 1744 | |
| 1745 | static void |
| 1746 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 1747 | { |
| 1748 | struct drm_i915_gem_object *obj, *next; |
| 1749 | |
| 1750 | i915_gem_evict_everything(dev_priv->dev); |
| 1751 | |
| 1752 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1753 | i915_gem_object_put_pages(obj); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1754 | } |
| 1755 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1756 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1757 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1758 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1759 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1760 | int page_count, i; |
| 1761 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1762 | struct sg_table *st; |
| 1763 | struct scatterlist *sg; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1764 | struct page *page; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1765 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1766 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1767 | /* Assert that the object is not currently in any GPU domain. As it |
| 1768 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1769 | * a GPU cache |
| 1770 | */ |
| 1771 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 1772 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 1773 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1774 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 1775 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1776 | return -ENOMEM; |
| 1777 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1778 | page_count = obj->base.size / PAGE_SIZE; |
| 1779 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
| 1780 | sg_free_table(st); |
| 1781 | kfree(st); |
| 1782 | return -ENOMEM; |
| 1783 | } |
| 1784 | |
| 1785 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1786 | * at this point until we release them. |
| 1787 | * |
| 1788 | * Fail silently without starting the shrinker |
| 1789 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1790 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
| 1791 | gfp = mapping_gfp_mask(mapping); |
Sedat Dilek | d7c3b93 | 2012-08-27 14:02:37 +0200 | [diff] [blame] | 1792 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1793 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1794 | for_each_sg(st->sgl, sg, page_count, i) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1795 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1796 | if (IS_ERR(page)) { |
| 1797 | i915_gem_purge(dev_priv, page_count); |
| 1798 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1799 | } |
| 1800 | if (IS_ERR(page)) { |
| 1801 | /* We've tried hard to allocate the memory by reaping |
| 1802 | * our own buffer, now let the real VM do its job and |
| 1803 | * go down in flames if truly OOM. |
| 1804 | */ |
Sedat Dilek | d7c3b93 | 2012-08-27 14:02:37 +0200 | [diff] [blame] | 1805 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1806 | gfp |= __GFP_IO | __GFP_WAIT; |
| 1807 | |
| 1808 | i915_gem_shrink_all(dev_priv); |
| 1809 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1810 | if (IS_ERR(page)) |
| 1811 | goto err_pages; |
| 1812 | |
Sedat Dilek | d7c3b93 | 2012-08-27 14:02:37 +0200 | [diff] [blame] | 1813 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1814 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 1815 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1816 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1817 | sg_set_page(sg, page, PAGE_SIZE, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1818 | } |
| 1819 | |
| 1820 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1821 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1822 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1823 | obj->pages = st; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | return 0; |
| 1825 | |
| 1826 | err_pages: |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1827 | for_each_sg(st->sgl, sg, i, page_count) |
| 1828 | page_cache_release(sg_page(sg)); |
| 1829 | sg_free_table(st); |
| 1830 | kfree(st); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1831 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1832 | } |
| 1833 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1834 | /* Ensure that the associated pages are gathered from the backing storage |
| 1835 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 1836 | * multiple times before they are released by a single call to |
| 1837 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 1838 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 1839 | * or as the object is itself released. |
| 1840 | */ |
| 1841 | int |
| 1842 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 1843 | { |
| 1844 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1845 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1846 | int ret; |
| 1847 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1848 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1849 | return 0; |
| 1850 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1851 | BUG_ON(obj->pages_pin_count); |
| 1852 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1853 | ret = ops->get_pages(obj); |
| 1854 | if (ret) |
| 1855 | return ret; |
| 1856 | |
| 1857 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
| 1858 | return 0; |
| 1859 | } |
| 1860 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 1861 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1862 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1863 | struct intel_ring_buffer *ring, |
| 1864 | u32 seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1865 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1866 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1868 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1869 | BUG_ON(ring == NULL); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1870 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1871 | |
| 1872 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1873 | if (!obj->active) { |
| 1874 | drm_gem_object_reference(&obj->base); |
| 1875 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1876 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1877 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1878 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1879 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
| 1880 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1881 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1882 | obj->last_read_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1883 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1884 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1885 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1886 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 1887 | /* Bump MRU to take account of the delayed flush */ |
| 1888 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 1889 | struct drm_i915_fence_reg *reg; |
| 1890 | |
| 1891 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 1892 | list_move_tail(®->lru_list, |
| 1893 | &dev_priv->mm.fence_list); |
| 1894 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1895 | } |
| 1896 | } |
| 1897 | |
| 1898 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1899 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 1900 | { |
| 1901 | struct drm_device *dev = obj->base.dev; |
| 1902 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1903 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1904 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1905 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1906 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 1907 | if (obj->pin_count) /* are we a framebuffer? */ |
| 1908 | intel_mark_fb_idle(obj); |
| 1909 | |
| 1910 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 1911 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1912 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1913 | obj->ring = NULL; |
| 1914 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1915 | obj->last_read_seqno = 0; |
| 1916 | obj->last_write_seqno = 0; |
| 1917 | obj->base.write_domain = 0; |
| 1918 | |
| 1919 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1920 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1921 | |
| 1922 | obj->active = 0; |
| 1923 | drm_gem_object_unreference(&obj->base); |
| 1924 | |
| 1925 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1926 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1927 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1928 | static u32 |
| 1929 | i915_gem_get_seqno(struct drm_device *dev) |
| 1930 | { |
| 1931 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1932 | u32 seqno = dev_priv->next_seqno; |
| 1933 | |
| 1934 | /* reserve 0 for non-seqno */ |
| 1935 | if (++dev_priv->next_seqno == 0) |
| 1936 | dev_priv->next_seqno = 1; |
| 1937 | |
| 1938 | return seqno; |
| 1939 | } |
| 1940 | |
| 1941 | u32 |
| 1942 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
| 1943 | { |
| 1944 | if (ring->outstanding_lazy_request == 0) |
| 1945 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); |
| 1946 | |
| 1947 | return ring->outstanding_lazy_request; |
| 1948 | } |
| 1949 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1950 | int |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1951 | i915_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1952 | struct drm_file *file, |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1953 | struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1954 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1955 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1956 | uint32_t seqno; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1957 | u32 request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1958 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1959 | int ret; |
| 1960 | |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 1961 | /* |
| 1962 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 1963 | * after having emitted the batchbuffer command. Hence we need to fix |
| 1964 | * things up similar to emitting the lazy request. The difference here |
| 1965 | * is that the flush _must_ happen before the next request, no matter |
| 1966 | * what. |
| 1967 | */ |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 1968 | ret = intel_ring_flush_all_caches(ring); |
| 1969 | if (ret) |
| 1970 | return ret; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 1971 | |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 1972 | if (request == NULL) { |
| 1973 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
| 1974 | if (request == NULL) |
| 1975 | return -ENOMEM; |
| 1976 | } |
| 1977 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 1978 | seqno = i915_gem_next_request_seqno(ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1979 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1980 | /* Record the position of the start of the request so that |
| 1981 | * should we detect the updated seqno part-way through the |
| 1982 | * GPU processing the request, we never over-estimate the |
| 1983 | * position of the head. |
| 1984 | */ |
| 1985 | request_ring_position = intel_ring_get_tail(ring); |
| 1986 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1987 | ret = ring->add_request(ring, &seqno); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 1988 | if (ret) { |
| 1989 | kfree(request); |
| 1990 | return ret; |
| 1991 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1992 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1993 | trace_i915_gem_request_add(ring, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1994 | |
| 1995 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1996 | request->ring = ring; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1997 | request->tail = request_ring_position; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1998 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1999 | was_empty = list_empty(&ring->request_list); |
| 2000 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2001 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2002 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2003 | if (file) { |
| 2004 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2005 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2006 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2007 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2008 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2009 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2010 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2011 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2012 | |
Daniel Vetter | 5391d0c | 2012-01-25 14:03:57 +0100 | [diff] [blame] | 2013 | ring->outstanding_lazy_request = 0; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2014 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2015 | if (!dev_priv->mm.suspended) { |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2016 | if (i915_enable_hangcheck) { |
| 2017 | mod_timer(&dev_priv->hangcheck_timer, |
Chris Wilson | cecc21f | 2012-10-05 17:02:56 +0100 | [diff] [blame^] | 2018 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2019 | } |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2020 | if (was_empty) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 2021 | queue_delayed_work(dev_priv->wq, |
| 2022 | &dev_priv->mm.retire_work, HZ); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2023 | intel_mark_busy(dev_priv->dev); |
| 2024 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2025 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2026 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2027 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2028 | } |
| 2029 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2030 | static inline void |
| 2031 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2032 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2033 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2034 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2035 | if (!file_priv) |
| 2036 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2037 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2038 | spin_lock(&file_priv->mm.lock); |
Herton Ronaldo Krzesinski | 09bfa51 | 2011-03-17 13:45:12 +0000 | [diff] [blame] | 2039 | if (request->file_priv) { |
| 2040 | list_del(&request->client_list); |
| 2041 | request->file_priv = NULL; |
| 2042 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2043 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2044 | } |
| 2045 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2046 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 2047 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2048 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2049 | while (!list_empty(&ring->request_list)) { |
| 2050 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2051 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2052 | request = list_first_entry(&ring->request_list, |
| 2053 | struct drm_i915_gem_request, |
| 2054 | list); |
| 2055 | |
| 2056 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2057 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2058 | kfree(request); |
| 2059 | } |
| 2060 | |
| 2061 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2062 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2063 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2064 | obj = list_first_entry(&ring->active_list, |
| 2065 | struct drm_i915_gem_object, |
| 2066 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2067 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2068 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2069 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2070 | } |
| 2071 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2072 | static void i915_gem_reset_fences(struct drm_device *dev) |
| 2073 | { |
| 2074 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2075 | int i; |
| 2076 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2077 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2078 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2079 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2080 | i915_gem_write_fence(dev, i, NULL); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2081 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2082 | if (reg->obj) |
| 2083 | i915_gem_object_fence_lost(reg->obj); |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2084 | |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2085 | reg->pin_count = 0; |
| 2086 | reg->obj = NULL; |
| 2087 | INIT_LIST_HEAD(®->lru_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2088 | } |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 2089 | |
| 2090 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2091 | } |
| 2092 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2093 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2094 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2095 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2096 | struct drm_i915_gem_object *obj; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2097 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2098 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2099 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2100 | for_each_ring(ring, dev_priv, i) |
| 2101 | i915_gem_reset_ring_lists(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2102 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2103 | /* Move everything out of the GPU domains to ensure we do any |
| 2104 | * necessary invalidation upon reuse. |
| 2105 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2106 | list_for_each_entry(obj, |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2107 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2108 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2109 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2110 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 2111 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2112 | |
| 2113 | /* The fence registers are invalidated so clear them out */ |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2114 | i915_gem_reset_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | } |
| 2116 | |
| 2117 | /** |
| 2118 | * This function clears the request list as sequence numbers are passed. |
| 2119 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2120 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2121 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2122 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2123 | uint32_t seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2124 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2125 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2126 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2127 | return; |
| 2128 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2129 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2131 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2132 | |
Chris Wilson | 076e2c0 | 2011-01-21 10:07:18 +0000 | [diff] [blame] | 2133 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2134 | if (seqno >= ring->sync_seqno[i]) |
| 2135 | ring->sync_seqno[i] = 0; |
| 2136 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2137 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2138 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2139 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2140 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2141 | struct drm_i915_gem_request, |
| 2142 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2143 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2144 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2145 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2146 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2147 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2148 | /* We know the GPU must have read the request to have |
| 2149 | * sent us the seqno + interrupt, so use the position |
| 2150 | * of tail of the request to update the last known position |
| 2151 | * of the GPU head. |
| 2152 | */ |
| 2153 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2154 | |
| 2155 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2156 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2157 | kfree(request); |
| 2158 | } |
| 2159 | |
| 2160 | /* Move any buffers on the active list that are no longer referenced |
| 2161 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 2162 | */ |
| 2163 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2164 | struct drm_i915_gem_object *obj; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2165 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2166 | obj = list_first_entry(&ring->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2167 | struct drm_i915_gem_object, |
| 2168 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2169 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2170 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2171 | break; |
| 2172 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2173 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2174 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2175 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2176 | if (unlikely(ring->trace_irq_seqno && |
| 2177 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2178 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2179 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2180 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2181 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2182 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2183 | } |
| 2184 | |
| 2185 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2186 | i915_gem_retire_requests(struct drm_device *dev) |
| 2187 | { |
| 2188 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2189 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2190 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2191 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2192 | for_each_ring(ring, dev_priv, i) |
| 2193 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2194 | } |
| 2195 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2196 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2197 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2198 | { |
| 2199 | drm_i915_private_t *dev_priv; |
| 2200 | struct drm_device *dev; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2201 | struct intel_ring_buffer *ring; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2202 | bool idle; |
| 2203 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2204 | |
| 2205 | dev_priv = container_of(work, drm_i915_private_t, |
| 2206 | mm.retire_work.work); |
| 2207 | dev = dev_priv->dev; |
| 2208 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2209 | /* Come back later if the device is busy... */ |
| 2210 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 2211 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 2212 | return; |
| 2213 | } |
| 2214 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2215 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2216 | |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2217 | /* Send a periodic flush down the ring so we don't hold onto GEM |
| 2218 | * objects indefinitely. |
| 2219 | */ |
| 2220 | idle = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2221 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2222 | if (ring->gpu_caches_dirty) |
| 2223 | i915_add_request(ring, NULL, NULL); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2224 | |
| 2225 | idle &= list_empty(&ring->request_list); |
| 2226 | } |
| 2227 | |
| 2228 | if (!dev_priv->mm.suspended && !idle) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2229 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2230 | if (idle) |
| 2231 | intel_mark_idle(dev); |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2232 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2233 | mutex_unlock(&dev->struct_mutex); |
| 2234 | } |
| 2235 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2236 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2237 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2238 | * write domains, emitting any outstanding lazy request and retiring and |
| 2239 | * completed requests. |
| 2240 | */ |
| 2241 | static int |
| 2242 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2243 | { |
| 2244 | int ret; |
| 2245 | |
| 2246 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2247 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2248 | if (ret) |
| 2249 | return ret; |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2250 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2251 | i915_gem_retire_requests_ring(obj->ring); |
| 2252 | } |
| 2253 | |
| 2254 | return 0; |
| 2255 | } |
| 2256 | |
| 2257 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2258 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2259 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2260 | * |
| 2261 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2262 | * the timeout parameter. |
| 2263 | * -ETIME: object is still busy after timeout |
| 2264 | * -ERESTARTSYS: signal interrupted the wait |
| 2265 | * -ENONENT: object doesn't exist |
| 2266 | * Also possible, but rare: |
| 2267 | * -EAGAIN: GPU wedged |
| 2268 | * -ENOMEM: damn |
| 2269 | * -ENODEV: Internal IRQ fail |
| 2270 | * -E?: The add request failed |
| 2271 | * |
| 2272 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2273 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2274 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2275 | * without holding struct_mutex the object may become re-busied before this |
| 2276 | * function completes. A similar but shorter * race condition exists in the busy |
| 2277 | * ioctl |
| 2278 | */ |
| 2279 | int |
| 2280 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2281 | { |
| 2282 | struct drm_i915_gem_wait *args = data; |
| 2283 | struct drm_i915_gem_object *obj; |
| 2284 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2285 | struct timespec timeout_stack, *timeout = NULL; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2286 | u32 seqno = 0; |
| 2287 | int ret = 0; |
| 2288 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2289 | if (args->timeout_ns >= 0) { |
| 2290 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2291 | timeout = &timeout_stack; |
| 2292 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2293 | |
| 2294 | ret = i915_mutex_lock_interruptible(dev); |
| 2295 | if (ret) |
| 2296 | return ret; |
| 2297 | |
| 2298 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2299 | if (&obj->base == NULL) { |
| 2300 | mutex_unlock(&dev->struct_mutex); |
| 2301 | return -ENOENT; |
| 2302 | } |
| 2303 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2304 | /* Need to make sure the object gets inactive eventually. */ |
| 2305 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2306 | if (ret) |
| 2307 | goto out; |
| 2308 | |
| 2309 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2310 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2311 | ring = obj->ring; |
| 2312 | } |
| 2313 | |
| 2314 | if (seqno == 0) |
| 2315 | goto out; |
| 2316 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2317 | /* Do this after OLR check to make sure we make forward progress polling |
| 2318 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2319 | */ |
| 2320 | if (!args->timeout_ns) { |
| 2321 | ret = -ETIME; |
| 2322 | goto out; |
| 2323 | } |
| 2324 | |
| 2325 | drm_gem_object_unreference(&obj->base); |
| 2326 | mutex_unlock(&dev->struct_mutex); |
| 2327 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2328 | ret = __wait_seqno(ring, seqno, true, timeout); |
| 2329 | if (timeout) { |
| 2330 | WARN_ON(!timespec_valid(timeout)); |
| 2331 | args->timeout_ns = timespec_to_ns(timeout); |
| 2332 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2333 | return ret; |
| 2334 | |
| 2335 | out: |
| 2336 | drm_gem_object_unreference(&obj->base); |
| 2337 | mutex_unlock(&dev->struct_mutex); |
| 2338 | return ret; |
| 2339 | } |
| 2340 | |
| 2341 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2342 | * i915_gem_object_sync - sync an object to a ring. |
| 2343 | * |
| 2344 | * @obj: object which may be in use on another ring. |
| 2345 | * @to: ring we wish to use the object on. May be NULL. |
| 2346 | * |
| 2347 | * This code is meant to abstract object synchronization with the GPU. |
| 2348 | * Calling with NULL implies synchronizing the object with the CPU |
| 2349 | * rather than a particular GPU ring. |
| 2350 | * |
| 2351 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2352 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2353 | int |
| 2354 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2355 | struct intel_ring_buffer *to) |
| 2356 | { |
| 2357 | struct intel_ring_buffer *from = obj->ring; |
| 2358 | u32 seqno; |
| 2359 | int ret, idx; |
| 2360 | |
| 2361 | if (from == NULL || to == from) |
| 2362 | return 0; |
| 2363 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2364 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2365 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2366 | |
| 2367 | idx = intel_ring_sync_index(from, to); |
| 2368 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2369 | seqno = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2370 | if (seqno <= from->sync_seqno[idx]) |
| 2371 | return 0; |
| 2372 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2373 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2374 | if (ret) |
| 2375 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2376 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2377 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2378 | if (!ret) |
| 2379 | from->sync_seqno[idx] = seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2380 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2381 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2382 | } |
| 2383 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2384 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2385 | { |
| 2386 | u32 old_write_domain, old_read_domains; |
| 2387 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2388 | /* Act a barrier for all accesses through the GTT */ |
| 2389 | mb(); |
| 2390 | |
| 2391 | /* Force a pagefault for domain tracking on next user access */ |
| 2392 | i915_gem_release_mmap(obj); |
| 2393 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2394 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2395 | return; |
| 2396 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2397 | old_read_domains = obj->base.read_domains; |
| 2398 | old_write_domain = obj->base.write_domain; |
| 2399 | |
| 2400 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2401 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2402 | |
| 2403 | trace_i915_gem_object_change_domain(obj, |
| 2404 | old_read_domains, |
| 2405 | old_write_domain); |
| 2406 | } |
| 2407 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2408 | /** |
| 2409 | * Unbinds an object from the GTT aperture. |
| 2410 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2411 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2412 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2413 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2414 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2415 | int ret = 0; |
| 2416 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2417 | if (obj->gtt_space == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2418 | return 0; |
| 2419 | |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2420 | if (obj->pin_count) |
| 2421 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2422 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2423 | BUG_ON(obj->pages == NULL); |
| 2424 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2425 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2426 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2427 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2428 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2429 | * should be safe and we need to cleanup or else we might |
| 2430 | * cause memory corruption through use-after-free. |
| 2431 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2432 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2433 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2434 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2435 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2436 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2437 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2438 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2439 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2440 | trace_i915_gem_object_unbind(obj); |
| 2441 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 2442 | if (obj->has_global_gtt_mapping) |
| 2443 | i915_gem_gtt_unbind_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2444 | if (obj->has_aliasing_ppgtt_mapping) { |
| 2445 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); |
| 2446 | obj->has_aliasing_ppgtt_mapping = 0; |
| 2447 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2448 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2449 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2450 | list_del(&obj->mm_list); |
| 2451 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2452 | /* Avoid an unnecessary call to unbind on rebind. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2453 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2454 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2455 | drm_mm_put_block(obj->gtt_space); |
| 2456 | obj->gtt_space = NULL; |
| 2457 | obj->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2458 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2459 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2460 | } |
| 2461 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2462 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2463 | { |
Chris Wilson | 69c2fc8 | 2012-07-20 12:41:03 +0100 | [diff] [blame] | 2464 | if (list_empty(&ring->active_list)) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2465 | return 0; |
| 2466 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2467 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2468 | } |
| 2469 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2470 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2471 | { |
| 2472 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2473 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2474 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2475 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2476 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2477 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2478 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2479 | if (ret) |
| 2480 | return ret; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2481 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2482 | ret = i915_ring_idle(ring); |
Ben Widawsky | f2ef6eb | 2012-06-04 14:42:53 -0700 | [diff] [blame] | 2483 | if (ret) |
| 2484 | return ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2485 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2486 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2487 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2488 | } |
| 2489 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2490 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
| 2491 | struct drm_i915_gem_object *obj) |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2492 | { |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2493 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2494 | uint64_t val; |
| 2495 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2496 | if (obj) { |
| 2497 | u32 size = obj->gtt_space->size; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2498 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2499 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2500 | 0xfffff000) << 32; |
| 2501 | val |= obj->gtt_offset & 0xfffff000; |
| 2502 | val |= (uint64_t)((obj->stride / 128) - 1) << |
| 2503 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2504 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2505 | if (obj->tiling_mode == I915_TILING_Y) |
| 2506 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2507 | val |= I965_FENCE_REG_VALID; |
| 2508 | } else |
| 2509 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2510 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2511 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
| 2512 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2513 | } |
| 2514 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2515 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2516 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2517 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2518 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2519 | uint64_t val; |
| 2520 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2521 | if (obj) { |
| 2522 | u32 size = obj->gtt_space->size; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2523 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2524 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
| 2525 | 0xfffff000) << 32; |
| 2526 | val |= obj->gtt_offset & 0xfffff000; |
| 2527 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2528 | if (obj->tiling_mode == I915_TILING_Y) |
| 2529 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2530 | val |= I965_FENCE_REG_VALID; |
| 2531 | } else |
| 2532 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2533 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2534 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
| 2535 | POSTING_READ(FENCE_REG_965_0 + reg * 8); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2536 | } |
| 2537 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2538 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2539 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2540 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2541 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2542 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2543 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2544 | if (obj) { |
| 2545 | u32 size = obj->gtt_space->size; |
| 2546 | int pitch_val; |
| 2547 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2548 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2549 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2550 | (size & -size) != size || |
| 2551 | (obj->gtt_offset & (size - 1)), |
| 2552 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2553 | obj->gtt_offset, obj->map_and_fenceable, size); |
| 2554 | |
| 2555 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2556 | tile_width = 128; |
| 2557 | else |
| 2558 | tile_width = 512; |
| 2559 | |
| 2560 | /* Note: pitch better be a power of two tile widths */ |
| 2561 | pitch_val = obj->stride / tile_width; |
| 2562 | pitch_val = ffs(pitch_val) - 1; |
| 2563 | |
| 2564 | val = obj->gtt_offset; |
| 2565 | if (obj->tiling_mode == I915_TILING_Y) |
| 2566 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2567 | val |= I915_FENCE_SIZE_BITS(size); |
| 2568 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2569 | val |= I830_FENCE_REG_VALID; |
| 2570 | } else |
| 2571 | val = 0; |
| 2572 | |
| 2573 | if (reg < 8) |
| 2574 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2575 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2576 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2577 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2578 | I915_WRITE(reg, val); |
| 2579 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2580 | } |
| 2581 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2582 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2583 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2584 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2585 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2586 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2587 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2588 | if (obj) { |
| 2589 | u32 size = obj->gtt_space->size; |
| 2590 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2591 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2592 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
| 2593 | (size & -size) != size || |
| 2594 | (obj->gtt_offset & (size - 1)), |
| 2595 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", |
| 2596 | obj->gtt_offset, size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2597 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2598 | pitch_val = obj->stride / 128; |
| 2599 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2600 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2601 | val = obj->gtt_offset; |
| 2602 | if (obj->tiling_mode == I915_TILING_Y) |
| 2603 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2604 | val |= I830_FENCE_SIZE_BITS(size); |
| 2605 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2606 | val |= I830_FENCE_REG_VALID; |
| 2607 | } else |
| 2608 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2609 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2610 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2611 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2612 | } |
| 2613 | |
| 2614 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2615 | struct drm_i915_gem_object *obj) |
| 2616 | { |
| 2617 | switch (INTEL_INFO(dev)->gen) { |
| 2618 | case 7: |
| 2619 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; |
| 2620 | case 5: |
| 2621 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2622 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2623 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
| 2624 | default: break; |
| 2625 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2626 | } |
| 2627 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2628 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2629 | struct drm_i915_fence_reg *fence) |
| 2630 | { |
| 2631 | return fence - dev_priv->fence_regs; |
| 2632 | } |
| 2633 | |
| 2634 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2635 | struct drm_i915_fence_reg *fence, |
| 2636 | bool enable) |
| 2637 | { |
| 2638 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2639 | int reg = fence_number(dev_priv, fence); |
| 2640 | |
| 2641 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
| 2642 | |
| 2643 | if (enable) { |
| 2644 | obj->fence_reg = reg; |
| 2645 | fence->obj = obj; |
| 2646 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 2647 | } else { |
| 2648 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 2649 | fence->obj = NULL; |
| 2650 | list_del_init(&fence->lru_list); |
| 2651 | } |
| 2652 | } |
| 2653 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2654 | static int |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2655 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2656 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 2657 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2658 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 2659 | if (ret) |
| 2660 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2661 | |
| 2662 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2663 | } |
| 2664 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 2665 | /* Ensure that all CPU reads are completed before installing a fence |
| 2666 | * and all writes before removing the fence. |
| 2667 | */ |
| 2668 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) |
| 2669 | mb(); |
| 2670 | |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 2671 | obj->fenced_gpu_access = false; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2672 | return 0; |
| 2673 | } |
| 2674 | |
| 2675 | int |
| 2676 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 2677 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2678 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2679 | int ret; |
| 2680 | |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2681 | ret = i915_gem_object_flush_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2682 | if (ret) |
| 2683 | return ret; |
| 2684 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2685 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 2686 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2687 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2688 | i915_gem_object_update_fence(obj, |
| 2689 | &dev_priv->fence_regs[obj->fence_reg], |
| 2690 | false); |
| 2691 | i915_gem_object_fence_lost(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2692 | |
| 2693 | return 0; |
| 2694 | } |
| 2695 | |
| 2696 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 2697 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2698 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2699 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2700 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2701 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2702 | |
| 2703 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2704 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2705 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2706 | reg = &dev_priv->fence_regs[i]; |
| 2707 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2708 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2709 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2710 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2711 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2712 | } |
| 2713 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2714 | if (avail == NULL) |
| 2715 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2716 | |
| 2717 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2718 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2719 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2720 | continue; |
| 2721 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2722 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2723 | } |
| 2724 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 2725 | return NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2726 | } |
| 2727 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2728 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2729 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2730 | * @obj: object to map through a fence reg |
| 2731 | * |
| 2732 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2733 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2734 | * This function walks the fence regs looking for a free one for @obj, |
| 2735 | * stealing one if it can't find any. |
| 2736 | * |
| 2737 | * It then sets up the reg based on the object's properties: address, pitch |
| 2738 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2739 | * |
| 2740 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2741 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2742 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2743 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2744 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2745 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2746 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2747 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2748 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2749 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2750 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2751 | /* Have we updated the tiling parameters upon the object and so |
| 2752 | * will need to serialise the write to the associated fence register? |
| 2753 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2754 | if (obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2755 | ret = i915_gem_object_flush_fence(obj); |
| 2756 | if (ret) |
| 2757 | return ret; |
| 2758 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2759 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2760 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2761 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2762 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2763 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2764 | list_move_tail(®->lru_list, |
| 2765 | &dev_priv->mm.fence_list); |
| 2766 | return 0; |
| 2767 | } |
| 2768 | } else if (enable) { |
| 2769 | reg = i915_find_fence_reg(dev); |
| 2770 | if (reg == NULL) |
| 2771 | return -EDEADLK; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2772 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2773 | if (reg->obj) { |
| 2774 | struct drm_i915_gem_object *old = reg->obj; |
| 2775 | |
| 2776 | ret = i915_gem_object_flush_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2777 | if (ret) |
| 2778 | return ret; |
| 2779 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2780 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 2781 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2782 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2783 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2784 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2785 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 2786 | obj->fence_dirty = false; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 2787 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2788 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2789 | } |
| 2790 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2791 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 2792 | struct drm_mm_node *gtt_space, |
| 2793 | unsigned long cache_level) |
| 2794 | { |
| 2795 | struct drm_mm_node *other; |
| 2796 | |
| 2797 | /* On non-LLC machines we have to be careful when putting differing |
| 2798 | * types of snoopable memory together to avoid the prefetcher |
| 2799 | * crossing memory domains and dieing. |
| 2800 | */ |
| 2801 | if (HAS_LLC(dev)) |
| 2802 | return true; |
| 2803 | |
| 2804 | if (gtt_space == NULL) |
| 2805 | return true; |
| 2806 | |
| 2807 | if (list_empty(>t_space->node_list)) |
| 2808 | return true; |
| 2809 | |
| 2810 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 2811 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 2812 | return false; |
| 2813 | |
| 2814 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 2815 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 2816 | return false; |
| 2817 | |
| 2818 | return true; |
| 2819 | } |
| 2820 | |
| 2821 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 2822 | { |
| 2823 | #if WATCH_GTT |
| 2824 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2825 | struct drm_i915_gem_object *obj; |
| 2826 | int err = 0; |
| 2827 | |
| 2828 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { |
| 2829 | if (obj->gtt_space == NULL) { |
| 2830 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 2831 | err++; |
| 2832 | continue; |
| 2833 | } |
| 2834 | |
| 2835 | if (obj->cache_level != obj->gtt_space->color) { |
| 2836 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
| 2837 | obj->gtt_space->start, |
| 2838 | obj->gtt_space->start + obj->gtt_space->size, |
| 2839 | obj->cache_level, |
| 2840 | obj->gtt_space->color); |
| 2841 | err++; |
| 2842 | continue; |
| 2843 | } |
| 2844 | |
| 2845 | if (!i915_gem_valid_gtt_space(dev, |
| 2846 | obj->gtt_space, |
| 2847 | obj->cache_level)) { |
| 2848 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
| 2849 | obj->gtt_space->start, |
| 2850 | obj->gtt_space->start + obj->gtt_space->size, |
| 2851 | obj->cache_level); |
| 2852 | err++; |
| 2853 | continue; |
| 2854 | } |
| 2855 | } |
| 2856 | |
| 2857 | WARN_ON(err); |
| 2858 | #endif |
| 2859 | } |
| 2860 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2861 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2862 | * Finds free space in the GTT aperture and binds the object there. |
| 2863 | */ |
| 2864 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2865 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2866 | unsigned alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2867 | bool map_and_fenceable, |
| 2868 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2869 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2870 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2871 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2872 | struct drm_mm_node *free_space; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2873 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2874 | bool mappable, fenceable; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2875 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2876 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2877 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2878 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2879 | return -EINVAL; |
| 2880 | } |
| 2881 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2882 | fence_size = i915_gem_get_gtt_size(dev, |
| 2883 | obj->base.size, |
| 2884 | obj->tiling_mode); |
| 2885 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 2886 | obj->base.size, |
| 2887 | obj->tiling_mode); |
| 2888 | unfenced_alignment = |
| 2889 | i915_gem_get_unfenced_gtt_alignment(dev, |
| 2890 | obj->base.size, |
| 2891 | obj->tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2892 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2893 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 2894 | alignment = map_and_fenceable ? fence_alignment : |
| 2895 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2896 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2897 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2898 | return -EINVAL; |
| 2899 | } |
| 2900 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2901 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2902 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2903 | /* If the object is bigger than the entire aperture, reject it early |
| 2904 | * before evicting everything in a vain attempt to find space. |
| 2905 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2906 | if (obj->base.size > |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2907 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2908 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2909 | return -E2BIG; |
| 2910 | } |
| 2911 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2912 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2913 | if (ret) |
| 2914 | return ret; |
| 2915 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2916 | search_free: |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2917 | if (map_and_fenceable) |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2918 | free_space = |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2919 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
| 2920 | size, alignment, obj->cache_level, |
| 2921 | 0, dev_priv->mm.gtt_mappable_end, |
| 2922 | false); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2923 | else |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2924 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
| 2925 | size, alignment, obj->cache_level, |
| 2926 | false); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2927 | |
| 2928 | if (free_space != NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2929 | if (map_and_fenceable) |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2930 | obj->gtt_space = |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2931 | drm_mm_get_block_range_generic(free_space, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2932 | size, alignment, obj->cache_level, |
Chris Wilson | 6b9d89b | 2012-07-10 11:15:23 +0100 | [diff] [blame] | 2933 | 0, dev_priv->mm.gtt_mappable_end, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2934 | false); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2935 | else |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2936 | obj->gtt_space = |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2937 | drm_mm_get_block_generic(free_space, |
| 2938 | size, alignment, obj->cache_level, |
| 2939 | false); |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2940 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2941 | if (obj->gtt_space == NULL) { |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2942 | ret = i915_gem_evict_something(dev, size, alignment, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2943 | obj->cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 2944 | map_and_fenceable, |
| 2945 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2946 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2947 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2948 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2949 | goto search_free; |
| 2950 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2951 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
| 2952 | obj->gtt_space, |
| 2953 | obj->cache_level))) { |
| 2954 | drm_mm_put_block(obj->gtt_space); |
| 2955 | obj->gtt_space = NULL; |
| 2956 | return -EINVAL; |
| 2957 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2958 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2959 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2960 | ret = i915_gem_gtt_prepare_object(obj); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2961 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2962 | drm_mm_put_block(obj->gtt_space); |
| 2963 | obj->gtt_space = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2964 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2965 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2966 | |
Daniel Vetter | 0ebb982 | 2012-02-15 23:50:24 +0100 | [diff] [blame] | 2967 | if (!dev_priv->mm.aliasing_ppgtt) |
| 2968 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2969 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2970 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2971 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2972 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 2973 | obj->gtt_offset = obj->gtt_space->start; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2974 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2975 | fenceable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2976 | obj->gtt_space->size == fence_size && |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2977 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2978 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2979 | mappable = |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2980 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2981 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2982 | obj->map_and_fenceable = mappable && fenceable; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2983 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2984 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2985 | i915_gem_verify_gtt(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2986 | return 0; |
| 2987 | } |
| 2988 | |
| 2989 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2990 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2991 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2992 | /* If we don't have a page list set up, then we're not pinned |
| 2993 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2994 | * again at bind time. |
| 2995 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2996 | if (obj->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2997 | return; |
| 2998 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 2999 | /* If the GPU is snooping the contents of the CPU cache, |
| 3000 | * we do not need to manually clear the CPU cache lines. However, |
| 3001 | * the caches are only snooped when the render cache is |
| 3002 | * flushed/invalidated. As we always have to emit invalidations |
| 3003 | * and flushes when moving into and out of the RENDER domain, correct |
| 3004 | * snooping behaviour occurs naturally as the result of our domain |
| 3005 | * tracking. |
| 3006 | */ |
| 3007 | if (obj->cache_level != I915_CACHE_NONE) |
| 3008 | return; |
| 3009 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3010 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 3011 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3012 | drm_clflush_sg(obj->pages); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3013 | } |
| 3014 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3015 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3016 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3017 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3018 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3019 | uint32_t old_write_domain; |
| 3020 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3021 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3022 | return; |
| 3023 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3024 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3025 | * to it immediately go to main memory as far as we know, so there's |
| 3026 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3027 | * |
| 3028 | * However, we do have to enforce the order so that all writes through |
| 3029 | * the GTT land before any writes to the device, such as updates to |
| 3030 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3031 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3032 | wmb(); |
| 3033 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3034 | old_write_domain = obj->base.write_domain; |
| 3035 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3036 | |
| 3037 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3038 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3039 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3040 | } |
| 3041 | |
| 3042 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3043 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3044 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3045 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3046 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3047 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3048 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3049 | return; |
| 3050 | |
| 3051 | i915_gem_clflush_object(obj); |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 3052 | intel_gtt_chipset_flush(); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3053 | old_write_domain = obj->base.write_domain; |
| 3054 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3055 | |
| 3056 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3057 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3058 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3059 | } |
| 3060 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3061 | /** |
| 3062 | * Moves a single object to the GTT read, and possibly write domain. |
| 3063 | * |
| 3064 | * This function returns when the move is complete, including waiting on |
| 3065 | * flushes to occur. |
| 3066 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3067 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3068 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3069 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3070 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3071 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3072 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3073 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3074 | /* Not valid to be called on unbound objects. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3075 | if (obj->gtt_space == NULL) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3076 | return -EINVAL; |
| 3077 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3078 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3079 | return 0; |
| 3080 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3081 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3082 | if (ret) |
| 3083 | return ret; |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 3084 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3085 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3086 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3087 | old_write_domain = obj->base.write_domain; |
| 3088 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3089 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3090 | /* It should now be out of any other write domains, and we can update |
| 3091 | * the domain values for our changes. |
| 3092 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3093 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3094 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3095 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3096 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3097 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3098 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3099 | } |
| 3100 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3101 | trace_i915_gem_object_change_domain(obj, |
| 3102 | old_read_domains, |
| 3103 | old_write_domain); |
| 3104 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3105 | /* And bump the LRU for this access */ |
| 3106 | if (i915_gem_object_is_inactive(obj)) |
| 3107 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
| 3108 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3109 | return 0; |
| 3110 | } |
| 3111 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3112 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3113 | enum i915_cache_level cache_level) |
| 3114 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3115 | struct drm_device *dev = obj->base.dev; |
| 3116 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3117 | int ret; |
| 3118 | |
| 3119 | if (obj->cache_level == cache_level) |
| 3120 | return 0; |
| 3121 | |
| 3122 | if (obj->pin_count) { |
| 3123 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3124 | return -EBUSY; |
| 3125 | } |
| 3126 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3127 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
| 3128 | ret = i915_gem_object_unbind(obj); |
| 3129 | if (ret) |
| 3130 | return ret; |
| 3131 | } |
| 3132 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3133 | if (obj->gtt_space) { |
| 3134 | ret = i915_gem_object_finish_gpu(obj); |
| 3135 | if (ret) |
| 3136 | return ret; |
| 3137 | |
| 3138 | i915_gem_object_finish_gtt(obj); |
| 3139 | |
| 3140 | /* Before SandyBridge, you could not use tiling or fence |
| 3141 | * registers with snooped memory, so relinquish any fences |
| 3142 | * currently pointing to our region in the aperture. |
| 3143 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3144 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3145 | ret = i915_gem_object_put_fence(obj); |
| 3146 | if (ret) |
| 3147 | return ret; |
| 3148 | } |
| 3149 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3150 | if (obj->has_global_gtt_mapping) |
| 3151 | i915_gem_gtt_bind_object(obj, cache_level); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3152 | if (obj->has_aliasing_ppgtt_mapping) |
| 3153 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, |
| 3154 | obj, cache_level); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3155 | |
| 3156 | obj->gtt_space->color = cache_level; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3157 | } |
| 3158 | |
| 3159 | if (cache_level == I915_CACHE_NONE) { |
| 3160 | u32 old_read_domains, old_write_domain; |
| 3161 | |
| 3162 | /* If we're coming from LLC cached, then we haven't |
| 3163 | * actually been tracking whether the data is in the |
| 3164 | * CPU cache or not, since we only allow one bit set |
| 3165 | * in obj->write_domain and have been skipping the clflushes. |
| 3166 | * Just set it to the CPU cache for now. |
| 3167 | */ |
| 3168 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
| 3169 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); |
| 3170 | |
| 3171 | old_read_domains = obj->base.read_domains; |
| 3172 | old_write_domain = obj->base.write_domain; |
| 3173 | |
| 3174 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3175 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3176 | |
| 3177 | trace_i915_gem_object_change_domain(obj, |
| 3178 | old_read_domains, |
| 3179 | old_write_domain); |
| 3180 | } |
| 3181 | |
| 3182 | obj->cache_level = cache_level; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3183 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3184 | return 0; |
| 3185 | } |
| 3186 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3187 | int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, |
| 3188 | struct drm_file *file) |
| 3189 | { |
| 3190 | struct drm_i915_gem_cacheing *args = data; |
| 3191 | struct drm_i915_gem_object *obj; |
| 3192 | int ret; |
| 3193 | |
| 3194 | ret = i915_mutex_lock_interruptible(dev); |
| 3195 | if (ret) |
| 3196 | return ret; |
| 3197 | |
| 3198 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3199 | if (&obj->base == NULL) { |
| 3200 | ret = -ENOENT; |
| 3201 | goto unlock; |
| 3202 | } |
| 3203 | |
| 3204 | args->cacheing = obj->cache_level != I915_CACHE_NONE; |
| 3205 | |
| 3206 | drm_gem_object_unreference(&obj->base); |
| 3207 | unlock: |
| 3208 | mutex_unlock(&dev->struct_mutex); |
| 3209 | return ret; |
| 3210 | } |
| 3211 | |
| 3212 | int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, |
| 3213 | struct drm_file *file) |
| 3214 | { |
| 3215 | struct drm_i915_gem_cacheing *args = data; |
| 3216 | struct drm_i915_gem_object *obj; |
| 3217 | enum i915_cache_level level; |
| 3218 | int ret; |
| 3219 | |
| 3220 | ret = i915_mutex_lock_interruptible(dev); |
| 3221 | if (ret) |
| 3222 | return ret; |
| 3223 | |
| 3224 | switch (args->cacheing) { |
| 3225 | case I915_CACHEING_NONE: |
| 3226 | level = I915_CACHE_NONE; |
| 3227 | break; |
| 3228 | case I915_CACHEING_CACHED: |
| 3229 | level = I915_CACHE_LLC; |
| 3230 | break; |
| 3231 | default: |
| 3232 | return -EINVAL; |
| 3233 | } |
| 3234 | |
| 3235 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3236 | if (&obj->base == NULL) { |
| 3237 | ret = -ENOENT; |
| 3238 | goto unlock; |
| 3239 | } |
| 3240 | |
| 3241 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3242 | |
| 3243 | drm_gem_object_unreference(&obj->base); |
| 3244 | unlock: |
| 3245 | mutex_unlock(&dev->struct_mutex); |
| 3246 | return ret; |
| 3247 | } |
| 3248 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3249 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3250 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3251 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3252 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3253 | */ |
| 3254 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3255 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3256 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3257 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3258 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3259 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3260 | int ret; |
| 3261 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3262 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3263 | ret = i915_gem_object_sync(obj, pipelined); |
| 3264 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3265 | return ret; |
| 3266 | } |
| 3267 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3268 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3269 | * a result, we make sure that the pinning that is about to occur is |
| 3270 | * done with uncached PTEs. This is lowest common denominator for all |
| 3271 | * chipsets. |
| 3272 | * |
| 3273 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3274 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3275 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3276 | */ |
| 3277 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); |
| 3278 | if (ret) |
| 3279 | return ret; |
| 3280 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3281 | /* As the user may map the buffer once pinned in the display plane |
| 3282 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3283 | * always use map_and_fenceable for all scanout buffers. |
| 3284 | */ |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3285 | ret = i915_gem_object_pin(obj, alignment, true, false); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3286 | if (ret) |
| 3287 | return ret; |
| 3288 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3289 | i915_gem_object_flush_cpu_write_domain(obj); |
| 3290 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3291 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3292 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3293 | |
| 3294 | /* It should now be out of any other write domains, and we can update |
| 3295 | * the domain values for our changes. |
| 3296 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3297 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3298 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3299 | |
| 3300 | trace_i915_gem_object_change_domain(obj, |
| 3301 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3302 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3303 | |
| 3304 | return 0; |
| 3305 | } |
| 3306 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3307 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3308 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3309 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3310 | int ret; |
| 3311 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3312 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3313 | return 0; |
| 3314 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3315 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3316 | if (ret) |
| 3317 | return ret; |
| 3318 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3319 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3320 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3321 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3322 | } |
| 3323 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3324 | /** |
| 3325 | * Moves a single object to the CPU read, and possibly write domain. |
| 3326 | * |
| 3327 | * This function returns when the move is complete, including waiting on |
| 3328 | * flushes to occur. |
| 3329 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3330 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3331 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3332 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3333 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3334 | int ret; |
| 3335 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3336 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3337 | return 0; |
| 3338 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3339 | ret = i915_gem_object_wait_rendering(obj, !write); |
| 3340 | if (ret) |
| 3341 | return ret; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3342 | |
| 3343 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3344 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3345 | old_write_domain = obj->base.write_domain; |
| 3346 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3347 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3348 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3349 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3350 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3351 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3352 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3353 | } |
| 3354 | |
| 3355 | /* It should now be out of any other write domains, and we can update |
| 3356 | * the domain values for our changes. |
| 3357 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3358 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3359 | |
| 3360 | /* If we're writing through the CPU, then the GPU read domains will |
| 3361 | * need to be invalidated at next use. |
| 3362 | */ |
| 3363 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3364 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3365 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3366 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3367 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3368 | trace_i915_gem_object_change_domain(obj, |
| 3369 | old_read_domains, |
| 3370 | old_write_domain); |
| 3371 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3372 | return 0; |
| 3373 | } |
| 3374 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3375 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3376 | * emitted over 20 msec ago. |
| 3377 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3378 | * Note that if we were to use the current jiffies each time around the loop, |
| 3379 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3380 | * render a frame was over 20ms. |
| 3381 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3382 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3383 | * relatively low latency when blocking on a particular request to finish. |
| 3384 | */ |
| 3385 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3386 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3387 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3388 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3389 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3390 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3391 | struct drm_i915_gem_request *request; |
| 3392 | struct intel_ring_buffer *ring = NULL; |
| 3393 | u32 seqno = 0; |
| 3394 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3395 | |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3396 | if (atomic_read(&dev_priv->mm.wedged)) |
| 3397 | return -EIO; |
| 3398 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3399 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3400 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3401 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3402 | break; |
| 3403 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3404 | ring = request->ring; |
| 3405 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3406 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3407 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3408 | |
| 3409 | if (seqno == 0) |
| 3410 | return 0; |
| 3411 | |
Ben Widawsky | 5c81fe85 | 2012-05-24 15:03:08 -0700 | [diff] [blame] | 3412 | ret = __wait_seqno(ring, seqno, true, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3413 | if (ret == 0) |
| 3414 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3415 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3416 | return ret; |
| 3417 | } |
| 3418 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3419 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3420 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 3421 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3422 | bool map_and_fenceable, |
| 3423 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3424 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3425 | int ret; |
| 3426 | |
Chris Wilson | 7e81a42 | 2012-09-15 09:41:57 +0100 | [diff] [blame] | 3427 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 3428 | return -EBUSY; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3429 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3430 | if (obj->gtt_space != NULL) { |
| 3431 | if ((alignment && obj->gtt_offset & (alignment - 1)) || |
| 3432 | (map_and_fenceable && !obj->map_and_fenceable)) { |
| 3433 | WARN(obj->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3434 | "bo is already pinned with incorrect alignment:" |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3435 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
| 3436 | " obj->map_and_fenceable=%d\n", |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3437 | obj->gtt_offset, alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3438 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3439 | obj->map_and_fenceable); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3440 | ret = i915_gem_object_unbind(obj); |
| 3441 | if (ret) |
| 3442 | return ret; |
| 3443 | } |
| 3444 | } |
| 3445 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3446 | if (obj->gtt_space == NULL) { |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3447 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3448 | map_and_fenceable, |
| 3449 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3450 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3451 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3452 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3453 | |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3454 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
| 3455 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
| 3456 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3457 | obj->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3458 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3459 | |
| 3460 | return 0; |
| 3461 | } |
| 3462 | |
| 3463 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3464 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3465 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3466 | BUG_ON(obj->pin_count == 0); |
| 3467 | BUG_ON(obj->gtt_space == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3468 | |
Chris Wilson | 1b50247 | 2012-04-24 15:47:30 +0100 | [diff] [blame] | 3469 | if (--obj->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3470 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3471 | } |
| 3472 | |
| 3473 | int |
| 3474 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3475 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3476 | { |
| 3477 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3478 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3479 | int ret; |
| 3480 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3481 | ret = i915_mutex_lock_interruptible(dev); |
| 3482 | if (ret) |
| 3483 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3484 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3485 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3486 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3487 | ret = -ENOENT; |
| 3488 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3489 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3490 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3491 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3492 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3493 | ret = -EINVAL; |
| 3494 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3495 | } |
| 3496 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3497 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3498 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3499 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3500 | ret = -EINVAL; |
| 3501 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3502 | } |
| 3503 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3504 | obj->user_pin_count++; |
| 3505 | obj->pin_filp = file; |
| 3506 | if (obj->user_pin_count == 1) { |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3507 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3508 | if (ret) |
| 3509 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3510 | } |
| 3511 | |
| 3512 | /* XXX - flush the CPU caches for pinned objects |
| 3513 | * as the X server doesn't manage domains yet |
| 3514 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3515 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3516 | args->offset = obj->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3517 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3518 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3519 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3520 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3521 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3522 | } |
| 3523 | |
| 3524 | int |
| 3525 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3526 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3527 | { |
| 3528 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3529 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3530 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3531 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3532 | ret = i915_mutex_lock_interruptible(dev); |
| 3533 | if (ret) |
| 3534 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3535 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3536 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3537 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3538 | ret = -ENOENT; |
| 3539 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3540 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3541 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3542 | if (obj->pin_filp != file) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3543 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 3544 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3545 | ret = -EINVAL; |
| 3546 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3547 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3548 | obj->user_pin_count--; |
| 3549 | if (obj->user_pin_count == 0) { |
| 3550 | obj->pin_filp = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3551 | i915_gem_object_unpin(obj); |
| 3552 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3553 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3554 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3555 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3556 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3557 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3558 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3559 | } |
| 3560 | |
| 3561 | int |
| 3562 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3563 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3564 | { |
| 3565 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3566 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3567 | int ret; |
| 3568 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3569 | ret = i915_mutex_lock_interruptible(dev); |
| 3570 | if (ret) |
| 3571 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3572 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3573 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3574 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3575 | ret = -ENOENT; |
| 3576 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3577 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3578 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 3579 | /* Count all active objects as busy, even if they are currently not used |
| 3580 | * by the gpu. Users of this interface expect objects to eventually |
| 3581 | * become non-busy without any further actions, therefore emit any |
| 3582 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 3583 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3584 | ret = i915_gem_object_flush_active(obj); |
| 3585 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3586 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 3587 | if (obj->ring) { |
| 3588 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 3589 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 3590 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3591 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3592 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3593 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3594 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3595 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3596 | } |
| 3597 | |
| 3598 | int |
| 3599 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 3600 | struct drm_file *file_priv) |
| 3601 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3602 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3603 | } |
| 3604 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3605 | int |
| 3606 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 3607 | struct drm_file *file_priv) |
| 3608 | { |
| 3609 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3610 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3611 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3612 | |
| 3613 | switch (args->madv) { |
| 3614 | case I915_MADV_DONTNEED: |
| 3615 | case I915_MADV_WILLNEED: |
| 3616 | break; |
| 3617 | default: |
| 3618 | return -EINVAL; |
| 3619 | } |
| 3620 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3621 | ret = i915_mutex_lock_interruptible(dev); |
| 3622 | if (ret) |
| 3623 | return ret; |
| 3624 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3625 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3626 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3627 | ret = -ENOENT; |
| 3628 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3629 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3630 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3631 | if (obj->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3632 | ret = -EINVAL; |
| 3633 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3634 | } |
| 3635 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3636 | if (obj->madv != __I915_MADV_PURGED) |
| 3637 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3638 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3639 | /* if the object is no longer attached, discard its backing storage */ |
| 3640 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 3641 | i915_gem_object_truncate(obj); |
| 3642 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3643 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 3644 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3645 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3646 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3647 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3648 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3649 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3650 | } |
| 3651 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3652 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 3653 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3654 | { |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3655 | INIT_LIST_HEAD(&obj->mm_list); |
| 3656 | INIT_LIST_HEAD(&obj->gtt_list); |
| 3657 | INIT_LIST_HEAD(&obj->ring_list); |
| 3658 | INIT_LIST_HEAD(&obj->exec_list); |
| 3659 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3660 | obj->ops = ops; |
| 3661 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 3662 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3663 | obj->madv = I915_MADV_WILLNEED; |
| 3664 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 3665 | obj->map_and_fenceable = true; |
| 3666 | |
| 3667 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 3668 | } |
| 3669 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3670 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 3671 | .get_pages = i915_gem_object_get_pages_gtt, |
| 3672 | .put_pages = i915_gem_object_put_pages_gtt, |
| 3673 | }; |
| 3674 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3675 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 3676 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3677 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3678 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3679 | struct address_space *mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3680 | u32 mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3681 | |
| 3682 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 3683 | if (obj == NULL) |
| 3684 | return NULL; |
| 3685 | |
| 3686 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 3687 | kfree(obj); |
| 3688 | return NULL; |
| 3689 | } |
| 3690 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3691 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 3692 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 3693 | /* 965gm cannot relocate objects above 4GiB. */ |
| 3694 | mask &= ~__GFP_HIGHMEM; |
| 3695 | mask |= __GFP_DMA32; |
| 3696 | } |
| 3697 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3698 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 3699 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 3700 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3701 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 3702 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3703 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3704 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3705 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 3706 | if (HAS_LLC(dev)) { |
| 3707 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 3708 | * cache) for about a 10% performance improvement |
| 3709 | * compared to uncached. Graphics requests other than |
| 3710 | * display scanout are coherent with the CPU in |
| 3711 | * accessing this cache. This means in this mode we |
| 3712 | * don't need to clflush on the CPU side, and on the |
| 3713 | * GPU side we only need to flush internal caches to |
| 3714 | * get data visible to the CPU. |
| 3715 | * |
| 3716 | * However, we maintain the display planes as UC, and so |
| 3717 | * need to rebind when first used as such. |
| 3718 | */ |
| 3719 | obj->cache_level = I915_CACHE_LLC; |
| 3720 | } else |
| 3721 | obj->cache_level = I915_CACHE_NONE; |
| 3722 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3723 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 3724 | } |
| 3725 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3726 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 3727 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 3728 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3729 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | return 0; |
| 3731 | } |
| 3732 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3733 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3734 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3735 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3736 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3737 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3738 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 3739 | trace_i915_gem_object_destroy(obj); |
| 3740 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 3741 | if (obj->phys_obj) |
| 3742 | i915_gem_detach_phys_object(dev, obj); |
| 3743 | |
| 3744 | obj->pin_count = 0; |
| 3745 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { |
| 3746 | bool was_interruptible; |
| 3747 | |
| 3748 | was_interruptible = dev_priv->mm.interruptible; |
| 3749 | dev_priv->mm.interruptible = false; |
| 3750 | |
| 3751 | WARN_ON(i915_gem_object_unbind(obj)); |
| 3752 | |
| 3753 | dev_priv->mm.interruptible = was_interruptible; |
| 3754 | } |
| 3755 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 3756 | obj->pages_pin_count = 0; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3757 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 3758 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3759 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3760 | BUG_ON(obj->pages); |
| 3761 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 3762 | if (obj->base.import_attach) |
| 3763 | drm_prime_gem_destroy(&obj->base, NULL); |
| 3764 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3765 | drm_gem_object_release(&obj->base); |
| 3766 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3767 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3768 | kfree(obj->bit_17); |
| 3769 | kfree(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 3770 | } |
| 3771 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 3772 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3773 | i915_gem_idle(struct drm_device *dev) |
| 3774 | { |
| 3775 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3776 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3777 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3778 | mutex_lock(&dev->struct_mutex); |
| 3779 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 3780 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3781 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3782 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3783 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3784 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3785 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3786 | if (ret) { |
| 3787 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3788 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3789 | } |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3790 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3791 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3792 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 3793 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3794 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3795 | |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 3796 | i915_gem_reset_fences(dev); |
| 3797 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3798 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 3799 | * We need to replace this with a semaphore, or something. |
| 3800 | * And not confound mm.suspended! |
| 3801 | */ |
| 3802 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 3803 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3804 | |
| 3805 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3806 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3807 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 3808 | mutex_unlock(&dev->struct_mutex); |
| 3809 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 3810 | /* Cancel the retire work handler, which should be idle now. */ |
| 3811 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 3812 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3813 | return 0; |
| 3814 | } |
| 3815 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3816 | void i915_gem_l3_remap(struct drm_device *dev) |
| 3817 | { |
| 3818 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3819 | u32 misccpctl; |
| 3820 | int i; |
| 3821 | |
| 3822 | if (!IS_IVYBRIDGE(dev)) |
| 3823 | return; |
| 3824 | |
| 3825 | if (!dev_priv->mm.l3_remap_info) |
| 3826 | return; |
| 3827 | |
| 3828 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 3829 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 3830 | POSTING_READ(GEN7_MISCCPCTL); |
| 3831 | |
| 3832 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
| 3833 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); |
| 3834 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) |
| 3835 | DRM_DEBUG("0x%x was already programmed to %x\n", |
| 3836 | GEN7_L3LOG_BASE + i, remap); |
| 3837 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) |
| 3838 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
| 3839 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); |
| 3840 | } |
| 3841 | |
| 3842 | /* Make sure all the writes land before disabling dop clock gating */ |
| 3843 | POSTING_READ(GEN7_L3LOG_BASE); |
| 3844 | |
| 3845 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 3846 | } |
| 3847 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3848 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 3849 | { |
| 3850 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3851 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3852 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3853 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 3854 | return; |
| 3855 | |
| 3856 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 3857 | DISP_TILE_SURFACE_SWIZZLING); |
| 3858 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 3859 | if (IS_GEN5(dev)) |
| 3860 | return; |
| 3861 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3862 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 3863 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3864 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3865 | else |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3866 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3867 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3868 | |
| 3869 | void i915_gem_init_ppgtt(struct drm_device *dev) |
| 3870 | { |
| 3871 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3872 | uint32_t pd_offset; |
| 3873 | struct intel_ring_buffer *ring; |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3874 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 3875 | uint32_t __iomem *pd_addr; |
| 3876 | uint32_t pd_entry; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3877 | int i; |
| 3878 | |
| 3879 | if (!dev_priv->mm.aliasing_ppgtt) |
| 3880 | return; |
| 3881 | |
Daniel Vetter | 55a254a | 2012-03-22 00:14:43 +0100 | [diff] [blame] | 3882 | |
| 3883 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); |
| 3884 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
| 3885 | dma_addr_t pt_addr; |
| 3886 | |
| 3887 | if (dev_priv->mm.gtt->needs_dmar) |
| 3888 | pt_addr = ppgtt->pt_dma_addr[i]; |
| 3889 | else |
| 3890 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); |
| 3891 | |
| 3892 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
| 3893 | pd_entry |= GEN6_PDE_VALID; |
| 3894 | |
| 3895 | writel(pd_entry, pd_addr + i); |
| 3896 | } |
| 3897 | readl(pd_addr); |
| 3898 | |
| 3899 | pd_offset = ppgtt->pd_offset; |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3900 | pd_offset /= 64; /* in cachelines, */ |
| 3901 | pd_offset <<= 16; |
| 3902 | |
| 3903 | if (INTEL_INFO(dev)->gen == 6) { |
Daniel Vetter | 48ecfa1 | 2012-04-11 20:42:40 +0200 | [diff] [blame] | 3904 | uint32_t ecochk, gab_ctl, ecobits; |
| 3905 | |
| 3906 | ecobits = I915_READ(GAC_ECO_BITS); |
| 3907 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
Daniel Vetter | be901a5 | 2012-04-11 20:42:39 +0200 | [diff] [blame] | 3908 | |
| 3909 | gab_ctl = I915_READ(GAB_CTL); |
| 3910 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
| 3911 | |
| 3912 | ecochk = I915_READ(GAM_ECOCHK); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3913 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
| 3914 | ECOCHK_PPGTT_CACHE64B); |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3915 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3916 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 3917 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); |
| 3918 | /* GFX_MODE is per-ring on gen7+ */ |
| 3919 | } |
| 3920 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3921 | for_each_ring(ring, dev_priv, i) { |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3922 | if (INTEL_INFO(dev)->gen >= 7) |
| 3923 | I915_WRITE(RING_MODE_GEN7(ring), |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 3924 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3925 | |
| 3926 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 3927 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); |
| 3928 | } |
| 3929 | } |
| 3930 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3931 | static bool |
| 3932 | intel_enable_blt(struct drm_device *dev) |
| 3933 | { |
| 3934 | if (!HAS_BLT(dev)) |
| 3935 | return false; |
| 3936 | |
| 3937 | /* The blitter was dysfunctional on early prototypes */ |
| 3938 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 3939 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 3940 | " graphics performance will be degraded.\n"); |
| 3941 | return false; |
| 3942 | } |
| 3943 | |
| 3944 | return true; |
| 3945 | } |
| 3946 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3947 | int |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3948 | i915_gem_init_hw(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3949 | { |
| 3950 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3951 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3952 | |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame] | 3953 | if (!intel_enable_gtt()) |
| 3954 | return -EIO; |
| 3955 | |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 3956 | i915_gem_l3_remap(dev); |
| 3957 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 3958 | i915_gem_init_swizzling(dev); |
| 3959 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3960 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3961 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 3962 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3963 | |
| 3964 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 3965 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3966 | if (ret) |
| 3967 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3968 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3969 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 3970 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3971 | ret = intel_init_blt_ring_buffer(dev); |
| 3972 | if (ret) |
| 3973 | goto cleanup_bsd_ring; |
| 3974 | } |
| 3975 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 3976 | dev_priv->next_seqno = 1; |
| 3977 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 3978 | /* |
| 3979 | * XXX: There was some w/a described somewhere suggesting loading |
| 3980 | * contexts before PPGTT. |
| 3981 | */ |
| 3982 | i915_gem_context_init(dev); |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 3983 | i915_gem_init_ppgtt(dev); |
| 3984 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3985 | return 0; |
| 3986 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3987 | cleanup_bsd_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3988 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 3989 | cleanup_render_ring: |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3990 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 3991 | return ret; |
| 3992 | } |
| 3993 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 3994 | static bool |
| 3995 | intel_enable_ppgtt(struct drm_device *dev) |
| 3996 | { |
| 3997 | if (i915_enable_ppgtt >= 0) |
| 3998 | return i915_enable_ppgtt; |
| 3999 | |
| 4000 | #ifdef CONFIG_INTEL_IOMMU |
| 4001 | /* Disable ppgtt on SNB if VT-d is on. */ |
| 4002 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
| 4003 | return false; |
| 4004 | #endif |
| 4005 | |
| 4006 | return true; |
| 4007 | } |
| 4008 | |
| 4009 | int i915_gem_init(struct drm_device *dev) |
| 4010 | { |
| 4011 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4012 | unsigned long gtt_size, mappable_size; |
| 4013 | int ret; |
| 4014 | |
| 4015 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; |
| 4016 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
| 4017 | |
| 4018 | mutex_lock(&dev->struct_mutex); |
| 4019 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { |
| 4020 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the |
| 4021 | * aperture accordingly when using aliasing ppgtt. */ |
| 4022 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; |
| 4023 | |
| 4024 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); |
| 4025 | |
| 4026 | ret = i915_gem_init_aliasing_ppgtt(dev); |
| 4027 | if (ret) { |
| 4028 | mutex_unlock(&dev->struct_mutex); |
| 4029 | return ret; |
| 4030 | } |
| 4031 | } else { |
| 4032 | /* Let GEM Manage all of the aperture. |
| 4033 | * |
| 4034 | * However, leave one page at the end still bound to the scratch |
| 4035 | * page. There are a number of places where the hardware |
| 4036 | * apparently prefetches past the end of the object, and we've |
| 4037 | * seen multiple hangs with the GPU head pointer stuck in a |
| 4038 | * batchbuffer bound at the last page of the aperture. One page |
| 4039 | * should be enough to keep any prefetching inside of the |
| 4040 | * aperture. |
| 4041 | */ |
| 4042 | i915_gem_init_global_gtt(dev, 0, mappable_size, |
| 4043 | gtt_size); |
| 4044 | } |
| 4045 | |
| 4046 | ret = i915_gem_init_hw(dev); |
| 4047 | mutex_unlock(&dev->struct_mutex); |
| 4048 | if (ret) { |
| 4049 | i915_gem_cleanup_aliasing_ppgtt(dev); |
| 4050 | return ret; |
| 4051 | } |
| 4052 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4053 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4054 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4055 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4056 | return 0; |
| 4057 | } |
| 4058 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4059 | void |
| 4060 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4061 | { |
| 4062 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4063 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4064 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4065 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4066 | for_each_ring(ring, dev_priv, i) |
| 4067 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4068 | } |
| 4069 | |
| 4070 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4071 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4072 | struct drm_file *file_priv) |
| 4073 | { |
| 4074 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4075 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4076 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4077 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4078 | return 0; |
| 4079 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4080 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4081 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4082 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4083 | } |
| 4084 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4085 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4086 | dev_priv->mm.suspended = 0; |
| 4087 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4088 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4089 | if (ret != 0) { |
| 4090 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4091 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4092 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4093 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4094 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4095 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4096 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4097 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4098 | ret = drm_irq_install(dev); |
| 4099 | if (ret) |
| 4100 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4101 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4102 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4103 | |
| 4104 | cleanup_ringbuffer: |
| 4105 | mutex_lock(&dev->struct_mutex); |
| 4106 | i915_gem_cleanup_ringbuffer(dev); |
| 4107 | dev_priv->mm.suspended = 1; |
| 4108 | mutex_unlock(&dev->struct_mutex); |
| 4109 | |
| 4110 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4111 | } |
| 4112 | |
| 4113 | int |
| 4114 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4115 | struct drm_file *file_priv) |
| 4116 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4117 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4118 | return 0; |
| 4119 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4120 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4121 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4122 | } |
| 4123 | |
| 4124 | void |
| 4125 | i915_gem_lastclose(struct drm_device *dev) |
| 4126 | { |
| 4127 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4128 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4129 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4130 | return; |
| 4131 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4132 | ret = i915_gem_idle(dev); |
| 4133 | if (ret) |
| 4134 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4135 | } |
| 4136 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4137 | static void |
| 4138 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4139 | { |
| 4140 | INIT_LIST_HEAD(&ring->active_list); |
| 4141 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4142 | } |
| 4143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4144 | void |
| 4145 | i915_gem_load(struct drm_device *dev) |
| 4146 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4147 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4148 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4149 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4150 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4151 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4152 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4153 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4154 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4155 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4156 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4157 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4158 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4159 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4160 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4161 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4162 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4163 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4164 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4165 | I915_WRITE(MI_ARB_STATE, |
| 4166 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4167 | } |
| 4168 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4169 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4170 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4171 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4172 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4173 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4174 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4175 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4176 | dev_priv->num_fence_regs = 16; |
| 4177 | else |
| 4178 | dev_priv->num_fence_regs = 8; |
| 4179 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4180 | /* Initialize fence registers to zero */ |
Chris Wilson | ada726c | 2012-04-17 15:31:32 +0100 | [diff] [blame] | 4181 | i915_gem_reset_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4182 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4183 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4184 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4185 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4186 | dev_priv->mm.interruptible = true; |
| 4187 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4188 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4189 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4190 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4191 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4192 | |
| 4193 | /* |
| 4194 | * Create a physically contiguous memory object for this object |
| 4195 | * e.g. for cursor + overlay regs |
| 4196 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4197 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4198 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4199 | { |
| 4200 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4201 | struct drm_i915_gem_phys_object *phys_obj; |
| 4202 | int ret; |
| 4203 | |
| 4204 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4205 | return 0; |
| 4206 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4207 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4208 | if (!phys_obj) |
| 4209 | return -ENOMEM; |
| 4210 | |
| 4211 | phys_obj->id = id; |
| 4212 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4213 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4214 | if (!phys_obj->handle) { |
| 4215 | ret = -ENOMEM; |
| 4216 | goto kfree_obj; |
| 4217 | } |
| 4218 | #ifdef CONFIG_X86 |
| 4219 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4220 | #endif |
| 4221 | |
| 4222 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4223 | |
| 4224 | return 0; |
| 4225 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4226 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4227 | return ret; |
| 4228 | } |
| 4229 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4230 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4231 | { |
| 4232 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4233 | struct drm_i915_gem_phys_object *phys_obj; |
| 4234 | |
| 4235 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4236 | return; |
| 4237 | |
| 4238 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4239 | if (phys_obj->cur_obj) { |
| 4240 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4241 | } |
| 4242 | |
| 4243 | #ifdef CONFIG_X86 |
| 4244 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4245 | #endif |
| 4246 | drm_pci_free(dev, phys_obj->handle); |
| 4247 | kfree(phys_obj); |
| 4248 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4249 | } |
| 4250 | |
| 4251 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4252 | { |
| 4253 | int i; |
| 4254 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4255 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4256 | i915_gem_free_phys_object(dev, i); |
| 4257 | } |
| 4258 | |
| 4259 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4260 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4261 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4262 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4263 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4264 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4265 | int page_count; |
| 4266 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4267 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4268 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4269 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4270 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4271 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4272 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4273 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4274 | if (!IS_ERR(page)) { |
| 4275 | char *dst = kmap_atomic(page); |
| 4276 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4277 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4278 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4279 | drm_clflush_pages(&page, 1); |
| 4280 | |
| 4281 | set_page_dirty(page); |
| 4282 | mark_page_accessed(page); |
| 4283 | page_cache_release(page); |
| 4284 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4285 | } |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4286 | intel_gtt_chipset_flush(); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4287 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4288 | obj->phys_obj->cur_obj = NULL; |
| 4289 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4290 | } |
| 4291 | |
| 4292 | int |
| 4293 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4294 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4295 | int id, |
| 4296 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4297 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4298 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4299 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4300 | int ret = 0; |
| 4301 | int page_count; |
| 4302 | int i; |
| 4303 | |
| 4304 | if (id > I915_MAX_PHYS_OBJECT) |
| 4305 | return -EINVAL; |
| 4306 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4307 | if (obj->phys_obj) { |
| 4308 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4309 | return 0; |
| 4310 | i915_gem_detach_phys_object(dev, obj); |
| 4311 | } |
| 4312 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4313 | /* create a new object */ |
| 4314 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4315 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4316 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4317 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4318 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4319 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4320 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4321 | } |
| 4322 | } |
| 4323 | |
| 4324 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4325 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4326 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4327 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4328 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4329 | |
| 4330 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4331 | struct page *page; |
| 4332 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4333 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4334 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4335 | if (IS_ERR(page)) |
| 4336 | return PTR_ERR(page); |
| 4337 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4338 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4339 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4340 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4341 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4342 | |
| 4343 | mark_page_accessed(page); |
| 4344 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4345 | } |
| 4346 | |
| 4347 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4348 | } |
| 4349 | |
| 4350 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4351 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4352 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4353 | struct drm_i915_gem_pwrite *args, |
| 4354 | struct drm_file *file_priv) |
| 4355 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4356 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4357 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4358 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4359 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4360 | unsigned long unwritten; |
| 4361 | |
| 4362 | /* The physical object once assigned is fixed for the lifetime |
| 4363 | * of the obj, so we can safely drop the lock and continue |
| 4364 | * to access vaddr. |
| 4365 | */ |
| 4366 | mutex_unlock(&dev->struct_mutex); |
| 4367 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4368 | mutex_lock(&dev->struct_mutex); |
| 4369 | if (unwritten) |
| 4370 | return -EFAULT; |
| 4371 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4372 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 4373 | intel_gtt_chipset_flush(); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4374 | return 0; |
| 4375 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4376 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4377 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4378 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4379 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4380 | |
| 4381 | /* Clean up our request list when the client is going away, so that |
| 4382 | * later retire_requests won't dereference our soon-to-be-gone |
| 4383 | * file_priv. |
| 4384 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4385 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4386 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4387 | struct drm_i915_gem_request *request; |
| 4388 | |
| 4389 | request = list_first_entry(&file_priv->mm.request_list, |
| 4390 | struct drm_i915_gem_request, |
| 4391 | client_list); |
| 4392 | list_del(&request->client_list); |
| 4393 | request->file_priv = NULL; |
| 4394 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4395 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4396 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4397 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4398 | static int |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4399 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4400 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4401 | struct drm_i915_private *dev_priv = |
| 4402 | container_of(shrinker, |
| 4403 | struct drm_i915_private, |
| 4404 | mm.inactive_shrinker); |
| 4405 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4406 | struct drm_i915_gem_object *obj; |
Ying Han | 1495f23 | 2011-05-24 17:12:27 -0700 | [diff] [blame] | 4407 | int nr_to_scan = sc->nr_to_scan; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4408 | int cnt; |
| 4409 | |
| 4410 | if (!mutex_trylock(&dev->struct_mutex)) |
Chris Wilson | bbe2e11 | 2010-10-28 22:35:07 +0100 | [diff] [blame] | 4411 | return 0; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4412 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4413 | if (nr_to_scan) { |
| 4414 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); |
| 4415 | if (nr_to_scan > 0) |
| 4416 | i915_gem_shrink_all(dev_priv); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4417 | } |
| 4418 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4419 | cnt = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4420 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4421 | if (obj->pages_pin_count == 0) |
| 4422 | cnt += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4423 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4424 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4425 | cnt += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4426 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4427 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4428 | return cnt; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4429 | } |