Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 63 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 72 | #include <ttm/ttm_execbuf_util.h> |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 73 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 74 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 91 | extern int radeon_tv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 92 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 93 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 94 | extern int radeon_hw_i2c; |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 95 | extern int radeon_pcie_gen2; |
Alex Deucher | a18cee1 | 2011-11-01 14:20:30 -0400 | [diff] [blame] | 96 | extern int radeon_msi; |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 97 | extern int radeon_lockup_timeout; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 101 | * symbol; |
| 102 | */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 103 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 104 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 105 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 106 | #define RADEON_IB_POOL_SIZE 16 |
| 107 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
| 108 | #define RADEONFB_CONN_LIMIT 4 |
| 109 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 111 | /* max number of rings */ |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 112 | #define RADEON_NUM_RINGS 5 |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 113 | |
| 114 | /* fence seq are set to this number when signaled */ |
| 115 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 116 | |
| 117 | /* internal ring indices */ |
| 118 | /* r1xx+ has gfx CP ring */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 119 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 120 | |
| 121 | /* cayman has 2 compute CP rings */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 122 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
| 123 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 124 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 125 | /* R600+ has an async dma ring */ |
| 126 | #define R600_RING_TYPE_DMA_INDEX 3 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 127 | /* cayman add a second async dma ring */ |
| 128 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 129 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 130 | /* hardcode those limit for now */ |
Christian König | ca19f21 | 2012-09-11 16:09:59 +0200 | [diff] [blame] | 131 | #define RADEON_VA_IB_OFFSET (1 << 20) |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 132 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
| 133 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 134 | |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 135 | /* reset flags */ |
| 136 | #define RADEON_RESET_GFX (1 << 0) |
| 137 | #define RADEON_RESET_COMPUTE (1 << 1) |
| 138 | #define RADEON_RESET_DMA (1 << 2) |
Alex Deucher | 9ff0744 | 2013-01-18 12:18:17 -0500 | [diff] [blame] | 139 | #define RADEON_RESET_CP (1 << 3) |
| 140 | #define RADEON_RESET_GRBM (1 << 4) |
| 141 | #define RADEON_RESET_DMA1 (1 << 5) |
| 142 | #define RADEON_RESET_RLC (1 << 6) |
| 143 | #define RADEON_RESET_SEM (1 << 7) |
| 144 | #define RADEON_RESET_IH (1 << 8) |
| 145 | #define RADEON_RESET_VMC (1 << 9) |
| 146 | #define RADEON_RESET_MC (1 << 10) |
| 147 | #define RADEON_RESET_DISPLAY (1 << 11) |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 148 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 149 | /* |
| 150 | * Errata workarounds. |
| 151 | */ |
| 152 | enum radeon_pll_errata { |
| 153 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 154 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 155 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 156 | }; |
| 157 | |
| 158 | |
| 159 | struct radeon_device; |
| 160 | |
| 161 | |
| 162 | /* |
| 163 | * BIOS. |
| 164 | */ |
| 165 | bool radeon_get_bios(struct radeon_device *rdev); |
| 166 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 167 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 168 | * Dummy page |
| 169 | */ |
| 170 | struct radeon_dummy_page { |
| 171 | struct page *page; |
| 172 | dma_addr_t addr; |
| 173 | }; |
| 174 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 175 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 176 | |
| 177 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 178 | /* |
| 179 | * Clocks |
| 180 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | struct radeon_clock { |
| 182 | struct radeon_pll p1pll; |
| 183 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 184 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 185 | struct radeon_pll spll; |
| 186 | struct radeon_pll mpll; |
| 187 | /* 10 Khz units */ |
| 188 | uint32_t default_mclk; |
| 189 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 190 | uint32_t default_dispclk; |
| 191 | uint32_t dp_extclk; |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 192 | uint32_t max_pixel_clock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 193 | }; |
| 194 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 195 | /* |
| 196 | * Power management |
| 197 | */ |
| 198 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 199 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 200 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 201 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 202 | void radeon_pm_resume(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 203 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 204 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 205 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 206 | void rs690_pm_info(struct radeon_device *rdev); |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 207 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
| 208 | extern int rv770_get_temp(struct radeon_device *rdev); |
| 209 | extern int evergreen_get_temp(struct radeon_device *rdev); |
| 210 | extern int sumo_get_temp(struct radeon_device *rdev); |
Alex Deucher | 1bd47d2 | 2012-03-20 17:18:10 -0400 | [diff] [blame] | 211 | extern int si_get_temp(struct radeon_device *rdev); |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 212 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
| 213 | unsigned *bankh, unsigned *mtaspect, |
| 214 | unsigned *tile_split); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 215 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 216 | /* |
| 217 | * Fences. |
| 218 | */ |
| 219 | struct radeon_fence_driver { |
| 220 | uint32_t scratch_reg; |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 221 | uint64_t gpu_addr; |
| 222 | volatile uint32_t *cpu_addr; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 223 | /* sync_seq is protected by ring emission lock */ |
| 224 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 225 | atomic64_t last_seq; |
Christian König | 36abaca | 2012-05-02 15:11:13 +0200 | [diff] [blame] | 226 | unsigned long last_activity; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 227 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | }; |
| 229 | |
| 230 | struct radeon_fence { |
| 231 | struct radeon_device *rdev; |
| 232 | struct kref kref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 233 | /* protected by radeon_fence.lock */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 234 | uint64_t seq; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 235 | /* RB, DMA, etc. */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 236 | unsigned ring; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | }; |
| 238 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 239 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
| 240 | int radeon_fence_driver_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 241 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
Jerome Glisse | 76903b9 | 2012-12-17 10:29:06 -0500 | [diff] [blame] | 242 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 243 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 244 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 246 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
Christian König | 8a47cc9 | 2012-05-09 15:34:48 +0200 | [diff] [blame] | 247 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
Jerome Glisse | 5f8f635 | 2012-12-17 11:04:32 -0500 | [diff] [blame] | 248 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 249 | int radeon_fence_wait_any(struct radeon_device *rdev, |
| 250 | struct radeon_fence **fences, |
| 251 | bool intr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 253 | void radeon_fence_unref(struct radeon_fence **fence); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 254 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 255 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
| 256 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
| 257 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
| 258 | struct radeon_fence *b) |
| 259 | { |
| 260 | if (!a) { |
| 261 | return b; |
| 262 | } |
| 263 | |
| 264 | if (!b) { |
| 265 | return a; |
| 266 | } |
| 267 | |
| 268 | BUG_ON(a->ring != b->ring); |
| 269 | |
| 270 | if (a->seq > b->seq) { |
| 271 | return a; |
| 272 | } else { |
| 273 | return b; |
| 274 | } |
| 275 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 277 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
| 278 | struct radeon_fence *b) |
| 279 | { |
| 280 | if (!a) { |
| 281 | return false; |
| 282 | } |
| 283 | |
| 284 | if (!b) { |
| 285 | return true; |
| 286 | } |
| 287 | |
| 288 | BUG_ON(a->ring != b->ring); |
| 289 | |
| 290 | return a->seq < b->seq; |
| 291 | } |
| 292 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 293 | /* |
| 294 | * Tiling registers |
| 295 | */ |
| 296 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 297 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 298 | }; |
| 299 | |
| 300 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 301 | |
| 302 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 303 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 304 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 305 | struct radeon_mman { |
| 306 | struct ttm_bo_global_ref bo_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 307 | struct drm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 308 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 309 | bool mem_global_referenced; |
| 310 | bool initialized; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 311 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 313 | /* bo virtual address in a specific vm */ |
| 314 | struct radeon_bo_va { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 315 | /* protected by bo being reserved */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 316 | struct list_head bo_list; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 317 | uint64_t soffset; |
| 318 | uint64_t eoffset; |
| 319 | uint32_t flags; |
| 320 | bool valid; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 321 | unsigned ref_count; |
| 322 | |
| 323 | /* protected by vm mutex */ |
| 324 | struct list_head vm_list; |
| 325 | |
| 326 | /* constant after initialization */ |
| 327 | struct radeon_vm *vm; |
| 328 | struct radeon_bo *bo; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 329 | }; |
| 330 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 331 | struct radeon_bo { |
| 332 | /* Protected by gem.mutex */ |
| 333 | struct list_head list; |
| 334 | /* Protected by tbo.reserved */ |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 335 | u32 placements[3]; |
| 336 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 337 | struct ttm_buffer_object tbo; |
| 338 | struct ttm_bo_kmap_obj kmap; |
| 339 | unsigned pin_count; |
| 340 | void *kptr; |
| 341 | u32 tiling_flags; |
| 342 | u32 pitch; |
| 343 | int surface_reg; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 344 | /* list of all virtual address to which this bo |
| 345 | * is associated to |
| 346 | */ |
| 347 | struct list_head va; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 348 | /* Constant after initialization */ |
| 349 | struct radeon_device *rdev; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 350 | struct drm_gem_object gem_base; |
Dave Airlie | 63bc620 | 2012-05-31 13:52:53 +0100 | [diff] [blame] | 351 | |
| 352 | struct ttm_bo_kmap_obj dma_buf_vmap; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 353 | }; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 354 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 355 | |
| 356 | struct radeon_bo_list { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 357 | struct ttm_validate_buffer tv; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 358 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 359 | uint64_t gpu_offset; |
| 360 | unsigned rdomain; |
| 361 | unsigned wdomain; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 362 | u32 tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | }; |
| 364 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 365 | /* sub-allocation manager, it has to be protected by another lock. |
| 366 | * By conception this is an helper for other part of the driver |
| 367 | * like the indirect buffer or semaphore, which both have their |
| 368 | * locking. |
| 369 | * |
| 370 | * Principe is simple, we keep a list of sub allocation in offset |
| 371 | * order (first entry has offset == 0, last entry has the highest |
| 372 | * offset). |
| 373 | * |
| 374 | * When allocating new object we first check if there is room at |
| 375 | * the end total_size - (last_object_offset + last_object_size) >= |
| 376 | * alloc_size. If so we allocate new object there. |
| 377 | * |
| 378 | * When there is not enough room at the end, we start waiting for |
| 379 | * each sub object until we reach object_offset+object_size >= |
| 380 | * alloc_size, this object then become the sub object we return. |
| 381 | * |
| 382 | * Alignment can't be bigger than page size. |
| 383 | * |
| 384 | * Hole are not considered for allocation to keep things simple. |
| 385 | * Assumption is that there won't be hole (all object on same |
| 386 | * alignment). |
| 387 | */ |
| 388 | struct radeon_sa_manager { |
Christian König | bfb38d3 | 2012-07-11 21:07:57 +0200 | [diff] [blame] | 389 | wait_queue_head_t wq; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 390 | struct radeon_bo *bo; |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 391 | struct list_head *hole; |
| 392 | struct list_head flist[RADEON_NUM_RINGS]; |
| 393 | struct list_head olist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 394 | unsigned size; |
| 395 | uint64_t gpu_addr; |
| 396 | void *cpu_ptr; |
| 397 | uint32_t domain; |
| 398 | }; |
| 399 | |
| 400 | struct radeon_sa_bo; |
| 401 | |
| 402 | /* sub-allocation buffer */ |
| 403 | struct radeon_sa_bo { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 404 | struct list_head olist; |
| 405 | struct list_head flist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 406 | struct radeon_sa_manager *manager; |
Christian König | e6661a9 | 2012-05-09 15:34:52 +0200 | [diff] [blame] | 407 | unsigned soffset; |
| 408 | unsigned eoffset; |
Christian König | 557017a | 2012-05-09 15:34:54 +0200 | [diff] [blame] | 409 | struct radeon_fence *fence; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 410 | }; |
| 411 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 412 | /* |
| 413 | * GEM objects. |
| 414 | */ |
| 415 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 416 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 417 | struct list_head objects; |
| 418 | }; |
| 419 | |
| 420 | int radeon_gem_init(struct radeon_device *rdev); |
| 421 | void radeon_gem_fini(struct radeon_device *rdev); |
| 422 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 423 | int alignment, int initial_domain, |
| 424 | bool discardable, bool kernel, |
| 425 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 426 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 427 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 428 | struct drm_device *dev, |
| 429 | struct drm_mode_create_dumb *args); |
| 430 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 431 | struct drm_device *dev, |
| 432 | uint32_t handle, uint64_t *offset_p); |
| 433 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
| 434 | struct drm_device *dev, |
| 435 | uint32_t handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 436 | |
| 437 | /* |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 438 | * Semaphores. |
| 439 | */ |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 440 | /* everything here is constant */ |
| 441 | struct radeon_semaphore { |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 442 | struct radeon_sa_bo *sa_bo; |
| 443 | signed waiters; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 444 | uint64_t gpu_addr; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 445 | }; |
| 446 | |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 447 | int radeon_semaphore_create(struct radeon_device *rdev, |
| 448 | struct radeon_semaphore **semaphore); |
| 449 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
| 450 | struct radeon_semaphore *semaphore); |
| 451 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
| 452 | struct radeon_semaphore *semaphore); |
Christian König | 8f676c4 | 2012-05-02 15:11:18 +0200 | [diff] [blame] | 453 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
| 454 | struct radeon_semaphore *semaphore, |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 455 | int signaler, int waiter); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 456 | void radeon_semaphore_free(struct radeon_device *rdev, |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 457 | struct radeon_semaphore **semaphore, |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 458 | struct radeon_fence *fence); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 459 | |
| 460 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 461 | * GART structures, functions & helpers |
| 462 | */ |
| 463 | struct radeon_mc; |
| 464 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 465 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 466 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 467 | #define RADEON_GPU_PAGE_SHIFT 12 |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 468 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 469 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 470 | struct radeon_gart { |
| 471 | dma_addr_t table_addr; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 472 | struct radeon_bo *robj; |
| 473 | void *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 474 | unsigned num_gpu_pages; |
| 475 | unsigned num_cpu_pages; |
| 476 | unsigned table_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 477 | struct page **pages; |
| 478 | dma_addr_t *pages_addr; |
| 479 | bool ready; |
| 480 | }; |
| 481 | |
| 482 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 483 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 484 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 485 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 486 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 487 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | int radeon_gart_init(struct radeon_device *rdev); |
| 489 | void radeon_gart_fini(struct radeon_device *rdev); |
| 490 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 491 | int pages); |
| 492 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 493 | int pages, struct page **pagelist, |
| 494 | dma_addr_t *dma_addr); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 495 | void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 496 | |
| 497 | |
| 498 | /* |
| 499 | * GPU MC structures, functions & helpers |
| 500 | */ |
| 501 | struct radeon_mc { |
| 502 | resource_size_t aper_size; |
| 503 | resource_size_t aper_base; |
| 504 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 505 | /* for some chips with <= 32MB we need to lie |
| 506 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 507 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 508 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 509 | u64 gtt_size; |
| 510 | u64 gtt_start; |
| 511 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 512 | u64 vram_start; |
| 513 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 514 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 515 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 516 | int vram_mtrr; |
| 517 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 518 | bool igp_sideport_enabled; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 519 | u64 gtt_base_align; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 520 | }; |
| 521 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 522 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 523 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 524 | |
| 525 | /* |
| 526 | * GPU scratch registers structures, functions & helpers |
| 527 | */ |
| 528 | struct radeon_scratch { |
| 529 | unsigned num_reg; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 530 | uint32_t reg_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 531 | bool free[32]; |
| 532 | uint32_t reg[32]; |
| 533 | }; |
| 534 | |
| 535 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 536 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 537 | |
| 538 | |
| 539 | /* |
| 540 | * IRQS. |
| 541 | */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 542 | |
| 543 | struct radeon_unpin_work { |
| 544 | struct work_struct work; |
| 545 | struct radeon_device *rdev; |
| 546 | int crtc_id; |
| 547 | struct radeon_fence *fence; |
| 548 | struct drm_pending_vblank_event *event; |
| 549 | struct radeon_bo *old_rbo; |
| 550 | u64 new_crtc_base; |
| 551 | }; |
| 552 | |
| 553 | struct r500_irq_stat_regs { |
| 554 | u32 disp_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 555 | u32 hdmi0_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 556 | }; |
| 557 | |
| 558 | struct r600_irq_stat_regs { |
| 559 | u32 disp_int; |
| 560 | u32 disp_int_cont; |
| 561 | u32 disp_int_cont2; |
| 562 | u32 d1grph_int; |
| 563 | u32 d2grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 564 | u32 hdmi0_status; |
| 565 | u32 hdmi1_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 566 | }; |
| 567 | |
| 568 | struct evergreen_irq_stat_regs { |
| 569 | u32 disp_int; |
| 570 | u32 disp_int_cont; |
| 571 | u32 disp_int_cont2; |
| 572 | u32 disp_int_cont3; |
| 573 | u32 disp_int_cont4; |
| 574 | u32 disp_int_cont5; |
| 575 | u32 d1grph_int; |
| 576 | u32 d2grph_int; |
| 577 | u32 d3grph_int; |
| 578 | u32 d4grph_int; |
| 579 | u32 d5grph_int; |
| 580 | u32 d6grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 581 | u32 afmt_status1; |
| 582 | u32 afmt_status2; |
| 583 | u32 afmt_status3; |
| 584 | u32 afmt_status4; |
| 585 | u32 afmt_status5; |
| 586 | u32 afmt_status6; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 587 | }; |
| 588 | |
| 589 | union radeon_irq_stat_regs { |
| 590 | struct r500_irq_stat_regs r500; |
| 591 | struct r600_irq_stat_regs r600; |
| 592 | struct evergreen_irq_stat_regs evergreen; |
| 593 | }; |
| 594 | |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 595 | #define RADEON_MAX_HPD_PINS 6 |
| 596 | #define RADEON_MAX_CRTCS 6 |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 597 | #define RADEON_MAX_AFMT_BLOCKS 6 |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 598 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 599 | struct radeon_irq { |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 600 | bool installed; |
| 601 | spinlock_t lock; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 602 | atomic_t ring_int[RADEON_NUM_RINGS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 603 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 604 | atomic_t pflip[RADEON_MAX_CRTCS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 605 | wait_queue_head_t vblank_queue; |
| 606 | bool hpd[RADEON_MAX_HPD_PINS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 607 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
| 608 | union radeon_irq_stat_regs stat_regs; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 609 | }; |
| 610 | |
| 611 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 612 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 613 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
| 614 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 615 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 616 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 617 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
| 618 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
| 619 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
| 620 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 621 | |
| 622 | /* |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 623 | * CP & rings. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 624 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 625 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 626 | struct radeon_ib { |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 627 | struct radeon_sa_bo *sa_bo; |
| 628 | uint32_t length_dw; |
| 629 | uint64_t gpu_addr; |
| 630 | uint32_t *ptr; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 631 | int ring; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 632 | struct radeon_fence *fence; |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 633 | struct radeon_vm *vm; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 634 | bool is_const_ib; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 635 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 636 | struct radeon_semaphore *semaphore; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 637 | }; |
| 638 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 639 | struct radeon_ring { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 640 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 641 | volatile uint32_t *ring; |
| 642 | unsigned rptr; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 643 | unsigned rptr_offs; |
| 644 | unsigned rptr_reg; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 645 | unsigned rptr_save_reg; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 646 | u64 next_rptr_gpu_addr; |
| 647 | volatile u32 *next_rptr_cpu_addr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 648 | unsigned wptr; |
| 649 | unsigned wptr_old; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 650 | unsigned wptr_reg; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 651 | unsigned ring_size; |
| 652 | unsigned ring_free_dw; |
| 653 | int count_dw; |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 654 | unsigned long last_activity; |
| 655 | unsigned last_rptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 656 | uint64_t gpu_addr; |
| 657 | uint32_t align_mask; |
| 658 | uint32_t ptr_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 659 | bool ready; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 660 | u32 ptr_reg_shift; |
| 661 | u32 ptr_reg_mask; |
| 662 | u32 nop; |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 663 | u32 idx; |
Jerome Glisse | 5f0839c | 2013-01-11 15:19:43 -0500 | [diff] [blame] | 664 | u64 last_semaphore_signal_addr; |
| 665 | u64 last_semaphore_wait_addr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 666 | }; |
| 667 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 668 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 669 | * VM |
| 670 | */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 671 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 672 | /* maximum number of VMIDs */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 673 | #define RADEON_NUM_VM 16 |
| 674 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 675 | /* defines number of bits in page table versus page directory, |
| 676 | * a page is 4KB so we have 12 bits offset, 9 bits in the page |
| 677 | * table and the remaining 19 bits are in the page directory */ |
| 678 | #define RADEON_VM_BLOCK_SIZE 9 |
| 679 | |
| 680 | /* number of entries in page table */ |
| 681 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) |
| 682 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 683 | struct radeon_vm { |
| 684 | struct list_head list; |
| 685 | struct list_head va; |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 686 | unsigned id; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 687 | |
| 688 | /* contains the page directory */ |
| 689 | struct radeon_sa_bo *page_directory; |
| 690 | uint64_t pd_gpu_addr; |
| 691 | |
| 692 | /* array of page tables, one for each page directory entry */ |
| 693 | struct radeon_sa_bo **page_tables; |
| 694 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 695 | struct mutex mutex; |
| 696 | /* last fence for cs using this vm */ |
| 697 | struct radeon_fence *fence; |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 698 | /* last flush or NULL if we still need to flush */ |
| 699 | struct radeon_fence *last_flush; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 700 | }; |
| 701 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 702 | struct radeon_vm_manager { |
Christian König | 36ff39c | 2012-05-09 10:07:08 +0200 | [diff] [blame] | 703 | struct mutex lock; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 704 | struct list_head lru_vm; |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 705 | struct radeon_fence *active[RADEON_NUM_VM]; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 706 | struct radeon_sa_manager sa_manager; |
| 707 | uint32_t max_pfn; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 708 | /* number of VMIDs */ |
| 709 | unsigned nvm; |
| 710 | /* vram base address for page table entry */ |
| 711 | u64 vram_base_offset; |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 712 | /* is vm enabled? */ |
| 713 | bool enabled; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 714 | }; |
| 715 | |
| 716 | /* |
| 717 | * file private structure |
| 718 | */ |
| 719 | struct radeon_fpriv { |
| 720 | struct radeon_vm vm; |
| 721 | }; |
| 722 | |
| 723 | /* |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 724 | * R6xx+ IH ring |
| 725 | */ |
| 726 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 727 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 728 | volatile uint32_t *ring; |
| 729 | unsigned rptr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 730 | unsigned ring_size; |
| 731 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 732 | uint32_t ptr_mask; |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 733 | atomic_t lock; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 734 | bool enabled; |
| 735 | }; |
| 736 | |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 737 | struct r600_blit_cp_primitives { |
| 738 | void (*set_render_target)(struct radeon_device *rdev, int format, |
| 739 | int w, int h, u64 gpu_addr); |
| 740 | void (*cp_set_surface_sync)(struct radeon_device *rdev, |
| 741 | u32 sync_type, u32 size, |
| 742 | u64 mc_addr); |
| 743 | void (*set_shaders)(struct radeon_device *rdev); |
| 744 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); |
| 745 | void (*set_tex_resource)(struct radeon_device *rdev, |
| 746 | int format, int w, int h, int pitch, |
Alex Deucher | 9bb7703 | 2011-10-22 10:07:09 -0400 | [diff] [blame] | 747 | u64 gpu_addr, u32 size); |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 748 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
| 749 | int x2, int y2); |
| 750 | void (*draw_auto)(struct radeon_device *rdev); |
| 751 | void (*set_default_state)(struct radeon_device *rdev); |
| 752 | }; |
| 753 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 754 | struct r600_blit { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 755 | struct radeon_bo *shader_obj; |
Ilija Hadzic | 8eec9d6 | 2011-10-12 23:29:40 -0400 | [diff] [blame] | 756 | struct r600_blit_cp_primitives primitives; |
| 757 | int max_dim; |
| 758 | int ring_size_common; |
| 759 | int ring_size_per_loop; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 760 | u64 shader_gpu_addr; |
| 761 | u32 vs_offset, ps_offset; |
| 762 | u32 state_offset; |
| 763 | u32 state_len; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 764 | }; |
| 765 | |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 766 | /* |
| 767 | * SI RLC stuff |
| 768 | */ |
| 769 | struct si_rlc { |
| 770 | /* for power gating */ |
| 771 | struct radeon_bo *save_restore_obj; |
| 772 | uint64_t save_restore_gpu_addr; |
| 773 | /* for clear state */ |
| 774 | struct radeon_bo *clear_state_obj; |
| 775 | uint64_t clear_state_gpu_addr; |
| 776 | }; |
| 777 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 778 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 779 | struct radeon_ib *ib, struct radeon_vm *vm, |
| 780 | unsigned size); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 781 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 782 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 783 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 784 | struct radeon_ib *const_ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 785 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 786 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 787 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 788 | /* Ring access between begin & end cannot sleep */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 789 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
| 790 | struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 791 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
| 792 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 793 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 794 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
| 795 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 796 | void radeon_ring_undo(struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 797 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
| 798 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 799 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 800 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
| 801 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 802 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 803 | uint32_t **data); |
| 804 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 805 | unsigned size, uint32_t *data); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 806 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 807 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 808 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 809 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 810 | |
| 811 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 812 | /* r600 async dma */ |
| 813 | void r600_dma_stop(struct radeon_device *rdev); |
| 814 | int r600_dma_resume(struct radeon_device *rdev); |
| 815 | void r600_dma_fini(struct radeon_device *rdev); |
| 816 | |
Alex Deucher | 8c5fd7e | 2012-12-04 15:28:18 -0500 | [diff] [blame] | 817 | void cayman_dma_stop(struct radeon_device *rdev); |
| 818 | int cayman_dma_resume(struct radeon_device *rdev); |
| 819 | void cayman_dma_fini(struct radeon_device *rdev); |
| 820 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 821 | /* |
| 822 | * CS. |
| 823 | */ |
| 824 | struct radeon_cs_reloc { |
| 825 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 826 | struct radeon_bo *robj; |
| 827 | struct radeon_bo_list lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 828 | uint32_t handle; |
| 829 | uint32_t flags; |
| 830 | }; |
| 831 | |
| 832 | struct radeon_cs_chunk { |
| 833 | uint32_t chunk_id; |
| 834 | uint32_t length_dw; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 835 | int kpage_idx[2]; |
| 836 | uint32_t *kpage[2]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 837 | uint32_t *kdata; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 838 | void __user *user_ptr; |
| 839 | int last_copied_page; |
| 840 | int last_page_index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 841 | }; |
| 842 | |
| 843 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 844 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 845 | struct radeon_device *rdev; |
| 846 | struct drm_file *filp; |
| 847 | /* chunks */ |
| 848 | unsigned nchunks; |
| 849 | struct radeon_cs_chunk *chunks; |
| 850 | uint64_t *chunks_array; |
| 851 | /* IB */ |
| 852 | unsigned idx; |
| 853 | /* relocations */ |
| 854 | unsigned nrelocs; |
| 855 | struct radeon_cs_reloc *relocs; |
| 856 | struct radeon_cs_reloc **relocs_ptr; |
| 857 | struct list_head validated; |
Alex Deucher | cf4ccd0 | 2011-11-18 10:19:47 -0500 | [diff] [blame] | 858 | unsigned dma_reloc_idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 859 | /* indices of various chunks */ |
| 860 | int chunk_ib_idx; |
| 861 | int chunk_relocs_idx; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 862 | int chunk_flags_idx; |
Alex Deucher | dfcf5f3 | 2012-03-20 17:18:14 -0400 | [diff] [blame] | 863 | int chunk_const_ib_idx; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 864 | struct radeon_ib ib; |
| 865 | struct radeon_ib const_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 866 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 867 | unsigned family; |
Marek Olšák | e70f224 | 2011-10-25 01:38:45 +0200 | [diff] [blame] | 868 | int parser_error; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 869 | u32 cs_flags; |
| 870 | u32 ring; |
| 871 | s32 priority; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 872 | }; |
| 873 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 874 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 875 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 876 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 877 | struct radeon_cs_packet { |
| 878 | unsigned idx; |
| 879 | unsigned type; |
| 880 | unsigned reg; |
| 881 | unsigned opcode; |
| 882 | int count; |
| 883 | unsigned one_reg_wr; |
| 884 | }; |
| 885 | |
| 886 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 887 | struct radeon_cs_packet *pkt, |
| 888 | unsigned idx, unsigned reg); |
| 889 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 890 | struct radeon_cs_packet *pkt); |
| 891 | |
| 892 | |
| 893 | /* |
| 894 | * AGP |
| 895 | */ |
| 896 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 897 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 898 | void radeon_agp_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 899 | void radeon_agp_fini(struct radeon_device *rdev); |
| 900 | |
| 901 | |
| 902 | /* |
| 903 | * Writeback |
| 904 | */ |
| 905 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 906 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 907 | volatile uint32_t *wb; |
| 908 | uint64_t gpu_addr; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 909 | bool enabled; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 910 | bool use_event; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 911 | }; |
| 912 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 913 | #define RADEON_WB_SCRATCH_OFFSET 0 |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 914 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 915 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 916 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 917 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 918 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 919 | #define R600_WB_IH_WPTR_OFFSET 2048 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 920 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 921 | #define R600_WB_EVENT_OFFSET 3072 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 922 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 923 | /** |
| 924 | * struct radeon_pm - power management datas |
| 925 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 926 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 927 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 928 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 929 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 930 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 931 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 932 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 933 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 934 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 935 | * @needed_bandwidth: current bandwidth needs |
| 936 | * |
| 937 | * It keeps track of various data needed to take powermanagement decision. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 938 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 939 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 940 | * (type of memory, bus size, efficiency, ...) |
| 941 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 942 | |
| 943 | enum radeon_pm_method { |
| 944 | PM_METHOD_PROFILE, |
| 945 | PM_METHOD_DYNPM, |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 946 | }; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 947 | |
| 948 | enum radeon_dynpm_state { |
| 949 | DYNPM_STATE_DISABLED, |
| 950 | DYNPM_STATE_MINIMUM, |
| 951 | DYNPM_STATE_PAUSED, |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 952 | DYNPM_STATE_ACTIVE, |
| 953 | DYNPM_STATE_SUSPENDED, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 954 | }; |
| 955 | enum radeon_dynpm_action { |
| 956 | DYNPM_ACTION_NONE, |
| 957 | DYNPM_ACTION_MINIMUM, |
| 958 | DYNPM_ACTION_DOWNCLOCK, |
| 959 | DYNPM_ACTION_UPCLOCK, |
| 960 | DYNPM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 961 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 962 | |
| 963 | enum radeon_voltage_type { |
| 964 | VOLTAGE_NONE = 0, |
| 965 | VOLTAGE_GPIO, |
| 966 | VOLTAGE_VDDC, |
| 967 | VOLTAGE_SW |
| 968 | }; |
| 969 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 970 | enum radeon_pm_state_type { |
| 971 | POWER_STATE_TYPE_DEFAULT, |
| 972 | POWER_STATE_TYPE_POWERSAVE, |
| 973 | POWER_STATE_TYPE_BATTERY, |
| 974 | POWER_STATE_TYPE_BALANCED, |
| 975 | POWER_STATE_TYPE_PERFORMANCE, |
| 976 | }; |
| 977 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 978 | enum radeon_pm_profile_type { |
| 979 | PM_PROFILE_DEFAULT, |
| 980 | PM_PROFILE_AUTO, |
| 981 | PM_PROFILE_LOW, |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 982 | PM_PROFILE_MID, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 983 | PM_PROFILE_HIGH, |
| 984 | }; |
| 985 | |
| 986 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 987 | #define PM_PROFILE_LOW_SH_IDX 1 |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 988 | #define PM_PROFILE_MID_SH_IDX 2 |
| 989 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 990 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 991 | #define PM_PROFILE_MID_MH_IDX 5 |
| 992 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 993 | #define PM_PROFILE_MAX 7 |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 994 | |
| 995 | struct radeon_pm_profile { |
| 996 | int dpms_off_ps_idx; |
| 997 | int dpms_on_ps_idx; |
| 998 | int dpms_off_cm_idx; |
| 999 | int dpms_on_cm_idx; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 1000 | }; |
| 1001 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1002 | enum radeon_int_thermal_type { |
| 1003 | THERMAL_TYPE_NONE, |
| 1004 | THERMAL_TYPE_RV6XX, |
| 1005 | THERMAL_TYPE_RV770, |
| 1006 | THERMAL_TYPE_EVERGREEN, |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 1007 | THERMAL_TYPE_SUMO, |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 1008 | THERMAL_TYPE_NI, |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame] | 1009 | THERMAL_TYPE_SI, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1010 | }; |
| 1011 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1012 | struct radeon_voltage { |
| 1013 | enum radeon_voltage_type type; |
| 1014 | /* gpio voltage */ |
| 1015 | struct radeon_gpio_rec gpio; |
| 1016 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 1017 | bool active_high; /* voltage drop is active when bit is high */ |
| 1018 | /* VDDC voltage */ |
| 1019 | u8 vddc_id; /* index into vddc voltage table */ |
| 1020 | u8 vddci_id; /* index into vddci voltage table */ |
| 1021 | bool vddci_enabled; |
| 1022 | /* r6xx+ sw */ |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1023 | u16 voltage; |
| 1024 | /* evergreen+ vddci */ |
| 1025 | u16 vddci; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1026 | }; |
| 1027 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1028 | /* clock mode flags */ |
| 1029 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 1030 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1031 | struct radeon_pm_clock_info { |
| 1032 | /* memory clock */ |
| 1033 | u32 mclk; |
| 1034 | /* engine clock */ |
| 1035 | u32 sclk; |
| 1036 | /* voltage info */ |
| 1037 | struct radeon_voltage voltage; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1038 | /* standardized clock flags */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1039 | u32 flags; |
| 1040 | }; |
| 1041 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1042 | /* state flags */ |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1043 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1044 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1045 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1046 | enum radeon_pm_state_type type; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 1047 | struct radeon_pm_clock_info *clock_info; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1048 | /* number of valid clock modes in this power state */ |
| 1049 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1050 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1051 | /* standardized state flags */ |
| 1052 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 1053 | u32 misc; /* vbios specific flags */ |
| 1054 | u32 misc2; /* vbios specific flags */ |
| 1055 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1056 | }; |
| 1057 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 1058 | /* |
| 1059 | * Some modes are overclocked by very low value, accept them |
| 1060 | */ |
| 1061 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 1062 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1063 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1064 | struct mutex mutex; |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 1065 | /* write locked while reprogramming mclk */ |
| 1066 | struct rw_semaphore mclk_lock; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1067 | u32 active_crtcs; |
| 1068 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1069 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 1070 | bool vblank_sync; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1071 | fixed20_12 max_bandwidth; |
| 1072 | fixed20_12 igp_sideport_mclk; |
| 1073 | fixed20_12 igp_system_mclk; |
| 1074 | fixed20_12 igp_ht_link_clk; |
| 1075 | fixed20_12 igp_ht_link_width; |
| 1076 | fixed20_12 k8_bandwidth; |
| 1077 | fixed20_12 sideport_bandwidth; |
| 1078 | fixed20_12 ht_bandwidth; |
| 1079 | fixed20_12 core_bandwidth; |
| 1080 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1081 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1082 | fixed20_12 needed_bandwidth; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 1083 | struct radeon_power_state *power_state; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1084 | /* number of valid power states */ |
| 1085 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1086 | int current_power_state_index; |
| 1087 | int current_clock_mode_index; |
| 1088 | int requested_power_state_index; |
| 1089 | int requested_clock_mode_index; |
| 1090 | int default_power_state_index; |
| 1091 | u32 current_sclk; |
| 1092 | u32 current_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1093 | u16 current_vddc; |
| 1094 | u16 current_vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1095 | u32 default_sclk; |
| 1096 | u32 default_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1097 | u16 default_vddc; |
| 1098 | u16 default_vddci; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1099 | struct radeon_i2c_chan *i2c_bus; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1100 | /* selected pm method */ |
| 1101 | enum radeon_pm_method pm_method; |
| 1102 | /* dynpm power management */ |
| 1103 | struct delayed_work dynpm_idle_work; |
| 1104 | enum radeon_dynpm_state dynpm_state; |
| 1105 | enum radeon_dynpm_action dynpm_planned_action; |
| 1106 | unsigned long dynpm_action_timeout; |
| 1107 | bool dynpm_can_upclock; |
| 1108 | bool dynpm_can_downclock; |
| 1109 | /* profile-based power management */ |
| 1110 | enum radeon_pm_profile_type profile; |
| 1111 | int profile_index; |
| 1112 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1113 | /* internal thermal controller on rv6xx+ */ |
| 1114 | enum radeon_int_thermal_type int_thermal_type; |
| 1115 | struct device *int_hwmon_dev; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1116 | }; |
| 1117 | |
Alex Deucher | a4c9e2e | 2011-11-04 10:09:41 -0400 | [diff] [blame] | 1118 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
| 1119 | enum radeon_pm_state_type ps_type, |
| 1120 | int instance); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1121 | |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1122 | struct r600_audio { |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1123 | int channels; |
| 1124 | int rate; |
| 1125 | int bits_per_sample; |
| 1126 | u8 status_bits; |
| 1127 | u8 category_code; |
| 1128 | }; |
| 1129 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1130 | /* |
| 1131 | * Benchmarking |
| 1132 | */ |
Ilija Hadzic | 638dd7d | 2011-10-12 23:29:39 -0400 | [diff] [blame] | 1133 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1134 | |
| 1135 | |
| 1136 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1137 | * Testing |
| 1138 | */ |
| 1139 | void radeon_test_moves(struct radeon_device *rdev); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1140 | void radeon_test_ring_sync(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1141 | struct radeon_ring *cpA, |
| 1142 | struct radeon_ring *cpB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1143 | void radeon_test_syncing(struct radeon_device *rdev); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1144 | |
| 1145 | |
| 1146 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1147 | * Debugfs |
| 1148 | */ |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1149 | struct radeon_debugfs { |
| 1150 | struct drm_info_list *files; |
| 1151 | unsigned num_files; |
| 1152 | }; |
| 1153 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1154 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 1155 | struct drm_info_list *files, |
| 1156 | unsigned nfiles); |
| 1157 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1158 | |
| 1159 | |
| 1160 | /* |
| 1161 | * ASIC specific functions. |
| 1162 | */ |
| 1163 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1164 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1165 | void (*fini)(struct radeon_device *rdev); |
| 1166 | int (*resume)(struct radeon_device *rdev); |
| 1167 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1168 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1169 | int (*asic_reset)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1170 | /* ioctl hw specific callback. Some hw might want to perform special |
| 1171 | * operation on specific ioctl. For instance on wait idle some hw |
| 1172 | * might want to perform and HDP flush through MMIO as it seems that |
| 1173 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 1174 | * through ring. |
| 1175 | */ |
| 1176 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
| 1177 | /* check if 3D engine is idle */ |
| 1178 | bool (*gui_idle)(struct radeon_device *rdev); |
| 1179 | /* wait for mc_idle */ |
| 1180 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 1181 | /* get the reference clock */ |
| 1182 | u32 (*get_xclk)(struct radeon_device *rdev); |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 1183 | /* get the gpu clock counter */ |
| 1184 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1185 | /* gart */ |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1186 | struct { |
| 1187 | void (*tlb_flush)(struct radeon_device *rdev); |
| 1188 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 1189 | } gart; |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1190 | struct { |
| 1191 | int (*init)(struct radeon_device *rdev); |
| 1192 | void (*fini)(struct radeon_device *rdev); |
Christian König | 2a6f1ab | 2012-08-11 15:00:30 +0200 | [diff] [blame] | 1193 | |
| 1194 | u32 pt_ring_index; |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 1195 | void (*set_page)(struct radeon_device *rdev, |
| 1196 | struct radeon_ib *ib, |
| 1197 | uint64_t pe, |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1198 | uint64_t addr, unsigned count, |
| 1199 | uint32_t incr, uint32_t flags); |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1200 | } vm; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1201 | /* ring specific callbacks */ |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1202 | struct { |
| 1203 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1204 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1205 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1206 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1207 | struct radeon_semaphore *semaphore, bool emit_wait); |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1208 | int (*cs_parse)(struct radeon_cs_parser *p); |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1209 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1210 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1211 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1212 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
Alex Deucher | 498522b | 2012-10-02 14:43:38 -0400 | [diff] [blame] | 1213 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1214 | } ring[RADEON_NUM_RINGS]; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1215 | /* irqs */ |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1216 | struct { |
| 1217 | int (*set)(struct radeon_device *rdev); |
| 1218 | int (*process)(struct radeon_device *rdev); |
| 1219 | } irq; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1220 | /* displays */ |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1221 | struct { |
| 1222 | /* display watermarks */ |
| 1223 | void (*bandwidth_update)(struct radeon_device *rdev); |
| 1224 | /* get frame count */ |
| 1225 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 1226 | /* wait for vblank */ |
| 1227 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1228 | /* set backlight level */ |
| 1229 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1230 | /* get backlight level */ |
| 1231 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1232 | } display; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1233 | /* copy functions for bo handling */ |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1234 | struct { |
| 1235 | int (*blit)(struct radeon_device *rdev, |
| 1236 | uint64_t src_offset, |
| 1237 | uint64_t dst_offset, |
| 1238 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1239 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1240 | u32 blit_ring_index; |
| 1241 | int (*dma)(struct radeon_device *rdev, |
| 1242 | uint64_t src_offset, |
| 1243 | uint64_t dst_offset, |
| 1244 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1245 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1246 | u32 dma_ring_index; |
| 1247 | /* method used for bo copy */ |
| 1248 | int (*copy)(struct radeon_device *rdev, |
| 1249 | uint64_t src_offset, |
| 1250 | uint64_t dst_offset, |
| 1251 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1252 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1253 | /* ring used for bo copies */ |
| 1254 | u32 copy_ring_index; |
| 1255 | } copy; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1256 | /* surfaces */ |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1257 | struct { |
| 1258 | int (*set_reg)(struct radeon_device *rdev, int reg, |
| 1259 | uint32_t tiling_flags, uint32_t pitch, |
| 1260 | uint32_t offset, uint32_t obj_size); |
| 1261 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
| 1262 | } surface; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1263 | /* hotplug detect */ |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1264 | struct { |
| 1265 | void (*init)(struct radeon_device *rdev); |
| 1266 | void (*fini)(struct radeon_device *rdev); |
| 1267 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1268 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1269 | } hpd; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1270 | /* power management */ |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1271 | struct { |
| 1272 | void (*misc)(struct radeon_device *rdev); |
| 1273 | void (*prepare)(struct radeon_device *rdev); |
| 1274 | void (*finish)(struct radeon_device *rdev); |
| 1275 | void (*init_profile)(struct radeon_device *rdev); |
| 1276 | void (*get_dynpm_state)(struct radeon_device *rdev); |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1277 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
| 1278 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| 1279 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
| 1280 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| 1281 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
| 1282 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 1283 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1284 | } pm; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 1285 | /* pageflipping */ |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1286 | struct { |
| 1287 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
| 1288 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 1289 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
| 1290 | } pflip; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1291 | }; |
| 1292 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1293 | /* |
| 1294 | * Asic structures |
| 1295 | */ |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1296 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1297 | const unsigned *reg_safe_bm; |
| 1298 | unsigned reg_safe_bm_size; |
| 1299 | u32 hdp_cntl; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1300 | }; |
| 1301 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1302 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1303 | const unsigned *reg_safe_bm; |
| 1304 | unsigned reg_safe_bm_size; |
| 1305 | u32 resync_scratch; |
| 1306 | u32 hdp_cntl; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1307 | }; |
| 1308 | |
| 1309 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1310 | unsigned max_pipes; |
| 1311 | unsigned max_tile_pipes; |
| 1312 | unsigned max_simds; |
| 1313 | unsigned max_backends; |
| 1314 | unsigned max_gprs; |
| 1315 | unsigned max_threads; |
| 1316 | unsigned max_stack_entries; |
| 1317 | unsigned max_hw_contexts; |
| 1318 | unsigned max_gs_threads; |
| 1319 | unsigned sx_max_export_size; |
| 1320 | unsigned sx_max_export_pos_size; |
| 1321 | unsigned sx_max_export_smx_size; |
| 1322 | unsigned sq_num_cf_insts; |
| 1323 | unsigned tiling_nbanks; |
| 1324 | unsigned tiling_npipes; |
| 1325 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1326 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1327 | unsigned backend_map; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1328 | }; |
| 1329 | |
| 1330 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1331 | unsigned max_pipes; |
| 1332 | unsigned max_tile_pipes; |
| 1333 | unsigned max_simds; |
| 1334 | unsigned max_backends; |
| 1335 | unsigned max_gprs; |
| 1336 | unsigned max_threads; |
| 1337 | unsigned max_stack_entries; |
| 1338 | unsigned max_hw_contexts; |
| 1339 | unsigned max_gs_threads; |
| 1340 | unsigned sx_max_export_size; |
| 1341 | unsigned sx_max_export_pos_size; |
| 1342 | unsigned sx_max_export_smx_size; |
| 1343 | unsigned sq_num_cf_insts; |
| 1344 | unsigned sx_num_of_sets; |
| 1345 | unsigned sc_prim_fifo_size; |
| 1346 | unsigned sc_hiz_tile_fifo_size; |
| 1347 | unsigned sc_earlyz_tile_fifo_fize; |
| 1348 | unsigned tiling_nbanks; |
| 1349 | unsigned tiling_npipes; |
| 1350 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1351 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1352 | unsigned backend_map; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1353 | }; |
| 1354 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1355 | struct evergreen_asic { |
| 1356 | unsigned num_ses; |
| 1357 | unsigned max_pipes; |
| 1358 | unsigned max_tile_pipes; |
| 1359 | unsigned max_simds; |
| 1360 | unsigned max_backends; |
| 1361 | unsigned max_gprs; |
| 1362 | unsigned max_threads; |
| 1363 | unsigned max_stack_entries; |
| 1364 | unsigned max_hw_contexts; |
| 1365 | unsigned max_gs_threads; |
| 1366 | unsigned sx_max_export_size; |
| 1367 | unsigned sx_max_export_pos_size; |
| 1368 | unsigned sx_max_export_smx_size; |
| 1369 | unsigned sq_num_cf_insts; |
| 1370 | unsigned sx_num_of_sets; |
| 1371 | unsigned sc_prim_fifo_size; |
| 1372 | unsigned sc_hiz_tile_fifo_size; |
| 1373 | unsigned sc_earlyz_tile_fifo_size; |
| 1374 | unsigned tiling_nbanks; |
| 1375 | unsigned tiling_npipes; |
| 1376 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1377 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1378 | unsigned backend_map; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1379 | }; |
| 1380 | |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1381 | struct cayman_asic { |
| 1382 | unsigned max_shader_engines; |
| 1383 | unsigned max_pipes_per_simd; |
| 1384 | unsigned max_tile_pipes; |
| 1385 | unsigned max_simds_per_se; |
| 1386 | unsigned max_backends_per_se; |
| 1387 | unsigned max_texture_channel_caches; |
| 1388 | unsigned max_gprs; |
| 1389 | unsigned max_threads; |
| 1390 | unsigned max_gs_threads; |
| 1391 | unsigned max_stack_entries; |
| 1392 | unsigned sx_num_of_sets; |
| 1393 | unsigned sx_max_export_size; |
| 1394 | unsigned sx_max_export_pos_size; |
| 1395 | unsigned sx_max_export_smx_size; |
| 1396 | unsigned max_hw_contexts; |
| 1397 | unsigned sq_num_cf_insts; |
| 1398 | unsigned sc_prim_fifo_size; |
| 1399 | unsigned sc_hiz_tile_fifo_size; |
| 1400 | unsigned sc_earlyz_tile_fifo_size; |
| 1401 | |
| 1402 | unsigned num_shader_engines; |
| 1403 | unsigned num_shader_pipes_per_simd; |
| 1404 | unsigned num_tile_pipes; |
| 1405 | unsigned num_simds_per_se; |
| 1406 | unsigned num_backends_per_se; |
| 1407 | unsigned backend_disable_mask_per_asic; |
| 1408 | unsigned backend_map; |
| 1409 | unsigned num_texture_channel_caches; |
| 1410 | unsigned mem_max_burst_length_bytes; |
| 1411 | unsigned mem_row_size_in_kb; |
| 1412 | unsigned shader_engine_tile_size; |
| 1413 | unsigned num_gpus; |
| 1414 | unsigned multi_gpu_tile_size; |
| 1415 | |
| 1416 | unsigned tile_config; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1417 | }; |
| 1418 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1419 | struct si_asic { |
| 1420 | unsigned max_shader_engines; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1421 | unsigned max_tile_pipes; |
Alex Deucher | 1a8ca75 | 2012-06-01 18:58:22 -0400 | [diff] [blame] | 1422 | unsigned max_cu_per_sh; |
| 1423 | unsigned max_sh_per_se; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1424 | unsigned max_backends_per_se; |
| 1425 | unsigned max_texture_channel_caches; |
| 1426 | unsigned max_gprs; |
| 1427 | unsigned max_gs_threads; |
| 1428 | unsigned max_hw_contexts; |
| 1429 | unsigned sc_prim_fifo_size_frontend; |
| 1430 | unsigned sc_prim_fifo_size_backend; |
| 1431 | unsigned sc_hiz_tile_fifo_size; |
| 1432 | unsigned sc_earlyz_tile_fifo_size; |
| 1433 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1434 | unsigned num_tile_pipes; |
| 1435 | unsigned num_backends_per_se; |
| 1436 | unsigned backend_disable_mask_per_asic; |
| 1437 | unsigned backend_map; |
| 1438 | unsigned num_texture_channel_caches; |
| 1439 | unsigned mem_max_burst_length_bytes; |
| 1440 | unsigned mem_row_size_in_kb; |
| 1441 | unsigned shader_engine_tile_size; |
| 1442 | unsigned num_gpus; |
| 1443 | unsigned multi_gpu_tile_size; |
| 1444 | |
| 1445 | unsigned tile_config; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1446 | }; |
| 1447 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1448 | union radeon_asic_config { |
| 1449 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1450 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1451 | struct r600_asic r600; |
| 1452 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1453 | struct evergreen_asic evergreen; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1454 | struct cayman_asic cayman; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 1455 | struct si_asic si; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1456 | }; |
| 1457 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1458 | /* |
| 1459 | * asic initizalization from radeon_asic.c |
| 1460 | */ |
| 1461 | void radeon_agp_disable(struct radeon_device *rdev); |
| 1462 | int radeon_asic_init(struct radeon_device *rdev); |
| 1463 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1464 | |
| 1465 | /* |
| 1466 | * IOCTL. |
| 1467 | */ |
| 1468 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 1469 | struct drm_file *filp); |
| 1470 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1471 | struct drm_file *filp); |
| 1472 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1473 | struct drm_file *file_priv); |
| 1474 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1475 | struct drm_file *file_priv); |
| 1476 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1477 | struct drm_file *file_priv); |
| 1478 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1479 | struct drm_file *file_priv); |
| 1480 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1481 | struct drm_file *filp); |
| 1482 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1483 | struct drm_file *filp); |
| 1484 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1485 | struct drm_file *filp); |
| 1486 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 1487 | struct drm_file *filp); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1488 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 1489 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1490 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1491 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 1492 | struct drm_file *filp); |
| 1493 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 1494 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1495 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1496 | /* VRAM scratch page for HDP bug, default vram page */ |
| 1497 | struct r600_vram_scratch { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1498 | struct radeon_bo *robj; |
| 1499 | volatile uint32_t *ptr; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1500 | u64 gpu_addr; |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1501 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1502 | |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 1503 | /* |
| 1504 | * ACPI |
| 1505 | */ |
| 1506 | struct radeon_atif_notification_cfg { |
| 1507 | bool enabled; |
| 1508 | int command_code; |
| 1509 | }; |
| 1510 | |
| 1511 | struct radeon_atif_notifications { |
| 1512 | bool display_switch; |
| 1513 | bool expansion_mode_change; |
| 1514 | bool thermal_state; |
| 1515 | bool forced_power_state; |
| 1516 | bool system_power_state; |
| 1517 | bool display_conf_change; |
| 1518 | bool px_gfx_switch; |
| 1519 | bool brightness_change; |
| 1520 | bool dgpu_display_event; |
| 1521 | }; |
| 1522 | |
| 1523 | struct radeon_atif_functions { |
| 1524 | bool system_params; |
| 1525 | bool sbios_requests; |
| 1526 | bool select_active_disp; |
| 1527 | bool lid_state; |
| 1528 | bool get_tv_standard; |
| 1529 | bool set_tv_standard; |
| 1530 | bool get_panel_expansion_mode; |
| 1531 | bool set_panel_expansion_mode; |
| 1532 | bool temperature_change; |
| 1533 | bool graphics_device_types; |
| 1534 | }; |
| 1535 | |
| 1536 | struct radeon_atif { |
| 1537 | struct radeon_atif_notifications notifications; |
| 1538 | struct radeon_atif_functions functions; |
| 1539 | struct radeon_atif_notification_cfg notification_cfg; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1540 | struct radeon_encoder *encoder_for_bl; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 1541 | }; |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1542 | |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 1543 | struct radeon_atcs_functions { |
| 1544 | bool get_ext_state; |
| 1545 | bool pcie_perf_req; |
| 1546 | bool pcie_dev_rdy; |
| 1547 | bool pcie_bus_width; |
| 1548 | }; |
| 1549 | |
| 1550 | struct radeon_atcs { |
| 1551 | struct radeon_atcs_functions functions; |
| 1552 | }; |
| 1553 | |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 1554 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1555 | * Core structure, functions and helpers. |
| 1556 | */ |
| 1557 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 1558 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 1559 | |
| 1560 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1561 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1562 | struct drm_device *ddev; |
| 1563 | struct pci_dev *pdev; |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 1564 | struct rw_semaphore exclusive_lock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1565 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1566 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1567 | enum radeon_family family; |
| 1568 | unsigned long flags; |
| 1569 | int usec_timeout; |
| 1570 | enum radeon_pll_errata pll_errata; |
| 1571 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 1572 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1573 | int disp_priority; |
| 1574 | /* BIOS */ |
| 1575 | uint8_t *bios; |
| 1576 | bool is_atom_bios; |
| 1577 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1578 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1579 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 1580 | resource_size_t rmmio_base; |
| 1581 | resource_size_t rmmio_size; |
Daniel Vetter | 2c38515 | 2012-12-02 14:06:15 +0100 | [diff] [blame] | 1582 | /* protects concurrent MM_INDEX/DATA based register access */ |
| 1583 | spinlock_t mmio_idx_lock; |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1584 | void __iomem *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1585 | radeon_rreg_t mc_rreg; |
| 1586 | radeon_wreg_t mc_wreg; |
| 1587 | radeon_rreg_t pll_rreg; |
| 1588 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1589 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1590 | radeon_rreg_t pciep_rreg; |
| 1591 | radeon_wreg_t pciep_wreg; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1592 | /* io port */ |
| 1593 | void __iomem *rio_mem; |
| 1594 | resource_size_t rio_mem_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1595 | struct radeon_clock clock; |
| 1596 | struct radeon_mc mc; |
| 1597 | struct radeon_gart gart; |
| 1598 | struct radeon_mode_info mode_info; |
| 1599 | struct radeon_scratch scratch; |
| 1600 | struct radeon_mman mman; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 1601 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 1602 | wait_queue_head_t fence_queue; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 1603 | struct mutex ring_lock; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1604 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 1605 | bool ib_pool_ready; |
| 1606 | struct radeon_sa_manager ring_tmp_bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1607 | struct radeon_irq irq; |
| 1608 | struct radeon_asic *asic; |
| 1609 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1610 | struct radeon_pm pm; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1611 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1612 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1613 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1614 | bool shutdown; |
| 1615 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1616 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1617 | bool accel_working; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1618 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1619 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1620 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1621 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1622 | const struct firmware *mc_fw; /* NI MC firmware */ |
Alex Deucher | 0f0de06 | 2012-03-20 17:18:17 -0400 | [diff] [blame] | 1623 | const struct firmware *ce_fw; /* SI CE firmware */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1624 | struct r600_blit r600_blit; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1625 | struct r600_vram_scratch vram_scratch; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 1626 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1627 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 1628 | struct si_rlc rlc; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1629 | struct work_struct hotplug_work; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 1630 | struct work_struct audio_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1631 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1632 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Rafał Miłecki | 3299de9 | 2012-05-14 21:25:57 +0200 | [diff] [blame] | 1633 | bool audio_enabled; |
| 1634 | struct r600_audio audio_status; /* audio stuff */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1635 | struct notifier_block acpi_nb; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1636 | /* only one userspace can use Hyperz features or CMASK at a time */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 1637 | struct drm_file *hyperz_filp; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1638 | struct drm_file *cmask_filp; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1639 | /* i2c buses */ |
| 1640 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1641 | /* debugfs */ |
| 1642 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
| 1643 | unsigned debugfs_count; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1644 | /* virtual memory */ |
| 1645 | struct radeon_vm_manager vm_manager; |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 1646 | struct mutex gpu_clock_mutex; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 1647 | /* ACPI interface */ |
| 1648 | struct radeon_atif atif; |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 1649 | struct radeon_atcs atcs; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1650 | }; |
| 1651 | |
| 1652 | int radeon_device_init(struct radeon_device *rdev, |
| 1653 | struct drm_device *ddev, |
| 1654 | struct pci_dev *pdev, |
| 1655 | uint32_t flags); |
| 1656 | void radeon_device_fini(struct radeon_device *rdev); |
| 1657 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1658 | |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 1659 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
| 1660 | bool always_indirect); |
| 1661 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
| 1662 | bool always_indirect); |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 1663 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
| 1664 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1665 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1666 | /* |
| 1667 | * Cast helper |
| 1668 | */ |
| 1669 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1670 | |
| 1671 | /* |
| 1672 | * Registers read & write functions. |
| 1673 | */ |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1674 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
| 1675 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
| 1676 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
| 1677 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 1678 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
| 1679 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
| 1680 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
| 1681 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
| 1682 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1683 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1684 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1685 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1686 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1687 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1688 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1689 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1690 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Rafał Miłecki | aa5120d | 2010-02-18 20:24:28 +0000 | [diff] [blame] | 1691 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1692 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1693 | #define WREG32_P(reg, val, mask) \ |
| 1694 | do { \ |
| 1695 | uint32_t tmp_ = RREG32(reg); \ |
| 1696 | tmp_ &= (mask); \ |
| 1697 | tmp_ |= ((val) & ~(mask)); \ |
| 1698 | WREG32(reg, tmp_); \ |
| 1699 | } while (0) |
| 1700 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1701 | do { \ |
| 1702 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1703 | tmp_ &= (mask); \ |
| 1704 | tmp_ |= ((val) & ~(mask)); \ |
| 1705 | WREG32_PLL(reg, tmp_); \ |
| 1706 | } while (0) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 1707 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1708 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 1709 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1710 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1711 | /* |
| 1712 | * Indirect registers accessor |
| 1713 | */ |
| 1714 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1715 | { |
| 1716 | uint32_t r; |
| 1717 | |
| 1718 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1719 | r = RREG32(RADEON_PCIE_DATA); |
| 1720 | return r; |
| 1721 | } |
| 1722 | |
| 1723 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1724 | { |
| 1725 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1726 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1727 | } |
| 1728 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1729 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1730 | |
| 1731 | |
| 1732 | /* |
| 1733 | * ASICs helpers. |
| 1734 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 1735 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1736 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1737 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1738 | (rdev->family == CHIP_RV200) || \ |
| 1739 | (rdev->family == CHIP_RS100) || \ |
| 1740 | (rdev->family == CHIP_RS200) || \ |
| 1741 | (rdev->family == CHIP_RV250) || \ |
| 1742 | (rdev->family == CHIP_RV280) || \ |
| 1743 | (rdev->family == CHIP_RS300)) |
| 1744 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1745 | (rdev->family == CHIP_RV350) || \ |
| 1746 | (rdev->family == CHIP_R350) || \ |
| 1747 | (rdev->family == CHIP_RV380) || \ |
| 1748 | (rdev->family == CHIP_R420) || \ |
| 1749 | (rdev->family == CHIP_R423) || \ |
| 1750 | (rdev->family == CHIP_RV410) || \ |
| 1751 | (rdev->family == CHIP_RS400) || \ |
| 1752 | (rdev->family == CHIP_RS480)) |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 1753 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 1754 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 1755 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 1756 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 1757 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 1758 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 1759 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 1760 | (rdev->ddev->pdev->device == 0x689D)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1761 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 1762 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 1763 | (rdev->family == CHIP_RS690) || \ |
| 1764 | (rdev->family == CHIP_RS740) || \ |
| 1765 | (rdev->family >= CHIP_R600)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1766 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1767 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1768 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Alex Deucher | 633b916 | 2011-01-06 21:19:11 -0500 | [diff] [blame] | 1769 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 1770 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 1771 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
Alex Deucher | 8848f75 | 2012-03-20 17:18:28 -0400 | [diff] [blame] | 1772 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
| 1773 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
| 1774 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 624d352 | 2012-12-18 17:01:35 -0500 | [diff] [blame] | 1775 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1776 | |
| 1777 | /* |
| 1778 | * BIOS helpers. |
| 1779 | */ |
| 1780 | #define RBIOS8(i) (rdev->bios[i]) |
| 1781 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1782 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1783 | |
| 1784 | int radeon_combios_init(struct radeon_device *rdev); |
| 1785 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1786 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1787 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1788 | |
| 1789 | |
| 1790 | /* |
| 1791 | * RING helpers. |
| 1792 | */ |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1793 | #if DRM_DEBUG_CODE == 0 |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1794 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1795 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1796 | ring->ring[ring->wptr++] = v; |
| 1797 | ring->wptr &= ring->ptr_mask; |
| 1798 | ring->count_dw--; |
| 1799 | ring->ring_free_dw--; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1800 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1801 | #else |
| 1802 | /* With debugging this is just too big to inline */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1803 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1804 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1805 | |
| 1806 | /* |
| 1807 | * ASICs macro. |
| 1808 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1809 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1810 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1811 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1812 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Christian König | eb0c19c | 2012-02-23 15:18:44 +0100 | [diff] [blame] | 1813 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1814 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1815 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1816 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
| 1817 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1818 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
| 1819 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 1820 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
Alex Deucher | f712812 | 2012-02-23 17:53:45 -0500 | [diff] [blame] | 1821 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
| 1822 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) |
| 1823 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1824 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1825 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
Christian König | 312c4a8 | 2012-05-02 15:11:09 +0200 | [diff] [blame] | 1826 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
Alex Deucher | 498522b | 2012-10-02 14:43:38 -0400 | [diff] [blame] | 1827 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1828 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
| 1829 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1830 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1831 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1832 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 1833 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
| 1834 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1835 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
| 1836 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
| 1837 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
| 1838 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
| 1839 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
| 1840 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1841 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
| 1842 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
| 1843 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
| 1844 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
| 1845 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
| 1846 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
| 1847 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1848 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
| 1849 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1850 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1851 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
| 1852 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
| 1853 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
| 1854 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 1855 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1856 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
| 1857 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
| 1858 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
| 1859 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
| 1860 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
Alex Deucher | 69b62ad | 2012-08-03 11:50:54 -0400 | [diff] [blame] | 1861 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
| 1862 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
| 1863 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) |
| 1864 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
| 1865 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 1866 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 1867 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1868 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1869 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1870 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1871 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Alex Deucher | 410a341 | 2013-01-18 13:05:39 -0500 | [diff] [blame] | 1872 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1873 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1874 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1875 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1876 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1877 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1878 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1879 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1880 | extern void radeon_scratch_init(struct radeon_device *rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1881 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 1882 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 1883 | extern void radeon_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1884 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1885 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1886 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1887 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 1888 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 1889 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1890 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1891 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1892 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1893 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1894 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1895 | |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 1896 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1897 | * vm |
| 1898 | */ |
| 1899 | int radeon_vm_manager_init(struct radeon_device *rdev); |
| 1900 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
Christian König | d72d43c | 2012-10-09 13:31:18 +0200 | [diff] [blame] | 1901 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1902 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
Christian König | ddf03f5 | 2012-08-09 20:02:28 +0200 | [diff] [blame] | 1903 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
Christian König | 13e55c3 | 2012-10-09 13:31:19 +0200 | [diff] [blame] | 1904 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 1905 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
| 1906 | struct radeon_vm *vm, int ring); |
| 1907 | void radeon_vm_fence(struct radeon_device *rdev, |
| 1908 | struct radeon_vm *vm, |
| 1909 | struct radeon_fence *fence); |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1910 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1911 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
| 1912 | struct radeon_vm *vm, |
| 1913 | struct radeon_bo *bo, |
| 1914 | struct ttm_mem_reg *mem); |
| 1915 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
| 1916 | struct radeon_bo *bo); |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 1917 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
| 1918 | struct radeon_bo *bo); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1919 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
| 1920 | struct radeon_vm *vm, |
| 1921 | struct radeon_bo *bo); |
| 1922 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
| 1923 | struct radeon_bo_va *bo_va, |
| 1924 | uint64_t offset, |
| 1925 | uint32_t flags); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1926 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 1927 | struct radeon_bo_va *bo_va); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1928 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 1929 | /* audio */ |
| 1930 | void r600_audio_update_hdmi(struct work_struct *work); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1931 | |
| 1932 | /* |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 1933 | * R600 vram scratch functions |
| 1934 | */ |
| 1935 | int r600_vram_scratch_init(struct radeon_device *rdev); |
| 1936 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
| 1937 | |
| 1938 | /* |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 1939 | * r600 cs checking helper |
| 1940 | */ |
| 1941 | unsigned r600_mip_minify(unsigned size, unsigned level); |
| 1942 | bool r600_fmt_is_valid_color(u32 format); |
| 1943 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
| 1944 | int r600_fmt_get_blocksize(u32 format); |
| 1945 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
| 1946 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
| 1947 | |
| 1948 | /* |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 1949 | * r600 functions used by radeon_encoder.c |
| 1950 | */ |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 1951 | struct radeon_hdmi_acr { |
| 1952 | u32 clock; |
| 1953 | |
| 1954 | int n_32khz; |
| 1955 | int cts_32khz; |
| 1956 | |
| 1957 | int n_44_1khz; |
| 1958 | int cts_44_1khz; |
| 1959 | |
| 1960 | int n_48khz; |
| 1961 | int cts_48khz; |
| 1962 | |
| 1963 | }; |
| 1964 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 1965 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
| 1966 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 1967 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1968 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1969 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 1970 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
| 1971 | u32 tiling_pipe_num, |
| 1972 | u32 max_rb_num, |
| 1973 | u32 total_max_rb_num, |
| 1974 | u32 enabled_rb_mask); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1975 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 1976 | /* |
| 1977 | * evergreen functions used by radeon_encoder.c |
| 1978 | */ |
| 1979 | |
| 1980 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
| 1981 | |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1982 | extern int ni_init_microcode(struct radeon_device *rdev); |
Alex Deucher | 755d819 | 2011-03-02 20:07:34 -0500 | [diff] [blame] | 1983 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1984 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 1985 | /* radeon_acpi.c */ |
| 1986 | #if defined(CONFIG_ACPI) |
| 1987 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 1988 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
| 1989 | #else |
| 1990 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 1991 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
| 1992 | #endif |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 1993 | |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 1994 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
| 1995 | struct radeon_cs_packet *pkt, |
| 1996 | unsigned idx); |
Ilija Hadzic | 9ffb7a6 | 2013-01-02 18:27:42 -0500 | [diff] [blame] | 1997 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
Ilija Hadzic | c3ad63a | 2013-01-02 18:27:45 -0500 | [diff] [blame] | 1998 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
| 1999 | struct radeon_cs_packet *pkt); |
Ilija Hadzic | e971699 | 2013-01-02 18:27:46 -0500 | [diff] [blame] | 2000 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 2001 | struct radeon_cs_reloc **cs_reloc, |
| 2002 | int nomm); |
Ilija Hadzic | 40592a1 | 2013-01-02 18:27:43 -0500 | [diff] [blame] | 2003 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
| 2004 | uint32_t *vline_start_end, |
| 2005 | uint32_t *vline_status); |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 2006 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2007 | #include "radeon_object.h" |
| 2008 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2009 | #endif |