blob: b01c2363a2c76642310b3987d0fb794bb45ea5cd [file] [log] [blame]
Frank Barchard1a953052020-11-16 18:44:58 -08001# Copyright 2020 Google LLC
Marat Dukhan08c4a432019-10-03 09:29:21 -07002#
3# This source code is licensed under the BSD-style license found in the
4# LICENSE file in the root directory of this source tree.
5#
6# Description:
7# XNNPACK - optimized floating-point neural network operators library
8
Marat Dukhan10a38082020-04-17 03:58:35 -07009load(":build_defs.bzl", "xnnpack_aggregate_library", "xnnpack_benchmark", "xnnpack_binary", "xnnpack_cc_library", "xnnpack_gcc_std_copts", "xnnpack_min_size_copts", "xnnpack_msvc_std_copts", "xnnpack_optional_armcl_copts", "xnnpack_optional_armcl_deps", "xnnpack_optional_dnnl_copts", "xnnpack_optional_dnnl_deps", "xnnpack_optional_gemmlowp_copts", "xnnpack_optional_gemmlowp_deps", "xnnpack_optional_ruy_copts", "xnnpack_optional_ruy_deps", "xnnpack_optional_tflite_copts", "xnnpack_optional_tflite_deps", "xnnpack_std_cxxopts", "xnnpack_unit_test", "xnnpack_visibility")
Marat Dukhan69c3f2c2019-11-06 12:30:01 -080010
Marat Dukhan08c4a432019-10-03 09:29:21 -070011licenses(["notice"])
12
13exports_files(["LICENSE"])
14
Marat Dukhan1b354632020-03-23 12:50:22 -070015OPERATOR_BENCHMARK_DEPS = [
16 ":XNNPACK",
17 ":bench_utils",
18 "@cpuinfo",
Frank Barchard0c849732020-06-12 13:31:32 -070019 "@FP16",
Marat Dukhan1b354632020-03-23 12:50:22 -070020 "@pthreadpool",
21]
22
Marat Dukhan08c4a432019-10-03 09:29:21 -070023MICROKERNEL_BENCHMARK_DEPS = [
Marat Dukhan2c724952021-07-27 18:46:30 -070024 ":bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -070025 ":bench_utils",
Frank Barchard7e955972019-10-11 10:34:25 -070026 ":enable_assembly",
Marat Dukhan08c4a432019-10-03 09:29:21 -070027 "@cpuinfo",
28 "@FP16",
29 "@pthreadpool",
30]
31
Marat Dukhan6adff4e2019-10-14 18:32:07 -070032ACCURACY_EVAL_DEPS = [
33 ":XNNPACK",
Marat Dukhan2c724952021-07-27 18:46:30 -070034 ":bench_microkernels",
Marat Dukhan6adff4e2019-10-14 18:32:07 -070035 "@FP16",
36 "@pthreadpool",
37]
38
Marat Dukhan08c4a432019-10-03 09:29:21 -070039MICROKERNEL_TEST_DEPS = [
Marat Dukhan2c724952021-07-27 18:46:30 -070040 ":test_microkernels",
Frank Barchard7e955972019-10-11 10:34:25 -070041 ":enable_assembly",
Marat Dukhan08c4a432019-10-03 09:29:21 -070042 "@cpuinfo",
43 "@FP16",
44 "@pthreadpool",
45]
46
Marat Dukhan1b354632020-03-23 12:50:22 -070047OPERATOR_TEST_DEPS = [
Marat Dukhan33fcf782020-05-24 14:27:15 -070048 ":XNNPACK_test_mode",
Marat Dukhan1b354632020-03-23 12:50:22 -070049 "@pthreadpool",
50 "@FP16",
51]
52
Marat Dukhan08c4a432019-10-03 09:29:21 -070053OPERATOR_SRCS = [
Marat Dukhane8265432020-04-28 18:42:59 -070054 "src/operators/argmax-pooling-nhwc.c",
55 "src/operators/average-pooling-nhwc.c",
56 "src/operators/binary-elementwise-nd.c",
Marat Dukhane8265432020-04-28 18:42:59 -070057 "src/operators/channel-shuffle-nc.c",
Marat Dukhan065b11e2020-05-22 09:49:41 -070058 "src/operators/constant-pad-nd.c",
Marat Dukhane8265432020-04-28 18:42:59 -070059 "src/operators/convolution-nchw.c",
60 "src/operators/convolution-nhwc.c",
61 "src/operators/deconvolution-nhwc.c",
Marat Dukhan13b68f22020-11-12 11:55:19 -080062 "src/operators/depth-to-space-nchw2nhwc.c",
Marat Dukhan0e521172020-11-25 13:10:04 -080063 "src/operators/depth-to-space-nhwc.c",
Marat Dukhane8265432020-04-28 18:42:59 -070064 "src/operators/fully-connected-nc.c",
65 "src/operators/global-average-pooling-ncw.c",
66 "src/operators/global-average-pooling-nwc.c",
Marat Dukhane8265432020-04-28 18:42:59 -070067 "src/operators/leaky-relu-nc.c",
68 "src/operators/max-pooling-nhwc.c",
69 "src/operators/prelu-nc.c",
Artsiom Ablavatski97918102020-10-27 15:52:59 -070070 "src/operators/resize-bilinear-nchw.c",
Marat Dukhane8265432020-04-28 18:42:59 -070071 "src/operators/resize-bilinear-nhwc.c",
72 "src/operators/sigmoid-nc.c",
73 "src/operators/softmax-nc.c",
Marat Dukhanc3065f52020-06-04 13:33:32 -070074 "src/operators/unary-elementwise-nc.c",
Marat Dukhane8265432020-04-28 18:42:59 -070075 "src/operators/unpooling-nhwc.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -070076]
77
Marat Dukhan95e8b7a2020-06-03 12:46:26 -070078SUBGRAPH_SRCS = [
Marat Dukhan5fab4092020-06-10 01:28:28 -070079 "src/subgraph/abs.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -070080 "src/subgraph/add2.c",
81 "src/subgraph/argmax-pooling-2d.c",
82 "src/subgraph/average-pooling-2d.c",
Marat Dukhan5fab4092020-06-10 01:28:28 -070083 "src/subgraph/bankers-rounding.c",
84 "src/subgraph/ceiling.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -070085 "src/subgraph/clamp.c",
86 "src/subgraph/convolution-2d.c",
87 "src/subgraph/deconvolution-2d.c",
Artsiom Ablavatskibbe85062020-11-05 14:07:37 -080088 "src/subgraph/depth-to-space.c",
Frank Barchard9cef5ea2020-11-18 14:52:08 -080089 "src/subgraph/depthwise-convolution-2d.c",
Marat Dukhan9d3a4592020-06-05 16:52:42 -070090 "src/subgraph/divide.c",
Marat Dukhana1600202020-12-01 22:17:16 -080091 "src/subgraph/elu.c",
Marat Dukhan5fab4092020-06-10 01:28:28 -070092 "src/subgraph/floor.c",
Frank Barchard04336c12020-10-22 16:48:55 -070093 "src/subgraph/fully-connected.c",
Marat Dukhana059b7d2020-06-11 11:41:27 -070094 "src/subgraph/global-average-pooling-2d.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -070095 "src/subgraph/hardswish.c",
Marat Dukhan5bbebac2020-06-10 19:42:15 -070096 "src/subgraph/leaky-relu.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -070097 "src/subgraph/max-pooling-2d.c",
Marat Dukhan9d3a4592020-06-05 16:52:42 -070098 "src/subgraph/maximum2.c",
99 "src/subgraph/minimum2.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -0700100 "src/subgraph/multiply2.c",
Marat Dukhan5fab4092020-06-10 01:28:28 -0700101 "src/subgraph/negate.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -0700102 "src/subgraph/prelu.c",
103 "src/subgraph/sigmoid.c",
104 "src/subgraph/softmax.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700105 "src/subgraph/square-root.c",
106 "src/subgraph/square.c",
107 "src/subgraph/squared-difference.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -0700108 "src/subgraph/static-constant-pad.c",
Marat Dukhand27202d2020-07-09 23:43:40 -0700109 "src/subgraph/static-reshape.c",
Marat Dukhanaff24e22020-07-23 01:43:58 -0700110 "src/subgraph/static-resize-bilinear-2d.c",
Marat Dukhan9d3a4592020-06-05 16:52:42 -0700111 "src/subgraph/subtract.c",
Marat Dukhan95e8b7a2020-06-03 12:46:26 -0700112 "src/subgraph/unpooling-2d.c",
113]
114
Marat Dukhan3a77ea72019-12-23 12:10:24 -0800115TABLE_SRCS = [
116 "src/tables/exp2-k-over-64.c",
117 "src/tables/exp2-k-over-2048.c",
Marat Dukhande390d42020-11-29 19:32:18 -0800118 "src/tables/exp2minus-k-over-4.c",
119 "src/tables/exp2minus-k-over-8.c",
Marat Dukhanc60742b2020-11-23 12:33:27 -0800120 "src/tables/exp2minus-k-over-16.c",
Marat Dukhan1f256fc2020-09-24 21:27:14 -0700121 "src/tables/exp2minus-k-over-64.c",
122 "src/tables/exp2minus-k-over-2048.c",
Marat Dukhan3a77ea72019-12-23 12:10:24 -0800123]
124
Marat Dukhan2c724952021-07-27 18:46:30 -0700125PROD_SCALAR_MICROKERNEL_SRCS = [
126 "src/f32-argmaxpool/4x-scalar-c1.c",
127 "src/f32-argmaxpool/9p8x-scalar-c1.c",
128 "src/f32-argmaxpool/9x-scalar-c1.c",
129 "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
130 "src/f32-avgpool/9x-minmax-scalar-c1.c",
131 "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
132 "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
133 "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
134 "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
135 "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
136 "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
137 "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
138 "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
139 "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
140 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
141 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-4x1.c",
142 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
143 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1-acc2.c",
144 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
145 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc2.c",
146 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
147 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc2.c",
148 "src/f32-gavgpool-cw/scalar-x1.c",
149 "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
150 "src/f32-gavgpool/7x-minmax-scalar-c1.c",
151 "src/f32-gemm/gen/1x4-minmax-scalar.c",
152 "src/f32-gemm/gen/1x4-relu-scalar.c",
153 "src/f32-gemm/gen/1x4-scalar.c",
154 "src/f32-gemm/gen/2x4-minmax-scalar.c",
155 "src/f32-gemm/gen/2x4-relu-scalar.c",
156 "src/f32-gemm/gen/2x4-scalar.c",
157 "src/f32-gemm/gen/4x2-minmax-scalar.c",
158 "src/f32-gemm/gen/4x2-relu-scalar.c",
159 "src/f32-gemm/gen/4x2-scalar.c",
160 "src/f32-gemm/gen/4x4-minmax-scalar.c",
161 "src/f32-gemm/gen/4x4-relu-scalar.c",
162 "src/f32-gemm/gen/4x4-scalar.c",
163 "src/f32-ibilinear-chw/gen/scalar-p4.c",
164 "src/f32-ibilinear/gen/scalar-c2.c",
165 "src/f32-igemm/gen/1x4-minmax-scalar.c",
166 "src/f32-igemm/gen/1x4-relu-scalar.c",
167 "src/f32-igemm/gen/1x4-scalar.c",
168 "src/f32-igemm/gen/2x4-minmax-scalar.c",
169 "src/f32-igemm/gen/2x4-relu-scalar.c",
170 "src/f32-igemm/gen/2x4-scalar.c",
171 "src/f32-igemm/gen/4x2-minmax-scalar.c",
172 "src/f32-igemm/gen/4x2-relu-scalar.c",
173 "src/f32-igemm/gen/4x2-scalar.c",
174 "src/f32-igemm/gen/4x4-minmax-scalar.c",
175 "src/f32-igemm/gen/4x4-relu-scalar.c",
176 "src/f32-igemm/gen/4x4-scalar.c",
177 "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
178 "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
179 "src/f32-pavgpool/9x-minmax-scalar-c1.c",
180 "src/f32-prelu/gen/scalar-2x4.c",
181 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4-acc2.c",
182 "src/f32-rmax/scalar.c",
183 "src/f32-spmm/gen/8x1-minmax-scalar.c",
184 "src/f32-spmm/gen/8x2-minmax-scalar.c",
185 "src/f32-spmm/gen/8x4-minmax-scalar.c",
186 "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
187 "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
188 "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
189 "src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c",
190 "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
191 "src/f32-vbinary/gen/vdivc-minmax-scalar-x8.c",
192 "src/f32-vbinary/gen/vmax-scalar-x8.c",
193 "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
194 "src/f32-vbinary/gen/vmin-scalar-x8.c",
195 "src/f32-vbinary/gen/vminc-scalar-x8.c",
196 "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
197 "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
198 "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
199 "src/f32-vbinary/gen/vrdivc-minmax-scalar-x8.c",
200 "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
201 "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
202 "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
203 "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
204 "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
205 "src/f32-vclamp/gen/vclamp-scalar-x4.c",
206 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
207 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
208 "src/f32-vhswish/gen/vhswish-scalar-x4.c",
209 "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
210 "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
211 "src/f32-vrelu/gen/vrelu-scalar-x8.c",
212 "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
213 "src/f32-vrnd/gen/vrndd-scalar-libm-x4.c",
214 "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
215 "src/f32-vrnd/gen/vrndne-scalar-libm-x4.c",
216 "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
217 "src/f32-vrnd/gen/vrndu-scalar-libm-x4.c",
218 "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
219 "src/f32-vrnd/gen/vrndz-scalar-libm-x4.c",
220 "src/f32-vsigmoid/gen/vsigmoid-scalar-lut64-p2-div-x2.c",
221 "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
222 "src/f32-vunary/gen/vabs-scalar-x4.c",
223 "src/f32-vunary/gen/vneg-scalar-x4.c",
224 "src/f32-vunary/gen/vsqr-scalar-x4.c",
225 "src/params-init.c",
226 "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-magic.c",
227 "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-magic.c",
228 "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-magic.c",
229 "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-magic.c",
230 "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-magic.c",
231 "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-magic.c",
232 "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-magic.c",
233 "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-magic.c",
234 "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-magic.c",
235 "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-magic.c",
Marat Dukhan66a3ca12021-08-06 18:24:19 -0700236 "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-magic.c",
237 "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-magic.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700238 "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-magic.c",
239 "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-magic.c",
240 "src/qs8-gavgpool/gen/7p7x-minmax-scalar-c1.c",
241 "src/qs8-gavgpool/gen/7p7x-minmax-scalar-c4.c",
242 "src/qs8-gavgpool/gen/7x-minmax-scalar-c1.c",
243 "src/qs8-gavgpool/gen/7x-minmax-scalar-c4.c",
244 "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-magic.c",
245 "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-magic.c",
246 "src/qs8-gemm/gen/1x4-minmax-rndnu-scalar.c",
247 "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-magic.c",
248 "src/qs8-gemm/gen/3x4-minmax-rndnu-scalar.c",
249 "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-magic.c",
250 "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-magic.c",
251 "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-magic.c",
252 "src/qs8-igemm/gen/1x4-minmax-rndnu-scalar.c",
253 "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-magic.c",
254 "src/qs8-igemm/gen/3x4-minmax-rndnu-scalar.c",
255 "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-magic.c",
Marat Dukhan66a3ca12021-08-06 18:24:19 -0700256 "src/qs8-vadd/gen/minmax-scalar-x1.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700257 "src/qs8-vadd/gen/minmax-scalar-x4.c",
Marat Dukhan66a3ca12021-08-06 18:24:19 -0700258 "src/qs8-vaddc/gen/minmax-scalar-x1.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700259 "src/qs8-vaddc/gen/minmax-scalar-x4.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -0700260 "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
261 "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700262 "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
263 "src/qu8-avgpool/9x-minmax-scalar-c1.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700264 "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-magic.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700265 "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-magic.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700266 "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-magic.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700267 "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-magic.c",
268 "src/qu8-gavgpool/7p7x-minmax-scalar-c1.c",
269 "src/qu8-gavgpool/7x-minmax-scalar-c1.c",
270 "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-magic.c",
271 "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-magic.c",
272 "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-magic.c",
273 "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-magic.c",
274 "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-magic.c",
275 "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-magic.c",
276 "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-magic.c",
277 "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-magic.c",
278 "src/qu8-vadd/gen/minmax-scalar-x1.c",
279 "src/qu8-vadd/gen/minmax-scalar-x4.c",
280 "src/qu8-vaddc/gen/minmax-scalar-x1.c",
281 "src/qu8-vaddc/gen/minmax-scalar-x4.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -0700282 "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
283 "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
Marat Dukhan23147532021-08-16 07:26:56 -0700284 "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
Marat Dukhane79acb72021-08-16 19:03:53 -0700285 "src/s8-vclamp/scalar-x4.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700286 "src/u8-lut32norm/scalar.c",
287 "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
288 "src/u8-rmax/scalar.c",
289 "src/u8-vclamp/scalar-x4.c",
290 "src/x8-lut/scalar.c",
291 "src/x8-zip/x2-scalar.c",
292 "src/x8-zip/x3-scalar.c",
293 "src/x8-zip/x4-scalar.c",
294 "src/x8-zip/xm-scalar.c",
295 "src/x32-depthtospace2d-chw2hwc/scalar.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700296 "src/x32-packx/x2-scalar.c",
297 "src/x32-packx/x3-scalar.c",
298 "src/x32-packx/x4-scalar.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700299 "src/x32-unpool/scalar.c",
300 "src/x32-zip/x2-scalar.c",
301 "src/x32-zip/x3-scalar.c",
302 "src/x32-zip/x4-scalar.c",
303 "src/x32-zip/xm-scalar.c",
304 "src/xx-copy/memcpy.c",
Marat Dukhan933051b2021-08-07 16:26:15 -0700305 "src/xx-fill/scalar-x16.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -0700306 "src/xx-pad/scalar.c",
Marat Dukhan2c724952021-07-27 18:46:30 -0700307]
308
309ALL_SCALAR_MICROKERNEL_SRCS = [
Marat Dukhan329da642019-11-19 21:44:39 -0800310 "src/f32-argmaxpool/4x-scalar-c1.c",
Marat Dukhan1e782c42019-11-21 17:02:40 -0800311 "src/f32-argmaxpool/9p8x-scalar-c1.c",
Marat Dukhan329da642019-11-19 21:44:39 -0800312 "src/f32-argmaxpool/9x-scalar-c1.c",
Marat Dukhan99936602020-04-11 16:47:01 -0700313 "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
314 "src/f32-avgpool/9x-minmax-scalar-c1.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700315 "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700316 "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
Marat Dukhan1f29b802020-05-15 23:46:39 -0700317 "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700318 "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700319 "src/f32-dwconv/gen/up1x4-minmax-scalar.c",
320 "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
321 "src/f32-dwconv/gen/up1x4-scalar.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700322 "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700323 "src/f32-dwconv/gen/up1x9-minmax-scalar.c",
324 "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
325 "src/f32-dwconv/gen/up1x9-scalar.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700326 "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700327 "src/f32-dwconv/gen/up1x25-minmax-scalar.c",
328 "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
329 "src/f32-dwconv/gen/up1x25-scalar.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700330 "src/f32-dwconv/gen/up2x4-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700331 "src/f32-dwconv/gen/up2x4-minmax-scalar.c",
332 "src/f32-dwconv/gen/up2x4-scalar-acc2.c",
333 "src/f32-dwconv/gen/up2x4-scalar.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700334 "src/f32-dwconv/gen/up2x9-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700335 "src/f32-dwconv/gen/up2x9-minmax-scalar.c",
336 "src/f32-dwconv/gen/up2x9-scalar-acc2.c",
337 "src/f32-dwconv/gen/up2x9-scalar.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700338 "src/f32-dwconv/gen/up2x25-minmax-scalar-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700339 "src/f32-dwconv/gen/up2x25-minmax-scalar.c",
340 "src/f32-dwconv/gen/up2x25-scalar-acc2.c",
341 "src/f32-dwconv/gen/up2x25-scalar.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700342 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc2.c",
343 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc3.c",
344 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc4.c",
Marat Dukhan91249d22020-10-24 12:02:51 -0700345 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700346 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
Marat Dukhan91249d22020-10-24 12:02:51 -0700347 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1.c",
348 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-3x1.c",
349 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-4x1.c",
350 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-5x1.c",
351 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-6x1.c",
Marat Dukhancf5b3c32020-10-25 19:21:10 -0700352 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
353 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc3.c",
354 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700355 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1.c",
Marat Dukhancf5b3c32020-10-25 19:21:10 -0700356 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700357 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1.c",
358 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-3x1.c",
359 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-4x1.c",
Marat Dukhanc4efb002020-10-25 23:14:47 -0700360 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc2.c",
361 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc3.c",
362 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc4.c",
363 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700364 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1.c",
Marat Dukhanc4efb002020-10-25 23:14:47 -0700365 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc2.c",
366 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc3.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700367 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1.c",
Marat Dukhanc4efb002020-10-25 23:14:47 -0700368 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-3x1-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -0700369 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-3x1.c",
Marat Dukhan29c0c332020-10-28 22:11:00 -0700370 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc2.c",
371 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc3.c",
372 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc4.c",
373 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
374 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1.c",
375 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc2.c",
376 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc3.c",
377 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1.c",
378 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1-acc2.c",
379 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1.c",
Marat Dukhan1f29b802020-05-15 23:46:39 -0700380 "src/f32-gavgpool-cw/scalar-x1.c",
Marat Dukhan99936602020-04-11 16:47:01 -0700381 "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
382 "src/f32-gavgpool/7x-minmax-scalar-c1.c",
Frank Barchardc9c320e2020-08-07 22:12:46 -0700383 "src/f32-gemm/gen-inc/1x4inc-minmax-scalar.c",
384 "src/f32-gemm/gen-inc/2x4inc-minmax-scalar.c",
385 "src/f32-gemm/gen-inc/4x4inc-minmax-scalar.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700386 "src/f32-gemm/gen/1x4-minmax-scalar.c",
387 "src/f32-gemm/gen/1x4-relu-scalar.c",
388 "src/f32-gemm/gen/1x4-scalar.c",
389 "src/f32-gemm/gen/2x4-minmax-scalar.c",
390 "src/f32-gemm/gen/2x4-relu-scalar.c",
391 "src/f32-gemm/gen/2x4-scalar.c",
392 "src/f32-gemm/gen/4x2-minmax-scalar.c",
393 "src/f32-gemm/gen/4x2-relu-scalar.c",
394 "src/f32-gemm/gen/4x2-scalar.c",
395 "src/f32-gemm/gen/4x4-minmax-scalar.c",
396 "src/f32-gemm/gen/4x4-relu-scalar.c",
397 "src/f32-gemm/gen/4x4-scalar.c",
XNNPACK Team21432672020-10-19 19:58:48 -0700398 "src/f32-ibilinear-chw/gen/scalar-p1.c",
399 "src/f32-ibilinear-chw/gen/scalar-p2.c",
400 "src/f32-ibilinear-chw/gen/scalar-p4.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700401 "src/f32-ibilinear/gen/scalar-c1.c",
402 "src/f32-ibilinear/gen/scalar-c2.c",
403 "src/f32-ibilinear/gen/scalar-c4.c",
Marat Dukhan1c587112020-04-08 20:04:28 -0700404 "src/f32-igemm/gen/1x4-minmax-scalar.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700405 "src/f32-igemm/gen/1x4-relu-scalar.c",
406 "src/f32-igemm/gen/1x4-scalar.c",
Marat Dukhan1c587112020-04-08 20:04:28 -0700407 "src/f32-igemm/gen/2x4-minmax-scalar.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700408 "src/f32-igemm/gen/2x4-relu-scalar.c",
409 "src/f32-igemm/gen/2x4-scalar.c",
Marat Dukhan1c587112020-04-08 20:04:28 -0700410 "src/f32-igemm/gen/4x2-minmax-scalar.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700411 "src/f32-igemm/gen/4x2-relu-scalar.c",
412 "src/f32-igemm/gen/4x2-scalar.c",
Marat Dukhan1c587112020-04-08 20:04:28 -0700413 "src/f32-igemm/gen/4x4-minmax-scalar.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700414 "src/f32-igemm/gen/4x4-relu-scalar.c",
415 "src/f32-igemm/gen/4x4-scalar.c",
Marat Dukhan99936602020-04-11 16:47:01 -0700416 "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
417 "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
418 "src/f32-pavgpool/9x-minmax-scalar-c1.c",
Marat Dukhan1c587112020-04-08 20:04:28 -0700419 "src/f32-ppmm/gen/2x4-minmax-scalar.c",
420 "src/f32-ppmm/gen/3x3-minmax-scalar.c",
421 "src/f32-ppmm/gen/4x2-minmax-scalar.c",
422 "src/f32-ppmm/gen/4x4-minmax-scalar.c",
Marat Dukhan40a672f2019-11-25 03:08:22 -0800423 "src/f32-prelu/gen/scalar-2x1.c",
424 "src/f32-prelu/gen/scalar-2x4.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800425 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x1.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800426 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x2-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700427 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x2.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800428 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4-acc2.c",
429 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700430 "src/f32-raddstoreexpminusmax/gen/scalar-lut64-p2-x4.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800431 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x1.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800432 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x2-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700433 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x2.c",
Marat Dukhanf46f6752020-01-21 11:03:49 -0800434 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4-acc2.c",
435 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700436 "src/f32-raddstoreexpminusmax/gen/scalar-p5-x4.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700437 "src/f32-rmax/scalar.c",
Marat Dukhan355ab432020-04-09 19:01:52 -0700438 "src/f32-spmm/gen/1x1-minmax-scalar-pipelined.c",
439 "src/f32-spmm/gen/1x1-minmax-scalar.c",
440 "src/f32-spmm/gen/2x1-minmax-scalar-pipelined.c",
441 "src/f32-spmm/gen/2x1-minmax-scalar.c",
442 "src/f32-spmm/gen/4x1-minmax-scalar-pipelined.c",
443 "src/f32-spmm/gen/4x1-minmax-scalar.c",
444 "src/f32-spmm/gen/8x1-minmax-scalar-pipelined.c",
445 "src/f32-spmm/gen/8x1-minmax-scalar.c",
446 "src/f32-spmm/gen/8x2-minmax-scalar.c",
447 "src/f32-spmm/gen/8x4-minmax-scalar.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -0700448 "src/f32-vbinary/gen/vadd-minmax-scalar-x1.c",
449 "src/f32-vbinary/gen/vadd-minmax-scalar-x2.c",
450 "src/f32-vbinary/gen/vadd-minmax-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700451 "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
Frank Barchard674778d2020-08-08 10:17:25 -0700452 "src/f32-vbinary/gen/vadd-relu-scalar-x1.c",
453 "src/f32-vbinary/gen/vadd-relu-scalar-x2.c",
454 "src/f32-vbinary/gen/vadd-relu-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700455 "src/f32-vbinary/gen/vadd-relu-scalar-x8.c",
Frank Barchard8e229db2020-07-06 23:31:35 -0700456 "src/f32-vbinary/gen/vadd-scalar-x1.c",
457 "src/f32-vbinary/gen/vadd-scalar-x2.c",
458 "src/f32-vbinary/gen/vadd-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700459 "src/f32-vbinary/gen/vadd-scalar-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -0700460 "src/f32-vbinary/gen/vaddc-minmax-scalar-x1.c",
461 "src/f32-vbinary/gen/vaddc-minmax-scalar-x2.c",
462 "src/f32-vbinary/gen/vaddc-minmax-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700463 "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
Frank Barchard674778d2020-08-08 10:17:25 -0700464 "src/f32-vbinary/gen/vaddc-relu-scalar-x1.c",
465 "src/f32-vbinary/gen/vaddc-relu-scalar-x2.c",
466 "src/f32-vbinary/gen/vaddc-relu-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700467 "src/f32-vbinary/gen/vaddc-relu-scalar-x8.c",
Frank Barchard8e229db2020-07-06 23:31:35 -0700468 "src/f32-vbinary/gen/vaddc-scalar-x1.c",
469 "src/f32-vbinary/gen/vaddc-scalar-x2.c",
470 "src/f32-vbinary/gen/vaddc-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700471 "src/f32-vbinary/gen/vaddc-scalar-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -0700472 "src/f32-vbinary/gen/vdiv-minmax-scalar-x1.c",
473 "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
474 "src/f32-vbinary/gen/vdiv-minmax-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700475 "src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c",
Frank Barchard674778d2020-08-08 10:17:25 -0700476 "src/f32-vbinary/gen/vdiv-relu-scalar-x1.c",
477 "src/f32-vbinary/gen/vdiv-relu-scalar-x2.c",
478 "src/f32-vbinary/gen/vdiv-relu-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700479 "src/f32-vbinary/gen/vdiv-relu-scalar-x8.c",
Frank Barchard8e229db2020-07-06 23:31:35 -0700480 "src/f32-vbinary/gen/vdiv-scalar-x1.c",
481 "src/f32-vbinary/gen/vdiv-scalar-x2.c",
482 "src/f32-vbinary/gen/vdiv-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700483 "src/f32-vbinary/gen/vdiv-scalar-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -0700484 "src/f32-vbinary/gen/vdivc-minmax-scalar-x1.c",
485 "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
486 "src/f32-vbinary/gen/vdivc-minmax-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700487 "src/f32-vbinary/gen/vdivc-minmax-scalar-x8.c",
Frank Barchard674778d2020-08-08 10:17:25 -0700488 "src/f32-vbinary/gen/vdivc-relu-scalar-x1.c",
489 "src/f32-vbinary/gen/vdivc-relu-scalar-x2.c",
490 "src/f32-vbinary/gen/vdivc-relu-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700491 "src/f32-vbinary/gen/vdivc-relu-scalar-x8.c",
Frank Barchard8e229db2020-07-06 23:31:35 -0700492 "src/f32-vbinary/gen/vdivc-scalar-x1.c",
493 "src/f32-vbinary/gen/vdivc-scalar-x2.c",
494 "src/f32-vbinary/gen/vdivc-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700495 "src/f32-vbinary/gen/vdivc-scalar-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -0800496 "src/f32-vbinary/gen/vmax-scalar-x1.c",
497 "src/f32-vbinary/gen/vmax-scalar-x2.c",
498 "src/f32-vbinary/gen/vmax-scalar-x4.c",
Frank Barchard9c7308f2020-08-31 17:03:01 -0700499 "src/f32-vbinary/gen/vmax-scalar-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -0800500 "src/f32-vbinary/gen/vmaxc-scalar-x1.c",
501 "src/f32-vbinary/gen/vmaxc-scalar-x2.c",
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Marat Dukhan91cd2b72020-04-09 23:57:31 -0700512 "src/f32-vbinary/gen/vmul-minmax-scalar-x1.c",
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Marat Dukhan91cd2b72020-04-09 23:57:31 -0700536 "src/f32-vbinary/gen/vrdivc-minmax-scalar-x1.c",
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Marat Dukhan91cd2b72020-04-09 23:57:31 -0700548 "src/f32-vbinary/gen/vrsubc-minmax-scalar-x1.c",
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Marat Dukhan13bafb02020-06-05 00:43:11 -0700560 "src/f32-vbinary/gen/vsqrdiff-scalar-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -0700563 "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
Marat Dukhan13bafb02020-06-05 00:43:11 -0700564 "src/f32-vbinary/gen/vsqrdiffc-scalar-x1.c",
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Marat Dukhan91cd2b72020-04-09 23:57:31 -0700568 "src/f32-vbinary/gen/vsub-minmax-scalar-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -0700572 "src/f32-vbinary/gen/vsub-relu-scalar-x1.c",
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Marat Dukhan91cd2b72020-04-09 23:57:31 -0700580 "src/f32-vbinary/gen/vsubc-minmax-scalar-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -0700584 "src/f32-vbinary/gen/vsubc-relu-scalar-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -0700591 "src/f32-vbinary/gen/vsubc-scalar-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -0700592 "src/f32-vclamp/gen/vclamp-scalar-x1.c",
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594 "src/f32-vclamp/gen/vclamp-scalar-x4.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -0800595 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x1.c",
596 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
597 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x3.c",
598 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
599 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x5.c",
600 "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x6.c",
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605 "src/f32-velu/gen/velu-scalar-rr2-p6-x5.c",
606 "src/f32-velu/gen/velu-scalar-rr2-p6-x6.c",
Marat Dukhan6674d692021-05-05 22:27:00 -0700607 "src/f32-vhswish/gen/vhswish-scalar-x1.c",
608 "src/f32-vhswish/gen/vhswish-scalar-x2.c",
609 "src/f32-vhswish/gen/vhswish-scalar-x4.c",
Frank Barchard04336c12020-10-22 16:48:55 -0700610 "src/f32-vlrelu/gen/vlrelu-scalar-x1.c",
611 "src/f32-vlrelu/gen/vlrelu-scalar-x2.c",
612 "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
Marat Dukhan99936602020-04-11 16:47:01 -0700613 "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
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615 "src/f32-vmulcaddc/gen/c4-minmax-scalar-2x.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -0700616 "src/f32-vrelu/gen/vrelu-scalar-x1.c",
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Marat Dukhaneecf8fd2020-06-09 08:59:37 -0700620 "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
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Frank Barchardc9c320e2020-08-07 22:12:46 -0700623 "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
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626 "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
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Marat Dukhanb1eec082021-05-05 23:24:55 -0700632 "src/f32-vsigmoid/gen/vsigmoid-scalar-lut64-p2-div-x1.c",
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634 "src/f32-vsigmoid/gen/vsigmoid-scalar-lut64-p2-div-x4.c",
635 "src/f32-vsigmoid/gen/vsigmoid-scalar-lut2048-p1-div-x1.c",
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Marat Dukhanf4db2f32020-06-30 10:55:30 -0700641 "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
642 "src/f32-vsqrt/gen/scalar-sqrt-x2.c",
643 "src/f32-vsqrt/gen/scalar-sqrt-x4.c",
Marat Dukhan5020b962020-06-08 13:30:10 -0700644 "src/f32-vunary/gen/vabs-scalar-x1.c",
645 "src/f32-vunary/gen/vabs-scalar-x2.c",
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647 "src/f32-vunary/gen/vneg-scalar-x1.c",
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650 "src/f32-vunary/gen/vsqr-scalar-x1.c",
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Marat Dukhande390d42020-11-29 19:32:18 -0800653 "src/math/expm1minus-scalar-rr2-lut4-p4.c",
654 "src/math/expm1minus-scalar-rr2-lut8-p3.c",
655 "src/math/expm1minus-scalar-rr2-lut8-p4.c",
Marat Dukhanc60742b2020-11-23 12:33:27 -0800656 "src/math/expm1minus-scalar-rr2-lut16-p3.c",
657 "src/math/expm1minus-scalar-rr2-lut16-p4.c",
658 "src/math/expm1minus-scalar-rr2-p5.c",
659 "src/math/expm1minus-scalar-rr2-p6.c",
Frank Barchard22136062020-11-24 18:44:46 -0800660 "src/math/expminus-scalar-rr2-lut64-p2.c",
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662 "src/math/expminus-scalar-rr2-p5.c",
Marat Dukhanc9852ba2020-05-13 17:21:29 -0700663 "src/math/roundd-scalar-addsub.c",
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667 "src/math/roundne-scalar-nearbyint.c",
668 "src/math/roundne-scalar-rint.c",
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Marat Dukhanc9852ba2020-05-13 17:21:29 -0700671 "src/math/roundu-scalar-cvt.c",
Marat Dukhan2dbb9442020-05-12 20:43:43 -0700672 "src/math/roundz-scalar-addsub.c",
673 "src/math/roundz-scalar-cvt.c",
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Marat Dukhanf8475d62020-09-17 15:01:43 -0700675 "src/math/sigmoid-scalar-rr2-lut64-p2-div.c",
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Marat Dukhanf8475d62020-09-17 15:01:43 -0700677 "src/math/sigmoid-scalar-rr2-p5-div.c",
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681 "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-lrint.c",
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683 "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-lrint.c",
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685 "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-lrint.c",
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687 "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-lrint.c",
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Marat Dukhand6021542021-06-30 09:04:20 -0700691 "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-lrint.c",
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715 "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-lrint.c",
716 "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-magic.c",
717 "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-lrint.c",
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720 "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-magic.c",
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722 "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-magic.c",
Marat Dukhan85d772b2021-06-30 11:02:42 -0700723 "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-lrint.c",
724 "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-magic.c",
725 "src/qs8-dwconv/gen/up1x9-minmax-gemmlowp-scalar.c",
Frank Barchardf10af6c2021-06-30 12:42:29 -0700726 "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-lrint.c",
727 "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-magic.c",
728 "src/qs8-dwconv/gen/up1x25-minmax-gemmlowp-scalar.c",
Marat Dukhan85d772b2021-06-30 11:02:42 -0700729 "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-lrint.c",
730 "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-magic.c",
731 "src/qs8-dwconv/gen/up2x9-minmax-gemmlowp-scalar.c",
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Marat Dukhan2c724952021-07-27 18:46:30 -0700921ALL_WASM_MICROKERNEL_SRCS = [
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Frank Barchard04336c12020-10-22 16:48:55 -07001006 "src/f32-vbinary/gen/vdivc-minmax-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001010 "src/f32-vbinary/gen/vdivc-relu-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001013 "src/f32-vbinary/gen/vdivc-relu-wasm-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08001014 "src/f32-vbinary/gen/vmax-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001017 "src/f32-vbinary/gen/vmax-wasm-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08001018 "src/f32-vbinary/gen/vmaxc-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001021 "src/f32-vbinary/gen/vmaxc-wasm-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08001022 "src/f32-vbinary/gen/vmin-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001025 "src/f32-vbinary/gen/vmin-wasm-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08001026 "src/f32-vbinary/gen/vminc-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001029 "src/f32-vbinary/gen/vminc-wasm-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07001030 "src/f32-vbinary/gen/vmul-minmax-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001034 "src/f32-vbinary/gen/vmul-relu-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001042 "src/f32-vbinary/gen/vmulc-relu-wasm-x1.c",
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Frank Barchard04336c12020-10-22 16:48:55 -07001046 "src/f32-vbinary/gen/vrdivc-minmax-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001050 "src/f32-vbinary/gen/vrdivc-relu-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001053 "src/f32-vbinary/gen/vrdivc-relu-wasm-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07001054 "src/f32-vbinary/gen/vrsubc-minmax-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001058 "src/f32-vbinary/gen/vrsubc-relu-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001061 "src/f32-vbinary/gen/vrsubc-relu-wasm-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07001062 "src/f32-vbinary/gen/vsub-minmax-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001069 "src/f32-vbinary/gen/vsub-relu-wasm-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07001070 "src/f32-vbinary/gen/vsubc-minmax-wasm-x1.c",
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Frank Barchard674778d2020-08-08 10:17:25 -07001074 "src/f32-vbinary/gen/vsubc-relu-wasm-x1.c",
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Frank Barchard9c7308f2020-08-31 17:03:01 -07001077 "src/f32-vbinary/gen/vsubc-relu-wasm-x8.c",
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1080 "src/f32-vclamp/gen/vclamp-wasm-x4.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08001081 "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x1.c",
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1088 "src/f32-velu/gen/velu-wasm-rr2-p6-x2.c",
1089 "src/f32-velu/gen/velu-wasm-rr2-p6-x3.c",
1090 "src/f32-velu/gen/velu-wasm-rr2-p6-x4.c",
1091 "src/f32-velu/gen/velu-wasm-rr2-p6-x5.c",
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Marat Dukhan6674d692021-05-05 22:27:00 -07001093 "src/f32-vhswish/gen/vhswish-wasm-x1.c",
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1095 "src/f32-vhswish/gen/vhswish-wasm-x4.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07001096 "src/f32-vlrelu/gen/vlrelu-wasm-x1.c",
1097 "src/f32-vlrelu/gen/vlrelu-wasm-x2.c",
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Frank Barchardd4416d62021-05-17 15:51:37 -07001099 "src/f32-vmulcaddc/gen/c1-minmax-wasm-2x.c",
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1101 "src/f32-vmulcaddc/gen/c4-minmax-wasm-2x.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07001102 "src/f32-vrelu/gen/vrelu-wasm-x1.c",
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1105 "src/f32-vrelu/gen/vrelu-wasm-x8.c",
Marat Dukhan436ebe62019-12-04 15:10:12 -08001106]
1107
Marat Dukhan2c724952021-07-27 18:46:30 -07001108ALL_WASMSIMD_MICROKERNEL_SRCS = [
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Marat Dukhan19dd91d2020-07-16 11:12:44 -07001692 "src/f32-vlrelu/gen/vlrelu-wasmsimd-bitselect-x4.c",
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Marat Dukhand816f622020-07-15 10:14:39 -07001696 "src/f32-vmulcaddc/gen/c4-minmax-wasmsimd-arm-2x.c",
Marat Dukhand816f622020-07-15 10:14:39 -07001697 "src/f32-vmulcaddc/gen/c4-minmax-wasmsimd-x86-2x.c",
Frank Barchard04336c12020-10-22 16:48:55 -07001698 "src/f32-vmulcaddc/gen/c8-minmax-wasmsimd-arm-2x.c",
Marat Dukhand816f622020-07-15 10:14:39 -07001699 "src/f32-vmulcaddc/gen/c8-minmax-wasmsimd-x86-2x.c",
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Marat Dukhanfeee77f2021-08-31 13:39:50 -07001703 "src/f32-vrnd/gen/vrndd-wasmsimd-addsub-x4.c",
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Marat Dukhanb1eec082021-05-05 23:24:55 -07001725 "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-lut64-p2-div-x4.c",
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1730 "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-lut64-p2-div-x24.c",
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Frank Barchard04336c12020-10-22 16:48:55 -07001749 "src/math/roundd-wasmsimd-addsub.c",
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Frank Barchard04336c12020-10-22 16:48:55 -07001757 "src/math/roundz-wasmsimd-addsub.c",
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Frank Barchard04336c12020-10-22 16:48:55 -07001760 "src/math/sigmoid-wasmsimd-rr2-lut64-p2-div.c",
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Frank Barcharda49e41f2021-08-31 20:30:24 -07001856 "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001857 "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1858 "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001859 "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
1860 "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001861 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001862 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-wasmsimd-mul16.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001863 "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1864 "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Frank Barcharda49e41f2021-08-31 20:30:24 -07001865 "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001866 "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1867 "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001868 "src/qs8-gemm/gen/4x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
1869 "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1870 "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1871 "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1872 "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001873 "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
1874 "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001875 "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1876 "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1877 "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1878 "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001879 "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
1880 "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001881 "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1882 "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1883 "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1884 "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001885 "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld64.c",
1886 "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul16-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001887 "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1888 "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1889 "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1890 "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhan2e23d2b2020-07-29 16:01:37 -07001891 "src/qs8-requantization/fp32-wasmsimd.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07001892 "src/qs8-requantization/gemmlowp-wasmsimd.c",
Marat Dukhan5df27f82020-09-02 23:59:21 -07001893 "src/qs8-vadd/gen/minmax-wasmsimd-x8.c",
1894 "src/qs8-vadd/gen/minmax-wasmsimd-x16.c",
1895 "src/qs8-vadd/gen/minmax-wasmsimd-x24.c",
1896 "src/qs8-vadd/gen/minmax-wasmsimd-x32.c",
1897 "src/qs8-vaddc/gen/minmax-wasmsimd-x8.c",
1898 "src/qs8-vaddc/gen/minmax-wasmsimd-x16.c",
1899 "src/qs8-vaddc/gen/minmax-wasmsimd-x24.c",
1900 "src/qs8-vaddc/gen/minmax-wasmsimd-x32.c",
Marat Dukhan661ea6d2021-08-02 11:25:41 -07001901 "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
1902 "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
1903 "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
1904 "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
Marat Dukhanf6011352021-07-15 15:11:14 -07001905 "src/qu8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16.c",
1906 "src/qu8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16.c",
1907 "src/qu8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16.c",
1908 "src/qu8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16.c",
1909 "src/qu8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16.c",
1910 "src/qu8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001911 "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1912 "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1913 "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1914 "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001915 "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1916 "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001917 "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1918 "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1919 "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1920 "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001921 "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1922 "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001923 "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1924 "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1925 "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1926 "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001927 "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1928 "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001929 "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1930 "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1931 "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1932 "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1933 "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1934 "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1935 "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1936 "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001937 "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1938 "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001939 "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1940 "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1941 "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1942 "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001943 "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1944 "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001945 "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1946 "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1947 "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1948 "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhandfc2db02021-08-08 21:19:07 -07001949 "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld64.c",
1950 "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-mul32-ld128.c",
Marat Dukhan8dc106e2021-08-31 15:23:02 -07001951 "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1952 "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
1953 "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
1954 "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07001955 "src/qu8-requantization/fp32-wasmsimd.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07001956 "src/qu8-requantization/gemmlowp-wasmsimd.c",
Marat Dukhan76e78c82021-07-20 21:11:23 -07001957 "src/qu8-vadd/gen/minmax-wasmsimd-x8.c",
1958 "src/qu8-vadd/gen/minmax-wasmsimd-x16.c",
1959 "src/qu8-vaddc/gen/minmax-wasmsimd-x8.c",
1960 "src/qu8-vaddc/gen/minmax-wasmsimd-x16.c",
Marat Dukhan661ea6d2021-08-02 11:25:41 -07001961 "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
1962 "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
1963 "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
1964 "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07001965 "src/s8-maxpool/9p8x-minmax-wasmsimd-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07001966 "src/s8-vclamp/wasmsimd-x64.c",
Marat Dukhanf1589422021-08-15 20:37:06 -07001967 "src/u8-maxpool/9p8x-minmax-wasmsimd-c16.c",
Marat Dukhan1f5b1082021-08-16 17:01:44 -07001968 "src/u8-vclamp/wasmsimd-x64.c",
Marat Dukhan66d99e92020-07-16 12:56:21 -07001969 "src/x32-packx/x4-wasmsimd.c",
Marat Dukhan9d4bfa22020-07-16 19:07:04 -07001970 "src/x32-unpool/wasmsimd.c",
Marat Dukhane3b78762020-07-16 20:02:58 -07001971 "src/x32-zip/x2-wasmsimd.c",
1972 "src/x32-zip/x3-wasmsimd.c",
1973 "src/x32-zip/x4-wasmsimd.c",
1974 "src/x32-zip/xm-wasmsimd.c",
Marat Dukhan933051b2021-08-07 16:26:15 -07001975 "src/xx-fill/wasmsimd-x64.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -07001976 "src/xx-pad/wasmsimd.c",
Marat Dukhan290055c2020-06-09 12:24:29 -07001977]
1978
Marat Dukhan08c4a432019-10-03 09:29:21 -07001979# ISA-specific micro-kernels
Marat Dukhan2c724952021-07-27 18:46:30 -07001980PROD_NEON_MICROKERNEL_SRCS = [
1981 "src/f32-argmaxpool/4x-neon-c4.c",
1982 "src/f32-argmaxpool/9p8x-neon-c4.c",
1983 "src/f32-argmaxpool/9x-neon-c4.c",
1984 "src/f32-avgpool/9p8x-minmax-neon-c4.c",
1985 "src/f32-avgpool/9x-minmax-neon-c4.c",
1986 "src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
1987 "src/f32-dwconv/gen/up4x4-minmax-neon.c",
1988 "src/f32-dwconv/gen/up4x9-minmax-neon.c",
1989 "src/f32-dwconv/gen/up4x25-minmax-neon-acc2.c",
1990 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c",
1991 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4.c",
1992 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4.c",
1993 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4.c",
1994 "src/f32-gavgpool-cw/neon-x4.c",
1995 "src/f32-gavgpool/7p7x-minmax-neon-c4.c",
1996 "src/f32-gavgpool/7x-minmax-neon-c4.c",
1997 "src/f32-gemm/gen/1x8-minmax-neon-lane-ld64.c",
1998 "src/f32-gemm/gen/4x2-minmax-neon-lane-ld64.c",
1999 "src/f32-gemm/gen/4x8-minmax-neon-lane-ld64.c",
2000 "src/f32-ibilinear-chw/gen/neon-p8.c",
2001 "src/f32-ibilinear/gen/neon-c8.c",
2002 "src/f32-igemm/gen/1x8-minmax-neon-lane-ld64.c",
2003 "src/f32-igemm/gen/4x2-minmax-neon-lane-ld64.c",
2004 "src/f32-igemm/gen/4x8-minmax-neon-lane-ld64.c",
2005 "src/f32-maxpool/9p8x-minmax-neon-c4.c",
2006 "src/f32-pavgpool/9p8x-minmax-neon-c4.c",
2007 "src/f32-pavgpool/9x-minmax-neon-c4.c",
2008 "src/f32-prelu/gen/neon-2x8.c",
2009 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x8.c",
2010 "src/f32-rmax/neon.c",
2011 "src/f32-spmm/gen/32x1-minmax-neon.c",
2012 "src/f32-vbinary/gen/vadd-minmax-neon-x8.c",
2013 "src/f32-vbinary/gen/vaddc-minmax-neon-x8.c",
2014 "src/f32-vbinary/gen/vmax-neon-x8.c",
2015 "src/f32-vbinary/gen/vmaxc-neon-x8.c",
2016 "src/f32-vbinary/gen/vmin-neon-x8.c",
2017 "src/f32-vbinary/gen/vminc-neon-x8.c",
2018 "src/f32-vbinary/gen/vmul-minmax-neon-x8.c",
2019 "src/f32-vbinary/gen/vmulc-minmax-neon-x8.c",
2020 "src/f32-vbinary/gen/vrsubc-minmax-neon-x8.c",
2021 "src/f32-vbinary/gen/vsqrdiff-neon-x8.c",
2022 "src/f32-vbinary/gen/vsqrdiffc-neon-x8.c",
2023 "src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
2024 "src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
2025 "src/f32-vclamp/gen/vclamp-neon-x8.c",
2026 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
2027 "src/f32-vhswish/gen/vhswish-neon-x16.c",
2028 "src/f32-vlrelu/gen/vlrelu-neon-x8.c",
2029 "src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
2030 "src/f32-vrnd/gen/vrndd-neon-x8.c",
2031 "src/f32-vrnd/gen/vrndne-neon-x8.c",
2032 "src/f32-vrnd/gen/vrndu-neon-x8.c",
2033 "src/f32-vrnd/gen/vrndz-neon-x8.c",
2034 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
2035 "src/f32-vunary/gen/vabs-neon-x8.c",
2036 "src/f32-vunary/gen/vneg-neon-x8.c",
2037 "src/f32-vunary/gen/vsqr-neon-x8.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002038 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
Frank Barchard7da8b022021-08-31 09:49:10 -07002039 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
2040 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002041 "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-padal-dup.c",
2042 "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-padal-dup.c",
2043 "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-padal-dup.c",
2044 "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002045 "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mla8-ld64.c",
Frank Barchard7da8b022021-08-31 09:49:10 -07002046 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld64.c",
2047 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld64.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002048 "src/qs8-gavgpool/gen/7p7x-minmax-neon-c8-acc2.c",
2049 "src/qs8-gavgpool/gen/7x-minmax-neon-c8-acc2.c",
2050 "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mlal-padal-dup.c",
2051 "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2052 "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mlal-padal-dup.c",
2053 "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mlal-padal-dup.c",
2054 "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2055 "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mlal-padal-dup.c",
Marat Dukhan01debd92021-07-29 18:14:21 -07002056 "src/qs8-vadd/gen/minmax-neon-ld64-x16.c",
2057 "src/qs8-vadd/gen/minmax-neon-ld64-x32.c",
2058 "src/qs8-vaddc/gen/minmax-neon-ld64-x16.c",
2059 "src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07002060 "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
2061 "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002062 "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
2063 "src/qu8-avgpool/9x-minmax-neon-c8.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002064 "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
Frank Barchard7da8b022021-08-31 09:49:10 -07002065 "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
2066 "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002067 "src/qu8-gavgpool/7p7x-minmax-neon-c8.c",
2068 "src/qu8-gavgpool/7x-minmax-neon-c8.c",
2069 "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
2070 "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2071 "src/qu8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
2072 "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
2073 "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
2074 "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2075 "src/qu8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
2076 "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
Frank Barchard0a3093c2021-08-31 09:58:11 -07002077 "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
2078 "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
2079 "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
2080 "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07002081 "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
2082 "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07002083 "src/s8-maxpool/9p8x-minmax-neon-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07002084 "src/s8-vclamp/neon-x64.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002085 "src/u8-maxpool/9p8x-minmax-neon-c16.c",
2086 "src/u8-rmax/neon.c",
2087 "src/u8-vclamp/neon-x64.c",
2088 "src/x8-zip/x2-neon.c",
2089 "src/x8-zip/x3-neon.c",
2090 "src/x8-zip/x4-neon.c",
2091 "src/x8-zip/xm-neon.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002092 "src/x32-packx/x4-neon-st4.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002093 "src/x32-unpool/neon.c",
2094 "src/x32-zip/x2-neon.c",
2095 "src/x32-zip/x3-neon.c",
2096 "src/x32-zip/x4-neon.c",
2097 "src/x32-zip/xm-neon.c",
Marat Dukhan933051b2021-08-07 16:26:15 -07002098 "src/xx-fill/neon-x64.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -07002099 "src/xx-pad/neon.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07002100]
2101
2102ALL_NEON_MICROKERNEL_SRCS = [
Marat Dukhanef25c6d2020-07-24 00:59:40 -07002103 "src/f32-argmaxpool/4x-neon-c4.c",
2104 "src/f32-argmaxpool/9p8x-neon-c4.c",
2105 "src/f32-argmaxpool/9x-neon-c4.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002106 "src/f32-avgpool/9p8x-minmax-neon-c4.c",
2107 "src/f32-avgpool/9x-minmax-neon-c4.c",
Marat Dukhan56b10cd2020-05-18 09:35:49 -07002108 "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002109 "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002110 "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neon-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002111 "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neon-2x2.c",
Marat Dukhan56b10cd2020-05-18 09:35:49 -07002112 "src/f32-conv-hwc/gen/3x3s2p1c3x4-neon-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002113 "src/f32-conv-hwc/gen/3x3s2p1c3x4-neon-2x2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002114 "src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002115 "src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x2.c",
Marat Dukhanc7634882020-12-07 15:11:12 -08002116 "src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
Marat Dukhanf5425ea2020-04-24 01:46:00 -07002117 "src/f32-dwconv/gen/up4x4-minmax-neon-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002118 "src/f32-dwconv/gen/up4x4-minmax-neon.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002119 "src/f32-dwconv/gen/up4x9-minmax-neon-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002120 "src/f32-dwconv/gen/up4x9-minmax-neon.c",
Marat Dukhanf5425ea2020-04-24 01:46:00 -07002121 "src/f32-dwconv/gen/up4x25-minmax-neon-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002122 "src/f32-dwconv/gen/up4x25-minmax-neon.c",
2123 "src/f32-dwconv/gen/up8x4-minmax-neon-acc2.c",
2124 "src/f32-dwconv/gen/up8x4-minmax-neon.c",
2125 "src/f32-dwconv/gen/up8x9-minmax-neon-acc2.c",
2126 "src/f32-dwconv/gen/up8x9-minmax-neon.c",
Marat Dukhanf5425ea2020-04-24 01:46:00 -07002127 "src/f32-dwconv/gen/up8x25-minmax-neon-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002128 "src/f32-dwconv/gen/up8x25-minmax-neon.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002129 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc2.c",
2130 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc3.c",
2131 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc4.c",
Marat Dukhanc581e482020-10-24 01:28:11 -07002132 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002133 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4-acc2.c",
Marat Dukhanc581e482020-10-24 01:28:11 -07002134 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c",
2135 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-3x4.c",
2136 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-4x4.c",
2137 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-5x4.c",
2138 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-6x4.c",
Marat Dukhan82f0c322020-10-25 19:17:35 -07002139 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc2.c",
2140 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc3.c",
2141 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002142 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4.c",
Marat Dukhan82f0c322020-10-25 19:17:35 -07002143 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-2x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002144 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-2x4.c",
2145 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-3x4.c",
2146 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-4x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002147 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc2.c",
2148 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc3.c",
2149 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc4.c",
2150 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc5.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002151 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002152 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4-acc2.c",
2153 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4-acc3.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002154 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002155 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-3x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002156 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-3x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002157 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-4x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002158 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-4x4.c",
2159 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-5x4.c",
Marat Dukhan30d4b252020-10-29 16:33:22 -07002160 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc2.c",
2161 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc3.c",
2162 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc4.c",
2163 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc5.c",
2164 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4.c",
2165 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4-acc2.c",
2166 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4-acc3.c",
2167 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4.c",
Marat Dukhan30d4b252020-10-29 16:33:22 -07002168 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4-acc2.c",
Frank Barchardbeca6522020-10-30 22:34:35 -07002169 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4.c",
Marat Dukhan1f29b802020-05-15 23:46:39 -07002170 "src/f32-gavgpool-cw/neon-x4.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002171 "src/f32-gavgpool/7p7x-minmax-neon-c4.c",
2172 "src/f32-gavgpool/7x-minmax-neon-c4.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002173 "src/f32-gemm/gen-inc/1x8inc-minmax-neon-dup-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002174 "src/f32-gemm/gen-inc/1x8inc-minmax-neon-lane-ld64.c",
2175 "src/f32-gemm/gen-inc/1x8s4inc-minmax-neon.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002176 "src/f32-gemm/gen-inc/4x8inc-minmax-neon-dup-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002177 "src/f32-gemm/gen-inc/4x8inc-minmax-neon-dup-ld128.c",
2178 "src/f32-gemm/gen-inc/4x8inc-minmax-neon-lane-ld64.c",
2179 "src/f32-gemm/gen-inc/4x8inc-minmax-neon-lane-ld128.c",
2180 "src/f32-gemm/gen-inc/4x8s4inc-minmax-neon.c",
2181 "src/f32-gemm/gen-inc/5x8inc-minmax-neon-lane-ld64.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002182 "src/f32-gemm/gen-inc/6x8inc-minmax-neon-dup-ld64.c",
2183 "src/f32-gemm/gen-inc/6x8inc-minmax-neon-dup-ld128.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002184 "src/f32-gemm/gen-inc/6x8inc-minmax-neon-lane-ld64.c",
2185 "src/f32-gemm/gen-inc/6x8inc-minmax-neon-lane-ld128.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002186 "src/f32-gemm/gen-inc/6x8s4inc-minmax-neon.c",
2187 "src/f32-gemm/gen-inc/8x8s4inc-minmax-neon.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002188 "src/f32-gemm/gen/1x8-minmax-neon-dup-ld64.c",
2189 "src/f32-gemm/gen/1x8-minmax-neon-lane-ld64.c",
2190 "src/f32-gemm/gen/1x8s4-minmax-neon.c",
2191 "src/f32-gemm/gen/4x2-minmax-neon-lane-ld64.c",
2192 "src/f32-gemm/gen/4x8-minmax-neon-dup-ld64.c",
2193 "src/f32-gemm/gen/4x8-minmax-neon-dup-ld128.c",
2194 "src/f32-gemm/gen/4x8-minmax-neon-lane-ld64.c",
2195 "src/f32-gemm/gen/4x8-minmax-neon-lane-ld128.c",
2196 "src/f32-gemm/gen/4x8s4-minmax-neon.c",
2197 "src/f32-gemm/gen/5x8-minmax-neon-lane-ld64.c",
2198 "src/f32-gemm/gen/6x8-minmax-neon-dup-ld64.c",
2199 "src/f32-gemm/gen/6x8-minmax-neon-dup-ld128.c",
2200 "src/f32-gemm/gen/6x8-minmax-neon-lane-ld64.c",
2201 "src/f32-gemm/gen/6x8-minmax-neon-lane-ld128.c",
2202 "src/f32-gemm/gen/6x8s4-minmax-neon.c",
2203 "src/f32-gemm/gen/8x8s4-minmax-neon.c",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -08002204 "src/f32-ibilinear-chw/gen/neon-p4.c",
2205 "src/f32-ibilinear-chw/gen/neon-p8.c",
Frank Barchard8247e212021-02-03 18:12:33 -08002206 "src/f32-ibilinear/gen/neon-c4.c",
2207 "src/f32-ibilinear/gen/neon-c8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002208 "src/f32-igemm/gen/1x8-minmax-neon-dup-ld64.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002209 "src/f32-igemm/gen/1x8-minmax-neon-lane-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002210 "src/f32-igemm/gen/1x8s4-minmax-neon.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002211 "src/f32-igemm/gen/4x2-minmax-neon-lane-ld64.c",
2212 "src/f32-igemm/gen/4x4-minmax-neon-lane-ld64.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002213 "src/f32-igemm/gen/4x8-minmax-neon-dup-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002214 "src/f32-igemm/gen/4x8-minmax-neon-dup-ld128.c",
2215 "src/f32-igemm/gen/4x8-minmax-neon-lane-ld64.c",
2216 "src/f32-igemm/gen/4x8-minmax-neon-lane-ld128.c",
2217 "src/f32-igemm/gen/4x8s4-minmax-neon.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002218 "src/f32-igemm/gen/6x8-minmax-neon-dup-ld64.c",
2219 "src/f32-igemm/gen/6x8-minmax-neon-dup-ld128.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002220 "src/f32-igemm/gen/6x8-minmax-neon-lane-ld64.c",
2221 "src/f32-igemm/gen/6x8-minmax-neon-lane-ld128.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002222 "src/f32-igemm/gen/6x8s4-minmax-neon.c",
2223 "src/f32-igemm/gen/8x8s4-minmax-neon.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002224 "src/f32-maxpool/9p8x-minmax-neon-c4.c",
2225 "src/f32-pavgpool/9p8x-minmax-neon-c4.c",
2226 "src/f32-pavgpool/9x-minmax-neon-c4.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002227 "src/f32-ppmm/gen/4x8-minmax-neon.c",
2228 "src/f32-ppmm/gen/8x8-minmax-neon.c",
Frank Barcharda5316982020-07-23 13:19:28 -07002229 "src/f32-prelu/gen/neon-1x4.c",
2230 "src/f32-prelu/gen/neon-1x8.c",
2231 "src/f32-prelu/gen/neon-1x16.c",
Marat Dukhan40a672f2019-11-25 03:08:22 -08002232 "src/f32-prelu/gen/neon-2x4.c",
2233 "src/f32-prelu/gen/neon-2x8.c",
Frank Barcharda5316982020-07-23 13:19:28 -07002234 "src/f32-prelu/gen/neon-2x16.c",
2235 "src/f32-prelu/gen/neon-4x4.c",
2236 "src/f32-prelu/gen/neon-4x8.c",
2237 "src/f32-prelu/gen/neon-4x16.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002238 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x4.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002239 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x8-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002240 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x8.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002241 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12-acc2.c",
2242 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002243 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x12.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002244 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16-acc2.c",
2245 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002246 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x16.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002247 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20-acc2.c",
2248 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002249 "src/f32-raddstoreexpminusmax/gen/neon-lut64-p2-x20.c",
2250 "src/f32-raddstoreexpminusmax/gen/neon-p5-x4.c",
2251 "src/f32-raddstoreexpminusmax/gen/neon-p5-x8-acc2.c",
2252 "src/f32-raddstoreexpminusmax/gen/neon-p5-x8.c",
2253 "src/f32-raddstoreexpminusmax/gen/neon-p5-x12-acc2.c",
2254 "src/f32-raddstoreexpminusmax/gen/neon-p5-x12-acc3.c",
2255 "src/f32-raddstoreexpminusmax/gen/neon-p5-x12.c",
2256 "src/f32-raddstoreexpminusmax/gen/neon-p5-x16-acc2.c",
2257 "src/f32-raddstoreexpminusmax/gen/neon-p5-x16-acc4.c",
2258 "src/f32-raddstoreexpminusmax/gen/neon-p5-x16.c",
2259 "src/f32-raddstoreexpminusmax/gen/neon-p5-x20-acc2.c",
2260 "src/f32-raddstoreexpminusmax/gen/neon-p5-x20-acc5.c",
2261 "src/f32-raddstoreexpminusmax/gen/neon-p5-x20.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002262 "src/f32-rmax/neon.c",
Marat Dukhan5b86c432020-12-06 19:15:03 -08002263 "src/f32-spmm/gen/4x1-minmax-neon-pipelined.c",
2264 "src/f32-spmm/gen/4x1-minmax-neon-x2.c",
2265 "src/f32-spmm/gen/4x1-minmax-neon.c",
2266 "src/f32-spmm/gen/8x1-minmax-neon-pipelined.c",
2267 "src/f32-spmm/gen/8x1-minmax-neon-x2.c",
2268 "src/f32-spmm/gen/8x1-minmax-neon.c",
2269 "src/f32-spmm/gen/12x1-minmax-neon.c",
2270 "src/f32-spmm/gen/16x1-minmax-neon-pipelined.c",
2271 "src/f32-spmm/gen/16x1-minmax-neon-x2.c",
2272 "src/f32-spmm/gen/16x1-minmax-neon.c",
2273 "src/f32-spmm/gen/32x1-minmax-neon-pipelined.c",
2274 "src/f32-spmm/gen/32x1-minmax-neon-x2.c",
2275 "src/f32-spmm/gen/32x1-minmax-neon.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07002276 "src/f32-vbinary/gen/vadd-minmax-neon-x4.c",
2277 "src/f32-vbinary/gen/vadd-minmax-neon-x8.c",
2278 "src/f32-vbinary/gen/vaddc-minmax-neon-x4.c",
2279 "src/f32-vbinary/gen/vaddc-minmax-neon-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08002280 "src/f32-vbinary/gen/vmax-neon-x4.c",
2281 "src/f32-vbinary/gen/vmax-neon-x8.c",
2282 "src/f32-vbinary/gen/vmaxc-neon-x4.c",
2283 "src/f32-vbinary/gen/vmaxc-neon-x8.c",
2284 "src/f32-vbinary/gen/vmin-neon-x4.c",
2285 "src/f32-vbinary/gen/vmin-neon-x8.c",
2286 "src/f32-vbinary/gen/vminc-neon-x4.c",
2287 "src/f32-vbinary/gen/vminc-neon-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07002288 "src/f32-vbinary/gen/vmul-minmax-neon-x4.c",
2289 "src/f32-vbinary/gen/vmul-minmax-neon-x8.c",
2290 "src/f32-vbinary/gen/vmulc-minmax-neon-x4.c",
2291 "src/f32-vbinary/gen/vmulc-minmax-neon-x8.c",
2292 "src/f32-vbinary/gen/vrsubc-minmax-neon-x4.c",
2293 "src/f32-vbinary/gen/vrsubc-minmax-neon-x8.c",
Marat Dukhan13bafb02020-06-05 00:43:11 -07002294 "src/f32-vbinary/gen/vsqrdiff-neon-x4.c",
2295 "src/f32-vbinary/gen/vsqrdiff-neon-x8.c",
2296 "src/f32-vbinary/gen/vsqrdiffc-neon-x4.c",
2297 "src/f32-vbinary/gen/vsqrdiffc-neon-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07002298 "src/f32-vbinary/gen/vsub-minmax-neon-x4.c",
2299 "src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
2300 "src/f32-vbinary/gen/vsubc-minmax-neon-x4.c",
2301 "src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07002302 "src/f32-vclamp/gen/vclamp-neon-x4.c",
2303 "src/f32-vclamp/gen/vclamp-neon-x8.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08002304 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x4.c",
2305 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
2306 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x12.c",
2307 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x16.c",
2308 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x20.c",
2309 "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x24.c",
2310 "src/f32-velu/gen/velu-neon-rr2-p6-x4.c",
2311 "src/f32-velu/gen/velu-neon-rr2-p6-x8.c",
2312 "src/f32-velu/gen/velu-neon-rr2-p6-x12.c",
2313 "src/f32-velu/gen/velu-neon-rr2-p6-x16.c",
2314 "src/f32-velu/gen/velu-neon-rr2-p6-x20.c",
2315 "src/f32-velu/gen/velu-neon-rr2-p6-x24.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07002316 "src/f32-vhswish/gen/vhswish-neon-x4.c",
2317 "src/f32-vhswish/gen/vhswish-neon-x8.c",
2318 "src/f32-vhswish/gen/vhswish-neon-x16.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07002319 "src/f32-vlrelu/gen/vlrelu-neon-x4.c",
2320 "src/f32-vlrelu/gen/vlrelu-neon-x8.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002321 "src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
2322 "src/f32-vmulcaddc/gen/c8-minmax-neon-2x.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07002323 "src/f32-vrelu/gen/vrelu-neon-x4.c",
2324 "src/f32-vrelu/gen/vrelu-neon-x8.c",
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07002325 "src/f32-vrnd/gen/vrndd-neon-x4.c",
2326 "src/f32-vrnd/gen/vrndd-neon-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002327 "src/f32-vrnd/gen/vrndne-neon-x4.c",
2328 "src/f32-vrnd/gen/vrndne-neon-x8.c",
2329 "src/f32-vrnd/gen/vrndu-neon-x4.c",
2330 "src/f32-vrnd/gen/vrndu-neon-x8.c",
2331 "src/f32-vrnd/gen/vrndz-neon-x4.c",
2332 "src/f32-vrnd/gen/vrndz-neon-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07002333 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x4.c",
2334 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
2335 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x12.c",
2336 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x16.c",
2337 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x20.c",
2338 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x24.c",
2339 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x4.c",
2340 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x8.c",
2341 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x12.c",
2342 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x16.c",
2343 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x20.c",
2344 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x24.c",
2345 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x4.c",
2346 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x8.c",
2347 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x12.c",
2348 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x16.c",
2349 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x20.c",
2350 "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x24.c",
Marat Dukhan5020b962020-06-08 13:30:10 -07002351 "src/f32-vunary/gen/vabs-neon-x4.c",
2352 "src/f32-vunary/gen/vabs-neon-x8.c",
2353 "src/f32-vunary/gen/vneg-neon-x4.c",
2354 "src/f32-vunary/gen/vneg-neon-x8.c",
2355 "src/f32-vunary/gen/vsqr-neon-x4.c",
2356 "src/f32-vunary/gen/vsqr-neon-x8.c",
Marat Dukhande390d42020-11-29 19:32:18 -08002357 "src/math/expm1minus-neon-rr2-lut16-p3.c",
2358 "src/math/expm1minus-neon-rr2-p6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002359 "src/math/roundd-neon-addsub.c",
2360 "src/math/roundd-neon-cvt.c",
2361 "src/math/roundne-neon-addsub.c",
2362 "src/math/roundu-neon-addsub.c",
2363 "src/math/roundu-neon-cvt.c",
2364 "src/math/roundz-neon-addsub.c",
2365 "src/math/roundz-neon-cvt.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002366 "src/math/sigmoid-neon-rr2-lut64-p2-nr2recps.c",
2367 "src/math/sigmoid-neon-rr2-lut2048-p1-nr2recps.c",
2368 "src/math/sigmoid-neon-rr2-p5-nr2recps.c",
2369 "src/math/sqrt-neon-nr1rsqrts.c",
2370 "src/math/sqrt-neon-nr2rsqrts.c",
2371 "src/math/sqrt-neon-nr3rsqrts.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002372 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mla8-ld64.c",
2373 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul8-ld64.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07002374 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002375 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
2376 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul8-ld64.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07002377 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002378 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
2379 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld128.c",
2380 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld64.c",
2381 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld128.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07002382 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002383 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
2384 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld128.c",
2385 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld64.c",
2386 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld128.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07002387 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
2388 "src/qc8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
2389 "src/qc8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
2390 "src/qc8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
2391 "src/qc8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07002392 "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07002393 "src/qc8-gemm/gen/1x8c8-minmax-fp32-neon-mlal-padal.c",
2394 "src/qc8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07002395 "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07002396 "src/qc8-gemm/gen/2x8c8-minmax-fp32-neon-mlal-padal.c",
2397 "src/qc8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07002398 "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07002399 "src/qc8-igemm/gen/1x8c8-minmax-fp32-neon-mlal-padal.c",
2400 "src/qc8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07002401 "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07002402 "src/qc8-igemm/gen/2x8c8-minmax-fp32-neon-mlal-padal.c",
2403 "src/qc8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002404 "src/qs8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002405 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002406 "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mla8-ld64.c",
2407 "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mul8-ld64.c",
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002408 "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002409 "src/qs8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002410 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002411 "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mla8-ld64.c",
2412 "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8-ld64.c",
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002413 "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002414 "src/qs8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002415 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002416 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld64.c",
2417 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld128.c",
2418 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8-ld64.c",
2419 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8-ld128.c",
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002420 "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002421 "src/qs8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002422 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07002423 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld64.c",
2424 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld128.c",
2425 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8-ld64.c",
2426 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8-ld128.c",
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07002427 "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002428 "src/qs8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002429 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002430 "src/qs8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002431 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002432 "src/qs8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002433 "src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan6f905292021-06-25 11:12:05 -07002434 "src/qs8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07002435 "src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-neon-mul16.c",
Marat Dukhan281262d2020-08-10 13:23:21 -07002436 "src/qs8-gavgpool/gen/7p7x-minmax-neon-c8-acc2.c",
2437 "src/qs8-gavgpool/gen/7p7x-minmax-neon-c16-acc2.c",
2438 "src/qs8-gavgpool/gen/7p7x-minmax-neon-c24-acc2.c",
2439 "src/qs8-gavgpool/gen/7p7x-minmax-neon-c32-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002440 "src/qs8-gavgpool/gen/7x-minmax-neon-c8-acc2.c",
2441 "src/qs8-gavgpool/gen/7x-minmax-neon-c16-acc2.c",
2442 "src/qs8-gavgpool/gen/7x-minmax-neon-c24-acc2.c",
2443 "src/qs8-gavgpool/gen/7x-minmax-neon-c32-acc2.c",
Marat Dukhand65d20e2021-05-24 16:59:51 -07002444 "src/qs8-gemm/gen/1x8-minmax-gemmlowp-neon-mlal-lane.c",
2445 "src/qs8-gemm/gen/1x8-minmax-gemmlowp-neon-mull-addw-dup.c",
Frank Barchard510b8e02021-07-26 17:25:18 -07002446 "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mull-addw-dup.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07002447 "src/qs8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-padal-dup.c",
Marat Dukhand65d20e2021-05-24 16:59:51 -07002448 "src/qs8-gemm/gen/1x8c2-minmax-gemmlowp-neon-mlal-padal-dup.c",
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Marat Dukhand65d20e2021-05-24 16:59:51 -07002461 "src/qs8-gemm/gen/1x16c2-minmax-gemmlowp-neon-mlal-padal-dup.c",
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Marat Dukhand65d20e2021-05-24 16:59:51 -07002479 "src/qs8-gemm/gen/2x16c2-minmax-gemmlowp-neon-mlal-padal-dup.c",
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Marat Dukhand65d20e2021-05-24 16:59:51 -07002493 "src/qs8-gemm/gen/3x16c2-minmax-gemmlowp-neon-mlal-padal-dup.c",
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Marat Dukhaneb3cff32021-07-30 11:35:27 -07002605 "src/qs8-vaddc/gen/minmax-neon-ld128-x16.c",
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Marat Dukhan4a7b70f2021-08-02 18:18:10 -07002607 "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
2608 "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
2609 "src/qs8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
2610 "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
2611 "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
2612 "src/qs8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
Marat Dukhan08b7a972020-07-14 18:17:29 -07002613 "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
2614 "src/qu8-avgpool/9x-minmax-neon-c8.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07002615 "src/qu8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
Marat Dukhan73a899a2021-07-27 00:10:38 -07002616 "src/qu8-dwconv/gen/up8x9-minmax-rndnu-neon-mul16.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07002617 "src/qu8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
Marat Dukhan73a899a2021-07-27 00:10:38 -07002618 "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07002619 "src/qu8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
Marat Dukhan73a899a2021-07-27 00:10:38 -07002620 "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07002621 "src/qu8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
Marat Dukhan73a899a2021-07-27 00:10:38 -07002622 "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07002623 "src/qu8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
2624 "src/qu8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
2625 "src/qu8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
2626 "src/qu8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
Marat Dukhan08b7a972020-07-14 18:17:29 -07002627 "src/qu8-gavgpool/7p7x-minmax-neon-c8.c",
2628 "src/qu8-gavgpool/7x-minmax-neon-c8.c",
Marat Dukhan173661d2021-07-26 23:47:08 -07002629 "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
Marat Dukhan69c8a292021-07-14 19:34:56 -07002630 "src/qu8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan173661d2021-07-26 23:47:08 -07002631 "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2632 "src/qu8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
Marat Dukhan69c8a292021-07-14 19:34:56 -07002633 "src/qu8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan173661d2021-07-26 23:47:08 -07002634 "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
2635 "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
Marat Dukhan69c8a292021-07-14 19:34:56 -07002636 "src/qu8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan173661d2021-07-26 23:47:08 -07002637 "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
2638 "src/qu8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
Marat Dukhan69c8a292021-07-14 19:34:56 -07002639 "src/qu8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
Marat Dukhan173661d2021-07-26 23:47:08 -07002640 "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07002641 "src/qu8-requantization/fp32-neon.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07002642 "src/qu8-requantization/gemmlowp-neon.c",
Marat Dukhan06716242021-05-26 15:56:39 -07002643 "src/qu8-requantization/rndna-neon.c",
Marat Dukhan76e78c82021-07-20 21:11:23 -07002644 "src/qu8-vadd/gen/minmax-neon-ld64-x8.c",
2645 "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
Frank Barchard0a3093c2021-08-31 09:58:11 -07002646 "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
Marat Dukhaneb3cff32021-07-30 11:35:27 -07002647 "src/qu8-vadd/gen/minmax-neon-ld128-x16.c",
Marat Dukhan76e78c82021-07-20 21:11:23 -07002648 "src/qu8-vaddc/gen/minmax-neon-ld64-x8.c",
2649 "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
Frank Barchard0a3093c2021-08-31 09:58:11 -07002650 "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
Marat Dukhaneb3cff32021-07-30 11:35:27 -07002651 "src/qu8-vaddc/gen/minmax-neon-ld128-x16.c",
Marat Dukhan4a7b70f2021-08-02 18:18:10 -07002652 "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
2653 "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
2654 "src/qu8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
2655 "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
2656 "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
2657 "src/qu8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07002658 "src/s8-maxpool/9p8x-minmax-neon-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07002659 "src/s8-vclamp/neon-x64.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002660 "src/u8-maxpool/9p8x-minmax-neon-c16.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002661 "src/u8-rmax/neon.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07002662 "src/u8-vclamp/neon-x64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002663 "src/x8-zip/x2-neon.c",
2664 "src/x8-zip/x3-neon.c",
2665 "src/x8-zip/x4-neon.c",
2666 "src/x8-zip/xm-neon.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002667 "src/x32-packx/x4-neon-st4.c",
Marat Dukhan57dccd82020-04-14 00:53:10 -07002668 "src/x32-unpool/neon.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002669 "src/x32-zip/x2-neon.c",
2670 "src/x32-zip/x3-neon.c",
2671 "src/x32-zip/x4-neon.c",
2672 "src/x32-zip/xm-neon.c",
Marat Dukhan933051b2021-08-07 16:26:15 -07002673 "src/xx-fill/neon-x64.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -07002674 "src/xx-pad/neon.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002675]
2676
Marat Dukhan2c724952021-07-27 18:46:30 -07002677PROD_NEONFMA_MICROKERNEL_SRCS = [
2678 "src/f32-dwconv/gen/up4x9-minmax-neonfma.c",
2679 "src/f32-dwconv/gen/up4x25-minmax-neonfma-acc2.c",
2680 "src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
2681 "src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
2682 "src/f32-gemm/gen/1x8s4-minmax-neonfma.c",
2683 "src/f32-gemm/gen/6x8s4-minmax-neonfma.c",
2684 "src/f32-ibilinear-chw/gen/neonfma-p8.c",
2685 "src/f32-ibilinear/gen/neonfma-c8.c",
2686 "src/f32-igemm/gen/1x8s4-minmax-neonfma.c",
2687 "src/f32-igemm/gen/6x8s4-minmax-neonfma.c",
2688 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16.c",
2689 "src/f32-spmm/gen/32x1-minmax-neonfma-pipelined.c",
2690 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x16.c",
2691 "src/f32-velu/gen/velu-neonfma-rr1-p6-x8.c",
2692 "src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
2693 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
2694]
2695
2696ALL_NEONFMA_MICROKERNEL_SRCS = [
Frank Barchard04336c12020-10-22 16:48:55 -07002697 "src/f32-dwconv/gen/up4x4-minmax-neonfma-acc2.c",
2698 "src/f32-dwconv/gen/up4x4-minmax-neonfma.c",
2699 "src/f32-dwconv/gen/up4x9-minmax-neonfma-acc2.c",
2700 "src/f32-dwconv/gen/up4x9-minmax-neonfma.c",
2701 "src/f32-dwconv/gen/up4x25-minmax-neonfma-acc2.c",
2702 "src/f32-dwconv/gen/up4x25-minmax-neonfma.c",
2703 "src/f32-dwconv/gen/up8x4-minmax-neonfma-acc2.c",
2704 "src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
2705 "src/f32-dwconv/gen/up8x9-minmax-neonfma-acc2.c",
2706 "src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
2707 "src/f32-dwconv/gen/up8x25-minmax-neonfma-acc2.c",
2708 "src/f32-dwconv/gen/up8x25-minmax-neonfma.c",
2709 "src/f32-gemm/gen-inc/1x8inc-minmax-neonfma-dup-ld64.c",
2710 "src/f32-gemm/gen-inc/1x8s4inc-minmax-neonfma.c",
2711 "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-dup-ld64.c",
2712 "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-dup-ld128.c",
2713 "src/f32-gemm/gen-inc/4x8s4inc-minmax-neonfma.c",
2714 "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-dup-ld64.c",
2715 "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-dup-ld128.c",
2716 "src/f32-gemm/gen-inc/6x8s4inc-minmax-neonfma.c",
2717 "src/f32-gemm/gen-inc/8x8s4inc-minmax-neonfma.c",
2718 "src/f32-gemm/gen/1x8-minmax-neonfma-dup-ld64.c",
2719 "src/f32-gemm/gen/1x8s4-minmax-neonfma.c",
2720 "src/f32-gemm/gen/4x8-minmax-neonfma-dup-ld64.c",
2721 "src/f32-gemm/gen/4x8-minmax-neonfma-dup-ld128.c",
2722 "src/f32-gemm/gen/4x8s4-minmax-neonfma.c",
2723 "src/f32-gemm/gen/6x8-minmax-neonfma-dup-ld64.c",
2724 "src/f32-gemm/gen/6x8-minmax-neonfma-dup-ld128.c",
2725 "src/f32-gemm/gen/6x8s4-minmax-neonfma.c",
2726 "src/f32-gemm/gen/8x8s4-minmax-neonfma.c",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -08002727 "src/f32-ibilinear-chw/gen/neonfma-p4.c",
2728 "src/f32-ibilinear-chw/gen/neonfma-p8.c",
Frank Barchard8247e212021-02-03 18:12:33 -08002729 "src/f32-ibilinear/gen/neonfma-c4.c",
2730 "src/f32-ibilinear/gen/neonfma-c8.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002731 "src/f32-igemm/gen/1x8-minmax-neonfma-dup-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002732 "src/f32-igemm/gen/1x8s4-minmax-neonfma.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002733 "src/f32-igemm/gen/4x8-minmax-neonfma-dup-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002734 "src/f32-igemm/gen/4x8-minmax-neonfma-dup-ld128.c",
2735 "src/f32-igemm/gen/4x8s4-minmax-neonfma.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002736 "src/f32-igemm/gen/6x8-minmax-neonfma-dup-ld64.c",
2737 "src/f32-igemm/gen/6x8-minmax-neonfma-dup-ld128.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002738 "src/f32-igemm/gen/6x8s4-minmax-neonfma.c",
2739 "src/f32-igemm/gen/8x8s4-minmax-neonfma.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07002740 "src/f32-ppmm/gen/4x8-minmax-neonfma.c",
2741 "src/f32-ppmm/gen/8x8-minmax-neonfma.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002742 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x4.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002743 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x8-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002744 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x8.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002745 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12-acc2.c",
2746 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002747 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x12.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002748 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16-acc2.c",
2749 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002750 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x16.c",
Marat Dukhan8137e4c2020-01-25 12:56:58 -08002751 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20-acc2.c",
2752 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002753 "src/f32-raddstoreexpminusmax/gen/neonfma-lut64-p2-x20.c",
2754 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x4.c",
2755 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x8-acc2.c",
2756 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x8.c",
2757 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12-acc2.c",
2758 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12-acc3.c",
2759 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x12.c",
2760 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16-acc2.c",
2761 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16-acc4.c",
2762 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x16.c",
2763 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20-acc2.c",
2764 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20-acc5.c",
2765 "src/f32-raddstoreexpminusmax/gen/neonfma-p5-x20.c",
Marat Dukhan2fa7a0c2020-12-06 19:09:02 -08002766 "src/f32-spmm/gen/4x1-minmax-neonfma-pipelined.c",
2767 "src/f32-spmm/gen/4x1-minmax-neonfma-x2.c",
2768 "src/f32-spmm/gen/4x1-minmax-neonfma.c",
2769 "src/f32-spmm/gen/8x1-minmax-neonfma-pipelined.c",
2770 "src/f32-spmm/gen/8x1-minmax-neonfma-x2.c",
2771 "src/f32-spmm/gen/8x1-minmax-neonfma.c",
2772 "src/f32-spmm/gen/12x1-minmax-neonfma.c",
2773 "src/f32-spmm/gen/16x1-minmax-neonfma-pipelined.c",
2774 "src/f32-spmm/gen/16x1-minmax-neonfma-x2.c",
2775 "src/f32-spmm/gen/16x1-minmax-neonfma.c",
2776 "src/f32-spmm/gen/32x1-minmax-neonfma-pipelined.c",
2777 "src/f32-spmm/gen/32x1-minmax-neonfma-x2.c",
2778 "src/f32-spmm/gen/32x1-minmax-neonfma.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08002779 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x4.c",
2780 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x8.c",
2781 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x12.c",
2782 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x16.c",
2783 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x20.c",
2784 "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x24.c",
2785 "src/f32-velu/gen/velu-neonfma-rr1-p6-x4.c",
2786 "src/f32-velu/gen/velu-neonfma-rr1-p6-x8.c",
2787 "src/f32-velu/gen/velu-neonfma-rr1-p6-x12.c",
2788 "src/f32-velu/gen/velu-neonfma-rr1-p6-x16.c",
2789 "src/f32-velu/gen/velu-neonfma-rr1-p6-x20.c",
2790 "src/f32-velu/gen/velu-neonfma-rr1-p6-x24.c",
Marat Dukhan99936602020-04-11 16:47:01 -07002791 "src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
2792 "src/f32-vmulcaddc/gen/c8-minmax-neonfma-2x.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07002793 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x4.c",
2794 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x8.c",
2795 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x12.c",
2796 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x16.c",
2797 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x20.c",
2798 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x24.c",
2799 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x4.c",
2800 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x8.c",
2801 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x12.c",
2802 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x16.c",
2803 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x20.c",
2804 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x24.c",
2805 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x4.c",
2806 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x8.c",
2807 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x12.c",
2808 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
2809 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x20.c",
2810 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x24.c",
2811 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x4.c",
2812 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x8.c",
2813 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x12.c",
2814 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x16.c",
2815 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x20.c",
2816 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x24.c",
2817 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x4.c",
2818 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x8.c",
2819 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x12.c",
2820 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x16.c",
2821 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x20.c",
2822 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x24.c",
2823 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x4.c",
2824 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x8.c",
2825 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x12.c",
2826 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x16.c",
2827 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x20.c",
2828 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x24.c",
2829 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x4.c",
2830 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x8.c",
2831 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x12.c",
2832 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x16.c",
2833 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x20.c",
2834 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x24.c",
2835 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x4.c",
2836 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x8.c",
2837 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x12.c",
2838 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x16.c",
2839 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x20.c",
2840 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x24.c",
2841 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x4.c",
2842 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x8.c",
2843 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x12.c",
2844 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x16.c",
2845 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x20.c",
2846 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x24.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07002847 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x4.c",
2848 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x8.c",
2849 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x12.c",
2850 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x16.c",
2851 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x20.c",
2852 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x24.c",
2853 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x28.c",
2854 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x32.c",
2855 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x36.c",
2856 "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x40.c",
2857 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x4.c",
2858 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x8.c",
2859 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x12.c",
2860 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x16.c",
2861 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x20.c",
2862 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x24.c",
2863 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x28.c",
2864 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x32.c",
2865 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x36.c",
2866 "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x40.c",
Marat Dukhanb7633f22020-11-20 16:34:56 -08002867 "src/math/exp-neonfma-rr2-lut64-p2.c",
2868 "src/math/exp-neonfma-rr2-p5.c",
Frank Barcharde7223ee2020-12-04 19:04:01 -08002869 "src/math/expm1minus-neonfma-rr1-lut16-p3.c",
2870 "src/math/expm1minus-neonfma-rr1-p6.c",
Marat Dukhan9dd119a2020-11-20 18:20:04 -08002871 "src/math/expminus-neonfma-rr2-lut64-p2.c",
2872 "src/math/expminus-neonfma-rr2-lut2048-p1.c",
2873 "src/math/expminus-neonfma-rr2-p5.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08002874 "src/math/sigmoid-neonfma-rr1-lut64-p2-nr1recps1fma.c",
2875 "src/math/sigmoid-neonfma-rr1-lut64-p2-nr2fma.c",
2876 "src/math/sigmoid-neonfma-rr1-lut64-p2-nr2recps.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002877 "src/math/sigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma.c",
2878 "src/math/sigmoid-neonfma-rr1-lut2048-p1-nr2fma.c",
2879 "src/math/sigmoid-neonfma-rr1-lut2048-p1-nr2recps.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08002880 "src/math/sigmoid-neonfma-rr1-p5-nr1recps1fma.c",
2881 "src/math/sigmoid-neonfma-rr1-p5-nr2fma.c",
2882 "src/math/sigmoid-neonfma-rr1-p5-nr2recps.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08002883 "src/math/sigmoid-neonfma-rr2-lut64-p2-nr1recps1fma.c",
2884 "src/math/sigmoid-neonfma-rr2-lut64-p2-nr2fma.c",
2885 "src/math/sigmoid-neonfma-rr2-lut64-p2-nr2recps.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002886 "src/math/sigmoid-neonfma-rr2-lut2048-p1-nr1recps1fma.c",
2887 "src/math/sigmoid-neonfma-rr2-lut2048-p1-nr2fma.c",
2888 "src/math/sigmoid-neonfma-rr2-lut2048-p1-nr2recps.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08002889 "src/math/sigmoid-neonfma-rr2-p5-nr1recps1fma.c",
2890 "src/math/sigmoid-neonfma-rr2-p5-nr2fma.c",
2891 "src/math/sigmoid-neonfma-rr2-p5-nr2recps.c",
Marat Dukhan84000762020-06-29 18:38:43 -07002892 "src/math/sqrt-neonfma-nr1fma.c",
Marat Dukhan84000762020-06-29 18:38:43 -07002893 "src/math/sqrt-neonfma-nr1rsqrts1fma1adj.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002894 "src/math/sqrt-neonfma-nr2fma.c",
2895 "src/math/sqrt-neonfma-nr2fma1adj.c",
2896 "src/math/sqrt-neonfma-nr3fma.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07002897]
2898
Marat Dukhan2c724952021-07-27 18:46:30 -07002899PROD_AARCH64_NEONFMA_MICROKERNEL_SRCS = [
2900 "src/f32-conv-hwc2chw/3x3s2p1c3x4-neonfma-2x2.c",
2901 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-3x4.c",
2902 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4-acc2.c",
2903 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4.c",
2904 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc2.c",
2905 "src/f32-gemm/gen/1x8-minmax-neonfma-lane-ld64.c",
2906 "src/f32-gemm/gen/4x2-minmax-neonfma-lane-ld64.c",
2907 "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld64.c",
2908 "src/f32-igemm/gen/1x8-minmax-neonfma-lane-ld64.c",
2909 "src/f32-igemm/gen/4x2-minmax-neonfma-lane-ld64.c",
2910 "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
2911 "src/f32-spmm/gen/32x2-minmax-neonfma.c",
2912 "src/f32-spmm/gen/32x4-minmax-neonfma.c",
2913 "src/f32-vbinary/gen/vdiv-minmax-neon-x8.c",
2914 "src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
2915 "src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
2916 "src/f32-vsqrt/gen/neon-sqrt-x4.c",
2917]
2918
2919ALL_AARCH64_NEONFMA_MICROKERNEL_SRCS = [
Marat Dukhan56b10cd2020-05-18 09:35:49 -07002920 "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002921 "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002922 "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neonfma-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002923 "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neonfma-2x2.c",
Marat Dukhan56b10cd2020-05-18 09:35:49 -07002924 "src/f32-conv-hwc/gen/3x3s2p1c3x4-neonfma-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002925 "src/f32-conv-hwc/gen/3x3s2p1c3x4-neonfma-2x2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002926 "src/f32-conv-hwc/gen/3x3s2p1c3x8-neonfma-2x1.c",
Marat Dukhance7a3f82020-05-17 21:46:44 -07002927 "src/f32-conv-hwc/gen/3x3s2p1c3x8-neonfma-2x2.c",
Marat Dukhan1f29b802020-05-15 23:46:39 -07002928 "src/f32-conv-hwc2chw/3x3s2p1c3x4-neonfma-2x2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002929 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc2.c",
2930 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc3.c",
2931 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc4.c",
Marat Dukhan1268a242020-10-24 00:36:32 -07002932 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002933 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-2x4-acc2.c",
Marat Dukhan1268a242020-10-24 00:36:32 -07002934 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-2x4.c",
2935 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-3x4.c",
2936 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-4x4.c",
2937 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-5x4.c",
2938 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-6x4.c",
Marat Dukhan82f0c322020-10-25 19:17:35 -07002939 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc2.c",
2940 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc3.c",
2941 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002942 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4.c",
Marat Dukhan82f0c322020-10-25 19:17:35 -07002943 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002944 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4.c",
2945 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-3x4.c",
2946 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-4x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002947 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc2.c",
2948 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc3.c",
2949 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc4.c",
2950 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc5.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002951 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002952 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4-acc2.c",
2953 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4-acc3.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002954 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002955 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-3x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002956 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-3x4.c",
Marat Dukhan149f0ea2020-10-26 12:50:33 -07002957 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07002958 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4.c",
2959 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-5x4.c",
Marat Dukhan30d4b252020-10-29 16:33:22 -07002960 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc2.c",
2961 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc3.c",
2962 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc4.c",
2963 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc5.c",
2964 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4.c",
2965 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4-acc2.c",
2966 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4-acc3.c",
2967 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4.c",
Marat Dukhan30d4b252020-10-29 16:33:22 -07002968 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-3x4-acc2.c",
Frank Barchardbeca6522020-10-30 22:34:35 -07002969 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-3x4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002970 "src/f32-gemm/gen-inc/1x8inc-minmax-neonfma-lane-ld64.c",
2971 "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-lane-ld64.c",
2972 "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-lane-ld128.c",
2973 "src/f32-gemm/gen-inc/5x8inc-minmax-neonfma-lane-ld64.c",
2974 "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-lane-ld64.c",
2975 "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-lane-ld128.c",
2976 "src/f32-gemm/gen/1x8-minmax-neonfma-lane-ld64.c",
2977 "src/f32-gemm/gen/4x2-minmax-neonfma-lane-ld64.c",
2978 "src/f32-gemm/gen/4x8-minmax-neonfma-lane-ld64.c",
2979 "src/f32-gemm/gen/4x8-minmax-neonfma-lane-ld128.c",
2980 "src/f32-gemm/gen/5x8-minmax-neonfma-lane-ld64.c",
2981 "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld64.c",
2982 "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld128.c",
2983 "src/f32-igemm/gen/1x8-minmax-neonfma-lane-ld64.c",
2984 "src/f32-igemm/gen/4x2-minmax-neonfma-lane-ld64.c",
2985 "src/f32-igemm/gen/4x4-minmax-neonfma-lane-ld64.c",
2986 "src/f32-igemm/gen/4x8-minmax-neonfma-lane-ld64.c",
2987 "src/f32-igemm/gen/4x8-minmax-neonfma-lane-ld128.c",
2988 "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
2989 "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld128.c",
Marat Dukhan355ab432020-04-09 19:01:52 -07002990 "src/f32-spmm/gen/4x2-minmax-neonfma.c",
2991 "src/f32-spmm/gen/4x4-minmax-neonfma.c",
Marat Dukhan355ab432020-04-09 19:01:52 -07002992 "src/f32-spmm/gen/8x2-minmax-neonfma.c",
2993 "src/f32-spmm/gen/8x4-minmax-neonfma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002994 "src/f32-spmm/gen/12x2-minmax-neonfma.c",
2995 "src/f32-spmm/gen/12x4-minmax-neonfma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07002996 "src/f32-spmm/gen/16x2-minmax-neonfma.c",
2997 "src/f32-spmm/gen/16x4-minmax-neonfma.c",
Frank Barchard846c0c62020-10-26 15:01:39 -07002998 "src/f32-spmm/gen/32x2-minmax-neonfma.c",
2999 "src/f32-spmm/gen/32x4-minmax-neonfma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003000 "src/f32-vbinary/gen/vdiv-minmax-neon-x4.c",
3001 "src/f32-vbinary/gen/vdiv-minmax-neon-x8.c",
3002 "src/f32-vbinary/gen/vdivc-minmax-neon-x4.c",
3003 "src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
3004 "src/f32-vbinary/gen/vrdivc-minmax-neon-x4.c",
3005 "src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07003006 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x4.c",
3007 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x8.c",
3008 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x12.c",
3009 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x16.c",
3010 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x20.c",
3011 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x24.c",
3012 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x4.c",
3013 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x8.c",
3014 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x12.c",
3015 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x16.c",
3016 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x20.c",
3017 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x24.c",
3018 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x4.c",
3019 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x8.c",
3020 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x12.c",
3021 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x16.c",
3022 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x20.c",
3023 "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x24.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07003024 "src/f32-vsqrt/gen/neon-sqrt-x4.c",
3025 "src/f32-vsqrt/gen/neon-sqrt-x8.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08003026 "src/math/sigmoid-neonfma-rr1-lut64-p2-div.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003027 "src/math/sigmoid-neonfma-rr1-lut2048-p1-div.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08003028 "src/math/sigmoid-neonfma-rr1-p5-div.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08003029 "src/math/sigmoid-neonfma-rr2-lut64-p2-div.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003030 "src/math/sigmoid-neonfma-rr2-lut2048-p1-div.c",
Marat Dukhan77221d32020-01-06 10:04:39 -08003031 "src/math/sigmoid-neonfma-rr2-p5-div.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003032]
3033
Marat Dukhan2c724952021-07-27 18:46:30 -07003034PROD_NEONV8_MICROKERNEL_SRCS = [
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3036 "src/f32-vrnd/gen/vrndne-neonv8-x8.c",
3037 "src/f32-vrnd/gen/vrndu-neonv8-x8.c",
3038 "src/f32-vrnd/gen/vrndz-neonv8-x8.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003039 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
Frank Barchard7da8b022021-08-31 09:49:10 -07003040 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
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Marat Dukhan2c724952021-07-27 18:46:30 -07003042 "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
3043 "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3044 "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
3045 "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
3046 "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
3047 "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
3048 "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
3049 "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3050 "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
3051 "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
3052 "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
3053 "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07003054 "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
3055 "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
3056 "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
3057 "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003058]
3059
3060ALL_NEONV8_MICROKERNEL_SRCS = [
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07003061 "src/f32-vrnd/gen/vrndd-neonv8-x4.c",
3062 "src/f32-vrnd/gen/vrndd-neonv8-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003063 "src/f32-vrnd/gen/vrndne-neonv8-x4.c",
3064 "src/f32-vrnd/gen/vrndne-neonv8-x8.c",
3065 "src/f32-vrnd/gen/vrndu-neonv8-x4.c",
3066 "src/f32-vrnd/gen/vrndu-neonv8-x8.c",
3067 "src/f32-vrnd/gen/vrndz-neonv8-x4.c",
3068 "src/f32-vrnd/gen/vrndz-neonv8-x8.c",
Marat Dukhanc9852ba2020-05-13 17:21:29 -07003069 "src/math/roundd-neonv8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003070 "src/math/roundne-neonv8.c",
Marat Dukhanc9852ba2020-05-13 17:21:29 -07003071 "src/math/roundu-neonv8.c",
Marat Dukhan2dbb9442020-05-12 20:43:43 -07003072 "src/math/roundz-neonv8.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07003073 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mla8-ld64.c",
3074 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul8-ld64.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07003075 "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07003076 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
3077 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul8-ld64.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07003078 "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07003079 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
3080 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld128.c",
3081 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld64.c",
3082 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld128.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07003083 "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
Marat Dukhan5f2939f2021-07-23 13:38:32 -07003084 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld64.c",
3085 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld128.c",
3086 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld64.c",
3087 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld128.c",
Marat Dukhan59af5812021-06-29 18:09:57 -07003088 "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
3089 "src/qc8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
3090 "src/qc8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
3091 "src/qc8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
3092 "src/qc8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003093 "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07003094 "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3095 "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003096 "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07003097 "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
3098 "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003099 "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07003100 "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3101 "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003102 "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Marat Dukhane76478b2021-06-28 16:35:40 -07003103 "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
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Frank Barcharda03020a2021-06-28 15:44:06 -07003105 "src/qs8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
3106 "src/qs8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
3107 "src/qs8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
3108 "src/qs8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
3109 "src/qs8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
3110 "src/qs8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
3111 "src/qs8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
3112 "src/qs8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003113 "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07003114 "src/qs8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3115 "src/qs8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003116 "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07003117 "src/qs8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
3118 "src/qs8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003119 "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07003120 "src/qs8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal-padal.c",
3121 "src/qs8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan14f325e2021-06-30 18:46:25 -07003122 "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-padal-dup.c",
Frank Barcharda03020a2021-06-28 15:44:06 -07003123 "src/qs8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal-padal.c",
3124 "src/qs8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan4a7b70f2021-08-02 18:18:10 -07003125 "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
3126 "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
3127 "src/qs8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
3128 "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
3129 "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
3130 "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
Marat Dukhan605696a2021-07-15 18:01:30 -07003131 "src/qu8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
3132 "src/qu8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
3133 "src/qu8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
3134 "src/qu8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
3135 "src/qu8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
3136 "src/qu8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
3137 "src/qu8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
3138 "src/qu8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
Marat Dukhan69c8a292021-07-14 19:34:56 -07003139 "src/qu8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
3140 "src/qu8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
3141 "src/qu8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
3142 "src/qu8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
Marat Dukhan4a7b70f2021-08-02 18:18:10 -07003143 "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
3144 "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
3145 "src/qu8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
3146 "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
3147 "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
3148 "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
Marat Dukhan8853b822020-05-07 12:19:01 -07003149]
3150
Marat Dukhan2c724952021-07-27 18:46:30 -07003151PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
3152 "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith-acc2.c",
3153 "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith.c",
3154 "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
3155 "src/f16-gavgpool/7p7x-minmax-neonfp16arith-c8.c",
3156 "src/f16-gavgpool/7x-minmax-neonfp16arith-c8.c",
3157 "src/f16-gemm/gen/1x16-minmax-neonfp16arith-ld64.c",
3158 "src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
3159 "src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
3160 "src/f16-igemm/gen/6x16-minmax-neonfp16arith-ld64.c",
3161 "src/f16-vbinary/gen/vadd-minmax-neonfp16arith-x16.c",
3162 "src/f16-vbinary/gen/vaddc-minmax-neonfp16arith-x16.c",
3163 "src/f16-vbinary/gen/vmul-minmax-neonfp16arith-x16.c",
3164 "src/f16-vbinary/gen/vmulc-minmax-neonfp16arith-x16.c",
3165 "src/f16-vhswish/gen/vhswish-neonfp16arith-x16.c",
3166 "src/f16-vmulcaddc/gen/c8-minmax-neonfp16arith-2x.c",
3167]
3168
3169ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
Frank Barchard5a599a62020-06-04 20:12:44 -07003170 "src/f16-dwconv/gen/up8x4-minmax-neonfp16arith-acc2.c",
3171 "src/f16-dwconv/gen/up8x4-minmax-neonfp16arith.c",
3172 "src/f16-dwconv/gen/up8x9-minmax-neonfp16arith-acc2.c",
3173 "src/f16-dwconv/gen/up8x9-minmax-neonfp16arith.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003174 "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith-acc2.c",
3175 "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith.c",
3176 "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith-acc2.c",
3177 "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith.c",
3178 "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith-acc2.c",
3179 "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
3180 "src/f16-dwconv/gen/up16x25-minmax-neonfp16arith-acc2.c",
3181 "src/f16-dwconv/gen/up16x25-minmax-neonfp16arith.c",
Frank Barchard0bb49a72020-06-04 11:35:11 -07003182 "src/f16-gavgpool/7p7x-minmax-neonfp16arith-c8.c",
3183 "src/f16-gavgpool/7x-minmax-neonfp16arith-c8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003184 "src/f16-gemm/gen-inc/1x8inc-minmax-neonfp16arith-ld64.c",
3185 "src/f16-gemm/gen-inc/1x16inc-minmax-neonfp16arith-ld64.c",
3186 "src/f16-gemm/gen-inc/4x8inc-minmax-neonfp16arith-ld64.c",
3187 "src/f16-gemm/gen-inc/4x16inc-minmax-neonfp16arith-ld64.c",
3188 "src/f16-gemm/gen-inc/6x8inc-minmax-neonfp16arith-ld64.c",
3189 "src/f16-gemm/gen-inc/6x16inc-minmax-neonfp16arith-ld64.c",
3190 "src/f16-gemm/gen-inc/8x8inc-minmax-neonfp16arith-ld64.c",
3191 "src/f16-gemm/gen-inc/8x16inc-minmax-neonfp16arith-ld64.c",
3192 "src/f16-gemm/gen/1x8-minmax-neonfp16arith-ld64.c",
3193 "src/f16-gemm/gen/1x16-minmax-neonfp16arith-ld64.c",
3194 "src/f16-gemm/gen/4x8-minmax-neonfp16arith-ld64.c",
3195 "src/f16-gemm/gen/4x16-minmax-neonfp16arith-ld64.c",
3196 "src/f16-gemm/gen/6x8-minmax-neonfp16arith-ld64.c",
3197 "src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
3198 "src/f16-gemm/gen/8x8-minmax-neonfp16arith-ld64.c",
3199 "src/f16-gemm/gen/8x16-minmax-neonfp16arith-ld64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003200 "src/f16-igemm/gen/1x8-minmax-neonfp16arith-ld64.c",
3201 "src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
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Marat Dukhan08c4a432019-10-03 09:29:21 -07003254]
3255
Marat Dukhan2c724952021-07-27 18:46:30 -07003256PROD_NEONDOT_MICROKERNEL_SRCS = [
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3282
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Benoit Jacoba9644732020-08-13 12:48:55 -07003354]
3355
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3410ALL_SSE_MICROKERNEL_SRCS = [
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Frank Barchard04336c12020-10-22 16:48:55 -07003419 "src/f32-dwconv/gen/up4x25-minmax-sse-acc2.c",
3420 "src/f32-dwconv/gen/up4x25-minmax-sse.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003421 "src/f32-dwconv/gen/up8x4-minmax-sse-acc2.c",
3422 "src/f32-dwconv/gen/up8x4-minmax-sse.c",
3423 "src/f32-dwconv/gen/up8x9-minmax-sse-acc2.c",
3424 "src/f32-dwconv/gen/up8x9-minmax-sse.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003425 "src/f32-dwconv/gen/up8x25-minmax-sse-acc2.c",
3426 "src/f32-dwconv/gen/up8x25-minmax-sse.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07003427 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc2.c",
3428 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc3.c",
3429 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc4.c",
Marat Dukhan470078a2020-10-23 22:36:52 -07003430 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07003431 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4-acc2.c",
Marat Dukhan470078a2020-10-23 22:36:52 -07003432 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4.c",
3433 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-3x4.c",
3434 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-4x4.c",
3435 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-5x4.c",
3436 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-6x4.c",
Marat Dukhan0ff97182020-10-25 19:14:03 -07003437 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc2.c",
3438 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc3.c",
3439 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07003440 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4.c",
Marat Dukhan0ff97182020-10-25 19:14:03 -07003441 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-2x4-acc2.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07003442 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-2x4.c",
3443 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-3x4.c",
3444 "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-4x4.c",
Marat Dukhand0503892020-10-30 08:22:04 -07003445 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc2.c",
3446 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc3.c",
3447 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc4.c",
3448 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc5.c",
3449 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4.c",
3450 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4-acc2.c",
3451 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4-acc3.c",
3452 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4.c",
3453 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-3x4-acc2.c",
3454 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-3x4.c",
3455 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4-acc2.c",
3456 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4.c",
3457 "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-5x4.c",
Marat Dukhanccca2142020-10-30 17:32:45 -07003458 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc2.c",
3459 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc3.c",
3460 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc4.c",
3461 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc5.c",
3462 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4.c",
3463 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4-acc2.c",
3464 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4-acc3.c",
3465 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4.c",
Marat Dukhanccca2142020-10-30 17:32:45 -07003466 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-3x4-acc2.c",
Frank Barchard8ef44cd2020-11-03 12:30:23 -08003467 "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-3x4.c",
Marat Dukhan1f29b802020-05-15 23:46:39 -07003468 "src/f32-gavgpool-cw/sse-x4.c",
Marat Dukhan99936602020-04-11 16:47:01 -07003469 "src/f32-gavgpool/7p7x-minmax-sse-c4.c",
3470 "src/f32-gavgpool/7x-minmax-sse-c4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003471 "src/f32-gemm/gen-inc/1x8inc-minmax-sse-dup.c",
3472 "src/f32-gemm/gen-inc/1x8inc-minmax-sse-load1.c",
3473 "src/f32-gemm/gen-inc/1x8s4inc-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003474 "src/f32-gemm/gen-inc/3x8inc-minmax-sse-dup.c",
3475 "src/f32-gemm/gen-inc/3x8inc-minmax-sse-load1.c",
3476 "src/f32-gemm/gen-inc/3x8s4inc-minmax-sse.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003477 "src/f32-gemm/gen-inc/4x8inc-minmax-sse-dup.c",
3478 "src/f32-gemm/gen-inc/4x8inc-minmax-sse-load1.c",
3479 "src/f32-gemm/gen-inc/4x8s4inc-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003480 "src/f32-gemm/gen-inc/5x8inc-minmax-sse-dup.c",
3481 "src/f32-gemm/gen-inc/5x8inc-minmax-sse-load1.c",
3482 "src/f32-gemm/gen-inc/5x8s4inc-minmax-sse.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003483 "src/f32-gemm/gen/1x8-minmax-sse-dup.c",
3484 "src/f32-gemm/gen/1x8-minmax-sse-load1.c",
3485 "src/f32-gemm/gen/1x8s4-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003486 "src/f32-gemm/gen/3x8-minmax-sse-dup.c",
3487 "src/f32-gemm/gen/3x8-minmax-sse-load1.c",
3488 "src/f32-gemm/gen/3x8s4-minmax-sse.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003489 "src/f32-gemm/gen/4x2c4-minmax-sse.c",
3490 "src/f32-gemm/gen/4x8-minmax-sse-dup.c",
3491 "src/f32-gemm/gen/4x8-minmax-sse-load1.c",
3492 "src/f32-gemm/gen/4x8s4-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003493 "src/f32-gemm/gen/5x8-minmax-sse-dup.c",
3494 "src/f32-gemm/gen/5x8-minmax-sse-load1.c",
3495 "src/f32-gemm/gen/5x8s4-minmax-sse.c",
Artsiom Ablavatskib3ffd582021-03-31 13:00:08 -07003496 "src/f32-ibilinear-chw/gen/sse-p4.c",
3497 "src/f32-ibilinear-chw/gen/sse-p8.c",
Frank Barchard4a352042021-04-13 15:52:08 -07003498 "src/f32-ibilinear/gen/sse-c4.c",
3499 "src/f32-ibilinear/gen/sse-c8.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003500 "src/f32-igemm/gen/1x8-minmax-sse-dup.c",
3501 "src/f32-igemm/gen/1x8-minmax-sse-load1.c",
3502 "src/f32-igemm/gen/1x8s4-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003503 "src/f32-igemm/gen/3x8-minmax-sse-dup.c",
3504 "src/f32-igemm/gen/3x8-minmax-sse-load1.c",
3505 "src/f32-igemm/gen/3x8s4-minmax-sse.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003506 "src/f32-igemm/gen/4x2c4-minmax-sse.c",
3507 "src/f32-igemm/gen/4x8-minmax-sse-dup.c",
3508 "src/f32-igemm/gen/4x8-minmax-sse-load1.c",
3509 "src/f32-igemm/gen/4x8s4-minmax-sse.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003510 "src/f32-igemm/gen/5x8-minmax-sse-dup.c",
3511 "src/f32-igemm/gen/5x8-minmax-sse-load1.c",
3512 "src/f32-igemm/gen/5x8s4-minmax-sse.c",
Marat Dukhan99936602020-04-11 16:47:01 -07003513 "src/f32-maxpool/9p8x-minmax-sse-c4.c",
3514 "src/f32-pavgpool/9p8x-minmax-sse-c4.c",
3515 "src/f32-pavgpool/9x-minmax-sse-c4.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07003516 "src/f32-ppmm/gen/4x8-minmax-sse.c",
Marat Dukhan39b5e942020-06-24 15:03:48 -07003517 "src/f32-prelu/gen/sse-2x4.c",
3518 "src/f32-prelu/gen/sse-2x8.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003519 "src/f32-rmax/sse.c",
Marat Dukhan355ab432020-04-09 19:01:52 -07003520 "src/f32-spmm/gen/4x1-minmax-sse.c",
3521 "src/f32-spmm/gen/8x1-minmax-sse.c",
Erich Elsen6e80fdc2020-06-09 15:35:37 -07003522 "src/f32-spmm/gen/16x1-minmax-sse.c",
Frank Barchard846c0c62020-10-26 15:01:39 -07003523 "src/f32-spmm/gen/32x1-minmax-sse.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07003524 "src/f32-vbinary/gen/vadd-minmax-sse-x4.c",
3525 "src/f32-vbinary/gen/vadd-minmax-sse-x8.c",
3526 "src/f32-vbinary/gen/vaddc-minmax-sse-x4.c",
3527 "src/f32-vbinary/gen/vaddc-minmax-sse-x8.c",
3528 "src/f32-vbinary/gen/vdiv-minmax-sse-x4.c",
3529 "src/f32-vbinary/gen/vdiv-minmax-sse-x8.c",
3530 "src/f32-vbinary/gen/vdivc-minmax-sse-x4.c",
3531 "src/f32-vbinary/gen/vdivc-minmax-sse-x8.c",
Marat Dukhan403b7d42019-12-05 12:49:11 -08003532 "src/f32-vbinary/gen/vmax-sse-x4.c",
3533 "src/f32-vbinary/gen/vmax-sse-x8.c",
3534 "src/f32-vbinary/gen/vmaxc-sse-x4.c",
3535 "src/f32-vbinary/gen/vmaxc-sse-x8.c",
3536 "src/f32-vbinary/gen/vmin-sse-x4.c",
3537 "src/f32-vbinary/gen/vmin-sse-x8.c",
3538 "src/f32-vbinary/gen/vminc-sse-x4.c",
3539 "src/f32-vbinary/gen/vminc-sse-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07003540 "src/f32-vbinary/gen/vmul-minmax-sse-x4.c",
3541 "src/f32-vbinary/gen/vmul-minmax-sse-x8.c",
3542 "src/f32-vbinary/gen/vmulc-minmax-sse-x4.c",
3543 "src/f32-vbinary/gen/vmulc-minmax-sse-x8.c",
3544 "src/f32-vbinary/gen/vrdivc-minmax-sse-x4.c",
3545 "src/f32-vbinary/gen/vrdivc-minmax-sse-x8.c",
3546 "src/f32-vbinary/gen/vrsubc-minmax-sse-x4.c",
3547 "src/f32-vbinary/gen/vrsubc-minmax-sse-x8.c",
Marat Dukhan13bafb02020-06-05 00:43:11 -07003548 "src/f32-vbinary/gen/vsqrdiff-sse-x4.c",
3549 "src/f32-vbinary/gen/vsqrdiff-sse-x8.c",
3550 "src/f32-vbinary/gen/vsqrdiffc-sse-x4.c",
3551 "src/f32-vbinary/gen/vsqrdiffc-sse-x8.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07003552 "src/f32-vbinary/gen/vsub-minmax-sse-x4.c",
3553 "src/f32-vbinary/gen/vsub-minmax-sse-x8.c",
3554 "src/f32-vbinary/gen/vsubc-minmax-sse-x4.c",
3555 "src/f32-vbinary/gen/vsubc-minmax-sse-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07003556 "src/f32-vclamp/gen/vclamp-sse-x4.c",
3557 "src/f32-vclamp/gen/vclamp-sse-x8.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07003558 "src/f32-vhswish/gen/vhswish-sse-x4.c",
3559 "src/f32-vhswish/gen/vhswish-sse-x8.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07003560 "src/f32-vlrelu/gen/vlrelu-sse-x4.c",
3561 "src/f32-vlrelu/gen/vlrelu-sse-x8.c",
Marat Dukhan99936602020-04-11 16:47:01 -07003562 "src/f32-vmulcaddc/gen/c4-minmax-sse-2x.c",
3563 "src/f32-vmulcaddc/gen/c8-minmax-sse-2x.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07003564 "src/f32-vrelu/gen/vrelu-sse-x4.c",
3565 "src/f32-vrelu/gen/vrelu-sse-x8.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07003566 "src/f32-vsqrt/gen/sse-sqrt-x4.c",
3567 "src/f32-vsqrt/gen/sse-sqrt-x8.c",
Marat Dukhan5020b962020-06-08 13:30:10 -07003568 "src/f32-vunary/gen/vabs-sse-x4.c",
3569 "src/f32-vunary/gen/vabs-sse-x8.c",
3570 "src/f32-vunary/gen/vneg-sse-x4.c",
3571 "src/f32-vunary/gen/vneg-sse-x8.c",
3572 "src/f32-vunary/gen/vsqr-sse-x4.c",
3573 "src/f32-vunary/gen/vsqr-sse-x8.c",
Marat Dukhanc9852ba2020-05-13 17:21:29 -07003574 "src/math/roundd-sse-addsub.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003575 "src/math/roundne-sse-addsub.c",
Marat Dukhanc9852ba2020-05-13 17:21:29 -07003576 "src/math/roundu-sse-addsub.c",
Marat Dukhan2dbb9442020-05-12 20:43:43 -07003577 "src/math/roundz-sse-addsub.c",
Marat Dukhan84000762020-06-29 18:38:43 -07003578 "src/math/sqrt-sse-hh1mac.c",
3579 "src/math/sqrt-sse-nr1mac.c",
3580 "src/math/sqrt-sse-nr2mac.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003581 "src/x32-packx/x4-sse.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003582]
3583
Marat Dukhan2c724952021-07-27 18:46:30 -07003584PROD_SSE2_MICROKERNEL_SRCS = [
3585 "src/f32-argmaxpool/4x-sse2-c4.c",
3586 "src/f32-argmaxpool/9p8x-sse2-c4.c",
3587 "src/f32-argmaxpool/9x-sse2-c4.c",
3588 "src/f32-prelu/gen/sse2-2x8.c",
3589 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20-acc2.c",
3590 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
3591 "src/f32-vlrelu/gen/vlrelu-sse2-x8.c",
3592 "src/f32-vrnd/gen/vrndd-sse2-x8.c",
3593 "src/f32-vrnd/gen/vrndne-sse2-x8.c",
3594 "src/f32-vrnd/gen/vrndu-sse2-x8.c",
3595 "src/f32-vrnd/gen/vrndz-sse2-x8.c",
3596 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x8.c",
3597 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
3598 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
3599 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3600 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3601 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3602 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3603 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
3604 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
3605 "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c8-acc2.c",
3606 "src/qs8-gavgpool/gen/7x-minmax-sse2-c8-acc2.c",
3607 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3608 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3609 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3610 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3611 "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
3612 "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07003613 "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3614 "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003615 "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
3616 "src/qu8-avgpool/9x-minmax-sse2-c8.c",
3617 "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
3618 "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
3619 "src/qu8-gavgpool/7p7x-minmax-sse2-c8.c",
3620 "src/qu8-gavgpool/7x-minmax-sse2-c8.c",
3621 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3622 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3623 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3624 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3625 "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
3626 "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07003627 "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3628 "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
Marat Dukhan23147532021-08-16 07:26:56 -07003629 "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07003630 "src/s8-vclamp/sse2-x64.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003631 "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
3632 "src/u8-rmax/sse2.c",
3633 "src/u8-vclamp/sse2-x64.c",
3634 "src/x8-zip/x2-sse2.c",
3635 "src/x8-zip/x3-sse2.c",
3636 "src/x8-zip/x4-sse2.c",
3637 "src/x8-zip/xm-sse2.c",
3638 "src/x32-unpool/sse2.c",
3639 "src/x32-zip/x2-sse2.c",
3640 "src/x32-zip/x3-sse2.c",
3641 "src/x32-zip/x4-sse2.c",
3642 "src/x32-zip/xm-sse2.c",
Marat Dukhan933051b2021-08-07 16:26:15 -07003643 "src/xx-fill/sse2-x64.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -07003644 "src/xx-pad/sse2.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003645]
3646
3647ALL_SSE2_MICROKERNEL_SRCS = [
Marat Dukhan329da642019-11-19 21:44:39 -08003648 "src/f32-argmaxpool/4x-sse2-c4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003649 "src/f32-argmaxpool/9p8x-sse2-c4.c",
Marat Dukhan329da642019-11-19 21:44:39 -08003650 "src/f32-argmaxpool/9x-sse2-c4.c",
Marat Dukhan802fcae2020-12-11 14:37:25 -08003651 "src/f32-gemm/gen-inc/1x8inc-minmax-sse2-dup.c",
3652 "src/f32-gemm/gen-inc/3x8inc-minmax-sse2-dup.c",
3653 "src/f32-gemm/gen-inc/4x8inc-minmax-sse2-dup.c",
3654 "src/f32-gemm/gen-inc/5x8inc-minmax-sse2-dup.c",
3655 "src/f32-gemm/gen/1x8-minmax-sse2-dup.c",
3656 "src/f32-gemm/gen/3x8-minmax-sse2-dup.c",
3657 "src/f32-gemm/gen/4x8-minmax-sse2-dup.c",
3658 "src/f32-gemm/gen/5x8-minmax-sse2-dup.c",
3659 "src/f32-igemm/gen/1x8-minmax-sse2-dup.c",
3660 "src/f32-igemm/gen/3x8-minmax-sse2-dup.c",
3661 "src/f32-igemm/gen/4x8-minmax-sse2-dup.c",
3662 "src/f32-igemm/gen/5x8-minmax-sse2-dup.c",
Marat Dukhan40a672f2019-11-25 03:08:22 -08003663 "src/f32-prelu/gen/sse2-2x4.c",
3664 "src/f32-prelu/gen/sse2-2x8.c",
Marat Dukhanb39689d2020-01-24 13:32:20 -08003665 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x4.c",
Marat Dukhanb39689d2020-01-24 13:32:20 -08003666 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x8-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003667 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x8.c",
Marat Dukhanb39689d2020-01-24 13:32:20 -08003668 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12-acc2.c",
3669 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003670 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x12.c",
Marat Dukhanb39689d2020-01-24 13:32:20 -08003671 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16-acc2.c",
3672 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003673 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x16.c",
Marat Dukhanb39689d2020-01-24 13:32:20 -08003674 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20-acc2.c",
3675 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003676 "src/f32-raddstoreexpminusmax/gen/sse2-p5-x20.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08003677 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x4.c",
3678 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x8.c",
3679 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
3680 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x16.c",
3681 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x20.c",
3682 "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x24.c",
3683 "src/f32-velu/gen/velu-sse2-rr2-p6-x4.c",
3684 "src/f32-velu/gen/velu-sse2-rr2-p6-x8.c",
3685 "src/f32-velu/gen/velu-sse2-rr2-p6-x12.c",
3686 "src/f32-velu/gen/velu-sse2-rr2-p6-x16.c",
3687 "src/f32-velu/gen/velu-sse2-rr2-p6-x20.c",
3688 "src/f32-velu/gen/velu-sse2-rr2-p6-x24.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07003689 "src/f32-vlrelu/gen/vlrelu-sse2-x4.c",
3690 "src/f32-vlrelu/gen/vlrelu-sse2-x8.c",
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07003691 "src/f32-vrnd/gen/vrndd-sse2-x4.c",
3692 "src/f32-vrnd/gen/vrndd-sse2-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003693 "src/f32-vrnd/gen/vrndne-sse2-x4.c",
3694 "src/f32-vrnd/gen/vrndne-sse2-x8.c",
3695 "src/f32-vrnd/gen/vrndu-sse2-x4.c",
3696 "src/f32-vrnd/gen/vrndu-sse2-x8.c",
3697 "src/f32-vrnd/gen/vrndz-sse2-x4.c",
3698 "src/f32-vrnd/gen/vrndz-sse2-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07003699 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x4.c",
3700 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x8.c",
3701 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x12.c",
3702 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x16.c",
3703 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x20.c",
3704 "src/f32-vsigmoid/gen/vsigmoid-sse2-lut64-p2-div-x24.c",
3705 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x4.c",
3706 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x8.c",
3707 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x12.c",
3708 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x16.c",
3709 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x20.c",
3710 "src/f32-vsigmoid/gen/vsigmoid-sse2-p5-div-x24.c",
Marat Dukhanb7633f22020-11-20 16:34:56 -08003711 "src/math/exp-sse2-rr2-lut64-p2.c",
3712 "src/math/exp-sse2-rr2-p5.c",
Marat Dukhande390d42020-11-29 19:32:18 -08003713 "src/math/expm1minus-sse2-rr2-lut16-p3.c",
Marat Dukhana438aca2020-11-20 15:45:01 -08003714 "src/math/expm1minus-sse2-rr2-p6.c",
Frank Barchard3b800452020-11-22 12:12:35 -08003715 "src/math/expminus-sse2-rr2-p5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003716 "src/math/roundd-sse2-cvt.c",
3717 "src/math/roundne-sse2-cvt.c",
3718 "src/math/roundu-sse2-cvt.c",
3719 "src/math/roundz-sse2-cvt.c",
3720 "src/math/sigmoid-sse2-rr2-lut64-p2-div.c",
3721 "src/math/sigmoid-sse2-rr2-lut64-p2-nr1.c",
3722 "src/math/sigmoid-sse2-rr2-lut64-p2-nr2.c",
3723 "src/math/sigmoid-sse2-rr2-p5-div.c",
3724 "src/math/sigmoid-sse2-rr2-p5-nr1.c",
3725 "src/math/sigmoid-sse2-rr2-p5-nr2.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003726 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003727 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003728 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003729 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003730 "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003731 "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003732 "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003733 "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07003734 "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
3735 "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003736 "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003737 "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003738 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003739 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003740 "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003741 "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003742 "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003743 "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003744 "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003745 "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003746 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003747 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003748 "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003749 "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003750 "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003751 "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003752 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003753 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003754 "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003755 "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003756 "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003757 "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003758 "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003759 "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003760 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003761 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07003762 "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003763 "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003764 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003765 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
Marat Dukhancaf48312021-06-01 20:20:58 -07003766 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003767 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003768 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003769 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003770 "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003771 "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003772 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-sse2-mul16.c",
Marat Dukhan09668562021-07-26 16:52:20 -07003773 "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07003774 "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003775 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-sse2-mul16.c",
3776 "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
3777 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-sse2-mul16.c",
3778 "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
3779 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-sse2-mul16.c",
Marat Dukhan159688f2020-08-06 10:34:29 -07003780 "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c8-acc2.c",
3781 "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c16-acc2.c",
3782 "src/qs8-gavgpool/gen/7p7x-minmax-sse2-c24-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003783 "src/qs8-gavgpool/gen/7x-minmax-sse2-c8-acc2.c",
3784 "src/qs8-gavgpool/gen/7x-minmax-sse2-c16-acc2.c",
3785 "src/qs8-gavgpool/gen/7x-minmax-sse2-c24-acc2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003786 "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003787 "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003788 "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003789 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003790 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003791 "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003792 "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003793 "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003794 "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003795 "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003796 "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003797 "src/qs8-gemm/gen/2x4c8-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003798 "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003799 "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003800 "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003801 "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003802 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003803 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003804 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003805 "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003806 "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003807 "src/qs8-gemm/gen/4x4c2-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003808 "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003809 "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003810 "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003811 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003812 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003813 "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003814 "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003815 "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003816 "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003817 "src/qs8-igemm/gen/2x4c8-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003818 "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003819 "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003820 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003821 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003822 "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003823 "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003824 "src/qs8-igemm/gen/4x4c2-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhanf62bbdc2020-08-04 13:59:04 -07003825 "src/qs8-requantization/fp32-sse2.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07003826 "src/qs8-requantization/gemmlowp-sse2.c",
Marat Dukhan06716242021-05-26 15:56:39 -07003827 "src/qs8-requantization/rndna-sse2.c",
Marat Dukhand9f3ad42020-08-10 12:30:58 -07003828 "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
3829 "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
3830 "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x24.c",
3831 "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x32.c",
Marat Dukhan0270d9f2020-08-11 00:56:46 -07003832 "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
3833 "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
3834 "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x24.c",
3835 "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x32.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07003836 "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3837 "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
3838 "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3839 "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
Marat Dukhan08b7a972020-07-14 18:17:29 -07003840 "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
3841 "src/qu8-avgpool/9x-minmax-sse2-c8.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07003842 "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
3843 "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
3844 "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
3845 "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
Marat Dukhan08b7a972020-07-14 18:17:29 -07003846 "src/qu8-gavgpool/7p7x-minmax-sse2-c8.c",
3847 "src/qu8-gavgpool/7x-minmax-sse2-c8.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07003848 "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
3849 "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
3850 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3851 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
3852 "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
3853 "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
3854 "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
3855 "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07003856 "src/qu8-gemm/gen/2x4c8-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07003857 "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
3858 "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
3859 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3860 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
3861 "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
3862 "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07003863 "src/qu8-gemm/gen/4x4c2-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07003864 "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
3865 "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
3866 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
3867 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
3868 "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
3869 "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
3870 "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
3871 "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07003872 "src/qu8-igemm/gen/2x4c8-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07003873 "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
3874 "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
3875 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
3876 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
3877 "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
3878 "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07003879 "src/qu8-igemm/gen/4x4c2-minmax-gemmlowp-sse2-ld64.c",
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07003880 "src/qu8-requantization/fp32-sse2.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07003881 "src/qu8-requantization/gemmlowp-sse2.c",
Marat Dukhan06716242021-05-26 15:56:39 -07003882 "src/qu8-requantization/rndna-sse2.c",
Marat Dukhan76e78c82021-07-20 21:11:23 -07003883 "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
3884 "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
3885 "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
3886 "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07003887 "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3888 "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
3889 "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
3890 "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07003891 "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07003892 "src/s8-vclamp/sse2-x64.c",
Marat Dukhan99936602020-04-11 16:47:01 -07003893 "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003894 "src/u8-rmax/sse2.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07003895 "src/u8-vclamp/sse2-x64.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003896 "src/x8-zip/x2-sse2.c",
3897 "src/x8-zip/x3-sse2.c",
3898 "src/x8-zip/x4-sse2.c",
3899 "src/x8-zip/xm-sse2.c",
Marat Dukhan57dccd82020-04-14 00:53:10 -07003900 "src/x32-unpool/sse2.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003901 "src/x32-zip/x2-sse2.c",
3902 "src/x32-zip/x3-sse2.c",
3903 "src/x32-zip/x4-sse2.c",
3904 "src/x32-zip/xm-sse2.c",
Marat Dukhan933051b2021-08-07 16:26:15 -07003905 "src/xx-fill/sse2-x64.c",
Marat Dukhan0461f2d2021-08-08 12:36:29 -07003906 "src/xx-pad/sse2.c",
Marat Dukhanfe7acb62020-03-09 19:30:05 -07003907]
3908
Marat Dukhan2c724952021-07-27 18:46:30 -07003909PROD_SSSE3_MICROKERNEL_SRCS = [
3910 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4-acc2.c",
3911 "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c8-acc2.c",
3912 "src/qs8-gavgpool/gen/7x-minmax-ssse3-c8-acc2.c",
3913]
3914
3915ALL_SSSE3_MICROKERNEL_SRCS = [
Frank Barchard35db7d02020-10-26 13:37:34 -07003916 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc2.c",
3917 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc3.c",
3918 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc4.c",
Marat Dukhan98f2eeb2020-10-23 23:13:41 -07003919 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4.c",
Frank Barchard35db7d02020-10-26 13:37:34 -07003920 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4-acc2.c",
Marat Dukhan98f2eeb2020-10-23 23:13:41 -07003921 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4.c",
3922 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-3x4.c",
3923 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-4x4.c",
3924 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-5x4.c",
3925 "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-6x4.c",
Marat Dukhancaf48312021-06-01 20:20:58 -07003926 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-ssse3-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003927 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-ssse3-mul16.c",
3928 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-ssse3-mul16.c",
3929 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-ssse3-mul16.c",
3930 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-ssse3-mul16.c",
3931 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-ssse3-mul16.c",
Marat Dukhan159688f2020-08-06 10:34:29 -07003932 "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c8-acc2.c",
3933 "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c16-acc2.c",
3934 "src/qs8-gavgpool/gen/7p7x-minmax-ssse3-c24-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07003935 "src/qs8-gavgpool/gen/7x-minmax-ssse3-c8-acc2.c",
3936 "src/qs8-gavgpool/gen/7x-minmax-ssse3-c16-acc2.c",
3937 "src/qs8-gavgpool/gen/7x-minmax-ssse3-c24-acc2.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003938 "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-ssse3.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003939 "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003940 "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003941 "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-ssse3.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003942 "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003943 "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003944 "src/qs8-gemm/gen/2x4c8-minmax-gemmlowp-ssse3-ld64.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003945 "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-ssse3.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003946 "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003947 "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07003948 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-ssse3.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003949 "src/qs8-gemm/gen/4x4c2-minmax-gemmlowp-ssse3-ld64.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003950 "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003951 "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003952 "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003953 "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003954 "src/qs8-igemm/gen/2x4c8-minmax-gemmlowp-ssse3-ld64.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003955 "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07003956 "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07003957 "src/qs8-igemm/gen/4x4c2-minmax-gemmlowp-ssse3-ld64.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07003958 "src/qs8-requantization/gemmlowp-ssse3.c",
Marat Dukhan06716242021-05-26 15:56:39 -07003959 "src/qs8-requantization/rndna-ssse3.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07003960 "src/qu8-gemm/gen/2x4c8-minmax-gemmlowp-ssse3-ld64.c",
3961 "src/qu8-gemm/gen/4x4c2-minmax-gemmlowp-ssse3-ld64.c",
3962 "src/qu8-igemm/gen/2x4c8-minmax-gemmlowp-ssse3-ld64.c",
3963 "src/qu8-igemm/gen/4x4c2-minmax-gemmlowp-ssse3-ld64.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07003964 "src/qu8-requantization/gemmlowp-ssse3.c",
Marat Dukhan06716242021-05-26 15:56:39 -07003965 "src/qu8-requantization/rndna-ssse3.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07003966]
3967
Marat Dukhan2c724952021-07-27 18:46:30 -07003968PROD_SSE41_MICROKERNEL_SRCS = [
3969 "src/f32-prelu/gen/sse41-2x8.c",
3970 "src/f32-vlrelu/gen/vlrelu-sse41-x8.c",
3971 "src/f32-vrnd/gen/vrndd-sse41-x8.c",
3972 "src/f32-vrnd/gen/vrndne-sse41-x8.c",
3973 "src/f32-vrnd/gen/vrndu-sse41-x8.c",
3974 "src/f32-vrnd/gen/vrndz-sse41-x8.c",
3975 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x8.c",
3976 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
3977 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
3978 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3979 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
3980 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3981 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
3982 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
3983 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
3984 "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c8-acc2.c",
3985 "src/qs8-gavgpool/gen/7x-minmax-sse41-c8-acc2.c",
3986 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3987 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
3988 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3989 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
3990 "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
3991 "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07003992 "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
3993 "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07003994 "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
3995 "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
3996 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3997 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
3998 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
3999 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
4000 "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
4001 "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07004002 "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
4003 "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07004004 "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07004005 "src/s8-vclamp/sse41-x64.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07004006]
4007
4008ALL_SSE41_MICROKERNEL_SRCS = [
Marat Dukhan40a672f2019-11-25 03:08:22 -08004009 "src/f32-prelu/gen/sse41-2x4.c",
4010 "src/f32-prelu/gen/sse41-2x8.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08004011 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x4.c",
4012 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x8.c",
4013 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x12.c",
4014 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x16.c",
4015 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x20.c",
4016 "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x24.c",
4017 "src/f32-velu/gen/velu-sse41-rr2-p6-x4.c",
4018 "src/f32-velu/gen/velu-sse41-rr2-p6-x8.c",
4019 "src/f32-velu/gen/velu-sse41-rr2-p6-x12.c",
4020 "src/f32-velu/gen/velu-sse41-rr2-p6-x16.c",
4021 "src/f32-velu/gen/velu-sse41-rr2-p6-x20.c",
4022 "src/f32-velu/gen/velu-sse41-rr2-p6-x24.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07004023 "src/f32-vlrelu/gen/vlrelu-sse41-x4.c",
4024 "src/f32-vlrelu/gen/vlrelu-sse41-x8.c",
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07004025 "src/f32-vrnd/gen/vrndd-sse41-x4.c",
4026 "src/f32-vrnd/gen/vrndd-sse41-x8.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004027 "src/f32-vrnd/gen/vrndne-sse41-x4.c",
4028 "src/f32-vrnd/gen/vrndne-sse41-x8.c",
4029 "src/f32-vrnd/gen/vrndu-sse41-x4.c",
4030 "src/f32-vrnd/gen/vrndu-sse41-x8.c",
4031 "src/f32-vrnd/gen/vrndz-sse41-x4.c",
4032 "src/f32-vrnd/gen/vrndz-sse41-x8.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07004033 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x4.c",
4034 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x8.c",
4035 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x12.c",
4036 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x16.c",
4037 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x20.c",
4038 "src/f32-vsigmoid/gen/vsigmoid-sse41-lut64-p2-div-x24.c",
4039 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x4.c",
4040 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x8.c",
4041 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x12.c",
4042 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x16.c",
4043 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x20.c",
4044 "src/f32-vsigmoid/gen/vsigmoid-sse41-p5-div-x24.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004045 "src/math/roundd-sse41.c",
4046 "src/math/roundne-sse41.c",
4047 "src/math/roundu-sse41.c",
4048 "src/math/roundz-sse41.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004049 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004050 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004051 "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004052 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004053 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004054 "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004055 "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004056 "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004057 "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004058 "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004059 "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004060 "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
4061 "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
4062 "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
4063 "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
4064 "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004065 "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004066 "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004067 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004068 "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004069 "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004070 "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004071 "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004072 "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004073 "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004074 "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004075 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004076 "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004077 "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004078 "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004079 "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004080 "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004081 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004082 "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004083 "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004084 "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004085 "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004086 "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004087 "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004088 "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004089 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004090 "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004091 "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004092 "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004093 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004094 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
Marat Dukhancaf48312021-06-01 20:20:58 -07004095 "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
4096 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-sse41-mul16.c",
4097 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004098 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004099 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004100 "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
4101 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-sse41-mul16.c",
4102 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004103 "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004104 "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004105 "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
4106 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-sse41-mul16.c",
4107 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-sse41-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004108 "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004109 "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004110 "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
4111 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-sse41-mul16.c",
4112 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-sse41-mul32.c",
4113 "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
4114 "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
4115 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-sse41-mul16.c",
4116 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-sse41-mul32.c",
4117 "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
4118 "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
4119 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-sse41-mul16.c",
4120 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-sse41-mul32.c",
Marat Dukhan159688f2020-08-06 10:34:29 -07004121 "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c8-acc2.c",
4122 "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c16-acc2.c",
4123 "src/qs8-gavgpool/gen/7p7x-minmax-sse41-c24-acc2.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004124 "src/qs8-gavgpool/gen/7x-minmax-sse41-c8-acc2.c",
4125 "src/qs8-gavgpool/gen/7x-minmax-sse41-c16-acc2.c",
4126 "src/qs8-gavgpool/gen/7x-minmax-sse41-c24-acc2.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004127 "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004128 "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004129 "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004130 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004131 "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004132 "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004133 "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004134 "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004135 "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004136 "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004137 "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004138 "src/qs8-gemm/gen/2x4c8-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004139 "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004140 "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004141 "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004142 "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004143 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004144 "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004145 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004146 "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004147 "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004148 "src/qs8-gemm/gen/4x4c2-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004149 "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse41.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004150 "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004151 "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004152 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004153 "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004154 "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004155 "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004156 "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004157 "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004158 "src/qs8-igemm/gen/2x4c8-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004159 "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004160 "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004161 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004162 "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004163 "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004164 "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004165 "src/qs8-igemm/gen/4x4c2-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhan2e23d2b2020-07-29 16:01:37 -07004166 "src/qs8-requantization/fp32-sse4.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07004167 "src/qs8-requantization/gemmlowp-sse4.c",
Marat Dukhan06716242021-05-26 15:56:39 -07004168 "src/qs8-requantization/rndna-sse4.c",
Marat Dukhan0d979d52021-06-09 13:21:18 -07004169 "src/qs8-requantization/rndnu-sse4-sra.c",
4170 "src/qs8-requantization/rndnu-sse4-srl.c",
Marat Dukhand9f3ad42020-08-10 12:30:58 -07004171 "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
4172 "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
4173 "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x24.c",
4174 "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x32.c",
Marat Dukhanbb9225e2020-09-06 22:40:56 -07004175 "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x8.c",
4176 "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x16.c",
4177 "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x24.c",
4178 "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x32.c",
Marat Dukhan0270d9f2020-08-11 00:56:46 -07004179 "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
4180 "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x16.c",
4181 "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x24.c",
4182 "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x32.c",
Marat Dukhanbb9225e2020-09-06 22:40:56 -07004183 "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x8.c",
4184 "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
4185 "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x24.c",
4186 "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x32.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07004187 "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
4188 "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
4189 "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
4190 "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004191 "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004192 "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004193 "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004194 "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004195 "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004196 "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004197 "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004198 "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004199 "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
4200 "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
4201 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
4202 "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
4203 "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
4204 "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
4205 "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
4206 "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07004207 "src/qu8-gemm/gen/2x4c8-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004208 "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
4209 "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
4210 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
4211 "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
4212 "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
4213 "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07004214 "src/qu8-gemm/gen/4x4c2-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004215 "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
4216 "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
4217 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
4218 "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
4219 "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
4220 "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
4221 "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
4222 "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07004223 "src/qu8-igemm/gen/2x4c8-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004224 "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
4225 "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
4226 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
4227 "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
4228 "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
4229 "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
Marat Dukhancdbe9a32021-07-01 23:52:04 -07004230 "src/qu8-igemm/gen/4x4c2-minmax-gemmlowp-sse41-ld64.c",
Marat Dukhan9976cd82021-05-24 23:15:45 -07004231 "src/qu8-requantization/gemmlowp-sse4.c",
Marat Dukhan06716242021-05-26 15:56:39 -07004232 "src/qu8-requantization/rndna-sse4.c",
Marat Dukhan3eac69c2021-07-21 01:42:29 -07004233 "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
4234 "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
4235 "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x8.c",
4236 "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x16.c",
4237 "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
4238 "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x16.c",
4239 "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x8.c",
4240 "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07004241 "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
4242 "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
4243 "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
4244 "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
Marat Dukhan23147532021-08-16 07:26:56 -07004245 "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
Marat Dukhane79acb72021-08-16 19:03:53 -07004246 "src/s8-vclamp/sse41-x64.c",
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08004247]
4248
Marat Dukhan2c724952021-07-27 18:46:30 -07004249PROD_AVX_MICROKERNEL_SRCS = [
4250 "src/f32-dwconv/gen/up8x25-minmax-avx.c",
4251 "src/f32-dwconv/gen/up16x4-minmax-avx.c",
4252 "src/f32-dwconv/gen/up16x9-minmax-avx.c",
4253 "src/f32-gemm/gen/1x16-minmax-avx-broadcast.c",
4254 "src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
4255 "src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
4256 "src/f32-igemm/gen/5x16-minmax-avx-broadcast.c",
4257 "src/f32-prelu/gen/avx-2x16.c",
4258 "src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
4259 "src/f32-vbinary/gen/vaddc-minmax-avx-x16.c",
4260 "src/f32-vbinary/gen/vdiv-minmax-avx-x16.c",
4261 "src/f32-vbinary/gen/vdivc-minmax-avx-x16.c",
4262 "src/f32-vbinary/gen/vmax-avx-x16.c",
4263 "src/f32-vbinary/gen/vmaxc-avx-x16.c",
4264 "src/f32-vbinary/gen/vmin-avx-x16.c",
4265 "src/f32-vbinary/gen/vminc-avx-x16.c",
4266 "src/f32-vbinary/gen/vmul-minmax-avx-x16.c",
4267 "src/f32-vbinary/gen/vmulc-minmax-avx-x16.c",
4268 "src/f32-vbinary/gen/vrdivc-minmax-avx-x16.c",
4269 "src/f32-vbinary/gen/vrsubc-minmax-avx-x16.c",
4270 "src/f32-vbinary/gen/vsqrdiff-avx-x16.c",
4271 "src/f32-vbinary/gen/vsqrdiffc-avx-x16.c",
4272 "src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
4273 "src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
4274 "src/f32-vclamp/gen/vclamp-avx-x16.c",
4275 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x32.c",
4276 "src/f32-vhswish/gen/vhswish-avx-x16.c",
4277 "src/f32-vlrelu/gen/vlrelu-avx-x16.c",
4278 "src/f32-vrnd/gen/vrndd-avx-x16.c",
4279 "src/f32-vrnd/gen/vrndne-avx-x16.c",
4280 "src/f32-vrnd/gen/vrndu-avx-x16.c",
4281 "src/f32-vrnd/gen/vrndz-avx-x16.c",
4282 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
4283 "src/f32-vsqrt/gen/avx-sqrt-x8.c",
4284 "src/f32-vunary/gen/vabs-avx-x16.c",
4285 "src/f32-vunary/gen/vneg-avx-x16.c",
4286 "src/f32-vunary/gen/vsqr-avx-x16.c",
Marat Dukhan28480592021-07-27 23:52:27 -07004287 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
4288 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07004289 "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4290 "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4291 "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4292 "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4293 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
4294 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
4295 "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4296 "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4297 "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4298 "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4299 "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
4300 "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07004301 "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
4302 "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07004303 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
4304 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
4305 "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4306 "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4307 "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4308 "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4309 "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
4310 "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
Marat Dukhan0853b8a2021-08-03 01:01:53 -07004311 "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
4312 "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07004313]
4314
4315ALL_AVX_MICROKERNEL_SRCS = [
Marat Dukhan1c587112020-04-08 20:04:28 -07004316 "src/f32-dwconv/gen/up8x4-minmax-avx-acc2.c",
4317 "src/f32-dwconv/gen/up8x4-minmax-avx.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004318 "src/f32-dwconv/gen/up8x9-minmax-avx-acc2.c",
4319 "src/f32-dwconv/gen/up8x9-minmax-avx.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004320 "src/f32-dwconv/gen/up8x25-minmax-avx-acc2.c",
4321 "src/f32-dwconv/gen/up8x25-minmax-avx.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004322 "src/f32-dwconv/gen/up16x4-minmax-avx-acc2.c",
4323 "src/f32-dwconv/gen/up16x4-minmax-avx.c",
4324 "src/f32-dwconv/gen/up16x9-minmax-avx-acc2.c",
4325 "src/f32-dwconv/gen/up16x9-minmax-avx.c",
4326 "src/f32-dwconv/gen/up16x25-minmax-avx-acc2.c",
4327 "src/f32-dwconv/gen/up16x25-minmax-avx.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004328 "src/f32-gemm/gen-inc/1x8inc-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004329 "src/f32-gemm/gen-inc/1x16inc-minmax-avx-broadcast.c",
4330 "src/f32-gemm/gen-inc/3x16inc-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004331 "src/f32-gemm/gen-inc/4x8inc-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004332 "src/f32-gemm/gen-inc/4x16inc-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004333 "src/f32-gemm/gen-inc/5x8inc-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004334 "src/f32-gemm/gen-inc/5x16inc-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004335 "src/f32-gemm/gen-inc/6x8inc-minmax-avx-broadcast.c",
4336 "src/f32-gemm/gen-inc/7x8inc-minmax-avx-broadcast.c",
4337 "src/f32-gemm/gen/1x8-minmax-avx-broadcast.c",
4338 "src/f32-gemm/gen/1x16-minmax-avx-broadcast.c",
4339 "src/f32-gemm/gen/3x16-minmax-avx-broadcast.c",
4340 "src/f32-gemm/gen/4x8-minmax-avx-broadcast.c",
4341 "src/f32-gemm/gen/4x16-minmax-avx-broadcast.c",
4342 "src/f32-gemm/gen/5x8-minmax-avx-broadcast.c",
4343 "src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
4344 "src/f32-gemm/gen/6x8-minmax-avx-broadcast.c",
4345 "src/f32-gemm/gen/7x8-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004346 "src/f32-igemm/gen/1x8-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004347 "src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
4348 "src/f32-igemm/gen/3x16-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004349 "src/f32-igemm/gen/4x8-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004350 "src/f32-igemm/gen/4x16-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004351 "src/f32-igemm/gen/5x8-minmax-avx-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004352 "src/f32-igemm/gen/5x16-minmax-avx-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004353 "src/f32-igemm/gen/6x8-minmax-avx-broadcast.c",
4354 "src/f32-igemm/gen/7x8-minmax-avx-broadcast.c",
Marat Dukhan90eca0a2020-03-11 00:52:23 -07004355 "src/f32-prelu/gen/avx-2x8.c",
4356 "src/f32-prelu/gen/avx-2x16.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07004357 "src/f32-rmax/avx.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07004358 "src/f32-vbinary/gen/vadd-minmax-avx-x8.c",
4359 "src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
4360 "src/f32-vbinary/gen/vaddc-minmax-avx-x8.c",
4361 "src/f32-vbinary/gen/vaddc-minmax-avx-x16.c",
4362 "src/f32-vbinary/gen/vdiv-minmax-avx-x8.c",
4363 "src/f32-vbinary/gen/vdiv-minmax-avx-x16.c",
4364 "src/f32-vbinary/gen/vdivc-minmax-avx-x8.c",
4365 "src/f32-vbinary/gen/vdivc-minmax-avx-x16.c",
Marat Dukhan9a88efe2019-12-10 15:54:24 -08004366 "src/f32-vbinary/gen/vmax-avx-x8.c",
4367 "src/f32-vbinary/gen/vmax-avx-x16.c",
4368 "src/f32-vbinary/gen/vmaxc-avx-x8.c",
4369 "src/f32-vbinary/gen/vmaxc-avx-x16.c",
4370 "src/f32-vbinary/gen/vmin-avx-x8.c",
4371 "src/f32-vbinary/gen/vmin-avx-x16.c",
4372 "src/f32-vbinary/gen/vminc-avx-x8.c",
4373 "src/f32-vbinary/gen/vminc-avx-x16.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07004374 "src/f32-vbinary/gen/vmul-minmax-avx-x8.c",
4375 "src/f32-vbinary/gen/vmul-minmax-avx-x16.c",
4376 "src/f32-vbinary/gen/vmulc-minmax-avx-x8.c",
4377 "src/f32-vbinary/gen/vmulc-minmax-avx-x16.c",
4378 "src/f32-vbinary/gen/vrdivc-minmax-avx-x8.c",
4379 "src/f32-vbinary/gen/vrdivc-minmax-avx-x16.c",
4380 "src/f32-vbinary/gen/vrsubc-minmax-avx-x8.c",
4381 "src/f32-vbinary/gen/vrsubc-minmax-avx-x16.c",
Marat Dukhan13bafb02020-06-05 00:43:11 -07004382 "src/f32-vbinary/gen/vsqrdiff-avx-x8.c",
4383 "src/f32-vbinary/gen/vsqrdiff-avx-x16.c",
4384 "src/f32-vbinary/gen/vsqrdiffc-avx-x8.c",
4385 "src/f32-vbinary/gen/vsqrdiffc-avx-x16.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07004386 "src/f32-vbinary/gen/vsub-minmax-avx-x8.c",
4387 "src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
4388 "src/f32-vbinary/gen/vsubc-minmax-avx-x8.c",
4389 "src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07004390 "src/f32-vclamp/gen/vclamp-avx-x8.c",
4391 "src/f32-vclamp/gen/vclamp-avx-x16.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08004392 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x8.c",
4393 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x16.c",
4394 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x24.c",
4395 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x32.c",
4396 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x40.c",
4397 "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x48.c",
4398 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x8.c",
4399 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x16.c",
4400 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x24.c",
4401 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x32.c",
4402 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x40.c",
4403 "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x48.c",
4404 "src/f32-velu/gen/velu-avx-rr2-p6-x8.c",
4405 "src/f32-velu/gen/velu-avx-rr2-p6-x16.c",
4406 "src/f32-velu/gen/velu-avx-rr2-p6-x24.c",
4407 "src/f32-velu/gen/velu-avx-rr2-p6-x32.c",
4408 "src/f32-velu/gen/velu-avx-rr2-p6-x40.c",
4409 "src/f32-velu/gen/velu-avx-rr2-p6-x48.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07004410 "src/f32-vhswish/gen/vhswish-avx-x8.c",
4411 "src/f32-vhswish/gen/vhswish-avx-x16.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07004412 "src/f32-vlrelu/gen/vlrelu-avx-x8.c",
4413 "src/f32-vlrelu/gen/vlrelu-avx-x16.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07004414 "src/f32-vrelu/gen/vrelu-avx-x8.c",
4415 "src/f32-vrelu/gen/vrelu-avx-x16.c",
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07004416 "src/f32-vrnd/gen/vrndd-avx-x8.c",
4417 "src/f32-vrnd/gen/vrndd-avx-x16.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004418 "src/f32-vrnd/gen/vrndne-avx-x8.c",
4419 "src/f32-vrnd/gen/vrndne-avx-x16.c",
4420 "src/f32-vrnd/gen/vrndu-avx-x8.c",
4421 "src/f32-vrnd/gen/vrndu-avx-x16.c",
4422 "src/f32-vrnd/gen/vrndz-avx-x8.c",
4423 "src/f32-vrnd/gen/vrndz-avx-x16.c",
Frank Barchardbeca6522020-10-30 22:34:35 -07004424 "src/f32-vscale/avx-x32.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07004425 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x8.c",
4426 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x16.c",
4427 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x24.c",
4428 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x32.c",
4429 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x40.c",
4430 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x48.c",
4431 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x56.c",
4432 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x64.c",
4433 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x72.c",
4434 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x80.c",
4435 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x8.c",
4436 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x16.c",
4437 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x24.c",
4438 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x32.c",
4439 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
4440 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x48.c",
4441 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x56.c",
4442 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x64.c",
4443 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x72.c",
4444 "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x80.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07004445 "src/f32-vsqrt/gen/avx-sqrt-x8.c",
4446 "src/f32-vsqrt/gen/avx-sqrt-x16.c",
Marat Dukhan5020b962020-06-08 13:30:10 -07004447 "src/f32-vunary/gen/vabs-avx-x8.c",
4448 "src/f32-vunary/gen/vabs-avx-x16.c",
4449 "src/f32-vunary/gen/vneg-avx-x8.c",
4450 "src/f32-vunary/gen/vneg-avx-x16.c",
4451 "src/f32-vunary/gen/vsqr-avx-x8.c",
4452 "src/f32-vunary/gen/vsqr-avx-x16.c",
Frank Barchard4a352042021-04-13 15:52:08 -07004453 "src/math/exp-avx-rr2-p5.c",
4454 "src/math/expm1minus-avx-rr2-lut4-p4-perm.c",
4455 "src/math/expm1minus-avx-rr2-lut16-p3.c",
4456 "src/math/expm1minus-avx-rr2-p6.c",
4457 "src/math/sigmoid-avx-rr2-lut64-p2-div.c",
4458 "src/math/sigmoid-avx-rr2-p5-div.c",
4459 "src/math/sigmoid-avx-rr2-p5-nr1.c",
4460 "src/math/sigmoid-avx-rr2-p5-nr2.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004461 "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004462 "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004463 "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004464 "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004465 "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004466 "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004467 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004468 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004469 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004470 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004471 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004472 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
4473 "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
4474 "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
4475 "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
4476 "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004477 "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004478 "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004479 "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004480 "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004481 "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004482 "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004483 "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004484 "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004485 "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004486 "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004487 "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004488 "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004489 "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004490 "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004491 "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004492 "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004493 "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004494 "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004495 "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004496 "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004497 "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004498 "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004499 "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004500 "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004501 "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004502 "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004503 "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004504 "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004505 "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004506 "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
Marat Dukhancaf48312021-06-01 20:20:58 -07004507 "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
4508 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-avx-mul16.c",
4509 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004510 "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004511 "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004512 "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
4513 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-avx-mul16.c",
4514 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004515 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004516 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004517 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
4518 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx-mul16.c",
4519 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004520 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07004521 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004522 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
4523 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx-mul16.c",
4524 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx-mul32.c",
4525 "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
4526 "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
4527 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-avx-mul16.c",
4528 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-avx-mul32.c",
4529 "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
4530 "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
4531 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-avx-mul16.c",
4532 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-avx-mul32.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004533 "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004534 "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004535 "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004536 "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004537 "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004538 "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004539 "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004540 "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004541 "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004542 "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004543 "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004544 "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004545 "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004546 "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004547 "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004548 "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004549 "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004550 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004551 "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004552 "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004553 "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-avx.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004554 "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004555 "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004556 "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004557 "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004558 "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004559 "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004560 "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004561 "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004562 "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004563 "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004564 "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004565 "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004566 "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004567 "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhane9c4b962021-04-02 16:56:55 -07004568 "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
4569 "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
4570 "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x24.c",
4571 "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x32.c",
4572 "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
4573 "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
4574 "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x24.c",
4575 "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x32.c",
4576 "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
4577 "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
4578 "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x24.c",
4579 "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x32.c",
4580 "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
4581 "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
4582 "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x24.c",
4583 "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x32.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07004584 "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
4585 "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
4586 "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
4587 "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004588 "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004589 "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004590 "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004591 "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004592 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004593 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
Marat Dukhanf0f28812021-07-08 22:34:20 -07004594 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004595 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004596 "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
4597 "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
4598 "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
4599 "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4600 "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
4601 "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
4602 "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
4603 "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4604 "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
4605 "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
4606 "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
4607 "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
4608 "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
4609 "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
4610 "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
4611 "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
4612 "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
4613 "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
4614 "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
4615 "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
4616 "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
4617 "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
4618 "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
4619 "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
4620 "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
4621 "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
4622 "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
4623 "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
Marat Dukhan3eac69c2021-07-21 01:42:29 -07004624 "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
4625 "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
4626 "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
4627 "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
4628 "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
4629 "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
4630 "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
4631 "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
Marat Dukhana212eac2021-08-02 09:58:04 -07004632 "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
4633 "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
4634 "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
4635 "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07004636]
4637
Marat Dukhan2c724952021-07-27 18:46:30 -07004638PROD_XOP_MICROKERNEL_SRCS = [
Marat Dukhan28480592021-07-27 23:52:27 -07004639 "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
4640 "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
Marat Dukhan2c724952021-07-27 18:46:30 -07004641 "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4642 "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4643 "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4644 "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4645 "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
4646 "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
4647 "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4648 "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4649 "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4650 "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4651 "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
4652 "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
4653 "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
4654 "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
4655 "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4656 "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4657 "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4658 "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4659 "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
4660 "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
4661]
4662
4663ALL_XOP_MICROKERNEL_SRCS = [
Marat Dukhan09668562021-07-26 16:52:20 -07004664 "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004665 "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004666 "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004667 "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004668 "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004669 "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004670 "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
Marat Dukhan98042f22021-06-15 00:43:13 -07004671 "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
4672 "src/qc8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
4673 "src/qc8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004674 "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004675 "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004676 "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004677 "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004678 "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004679 "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004680 "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
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Marat Dukhanfc188ed2021-06-03 12:21:22 -07004682 "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004683 "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004684 "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004685 "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004686 "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004687 "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004688 "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004689 "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004690 "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004691 "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004692 "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004693 "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004694 "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004695 "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004696 "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004697 "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004698 "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004699 "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanfc188ed2021-06-03 12:21:22 -07004700 "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004701 "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004702 "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
Marat Dukhancaf48312021-06-01 20:20:58 -07004703 "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
4704 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004705 "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004706 "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
4707 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004708 "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004709 "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
4710 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-xop-mul32.c",
Marat Dukhan09668562021-07-26 16:52:20 -07004711 "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004712 "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
4713 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-xop-mul32.c",
4714 "src/qs8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
4715 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-xop-mul32.c",
4716 "src/qs8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
4717 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-xop-mul32.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004718 "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004719 "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004720 "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004721 "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004722 "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004723 "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004724 "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004725 "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004726 "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004727 "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004728 "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004729 "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004730 "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004731 "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004732 "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004733 "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004734 "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004735 "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004736 "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004737 "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan0ff79892021-08-06 16:05:06 -07004738 "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-xop.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004739 "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004740 "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004741 "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004742 "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004743 "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004744 "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004745 "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004746 "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004747 "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004748 "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004749 "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004750 "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
Marat Dukhanc46e6712021-06-01 19:00:16 -07004751 "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
Frank Barchard23eb4822021-06-08 15:03:41 -07004752 "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhanbb9225e2020-09-06 22:40:56 -07004753 "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
4754 "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
4755 "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x24.c",
4756 "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x32.c",
4757 "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
4758 "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
4759 "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x24.c",
4760 "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x32.c",
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07004761 "src/qu8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
4762 "src/qu8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
4763 "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
4764 "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
Marat Dukhanef47f8d2021-07-02 15:08:32 -07004765 "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
4766 "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
4767 "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4768 "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
4769 "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
4770 "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
4771 "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4772 "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
4773 "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
4774 "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
4775 "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
4776 "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
4777 "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
4778 "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
4779 "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
4780 "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
4781 "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
4782 "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
4783 "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
4784 "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
4785 "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
4786 "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
4787 "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
4788 "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
4789 "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
4790 "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
4791 "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
4792 "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
Marat Dukhan3eac69c2021-07-21 01:42:29 -07004793 "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
4794 "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
4795 "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
4796 "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
Marat Dukhan1566fee2020-08-02 21:55:41 -07004797]
4798
Marat Dukhan2c724952021-07-27 18:46:30 -07004799PROD_FMA3_MICROKERNEL_SRCS = [
4800 "src/f32-dwconv/gen/up8x4-minmax-fma3-acc2.c",
4801 "src/f32-dwconv/gen/up8x4-minmax-fma3.c",
4802 "src/f32-dwconv/gen/up8x9-minmax-fma3-acc2.c",
4803 "src/f32-dwconv/gen/up8x9-minmax-fma3.c",
4804 "src/f32-dwconv/gen/up8x25-minmax-fma3-acc2.c",
4805 "src/f32-dwconv/gen/up8x25-minmax-fma3.c",
4806 "src/f32-dwconv/gen/up16x4-minmax-fma3-acc2.c",
4807 "src/f32-dwconv/gen/up16x4-minmax-fma3.c",
4808 "src/f32-dwconv/gen/up16x9-minmax-fma3-acc2.c",
4809 "src/f32-dwconv/gen/up16x9-minmax-fma3.c",
4810 "src/f32-dwconv/gen/up16x25-minmax-fma3-acc2.c",
4811 "src/f32-dwconv/gen/up16x25-minmax-fma3.c",
4812 "src/f32-gemm/gen/1x16-minmax-fma3-broadcast.c",
4813 "src/f32-gemm/gen/1x16s4-minmax-fma3-broadcast.c",
4814 "src/f32-gemm/gen/4x16s4-minmax-fma3-broadcast.c",
4815 "src/f32-gemm/gen/5x16-minmax-fma3-broadcast.c",
4816 "src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
4817 "src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
4818 "src/f32-igemm/gen/4x16s4-minmax-fma3-broadcast.c",
4819 "src/f32-igemm/gen/5x16-minmax-fma3-broadcast.c",
4820 "src/f32-vhswish/gen/vhswish-fma3-x16.c",
4821]
4822
4823ALL_FMA3_MICROKERNEL_SRCS = [
Marat Dukhan1c587112020-04-08 20:04:28 -07004824 "src/f32-dwconv/gen/up8x4-minmax-fma3-acc2.c",
4825 "src/f32-dwconv/gen/up8x4-minmax-fma3.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004826 "src/f32-dwconv/gen/up8x9-minmax-fma3-acc2.c",
4827 "src/f32-dwconv/gen/up8x9-minmax-fma3.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004828 "src/f32-dwconv/gen/up8x25-minmax-fma3-acc2.c",
4829 "src/f32-dwconv/gen/up8x25-minmax-fma3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004830 "src/f32-dwconv/gen/up16x4-minmax-fma3-acc2.c",
4831 "src/f32-dwconv/gen/up16x4-minmax-fma3.c",
4832 "src/f32-dwconv/gen/up16x9-minmax-fma3-acc2.c",
4833 "src/f32-dwconv/gen/up16x9-minmax-fma3.c",
4834 "src/f32-dwconv/gen/up16x25-minmax-fma3-acc2.c",
4835 "src/f32-dwconv/gen/up16x25-minmax-fma3.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004836 "src/f32-gemm/gen-inc/1x8inc-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004837 "src/f32-gemm/gen-inc/1x16inc-minmax-fma3-broadcast.c",
4838 "src/f32-gemm/gen-inc/1x16s4inc-minmax-fma3-broadcast.c",
4839 "src/f32-gemm/gen-inc/3x16inc-minmax-fma3-broadcast.c",
4840 "src/f32-gemm/gen-inc/3x16s4inc-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004841 "src/f32-gemm/gen-inc/4x8inc-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004842 "src/f32-gemm/gen-inc/4x16inc-minmax-fma3-broadcast.c",
4843 "src/f32-gemm/gen-inc/4x16s4inc-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004844 "src/f32-gemm/gen-inc/5x8inc-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004845 "src/f32-gemm/gen-inc/5x16inc-minmax-fma3-broadcast.c",
4846 "src/f32-gemm/gen-inc/5x16s4inc-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004847 "src/f32-gemm/gen-inc/6x8inc-minmax-fma3-broadcast.c",
4848 "src/f32-gemm/gen-inc/7x8inc-minmax-fma3-broadcast.c",
4849 "src/f32-gemm/gen-inc/8x8inc-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004850 "src/f32-gemm/gen/1x8-minmax-fma3-broadcast.c",
4851 "src/f32-gemm/gen/1x16-minmax-fma3-broadcast.c",
4852 "src/f32-gemm/gen/1x16s4-minmax-fma3-broadcast.c",
4853 "src/f32-gemm/gen/3x16-minmax-fma3-broadcast.c",
4854 "src/f32-gemm/gen/3x16s4-minmax-fma3-broadcast.c",
4855 "src/f32-gemm/gen/4x8-minmax-fma3-broadcast.c",
4856 "src/f32-gemm/gen/4x16-minmax-fma3-broadcast.c",
4857 "src/f32-gemm/gen/4x16s4-minmax-fma3-broadcast.c",
4858 "src/f32-gemm/gen/5x8-minmax-fma3-broadcast.c",
4859 "src/f32-gemm/gen/5x16-minmax-fma3-broadcast.c",
4860 "src/f32-gemm/gen/5x16s4-minmax-fma3-broadcast.c",
4861 "src/f32-gemm/gen/6x8-minmax-fma3-broadcast.c",
4862 "src/f32-gemm/gen/7x8-minmax-fma3-broadcast.c",
4863 "src/f32-gemm/gen/8x8-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004864 "src/f32-igemm/gen/1x8-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004865 "src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
4866 "src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
4867 "src/f32-igemm/gen/3x16-minmax-fma3-broadcast.c",
4868 "src/f32-igemm/gen/3x16s4-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004869 "src/f32-igemm/gen/4x8-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004870 "src/f32-igemm/gen/4x16-minmax-fma3-broadcast.c",
4871 "src/f32-igemm/gen/4x16s4-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004872 "src/f32-igemm/gen/5x8-minmax-fma3-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004873 "src/f32-igemm/gen/5x16-minmax-fma3-broadcast.c",
4874 "src/f32-igemm/gen/5x16s4-minmax-fma3-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07004875 "src/f32-igemm/gen/6x8-minmax-fma3-broadcast.c",
4876 "src/f32-igemm/gen/7x8-minmax-fma3-broadcast.c",
4877 "src/f32-igemm/gen/8x8-minmax-fma3-broadcast.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07004878 "src/f32-vhswish/gen/vhswish-fma3-x8.c",
4879 "src/f32-vhswish/gen/vhswish-fma3-x16.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07004880 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x8.c",
4881 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x16.c",
4882 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x24.c",
4883 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x32.c",
4884 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x40.c",
4885 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x48.c",
4886 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x56.c",
4887 "src/f32-vsqrt/gen/fma3-nr1fma1adj-x64.c",
Marat Dukhan84000762020-06-29 18:38:43 -07004888 "src/math/sqrt-fma3-nr1fma.c",
Marat Dukhan84000762020-06-29 18:38:43 -07004889 "src/math/sqrt-fma3-nr1fma1adj.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004890 "src/math/sqrt-fma3-nr2fma.c",
Marat Dukhanfda12b82019-11-21 12:27:59 -08004891]
4892
Marat Dukhan2c724952021-07-27 18:46:30 -07004893PROD_AVX2_MICROKERNEL_SRCS = [
4894 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x56.c",
4895 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
4896 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
4897 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
4898 "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
4899 "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
4900 "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
4901 "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
4902 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
4903 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
4904 "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
4905 "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
4906 "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
4907 "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
4908 "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
4909 "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
4910 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
4911 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
4912 "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
4913 "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
4914 "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
4915 "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
4916 "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
4917 "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
4918]
4919
4920ALL_AVX2_MICROKERNEL_SRCS = [
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004921 "src/f32-raddexpminusmax/gen/avx2-p5-x64-acc2.c",
4922 "src/f32-raddexpminusmax/gen/avx2-p5-x64-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004923 "src/f32-raddexpminusmax/gen/avx2-p5-x64.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004924 "src/f32-raddexpminusmax/gen/avx2-p5-x72-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004925 "src/f32-raddexpminusmax/gen/avx2-p5-x72.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004926 "src/f32-raddexpminusmax/gen/avx2-p5-x80-acc2.c",
4927 "src/f32-raddexpminusmax/gen/avx2-p5-x80-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004928 "src/f32-raddexpminusmax/gen/avx2-p5-x80.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004929 "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc2.c",
4930 "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc3.c",
4931 "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004932 "src/f32-raddexpminusmax/gen/avx2-p5-x96.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004933 "src/f32-raddextexp/gen/avx2-p5-x64-acc2.c",
4934 "src/f32-raddextexp/gen/avx2-p5-x64-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004935 "src/f32-raddextexp/gen/avx2-p5-x64.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004936 "src/f32-raddextexp/gen/avx2-p5-x72-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004937 "src/f32-raddextexp/gen/avx2-p5-x72.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004938 "src/f32-raddextexp/gen/avx2-p5-x80-acc2.c",
4939 "src/f32-raddextexp/gen/avx2-p5-x80-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004940 "src/f32-raddextexp/gen/avx2-p5-x80.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004941 "src/f32-raddextexp/gen/avx2-p5-x96-acc2.c",
4942 "src/f32-raddextexp/gen/avx2-p5-x96-acc3.c",
4943 "src/f32-raddextexp/gen/avx2-p5-x96-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004944 "src/f32-raddextexp/gen/avx2-p5-x96.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004945 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64-acc2.c",
4946 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004947 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x64.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004948 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x72-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004949 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x72.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004950 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80-acc2.c",
4951 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004952 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x80.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004953 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc2.c",
4954 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc3.c",
4955 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07004956 "src/f32-raddstoreexpminusmax/gen/avx2-p5-x96.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08004957 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x8.c",
4958 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x16.c",
4959 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x24.c",
4960 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x32.c",
4961 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x40.c",
4962 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x48.c",
4963 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x56.c",
4964 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x64.c",
4965 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x72.c",
4966 "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x80.c",
4967 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x8.c",
4968 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x16.c",
4969 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x24.c",
4970 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x32.c",
4971 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x40.c",
4972 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x48.c",
4973 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x56.c",
4974 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x64.c",
4975 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x72.c",
4976 "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x80.c",
4977 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x8.c",
4978 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x16.c",
4979 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x24.c",
4980 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x32.c",
4981 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x40.c",
4982 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x48.c",
4983 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x56.c",
4984 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x64.c",
4985 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x72.c",
4986 "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x80.c",
4987 "src/f32-velu/gen/velu-avx2-rr1-p6-x8.c",
4988 "src/f32-velu/gen/velu-avx2-rr1-p6-x16.c",
4989 "src/f32-velu/gen/velu-avx2-rr1-p6-x24.c",
4990 "src/f32-velu/gen/velu-avx2-rr1-p6-x32.c",
4991 "src/f32-velu/gen/velu-avx2-rr1-p6-x40.c",
4992 "src/f32-velu/gen/velu-avx2-rr1-p6-x48.c",
4993 "src/f32-velu/gen/velu-avx2-rr1-p6-x56.c",
4994 "src/f32-velu/gen/velu-avx2-rr1-p6-x64.c",
4995 "src/f32-velu/gen/velu-avx2-rr1-p6-x72.c",
4996 "src/f32-velu/gen/velu-avx2-rr1-p6-x80.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08004997 "src/f32-vscaleexpminusmax/gen/avx2-p5-x8.c",
4998 "src/f32-vscaleexpminusmax/gen/avx2-p5-x16.c",
4999 "src/f32-vscaleexpminusmax/gen/avx2-p5-x24.c",
5000 "src/f32-vscaleexpminusmax/gen/avx2-p5-x32.c",
5001 "src/f32-vscaleexpminusmax/gen/avx2-p5-x40.c",
5002 "src/f32-vscaleexpminusmax/gen/avx2-p5-x48.c",
5003 "src/f32-vscaleexpminusmax/gen/avx2-p5-x56.c",
5004 "src/f32-vscaleexpminusmax/gen/avx2-p5-x64.c",
5005 "src/f32-vscaleexpminusmax/gen/avx2-p5-x72.c",
5006 "src/f32-vscaleexpminusmax/gen/avx2-p5-x80.c",
5007 "src/f32-vscaleexpminusmax/gen/avx2-p5-x88.c",
5008 "src/f32-vscaleexpminusmax/gen/avx2-p5-x96.c",
5009 "src/f32-vscaleextexp/gen/avx2-p5-x8.c",
5010 "src/f32-vscaleextexp/gen/avx2-p5-x16.c",
5011 "src/f32-vscaleextexp/gen/avx2-p5-x24.c",
5012 "src/f32-vscaleextexp/gen/avx2-p5-x32.c",
5013 "src/f32-vscaleextexp/gen/avx2-p5-x40.c",
5014 "src/f32-vscaleextexp/gen/avx2-p5-x48.c",
5015 "src/f32-vscaleextexp/gen/avx2-p5-x56.c",
5016 "src/f32-vscaleextexp/gen/avx2-p5-x64.c",
5017 "src/f32-vscaleextexp/gen/avx2-p5-x72.c",
5018 "src/f32-vscaleextexp/gen/avx2-p5-x80.c",
5019 "src/f32-vscaleextexp/gen/avx2-p5-x88.c",
5020 "src/f32-vscaleextexp/gen/avx2-p5-x96.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07005021 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x8.c",
5022 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x16.c",
5023 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x24.c",
5024 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x32.c",
5025 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
5026 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x48.c",
5027 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x56.c",
5028 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x64.c",
5029 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x72.c",
5030 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x80.c",
5031 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x8.c",
5032 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x16.c",
5033 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x24.c",
5034 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x32.c",
5035 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x40.c",
5036 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x48.c",
5037 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x56.c",
5038 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x64.c",
5039 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x72.c",
5040 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x80.c",
5041 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x8.c",
5042 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x16.c",
5043 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x24.c",
5044 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x32.c",
5045 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x40.c",
5046 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x48.c",
5047 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x56.c",
5048 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x64.c",
5049 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x72.c",
5050 "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x80.c",
Marat Dukhanb7633f22020-11-20 16:34:56 -08005051 "src/math/exp-avx2-rr2-lut8-p3-perm.c",
5052 "src/math/exp-avx2-rr2-lut8-p4-perm.c",
5053 "src/math/exp-avx2-rr2-p5.c",
Marat Dukhande390d42020-11-29 19:32:18 -08005054 "src/math/expm1minus-avx2-rr1-lut4-p4-perm.c",
5055 "src/math/expm1minus-avx2-rr1-lut8-p4-perm.c",
5056 "src/math/expm1minus-avx2-rr1-lut16-p3-gather.c",
5057 "src/math/expm1minus-avx2-rr1-p6.c",
Frank Barcharde7223ee2020-12-04 19:04:01 -08005058 "src/math/expminus-avx2-rr2-p5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005059 "src/math/extexp-avx2-p5.c",
5060 "src/math/sigmoid-avx2-rr1-lut64-p2-gather-div.c",
5061 "src/math/sigmoid-avx2-rr1-lut64-p2-gather-nr1fma.c",
5062 "src/math/sigmoid-avx2-rr1-lut64-p2-gather-nr2fma.c",
5063 "src/math/sigmoid-avx2-rr1-lut64-p2-gather-nr2fma1adj.c",
5064 "src/math/sigmoid-avx2-rr1-p5-div.c",
5065 "src/math/sigmoid-avx2-rr1-p5-nr1fma.c",
5066 "src/math/sigmoid-avx2-rr1-p5-nr2fma.c",
5067 "src/math/sigmoid-avx2-rr2-lut64-p2-gather-div.c",
5068 "src/math/sigmoid-avx2-rr2-lut64-p2-gather-nr1fma.c",
5069 "src/math/sigmoid-avx2-rr2-lut64-p2-gather-nr2fma.c",
5070 "src/math/sigmoid-avx2-rr2-lut64-p2-gather-nr2fma1adj.c",
5071 "src/math/sigmoid-avx2-rr2-p5-div.c",
5072 "src/math/sigmoid-avx2-rr2-p5-nr1fma.c",
5073 "src/math/sigmoid-avx2-rr2-p5-nr2fma.c",
Marat Dukhan82286892021-06-04 17:27:27 -07005074 "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
5075 "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005076 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005077 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
5078 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan82286892021-06-04 17:27:27 -07005079 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005080 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005081 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
5082 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan82286892021-06-04 17:27:27 -07005083 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
5084 "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
5085 "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005086 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005087 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
5088 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan82286892021-06-04 17:27:27 -07005089 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005090 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005091 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
5092 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan82286892021-06-04 17:27:27 -07005093 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
Marat Dukhan0b043742021-06-02 18:29:11 -07005094 "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
5095 "src/qc8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
5096 "src/qc8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
5097 "src/qc8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
5098 "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
5099 "src/qc8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
Marat Dukhane06c8132021-06-03 08:59:11 -07005100 "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
5101 "src/qc8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
5102 "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005103 "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005104 "src/qs8-dwconv/gen/up8x9-minmax-gemmlowp-avx2-mul32.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005105 "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005106 "src/qs8-dwconv/gen/up8x25-minmax-gemmlowp-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005107 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005108 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
5109 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005110 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005111 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx2-mul16-vpmovsx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005112 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005113 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005114 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
5115 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005116 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005117 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx2-mul16-vpmovsx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005118 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx2-mul32.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005119 "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005120 "src/qs8-dwconv/gen/up24x9-minmax-gemmlowp-avx2-mul32.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005121 "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005122 "src/qs8-dwconv/gen/up24x25-minmax-gemmlowp-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005123 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005124 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
5125 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005126 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005127 "src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-avx2-mul16-vpmovsx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005128 "src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-avx2-mul32.c",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005129 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005130 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
5131 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005132 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
Marat Dukhan881ab022021-07-28 13:49:26 -07005133 "src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-avx2-mul16-vpmovsx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005134 "src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-avx2-mul32.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005135 "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
Marat Dukhan0b043742021-06-02 18:29:11 -07005136 "src/qs8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005137 "src/qs8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
Marat Dukhan0b043742021-06-02 18:29:11 -07005138 "src/qs8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005139 "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005140 "src/qs8-gemm/gen/3x8c8-minmax-gemmlowp-avx2.c",
Marat Dukhan0b043742021-06-02 18:29:11 -07005141 "src/qs8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005142 "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005143 "src/qs8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07005144 "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005145 "src/qs8-igemm/gen/3x8c8-minmax-gemmlowp-avx2.c",
Marat Dukhane6dc0b62020-09-08 23:57:14 -07005146 "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
5147 "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
5148 "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x24.c",
5149 "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x32.c",
5150 "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
5151 "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
5152 "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x24.c",
5153 "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x32.c",
Marat Dukhan09c312b2021-07-09 00:45:04 -07005154 "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
5155 "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
5156 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
5157 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
5158 "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
5159 "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
Marat Dukhan902ef7f2021-07-02 16:11:06 -07005160 "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
5161 "src/qu8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
5162 "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
5163 "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
5164 "src/qu8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
5165 "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
Marat Dukhan3eac69c2021-07-21 01:42:29 -07005166 "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
5167 "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
5168 "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
5169 "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07005170]
5171
Marat Dukhan2c724952021-07-27 18:46:30 -07005172PROD_AVX512F_MICROKERNEL_SRCS = [
5173 "src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
5174 "src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
5175 "src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
5176 "src/f32-gemm/gen/1x16-minmax-avx512f-broadcast.c",
5177 "src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
5178 "src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
5179 "src/f32-igemm/gen/7x16-minmax-avx512f-broadcast.c",
5180 "src/f32-prelu/gen/avx512f-2x16.c",
5181 "src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
5182 "src/f32-vbinary/gen/vaddc-minmax-avx512f-x32.c",
5183 "src/f32-vbinary/gen/vdiv-minmax-avx512f-x32.c",
5184 "src/f32-vbinary/gen/vdivc-minmax-avx512f-x32.c",
5185 "src/f32-vbinary/gen/vmax-avx512f-x32.c",
5186 "src/f32-vbinary/gen/vmaxc-avx512f-x32.c",
5187 "src/f32-vbinary/gen/vmin-avx512f-x32.c",
5188 "src/f32-vbinary/gen/vminc-avx512f-x32.c",
5189 "src/f32-vbinary/gen/vmul-minmax-avx512f-x32.c",
5190 "src/f32-vbinary/gen/vmulc-minmax-avx512f-x32.c",
5191 "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x32.c",
5192 "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x32.c",
5193 "src/f32-vbinary/gen/vsqrdiff-avx512f-x32.c",
5194 "src/f32-vbinary/gen/vsqrdiffc-avx512f-x32.c",
5195 "src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
5196 "src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
5197 "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
5198 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x64.c",
5199 "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
5200 "src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
5201 "src/f32-vrnd/gen/vrndd-avx512f-x16.c",
5202 "src/f32-vrnd/gen/vrndne-avx512f-x16.c",
5203 "src/f32-vrnd/gen/vrndu-avx512f-x16.c",
5204 "src/f32-vrnd/gen/vrndz-avx512f-x16.c",
5205 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
5206 "src/f32-vunary/gen/vabs-avx512f-x16.c",
5207 "src/f32-vunary/gen/vneg-avx512f-x16.c",
5208 "src/f32-vunary/gen/vsqr-avx512f-x16.c",
5209]
5210
5211ALL_AVX512F_MICROKERNEL_SRCS = [
Marat Dukhan1c587112020-04-08 20:04:28 -07005212 "src/f32-dwconv/gen/up16x4-minmax-avx512f-acc2.c",
5213 "src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07005214 "src/f32-dwconv/gen/up16x9-minmax-avx512f-acc2.c",
5215 "src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07005216 "src/f32-dwconv/gen/up16x25-minmax-avx512f-acc2.c",
5217 "src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005218 "src/f32-dwconv/gen/up32x4-minmax-avx512f-acc2.c",
5219 "src/f32-dwconv/gen/up32x4-minmax-avx512f.c",
5220 "src/f32-dwconv/gen/up32x9-minmax-avx512f-acc2.c",
5221 "src/f32-dwconv/gen/up32x9-minmax-avx512f.c",
5222 "src/f32-dwconv/gen/up32x25-minmax-avx512f-acc2.c",
5223 "src/f32-dwconv/gen/up32x25-minmax-avx512f.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07005224 "src/f32-gemm/gen-inc/1x16inc-minmax-avx512f-broadcast.c",
5225 "src/f32-gemm/gen-inc/4x16inc-minmax-avx512f-broadcast.c",
5226 "src/f32-gemm/gen-inc/5x16inc-minmax-avx512f-broadcast.c",
5227 "src/f32-gemm/gen-inc/6x16inc-minmax-avx512f-broadcast.c",
5228 "src/f32-gemm/gen-inc/7x16inc-minmax-avx512f-broadcast.c",
5229 "src/f32-gemm/gen-inc/8x16inc-minmax-avx512f-broadcast.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005230 "src/f32-gemm/gen/1x16-minmax-avx512f-broadcast.c",
5231 "src/f32-gemm/gen/4x16-minmax-avx512f-broadcast.c",
5232 "src/f32-gemm/gen/5x16-minmax-avx512f-broadcast.c",
5233 "src/f32-gemm/gen/6x16-minmax-avx512f-broadcast.c",
5234 "src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
5235 "src/f32-gemm/gen/8x16-minmax-avx512f-broadcast.c",
Marat Dukhan1c587112020-04-08 20:04:28 -07005236 "src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
5237 "src/f32-igemm/gen/4x16-minmax-avx512f-broadcast.c",
5238 "src/f32-igemm/gen/5x16-minmax-avx512f-broadcast.c",
5239 "src/f32-igemm/gen/6x16-minmax-avx512f-broadcast.c",
5240 "src/f32-igemm/gen/7x16-minmax-avx512f-broadcast.c",
5241 "src/f32-igemm/gen/8x16-minmax-avx512f-broadcast.c",
Marat Dukhan90eca0a2020-03-11 00:52:23 -07005242 "src/f32-prelu/gen/avx512f-2x16.c",
5243 "src/f32-prelu/gen/avx512f-2x32.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005244 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128-acc2.c",
5245 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005246 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005247 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x144-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005248 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x144.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005249 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160-acc2.c",
5250 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005251 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005252 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc2.c",
5253 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc3.c",
5254 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005255 "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005256 "src/f32-raddextexp/gen/avx512f-p5-scalef-x128-acc2.c",
5257 "src/f32-raddextexp/gen/avx512f-p5-scalef-x128-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005258 "src/f32-raddextexp/gen/avx512f-p5-scalef-x128.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005259 "src/f32-raddextexp/gen/avx512f-p5-scalef-x144-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005260 "src/f32-raddextexp/gen/avx512f-p5-scalef-x144.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005261 "src/f32-raddextexp/gen/avx512f-p5-scalef-x160-acc2.c",
5262 "src/f32-raddextexp/gen/avx512f-p5-scalef-x160-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005263 "src/f32-raddextexp/gen/avx512f-p5-scalef-x160.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005264 "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc2.c",
5265 "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc3.c",
5266 "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005267 "src/f32-raddextexp/gen/avx512f-p5-scalef-x192.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005268 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128-acc2.c",
5269 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128-acc4.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005270 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x128.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005271 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x144-acc3.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005272 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x144.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005273 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160-acc2.c",
5274 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160-acc5.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005275 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x160.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005276 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc2.c",
5277 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc3.c",
5278 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192-acc6.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005279 "src/f32-raddstoreexpminusmax/gen/avx512f-p5-scalef-x192.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005280 "src/f32-rmax/avx512f.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07005281 "src/f32-vbinary/gen/vadd-minmax-avx512f-x16.c",
5282 "src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
5283 "src/f32-vbinary/gen/vaddc-minmax-avx512f-x16.c",
5284 "src/f32-vbinary/gen/vaddc-minmax-avx512f-x32.c",
5285 "src/f32-vbinary/gen/vdiv-minmax-avx512f-x16.c",
5286 "src/f32-vbinary/gen/vdiv-minmax-avx512f-x32.c",
5287 "src/f32-vbinary/gen/vdivc-minmax-avx512f-x16.c",
5288 "src/f32-vbinary/gen/vdivc-minmax-avx512f-x32.c",
Marat Dukhan9a88efe2019-12-10 15:54:24 -08005289 "src/f32-vbinary/gen/vmax-avx512f-x16.c",
5290 "src/f32-vbinary/gen/vmax-avx512f-x32.c",
5291 "src/f32-vbinary/gen/vmaxc-avx512f-x16.c",
5292 "src/f32-vbinary/gen/vmaxc-avx512f-x32.c",
5293 "src/f32-vbinary/gen/vmin-avx512f-x16.c",
5294 "src/f32-vbinary/gen/vmin-avx512f-x32.c",
5295 "src/f32-vbinary/gen/vminc-avx512f-x16.c",
5296 "src/f32-vbinary/gen/vminc-avx512f-x32.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07005297 "src/f32-vbinary/gen/vmul-minmax-avx512f-x16.c",
5298 "src/f32-vbinary/gen/vmul-minmax-avx512f-x32.c",
5299 "src/f32-vbinary/gen/vmulc-minmax-avx512f-x16.c",
5300 "src/f32-vbinary/gen/vmulc-minmax-avx512f-x32.c",
5301 "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x16.c",
5302 "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x32.c",
5303 "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x16.c",
5304 "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x32.c",
Marat Dukhan13bafb02020-06-05 00:43:11 -07005305 "src/f32-vbinary/gen/vsqrdiff-avx512f-x16.c",
5306 "src/f32-vbinary/gen/vsqrdiff-avx512f-x32.c",
5307 "src/f32-vbinary/gen/vsqrdiffc-avx512f-x16.c",
5308 "src/f32-vbinary/gen/vsqrdiffc-avx512f-x32.c",
Marat Dukhan91cd2b72020-04-09 23:57:31 -07005309 "src/f32-vbinary/gen/vsub-minmax-avx512f-x16.c",
5310 "src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
5311 "src/f32-vbinary/gen/vsubc-minmax-avx512f-x16.c",
5312 "src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07005313 "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
5314 "src/f32-vclamp/gen/vclamp-avx512f-x32.c",
Marat Dukhaned6baaf2020-12-01 15:07:08 -08005315 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x16.c",
5316 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x32.c",
5317 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x48.c",
5318 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x64.c",
5319 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x80.c",
5320 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x96.c",
5321 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x112.c",
5322 "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x128.c",
5323 "src/f32-velu/gen/velu-avx512f-rr1-p6-x16.c",
5324 "src/f32-velu/gen/velu-avx512f-rr1-p6-x32.c",
5325 "src/f32-velu/gen/velu-avx512f-rr1-p6-x48.c",
5326 "src/f32-velu/gen/velu-avx512f-rr1-p6-x64.c",
5327 "src/f32-velu/gen/velu-avx512f-rr1-p6-x80.c",
5328 "src/f32-velu/gen/velu-avx512f-rr1-p6-x96.c",
5329 "src/f32-velu/gen/velu-avx512f-rr1-p6-x112.c",
5330 "src/f32-velu/gen/velu-avx512f-rr1-p6-x128.c",
Marat Dukhan6674d692021-05-05 22:27:00 -07005331 "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
5332 "src/f32-vhswish/gen/vhswish-avx512f-x32.c",
Marat Dukhan19dd91d2020-07-16 11:12:44 -07005333 "src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
5334 "src/f32-vlrelu/gen/vlrelu-avx512f-x32.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07005335 "src/f32-vrelu/gen/vrelu-avx512f-x16.c",
5336 "src/f32-vrelu/gen/vrelu-avx512f-x32.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005337 "src/f32-vrnd/gen/vrndd-avx512f-x16.c",
5338 "src/f32-vrnd/gen/vrndd-avx512f-x32.c",
5339 "src/f32-vrnd/gen/vrndne-avx512f-x16.c",
5340 "src/f32-vrnd/gen/vrndne-avx512f-x32.c",
5341 "src/f32-vrnd/gen/vrndu-avx512f-x16.c",
5342 "src/f32-vrnd/gen/vrndu-avx512f-x32.c",
5343 "src/f32-vrnd/gen/vrndz-avx512f-x16.c",
5344 "src/f32-vrnd/gen/vrndz-avx512f-x32.c",
Frank Barchardbeca6522020-10-30 22:34:35 -07005345 "src/f32-vscale/avx512f-x64.c",
Marat Dukhan4c4eb002019-12-08 21:27:49 -08005346 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x16.c",
5347 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x32.c",
5348 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x48.c",
5349 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x64.c",
5350 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x80.c",
5351 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x96.c",
5352 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x112.c",
5353 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x128.c",
5354 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x144.c",
5355 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x160.c",
5356 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x176.c",
5357 "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x192.c",
5358 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x16.c",
5359 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x32.c",
5360 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x48.c",
5361 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x64.c",
5362 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x80.c",
5363 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x96.c",
5364 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x112.c",
5365 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x128.c",
5366 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x144.c",
5367 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x160.c",
5368 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x176.c",
5369 "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x192.c",
Marat Dukhanb1eec082021-05-05 23:24:55 -07005370 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x16.c",
5371 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x32.c",
5372 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x48.c",
5373 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x64.c",
5374 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x80.c",
5375 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x96.c",
5376 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x112.c",
5377 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x128.c",
5378 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x16.c",
5379 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x32.c",
5380 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x48.c",
5381 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x64.c",
5382 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x80.c",
5383 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x96.c",
5384 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x112.c",
5385 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x128.c",
5386 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x16.c",
5387 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x32.c",
5388 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x48.c",
5389 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x64.c",
5390 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x80.c",
5391 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x96.c",
5392 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x112.c",
5393 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x128.c",
5394 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x16.c",
5395 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x32.c",
5396 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x48.c",
5397 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x64.c",
5398 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x80.c",
5399 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x96.c",
5400 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x112.c",
5401 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x128.c",
5402 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x16.c",
5403 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x32.c",
5404 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x48.c",
5405 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
5406 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x80.c",
5407 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x96.c",
5408 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x112.c",
5409 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x128.c",
5410 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x16.c",
5411 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x32.c",
5412 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x48.c",
5413 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x64.c",
5414 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x80.c",
5415 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x96.c",
5416 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x112.c",
5417 "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x128.c",
Marat Dukhanf4db2f32020-06-30 10:55:30 -07005418 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x16.c",
5419 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x32.c",
5420 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x48.c",
5421 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x64.c",
5422 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x80.c",
5423 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x96.c",
5424 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x112.c",
5425 "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x128.c",
Marat Dukhan5020b962020-06-08 13:30:10 -07005426 "src/f32-vunary/gen/vabs-avx512f-x16.c",
5427 "src/f32-vunary/gen/vabs-avx512f-x32.c",
5428 "src/f32-vunary/gen/vneg-avx512f-x16.c",
5429 "src/f32-vunary/gen/vneg-avx512f-x32.c",
5430 "src/f32-vunary/gen/vsqr-avx512f-x16.c",
5431 "src/f32-vunary/gen/vsqr-avx512f-x32.c",
Marat Dukhanb7633f22020-11-20 16:34:56 -08005432 "src/math/exp-avx512f-rr2-lut16-p3-perm-scalef.c",
5433 "src/math/exp-avx512f-rr2-lut16-p3-perm.c",
5434 "src/math/exp-avx512f-rr2-lut32-p2-perm2-scalef.c",
5435 "src/math/exp-avx512f-rr2-lut32-p2-perm2.c",
5436 "src/math/exp-avx512f-rr2-p5-scalef.c",
5437 "src/math/exp-avx512f-rr2-p5.c",
Marat Dukhande390d42020-11-29 19:32:18 -08005438 "src/math/expm1minus-avx512f-rr1-lut16-p3-perm.c",
5439 "src/math/expm1minus-avx512f-rr1-p6.c",
Marat Dukhan98ba4412019-10-23 02:14:28 -07005440 "src/math/extexp-avx512f-p5.c",
Marat Dukhan6a34c5f2020-09-22 21:44:15 -07005441 "src/math/sigmoid-avx512f-rr1-lut16-p3-perm-scalef-div.c",
Marat Dukhan6a34c5f2020-09-22 21:44:15 -07005442 "src/math/sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005443 "src/math/sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma1adj.c",
Marat Dukhan6a34c5f2020-09-22 21:44:15 -07005444 "src/math/sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-div.c",
Marat Dukhan6a34c5f2020-09-22 21:44:15 -07005445 "src/math/sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005446 "src/math/sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma1adj.c",
Marat Dukhan36173d22020-10-15 17:14:26 -07005447 "src/math/sigmoid-avx512f-rr1-lut64-p2-gather-scalef-div.c",
Marat Dukhan36173d22020-10-15 17:14:26 -07005448 "src/math/sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005449 "src/math/sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma1adj.c",
5450 "src/math/sigmoid-avx512f-rr1-p5-scalef-div.c",
5451 "src/math/sigmoid-avx512f-rr1-p5-scalef-nr1fma.c",
5452 "src/math/sigmoid-avx512f-rr1-p5-scalef-nr1fma1adj.c",
5453 "src/math/sigmoid-avx512f-rr2-lut16-p3-perm-scalef-div.c",
5454 "src/math/sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma.c",
5455 "src/math/sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma1adj.c",
5456 "src/math/sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div.c",
5457 "src/math/sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma.c",
5458 "src/math/sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma1adj.c",
Marat Dukhan36173d22020-10-15 17:14:26 -07005459 "src/math/sigmoid-avx512f-rr2-lut64-p2-gather-scalef-div.c",
Marat Dukhan36173d22020-10-15 17:14:26 -07005460 "src/math/sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005461 "src/math/sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma1adj.c",
5462 "src/math/sigmoid-avx512f-rr2-p5-scalef-div.c",
5463 "src/math/sigmoid-avx512f-rr2-p5-scalef-nr1fma.c",
5464 "src/math/sigmoid-avx512f-rr2-p5-scalef-nr1fma1adj.c",
Marat Dukhan84000762020-06-29 18:38:43 -07005465 "src/math/sqrt-avx512f-nr1fma.c",
Marat Dukhan84000762020-06-29 18:38:43 -07005466 "src/math/sqrt-avx512f-nr1fma1adj.c",
Frank Barchard04336c12020-10-22 16:48:55 -07005467 "src/math/sqrt-avx512f-nr2fma.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005468]
5469
Marat Dukhan2c724952021-07-27 18:46:30 -07005470PROD_AVX512SKX_MICROKERNEL_SRCS = [
5471 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
5472 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
5473 "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5474 "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5475 "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5476 "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5477 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
5478 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
5479 "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5480 "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5481 "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5482 "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5483 "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
5484 "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
5485 "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
5486 "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
5487 "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5488 "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5489 "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5490 "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5491 "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
5492 "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
5493]
5494
5495ALL_AVX512SKX_MICROKERNEL_SRCS = [
Marat Dukhan98042f22021-06-15 00:43:13 -07005496 "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
5497 "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
5498 "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
5499 "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
Marat Dukhanc3e3f1c2021-06-03 09:56:16 -07005500 "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5501 "src/qc8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
5502 "src/qc8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
5503 "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5504 "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5505 "src/qc8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
5506 "src/qc8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
5507 "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005508 "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005509 "src/qs8-dwconv/gen/up16x9-minmax-gemmlowp-avx512skx-mul32.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005510 "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005511 "src/qs8-dwconv/gen/up16x25-minmax-gemmlowp-avx512skx-mul32.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005512 "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005513 "src/qs8-dwconv/gen/up32x9-minmax-gemmlowp-avx512skx-mul32.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005514 "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005515 "src/qs8-dwconv/gen/up32x25-minmax-gemmlowp-avx512skx-mul32.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005516 "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005517 "src/qs8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005518 "src/qs8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005519 "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005520 "src/qs8-gemm/gen/4x16c8-minmax-gemmlowp-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005521 "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005522 "src/qs8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005523 "src/qs8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
Marat Dukhan71855ee2021-05-25 19:05:06 -07005524 "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
Frank Barchardd208bec2021-05-28 11:36:39 -07005525 "src/qs8-igemm/gen/4x16c8-minmax-gemmlowp-avx512skx.c",
Marat Dukhane76049a2021-07-22 14:48:59 -07005526 "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
5527 "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
5528 "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
5529 "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
Marat Dukhancfd606b2021-07-09 01:18:45 -07005530 "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
5531 "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
5532 "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
5533 "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
Marat Dukhan3cf2e222021-07-08 11:38:45 -07005534 "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5535 "src/qu8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
5536 "src/qu8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
5537 "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
5538 "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
5539 "src/qu8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
5540 "src/qu8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
5541 "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
Marat Dukhane76049a2021-07-22 14:48:59 -07005542 "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
5543 "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
5544 "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
5545 "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
Marat Dukhanbb00b1d2020-08-10 11:37:23 -07005546]
5547
Marat Dukhandb3b0a72021-07-27 08:58:01 -07005548WASM32_ASM_MICROKERNEL_SRCS = [
Marat Dukhan6674d692021-05-05 22:27:00 -07005549 "src/f32-vrelu/wasm_shr_x1.S",
5550 "src/f32-vrelu/wasm_shr_x2.S",
5551 "src/f32-vrelu/wasm_shr_x4.S",
Frank Barchardbcedc082020-08-17 18:00:51 -07005552]
5553
Marat Dukhandb3b0a72021-07-27 08:58:01 -07005554AARCH32_ASM_MICROKERNEL_SRCS = [
Marat Dukhan32f93812020-05-17 20:31:21 -07005555 "src/f32-gemm/4x4-aarch32-vfp-ld64.S",
Marat Dukhan3b98f6b2020-05-17 10:09:22 -07005556 "src/f32-gemm/4x4-minmax-aarch32-vfp-ld64.S",
Marat Dukhan1c587112020-04-08 20:04:28 -07005557 "src/f32-gemm/4x8-minmax-aarch32-neon-cortex-a53.S",
5558 "src/f32-gemm/4x8-minmax-aarch32-neon-cortex-a55.S",
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Frank Barchardd208bec2021-05-28 11:36:39 -07005713 "src/qs8-gemm/gen/2x8c8-minmax-gemmlowp-aarch64-neon-mull-padal.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005714 "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-cortex-a53.S",
5715 "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5716 "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm.S",
5717 "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal.S",
5718 "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mull-padal.S",
Frank Barchard1663c0c2021-07-01 11:20:06 -07005719 "src/qs8-gemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal-padal.S",
Frank Barchardd208bec2021-05-28 11:36:39 -07005720 "src/qs8-gemm/gen/2x8c16-minmax-gemmlowp-aarch64-neon-mlal-padal.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005721 "src/qs8-gemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal-padal.S",
Frank Barchard98af05c2021-06-30 12:15:04 -07005722 "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
5723 "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchardf10af6c2021-06-30 12:42:29 -07005724 "src/qs8-gemm/gen/4x16-minmax-gemmlowp-aarch64-neon-mlal-lane-cortex-a53.S",
5725 "src/qs8-gemm/gen/4x16-minmax-gemmlowp-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005726 "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
5727 "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchard1a0b2762021-06-29 18:37:59 -07005728 "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
5729 "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld32.S",
5730 "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
5731 "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
Frank Barchardd208bec2021-05-28 11:36:39 -07005732 "src/qs8-gemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-cortex-a55.S",
5733 "src/qs8-gemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-ld32.S",
5734 "src/qs8-gemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-ld64.S",
Frank Barchard0ae35f22021-06-15 17:34:24 -07005735 "src/qs8-gemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-ld128.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005736 "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
5737 "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld32.S",
5738 "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
Frank Barchard60729d02021-07-20 12:25:09 -07005739 "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
Frank Barchard960ae342021-07-01 11:31:11 -07005740 "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-padal-cortex-a53.S",
5741 "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5742 "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-padal-prfm.S",
5743 "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-padal.S",
Marat Dukhand65d20e2021-05-24 16:59:51 -07005744 "src/qs8-igemm/gen/1x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-cortex-a53.S",
5745 "src/qs8-igemm/gen/1x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5746 "src/qs8-igemm/gen/1x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-prfm.S",
5747 "src/qs8-igemm/gen/1x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005748 "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-padal-cortex-a53.S",
5749 "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5750 "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm.S",
5751 "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-padal.S",
Frank Barchard960ae342021-07-01 11:31:11 -07005752 "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-padal-cortex-a53.S",
5753 "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5754 "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-padal-prfm.S",
5755 "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-padal.S",
Marat Dukhand65d20e2021-05-24 16:59:51 -07005756 "src/qs8-igemm/gen/2x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-cortex-a53.S",
5757 "src/qs8-igemm/gen/2x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5758 "src/qs8-igemm/gen/2x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal-prfm.S",
5759 "src/qs8-igemm/gen/2x8c8-minmax-gemmlowp-aarch64-neon-mlal-padal.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005760 "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-cortex-a53.S",
5761 "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm-cortex-a53.S",
5762 "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal-prfm.S",
5763 "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-padal.S",
Frank Barchard1663c0c2021-07-01 11:20:06 -07005764 "src/qs8-igemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal-padal.S",
Frank Barchardd208bec2021-05-28 11:36:39 -07005765 "src/qs8-igemm/gen/2x8c16-minmax-gemmlowp-aarch64-neon-mlal-padal.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005766 "src/qs8-igemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal-padal.S",
Frank Barchard98af05c2021-06-30 12:15:04 -07005767 "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
5768 "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchardf10af6c2021-06-30 12:42:29 -07005769 "src/qs8-igemm/gen/4x16-minmax-gemmlowp-aarch64-neon-mlal-lane-cortex-a53.S",
5770 "src/qs8-igemm/gen/4x16-minmax-gemmlowp-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005771 "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
5772 "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchard1a0b2762021-06-29 18:37:59 -07005773 "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
5774 "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
5775 "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
Frank Barchardd208bec2021-05-28 11:36:39 -07005776 "src/qs8-igemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-cortex-a55.S",
5777 "src/qs8-igemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-ld64.S",
Frank Barchard0ae35f22021-06-15 17:34:24 -07005778 "src/qs8-igemm/gen/4x16c4-minmax-gemmlowp-aarch64-neondot-ld128.S",
Frank Barchard13db60f2021-07-20 14:34:35 -07005779 "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
5780 "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
Frank Barchard60729d02021-07-20 12:25:09 -07005781 "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
Frank Barchardca4c68e2021-08-25 19:06:40 -07005782 "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
Frank Barcharddf8e6042021-09-03 13:56:29 -07005783 "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005784 "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
Frank Barchardfb3a94f2021-08-02 20:37:06 -07005785 "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005786 "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchardfb3a94f2021-08-02 20:37:06 -07005787 "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
Frank Barcharda49e41f2021-08-31 20:30:24 -07005788 "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
Frank Barchard0c764222021-08-24 16:13:06 -07005789 "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
Frank Barchardca4c68e2021-08-25 19:06:40 -07005790 "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
Frank Barcharddf8e6042021-09-03 13:56:29 -07005791 "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005792 "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
Frank Barchardfb3a94f2021-08-02 20:37:06 -07005793 "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
Frank Barchard59ed1da2021-08-02 11:34:59 -07005794 "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
Frank Barchardfb3a94f2021-08-02 20:37:06 -07005795 "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
Frank Barcharda49e41f2021-08-31 20:30:24 -07005796 "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
Frank Barchard0c764222021-08-24 16:13:06 -07005797 "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005798]
5799
Marat Dukhan1b354632020-03-23 12:50:22 -07005800INTERNAL_MICROKERNEL_HDRS = [
Marat Dukhan08c4a432019-10-03 09:29:21 -07005801 "src/xnnpack/argmaxpool.h",
5802 "src/xnnpack/avgpool.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005803 "src/xnnpack/common.h",
5804 "src/xnnpack/conv.h",
Yury Kartynnike7841862020-11-04 18:22:18 -08005805 "src/xnnpack/depthtospace.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005806 "src/xnnpack/dwconv.h",
Frank Barchard04336c12020-10-22 16:48:55 -07005807 "src/xnnpack/fill.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005808 "src/xnnpack/gavgpool.h",
5809 "src/xnnpack/gemm.h",
Marat Dukhan660fd192020-03-10 04:55:30 -07005810 "src/xnnpack/ibilinear.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005811 "src/xnnpack/igemm.h",
Marat Dukhancfb31342019-12-05 10:42:57 -08005812 "src/xnnpack/intrinsics-polyfill.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005813 "src/xnnpack/lut.h",
5814 "src/xnnpack/math.h",
5815 "src/xnnpack/maxpool.h",
5816 "src/xnnpack/packx.h",
5817 "src/xnnpack/pad.h",
5818 "src/xnnpack/params.h",
5819 "src/xnnpack/pavgpool.h",
5820 "src/xnnpack/ppmm.h",
5821 "src/xnnpack/prelu.h",
Marat Dukhan97579532019-10-18 16:40:39 -07005822 "src/xnnpack/raddexpminusmax.h",
Marat Dukhan6f8d4d32019-10-25 17:07:09 -07005823 "src/xnnpack/raddextexp.h",
Marat Dukhan97579532019-10-18 16:40:39 -07005824 "src/xnnpack/raddstoreexpminusmax.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005825 "src/xnnpack/rmax.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005826 "src/xnnpack/spmm.h",
5827 "src/xnnpack/unpool.h",
Marat Dukhan64287252021-09-07 16:20:03 -07005828 "src/xnnpack/vaddsub.h",
Marat Dukhan1e782c42019-11-21 17:02:40 -08005829 "src/xnnpack/vbinary.h",
Marat Dukhana212eac2021-08-02 09:58:04 -07005830 "src/xnnpack/vmul.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005831 "src/xnnpack/vmulcaddc.h",
Marat Dukhan05ac8e32019-10-21 15:39:33 -07005832 "src/xnnpack/vscale.h",
Marat Dukhan97579532019-10-18 16:40:39 -07005833 "src/xnnpack/vscaleexpminusmax.h",
Marat Dukhan6f8d4d32019-10-25 17:07:09 -07005834 "src/xnnpack/vscaleextexp.h",
Marat Dukhan1e782c42019-11-21 17:02:40 -08005835 "src/xnnpack/vunary.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005836 "src/xnnpack/zip.h",
Marat Dukhan1b354632020-03-23 12:50:22 -07005837]
5838
5839INTERNAL_HDRS = INTERNAL_MICROKERNEL_HDRS + [
Marat Dukhan08c4a432019-10-03 09:29:21 -07005840 "include/xnnpack.h",
5841 "src/xnnpack/allocator.h",
5842 "src/xnnpack/compute.h",
5843 "src/xnnpack/im2col.h",
5844 "src/xnnpack/indirection.h",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07005845 "src/xnnpack/math-stubs.h",
Chao Mei6ddfc602020-05-13 22:29:36 -07005846 "src/xnnpack/memory-planner.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005847 "src/xnnpack/operator.h",
5848 "src/xnnpack/pack.h",
Marat Dukhaneeaa7bd2019-10-25 17:31:25 -07005849 "src/xnnpack/params-init.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005850 "src/xnnpack/requantization-stubs.h",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07005851 "src/xnnpack/requantization.h",
Marat Dukhan1d75a542020-02-03 12:23:01 -08005852 "src/xnnpack/subgraph.h",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07005853]
5854
Marat Dukhan1b354632020-03-23 12:50:22 -07005855ACCURACY_EVAL_HDRS = INTERNAL_MICROKERNEL_HDRS + [
Marat Dukhan6adff4e2019-10-14 18:32:07 -07005856 "src/xnnpack/math-stubs.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005857]
5858
Marat Dukhan1b354632020-03-23 12:50:22 -07005859MICROKERNEL_BENCHMARK_HDRS = INTERNAL_MICROKERNEL_HDRS + [
Marat Dukhan08c4a432019-10-03 09:29:21 -07005860 "include/xnnpack.h",
Frank Barchard35db7d02020-10-26 13:37:34 -07005861 "src/xnnpack/params-init.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005862]
5863
Marat Dukhan1b354632020-03-23 12:50:22 -07005864MICROKERNEL_TEST_HDRS = INTERNAL_MICROKERNEL_HDRS + [
Frank Barchard35db7d02020-10-26 13:37:34 -07005865 "include/xnnpack.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005866 "src/xnnpack/isa-checks.h",
Marat Dukhaneeaa7bd2019-10-25 17:31:25 -07005867 "src/xnnpack/params-init.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005868 "src/xnnpack/requantization.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005869]
5870
5871OPERATOR_TEST_PARAMS_HDRS = [
Marat Dukhan08c4a432019-10-03 09:29:21 -07005872 "src/xnnpack/common.h",
Frank Barchard04336c12020-10-22 16:48:55 -07005873 "src/xnnpack/params.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005874]
5875
5876WEIGHTS_PACK_HDRS = [
Marat Dukhan08c4a432019-10-03 09:29:21 -07005877 "src/xnnpack/compute.h",
Frank Barchard04336c12020-10-22 16:48:55 -07005878 "src/xnnpack/operator.h",
5879 "src/xnnpack/pack.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005880]
5881
Marat Dukhanc8e00eb2019-10-04 14:55:26 -07005882LOGGING_COPTS = select({
5883 # No logging in optimized mode
5884 ":optimized_build": ["-DXNN_LOG_LEVEL=0"],
5885 # Full logging in debug mode
5886 ":debug_build": ["-DXNN_LOG_LEVEL=5"],
5887 # Error-only logging in default (fastbuild) mode
5888 "//conditions:default": ["-DXNN_LOG_LEVEL=2"],
5889})
5890
Marat Dukhan3b59de22020-06-03 20:15:19 -07005891LOGGING_SRCS = select({
5892 # No logging in optimized mode
5893 ":optimized_build": [],
5894 "//conditions:default": [
Marat Dukhanccd3a1d2021-03-29 16:03:12 -07005895 "src/datatype-strings.c",
Marat Dukhan3b59de22020-06-03 20:15:19 -07005896 "src/operator-strings.c",
5897 "src/subgraph-strings.c",
5898 ],
5899})
5900
Marat Dukhanc8e00eb2019-10-04 14:55:26 -07005901LOGGING_HDRS = [
5902 "src/xnnpack/log.h",
5903]
5904
Marat Dukhan08c4a432019-10-03 09:29:21 -07005905xnnpack_cc_library(
Marat Dukhan3a77ea72019-12-23 12:10:24 -08005906 name = "tables",
5907 srcs = TABLE_SRCS,
5908 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07005909 gcc_copts = xnnpack_gcc_std_copts(),
5910 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan3a77ea72019-12-23 12:10:24 -08005911)
5912
5913xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07005914 name = "scalar_bench_microkernels",
5915 srcs = ALL_SCALAR_MICROKERNEL_SRCS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07005916 hdrs = INTERNAL_HDRS,
5917 aarch32_copts = ["-marm"],
Marat Dukhan10a38082020-04-17 03:58:35 -07005918 gcc_copts = xnnpack_gcc_std_copts(),
5919 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07005920 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08005921 ":tables",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005922 "@FP16",
5923 "@FXdiv",
Marat Dukhan04f03be2019-11-19 12:36:47 -08005924 "@pthreadpool",
Marat Dukhan08c4a432019-10-03 09:29:21 -07005925 ],
5926)
5927
5928xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07005929 name = "scalar_prod_microkernels",
5930 srcs = PROD_SCALAR_MICROKERNEL_SRCS,
5931 hdrs = INTERNAL_HDRS,
5932 aarch32_copts = ["-marm"],
5933 gcc_copts = xnnpack_gcc_std_copts(),
5934 msvc_copts = xnnpack_msvc_std_copts(),
5935 deps = [
5936 ":tables",
5937 "@FP16",
5938 "@FXdiv",
5939 "@pthreadpool",
5940 ],
5941)
5942
5943xnnpack_cc_library(
5944 name = "scalar_test_microkernels",
5945 srcs = ALL_SCALAR_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07005946 hdrs = INTERNAL_HDRS,
5947 aarch32_copts = ["-marm"],
5948 copts = [
5949 "-UNDEBUG",
5950 "-DXNN_TEST_MODE=1",
5951 ],
5952 gcc_copts = xnnpack_gcc_std_copts(),
5953 msvc_copts = xnnpack_msvc_std_copts(),
5954 deps = [
5955 ":tables",
5956 "@FP16",
5957 "@FXdiv",
5958 "@pthreadpool",
5959 ],
5960)
5961
5962xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07005963 name = "wasm_bench_microkernels",
Marat Dukhan436ebe62019-12-04 15:10:12 -08005964 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07005965 gcc_copts = xnnpack_gcc_std_copts(),
5966 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan2c724952021-07-27 18:46:30 -07005967 wasm_srcs = ALL_WASM_MICROKERNEL_SRCS,
5968 wasmsimd_srcs = ALL_WASM_MICROKERNEL_SRCS + ALL_WASMSIMD_MICROKERNEL_SRCS,
Marat Dukhan436ebe62019-12-04 15:10:12 -08005969 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08005970 ":tables",
Marat Dukhan436ebe62019-12-04 15:10:12 -08005971 "@FP16",
5972 "@FXdiv",
5973 "@pthreadpool",
5974 ],
5975)
5976
5977xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07005978 name = "wasm_prod_microkernels",
5979 hdrs = INTERNAL_HDRS,
5980 gcc_copts = xnnpack_gcc_std_copts(),
5981 msvc_copts = xnnpack_msvc_std_copts(),
5982 wasm_srcs = ALL_WASM_MICROKERNEL_SRCS,
5983 wasmsimd_srcs = ALL_WASM_MICROKERNEL_SRCS + ALL_WASMSIMD_MICROKERNEL_SRCS,
5984 deps = [
5985 ":tables",
5986 "@FP16",
5987 "@FXdiv",
5988 "@pthreadpool",
5989 ],
5990)
5991
5992xnnpack_cc_library(
5993 name = "wasm_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07005994 hdrs = INTERNAL_HDRS,
5995 copts = [
5996 "-UNDEBUG",
5997 "-DXNN_TEST_MODE=1",
5998 ],
5999 gcc_copts = xnnpack_gcc_std_copts(),
6000 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan2c724952021-07-27 18:46:30 -07006001 wasm_srcs = ALL_WASM_MICROKERNEL_SRCS,
6002 wasmsimd_srcs = ALL_WASM_MICROKERNEL_SRCS + ALL_WASMSIMD_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006003 deps = [
6004 ":tables",
6005 "@FP16",
6006 "@FXdiv",
6007 "@pthreadpool",
6008 ],
6009)
6010
6011xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006012 name = "neon_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006013 hdrs = INTERNAL_HDRS,
6014 aarch32_copts = [
6015 "-marm",
Marat Dukhan8853b822020-05-07 12:19:01 -07006016 "-march=armv7-a",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006017 "-mfpu=neon",
6018 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006019 aarch32_srcs = ALL_NEON_MICROKERNEL_SRCS,
6020 aarch64_srcs = ALL_NEON_MICROKERNEL_SRCS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006021 gcc_copts = xnnpack_gcc_std_copts(),
6022 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan04f03be2019-11-19 12:36:47 -08006023 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006024 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006025 "@FP16",
6026 "@pthreadpool",
6027 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006028)
6029
6030xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006031 name = "neon_prod_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006032 hdrs = INTERNAL_HDRS,
6033 aarch32_copts = [
6034 "-marm",
6035 "-march=armv7-a",
6036 "-mfpu=neon",
6037 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006038 aarch32_srcs = PROD_NEON_MICROKERNEL_SRCS,
6039 aarch64_srcs = PROD_NEON_MICROKERNEL_SRCS,
6040 gcc_copts = xnnpack_gcc_std_copts(),
6041 msvc_copts = xnnpack_msvc_std_copts(),
6042 deps = [
6043 ":tables",
6044 "@FP16",
6045 "@pthreadpool",
6046 ],
6047)
6048
6049xnnpack_cc_library(
6050 name = "neon_test_microkernels",
6051 hdrs = INTERNAL_HDRS,
6052 aarch32_copts = [
6053 "-marm",
6054 "-march=armv7-a",
6055 "-mfpu=neon",
6056 ],
6057 aarch32_srcs = ALL_NEON_MICROKERNEL_SRCS,
6058 aarch64_srcs = ALL_NEON_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006059 copts = [
6060 "-UNDEBUG",
6061 "-DXNN_TEST_MODE=1",
6062 ],
6063 gcc_copts = xnnpack_gcc_std_copts(),
6064 msvc_copts = xnnpack_msvc_std_copts(),
6065 deps = [
6066 ":tables",
6067 "@FP16",
6068 "@pthreadpool",
6069 ],
6070)
6071
6072xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006073 name = "neonfma_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006074 hdrs = INTERNAL_HDRS,
6075 aarch32_copts = [
6076 "-marm",
Marat Dukhan8853b822020-05-07 12:19:01 -07006077 "-march=armv7-a",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006078 "-mfpu=neon-vfpv4",
6079 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006080 aarch32_srcs = ALL_NEONFMA_MICROKERNEL_SRCS,
6081 aarch64_srcs = ALL_NEONFMA_MICROKERNEL_SRCS + ALL_AARCH64_NEONFMA_MICROKERNEL_SRCS,
Marat Dukhanbc69ed62020-06-09 21:34:56 -07006082 apple_aarch32_copts = [
6083 "-mcpu=swift",
6084 "-mtune=generic",
6085 ],
Marat Dukhan10a38082020-04-17 03:58:35 -07006086 gcc_copts = xnnpack_gcc_std_copts(),
6087 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan04f03be2019-11-19 12:36:47 -08006088 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006089 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006090 "@FP16",
6091 "@pthreadpool",
6092 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006093)
6094
6095xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006096 name = "neonfma_prod_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006097 hdrs = INTERNAL_HDRS,
6098 aarch32_copts = [
6099 "-marm",
6100 "-march=armv7-a",
6101 "-mfpu=neon-vfpv4",
6102 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006103 aarch32_srcs = PROD_NEONFMA_MICROKERNEL_SRCS,
6104 aarch64_srcs = PROD_NEONFMA_MICROKERNEL_SRCS + PROD_AARCH64_NEONFMA_MICROKERNEL_SRCS,
6105 apple_aarch32_copts = [
6106 "-mcpu=swift",
6107 "-mtune=generic",
6108 ],
6109 gcc_copts = xnnpack_gcc_std_copts(),
6110 msvc_copts = xnnpack_msvc_std_copts(),
6111 deps = [
6112 ":tables",
6113 "@FP16",
6114 "@pthreadpool",
6115 ],
6116)
6117
6118xnnpack_cc_library(
6119 name = "neonfma_test_microkernels",
6120 hdrs = INTERNAL_HDRS,
6121 aarch32_copts = [
6122 "-marm",
6123 "-march=armv7-a",
6124 "-mfpu=neon-vfpv4",
6125 ],
6126 aarch32_srcs = ALL_NEONFMA_MICROKERNEL_SRCS,
6127 aarch64_srcs = ALL_NEONFMA_MICROKERNEL_SRCS + ALL_AARCH64_NEONFMA_MICROKERNEL_SRCS,
Marat Dukhanbc69ed62020-06-09 21:34:56 -07006128 apple_aarch32_copts = [
6129 "-mcpu=swift",
6130 "-mtune=generic",
6131 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07006132 copts = [
6133 "-UNDEBUG",
6134 "-DXNN_TEST_MODE=1",
6135 ],
6136 gcc_copts = xnnpack_gcc_std_copts(),
6137 msvc_copts = xnnpack_msvc_std_copts(),
6138 deps = [
6139 ":tables",
6140 "@FP16",
6141 "@pthreadpool",
6142 ],
6143)
6144
6145xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006146 name = "neonv8_bench_microkernels",
Marat Dukhan8853b822020-05-07 12:19:01 -07006147 hdrs = INTERNAL_HDRS,
6148 aarch32_copts = [
6149 "-marm",
6150 "-march=armv8-a",
6151 "-mfpu=neon-fp-armv8",
6152 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006153 aarch32_srcs = ALL_NEONV8_MICROKERNEL_SRCS,
6154 aarch64_srcs = ALL_NEONV8_MICROKERNEL_SRCS,
Marat Dukhanbc69ed62020-06-09 21:34:56 -07006155 apple_aarch32_copts = [
6156 "-mcpu=cyclone",
6157 "-mtune=generic",
6158 ],
Marat Dukhan8853b822020-05-07 12:19:01 -07006159 gcc_copts = xnnpack_gcc_std_copts(),
6160 msvc_copts = xnnpack_msvc_std_copts(),
6161 deps = [
6162 ":tables",
6163 "@FP16",
6164 "@pthreadpool",
6165 ],
6166)
6167
6168xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006169 name = "neonv8_prod_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006170 hdrs = INTERNAL_HDRS,
6171 aarch32_copts = [
6172 "-marm",
6173 "-march=armv8-a",
6174 "-mfpu=neon-fp-armv8",
6175 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006176 aarch32_srcs = PROD_NEONV8_MICROKERNEL_SRCS,
6177 aarch64_srcs = PROD_NEONV8_MICROKERNEL_SRCS,
6178 apple_aarch32_copts = [
6179 "-mcpu=cyclone",
6180 "-mtune=generic",
6181 ],
6182 gcc_copts = xnnpack_gcc_std_copts(),
6183 msvc_copts = xnnpack_msvc_std_copts(),
6184 deps = [
6185 ":tables",
6186 "@FP16",
6187 "@pthreadpool",
6188 ],
6189)
6190
6191xnnpack_cc_library(
6192 name = "neonv8_test_microkernels",
6193 hdrs = INTERNAL_HDRS,
6194 aarch32_copts = [
6195 "-marm",
6196 "-march=armv8-a",
6197 "-mfpu=neon-fp-armv8",
6198 ],
6199 aarch32_srcs = ALL_NEONV8_MICROKERNEL_SRCS,
6200 aarch64_srcs = ALL_NEONV8_MICROKERNEL_SRCS,
Marat Dukhanbc69ed62020-06-09 21:34:56 -07006201 apple_aarch32_copts = [
6202 "-mcpu=cyclone",
6203 "-mtune=generic",
6204 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07006205 copts = [
6206 "-UNDEBUG",
6207 "-DXNN_TEST_MODE=1",
6208 ],
6209 gcc_copts = xnnpack_gcc_std_copts(),
6210 msvc_copts = xnnpack_msvc_std_copts(),
6211 deps = [
6212 ":tables",
6213 "@FP16",
6214 "@pthreadpool",
6215 ],
6216)
6217
6218xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006219 name = "neonfp16arith_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006220 hdrs = INTERNAL_HDRS,
6221 aarch64_copts = ["-march=armv8.2-a+fp16"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006222 aarch64_srcs = ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006223 gcc_copts = xnnpack_gcc_std_copts(),
6224 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan04f03be2019-11-19 12:36:47 -08006225 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006226 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006227 "@FP16",
6228 "@pthreadpool",
6229 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006230)
6231
6232xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006233 name = "neonfp16arith_prod_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006234 hdrs = INTERNAL_HDRS,
6235 aarch64_copts = ["-march=armv8.2-a+fp16"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006236 aarch64_srcs = PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
6237 gcc_copts = xnnpack_gcc_std_copts(),
6238 msvc_copts = xnnpack_msvc_std_copts(),
6239 deps = [
6240 ":tables",
6241 "@FP16",
6242 "@pthreadpool",
6243 ],
6244)
6245
6246xnnpack_cc_library(
6247 name = "neonfp16arith_test_microkernels",
6248 hdrs = INTERNAL_HDRS,
6249 aarch64_copts = ["-march=armv8.2-a+fp16"],
6250 aarch64_srcs = ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006251 copts = [
6252 "-UNDEBUG",
6253 "-DXNN_TEST_MODE=1",
6254 ],
6255 gcc_copts = xnnpack_gcc_std_copts(),
6256 msvc_copts = xnnpack_msvc_std_copts(),
6257 deps = [
6258 ":tables",
6259 "@FP16",
6260 "@pthreadpool",
6261 ],
6262)
6263
6264xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006265 name = "neondot_bench_microkernels",
Benoit Jacoba9644732020-08-13 12:48:55 -07006266 hdrs = INTERNAL_HDRS,
Marat Dukhan799ac752020-08-13 16:08:03 -07006267 aarch32_copts = [
6268 "-marm",
6269 "-march=armv8.2-a+dotprod",
6270 "-mfpu=neon-fp-armv8",
6271 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006272 aarch32_srcs = ALL_NEONDOT_MICROKERNEL_SRCS,
Benoit Jacoba9644732020-08-13 12:48:55 -07006273 aarch64_copts = ["-march=armv8.2-a+dotprod"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006274 aarch64_srcs = ALL_NEONDOT_MICROKERNEL_SRCS,
Benoit Jacoba9644732020-08-13 12:48:55 -07006275 gcc_copts = xnnpack_gcc_std_copts(),
6276 msvc_copts = xnnpack_msvc_std_copts(),
6277 deps = [
6278 ":tables",
6279 "@FP16",
6280 "@pthreadpool",
6281 ],
6282)
6283
6284xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006285 name = "neondot_prod_microkernels",
Benoit Jacoba9644732020-08-13 12:48:55 -07006286 hdrs = INTERNAL_HDRS,
Marat Dukhan799ac752020-08-13 16:08:03 -07006287 aarch32_copts = [
6288 "-marm",
6289 "-march=armv8.2-a+dotprod",
6290 "-mfpu=neon-fp-armv8",
6291 ],
Marat Dukhan2c724952021-07-27 18:46:30 -07006292 aarch32_srcs = PROD_NEONDOT_MICROKERNEL_SRCS,
Benoit Jacoba9644732020-08-13 12:48:55 -07006293 aarch64_copts = ["-march=armv8.2-a+dotprod"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006294 aarch64_srcs = PROD_NEONDOT_MICROKERNEL_SRCS,
6295 gcc_copts = xnnpack_gcc_std_copts(),
6296 msvc_copts = xnnpack_msvc_std_copts(),
6297 deps = [
6298 ":tables",
6299 "@FP16",
6300 "@pthreadpool",
6301 ],
6302)
6303
6304xnnpack_cc_library(
6305 name = "neondot_test_microkernels",
6306 hdrs = INTERNAL_HDRS,
6307 aarch32_copts = [
6308 "-marm",
6309 "-march=armv8.2-a+dotprod",
6310 "-mfpu=neon-fp-armv8",
6311 ],
6312 aarch32_srcs = ALL_NEONDOT_MICROKERNEL_SRCS,
6313 aarch64_copts = ["-march=armv8.2-a+dotprod"],
6314 aarch64_srcs = ALL_NEONDOT_MICROKERNEL_SRCS,
Benoit Jacoba9644732020-08-13 12:48:55 -07006315 copts = [
6316 "-UNDEBUG",
6317 "-DXNN_TEST_MODE=1",
6318 ],
6319 gcc_copts = xnnpack_gcc_std_copts(),
6320 msvc_copts = xnnpack_msvc_std_copts(),
6321 deps = [
6322 ":tables",
6323 "@FP16",
6324 "@pthreadpool",
6325 ],
6326)
6327
6328xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006329 name = "sse2_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006330 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006331 gcc_copts = xnnpack_gcc_std_copts(),
6332 gcc_x86_copts = ["-msse2"],
6333 msvc_copts = xnnpack_msvc_std_copts(),
6334 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006335 x86_srcs = ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
Marat Dukhan04f03be2019-11-19 12:36:47 -08006336 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006337 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006338 "@FP16",
6339 "@pthreadpool",
6340 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006341)
6342
6343xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006344 name = "sse2_prod_microkernels",
6345 hdrs = INTERNAL_HDRS,
6346 gcc_copts = xnnpack_gcc_std_copts(),
6347 gcc_x86_copts = ["-msse2"],
6348 msvc_copts = xnnpack_msvc_std_copts(),
6349 msvc_x86_32_copts = ["/arch:SSE2"],
6350 x86_srcs = PROD_SSE_MICROKERNEL_SRCS + PROD_SSE2_MICROKERNEL_SRCS,
6351 deps = [
6352 ":tables",
6353 "@FP16",
6354 "@pthreadpool",
6355 ],
6356)
6357
6358xnnpack_cc_library(
6359 name = "sse2_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006360 hdrs = INTERNAL_HDRS,
6361 copts = [
6362 "-UNDEBUG",
6363 "-DXNN_TEST_MODE=1",
6364 ],
6365 gcc_copts = xnnpack_gcc_std_copts(),
6366 gcc_x86_copts = ["-msse2"],
6367 msvc_copts = xnnpack_msvc_std_copts(),
6368 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006369 x86_srcs = ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006370 deps = [
6371 ":tables",
6372 "@FP16",
6373 "@pthreadpool",
6374 ],
6375)
6376
6377xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006378 name = "ssse3_bench_microkernels",
Marat Dukhanfe7acb62020-03-09 19:30:05 -07006379 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006380 gcc_copts = xnnpack_gcc_std_copts(),
6381 gcc_x86_copts = ["-mssse3"],
6382 msvc_copts = xnnpack_msvc_std_copts(),
6383 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006384 x86_srcs = ALL_SSSE3_MICROKERNEL_SRCS,
Marat Dukhanfe7acb62020-03-09 19:30:05 -07006385 deps = [
6386 ":tables",
6387 "@FP16",
6388 "@pthreadpool",
6389 ],
6390)
6391
6392xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006393 name = "ssse3_prod_microkernels",
6394 hdrs = INTERNAL_HDRS,
6395 gcc_copts = xnnpack_gcc_std_copts(),
6396 gcc_x86_copts = ["-mssse3"],
6397 msvc_copts = xnnpack_msvc_std_copts(),
6398 msvc_x86_32_copts = ["/arch:SSE2"],
6399 x86_srcs = PROD_SSSE3_MICROKERNEL_SRCS,
6400 deps = [
6401 ":tables",
6402 "@FP16",
6403 "@pthreadpool",
6404 ],
6405)
6406
6407xnnpack_cc_library(
6408 name = "ssse3_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006409 hdrs = INTERNAL_HDRS,
6410 copts = [
6411 "-UNDEBUG",
6412 "-DXNN_TEST_MODE=1",
6413 ],
6414 gcc_copts = xnnpack_gcc_std_copts(),
6415 gcc_x86_copts = ["-mssse3"],
6416 msvc_copts = xnnpack_msvc_std_copts(),
6417 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006418 x86_srcs = ALL_SSSE3_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006419 deps = [
6420 ":tables",
6421 "@FP16",
6422 "@pthreadpool",
6423 ],
6424)
6425
6426xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006427 name = "sse41_bench_microkernels",
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08006428 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006429 gcc_copts = xnnpack_gcc_std_copts(),
6430 gcc_x86_copts = ["-msse4.1"],
6431 msvc_copts = xnnpack_msvc_std_copts(),
6432 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006433 x86_srcs = ALL_SSE41_MICROKERNEL_SRCS,
Marat Dukhan04f03be2019-11-19 12:36:47 -08006434 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006435 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006436 "@FP16",
6437 "@pthreadpool",
6438 ],
Marat Dukhan69c3f2c2019-11-06 12:30:01 -08006439)
6440
6441xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006442 name = "sse41_prod_microkernels",
6443 hdrs = INTERNAL_HDRS,
6444 gcc_copts = xnnpack_gcc_std_copts(),
6445 gcc_x86_copts = ["-msse4.1"],
6446 msvc_copts = xnnpack_msvc_std_copts(),
6447 msvc_x86_32_copts = ["/arch:SSE2"],
6448 x86_srcs = PROD_SSE41_MICROKERNEL_SRCS,
6449 deps = [
6450 ":tables",
6451 "@FP16",
6452 "@pthreadpool",
6453 ],
6454)
6455
6456xnnpack_cc_library(
6457 name = "sse41_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006458 hdrs = INTERNAL_HDRS,
6459 copts = [
6460 "-UNDEBUG",
6461 "-DXNN_TEST_MODE=1",
6462 ],
6463 gcc_copts = xnnpack_gcc_std_copts(),
6464 gcc_x86_copts = ["-msse4.1"],
6465 msvc_copts = xnnpack_msvc_std_copts(),
6466 msvc_x86_32_copts = ["/arch:SSE2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006467 x86_srcs = ALL_SSE41_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006468 deps = [
6469 ":tables",
6470 "@FP16",
6471 "@pthreadpool",
6472 ],
6473)
6474
6475xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006476 name = "avx_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006477 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006478 gcc_copts = xnnpack_gcc_std_copts(),
6479 gcc_x86_copts = ["-mavx"],
6480 msvc_copts = xnnpack_msvc_std_copts(),
6481 msvc_x86_32_copts = ["/arch:AVX"],
6482 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006483 x86_srcs = ALL_AVX_MICROKERNEL_SRCS,
Marat Dukhan04f03be2019-11-19 12:36:47 -08006484 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006485 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006486 "@FP16",
6487 "@pthreadpool",
6488 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006489)
6490
6491xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006492 name = "avx_prod_microkernels",
6493 hdrs = INTERNAL_HDRS,
6494 gcc_copts = xnnpack_gcc_std_copts(),
6495 gcc_x86_copts = ["-mavx"],
6496 msvc_copts = xnnpack_msvc_std_copts(),
6497 msvc_x86_32_copts = ["/arch:AVX"],
6498 msvc_x86_64_copts = ["/arch:AVX"],
6499 x86_srcs = PROD_AVX_MICROKERNEL_SRCS,
6500 deps = [
6501 ":tables",
6502 "@FP16",
6503 "@pthreadpool",
6504 ],
6505)
6506
6507xnnpack_cc_library(
6508 name = "avx_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006509 hdrs = INTERNAL_HDRS,
6510 copts = [
6511 "-UNDEBUG",
6512 "-DXNN_TEST_MODE=1",
6513 ],
6514 gcc_copts = xnnpack_gcc_std_copts(),
6515 gcc_x86_copts = ["-mavx"],
6516 msvc_copts = xnnpack_msvc_std_copts(),
6517 msvc_x86_32_copts = ["/arch:AVX"],
6518 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006519 x86_srcs = ALL_AVX_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006520 deps = [
6521 ":tables",
6522 "@FP16",
6523 "@pthreadpool",
6524 ],
6525)
6526
6527xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006528 name = "xop_bench_microkernels",
Marat Dukhan1566fee2020-08-02 21:55:41 -07006529 hdrs = INTERNAL_HDRS,
6530 gcc_copts = xnnpack_gcc_std_copts(),
6531 gcc_x86_copts = ["-mxop"],
6532 msvc_copts = xnnpack_msvc_std_copts(),
6533 msvc_x86_32_copts = ["/arch:AVX"],
6534 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006535 x86_srcs = ALL_XOP_MICROKERNEL_SRCS,
Marat Dukhan1566fee2020-08-02 21:55:41 -07006536 deps = [
6537 ":tables",
6538 "@FP16",
6539 "@pthreadpool",
6540 ],
6541)
6542
6543xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006544 name = "xop_prod_microkernels",
6545 hdrs = INTERNAL_HDRS,
6546 gcc_copts = xnnpack_gcc_std_copts(),
6547 gcc_x86_copts = ["-mxop"],
6548 msvc_copts = xnnpack_msvc_std_copts(),
6549 msvc_x86_32_copts = ["/arch:AVX"],
6550 msvc_x86_64_copts = ["/arch:AVX"],
6551 x86_srcs = PROD_XOP_MICROKERNEL_SRCS,
6552 deps = [
6553 ":tables",
6554 "@FP16",
6555 "@pthreadpool",
6556 ],
6557)
6558
6559xnnpack_cc_library(
6560 name = "xop_test_microkernels",
Marat Dukhan1566fee2020-08-02 21:55:41 -07006561 hdrs = INTERNAL_HDRS,
6562 copts = [
6563 "-UNDEBUG",
6564 "-DXNN_TEST_MODE=1",
6565 ],
6566 gcc_copts = xnnpack_gcc_std_copts(),
6567 gcc_x86_copts = ["-mxop"],
6568 msvc_copts = xnnpack_msvc_std_copts(),
6569 msvc_x86_32_copts = ["/arch:AVX"],
6570 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006571 x86_srcs = ALL_XOP_MICROKERNEL_SRCS,
Marat Dukhan1566fee2020-08-02 21:55:41 -07006572 deps = [
6573 ":tables",
6574 "@FP16",
6575 "@pthreadpool",
6576 ],
6577)
6578
6579xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006580 name = "fma3_bench_microkernels",
Marat Dukhanfda12b82019-11-21 12:27:59 -08006581 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006582 gcc_copts = xnnpack_gcc_std_copts(),
6583 gcc_x86_copts = ["-mfma"],
6584 msvc_copts = xnnpack_msvc_std_copts(),
6585 msvc_x86_32_copts = ["/arch:AVX"],
6586 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006587 x86_srcs = ALL_FMA3_MICROKERNEL_SRCS,
Marat Dukhanfda12b82019-11-21 12:27:59 -08006588 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006589 ":tables",
Marat Dukhanfda12b82019-11-21 12:27:59 -08006590 "@FP16",
6591 "@pthreadpool",
6592 ],
6593)
6594
6595xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006596 name = "fma3_prod_microkernels",
6597 hdrs = INTERNAL_HDRS,
6598 gcc_copts = xnnpack_gcc_std_copts(),
6599 gcc_x86_copts = ["-mfma"],
6600 msvc_copts = xnnpack_msvc_std_copts(),
6601 msvc_x86_32_copts = ["/arch:AVX"],
6602 msvc_x86_64_copts = ["/arch:AVX"],
6603 x86_srcs = PROD_FMA3_MICROKERNEL_SRCS,
6604 deps = [
6605 ":tables",
6606 "@FP16",
6607 "@pthreadpool",
6608 ],
6609)
6610
6611xnnpack_cc_library(
6612 name = "fma3_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006613 hdrs = INTERNAL_HDRS,
6614 copts = [
6615 "-UNDEBUG",
6616 "-DXNN_TEST_MODE=1",
6617 ],
6618 gcc_copts = xnnpack_gcc_std_copts(),
6619 gcc_x86_copts = ["-mfma"],
6620 msvc_copts = xnnpack_msvc_std_copts(),
6621 msvc_x86_32_copts = ["/arch:AVX"],
6622 msvc_x86_64_copts = ["/arch:AVX"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006623 x86_srcs = ALL_FMA3_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006624 deps = [
6625 ":tables",
6626 "@FP16",
6627 "@pthreadpool",
6628 ],
6629)
6630
6631xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006632 name = "avx2_bench_microkernels",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07006633 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006634 gcc_copts = xnnpack_gcc_std_copts(),
6635 gcc_x86_copts = [
Marat Dukhan6adff4e2019-10-14 18:32:07 -07006636 "-mfma",
6637 "-mavx2",
6638 ],
Marat Dukhan10a38082020-04-17 03:58:35 -07006639 msvc_copts = xnnpack_msvc_std_copts(),
6640 msvc_x86_32_copts = ["/arch:AVX2"],
6641 msvc_x86_64_copts = ["/arch:AVX2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006642 x86_srcs = ALL_AVX2_MICROKERNEL_SRCS,
Marat Dukhan04f03be2019-11-19 12:36:47 -08006643 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006644 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006645 "@FP16",
6646 "@pthreadpool",
6647 ],
Marat Dukhan6adff4e2019-10-14 18:32:07 -07006648)
6649
6650xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006651 name = "avx2_prod_microkernels",
6652 hdrs = INTERNAL_HDRS,
6653 gcc_copts = xnnpack_gcc_std_copts(),
6654 gcc_x86_copts = [
6655 "-mfma",
6656 "-mavx2",
6657 ],
6658 msvc_copts = xnnpack_msvc_std_copts(),
6659 msvc_x86_32_copts = ["/arch:AVX2"],
6660 msvc_x86_64_copts = ["/arch:AVX2"],
6661 x86_srcs = PROD_AVX2_MICROKERNEL_SRCS,
6662 deps = [
6663 ":tables",
6664 "@FP16",
6665 "@pthreadpool",
6666 ],
6667)
6668
6669xnnpack_cc_library(
6670 name = "avx2_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006671 hdrs = INTERNAL_HDRS,
6672 copts = [
6673 "-UNDEBUG",
6674 "-DXNN_TEST_MODE=1",
6675 ],
6676 gcc_copts = xnnpack_gcc_std_copts(),
6677 gcc_x86_copts = [
6678 "-mfma",
6679 "-mavx2",
6680 ],
6681 msvc_copts = xnnpack_msvc_std_copts(),
6682 msvc_x86_32_copts = ["/arch:AVX2"],
6683 msvc_x86_64_copts = ["/arch:AVX2"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006684 x86_srcs = ALL_AVX2_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006685 deps = [
6686 ":tables",
6687 "@FP16",
6688 "@pthreadpool",
6689 ],
6690)
6691
6692xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006693 name = "avx512f_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006694 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07006695 gcc_copts = xnnpack_gcc_std_copts(),
6696 gcc_x86_copts = ["-mavx512f"],
6697 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6698 msvc_copts = xnnpack_msvc_std_copts(),
6699 msvc_x86_32_copts = ["/arch:AVX512"],
6700 msvc_x86_64_copts = ["/arch:AVX512"],
6701 msys_copts = ["-fno-asynchronous-unwind-tables"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006702 x86_srcs = ALL_AVX512F_MICROKERNEL_SRCS,
Marat Dukhan04f03be2019-11-19 12:36:47 -08006703 deps = [
Marat Dukhan3a77ea72019-12-23 12:10:24 -08006704 ":tables",
Marat Dukhan04f03be2019-11-19 12:36:47 -08006705 "@FP16",
6706 "@pthreadpool",
6707 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006708)
6709
6710xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006711 name = "avx512f_prod_microkernels",
6712 hdrs = INTERNAL_HDRS,
6713 gcc_copts = xnnpack_gcc_std_copts(),
6714 gcc_x86_copts = ["-mavx512f"],
6715 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6716 msvc_copts = xnnpack_msvc_std_copts(),
6717 msvc_x86_32_copts = ["/arch:AVX512"],
6718 msvc_x86_64_copts = ["/arch:AVX512"],
6719 msys_copts = ["-fno-asynchronous-unwind-tables"],
6720 x86_srcs = PROD_AVX512F_MICROKERNEL_SRCS,
6721 deps = [
6722 ":tables",
6723 "@FP16",
6724 "@pthreadpool",
6725 ],
6726)
6727
6728xnnpack_cc_library(
6729 name = "avx512f_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006730 hdrs = INTERNAL_HDRS,
6731 copts = [
6732 "-UNDEBUG",
6733 "-DXNN_TEST_MODE=1",
6734 ],
6735 gcc_copts = xnnpack_gcc_std_copts(),
6736 gcc_x86_copts = ["-mavx512f"],
6737 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6738 msvc_copts = xnnpack_msvc_std_copts(),
6739 msvc_x86_32_copts = ["/arch:AVX512"],
6740 msvc_x86_64_copts = ["/arch:AVX512"],
6741 msys_copts = ["-fno-asynchronous-unwind-tables"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006742 x86_srcs = ALL_AVX512F_MICROKERNEL_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07006743 deps = [
6744 ":tables",
6745 "@FP16",
6746 "@pthreadpool",
6747 ],
6748)
6749
6750xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006751 name = "avx512skx_bench_microkernels",
Marat Dukhanbb00b1d2020-08-10 11:37:23 -07006752 hdrs = INTERNAL_HDRS,
6753 gcc_copts = xnnpack_gcc_std_copts(),
6754 gcc_x86_copts = [
6755 "-mavx512f",
6756 "-mavx512cd",
6757 "-mavx512bw",
6758 "-mavx512dq",
6759 "-mavx512vl",
6760 ],
6761 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6762 msvc_copts = xnnpack_msvc_std_copts(),
6763 msvc_x86_32_copts = ["/arch:AVX512"],
6764 msvc_x86_64_copts = ["/arch:AVX512"],
6765 msys_copts = ["-fno-asynchronous-unwind-tables"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006766 x86_srcs = ALL_AVX512SKX_MICROKERNEL_SRCS,
Marat Dukhanbb00b1d2020-08-10 11:37:23 -07006767 deps = [
6768 ":tables",
6769 "@FP16",
6770 "@pthreadpool",
6771 ],
6772)
6773
6774xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006775 name = "avx512skx_prod_microkernels",
6776 hdrs = INTERNAL_HDRS,
6777 gcc_copts = xnnpack_gcc_std_copts(),
6778 gcc_x86_copts = [
6779 "-mavx512f",
6780 "-mavx512cd",
6781 "-mavx512bw",
6782 "-mavx512dq",
6783 "-mavx512vl",
6784 ],
6785 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6786 msvc_copts = xnnpack_msvc_std_copts(),
6787 msvc_x86_32_copts = ["/arch:AVX512"],
6788 msvc_x86_64_copts = ["/arch:AVX512"],
6789 msys_copts = ["-fno-asynchronous-unwind-tables"],
6790 x86_srcs = PROD_AVX512SKX_MICROKERNEL_SRCS,
6791 deps = [
6792 ":tables",
6793 "@FP16",
6794 "@pthreadpool",
6795 ],
6796)
6797
6798xnnpack_cc_library(
6799 name = "avx512skx_test_microkernels",
Marat Dukhanbb00b1d2020-08-10 11:37:23 -07006800 hdrs = INTERNAL_HDRS,
6801 copts = [
6802 "-UNDEBUG",
6803 "-DXNN_TEST_MODE=1",
6804 ],
6805 gcc_copts = xnnpack_gcc_std_copts(),
6806 gcc_x86_copts = [
6807 "-mavx512f",
6808 "-mavx512cd",
6809 "-mavx512bw",
6810 "-mavx512dq",
6811 "-mavx512vl",
6812 ],
6813 mingw_copts = ["-fno-asynchronous-unwind-tables"],
6814 msvc_copts = xnnpack_msvc_std_copts(),
6815 msvc_x86_32_copts = ["/arch:AVX512"],
6816 msvc_x86_64_copts = ["/arch:AVX512"],
6817 msys_copts = ["-fno-asynchronous-unwind-tables"],
Marat Dukhan2c724952021-07-27 18:46:30 -07006818 x86_srcs = ALL_AVX512SKX_MICROKERNEL_SRCS,
Marat Dukhanbb00b1d2020-08-10 11:37:23 -07006819 deps = [
6820 ":tables",
6821 "@FP16",
6822 "@pthreadpool",
6823 ],
6824)
6825
6826xnnpack_cc_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006827 name = "asm_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006828 hdrs = ["src/xnnpack/assembly.h"],
Marat Dukhandb3b0a72021-07-27 08:58:01 -07006829 aarch32_srcs = AARCH32_ASM_MICROKERNEL_SRCS,
Frank Barchard31bb45b2020-10-06 00:26:33 -07006830 aarch64_copts = ["-march=armv8.2-a+fp16+dotprod"],
Marat Dukhandb3b0a72021-07-27 08:58:01 -07006831 aarch64_srcs = AARCH64_ASM_MICROKERNEL_SRCS,
6832 wasm_srcs = WASM32_ASM_MICROKERNEL_SRCS,
6833 wasmsimd_srcs = WASM32_ASM_MICROKERNEL_SRCS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07006834)
6835
Marat Dukhan3b59de22020-06-03 20:15:19 -07006836xnnpack_cc_library(
6837 name = "logging_utils",
6838 srcs = LOGGING_SRCS,
6839 hdrs = INTERNAL_HDRS + LOGGING_HDRS,
6840 copts = LOGGING_COPTS + [
6841 "-Isrc",
6842 "-Iinclude",
6843 ] + select({
6844 ":debug_build": [],
6845 "//conditions:default": xnnpack_min_size_copts(),
6846 }),
6847 gcc_copts = xnnpack_gcc_std_copts(),
6848 msvc_copts = xnnpack_msvc_std_copts(),
6849 visibility = xnnpack_visibility(),
6850 deps = [
6851 "@FP16",
6852 "@clog",
6853 "@pthreadpool",
6854 ],
6855)
6856
Marat Dukhan08c4a432019-10-03 09:29:21 -07006857xnnpack_aggregate_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006858 name = "bench_microkernels",
Marat Dukhan6e8c0ce2021-04-13 14:35:08 -07006859 aarch32_ios_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006860 ":neon_bench_microkernels",
6861 ":neonfma_bench_microkernels",
6862 ":neonv8_bench_microkernels",
6863 ":asm_microkernels",
Marat Dukhan6e8c0ce2021-04-13 14:35:08 -07006864 ],
6865 aarch32_nonios_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006866 ":neon_bench_microkernels",
6867 ":neonfma_bench_microkernels",
6868 ":neonv8_bench_microkernels",
6869 ":neondot_bench_microkernels",
6870 ":asm_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006871 ],
6872 aarch64_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006873 ":neon_bench_microkernels",
6874 ":neonfma_bench_microkernels",
6875 ":neonv8_bench_microkernels",
6876 ":neonfp16arith_bench_microkernels",
6877 ":neondot_bench_microkernels",
6878 ":asm_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006879 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07006880 generic_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006881 ":scalar_bench_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006882 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07006883 wasm_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006884 ":wasm_bench_microkernels",
6885 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006886 ],
6887 wasmsimd_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006888 ":wasm_bench_microkernels",
6889 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006890 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07006891 x86_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006892 ":sse2_bench_microkernels",
6893 ":ssse3_bench_microkernels",
6894 ":sse41_bench_microkernels",
6895 ":avx_bench_microkernels",
6896 ":xop_bench_microkernels",
6897 ":fma3_bench_microkernels",
6898 ":avx2_bench_microkernels",
6899 ":avx512f_bench_microkernels",
6900 ":avx512skx_bench_microkernels",
Marat Dukhan08c4a432019-10-03 09:29:21 -07006901 ],
6902)
6903
Marat Dukhan33fcf782020-05-24 14:27:15 -07006904xnnpack_aggregate_library(
Marat Dukhan2c724952021-07-27 18:46:30 -07006905 name = "prod_microkernels",
Marat Dukhan6e8c0ce2021-04-13 14:35:08 -07006906 aarch32_ios_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006907 ":neon_prod_microkernels",
6908 ":neonfma_prod_microkernels",
6909 ":neonv8_prod_microkernels",
6910 ":asm_microkernels",
Marat Dukhan6e8c0ce2021-04-13 14:35:08 -07006911 ],
6912 aarch32_nonios_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006913 ":neon_prod_microkernels",
6914 ":neonfma_prod_microkernels",
6915 ":neonv8_prod_microkernels",
6916 ":neondot_prod_microkernels",
6917 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006918 ],
6919 aarch64_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006920 ":neon_prod_microkernels",
6921 ":neonfma_prod_microkernels",
6922 ":neonv8_prod_microkernels",
6923 ":neonfp16arith_prod_microkernels",
6924 ":neondot_prod_microkernels",
6925 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006926 ],
6927 generic_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006928 ":scalar_prod_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006929 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07006930 wasm_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006931 ":wasm_prod_microkernels",
6932 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006933 ],
6934 wasmsimd_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006935 ":wasm_prod_microkernels",
6936 ":asm_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006937 ],
6938 x86_deps = [
Marat Dukhan2c724952021-07-27 18:46:30 -07006939 ":sse2_prod_microkernels",
6940 ":ssse3_prod_microkernels",
6941 ":sse41_prod_microkernels",
6942 ":avx_prod_microkernels",
6943 ":xop_prod_microkernels",
6944 ":fma3_prod_microkernels",
6945 ":avx2_prod_microkernels",
6946 ":avx512f_prod_microkernels",
6947 ":avx512skx_prod_microkernels",
6948 ],
6949)
6950
6951xnnpack_aggregate_library(
6952 name = "test_microkernels",
6953 aarch32_ios_deps = [
6954 ":neon_test_microkernels",
6955 ":neonfma_test_microkernels",
6956 ":neonv8_test_microkernels",
6957 ":asm_microkernels",
6958 ],
6959 aarch32_nonios_deps = [
6960 ":neon_test_microkernels",
6961 ":neonfma_test_microkernels",
6962 ":neonv8_test_microkernels",
6963 ":neondot_test_microkernels",
6964 ":asm_microkernels",
6965 ],
6966 aarch64_deps = [
6967 ":neon_test_microkernels",
6968 ":neonfma_test_microkernels",
6969 ":neonv8_test_microkernels",
6970 ":neonfp16arith_test_microkernels",
6971 ":neondot_test_microkernels",
6972 ":asm_microkernels",
6973 ],
6974 generic_deps = [
6975 ":scalar_test_microkernels",
6976 ],
6977 wasm_deps = [
6978 ":wasm_test_microkernels",
6979 ":asm_microkernels",
6980 ],
6981 wasmsimd_deps = [
6982 ":wasm_test_microkernels",
6983 ":asm_microkernels",
6984 ],
6985 x86_deps = [
6986 ":sse2_test_microkernels",
6987 ":ssse3_test_microkernels",
6988 ":sse41_test_microkernels",
6989 ":avx_test_microkernels",
6990 ":xop_test_microkernels",
6991 ":fma3_test_microkernels",
6992 ":avx2_test_microkernels",
6993 ":avx512f_test_microkernels",
6994 ":avx512skx_test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07006995 ],
6996)
6997
Marat Dukhan08c4a432019-10-03 09:29:21 -07006998xnnpack_cc_library(
6999 name = "im2col",
7000 srcs = ["src/im2col.c"],
7001 hdrs = [
7002 "src/xnnpack/common.h",
7003 "src/xnnpack/im2col.h",
7004 ],
Marat Dukhan10a38082020-04-17 03:58:35 -07007005 gcc_copts = xnnpack_gcc_std_copts(),
7006 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007007)
7008
7009xnnpack_cc_library(
7010 name = "indirection",
7011 srcs = ["src/indirection.c"],
7012 hdrs = INTERNAL_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007013 gcc_copts = xnnpack_gcc_std_copts(),
7014 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007015 deps = [
7016 "@FP16",
7017 "@FXdiv",
7018 "@pthreadpool",
7019 ],
7020)
7021
7022xnnpack_cc_library(
Marat Dukhan33fcf782020-05-24 14:27:15 -07007023 name = "indirection_test_mode",
7024 srcs = ["src/indirection.c"],
7025 hdrs = INTERNAL_HDRS,
7026 copts = [
7027 "-UNDEBUG",
7028 "-DXNN_TEST_MODE=1",
7029 ],
7030 gcc_copts = xnnpack_gcc_std_copts(),
7031 msvc_copts = xnnpack_msvc_std_copts(),
7032 deps = [
7033 "@FP16",
7034 "@FXdiv",
7035 "@pthreadpool",
7036 ],
7037)
7038
7039xnnpack_cc_library(
Marat Dukhanab582382020-07-06 13:32:08 -07007040 name = "packing",
7041 srcs = ["src/packing.c"],
7042 hdrs = INTERNAL_HDRS,
7043 gcc_copts = xnnpack_gcc_std_copts(),
7044 msvc_copts = xnnpack_msvc_std_copts(),
7045 deps = [
7046 "@FP16",
7047 "@FXdiv",
7048 "@pthreadpool",
7049 ],
7050)
7051
7052xnnpack_cc_library(
7053 name = "packing_test_mode",
7054 srcs = ["src/packing.c"],
7055 hdrs = INTERNAL_HDRS,
7056 copts = [
7057 "-UNDEBUG",
7058 "-DXNN_TEST_MODE=1",
7059 ],
7060 gcc_copts = xnnpack_gcc_std_copts(),
7061 msvc_copts = xnnpack_msvc_std_copts(),
7062 deps = [
7063 "@FP16",
7064 "@FXdiv",
7065 "@pthreadpool",
7066 ],
7067)
7068
7069xnnpack_cc_library(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007070 name = "operator_run",
7071 srcs = ["src/operator-run.c"],
Marat Dukhanc8e00eb2019-10-04 14:55:26 -07007072 hdrs = INTERNAL_HDRS + LOGGING_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007073 copts = LOGGING_COPTS + select({
Marat Dukhan05702cf2020-03-26 15:41:33 -07007074 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7075 "//conditions:default": [],
7076 }),
Marat Dukhan10a38082020-04-17 03:58:35 -07007077 gcc_copts = xnnpack_gcc_std_copts(),
7078 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007079 deps = [
Marat Dukhan3b59de22020-06-03 20:15:19 -07007080 ":logging_utils",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007081 "@FP16",
7082 "@FXdiv",
7083 "@clog",
7084 "@pthreadpool",
7085 ],
7086)
7087
Chao Mei6ddfc602020-05-13 22:29:36 -07007088xnnpack_cc_library(
Marat Dukhan33fcf782020-05-24 14:27:15 -07007089 name = "operator_run_test_mode",
7090 srcs = ["src/operator-run.c"],
7091 hdrs = INTERNAL_HDRS + LOGGING_HDRS,
7092 copts = LOGGING_COPTS + [
7093 "-UNDEBUG",
7094 "-DXNN_TEST_MODE=1",
7095 ] + select({
7096 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7097 "//conditions:default": [],
7098 }),
7099 gcc_copts = xnnpack_gcc_std_copts(),
7100 msvc_copts = xnnpack_msvc_std_copts(),
7101 deps = [
Marat Dukhan3b59de22020-06-03 20:15:19 -07007102 ":logging_utils",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007103 "@FP16",
7104 "@FXdiv",
7105 "@clog",
7106 "@pthreadpool",
7107 ],
7108)
7109
7110xnnpack_cc_library(
Chao Mei6ddfc602020-05-13 22:29:36 -07007111 name = "memory_planner",
7112 srcs = ["src/memory-planner.c"],
7113 hdrs = INTERNAL_HDRS,
7114 defines = select({
7115 ":xnn_enable_memopt_explicit_true": ["XNN_ENABLE_MEMOPT=1"],
7116 ":xnn_enable_memopt_explicit_false": ["XNN_ENABLE_MEMOPT=0"],
7117 "//conditions:default": ["XNN_ENABLE_MEMOPT=1"],
7118 }),
7119 gcc_copts = xnnpack_gcc_std_copts(),
7120 msvc_copts = xnnpack_msvc_std_copts(),
7121 deps = [
Marat Dukhan3b59de22020-06-03 20:15:19 -07007122 ":logging_utils",
Chao Mei6ddfc602020-05-13 22:29:36 -07007123 "@pthreadpool",
7124 ],
7125)
7126
Marat Dukhan33fcf782020-05-24 14:27:15 -07007127xnnpack_cc_library(
7128 name = "memory_planner_test_mode",
7129 srcs = ["src/memory-planner.c"],
7130 hdrs = INTERNAL_HDRS,
7131 copts = [
7132 "-UNDEBUG",
7133 "-DXNN_TEST_MODE=1",
7134 ],
7135 defines = select({
7136 ":xnn_enable_memopt_explicit_true": ["XNN_ENABLE_MEMOPT=1"],
7137 ":xnn_enable_memopt_explicit_false": ["XNN_ENABLE_MEMOPT=0"],
7138 "//conditions:default": ["XNN_ENABLE_MEMOPT=1"],
7139 }),
7140 gcc_copts = xnnpack_gcc_std_copts(),
7141 msvc_copts = xnnpack_msvc_std_copts(),
7142 deps = [
Marat Dukhan3b59de22020-06-03 20:15:19 -07007143 ":logging_utils",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007144 "@pthreadpool",
7145 ],
7146)
7147
Marat Dukhan08c4a432019-10-03 09:29:21 -07007148cc_library(
7149 name = "enable_assembly",
7150 defines = select({
7151 ":xnn_enable_assembly_explicit_true": ["XNN_ENABLE_ASSEMBLY=1"],
7152 ":xnn_enable_assembly_explicit_false": ["XNN_ENABLE_ASSEMBLY=0"],
Frank Barchard810171d2019-10-10 10:34:51 -07007153 "//conditions:default": ["XNN_ENABLE_ASSEMBLY=1"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007154 }),
7155)
7156
Marat Dukhan9de90e02020-06-18 16:04:12 -07007157cc_library(
7158 name = "enable_sparse",
7159 defines = select({
7160 ":xnn_enable_sparse_explicit_true": ["XNN_ENABLE_SPARSE=1"],
7161 ":xnn_enable_sparse_explicit_false": ["XNN_ENABLE_SPARSE=0"],
Marat Dukhanb36582b2020-12-08 11:16:28 -08007162 "//conditions:default": ["XNN_ENABLE_SPARSE=1"],
Marat Dukhan9de90e02020-06-18 16:04:12 -07007163 }),
7164)
7165
Marat Dukhancf056b22019-10-07 10:26:29 -07007166xnnpack_cc_library(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007167 name = "operators",
7168 srcs = OPERATOR_SRCS + [
Marat Dukhan496389f2021-04-07 15:47:12 -07007169 "src/allocator.c",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007170 "src/operator-delete.c",
Marat Dukhancf056b22019-10-07 10:26:29 -07007171 ],
7172 hdrs = INTERNAL_HDRS + LOGGING_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007173 copts = LOGGING_COPTS + [
Marat Dukhan08c4a432019-10-03 09:29:21 -07007174 "-Isrc",
7175 "-Iinclude",
7176 ] + select({
7177 ":debug_build": [],
7178 "//conditions:default": xnnpack_min_size_copts(),
Marat Dukhan05702cf2020-03-26 15:41:33 -07007179 }) + select({
7180 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7181 "//conditions:default": [],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007182 }),
Marat Dukhan10a38082020-04-17 03:58:35 -07007183 gcc_copts = xnnpack_gcc_std_copts(),
7184 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007185 deps = [
Marat Dukhan08c4a432019-10-03 09:29:21 -07007186 ":indirection",
Marat Dukhan3b59de22020-06-03 20:15:19 -07007187 ":logging_utils",
Marat Dukhanab582382020-07-06 13:32:08 -07007188 ":packing",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007189 "@FP16",
7190 "@FXdiv",
7191 "@clog",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007192 "@pthreadpool",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007193 ],
7194)
7195
Marat Dukhan10a38082020-04-17 03:58:35 -07007196xnnpack_cc_library(
Marat Dukhan33fcf782020-05-24 14:27:15 -07007197 name = "operators_test_mode",
7198 srcs = OPERATOR_SRCS + [
Marat Dukhan496389f2021-04-07 15:47:12 -07007199 "src/allocator.c",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007200 "src/operator-delete.c",
7201 ],
7202 hdrs = INTERNAL_HDRS + LOGGING_HDRS,
7203 copts = LOGGING_COPTS + [
7204 "-Isrc",
7205 "-Iinclude",
7206 "-UNDEBUG",
7207 "-DXNN_TEST_MODE=1",
7208 ] + select({
7209 ":debug_build": [],
7210 "//conditions:default": xnnpack_min_size_copts(),
7211 }) + select({
7212 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7213 "//conditions:default": [],
7214 }),
7215 gcc_copts = xnnpack_gcc_std_copts(),
7216 msvc_copts = xnnpack_msvc_std_copts(),
7217 deps = [
7218 ":indirection_test_mode",
Marat Dukhan3b59de22020-06-03 20:15:19 -07007219 ":logging_utils",
Marat Dukhanab582382020-07-06 13:32:08 -07007220 ":packing_test_mode",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007221 "@FP16",
7222 "@FXdiv",
7223 "@clog",
7224 "@pthreadpool",
7225 ],
7226)
7227
7228xnnpack_cc_library(
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007229 name = "XNNPACK",
7230 srcs = [
7231 "src/init.c",
Marat Dukhanccfdbd12020-02-03 14:27:45 -08007232 "src/runtime.c",
7233 "src/subgraph.c",
7234 "src/tensor.c",
Marat Dukhanf03da0d2020-06-10 16:00:20 -07007235 ] + SUBGRAPH_SRCS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007236 hdrs = ["include/xnnpack.h"],
7237 copts = LOGGING_COPTS + [
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007238 "-Isrc",
7239 "-Iinclude",
7240 ] + select({
7241 ":debug_build": [],
7242 "//conditions:default": xnnpack_min_size_copts(),
Marat Dukhan05702cf2020-03-26 15:41:33 -07007243 }) + select({
7244 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7245 "//conditions:default": [],
Marat Dukhan1ce78ab2021-09-03 17:37:51 -07007246 }) + select({
7247 ":xnn_wasmsimd_version_m87": [
7248 "-DXNN_WASMSIMD_VERSION=87",
7249 ],
7250 ":xnn_wasmsimd_version_m88": [
7251 "-DXNN_WASMSIMD_VERSION=88",
7252 ],
7253 ":xnn_wasmsimd_version_m91": [
7254 "-DXNN_WASMSIMD_VERSION=91",
7255 ],
7256 "//conditions:default": [
7257 "-DXNN_WASMSIMD_VERSION=87",
7258 ],
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007259 }),
Marat Dukhan10a38082020-04-17 03:58:35 -07007260 gcc_copts = xnnpack_gcc_std_copts(),
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007261 includes = ["include"],
Marat Dukhan10a38082020-04-17 03:58:35 -07007262 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007263 visibility = xnnpack_visibility(),
7264 deps = [
7265 ":enable_assembly",
Marat Dukhan9de90e02020-06-18 16:04:12 -07007266 ":enable_sparse",
Marat Dukhan3b59de22020-06-03 20:15:19 -07007267 ":logging_utils",
Chao Mei6ddfc602020-05-13 22:29:36 -07007268 ":memory_planner",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007269 ":operator_run",
7270 ":operators",
Marat Dukhan2c724952021-07-27 18:46:30 -07007271 ":prod_microkernels",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007272 "@clog",
Marat Dukhanab2946c2020-05-21 20:04:13 -07007273 "@FP16",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007274 "@pthreadpool",
Marat Dukhand343c222019-10-07 09:22:14 -07007275 ] + select({
7276 ":emscripten": [],
7277 "//conditions:default": ["@cpuinfo"],
7278 }),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007279)
7280
Marat Dukhan10a38082020-04-17 03:58:35 -07007281xnnpack_cc_library(
Marat Dukhan33fcf782020-05-24 14:27:15 -07007282 name = "XNNPACK_test_mode",
7283 srcs = [
7284 "src/init.c",
7285 "src/runtime.c",
7286 "src/subgraph.c",
7287 "src/tensor.c",
Marat Dukhanf03da0d2020-06-10 16:00:20 -07007288 ] + SUBGRAPH_SRCS,
Marat Dukhan33fcf782020-05-24 14:27:15 -07007289 hdrs = ["include/xnnpack.h"],
7290 copts = LOGGING_COPTS + [
7291 "-Isrc",
7292 "-Iinclude",
7293 "-UNDEBUG",
7294 "-DXNN_TEST_MODE=1",
7295 ] + select({
7296 ":debug_build": [],
7297 "//conditions:default": xnnpack_min_size_copts(),
7298 }) + select({
7299 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7300 "//conditions:default": [],
Marat Dukhan1ce78ab2021-09-03 17:37:51 -07007301 }) + select({
7302 ":xnn_wasmsimd_version_m87": [
7303 "-DXNN_WASMSIMD_VERSION=87",
7304 ],
7305 ":xnn_wasmsimd_version_m88": [
7306 "-DXNN_WASMSIMD_VERSION=88",
7307 ],
7308 ":xnn_wasmsimd_version_m91": [
7309 "-DXNN_WASMSIMD_VERSION=91",
7310 ],
7311 "//conditions:default": [
7312 "-DXNN_WASMSIMD_VERSION=87",
7313 ],
Marat Dukhan33fcf782020-05-24 14:27:15 -07007314 }),
7315 gcc_copts = xnnpack_gcc_std_copts(),
7316 includes = ["include"],
7317 msvc_copts = xnnpack_msvc_std_copts(),
7318 visibility = xnnpack_visibility(),
7319 deps = [
7320 ":enable_assembly",
Marat Dukhan9de90e02020-06-18 16:04:12 -07007321 ":enable_sparse",
Marat Dukhan3b59de22020-06-03 20:15:19 -07007322 ":logging_utils",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007323 ":memory_planner_test_mode",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007324 ":operator_run_test_mode",
7325 ":operators_test_mode",
Marat Dukhan2c724952021-07-27 18:46:30 -07007326 ":test_microkernels",
Marat Dukhan33fcf782020-05-24 14:27:15 -07007327 "@clog",
7328 "@FP16",
7329 "@pthreadpool",
7330 ] + select({
7331 ":emscripten": [],
7332 "//conditions:default": ["@cpuinfo"],
7333 }),
7334)
7335
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07007336# Specialized XNNPACK version for TensorFlow Lite. Excludes operators currently
7337# not used by the TensorFlow Lite XNNPACK delegate to minimize code size.
Marat Dukhanae046f52020-06-15 13:16:14 -07007338xnnpack_cc_library(
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07007339 name = "xnnpack_for_tflite",
7340 srcs = [
7341 "src/init.c",
7342 "src/runtime.c",
7343 "src/subgraph.c",
7344 "src/tensor.c",
7345 ] + SUBGRAPH_SRCS,
7346 hdrs = ["include/xnnpack.h"],
7347 copts = LOGGING_COPTS + [
7348 "-Isrc",
7349 "-Iinclude",
7350 ] + select({
7351 ":debug_build": [],
7352 "//conditions:default": xnnpack_min_size_copts(),
7353 }) + select({
7354 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7355 "//conditions:default": [],
7356 }),
7357 defines = [
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07007358 "XNN_NO_F16_OPERATORS",
7359 "XNN_NO_X16_OPERATORS",
Marat Dukhanb939cdb2021-03-30 18:51:51 -07007360 ] + select({
7361 ":xnn_enable_qs8_explicit_true": [],
Marat Dukhan5e353862021-06-15 09:03:25 -07007362 ":xnn_enable_qs8_explicit_false": [
7363 "XNN_NO_QC8_OPERATORS",
7364 "XNN_NO_QS8_OPERATORS",
Marat Dukhan0d00baa2021-08-16 23:59:07 -07007365 "XNN_NO_S8_OPERATORS",
Marat Dukhan5e353862021-06-15 09:03:25 -07007366 ],
Marat Dukhan6507b172021-08-19 03:23:40 -07007367 ":emscripten": [],
Marat Dukhan5e353862021-06-15 09:03:25 -07007368 "//conditions:default": [
7369 "XNN_NO_QC8_OPERATORS",
7370 "XNN_NO_QS8_OPERATORS",
Marat Dukhan0d00baa2021-08-16 23:59:07 -07007371 "XNN_NO_S8_OPERATORS",
Marat Dukhan5e353862021-06-15 09:03:25 -07007372 ],
Marat Dukhan8c8c1592021-07-13 13:59:02 -07007373 }) + select({
7374 ":xnn_enable_qu8_explicit_true": [],
7375 ":xnn_enable_qu8_explicit_false": [
7376 "XNN_NO_QU8_OPERATORS",
Marat Dukhan0d00baa2021-08-16 23:59:07 -07007377 "XNN_NO_U8_OPERATORS",
Marat Dukhan8c8c1592021-07-13 13:59:02 -07007378 ],
Marat Dukhan6507b172021-08-19 03:23:40 -07007379 ":emscripten": [],
Marat Dukhan8c8c1592021-07-13 13:59:02 -07007380 "//conditions:default": [
7381 "XNN_NO_QU8_OPERATORS",
Marat Dukhan0d00baa2021-08-16 23:59:07 -07007382 "XNN_NO_U8_OPERATORS",
Marat Dukhan8c8c1592021-07-13 13:59:02 -07007383 ],
Marat Dukhan189c1d02021-09-03 15:39:54 -07007384 }) + select({
7385 ":xnn_wasmsimd_version_m87": [
7386 "XNN_WASMSIMD_VERSION=87",
7387 ],
7388 ":xnn_wasmsimd_version_m88": [
7389 "XNN_WASMSIMD_VERSION=88",
7390 ],
7391 ":xnn_wasmsimd_version_m91": [
7392 "XNN_WASMSIMD_VERSION=91",
7393 ],
7394 "//conditions:default": [
7395 "XNN_WASMSIMD_VERSION=87",
7396 ],
Marat Dukhanb939cdb2021-03-30 18:51:51 -07007397 }),
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07007398 gcc_copts = xnnpack_gcc_std_copts(),
7399 includes = ["include"],
7400 msvc_copts = xnnpack_msvc_std_copts(),
7401 visibility = xnnpack_visibility(),
7402 deps = [
7403 ":enable_assembly",
7404 ":enable_sparse",
7405 ":logging_utils",
7406 ":memory_planner",
7407 ":operator_run",
7408 ":operators",
Marat Dukhan2c724952021-07-27 18:46:30 -07007409 ":prod_microkernels",
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07007410 "@clog",
7411 "@FP16",
7412 "@pthreadpool",
7413 ] + select({
7414 ":emscripten": [],
7415 "//conditions:default": ["@cpuinfo"],
7416 }),
7417)
7418
7419# Specialized XNNPACK version for TensorFlow.js. Excludes operators currently
7420# not used by the TensorFlow.js WebAssembly backend to minimize code size.
7421xnnpack_cc_library(
7422 name = "xnnpack_for_tfjs",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007423 srcs = [
7424 "src/init.c",
7425 ],
Marat Dukhan10a38082020-04-17 03:58:35 -07007426 hdrs = ["include/xnnpack.h"],
7427 copts = LOGGING_COPTS + [
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007428 "-Isrc",
7429 "-Iinclude",
7430 ] + select({
7431 ":debug_build": [],
7432 "//conditions:default": xnnpack_min_size_copts(),
Marat Dukhan05702cf2020-03-26 15:41:33 -07007433 }) + select({
7434 ":xnn_enable_hmp_explicit_false": ["-DXNN_MAX_UARCH_TYPES=1"],
7435 "//conditions:default": [],
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007436 }),
7437 defines = [
Marat Dukhan16f1e1a2020-08-04 16:38:22 -07007438 "XNN_NO_QS8_OPERATORS",
Marat Dukhan08b7a972020-07-14 18:17:29 -07007439 "XNN_NO_QU8_OPERATORS",
Marat Dukhan23147532021-08-16 07:26:56 -07007440 "XNN_NO_S8_OPERATORS",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007441 "XNN_NO_U8_OPERATORS",
7442 "XNN_NO_X8_OPERATORS",
Marat Dukhanefc47b82019-11-18 09:25:38 -08007443 "XNN_NO_NCHW_OPERATORS",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007444 ],
Marat Dukhan10a38082020-04-17 03:58:35 -07007445 gcc_copts = xnnpack_gcc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007446 includes = ["include"],
Marat Dukhan10a38082020-04-17 03:58:35 -07007447 msvc_copts = xnnpack_msvc_std_copts(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007448 visibility = xnnpack_visibility(),
7449 deps = [
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007450 ":enable_assembly",
Marat Dukhan3b59de22020-06-03 20:15:19 -07007451 ":logging_utils",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007452 ":operator_run",
7453 ":operators",
Marat Dukhan2c724952021-07-27 18:46:30 -07007454 ":prod_microkernels",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007455 "@clog",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007456 "@pthreadpool",
Marat Dukhan8fe54e42019-10-10 14:12:59 -07007457 ] + select({
7458 ":emscripten": [],
7459 "//conditions:default": ["@cpuinfo"],
7460 }),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007461)
7462
Marat Dukhancf056b22019-10-07 10:26:29 -07007463xnnpack_cc_library(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007464 name = "bench_utils",
7465 srcs = ["bench/utils.cc"],
7466 hdrs = ["bench/utils.h"],
Marat Dukhanbad48fe2019-11-04 10:35:22 -08007467 deps = [
7468 "@com_google_benchmark//:benchmark",
7469 "@cpuinfo",
7470 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007471)
7472
Frank Barchard7e955972019-10-11 10:34:25 -07007473######################### Benchmarks for micro-kernels #########################
Marat Dukhan08c4a432019-10-03 09:29:21 -07007474
7475xnnpack_benchmark(
Marat Dukhan0744fa02021-07-26 22:56:27 -07007476 name = "qs8_dwconv_bench",
7477 srcs = [
7478 "bench/dwconv.h",
7479 "bench/qs8-dwconv.cc",
7480 "src/xnnpack/AlignedAllocator.h",
7481 ] + MICROKERNEL_BENCHMARK_HDRS,
7482 deps = MICROKERNEL_BENCHMARK_DEPS + [
7483 ":indirection",
7484 ":packing",
7485 ],
7486)
7487
7488xnnpack_benchmark(
Marat Dukhan595e1702020-07-31 10:12:52 -07007489 name = "qs8_gemm_bench",
7490 srcs = [
7491 "bench/gemm.h",
7492 "bench/qs8-gemm.cc",
7493 "src/xnnpack/AlignedAllocator.h",
7494 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Frank Barchard31328cb2020-10-12 11:55:18 -07007495 copts = xnnpack_optional_ruy_copts() + xnnpack_optional_gemmlowp_copts(),
7496 deps = MICROKERNEL_BENCHMARK_DEPS + [":packing"] + xnnpack_optional_ruy_deps() + xnnpack_optional_gemmlowp_deps(),
Marat Dukhan595e1702020-07-31 10:12:52 -07007497)
7498
7499xnnpack_benchmark(
Marat Dukhan56bdd4a2020-08-03 19:47:04 -07007500 name = "qs8_requantization_bench",
7501 srcs = [
7502 "bench/qs8-requantization.cc",
Marat Dukhan56bdd4a2020-08-03 19:47:04 -07007503 "src/xnnpack/AlignedAllocator.h",
Frank Barchard04336c12020-10-22 16:48:55 -07007504 "src/xnnpack/requantization-stubs.h",
Marat Dukhan56bdd4a2020-08-03 19:47:04 -07007505 ] + MICROKERNEL_BENCHMARK_HDRS,
7506 deps = MICROKERNEL_BENCHMARK_DEPS,
7507)
7508
7509xnnpack_benchmark(
Marat Dukhan83a8d2f2021-07-29 16:41:19 -07007510 name = "qs8_vadd_bench",
7511 srcs = [
7512 "bench/qs8-vadd.cc",
7513 "src/xnnpack/AlignedAllocator.h",
7514 ] + MICROKERNEL_BENCHMARK_HDRS,
7515 deps = MICROKERNEL_BENCHMARK_DEPS,
7516)
7517
7518xnnpack_benchmark(
7519 name = "qs8_vaddc_bench",
7520 srcs = [
7521 "bench/qs8-vaddc.cc",
7522 "src/xnnpack/AlignedAllocator.h",
7523 ] + MICROKERNEL_BENCHMARK_HDRS,
7524 deps = MICROKERNEL_BENCHMARK_DEPS,
7525)
7526
7527xnnpack_benchmark(
Marat Dukhan795e5ab2021-08-02 19:07:52 -07007528 name = "qs8_vmul_bench",
7529 srcs = [
7530 "bench/qs8-vmul.cc",
7531 "src/xnnpack/AlignedAllocator.h",
7532 ] + MICROKERNEL_BENCHMARK_HDRS,
7533 deps = MICROKERNEL_BENCHMARK_DEPS,
7534)
7535
7536xnnpack_benchmark(
Marat Dukhan8b024c92021-08-03 00:05:14 -07007537 name = "qs8_vmulc_bench",
7538 srcs = [
7539 "bench/qs8-vmulc.cc",
7540 "src/xnnpack/AlignedAllocator.h",
7541 ] + MICROKERNEL_BENCHMARK_HDRS,
7542 deps = MICROKERNEL_BENCHMARK_DEPS,
7543)
7544
7545xnnpack_benchmark(
Marat Dukhan08b7a972020-07-14 18:17:29 -07007546 name = "qu8_gemm_bench",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007547 srcs = [
7548 "bench/gemm.h",
Marat Dukhan08b7a972020-07-14 18:17:29 -07007549 "bench/qu8-gemm.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007550 "src/xnnpack/AlignedAllocator.h",
7551 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007552 copts = xnnpack_optional_ruy_copts() + xnnpack_optional_gemmlowp_copts(),
Marat Dukhanab582382020-07-06 13:32:08 -07007553 deps = MICROKERNEL_BENCHMARK_DEPS + [":packing"] + xnnpack_optional_ruy_deps() + xnnpack_optional_gemmlowp_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007554)
7555
7556xnnpack_benchmark(
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07007557 name = "qu8_requantization_bench",
7558 srcs = [
7559 "bench/qu8-requantization.cc",
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07007560 "src/xnnpack/AlignedAllocator.h",
Frank Barchard04336c12020-10-22 16:48:55 -07007561 "src/xnnpack/requantization-stubs.h",
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07007562 ] + MICROKERNEL_BENCHMARK_HDRS,
7563 deps = MICROKERNEL_BENCHMARK_DEPS,
7564)
7565
7566xnnpack_benchmark(
Marat Dukhan1ef9de82021-07-29 17:15:33 -07007567 name = "qu8_vadd_bench",
7568 srcs = [
7569 "bench/qu8-vadd.cc",
7570 "src/xnnpack/AlignedAllocator.h",
7571 ] + MICROKERNEL_BENCHMARK_HDRS,
7572 deps = MICROKERNEL_BENCHMARK_DEPS,
7573)
7574
7575xnnpack_benchmark(
7576 name = "qu8_vaddc_bench",
7577 srcs = [
7578 "bench/qu8-vaddc.cc",
7579 "src/xnnpack/AlignedAllocator.h",
7580 ] + MICROKERNEL_BENCHMARK_HDRS,
7581 deps = MICROKERNEL_BENCHMARK_DEPS,
7582)
7583
7584xnnpack_benchmark(
Marat Dukhan795e5ab2021-08-02 19:07:52 -07007585 name = "qu8_vmul_bench",
7586 srcs = [
7587 "bench/qu8-vmul.cc",
7588 "src/xnnpack/AlignedAllocator.h",
7589 ] + MICROKERNEL_BENCHMARK_HDRS,
7590 deps = MICROKERNEL_BENCHMARK_DEPS,
7591)
7592
7593xnnpack_benchmark(
Marat Dukhan8b024c92021-08-03 00:05:14 -07007594 name = "qu8_vmulc_bench",
7595 srcs = [
7596 "bench/qu8-vmulc.cc",
7597 "src/xnnpack/AlignedAllocator.h",
7598 ] + MICROKERNEL_BENCHMARK_HDRS,
7599 deps = MICROKERNEL_BENCHMARK_DEPS,
7600)
7601
7602xnnpack_benchmark(
Frank Barchard40d20fe2020-05-05 00:37:45 -07007603 name = "f16_igemm_bench",
7604 srcs = [
7605 "bench/f16-igemm.cc",
7606 "bench/conv.h",
Frank Barchard40d20fe2020-05-05 00:37:45 -07007607 "src/xnnpack/AlignedAllocator.h",
7608 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007609 deps = MICROKERNEL_BENCHMARK_DEPS + [
7610 ":indirection",
7611 ":packing",
7612 ],
Frank Barchard40d20fe2020-05-05 00:37:45 -07007613)
7614
7615xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007616 name = "f16_gemm_bench",
7617 srcs = [
7618 "bench/f16-gemm.cc",
7619 "bench/gemm.h",
7620 "src/xnnpack/AlignedAllocator.h",
7621 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007622 deps = MICROKERNEL_BENCHMARK_DEPS + [
7623 ":packing",
7624 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007625)
7626
7627xnnpack_benchmark(
Marat Dukhanbdb56f52020-02-05 21:42:49 -08007628 name = "f16_spmm_bench",
7629 srcs = [
7630 "bench/f16-spmm.cc",
Marat Dukhan1631e3e2020-12-06 19:29:31 -08007631 "bench/spmm.h",
Marat Dukhanbdb56f52020-02-05 21:42:49 -08007632 "src/xnnpack/AlignedAllocator.h",
7633 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanbdb56f52020-02-05 21:42:49 -08007634 deps = MICROKERNEL_BENCHMARK_DEPS,
7635)
7636
7637xnnpack_benchmark(
Marat Dukhan6674d692021-05-05 22:27:00 -07007638 name = "f16_vrelu_bench",
7639 srcs = [
7640 "bench/f16-vrelu.cc",
7641 "src/xnnpack/AlignedAllocator.h",
7642 ] + MICROKERNEL_BENCHMARK_HDRS,
7643 deps = MICROKERNEL_BENCHMARK_DEPS,
7644)
7645
7646xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007647 name = "f32_igemm_bench",
7648 srcs = [
7649 "bench/f32-igemm.cc",
7650 "bench/conv.h",
7651 "src/xnnpack/AlignedAllocator.h",
7652 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007653 deps = MICROKERNEL_BENCHMARK_DEPS + [
7654 ":indirection",
7655 ":packing",
7656 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007657)
7658
7659xnnpack_benchmark(
7660 name = "f32_conv_hwc_bench",
7661 srcs = [
7662 "bench/f32-conv-hwc.cc",
7663 "bench/dconv.h",
7664 "src/xnnpack/AlignedAllocator.h",
7665 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007666 deps = MICROKERNEL_BENCHMARK_DEPS + [
7667 ":packing",
7668 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007669)
7670
7671xnnpack_benchmark(
Marat Dukhan1f29b802020-05-15 23:46:39 -07007672 name = "f32_conv_hwc2chw_bench",
Erich Elsen563df5f2019-10-23 08:02:21 -07007673 srcs = [
Marat Dukhan1f29b802020-05-15 23:46:39 -07007674 "bench/f32-conv-hwc2chw.cc",
Erich Elsen563df5f2019-10-23 08:02:21 -07007675 "bench/dconv.h",
7676 "src/xnnpack/AlignedAllocator.h",
7677 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007678 deps = MICROKERNEL_BENCHMARK_DEPS + [
7679 ":packing",
7680 ],
Erich Elsen563df5f2019-10-23 08:02:21 -07007681)
7682
7683xnnpack_benchmark(
Frank Barchard5a599a62020-06-04 20:12:44 -07007684 name = "f16_dwconv_bench",
7685 srcs = [
7686 "bench/f16-dwconv.cc",
7687 "bench/dwconv.h",
Frank Barchard5a599a62020-06-04 20:12:44 -07007688 "src/xnnpack/AlignedAllocator.h",
7689 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007690 deps = MICROKERNEL_BENCHMARK_DEPS + [
7691 ":indirection",
7692 ":packing",
7693 ],
Frank Barchard5a599a62020-06-04 20:12:44 -07007694)
7695
7696xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007697 name = "f32_dwconv_bench",
7698 srcs = [
7699 "bench/f32-dwconv.cc",
7700 "bench/dwconv.h",
7701 "src/xnnpack/AlignedAllocator.h",
7702 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007703 deps = MICROKERNEL_BENCHMARK_DEPS + [
7704 ":indirection",
7705 ":packing",
7706 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007707)
7708
7709xnnpack_benchmark(
Marat Dukhanbf715f92020-10-23 20:17:00 -07007710 name = "f32_dwconv2d_chw_bench",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007711 srcs = [
Marat Dukhanbf715f92020-10-23 20:17:00 -07007712 "bench/f32-dwconv2d-chw.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007713 "bench/dwconv.h",
7714 "src/xnnpack/AlignedAllocator.h",
7715 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007716 deps = MICROKERNEL_BENCHMARK_DEPS + [
7717 ":indirection",
7718 ":packing",
7719 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007720)
7721
7722xnnpack_benchmark(
7723 name = "f32_gemm_bench",
7724 srcs = [
7725 "bench/f32-gemm.cc",
7726 "bench/gemm.h",
7727 "src/xnnpack/AlignedAllocator.h",
7728 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007729 copts = xnnpack_optional_ruy_copts(),
Marat Dukhanab582382020-07-06 13:32:08 -07007730 deps = MICROKERNEL_BENCHMARK_DEPS + [":packing"] + xnnpack_optional_ruy_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007731)
7732
7733xnnpack_benchmark(
Marat Dukhan4c4eb002019-12-08 21:27:49 -08007734 name = "f32_raddexpminusmax_bench",
7735 srcs = [
7736 "bench/f32-raddexpminusmax.cc",
7737 "src/xnnpack/AlignedAllocator.h",
7738 ] + MICROKERNEL_BENCHMARK_HDRS,
7739 deps = MICROKERNEL_BENCHMARK_DEPS,
7740)
7741
7742xnnpack_benchmark(
7743 name = "f32_raddextexp_bench",
7744 srcs = [
7745 "bench/f32-raddextexp.cc",
7746 "src/xnnpack/AlignedAllocator.h",
7747 ] + MICROKERNEL_BENCHMARK_HDRS,
7748 deps = MICROKERNEL_BENCHMARK_DEPS,
7749)
7750
7751xnnpack_benchmark(
7752 name = "f32_raddstoreexpminusmax_bench",
7753 srcs = [
7754 "bench/f32-raddstoreexpminusmax.cc",
7755 "src/xnnpack/AlignedAllocator.h",
7756 ] + MICROKERNEL_BENCHMARK_HDRS,
7757 deps = MICROKERNEL_BENCHMARK_DEPS,
7758)
7759
7760xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007761 name = "f32_rmax_bench",
7762 srcs = [
7763 "bench/f32-rmax.cc",
7764 "src/xnnpack/AlignedAllocator.h",
7765 ] + MICROKERNEL_BENCHMARK_HDRS,
7766 deps = MICROKERNEL_BENCHMARK_DEPS,
7767)
7768
7769xnnpack_benchmark(
7770 name = "f32_spmm_bench",
7771 srcs = [
7772 "bench/f32-spmm.cc",
Marat Dukhan1631e3e2020-12-06 19:29:31 -08007773 "bench/spmm.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07007774 "src/xnnpack/AlignedAllocator.h",
7775 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07007776 deps = MICROKERNEL_BENCHMARK_DEPS,
7777)
7778
7779xnnpack_benchmark(
Marat Dukhanfd8e6892020-01-27 15:25:25 -08007780 name = "f32_softmax_bench",
Marat Dukhan4a4a7fa2019-10-21 13:46:14 -07007781 srcs = [
Marat Dukhanfd8e6892020-01-27 15:25:25 -08007782 "bench/f32-softmax.cc",
Marat Dukhan4a4a7fa2019-10-21 13:46:14 -07007783 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhan10a38082020-04-17 03:58:35 -07007784 copts = xnnpack_optional_dnnl_copts(),
Marat Dukhan8d3c6932020-03-06 20:27:27 -08007785 deps = MICROKERNEL_BENCHMARK_DEPS + xnnpack_optional_dnnl_deps(),
Marat Dukhan4a4a7fa2019-10-21 13:46:14 -07007786)
7787
7788xnnpack_benchmark(
Marat Dukhaned6baaf2020-12-01 15:07:08 -08007789 name = "f32_velu_bench",
7790 srcs = [
7791 "bench/f32-velu.cc",
7792 "src/xnnpack/AlignedAllocator.h",
7793 ] + MICROKERNEL_BENCHMARK_HDRS,
7794 deps = MICROKERNEL_BENCHMARK_DEPS,
7795)
7796
7797xnnpack_benchmark(
Marat Dukhan6674d692021-05-05 22:27:00 -07007798 name = "f32_vhswish_bench",
7799 srcs = [
7800 "bench/f32-vhswish.cc",
7801 "src/xnnpack/AlignedAllocator.h",
7802 ] + MICROKERNEL_BENCHMARK_HDRS,
7803 deps = MICROKERNEL_BENCHMARK_DEPS,
7804)
7805
7806xnnpack_benchmark(
Marat Dukhan7c74aff2021-08-07 15:44:27 -07007807 name = "f32_vlrelu_bench",
7808 srcs = [
7809 "bench/f32-vlrelu.cc",
7810 "src/xnnpack/AlignedAllocator.h",
7811 ] + MICROKERNEL_BENCHMARK_HDRS,
7812 deps = MICROKERNEL_BENCHMARK_DEPS,
7813)
7814
7815xnnpack_benchmark(
Marat Dukhan6674d692021-05-05 22:27:00 -07007816 name = "f32_vrelu_bench",
7817 srcs = [
7818 "bench/f32-vrelu.cc",
7819 "src/xnnpack/AlignedAllocator.h",
7820 ] + MICROKERNEL_BENCHMARK_HDRS,
7821 deps = MICROKERNEL_BENCHMARK_DEPS,
7822)
7823
7824xnnpack_benchmark(
Marat Dukhan4c4eb002019-12-08 21:27:49 -08007825 name = "f32_vscaleexpminusmax_bench",
7826 srcs = [
7827 "bench/f32-vscaleexpminusmax.cc",
7828 "src/xnnpack/AlignedAllocator.h",
7829 ] + MICROKERNEL_BENCHMARK_HDRS,
7830 deps = MICROKERNEL_BENCHMARK_DEPS,
7831)
7832
7833xnnpack_benchmark(
7834 name = "f32_vscaleextexp_bench",
7835 srcs = [
7836 "bench/f32-vscaleextexp.cc",
7837 "src/xnnpack/AlignedAllocator.h",
7838 ] + MICROKERNEL_BENCHMARK_HDRS,
7839 deps = MICROKERNEL_BENCHMARK_DEPS,
7840)
7841
7842xnnpack_benchmark(
Marat Dukhan6674d692021-05-05 22:27:00 -07007843 name = "f32_vsigmoid_bench",
7844 srcs = [
7845 "bench/f32-vsigmoid.cc",
7846 "src/xnnpack/AlignedAllocator.h",
7847 ] + MICROKERNEL_BENCHMARK_HDRS,
7848 deps = MICROKERNEL_BENCHMARK_DEPS,
7849)
7850
7851xnnpack_benchmark(
Marat Dukhanf4db2f32020-06-30 10:55:30 -07007852 name = "f32_vsqrt_bench",
7853 srcs = [
7854 "bench/f32-vsqrt.cc",
7855 "src/xnnpack/AlignedAllocator.h",
7856 ] + MICROKERNEL_BENCHMARK_HDRS,
7857 deps = MICROKERNEL_BENCHMARK_DEPS,
7858)
7859
7860xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007861 name = "f32_im2col_gemm_bench",
7862 srcs = [
7863 "bench/f32-im2col-gemm.cc",
7864 "bench/conv.h",
7865 "src/xnnpack/AlignedAllocator.h",
7866 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07007867 deps = MICROKERNEL_BENCHMARK_DEPS + [
7868 ":im2col",
7869 ":packing",
7870 ],
Marat Dukhan08c4a432019-10-03 09:29:21 -07007871)
7872
Marat Dukhanfe7acb62020-03-09 19:30:05 -07007873xnnpack_benchmark(
Marat Dukhanffbf96a2020-05-14 02:59:08 -07007874 name = "rounding_bench",
7875 srcs = [
7876 "bench/rounding.cc",
Marat Dukhanffbf96a2020-05-14 02:59:08 -07007877 "src/xnnpack/AlignedAllocator.h",
Frank Barchard04336c12020-10-22 16:48:55 -07007878 "src/xnnpack/math-stubs.h",
Marat Dukhanffbf96a2020-05-14 02:59:08 -07007879 ] + MICROKERNEL_BENCHMARK_HDRS,
7880 deps = MICROKERNEL_BENCHMARK_DEPS,
7881)
7882
Marat Dukhan08c4a432019-10-03 09:29:21 -07007883########################### Benchmarks for operators ###########################
7884
7885xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007886 name = "average_pooling_bench",
7887 srcs = ["bench/average-pooling.cc"],
Marat Dukhan7a16d8b2020-03-11 04:22:44 -07007888 copts = xnnpack_optional_tflite_copts(),
Marat Dukhan8ea0b072020-04-23 16:12:18 -07007889 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007890 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007891)
7892
7893xnnpack_benchmark(
Marat Dukhan87727142020-06-24 15:24:10 -07007894 name = "bankers_rounding_bench",
7895 srcs = ["bench/bankers-rounding.cc"],
7896 copts = xnnpack_optional_tflite_copts(),
7897 tags = ["nowin32"],
7898 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7899)
7900
7901xnnpack_benchmark(
7902 name = "ceiling_bench",
7903 srcs = ["bench/ceiling.cc"],
7904 copts = xnnpack_optional_tflite_copts(),
7905 tags = ["nowin32"],
7906 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7907)
7908
7909xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007910 name = "channel_shuffle_bench",
7911 srcs = ["bench/channel-shuffle.cc"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007912 deps = OPERATOR_BENCHMARK_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07007913)
7914
7915xnnpack_benchmark(
7916 name = "convolution_bench",
7917 srcs = ["bench/convolution.cc"],
7918 copts = xnnpack_optional_tflite_copts() + xnnpack_optional_armcl_copts(),
Marat Dukhan8ea0b072020-04-23 16:12:18 -07007919 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007920 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps() + xnnpack_optional_armcl_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007921)
7922
7923xnnpack_benchmark(
7924 name = "deconvolution_bench",
7925 srcs = ["bench/deconvolution.cc"],
7926 copts = xnnpack_optional_tflite_copts(),
Marat Dukhan8ea0b072020-04-23 16:12:18 -07007927 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007928 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007929)
7930
7931xnnpack_benchmark(
Marat Dukhanb6bd4bc2020-12-01 17:01:40 -08007932 name = "elu_bench",
7933 srcs = ["bench/elu.cc"],
7934 copts = xnnpack_optional_tflite_copts(),
7935 tags = ["nowin32"],
7936 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7937)
7938
7939xnnpack_benchmark(
Marat Dukhan87727142020-06-24 15:24:10 -07007940 name = "floor_bench",
7941 srcs = ["bench/floor.cc"],
7942 copts = xnnpack_optional_tflite_copts(),
7943 tags = ["nowin32"],
7944 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7945)
7946
7947xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007948 name = "global_average_pooling_bench",
7949 srcs = ["bench/global-average-pooling.cc"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007950 deps = OPERATOR_BENCHMARK_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07007951)
7952
7953xnnpack_benchmark(
Marat Dukhanad352602020-06-25 21:50:54 -07007954 name = "hardswish_bench",
7955 srcs = ["bench/hardswish.cc"],
7956 copts = xnnpack_optional_tflite_copts(),
7957 tags = ["nowin32"],
7958 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7959)
7960
7961xnnpack_benchmark(
Marat Dukhan08c4a432019-10-03 09:29:21 -07007962 name = "max_pooling_bench",
7963 srcs = ["bench/max-pooling.cc"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007964 deps = OPERATOR_BENCHMARK_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07007965)
7966
7967xnnpack_benchmark(
7968 name = "sigmoid_bench",
7969 srcs = ["bench/sigmoid.cc"],
Marat Dukhanc3b9e862019-11-17 13:18:54 -08007970 copts = xnnpack_optional_tflite_copts(),
Marat Dukhanca2ba702020-04-24 01:31:47 -07007971 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007972 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007973)
7974
7975xnnpack_benchmark(
Marat Dukhan95b22432019-10-30 16:30:14 -07007976 name = "prelu_bench",
7977 srcs = ["bench/prelu.cc"],
7978 copts = xnnpack_optional_tflite_copts(),
Marat Dukhan8ea0b072020-04-23 16:12:18 -07007979 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007980 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
Marat Dukhan95b22432019-10-30 16:30:14 -07007981)
7982
7983xnnpack_benchmark(
Marat Dukhanfd8e6892020-01-27 15:25:25 -08007984 name = "softmax_bench",
7985 srcs = ["bench/softmax.cc"],
Marat Dukhan9c0db962020-01-28 12:30:14 -08007986 copts = xnnpack_optional_tflite_copts(),
Marat Dukhanca2ba702020-04-24 01:31:47 -07007987 tags = ["nowin32"],
Marat Dukhan1b354632020-03-23 12:50:22 -07007988 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
Marat Dukhan08c4a432019-10-03 09:29:21 -07007989)
7990
Marat Dukhan87727142020-06-24 15:24:10 -07007991xnnpack_benchmark(
Marat Dukhan6804bbd2020-06-30 19:26:11 -07007992 name = "square_root_bench",
7993 srcs = ["bench/square-root.cc"],
7994 copts = xnnpack_optional_tflite_copts(),
7995 tags = ["nowin32"],
7996 deps = OPERATOR_BENCHMARK_DEPS + xnnpack_optional_tflite_deps(),
7997)
7998
7999xnnpack_benchmark(
Marat Dukhan87727142020-06-24 15:24:10 -07008000 name = "truncation_bench",
8001 srcs = ["bench/truncation.cc"],
8002 deps = OPERATOR_BENCHMARK_DEPS,
8003)
8004
Marat Dukhanc068bb62019-10-04 13:24:39 -07008005############################# End-to-end benchmarks ############################
8006
8007cc_library(
Marat Dukhan270a2c42020-06-26 16:45:52 -07008008 name = "fp32_mobilenet_v1",
8009 srcs = ["models/fp32-mobilenet-v1.cc"],
Marat Dukhanc068bb62019-10-04 13:24:39 -07008010 hdrs = ["models/models.h"],
Marat Dukhana84e40b2019-12-11 15:38:03 -08008011 copts = xnnpack_std_cxxopts(),
Marat Dukhanc068bb62019-10-04 13:24:39 -07008012 linkstatic = True,
8013 deps = [
8014 ":XNNPACK",
8015 "@pthreadpool",
8016 ],
8017)
8018
8019cc_library(
Marat Dukhan4cea2322021-03-09 09:35:36 -08008020 name = "fp32_sparse_mobilenet_v1",
8021 srcs = ["models/fp32-sparse-mobilenet-v1.cc"],
8022 hdrs = ["models/models.h"],
8023 copts = xnnpack_std_cxxopts(),
8024 linkstatic = True,
8025 deps = [
8026 ":XNNPACK",
8027 "@pthreadpool",
8028 ],
8029)
8030
8031cc_library(
Marat Dukhan270a2c42020-06-26 16:45:52 -07008032 name = "fp16_mobilenet_v1",
8033 srcs = ["models/fp16-mobilenet-v1.cc"],
8034 hdrs = ["models/models.h"],
8035 copts = xnnpack_std_cxxopts(),
8036 linkstatic = True,
8037 deps = [
8038 ":XNNPACK",
8039 "@FP16",
8040 "@pthreadpool",
8041 ],
8042)
8043
8044cc_library(
Marat Dukhane252f922021-08-31 08:57:41 -07008045 name = "qc8_mobilenet_v1",
8046 srcs = ["models/qc8-mobilenet-v1.cc"],
8047 hdrs = ["models/models.h"],
8048 copts = xnnpack_std_cxxopts(),
8049 linkstatic = True,
8050 deps = [
8051 ":XNNPACK",
8052 "@pthreadpool",
8053 ],
8054)
8055
8056cc_library(
8057 name = "qc8_mobilenet_v2",
8058 srcs = ["models/qc8-mobilenet-v2.cc"],
8059 hdrs = ["models/models.h"],
8060 copts = xnnpack_std_cxxopts(),
8061 linkstatic = True,
8062 deps = [
8063 ":XNNPACK",
8064 "@pthreadpool",
8065 ],
8066)
8067
8068cc_library(
Marat Dukhan0743cdf2020-08-04 18:52:07 -07008069 name = "qs8_mobilenet_v1",
8070 srcs = ["models/qs8-mobilenet-v1.cc"],
8071 hdrs = ["models/models.h"],
8072 copts = xnnpack_std_cxxopts(),
8073 linkstatic = True,
8074 deps = [
8075 ":XNNPACK",
8076 "@pthreadpool",
8077 ],
8078)
8079
8080cc_library(
Marat Dukhan70a96182020-09-03 17:13:58 -07008081 name = "qs8_mobilenet_v2",
8082 srcs = ["models/qs8-mobilenet-v2.cc"],
8083 hdrs = ["models/models.h"],
8084 copts = xnnpack_std_cxxopts(),
8085 linkstatic = True,
8086 deps = [
8087 ":XNNPACK",
8088 "@pthreadpool",
8089 ],
8090)
8091
8092cc_library(
Marat Dukhan12a23bb2021-03-08 08:13:21 -08008093 name = "qu8_mobilenet_v1",
8094 srcs = ["models/qu8-mobilenet-v1.cc"],
8095 hdrs = ["models/models.h"],
8096 copts = xnnpack_std_cxxopts(),
8097 linkstatic = True,
8098 deps = [
8099 ":XNNPACK",
8100 "@pthreadpool",
8101 ],
8102)
8103
8104cc_library(
Marat Dukhan036b2b12021-07-21 01:12:58 -07008105 name = "qu8_mobilenet_v2",
8106 srcs = ["models/qu8-mobilenet-v2.cc"],
8107 hdrs = ["models/models.h"],
8108 copts = xnnpack_std_cxxopts(),
8109 linkstatic = True,
8110 deps = [
8111 ":XNNPACK",
8112 "@pthreadpool",
8113 ],
8114)
8115
8116cc_library(
Marat Dukhan270a2c42020-06-26 16:45:52 -07008117 name = "fp32_mobilenet_v2",
8118 srcs = ["models/fp32-mobilenet-v2.cc"],
Marat Dukhanc068bb62019-10-04 13:24:39 -07008119 hdrs = ["models/models.h"],
Marat Dukhana84e40b2019-12-11 15:38:03 -08008120 copts = xnnpack_std_cxxopts(),
Marat Dukhanc068bb62019-10-04 13:24:39 -07008121 linkstatic = True,
8122 deps = [
8123 ":XNNPACK",
8124 "@pthreadpool",
8125 ],
8126)
8127
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008128cc_library(
Marat Dukhan4cea2322021-03-09 09:35:36 -08008129 name = "fp32_sparse_mobilenet_v2",
8130 srcs = ["models/fp32-sparse-mobilenet-v2.cc"],
8131 hdrs = ["models/models.h"],
8132 copts = xnnpack_std_cxxopts(),
8133 linkstatic = True,
8134 deps = [
8135 ":XNNPACK",
8136 "@pthreadpool",
8137 ],
8138)
8139
8140cc_library(
Marat Dukhan270a2c42020-06-26 16:45:52 -07008141 name = "fp16_mobilenet_v2",
8142 srcs = ["models/fp16-mobilenet-v2.cc"],
8143 hdrs = ["models/models.h"],
8144 copts = xnnpack_std_cxxopts(),
8145 linkstatic = True,
8146 deps = [
8147 ":XNNPACK",
8148 "@FP16",
8149 "@pthreadpool",
8150 ],
8151)
8152
8153cc_library(
8154 name = "fp32_mobilenet_v3_large",
8155 srcs = ["models/fp32-mobilenet-v3-large.cc"],
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008156 hdrs = ["models/models.h"],
Marat Dukhana84e40b2019-12-11 15:38:03 -08008157 copts = xnnpack_std_cxxopts(),
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008158 linkstatic = True,
8159 deps = [
8160 ":XNNPACK",
8161 "@pthreadpool",
8162 ],
8163)
8164
8165cc_library(
Marat Dukhan4cea2322021-03-09 09:35:36 -08008166 name = "fp32_sparse_mobilenet_v3_large",
8167 srcs = ["models/fp32-sparse-mobilenet-v3-large.cc"],
8168 hdrs = ["models/models.h"],
8169 copts = xnnpack_std_cxxopts(),
8170 linkstatic = True,
8171 deps = [
8172 ":XNNPACK",
8173 "@pthreadpool",
8174 ],
8175)
8176
8177cc_library(
Marat Dukhan66f3ccd2020-09-14 16:09:38 -07008178 name = "fp16_mobilenet_v3_large",
8179 srcs = ["models/fp16-mobilenet-v3-large.cc"],
8180 hdrs = ["models/models.h"],
8181 copts = xnnpack_std_cxxopts(),
8182 linkstatic = True,
8183 deps = [
8184 ":XNNPACK",
8185 "@FP16",
8186 "@pthreadpool",
8187 ],
8188)
8189
8190cc_library(
Marat Dukhan270a2c42020-06-26 16:45:52 -07008191 name = "fp32_mobilenet_v3_small",
8192 srcs = ["models/fp32-mobilenet-v3-small.cc"],
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008193 hdrs = ["models/models.h"],
Marat Dukhana84e40b2019-12-11 15:38:03 -08008194 copts = xnnpack_std_cxxopts(),
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008195 linkstatic = True,
8196 deps = [
8197 ":XNNPACK",
8198 "@pthreadpool",
8199 ],
8200)
8201
Marat Dukhan66f3ccd2020-09-14 16:09:38 -07008202cc_library(
Marat Dukhan4cea2322021-03-09 09:35:36 -08008203 name = "fp32_sparse_mobilenet_v3_small",
8204 srcs = ["models/fp32-sparse-mobilenet-v3-small.cc"],
8205 hdrs = ["models/models.h"],
8206 copts = xnnpack_std_cxxopts(),
8207 linkstatic = True,
8208 deps = [
8209 ":XNNPACK",
8210 "@pthreadpool",
8211 ],
8212)
8213
8214cc_library(
Marat Dukhan66f3ccd2020-09-14 16:09:38 -07008215 name = "fp16_mobilenet_v3_small",
8216 srcs = ["models/fp16-mobilenet-v3-small.cc"],
8217 hdrs = ["models/models.h"],
8218 copts = xnnpack_std_cxxopts(),
8219 linkstatic = True,
8220 deps = [
8221 ":XNNPACK",
8222 "@FP16",
8223 "@pthreadpool",
8224 ],
8225)
8226
Marat Dukhanc068bb62019-10-04 13:24:39 -07008227xnnpack_benchmark(
Marat Dukhanef4416e2019-10-31 13:44:40 -07008228 name = "f32_dwconv_e2e_bench",
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008229 srcs = [
8230 "bench/f32-dwconv-e2e.cc",
8231 "bench/end2end.h",
8232 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhanef4416e2019-10-31 13:44:40 -07008233 deps = MICROKERNEL_BENCHMARK_DEPS + [
8234 ":XNNPACK",
Marat Dukhan270a2c42020-06-26 16:45:52 -07008235 ":fp32_mobilenet_v1",
8236 ":fp32_mobilenet_v2",
8237 ":fp32_mobilenet_v3_large",
8238 ":fp32_mobilenet_v3_small",
Marat Dukhanef4416e2019-10-31 13:44:40 -07008239 ],
8240)
8241
8242xnnpack_benchmark(
Marat Dukhan5f18d262019-10-31 10:24:14 -07008243 name = "f32_gemm_e2e_bench",
Marat Dukhanc08cdf52019-12-09 09:17:51 -08008244 srcs = [
8245 "bench/f32-gemm-e2e.cc",
8246 "bench/end2end.h",
8247 ] + MICROKERNEL_BENCHMARK_HDRS,
Marat Dukhan5f18d262019-10-31 10:24:14 -07008248 deps = MICROKERNEL_BENCHMARK_DEPS + [
8249 ":XNNPACK",
Marat Dukhan270a2c42020-06-26 16:45:52 -07008250 ":fp32_mobilenet_v1",
8251 ":fp32_mobilenet_v2",
8252 ":fp32_mobilenet_v3_large",
8253 ":fp32_mobilenet_v3_small",
Marat Dukhan5f18d262019-10-31 10:24:14 -07008254 ],
8255)
8256
8257xnnpack_benchmark(
Marat Dukhanbbfc6d32021-07-26 18:31:02 -07008258 name = "qs8_dwconv_e2e_bench",
8259 srcs = [
8260 "bench/qs8-dwconv-e2e.cc",
8261 "bench/end2end.h",
8262 ] + MICROKERNEL_BENCHMARK_HDRS,
8263 deps = MICROKERNEL_BENCHMARK_DEPS + [
8264 ":XNNPACK",
8265 ":qs8_mobilenet_v1",
8266 ":qs8_mobilenet_v2",
8267 ],
8268)
8269
8270xnnpack_benchmark(
Frank Barcharddc909cb2021-02-08 13:59:31 -08008271 name = "qs8_gemm_e2e_bench",
8272 srcs = [
8273 "bench/qs8-gemm-e2e.cc",
8274 "bench/end2end.h",
8275 ] + MICROKERNEL_BENCHMARK_HDRS,
8276 deps = MICROKERNEL_BENCHMARK_DEPS + [
8277 ":XNNPACK",
8278 ":qs8_mobilenet_v1",
8279 ":qs8_mobilenet_v2",
8280 ],
8281)
8282
8283xnnpack_benchmark(
Frank Barchard9098aba2021-08-12 12:20:03 -07008284 name = "qu8_gemm_e2e_bench",
8285 srcs = [
8286 "bench/qu8-gemm-e2e.cc",
8287 "bench/end2end.h",
8288 ] + MICROKERNEL_BENCHMARK_HDRS,
8289 deps = MICROKERNEL_BENCHMARK_DEPS + [
8290 ":XNNPACK",
8291 ":qu8_mobilenet_v1",
8292 ":qu8_mobilenet_v2",
8293 ],
8294)
8295
8296xnnpack_benchmark(
Marat Dukhan6084fb82021-07-27 07:45:02 -07008297 name = "qu8_dwconv_e2e_bench",
8298 srcs = [
8299 "bench/qu8-dwconv-e2e.cc",
8300 "bench/end2end.h",
8301 ] + MICROKERNEL_BENCHMARK_HDRS,
8302 deps = MICROKERNEL_BENCHMARK_DEPS + [
8303 ":XNNPACK",
8304 ":qu8_mobilenet_v1",
8305 ":qu8_mobilenet_v2",
8306 ],
8307)
8308
8309xnnpack_benchmark(
Marat Dukhanc068bb62019-10-04 13:24:39 -07008310 name = "end2end_bench",
8311 srcs = ["bench/end2end.cc"],
8312 deps = [
8313 ":XNNPACK",
Frank Barchardc712fa42019-10-31 14:00:21 -07008314 ":bench_utils",
Marat Dukhan270a2c42020-06-26 16:45:52 -07008315 ":fp16_mobilenet_v1",
8316 ":fp16_mobilenet_v2",
Marat Dukhan66f3ccd2020-09-14 16:09:38 -07008317 ":fp16_mobilenet_v3_large",
8318 ":fp16_mobilenet_v3_small",
Marat Dukhan270a2c42020-06-26 16:45:52 -07008319 ":fp32_mobilenet_v1",
8320 ":fp32_mobilenet_v2",
8321 ":fp32_mobilenet_v3_large",
8322 ":fp32_mobilenet_v3_small",
Marat Dukhan4cea2322021-03-09 09:35:36 -08008323 ":fp32_sparse_mobilenet_v1",
8324 ":fp32_sparse_mobilenet_v2",
8325 ":fp32_sparse_mobilenet_v3_large",
8326 ":fp32_sparse_mobilenet_v3_small",
Marat Dukhane252f922021-08-31 08:57:41 -07008327 ":qc8_mobilenet_v1",
8328 ":qc8_mobilenet_v2",
Marat Dukhan0743cdf2020-08-04 18:52:07 -07008329 ":qs8_mobilenet_v1",
Marat Dukhan70a96182020-09-03 17:13:58 -07008330 ":qs8_mobilenet_v2",
Marat Dukhan12a23bb2021-03-08 08:13:21 -08008331 ":qu8_mobilenet_v1",
Marat Dukhan036b2b12021-07-21 01:12:58 -07008332 ":qu8_mobilenet_v2",
Marat Dukhanc068bb62019-10-04 13:24:39 -07008333 "@pthreadpool",
8334 ],
8335)
8336
Marat Dukhan6adff4e2019-10-14 18:32:07 -07008337#################### Accuracy evaluation for math functions ####################
8338
8339xnnpack_benchmark(
Marat Dukhancf67ec62020-12-14 09:56:37 -08008340 name = "f32_exp_ulp_eval",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07008341 srcs = [
Marat Dukhancf67ec62020-12-14 09:56:37 -08008342 "eval/f32-exp-ulp.cc",
Marat Dukhan6adff4e2019-10-14 18:32:07 -07008343 "src/xnnpack/AlignedAllocator.h",
8344 ] + ACCURACY_EVAL_HDRS,
Marat Dukhan3a305212020-12-06 19:24:27 -08008345 deps = ACCURACY_EVAL_DEPS + [
8346 ":bench_utils",
8347 "@cpuinfo",
8348 ],
Marat Dukhan6adff4e2019-10-14 18:32:07 -07008349)
8350
Marat Dukhan515c9772019-10-17 18:07:57 -07008351xnnpack_benchmark(
Marat Dukhancf67ec62020-12-14 09:56:37 -08008352 name = "f32_expminus_ulp_eval",
Marat Dukhan515c9772019-10-17 18:07:57 -07008353 srcs = [
Marat Dukhancf67ec62020-12-14 09:56:37 -08008354 "eval/f32-expminus-ulp.cc",
Marat Dukhan515c9772019-10-17 18:07:57 -07008355 "src/xnnpack/AlignedAllocator.h",
8356 ] + ACCURACY_EVAL_HDRS,
Marat Dukhan3a305212020-12-06 19:24:27 -08008357 deps = ACCURACY_EVAL_DEPS + [
8358 ":bench_utils",
8359 "@cpuinfo",
8360 ],
Marat Dukhan515c9772019-10-17 18:07:57 -07008361)
8362
Marat Dukhan98ba4412019-10-23 02:14:28 -07008363xnnpack_benchmark(
Marat Dukhancf67ec62020-12-14 09:56:37 -08008364 name = "f32_expm1minus_ulp_eval",
Marat Dukhana438aca2020-11-20 15:45:01 -08008365 srcs = [
Marat Dukhancf67ec62020-12-14 09:56:37 -08008366 "eval/f32-expm1minus-ulp.cc",
Marat Dukhana438aca2020-11-20 15:45:01 -08008367 "src/xnnpack/AlignedAllocator.h",
8368 ] + ACCURACY_EVAL_HDRS,
Marat Dukhande390d42020-11-29 19:32:18 -08008369 deps = ACCURACY_EVAL_DEPS + [
8370 ":bench_utils",
Marat Dukhan3a305212020-12-06 19:24:27 -08008371 "@cpuinfo",
Marat Dukhande390d42020-11-29 19:32:18 -08008372 ],
Marat Dukhana438aca2020-11-20 15:45:01 -08008373)
8374
8375xnnpack_benchmark(
Marat Dukhancf67ec62020-12-14 09:56:37 -08008376 name = "f32_extexp_ulp_eval",
Marat Dukhan98ba4412019-10-23 02:14:28 -07008377 srcs = [
Marat Dukhancf67ec62020-12-14 09:56:37 -08008378 "eval/f32-extexp-ulp.cc",
Marat Dukhan98ba4412019-10-23 02:14:28 -07008379 "src/xnnpack/AlignedAllocator.h",
8380 ] + ACCURACY_EVAL_HDRS,
Marat Dukhan3a305212020-12-06 19:24:27 -08008381 deps = ACCURACY_EVAL_DEPS + [
8382 ":bench_utils",
8383 "@cpuinfo",
8384 ],
Marat Dukhan98ba4412019-10-23 02:14:28 -07008385)
8386
Marat Dukhanf44f0222020-12-14 11:53:27 -08008387xnnpack_benchmark(
8388 name = "f32_sigmoid_ulp_eval",
8389 srcs = [
8390 "eval/f32-sigmoid-ulp.cc",
8391 "src/xnnpack/AlignedAllocator.h",
8392 ] + ACCURACY_EVAL_HDRS,
8393 deps = ACCURACY_EVAL_DEPS + [
8394 ":bench_utils",
8395 "@cpuinfo",
8396 ],
8397)
8398
8399xnnpack_benchmark(
8400 name = "f32_sqrt_ulp_eval",
8401 srcs = [
8402 "eval/f32-sqrt-ulp.cc",
8403 "src/xnnpack/AlignedAllocator.h",
8404 ] + ACCURACY_EVAL_HDRS,
8405 deps = ACCURACY_EVAL_DEPS + [
8406 ":bench_utils",
8407 "@cpuinfo",
8408 ],
8409)
8410
8411################### Accuracy verification for math functions ##################
8412
8413xnnpack_unit_test(
Marat Dukhanf7291fc2020-12-15 11:02:50 -08008414 name = "f32_exp_eval",
8415 srcs = [
8416 "eval/f32-exp.cc",
8417 "src/xnnpack/AlignedAllocator.h",
8418 "src/xnnpack/math-stubs.h",
8419 ] + MICROKERNEL_TEST_HDRS,
8420 automatic = False,
8421 deps = MICROKERNEL_TEST_DEPS,
8422)
8423
8424xnnpack_unit_test(
Marat Dukhanf44f0222020-12-14 11:53:27 -08008425 name = "f32_expm1minus_eval",
8426 srcs = [
8427 "eval/f32-expm1minus.cc",
8428 "src/xnnpack/AlignedAllocator.h",
8429 "src/xnnpack/math-stubs.h",
8430 ] + MICROKERNEL_TEST_HDRS,
8431 automatic = False,
8432 deps = MICROKERNEL_TEST_DEPS,
8433)
8434
Marat Dukhan8853b822020-05-07 12:19:01 -07008435xnnpack_unit_test(
Marat Dukhand28a5a22020-12-14 15:27:22 -08008436 name = "f32_expminus_eval",
8437 srcs = [
8438 "eval/f32-expminus.cc",
8439 "src/xnnpack/AlignedAllocator.h",
8440 "src/xnnpack/math-stubs.h",
8441 ] + MICROKERNEL_TEST_HDRS,
8442 automatic = False,
8443 deps = MICROKERNEL_TEST_DEPS,
8444)
8445
8446xnnpack_unit_test(
Marat Dukhan8853b822020-05-07 12:19:01 -07008447 name = "f32_roundne_eval",
8448 srcs = [
8449 "eval/f32-roundne.cc",
8450 "src/xnnpack/AlignedAllocator.h",
8451 "src/xnnpack/math-stubs.h",
8452 ] + MICROKERNEL_TEST_HDRS,
Marat Dukhan22eed3d2020-05-11 20:13:37 -07008453 automatic = False,
Marat Dukhan8853b822020-05-07 12:19:01 -07008454 deps = MICROKERNEL_TEST_DEPS,
8455)
8456
Marat Dukhan2dbb9442020-05-12 20:43:43 -07008457xnnpack_unit_test(
Marat Dukhanc9852ba2020-05-13 17:21:29 -07008458 name = "f32_roundd_eval",
8459 srcs = [
8460 "eval/f32-roundd.cc",
8461 "src/xnnpack/AlignedAllocator.h",
8462 "src/xnnpack/math-stubs.h",
8463 ] + MICROKERNEL_TEST_HDRS,
8464 automatic = False,
8465 deps = MICROKERNEL_TEST_DEPS,
8466)
8467
8468xnnpack_unit_test(
8469 name = "f32_roundu_eval",
8470 srcs = [
8471 "eval/f32-roundu.cc",
8472 "src/xnnpack/AlignedAllocator.h",
8473 "src/xnnpack/math-stubs.h",
8474 ] + MICROKERNEL_TEST_HDRS,
8475 automatic = False,
8476 deps = MICROKERNEL_TEST_DEPS,
8477)
8478
8479xnnpack_unit_test(
Marat Dukhan2dbb9442020-05-12 20:43:43 -07008480 name = "f32_roundz_eval",
8481 srcs = [
8482 "eval/f32-roundz.cc",
8483 "src/xnnpack/AlignedAllocator.h",
8484 "src/xnnpack/math-stubs.h",
8485 ] + MICROKERNEL_TEST_HDRS,
Marat Dukhanc9852ba2020-05-13 17:21:29 -07008486 automatic = False,
Marat Dukhan2dbb9442020-05-12 20:43:43 -07008487 deps = MICROKERNEL_TEST_DEPS,
8488)
8489
Marat Dukhan08c4a432019-10-03 09:29:21 -07008490######################### Unit tests for micro-kernels #########################
8491
8492xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07008493 name = "f16_dwconv_minmax_test",
8494 srcs = [
8495 "test/f16-dwconv-minmax.cc",
8496 "test/dwconv-microkernel-tester.h",
8497 "src/xnnpack/AlignedAllocator.h",
8498 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
8499 deps = MICROKERNEL_TEST_DEPS + [":packing"],
8500)
8501
8502xnnpack_unit_test(
8503 name = "f16_gavgpool_minmax_test",
8504 srcs = [
8505 "test/f16-gavgpool-minmax.cc",
8506 "test/gavgpool-microkernel-tester.h",
8507 "src/xnnpack/AlignedAllocator.h",
8508 ] + MICROKERNEL_TEST_HDRS,
8509 deps = MICROKERNEL_TEST_DEPS,
8510)
8511
8512xnnpack_unit_test(
Marat Dukhande06f492020-04-09 00:19:31 -07008513 name = "f16_gemm_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008514 srcs = [
Marat Dukhande06f492020-04-09 00:19:31 -07008515 "test/f16-gemm-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008516 "test/gemm-microkernel-tester.h",
8517 "src/xnnpack/AlignedAllocator.h",
8518 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008519 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008520)
8521
8522xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07008523 name = "f16_igemm_minmax_test",
8524 srcs = [
8525 "test/f16-igemm-minmax.cc",
8526 "test/gemm-microkernel-tester.h",
8527 "src/xnnpack/AlignedAllocator.h",
8528 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
8529 deps = MICROKERNEL_TEST_DEPS + [":packing"],
8530)
8531
8532xnnpack_unit_test(
Marat Dukhan355ab432020-04-09 19:01:52 -07008533 name = "f16_spmm_minmax_test",
Marat Dukhanbdb56f52020-02-05 21:42:49 -08008534 srcs = [
Marat Dukhan355ab432020-04-09 19:01:52 -07008535 "test/f16-spmm-minmax.cc",
Marat Dukhanbdb56f52020-02-05 21:42:49 -08008536 "test/spmm-microkernel-tester.h",
8537 "src/xnnpack/AlignedAllocator.h",
8538 ] + MICROKERNEL_TEST_HDRS,
8539 deps = MICROKERNEL_TEST_DEPS,
8540)
8541
8542xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07008543 name = "f16_vadd_minmax_test",
8544 srcs = [
8545 "test/f16-vadd-minmax.cc",
8546 "test/vbinary-microkernel-tester.h",
8547 ] + MICROKERNEL_TEST_HDRS,
8548 deps = MICROKERNEL_TEST_DEPS,
8549)
8550
8551xnnpack_unit_test(
8552 name = "f16_vaddc_minmax_test",
8553 srcs = [
8554 "test/f16-vaddc-minmax.cc",
8555 "test/vbinaryc-microkernel-tester.h",
8556 ] + MICROKERNEL_TEST_HDRS,
8557 deps = MICROKERNEL_TEST_DEPS,
8558)
8559
8560xnnpack_unit_test(
8561 name = "f16_vclamp_test",
8562 srcs = [
8563 "test/f16-vclamp.cc",
Marat Dukhana6c05162021-05-13 16:52:02 -07008564 "test/vunary-microkernel-tester.h",
Marat Dukhan6674d692021-05-05 22:27:00 -07008565 ] + MICROKERNEL_TEST_HDRS,
8566 deps = MICROKERNEL_TEST_DEPS,
8567)
8568
8569xnnpack_unit_test(
8570 name = "f16_vdiv_minmax_test",
8571 srcs = [
8572 "test/f16-vdiv-minmax.cc",
8573 "test/vbinary-microkernel-tester.h",
8574 ] + MICROKERNEL_TEST_HDRS,
8575 deps = MICROKERNEL_TEST_DEPS,
8576)
8577
8578xnnpack_unit_test(
8579 name = "f16_vdivc_minmax_test",
8580 srcs = [
8581 "test/f16-vdivc-minmax.cc",
8582 "test/vbinaryc-microkernel-tester.h",
8583 ] + MICROKERNEL_TEST_HDRS,
8584 deps = MICROKERNEL_TEST_DEPS,
8585)
8586
8587xnnpack_unit_test(
8588 name = "f16_vrdivc_minmax_test",
8589 srcs = [
8590 "test/f16-vrdivc-minmax.cc",
8591 "test/vbinaryc-microkernel-tester.h",
8592 ] + MICROKERNEL_TEST_HDRS,
8593 deps = MICROKERNEL_TEST_DEPS,
8594)
8595
8596xnnpack_unit_test(
8597 name = "f16_vhswish_test",
8598 srcs = [
8599 "test/f16-vhswish.cc",
Marat Dukhana6c05162021-05-13 16:52:02 -07008600 "test/vunary-microkernel-tester.h",
Marat Dukhan6674d692021-05-05 22:27:00 -07008601 ] + MICROKERNEL_TEST_HDRS,
8602 deps = MICROKERNEL_TEST_DEPS,
8603)
8604
8605xnnpack_unit_test(
8606 name = "f16_vmax_test",
8607 srcs = [
8608 "test/f16-vmax.cc",
8609 "test/vbinary-microkernel-tester.h",
8610 ] + MICROKERNEL_TEST_HDRS,
8611 deps = MICROKERNEL_TEST_DEPS,
8612)
8613
8614xnnpack_unit_test(
8615 name = "f16_vmaxc_test",
8616 srcs = [
8617 "test/f16-vmaxc.cc",
8618 "test/vbinaryc-microkernel-tester.h",
8619 ] + MICROKERNEL_TEST_HDRS,
8620 deps = MICROKERNEL_TEST_DEPS,
8621)
8622
8623xnnpack_unit_test(
8624 name = "f16_vmin_test",
8625 srcs = [
8626 "test/f16-vmin.cc",
8627 "test/vbinary-microkernel-tester.h",
8628 ] + MICROKERNEL_TEST_HDRS,
8629 deps = MICROKERNEL_TEST_DEPS,
8630)
8631
8632xnnpack_unit_test(
8633 name = "f16_vminc_test",
8634 srcs = [
8635 "test/f16-vminc.cc",
8636 "test/vbinaryc-microkernel-tester.h",
8637 ] + MICROKERNEL_TEST_HDRS,
8638 deps = MICROKERNEL_TEST_DEPS,
8639)
8640
8641xnnpack_unit_test(
8642 name = "f16_vmul_minmax_test",
8643 srcs = [
8644 "test/f16-vmul-minmax.cc",
8645 "test/vbinary-microkernel-tester.h",
8646 ] + MICROKERNEL_TEST_HDRS,
8647 deps = MICROKERNEL_TEST_DEPS,
8648)
8649
8650xnnpack_unit_test(
8651 name = "f16_vmulc_minmax_test",
8652 srcs = [
8653 "test/f16-vmulc-minmax.cc",
8654 "test/vbinaryc-microkernel-tester.h",
8655 ] + MICROKERNEL_TEST_HDRS,
8656 deps = MICROKERNEL_TEST_DEPS,
8657)
8658
8659xnnpack_unit_test(
8660 name = "f16_vmulcaddc_minmax_test",
8661 srcs = [
8662 "test/f16-vmulcaddc-minmax.cc",
8663 "test/vmulcaddc-microkernel-tester.h",
8664 "src/xnnpack/AlignedAllocator.h",
8665 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
8666 deps = MICROKERNEL_TEST_DEPS + [":packing"],
8667)
8668
8669xnnpack_unit_test(
8670 name = "f16_vsub_minmax_test",
8671 srcs = [
8672 "test/f16-vsub-minmax.cc",
8673 "test/vbinary-microkernel-tester.h",
8674 ] + MICROKERNEL_TEST_HDRS,
8675 deps = MICROKERNEL_TEST_DEPS,
8676)
8677
8678xnnpack_unit_test(
8679 name = "f16_vsubc_minmax_test",
8680 srcs = [
8681 "test/f16-vsubc-minmax.cc",
8682 "test/vbinaryc-microkernel-tester.h",
8683 ] + MICROKERNEL_TEST_HDRS,
8684 deps = MICROKERNEL_TEST_DEPS,
8685)
8686
8687xnnpack_unit_test(
8688 name = "f16_vrsubc_minmax_test",
8689 srcs = [
8690 "test/f16-vrsubc-minmax.cc",
8691 "test/vbinaryc-microkernel-tester.h",
8692 ] + MICROKERNEL_TEST_HDRS,
8693 deps = MICROKERNEL_TEST_DEPS,
8694)
8695
8696xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07008697 name = "f32_argmaxpool_test",
8698 srcs = [
8699 "test/f32-argmaxpool.cc",
8700 "test/argmaxpool-microkernel-tester.h",
8701 "src/xnnpack/AlignedAllocator.h",
8702 ] + MICROKERNEL_TEST_HDRS,
8703 deps = MICROKERNEL_TEST_DEPS,
8704)
8705
8706xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07008707 name = "f32_avgpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008708 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07008709 "test/f32-avgpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008710 "test/avgpool-microkernel-tester.h",
8711 "src/xnnpack/AlignedAllocator.h",
8712 ] + MICROKERNEL_TEST_HDRS,
8713 deps = MICROKERNEL_TEST_DEPS,
8714)
8715
8716xnnpack_unit_test(
Marat Dukhan660fd192020-03-10 04:55:30 -07008717 name = "f32_ibilinear_test",
Marat Dukhan35dacfb2019-11-07 19:18:16 -08008718 srcs = [
Marat Dukhan660fd192020-03-10 04:55:30 -07008719 "test/f32-ibilinear.cc",
8720 "test/ibilinear-microkernel-tester.h",
Marat Dukhan35dacfb2019-11-07 19:18:16 -08008721 "src/xnnpack/AlignedAllocator.h",
8722 ] + MICROKERNEL_TEST_HDRS,
8723 deps = MICROKERNEL_TEST_DEPS,
8724)
8725
8726xnnpack_unit_test(
XNNPACK Team21432672020-10-19 19:58:48 -07008727 name = "f32_ibilinear_chw_test",
8728 srcs = [
8729 "test/f32-ibilinear-chw.cc",
XNNPACK Team6be46b22020-10-22 23:34:54 -07008730 "test/ibilinear-microkernel-tester.h",
XNNPACK Team21432672020-10-19 19:58:48 -07008731 "src/xnnpack/AlignedAllocator.h",
8732 ] + MICROKERNEL_TEST_HDRS,
8733 deps = MICROKERNEL_TEST_DEPS,
8734)
8735
8736xnnpack_unit_test(
Marat Dukhan163a7e62020-04-09 04:19:26 -07008737 name = "f32_igemm_test",
8738 srcs = [
8739 "test/f32-igemm.cc",
8740 "test/gemm-microkernel-tester.h",
8741 "src/xnnpack/AlignedAllocator.h",
8742 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008743 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan163a7e62020-04-09 04:19:26 -07008744)
8745
8746xnnpack_unit_test(
Marat Dukhan467f6362020-05-22 23:21:55 -07008747 name = "f32_igemm_relu_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008748 srcs = [
Marat Dukhan467f6362020-05-22 23:21:55 -07008749 "test/f32-igemm-relu.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008750 "test/gemm-microkernel-tester.h",
8751 "src/xnnpack/AlignedAllocator.h",
8752 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008753 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008754)
8755
8756xnnpack_unit_test(
Marat Dukhane207b7b2020-05-28 16:27:42 -07008757 name = "f32_igemm_minmax_test",
8758 srcs = [
8759 "test/f32-igemm-minmax.cc",
8760 "test/gemm-microkernel-tester.h",
8761 "src/xnnpack/AlignedAllocator.h",
8762 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008763 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhane207b7b2020-05-28 16:27:42 -07008764)
8765
8766xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07008767 name = "f32_conv_hwc_test",
8768 srcs = [
8769 "test/f32-conv-hwc.cc",
8770 "test/conv-hwc-microkernel-tester.h",
8771 "src/xnnpack/AlignedAllocator.h",
8772 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008773 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008774)
8775
8776xnnpack_unit_test(
Marat Dukhan1f29b802020-05-15 23:46:39 -07008777 name = "f32_conv_hwc2chw_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008778 srcs = [
Marat Dukhan1f29b802020-05-15 23:46:39 -07008779 "test/f32-conv-hwc2chw.cc",
8780 "test/conv-hwc2chw-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008781 "src/xnnpack/AlignedAllocator.h",
8782 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008783 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008784)
8785
8786xnnpack_unit_test(
Marat Dukhan163a7e62020-04-09 04:19:26 -07008787 name = "f32_dwconv_test",
8788 srcs = [
8789 "test/f32-dwconv.cc",
8790 "test/dwconv-microkernel-tester.h",
8791 "src/xnnpack/AlignedAllocator.h",
8792 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008793 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan163a7e62020-04-09 04:19:26 -07008794)
8795
8796xnnpack_unit_test(
Marat Dukhan1c587112020-04-08 20:04:28 -07008797 name = "f32_dwconv_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008798 srcs = [
Marat Dukhan1c587112020-04-08 20:04:28 -07008799 "test/f32-dwconv-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008800 "test/dwconv-microkernel-tester.h",
8801 "src/xnnpack/AlignedAllocator.h",
8802 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008803 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008804)
8805
8806xnnpack_unit_test(
Marat Dukhanbf715f92020-10-23 20:17:00 -07008807 name = "f32_dwconv2d_chw_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008808 srcs = [
Marat Dukhanbf715f92020-10-23 20:17:00 -07008809 "test/f32-dwconv2d-chw.cc",
8810 "test/dwconv2d-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008811 "src/xnnpack/AlignedAllocator.h",
8812 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008813 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008814)
8815
8816xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07008817 name = "f32_gavgpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008818 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07008819 "test/f32-gavgpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008820 "test/gavgpool-microkernel-tester.h",
8821 "src/xnnpack/AlignedAllocator.h",
8822 ] + MICROKERNEL_TEST_HDRS,
8823 deps = MICROKERNEL_TEST_DEPS,
8824)
8825
8826xnnpack_unit_test(
Marat Dukhan1f29b802020-05-15 23:46:39 -07008827 name = "f32_gavgpool_cw_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008828 srcs = [
Marat Dukhan1f29b802020-05-15 23:46:39 -07008829 "test/f32-gavgpool-cw.cc",
8830 "test/gavgpool-cw-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008831 "src/xnnpack/AlignedAllocator.h",
8832 ] + MICROKERNEL_TEST_HDRS,
8833 deps = MICROKERNEL_TEST_DEPS,
8834)
8835
8836xnnpack_unit_test(
Marat Dukhan163a7e62020-04-09 04:19:26 -07008837 name = "f32_gemm_test",
8838 srcs = [
8839 "test/f32-gemm.cc",
8840 "test/gemm-microkernel-tester.h",
8841 "src/xnnpack/AlignedAllocator.h",
8842 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008843 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan163a7e62020-04-09 04:19:26 -07008844)
8845
8846xnnpack_unit_test(
Marat Dukhan467f6362020-05-22 23:21:55 -07008847 name = "f32_gemm_relu_test",
8848 srcs = [
8849 "test/f32-gemm-relu.cc",
8850 "test/gemm-microkernel-tester.h",
8851 "src/xnnpack/AlignedAllocator.h",
8852 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008853 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan467f6362020-05-22 23:21:55 -07008854)
8855
8856xnnpack_unit_test(
Marat Dukhan1c587112020-04-08 20:04:28 -07008857 name = "f32_gemm_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008858 srcs = [
Marat Dukhan1c587112020-04-08 20:04:28 -07008859 "test/f32-gemm-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008860 "test/gemm-microkernel-tester.h",
8861 "src/xnnpack/AlignedAllocator.h",
8862 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008863 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008864)
8865
8866xnnpack_unit_test(
Marat Dukhan1c587112020-04-08 20:04:28 -07008867 name = "f32_gemminc_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008868 srcs = [
Marat Dukhan1c587112020-04-08 20:04:28 -07008869 "test/f32-gemminc-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008870 "test/gemm-microkernel-tester.h",
8871 "src/xnnpack/AlignedAllocator.h",
8872 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008873 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008874)
8875
8876xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07008877 name = "f32_vhswish_test",
Frank Barchardb1966592020-05-12 13:47:06 -07008878 srcs = [
Marat Dukhan6674d692021-05-05 22:27:00 -07008879 "test/f32-vhswish.cc",
Marat Dukhan949b6e72021-05-13 11:21:06 -07008880 "test/vunary-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008881 ] + MICROKERNEL_TEST_HDRS,
8882 deps = MICROKERNEL_TEST_DEPS,
8883)
8884
8885xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07008886 name = "f32_maxpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008887 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07008888 "test/f32-maxpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008889 "test/maxpool-microkernel-tester.h",
8890 ] + MICROKERNEL_TEST_HDRS,
8891 deps = MICROKERNEL_TEST_DEPS,
8892)
8893
8894xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07008895 name = "f32_pavgpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008896 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07008897 "test/f32-pavgpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008898 "test/avgpool-microkernel-tester.h",
8899 "src/xnnpack/AlignedAllocator.h",
8900 ] + MICROKERNEL_TEST_HDRS,
8901 deps = MICROKERNEL_TEST_DEPS,
8902)
8903
8904xnnpack_unit_test(
Marat Dukhan1c587112020-04-08 20:04:28 -07008905 name = "f32_ppmm_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008906 srcs = [
Marat Dukhan1c587112020-04-08 20:04:28 -07008907 "test/f32-ppmm-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008908 "test/gemm-microkernel-tester.h",
8909 "src/xnnpack/AlignedAllocator.h",
8910 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07008911 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07008912)
8913
8914xnnpack_unit_test(
Frank Barchardb1966592020-05-12 13:47:06 -07008915 name = "f16_prelu_test",
8916 srcs = [
8917 "test/f16-prelu.cc",
8918 "test/prelu-microkernel-tester.h",
8919 "src/xnnpack/AlignedAllocator.h",
8920 ] + MICROKERNEL_TEST_HDRS,
8921 deps = MICROKERNEL_TEST_DEPS,
8922)
8923
8924xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07008925 name = "f32_prelu_test",
8926 srcs = [
8927 "test/f32-prelu.cc",
8928 "test/prelu-microkernel-tester.h",
8929 "src/xnnpack/AlignedAllocator.h",
8930 ] + MICROKERNEL_TEST_HDRS,
8931 deps = MICROKERNEL_TEST_DEPS,
8932)
8933
8934xnnpack_unit_test(
Marat Dukhan97579532019-10-18 16:40:39 -07008935 name = "f32_raddexpminusmax_test",
8936 srcs = [
8937 "test/f32-raddexpminusmax.cc",
8938 "test/raddexpminusmax-microkernel-tester.h",
8939 ] + MICROKERNEL_TEST_HDRS,
8940 deps = MICROKERNEL_TEST_DEPS,
8941)
8942
8943xnnpack_unit_test(
Marat Dukhan6f8d4d32019-10-25 17:07:09 -07008944 name = "f32_raddextexp_test",
8945 srcs = [
8946 "test/f32-raddextexp.cc",
8947 "test/raddextexp-microkernel-tester.h",
8948 ] + MICROKERNEL_TEST_HDRS,
8949 deps = MICROKERNEL_TEST_DEPS,
8950)
8951
8952xnnpack_unit_test(
Marat Dukhan97579532019-10-18 16:40:39 -07008953 name = "f32_raddstoreexpminusmax_test",
8954 srcs = [
8955 "test/f32-raddstoreexpminusmax.cc",
8956 "test/raddstoreexpminusmax-microkernel-tester.h",
8957 ] + MICROKERNEL_TEST_HDRS,
8958 deps = MICROKERNEL_TEST_DEPS,
8959)
8960
8961xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07008962 name = "f32_rmax_test",
8963 srcs = [
8964 "test/f32-rmax.cc",
8965 "test/rmax-microkernel-tester.h",
8966 ] + MICROKERNEL_TEST_HDRS,
8967 deps = MICROKERNEL_TEST_DEPS,
8968)
8969
8970xnnpack_unit_test(
Marat Dukhan355ab432020-04-09 19:01:52 -07008971 name = "f32_spmm_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008972 srcs = [
Marat Dukhan355ab432020-04-09 19:01:52 -07008973 "test/f32-spmm-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07008974 "test/spmm-microkernel-tester.h",
8975 "src/xnnpack/AlignedAllocator.h",
8976 ] + MICROKERNEL_TEST_HDRS,
8977 deps = MICROKERNEL_TEST_DEPS,
8978)
8979
8980xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -07008981 name = "f32_vabs_test",
8982 srcs = [
8983 "test/f32-vabs.cc",
8984 "test/vunary-microkernel-tester.h",
8985 ] + MICROKERNEL_TEST_HDRS,
8986 deps = MICROKERNEL_TEST_DEPS,
8987)
8988
8989xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07008990 name = "f32_vadd_test",
8991 srcs = [
8992 "test/f32-vadd.cc",
8993 "test/vbinary-microkernel-tester.h",
8994 ] + MICROKERNEL_TEST_HDRS,
8995 deps = MICROKERNEL_TEST_DEPS,
8996)
8997
8998xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07008999 name = "f32_vadd_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009000 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009001 "test/f32-vadd-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009002 "test/vbinary-microkernel-tester.h",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009003 ] + MICROKERNEL_TEST_HDRS,
9004 deps = MICROKERNEL_TEST_DEPS,
9005)
9006
9007xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009008 name = "f32_vadd_relu_test",
9009 srcs = [
9010 "test/f32-vadd-relu.cc",
9011 "test/vbinary-microkernel-tester.h",
9012 ] + MICROKERNEL_TEST_HDRS,
9013 deps = MICROKERNEL_TEST_DEPS,
9014)
9015
9016xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009017 name = "f32_vaddc_test",
9018 srcs = [
9019 "test/f32-vaddc.cc",
9020 "test/vbinaryc-microkernel-tester.h",
9021 ] + MICROKERNEL_TEST_HDRS,
9022 deps = MICROKERNEL_TEST_DEPS,
9023)
9024
9025xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009026 name = "f32_vaddc_minmax_test",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009027 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009028 "test/f32-vaddc-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009029 "test/vbinaryc-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009030 ] + MICROKERNEL_TEST_HDRS,
9031 deps = MICROKERNEL_TEST_DEPS,
9032)
9033
9034xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009035 name = "f32_vaddc_relu_test",
9036 srcs = [
9037 "test/f32-vaddc-relu.cc",
9038 "test/vbinaryc-microkernel-tester.h",
9039 ] + MICROKERNEL_TEST_HDRS,
9040 deps = MICROKERNEL_TEST_DEPS,
9041)
9042
9043xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07009044 name = "f32_vclamp_test",
9045 srcs = [
9046 "test/f32-vclamp.cc",
Marat Dukhan60d3f242021-05-13 11:59:02 -07009047 "test/vunary-microkernel-tester.h",
Marat Dukhan6674d692021-05-05 22:27:00 -07009048 ] + MICROKERNEL_TEST_HDRS,
9049 deps = MICROKERNEL_TEST_DEPS,
9050)
9051
9052xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009053 name = "f32_vdiv_test",
9054 srcs = [
9055 "test/f32-vdiv.cc",
9056 "test/vbinary-microkernel-tester.h",
9057 ] + MICROKERNEL_TEST_HDRS,
9058 deps = MICROKERNEL_TEST_DEPS,
9059)
9060
9061xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009062 name = "f32_vdiv_minmax_test",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009063 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009064 "test/f32-vdiv-minmax.cc",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009065 "test/vbinary-microkernel-tester.h",
9066 ] + MICROKERNEL_TEST_HDRS,
9067 deps = MICROKERNEL_TEST_DEPS,
9068)
9069
9070xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009071 name = "f32_vdiv_relu_test",
9072 srcs = [
9073 "test/f32-vdiv-relu.cc",
9074 "test/vbinary-microkernel-tester.h",
9075 ] + MICROKERNEL_TEST_HDRS,
9076 deps = MICROKERNEL_TEST_DEPS,
9077)
9078
9079xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009080 name = "f32_vdivc_test",
9081 srcs = [
9082 "test/f32-vdivc.cc",
9083 "test/vbinaryc-microkernel-tester.h",
9084 ] + MICROKERNEL_TEST_HDRS,
9085 deps = MICROKERNEL_TEST_DEPS,
9086)
9087
9088xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009089 name = "f32_vdivc_minmax_test",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009090 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009091 "test/f32-vdivc-minmax.cc",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009092 "test/vbinaryc-microkernel-tester.h",
9093 ] + MICROKERNEL_TEST_HDRS,
9094 deps = MICROKERNEL_TEST_DEPS,
9095)
9096
9097xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009098 name = "f32_vdivc_relu_test",
9099 srcs = [
9100 "test/f32-vdivc-relu.cc",
9101 "test/vbinaryc-microkernel-tester.h",
9102 ] + MICROKERNEL_TEST_HDRS,
9103 deps = MICROKERNEL_TEST_DEPS,
9104)
9105
9106xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009107 name = "f32_vrdivc_test",
9108 srcs = [
9109 "test/f32-vrdivc.cc",
9110 "test/vbinaryc-microkernel-tester.h",
9111 ] + MICROKERNEL_TEST_HDRS,
9112 deps = MICROKERNEL_TEST_DEPS,
9113)
9114
9115xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009116 name = "f32_vrdivc_minmax_test",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009117 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009118 "test/f32-vrdivc-minmax.cc",
Marat Dukhan77ca6302019-12-06 12:48:15 -08009119 "test/vbinaryc-microkernel-tester.h",
9120 ] + MICROKERNEL_TEST_HDRS,
9121 deps = MICROKERNEL_TEST_DEPS,
9122)
9123
9124xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009125 name = "f32_vrdivc_relu_test",
9126 srcs = [
9127 "test/f32-vrdivc-relu.cc",
9128 "test/vbinaryc-microkernel-tester.h",
9129 ] + MICROKERNEL_TEST_HDRS,
9130 deps = MICROKERNEL_TEST_DEPS,
9131)
9132
9133xnnpack_unit_test(
Marat Dukhaned6baaf2020-12-01 15:07:08 -08009134 name = "f32_velu_test",
9135 srcs = [
9136 "test/f32-velu.cc",
9137 "test/vunary-microkernel-tester.h",
9138 ] + MICROKERNEL_TEST_HDRS,
9139 deps = MICROKERNEL_TEST_DEPS,
9140)
9141
9142xnnpack_unit_test(
Marat Dukhan403b7d42019-12-05 12:49:11 -08009143 name = "f32_vmax_test",
9144 srcs = [
9145 "test/f32-vmax.cc",
9146 "test/vbinary-microkernel-tester.h",
9147 ] + MICROKERNEL_TEST_HDRS,
9148 deps = MICROKERNEL_TEST_DEPS,
9149)
9150
9151xnnpack_unit_test(
9152 name = "f32_vmaxc_test",
9153 srcs = [
9154 "test/f32-vmaxc.cc",
9155 "test/vbinaryc-microkernel-tester.h",
9156 ] + MICROKERNEL_TEST_HDRS,
9157 deps = MICROKERNEL_TEST_DEPS,
9158)
9159
9160xnnpack_unit_test(
9161 name = "f32_vmin_test",
9162 srcs = [
9163 "test/f32-vmin.cc",
9164 "test/vbinary-microkernel-tester.h",
9165 ] + MICROKERNEL_TEST_HDRS,
9166 deps = MICROKERNEL_TEST_DEPS,
9167)
9168
9169xnnpack_unit_test(
9170 name = "f32_vminc_test",
9171 srcs = [
9172 "test/f32-vminc.cc",
9173 "test/vbinaryc-microkernel-tester.h",
9174 ] + MICROKERNEL_TEST_HDRS,
9175 deps = MICROKERNEL_TEST_DEPS,
9176)
9177
9178xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009179 name = "f32_vmul_test",
9180 srcs = [
9181 "test/f32-vmul.cc",
9182 "test/vbinary-microkernel-tester.h",
9183 ] + MICROKERNEL_TEST_HDRS,
9184 deps = MICROKERNEL_TEST_DEPS,
9185)
9186
9187xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009188 name = "f32_vmul_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009189 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009190 "test/f32-vmul-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009191 "test/vbinary-microkernel-tester.h",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009192 ] + MICROKERNEL_TEST_HDRS,
9193 deps = MICROKERNEL_TEST_DEPS,
9194)
9195
9196xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009197 name = "f32_vmul_relu_test",
9198 srcs = [
9199 "test/f32-vmul-relu.cc",
9200 "test/vbinary-microkernel-tester.h",
9201 ] + MICROKERNEL_TEST_HDRS,
9202 deps = MICROKERNEL_TEST_DEPS,
9203)
9204
9205xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009206 name = "f32_vmulc_test",
9207 srcs = [
9208 "test/f32-vmulc.cc",
9209 "test/vbinaryc-microkernel-tester.h",
9210 ] + MICROKERNEL_TEST_HDRS,
9211 deps = MICROKERNEL_TEST_DEPS,
9212)
9213
9214xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009215 name = "f32_vmulc_minmax_test",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009216 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009217 "test/f32-vmulc-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009218 "test/vbinaryc-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009219 ] + MICROKERNEL_TEST_HDRS,
9220 deps = MICROKERNEL_TEST_DEPS,
9221)
9222
9223xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009224 name = "f32_vmulc_relu_test",
9225 srcs = [
9226 "test/f32-vmulc-relu.cc",
9227 "test/vbinaryc-microkernel-tester.h",
9228 ] + MICROKERNEL_TEST_HDRS,
9229 deps = MICROKERNEL_TEST_DEPS,
9230)
9231
9232xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07009233 name = "f32_vmulcaddc_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009234 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07009235 "test/f32-vmulcaddc-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009236 "test/vmulcaddc-microkernel-tester.h",
9237 "src/xnnpack/AlignedAllocator.h",
9238 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07009239 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07009240)
9241
9242xnnpack_unit_test(
Marat Dukhan8cc7efe2020-06-10 16:24:27 -07009243 name = "f32_vlrelu_test",
9244 srcs = [
9245 "test/f32-vlrelu.cc",
9246 "test/vunary-microkernel-tester.h",
9247 ] + MICROKERNEL_TEST_HDRS,
9248 deps = MICROKERNEL_TEST_DEPS,
9249)
9250
9251xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -07009252 name = "f32_vneg_test",
9253 srcs = [
9254 "test/f32-vneg.cc",
9255 "test/vunary-microkernel-tester.h",
9256 ] + MICROKERNEL_TEST_HDRS,
9257 deps = MICROKERNEL_TEST_DEPS,
9258)
9259
9260xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07009261 name = "f32_vrelu_test",
9262 srcs = [
9263 "test/f32-vrelu.cc",
9264 "test/vunary-microkernel-tester.h",
9265 ] + MICROKERNEL_TEST_HDRS,
9266 deps = MICROKERNEL_TEST_DEPS,
9267)
9268
9269xnnpack_unit_test(
Marat Dukhaneecf8fd2020-06-09 08:59:37 -07009270 name = "f32_vrndne_test",
9271 srcs = [
9272 "test/f32-vrndne.cc",
9273 "test/vunary-microkernel-tester.h",
9274 ] + MICROKERNEL_TEST_HDRS,
9275 deps = MICROKERNEL_TEST_DEPS,
9276)
9277
9278xnnpack_unit_test(
9279 name = "f32_vrndz_test",
9280 srcs = [
9281 "test/f32-vrndz.cc",
9282 "test/vunary-microkernel-tester.h",
9283 ] + MICROKERNEL_TEST_HDRS,
9284 deps = MICROKERNEL_TEST_DEPS,
9285)
9286
9287xnnpack_unit_test(
9288 name = "f32_vrndu_test",
9289 srcs = [
9290 "test/f32-vrndu.cc",
9291 "test/vunary-microkernel-tester.h",
9292 ] + MICROKERNEL_TEST_HDRS,
9293 deps = MICROKERNEL_TEST_DEPS,
9294)
9295
9296xnnpack_unit_test(
9297 name = "f32_vrndd_test",
9298 srcs = [
9299 "test/f32-vrndd.cc",
9300 "test/vunary-microkernel-tester.h",
9301 ] + MICROKERNEL_TEST_HDRS,
9302 deps = MICROKERNEL_TEST_DEPS,
9303)
9304
9305xnnpack_unit_test(
Marat Dukhan05ac8e32019-10-21 15:39:33 -07009306 name = "f32_vscale_test",
9307 srcs = [
9308 "test/f32-vscale.cc",
9309 "test/vscale-microkernel-tester.h",
9310 ] + MICROKERNEL_TEST_HDRS,
9311 deps = MICROKERNEL_TEST_DEPS,
9312)
9313
9314xnnpack_unit_test(
Marat Dukhan97579532019-10-18 16:40:39 -07009315 name = "f32_vscaleexpminusmax_test",
9316 srcs = [
9317 "test/f32-vscaleexpminusmax.cc",
9318 "test/vscaleexpminusmax-microkernel-tester.h",
9319 ] + MICROKERNEL_TEST_HDRS,
9320 deps = MICROKERNEL_TEST_DEPS,
9321)
9322
9323xnnpack_unit_test(
Marat Dukhan6f8d4d32019-10-25 17:07:09 -07009324 name = "f32_vscaleextexp_test",
9325 srcs = [
9326 "test/f32-vscaleextexp.cc",
9327 "test/vscaleextexp-microkernel-tester.h",
9328 ] + MICROKERNEL_TEST_HDRS,
9329 deps = MICROKERNEL_TEST_DEPS,
9330)
9331
9332xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07009333 name = "f32_vsigmoid_test",
9334 srcs = [
9335 "test/f32-vsigmoid.cc",
9336 "test/vunary-microkernel-tester.h",
9337 ] + MICROKERNEL_TEST_HDRS,
9338 deps = MICROKERNEL_TEST_DEPS,
9339)
9340
9341xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -07009342 name = "f32_vsqr_test",
9343 srcs = [
9344 "test/f32-vsqr.cc",
9345 "test/vunary-microkernel-tester.h",
9346 ] + MICROKERNEL_TEST_HDRS,
9347 deps = MICROKERNEL_TEST_DEPS,
9348)
9349
9350xnnpack_unit_test(
Marat Dukhan13bafb02020-06-05 00:43:11 -07009351 name = "f32_vsqrdiff_test",
9352 srcs = [
9353 "test/f32-vsqrdiff.cc",
9354 "test/vbinary-microkernel-tester.h",
9355 ] + MICROKERNEL_TEST_HDRS,
9356 deps = MICROKERNEL_TEST_DEPS,
9357)
9358
9359xnnpack_unit_test(
9360 name = "f32_vsqrdiffc_test",
9361 srcs = [
9362 "test/f32-vsqrdiffc.cc",
9363 "test/vbinaryc-microkernel-tester.h",
9364 ] + MICROKERNEL_TEST_HDRS,
9365 deps = MICROKERNEL_TEST_DEPS,
9366)
9367
9368xnnpack_unit_test(
Marat Dukhanf4db2f32020-06-30 10:55:30 -07009369 name = "f32_vsqrt_test",
9370 srcs = [
9371 "test/f32-vsqrt.cc",
9372 "test/vunary-microkernel-tester.h",
9373 ] + MICROKERNEL_TEST_HDRS,
9374 deps = MICROKERNEL_TEST_DEPS,
9375)
9376
9377xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009378 name = "f32_vsub_test",
9379 srcs = [
9380 "test/f32-vsub.cc",
9381 "test/vbinary-microkernel-tester.h",
9382 ] + MICROKERNEL_TEST_HDRS,
9383 deps = MICROKERNEL_TEST_DEPS,
9384)
9385
9386xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009387 name = "f32_vsub_minmax_test",
Marat Dukhan97579532019-10-18 16:40:39 -07009388 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009389 "test/f32-vsub-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009390 "test/vbinary-microkernel-tester.h",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009391 ] + MICROKERNEL_TEST_HDRS,
9392 deps = MICROKERNEL_TEST_DEPS,
9393)
9394
9395xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009396 name = "f32_vsub_relu_test",
9397 srcs = [
9398 "test/f32-vsub-relu.cc",
9399 "test/vbinary-microkernel-tester.h",
9400 ] + MICROKERNEL_TEST_HDRS,
9401 deps = MICROKERNEL_TEST_DEPS,
9402)
9403
9404xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009405 name = "f32_vsubc_test",
9406 srcs = [
9407 "test/f32-vsubc.cc",
9408 "test/vbinaryc-microkernel-tester.h",
9409 ] + MICROKERNEL_TEST_HDRS,
9410 deps = MICROKERNEL_TEST_DEPS,
9411)
9412
9413xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009414 name = "f32_vsubc_minmax_test",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009415 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009416 "test/f32-vsubc-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009417 "test/vbinaryc-microkernel-tester.h",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009418 ] + MICROKERNEL_TEST_HDRS,
9419 deps = MICROKERNEL_TEST_DEPS,
9420)
9421
9422xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009423 name = "f32_vsubc_relu_test",
9424 srcs = [
9425 "test/f32-vsubc-relu.cc",
9426 "test/vbinaryc-microkernel-tester.h",
9427 ] + MICROKERNEL_TEST_HDRS,
9428 deps = MICROKERNEL_TEST_DEPS,
9429)
9430
9431xnnpack_unit_test(
Frank Barchardd5b9f1c2020-07-01 15:00:19 -07009432 name = "f32_vrsubc_test",
9433 srcs = [
9434 "test/f32-vrsubc.cc",
9435 "test/vbinaryc-microkernel-tester.h",
9436 ] + MICROKERNEL_TEST_HDRS,
9437 deps = MICROKERNEL_TEST_DEPS,
9438)
9439
9440xnnpack_unit_test(
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009441 name = "f32_vrsubc_minmax_test",
Marat Dukhanc07cb7f2019-11-14 15:32:05 -08009442 srcs = [
Marat Dukhan91cd2b72020-04-09 23:57:31 -07009443 "test/f32-vrsubc-minmax.cc",
Marat Dukhan1e782c42019-11-21 17:02:40 -08009444 "test/vbinaryc-microkernel-tester.h",
Marat Dukhan97579532019-10-18 16:40:39 -07009445 ] + MICROKERNEL_TEST_HDRS,
9446 deps = MICROKERNEL_TEST_DEPS,
9447)
9448
9449xnnpack_unit_test(
Frank Barchard674778d2020-08-08 10:17:25 -07009450 name = "f32_vrsubc_relu_test",
9451 srcs = [
9452 "test/f32-vrsubc-relu.cc",
9453 "test/vbinaryc-microkernel-tester.h",
9454 ] + MICROKERNEL_TEST_HDRS,
9455 deps = MICROKERNEL_TEST_DEPS,
9456)
9457
9458xnnpack_unit_test(
Marat Dukhan82286892021-06-04 17:27:27 -07009459 name = "qc8_dwconv_minmax_fp32_test",
9460 timeout = "moderate",
9461 srcs = [
9462 "test/qc8-dwconv-minmax-fp32.cc",
9463 "test/dwconv-microkernel-tester.h",
9464 "src/xnnpack/AlignedAllocator.h",
9465 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9466 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9467)
9468
9469xnnpack_unit_test(
Marat Dukhan0b043742021-06-02 18:29:11 -07009470 name = "qc8_gemm_minmax_fp32_test",
9471 timeout = "moderate",
9472 srcs = [
9473 "test/qc8-gemm-minmax-fp32.cc",
9474 "test/gemm-microkernel-tester.h",
9475 "src/xnnpack/AlignedAllocator.h",
9476 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9477 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9478)
9479
9480xnnpack_unit_test(
Marat Dukhane06c8132021-06-03 08:59:11 -07009481 name = "qc8_igemm_minmax_fp32_test",
9482 timeout = "moderate",
9483 srcs = [
9484 "test/qc8-igemm-minmax-fp32.cc",
9485 "test/gemm-microkernel-tester.h",
9486 "src/xnnpack/AlignedAllocator.h",
9487 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9488 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9489)
9490
9491xnnpack_unit_test(
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07009492 name = "qs8_dwconv_minmax_fp32_test",
9493 srcs = [
9494 "test/qs8-dwconv-minmax-fp32.cc",
9495 "test/dwconv-microkernel-tester.h",
9496 "src/xnnpack/AlignedAllocator.h",
9497 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9498 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9499)
9500
9501xnnpack_unit_test(
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009502 name = "qs8_dwconv_minmax_gemmlowp_test",
Marat Dukhanf62bbdc2020-08-04 13:59:04 -07009503 srcs = [
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009504 "test/qs8-dwconv-minmax-gemmlowp.cc",
Marat Dukhanf62bbdc2020-08-04 13:59:04 -07009505 "test/dwconv-microkernel-tester.h",
9506 "src/xnnpack/AlignedAllocator.h",
9507 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9508 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9509)
9510
9511xnnpack_unit_test(
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07009512 name = "qs8_dwconv_minmax_rndnu_test",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009513 srcs = [
Marat Dukhanbe18f5c2021-07-16 18:46:39 -07009514 "test/qs8-dwconv-minmax-rndnu.cc",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009515 "test/dwconv-microkernel-tester.h",
9516 "src/xnnpack/AlignedAllocator.h",
9517 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9518 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9519)
9520
9521xnnpack_unit_test(
Marat Dukhan4ed53f42020-08-06 01:12:55 -07009522 name = "qs8_gavgpool_minmax_test",
9523 srcs = [
9524 "test/qs8-gavgpool-minmax.cc",
9525 "test/gavgpool-microkernel-tester.h",
9526 "src/xnnpack/AlignedAllocator.h",
9527 ] + MICROKERNEL_TEST_HDRS,
9528 deps = MICROKERNEL_TEST_DEPS,
9529)
9530
9531xnnpack_unit_test(
Marat Dukhane903dff2021-07-16 19:43:41 -07009532 name = "qs8_gemm_minmax_fp32_test",
9533 timeout = "moderate",
9534 srcs = [
9535 "test/qs8-gemm-minmax-fp32.cc",
9536 "test/gemm-microkernel-tester.h",
9537 "src/xnnpack/AlignedAllocator.h",
9538 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9539 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9540)
9541
9542xnnpack_unit_test(
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009543 name = "qs8_gemm_minmax_gemmlowp_test",
Marat Dukhan56fdb252021-05-24 13:44:00 -07009544 timeout = "moderate",
Marat Dukhan595e1702020-07-31 10:12:52 -07009545 srcs = [
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009546 "test/qs8-gemm-minmax-gemmlowp.cc",
Marat Dukhan595e1702020-07-31 10:12:52 -07009547 "test/gemm-microkernel-tester.h",
9548 "src/xnnpack/AlignedAllocator.h",
9549 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9550 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9551)
9552
9553xnnpack_unit_test(
Marat Dukhane903dff2021-07-16 19:43:41 -07009554 name = "qs8_gemm_minmax_rndnu_test",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009555 timeout = "moderate",
9556 srcs = [
Marat Dukhane903dff2021-07-16 19:43:41 -07009557 "test/qs8-gemm-minmax-rndnu.cc",
9558 "test/gemm-microkernel-tester.h",
9559 "src/xnnpack/AlignedAllocator.h",
9560 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9561 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9562)
9563
9564xnnpack_unit_test(
9565 name = "qs8_igemm_minmax_fp32_test",
9566 timeout = "moderate",
9567 srcs = [
9568 "test/qs8-igemm-minmax-fp32.cc",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009569 "test/gemm-microkernel-tester.h",
9570 "src/xnnpack/AlignedAllocator.h",
9571 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9572 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9573)
9574
9575xnnpack_unit_test(
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009576 name = "qs8_igemm_minmax_gemmlowp_test",
Marat Dukhan56fdb252021-05-24 13:44:00 -07009577 timeout = "moderate",
Marat Dukhanf9480682020-07-31 14:50:24 -07009578 srcs = [
Marat Dukhanb07c26a2021-05-24 19:44:51 -07009579 "test/qs8-igemm-minmax-gemmlowp.cc",
Marat Dukhanf9480682020-07-31 14:50:24 -07009580 "test/gemm-microkernel-tester.h",
9581 "src/xnnpack/AlignedAllocator.h",
9582 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9583 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9584)
9585
9586xnnpack_unit_test(
Marat Dukhane903dff2021-07-16 19:43:41 -07009587 name = "qs8_igemm_minmax_rndnu_test",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009588 timeout = "moderate",
9589 srcs = [
Marat Dukhane903dff2021-07-16 19:43:41 -07009590 "test/qs8-igemm-minmax-rndnu.cc",
Marat Dukhan9b474cf2021-05-25 16:37:48 -07009591 "test/gemm-microkernel-tester.h",
9592 "src/xnnpack/AlignedAllocator.h",
9593 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9594 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9595)
9596
9597xnnpack_unit_test(
Marat Dukhanf9480682020-07-31 14:50:24 -07009598 name = "qs8_requantization_test",
9599 srcs = [
9600 "src/xnnpack/requantization-stubs.h",
9601 "test/qs8-requantization.cc",
9602 "test/requantization-tester.h",
9603 ] + MICROKERNEL_TEST_HDRS,
9604 deps = MICROKERNEL_TEST_DEPS,
9605)
9606
9607xnnpack_unit_test(
Marat Dukhand9f3ad42020-08-10 12:30:58 -07009608 name = "qs8_vadd_minmax_test",
9609 srcs = [
9610 "test/qs8-vadd-minmax.cc",
9611 "test/vadd-microkernel-tester.h",
9612 ] + MICROKERNEL_TEST_HDRS,
9613 deps = MICROKERNEL_TEST_DEPS,
9614)
9615
9616xnnpack_unit_test(
Marat Dukhan0270d9f2020-08-11 00:56:46 -07009617 name = "qs8_vaddc_minmax_test",
9618 srcs = [
9619 "test/qs8-vaddc-minmax.cc",
9620 "test/vaddc-microkernel-tester.h",
9621 ] + MICROKERNEL_TEST_HDRS,
9622 deps = MICROKERNEL_TEST_DEPS,
9623)
9624
9625xnnpack_unit_test(
Marat Dukhana212eac2021-08-02 09:58:04 -07009626 name = "qs8_vmul_minmax_fp32_test",
9627 srcs = [
9628 "test/qs8-vmul-minmax-fp32.cc",
9629 "test/vmul-microkernel-tester.h",
9630 ] + MICROKERNEL_TEST_HDRS,
9631 deps = MICROKERNEL_TEST_DEPS,
9632)
9633
9634xnnpack_unit_test(
9635 name = "qs8_vmulc_minmax_fp32_test",
9636 srcs = [
9637 "test/qs8-vmulc-minmax-fp32.cc",
9638 "test/vmulc-microkernel-tester.h",
9639 ] + MICROKERNEL_TEST_HDRS,
9640 deps = MICROKERNEL_TEST_DEPS,
9641)
9642
9643xnnpack_unit_test(
Marat Dukhan08b7a972020-07-14 18:17:29 -07009644 name = "qu8_avgpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009645 srcs = [
Marat Dukhan08b7a972020-07-14 18:17:29 -07009646 "test/qu8-avgpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009647 "test/avgpool-microkernel-tester.h",
9648 "src/xnnpack/AlignedAllocator.h",
9649 ] + MICROKERNEL_TEST_HDRS,
9650 deps = MICROKERNEL_TEST_DEPS,
9651)
9652
9653xnnpack_unit_test(
Marat Dukhan3c35f7a2021-07-08 18:55:42 -07009654 name = "qu8_dwconv_minmax_fp32_test",
9655 srcs = [
9656 "test/qu8-dwconv-minmax-fp32.cc",
9657 "test/dwconv-microkernel-tester.h",
9658 "src/xnnpack/AlignedAllocator.h",
9659 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9660 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9661)
9662
9663xnnpack_unit_test(
Marat Dukhan73a899a2021-07-27 00:10:38 -07009664 name = "qu8_dwconv_minmax_rndnu_test",
9665 srcs = [
9666 "test/qu8-dwconv-minmax-rndnu.cc",
9667 "test/dwconv-microkernel-tester.h",
9668 "src/xnnpack/AlignedAllocator.h",
9669 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9670 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9671)
9672
9673xnnpack_unit_test(
Marat Dukhan08b7a972020-07-14 18:17:29 -07009674 name = "qu8_gavgpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009675 srcs = [
Marat Dukhan08b7a972020-07-14 18:17:29 -07009676 "test/qu8-gavgpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009677 "test/gavgpool-microkernel-tester.h",
9678 "src/xnnpack/AlignedAllocator.h",
9679 ] + MICROKERNEL_TEST_HDRS,
9680 deps = MICROKERNEL_TEST_DEPS,
9681)
9682
9683xnnpack_unit_test(
Marat Dukhanef47f8d2021-07-02 15:08:32 -07009684 name = "qu8_gemm_minmax_fp32_test",
9685 srcs = [
9686 "test/qu8-gemm-minmax-fp32.cc",
9687 "test/gemm-microkernel-tester.h",
9688 "src/xnnpack/AlignedAllocator.h",
9689 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9690 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9691)
9692
9693xnnpack_unit_test(
Marat Dukhanc2e8f662021-07-01 17:06:34 -07009694 name = "qu8_gemm_minmax_gemmlowp_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009695 srcs = [
Marat Dukhanc2e8f662021-07-01 17:06:34 -07009696 "test/qu8-gemm-minmax-gemmlowp.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009697 "test/gemm-microkernel-tester.h",
9698 "src/xnnpack/AlignedAllocator.h",
9699 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
Marat Dukhanab582382020-07-06 13:32:08 -07009700 deps = MICROKERNEL_TEST_DEPS + [":packing"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07009701)
9702
9703xnnpack_unit_test(
Marat Dukhan173661d2021-07-26 23:47:08 -07009704 name = "qu8_gemm_minmax_rndnu_test",
9705 srcs = [
9706 "test/qu8-gemm-minmax-rndnu.cc",
9707 "test/gemm-microkernel-tester.h",
9708 "src/xnnpack/AlignedAllocator.h",
9709 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9710 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9711)
9712
9713xnnpack_unit_test(
9714 name = "qu8_igemm_minmax_fp32_test",
9715 srcs = [
9716 "test/qu8-igemm-minmax-fp32.cc",
9717 "test/gemm-microkernel-tester.h",
9718 "src/xnnpack/AlignedAllocator.h",
9719 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9720 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9721)
9722
9723xnnpack_unit_test(
9724 name = "qu8_igemm_minmax_gemmlowp_test",
9725 srcs = [
9726 "test/qu8-igemm-minmax-gemmlowp.cc",
9727 "test/gemm-microkernel-tester.h",
9728 "src/xnnpack/AlignedAllocator.h",
9729 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9730 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9731)
9732
9733xnnpack_unit_test(
9734 name = "qu8_igemm_minmax_rndnu_test",
9735 srcs = [
9736 "test/qu8-igemm-minmax-rndnu.cc",
9737 "test/gemm-microkernel-tester.h",
9738 "src/xnnpack/AlignedAllocator.h",
9739 ] + WEIGHTS_PACK_HDRS + MICROKERNEL_TEST_HDRS,
9740 deps = MICROKERNEL_TEST_DEPS + [":packing"],
9741)
9742
9743xnnpack_unit_test(
Marat Dukhan5b69f8b2020-07-24 15:26:48 -07009744 name = "qu8_requantization_test",
9745 srcs = [
9746 "src/xnnpack/requantization-stubs.h",
9747 "test/qu8-requantization.cc",
9748 "test/requantization-tester.h",
9749 ] + MICROKERNEL_TEST_HDRS,
9750 deps = MICROKERNEL_TEST_DEPS,
9751)
9752
9753xnnpack_unit_test(
Marat Dukhan08b7a972020-07-14 18:17:29 -07009754 name = "qu8_vadd_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009755 srcs = [
Marat Dukhan08b7a972020-07-14 18:17:29 -07009756 "test/qu8-vadd-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009757 "test/vadd-microkernel-tester.h",
9758 ] + MICROKERNEL_TEST_HDRS,
9759 deps = MICROKERNEL_TEST_DEPS,
9760)
9761
9762xnnpack_unit_test(
Marat Dukhan76e78c82021-07-20 21:11:23 -07009763 name = "qu8_vaddc_minmax_test",
9764 srcs = [
9765 "test/qu8-vaddc-minmax.cc",
9766 "test/vaddc-microkernel-tester.h",
9767 ] + MICROKERNEL_TEST_HDRS,
9768 deps = MICROKERNEL_TEST_DEPS,
9769)
9770
9771xnnpack_unit_test(
Marat Dukhana212eac2021-08-02 09:58:04 -07009772 name = "qu8_vmul_minmax_fp32_test",
9773 srcs = [
9774 "test/qu8-vmul-minmax-fp32.cc",
9775 "test/vmul-microkernel-tester.h",
9776 ] + MICROKERNEL_TEST_HDRS,
9777 deps = MICROKERNEL_TEST_DEPS,
9778)
9779
9780xnnpack_unit_test(
9781 name = "qu8_vmulc_minmax_fp32_test",
9782 srcs = [
9783 "test/qu8-vmulc-minmax-fp32.cc",
9784 "test/vmulc-microkernel-tester.h",
9785 ] + MICROKERNEL_TEST_HDRS,
9786 deps = MICROKERNEL_TEST_DEPS,
9787)
9788
9789xnnpack_unit_test(
Marat Dukhan23147532021-08-16 07:26:56 -07009790 name = "s8_maxpool_minmax_test",
9791 srcs = [
9792 "test/s8-maxpool-minmax.cc",
9793 "test/maxpool-microkernel-tester.h",
9794 ] + MICROKERNEL_TEST_HDRS,
9795 deps = MICROKERNEL_TEST_DEPS,
9796)
9797
9798xnnpack_unit_test(
Marat Dukhane79acb72021-08-16 19:03:53 -07009799 name = "s8_vclamp_test",
9800 srcs = [
9801 "test/s8-vclamp.cc",
9802 "test/vunary-microkernel-tester.h",
9803 ] + MICROKERNEL_TEST_HDRS,
9804 deps = MICROKERNEL_TEST_DEPS,
9805)
9806
9807xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07009808 name = "u8_lut32norm_test",
9809 srcs = [
9810 "test/u8-lut32norm.cc",
9811 "test/lut-norm-microkernel-tester.h",
9812 ] + MICROKERNEL_TEST_HDRS,
9813 deps = MICROKERNEL_TEST_DEPS,
9814)
9815
9816xnnpack_unit_test(
Marat Dukhan99936602020-04-11 16:47:01 -07009817 name = "u8_maxpool_minmax_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009818 srcs = [
Marat Dukhan99936602020-04-11 16:47:01 -07009819 "test/u8-maxpool-minmax.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009820 "test/maxpool-microkernel-tester.h",
9821 ] + MICROKERNEL_TEST_HDRS,
9822 deps = MICROKERNEL_TEST_DEPS,
9823)
9824
9825xnnpack_unit_test(
9826 name = "u8_rmax_test",
9827 srcs = [
9828 "test/u8-rmax.cc",
9829 "test/rmax-microkernel-tester.h",
9830 ] + MICROKERNEL_TEST_HDRS,
9831 deps = MICROKERNEL_TEST_DEPS,
9832)
9833
9834xnnpack_unit_test(
Marat Dukhan6674d692021-05-05 22:27:00 -07009835 name = "u8_vclamp_test",
9836 srcs = [
9837 "test/u8-vclamp.cc",
Marat Dukhana6c05162021-05-13 16:52:02 -07009838 "test/vunary-microkernel-tester.h",
Marat Dukhan6674d692021-05-05 22:27:00 -07009839 ] + MICROKERNEL_TEST_HDRS,
9840 deps = MICROKERNEL_TEST_DEPS,
9841)
9842
9843xnnpack_unit_test(
Marat Dukhan933051b2021-08-07 16:26:15 -07009844 name = "x8_lut_test",
Yury Kartynnike7841862020-11-04 18:22:18 -08009845 srcs = [
Marat Dukhan933051b2021-08-07 16:26:15 -07009846 "test/x8-lut.cc",
9847 "test/lut-microkernel-tester.h",
Yury Kartynnike7841862020-11-04 18:22:18 -08009848 ] + MICROKERNEL_TEST_HDRS,
9849 deps = MICROKERNEL_TEST_DEPS,
9850)
9851
9852xnnpack_unit_test(
Marat Dukhan933051b2021-08-07 16:26:15 -07009853 name = "x8_zip_test",
Marat Dukhan3bb3bfc2020-05-19 17:42:46 -07009854 srcs = [
Marat Dukhan933051b2021-08-07 16:26:15 -07009855 "test/x8-zip.cc",
9856 "test/zip-microkernel-tester.h",
9857 ] + MICROKERNEL_TEST_HDRS,
9858 deps = MICROKERNEL_TEST_DEPS,
9859)
9860
9861xnnpack_unit_test(
9862 name = "x32_depthtospace2d_chw2hwc_test",
9863 srcs = [
9864 "test/x32-depthtospace2d-chw2hwc.cc",
9865 "test/depthtospace-microkernel-tester.h",
Marat Dukhan3bb3bfc2020-05-19 17:42:46 -07009866 ] + MICROKERNEL_TEST_HDRS,
9867 deps = MICROKERNEL_TEST_DEPS,
9868)
9869
9870xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07009871 name = "x32_packx_test",
9872 srcs = [
9873 "test/x32-packx.cc",
9874 "test/pack-microkernel-tester.h",
9875 "src/xnnpack/AlignedAllocator.h",
9876 ] + MICROKERNEL_TEST_HDRS,
9877 deps = MICROKERNEL_TEST_DEPS,
9878)
9879
9880xnnpack_unit_test(
Marat Dukhan08c4a432019-10-03 09:29:21 -07009881 name = "x32_unpool_test",
9882 srcs = [
9883 "test/x32-unpool.cc",
9884 "test/unpool-microkernel-tester.h",
9885 ] + MICROKERNEL_TEST_HDRS,
9886 deps = MICROKERNEL_TEST_DEPS,
9887)
9888
9889xnnpack_unit_test(
9890 name = "x32_zip_test",
9891 srcs = [
9892 "test/x32-zip.cc",
9893 "test/zip-microkernel-tester.h",
9894 ] + MICROKERNEL_TEST_HDRS,
9895 deps = MICROKERNEL_TEST_DEPS,
9896)
9897
9898xnnpack_unit_test(
Marat Dukhan933051b2021-08-07 16:26:15 -07009899 name = "xx_fill_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009900 srcs = [
Marat Dukhan933051b2021-08-07 16:26:15 -07009901 "test/xx-fill.cc",
9902 "test/fill-microkernel-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009903 ] + MICROKERNEL_TEST_HDRS,
9904 deps = MICROKERNEL_TEST_DEPS,
9905)
9906
Marat Dukhan0461f2d2021-08-08 12:36:29 -07009907xnnpack_unit_test(
9908 name = "xx_pad_test",
9909 srcs = [
9910 "test/xx-pad.cc",
9911 "test/pad-microkernel-tester.h",
9912 ] + MICROKERNEL_TEST_HDRS,
9913 deps = MICROKERNEL_TEST_DEPS,
9914)
9915
Marat Dukhan20c3b922020-03-10 03:45:06 -07009916########################## Size tests for the library #########################
Marat Dukhan08c4a432019-10-03 09:29:21 -07009917
9918xnnpack_binary(
Marat Dukhan20c3b922020-03-10 03:45:06 -07009919 name = "operator_size_test",
9920 srcs = ["test/operator-size.c"],
Marat Dukhanf0cb70a2021-03-30 15:45:15 -07009921 deps = [":xnnpack_for_tfjs"],
Marat Dukhan08c4a432019-10-03 09:29:21 -07009922)
9923
Marat Dukhan20c3b922020-03-10 03:45:06 -07009924xnnpack_binary(
9925 name = "subgraph_size_test",
9926 srcs = ["test/subgraph-size.c"],
9927 deps = [":XNNPACK"],
9928)
9929
9930########################### Unit tests for operators ##########################
Marat Dukhan08c4a432019-10-03 09:29:21 -07009931
9932xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -07009933 name = "abs_nc_test",
9934 srcs = [
9935 "test/abs-nc.cc",
9936 "test/abs-operator-tester.h",
9937 ],
9938 deps = OPERATOR_TEST_DEPS,
9939)
9940
9941xnnpack_unit_test(
Marat Dukhanb1a0fc32019-12-02 19:32:02 -08009942 name = "add_nd_test",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -08009943 timeout = "moderate",
Marat Dukhanb1a0fc32019-12-02 19:32:02 -08009944 srcs = [
9945 "test/add-nd.cc",
9946 "test/binary-elementwise-operator-tester.h",
9947 ],
Marat Dukhan1b354632020-03-23 12:50:22 -07009948 deps = OPERATOR_TEST_DEPS,
Marat Dukhanb1a0fc32019-12-02 19:32:02 -08009949)
9950
9951xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -08009952 name = "argmax_pooling_nhwc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009953 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -08009954 "test/argmax-pooling-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009955 "test/argmax-pooling-operator-tester.h",
9956 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -07009957 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07009958)
9959
9960xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -08009961 name = "average_pooling_nhwc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009962 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -08009963 "test/average-pooling-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009964 "test/average-pooling-operator-tester.h",
9965 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -07009966 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07009967)
9968
9969xnnpack_unit_test(
Marat Dukhan64e52512020-06-09 13:41:16 -07009970 name = "bankers_rounding_nc_test",
9971 srcs = [
9972 "test/bankers-rounding-nc.cc",
9973 "test/bankers-rounding-operator-tester.h",
9974 ],
9975 deps = OPERATOR_TEST_DEPS,
9976)
9977
9978xnnpack_unit_test(
9979 name = "ceiling_nc_test",
9980 srcs = [
9981 "test/ceiling-nc.cc",
9982 "test/ceiling-operator-tester.h",
9983 ],
9984 deps = OPERATOR_TEST_DEPS,
9985)
9986
9987xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -08009988 name = "channel_shuffle_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009989 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -08009990 "test/channel-shuffle-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009991 "test/channel-shuffle-operator-tester.h",
9992 ],
Marat Dukhan1b354632020-03-23 12:50:22 -07009993 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -07009994)
9995
9996xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -08009997 name = "clamp_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -07009998 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -08009999 "test/clamp-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010000 "test/clamp-operator-tester.h",
10001 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010002 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010003)
10004
10005xnnpack_unit_test(
Marat Dukhan065b11e2020-05-22 09:49:41 -070010006 name = "constant_pad_nd_test",
10007 srcs = [
10008 "test/constant-pad-nd.cc",
10009 "test/constant-pad-operator-tester.h",
10010 ],
10011 deps = OPERATOR_TEST_DEPS,
10012)
10013
10014xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010015 name = "convolution_nhwc_test",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -080010016 timeout = "moderate",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010017 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010018 "test/convolution-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010019 "test/convolution-operator-tester.h",
10020 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010021 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010022)
10023
10024xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010025 name = "convolution_nchw_test",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -080010026 timeout = "moderate",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010027 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010028 "test/convolution-nchw.cc",
10029 "test/convolution-operator-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010030 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010031 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010032)
10033
10034xnnpack_unit_test(
Marat Dukhan4e21b272020-06-04 18:45:01 -070010035 name = "copy_nc_test",
10036 srcs = [
10037 "test/copy-nc.cc",
10038 "test/copy-operator-tester.h",
10039 ],
10040 deps = OPERATOR_TEST_DEPS,
10041)
10042
10043xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010044 name = "deconvolution_nhwc_test",
Artsiom Ablavatskic1aa2972020-12-08 11:23:34 -080010045 timeout = "moderate",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010046 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010047 "test/deconvolution-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010048 "test/deconvolution-operator-tester.h",
10049 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -070010050 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010051)
10052
10053xnnpack_unit_test(
Marat Dukhan188d1042020-11-24 23:39:40 -080010054 name = "depth_to_space_nchw2nhwc_test",
Artsiom Ablavatski0f1dc182020-11-05 19:21:50 -080010055 srcs = [
Marat Dukhan188d1042020-11-24 23:39:40 -080010056 "test/depth-to-space-nchw2nhwc.cc",
Artsiom Ablavatski0f1dc182020-11-05 19:21:50 -080010057 "test/depth-to-space-operator-tester.h",
10058 ] + OPERATOR_TEST_PARAMS_HDRS,
10059 deps = OPERATOR_TEST_DEPS,
10060)
10061
10062xnnpack_unit_test(
Marat Dukhan0e521172020-11-25 13:10:04 -080010063 name = "depth_to_space_nhwc_test",
10064 srcs = [
10065 "test/depth-to-space-nhwc.cc",
10066 "test/depth-to-space-operator-tester.h",
10067 ] + OPERATOR_TEST_PARAMS_HDRS,
10068 deps = OPERATOR_TEST_DEPS,
10069)
10070
10071xnnpack_unit_test(
Marat Dukhan69180502019-12-06 15:00:31 -080010072 name = "divide_nd_test",
10073 srcs = [
10074 "test/binary-elementwise-operator-tester.h",
10075 "test/divide-nd.cc",
10076 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010077 deps = OPERATOR_TEST_DEPS,
Marat Dukhan69180502019-12-06 15:00:31 -080010078)
10079
10080xnnpack_unit_test(
Marat Dukhanb6bd4bc2020-12-01 17:01:40 -080010081 name = "elu_nc_test",
10082 srcs = [
10083 "test/elu-nc.cc",
10084 "test/elu-operator-tester.h",
10085 ],
10086 deps = OPERATOR_TEST_DEPS,
10087)
10088
10089xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010090 name = "fully_connected_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010091 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010092 "test/fully-connected-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010093 "test/fully-connected-operator-tester.h",
10094 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010095 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010096)
10097
10098xnnpack_unit_test(
Marat Dukhan64e52512020-06-09 13:41:16 -070010099 name = "floor_nc_test",
10100 srcs = [
10101 "test/floor-nc.cc",
10102 "test/floor-operator-tester.h",
10103 ],
10104 deps = OPERATOR_TEST_DEPS,
10105)
10106
10107xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010108 name = "global_average_pooling_nwc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010109 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010110 "test/global-average-pooling-nwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010111 "test/global-average-pooling-operator-tester.h",
Marat Dukhanef61d022020-06-19 13:54:49 -070010112 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -070010113 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010114)
10115
10116xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010117 name = "global_average_pooling_ncw_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010118 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010119 "test/global-average-pooling-ncw.cc",
10120 "test/global-average-pooling-operator-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010121 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010122 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010123)
10124
10125xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010126 name = "hardswish_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010127 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010128 "test/hardswish-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010129 "test/hardswish-operator-tester.h",
10130 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010131 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010132)
10133
10134xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010135 name = "leaky_relu_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010136 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010137 "test/leaky-relu-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010138 "test/leaky-relu-operator-tester.h",
10139 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010140 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010141)
10142
10143xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010144 name = "max_pooling_nhwc_test",
Artsiom Ablavatski2202c812021-01-22 14:16:43 -080010145 timeout = "moderate",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010146 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010147 "test/max-pooling-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010148 "test/max-pooling-operator-tester.h",
10149 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -070010150 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010151)
10152
10153xnnpack_unit_test(
Marat Dukhan79e7f842019-12-05 14:35:50 -080010154 name = "maximum_nd_test",
10155 srcs = [
10156 "test/binary-elementwise-operator-tester.h",
10157 "test/maximum-nd.cc",
10158 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010159 deps = OPERATOR_TEST_DEPS,
Marat Dukhan79e7f842019-12-05 14:35:50 -080010160)
10161
10162xnnpack_unit_test(
10163 name = "minimum_nd_test",
10164 srcs = [
10165 "test/binary-elementwise-operator-tester.h",
10166 "test/minimum-nd.cc",
10167 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010168 deps = OPERATOR_TEST_DEPS,
Marat Dukhan79e7f842019-12-05 14:35:50 -080010169)
10170
10171xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010172 name = "multiply_nd_test",
Marat Dukhancf557d42021-08-10 23:28:38 -070010173 timeout = "moderate",
Marat Dukhanca2733c2019-11-15 23:21:17 -080010174 srcs = [
Marat Dukhanb1a0fc32019-12-02 19:32:02 -080010175 "test/binary-elementwise-operator-tester.h",
Marat Dukhanefc47b82019-11-18 09:25:38 -080010176 "test/multiply-nd.cc",
Marat Dukhanca2733c2019-11-15 23:21:17 -080010177 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010178 deps = OPERATOR_TEST_DEPS,
Marat Dukhanca2733c2019-11-15 23:21:17 -080010179)
10180
10181xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -070010182 name = "negate_nc_test",
10183 srcs = [
10184 "test/negate-nc.cc",
10185 "test/negate-operator-tester.h",
10186 ],
10187 deps = OPERATOR_TEST_DEPS,
10188)
10189
10190xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010191 name = "prelu_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010192 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010193 "test/prelu-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010194 "test/prelu-operator-tester.h",
10195 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -070010196 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010197)
10198
10199xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010200 name = "resize_bilinear_nhwc_test",
Marat Dukhan69722492019-11-11 19:55:50 -080010201 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010202 "test/resize-bilinear-nhwc.cc",
Marat Dukhan69722492019-11-11 19:55:50 -080010203 "test/resize-bilinear-operator-tester.h",
10204 ] + OPERATOR_TEST_PARAMS_HDRS,
Marat Dukhan1b354632020-03-23 12:50:22 -070010205 deps = OPERATOR_TEST_DEPS,
Marat Dukhan69722492019-11-11 19:55:50 -080010206)
10207
10208xnnpack_unit_test(
Artsiom Ablavatski97918102020-10-27 15:52:59 -070010209 name = "resize_bilinear_nchw_test",
10210 srcs = [
10211 "test/resize-bilinear-nchw.cc",
10212 "test/resize-bilinear-operator-tester.h",
10213 ] + OPERATOR_TEST_PARAMS_HDRS,
10214 deps = OPERATOR_TEST_DEPS,
10215)
10216
10217xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010218 name = "sigmoid_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010219 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010220 "test/sigmoid-nc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010221 "test/sigmoid-operator-tester.h",
10222 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010223 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010224)
10225
10226xnnpack_unit_test(
Marat Dukhanfd8e6892020-01-27 15:25:25 -080010227 name = "softmax_nc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010228 srcs = [
Marat Dukhanfd8e6892020-01-27 15:25:25 -080010229 "test/softmax-nc.cc",
10230 "test/softmax-operator-tester.h",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010231 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010232 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010233)
10234
10235xnnpack_unit_test(
Marat Dukhan5020b962020-06-08 13:30:10 -070010236 name = "square_nc_test",
10237 srcs = [
10238 "test/square-nc.cc",
10239 "test/square-operator-tester.h",
10240 ],
10241 deps = OPERATOR_TEST_DEPS,
10242)
10243
10244xnnpack_unit_test(
Marat Dukhan6804bbd2020-06-30 19:26:11 -070010245 name = "square_root_nc_test",
10246 srcs = [
10247 "test/square-root-nc.cc",
10248 "test/square-root-operator-tester.h",
10249 ],
10250 deps = OPERATOR_TEST_DEPS,
10251)
10252
10253xnnpack_unit_test(
Marat Dukhanf7399262020-06-05 10:58:44 -070010254 name = "squared_difference_nd_test",
10255 srcs = [
10256 "test/binary-elementwise-operator-tester.h",
10257 "test/squared-difference-nd.cc",
10258 ],
10259 deps = OPERATOR_TEST_DEPS,
10260)
10261
10262xnnpack_unit_test(
Marat Dukhan05f3f6d2019-12-03 15:13:53 -080010263 name = "subtract_nd_test",
10264 srcs = [
10265 "test/binary-elementwise-operator-tester.h",
10266 "test/subtract-nd.cc",
10267 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010268 deps = OPERATOR_TEST_DEPS,
Marat Dukhan05f3f6d2019-12-03 15:13:53 -080010269)
10270
10271xnnpack_unit_test(
Marat Dukhan64e52512020-06-09 13:41:16 -070010272 name = "truncation_nc_test",
10273 srcs = [
10274 "test/truncation-nc.cc",
10275 "test/truncation-operator-tester.h",
10276 ],
10277 deps = OPERATOR_TEST_DEPS,
10278)
10279
10280xnnpack_unit_test(
Marat Dukhanefc47b82019-11-18 09:25:38 -080010281 name = "unpooling_nhwc_test",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010282 srcs = [
Marat Dukhanefc47b82019-11-18 09:25:38 -080010283 "test/unpooling-nhwc.cc",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010284 "test/unpooling-operator-tester.h",
10285 ],
Marat Dukhan1b354632020-03-23 12:50:22 -070010286 deps = OPERATOR_TEST_DEPS,
Marat Dukhan08c4a432019-10-03 09:29:21 -070010287)
10288
Chao Mei6ddfc602020-05-13 22:29:36 -070010289############################### Misc unit tests ###############################
10290
10291xnnpack_unit_test(
10292 name = "memory_planner_test",
10293 srcs = [
10294 "test/memory-planner-test.cc",
10295 ],
10296 deps = [
10297 ":XNNPACK",
10298 ":memory_planner",
10299 ],
10300)
10301
XNNPACK Teamab8c4c82020-10-09 08:05:51 -070010302xnnpack_unit_test(
10303 name = "subgraph_nchw_test",
10304 srcs = [
10305 "src/xnnpack/subgraph.h",
10306 "test/subgraph-nchw.cc",
10307 "test/subgraph-tester.h",
10308 ],
10309 deps = [
10310 ":XNNPACK",
10311 ],
10312)
10313
Marat Dukhan08c4a432019-10-03 09:29:21 -070010314############################# Build configurations #############################
10315
Marat Dukhanb8642352019-10-30 15:43:02 -070010316# Enables usage of assembly kernels.
Marat Dukhan08c4a432019-10-03 09:29:21 -070010317config_setting(
Marat Dukhanb8642352019-10-30 15:43:02 -070010318 name = "xnn_enable_assembly_explicit_true",
10319 define_values = {"xnn_enable_assembly": "true"},
10320)
10321
10322# Disables usage of assembly kernels.
10323config_setting(
10324 name = "xnn_enable_assembly_explicit_false",
10325 define_values = {"xnn_enable_assembly": "false"},
10326)
10327
Marat Dukhan9de90e02020-06-18 16:04:12 -070010328# Enables usage of sparse inference.
10329config_setting(
10330 name = "xnn_enable_sparse_explicit_true",
10331 define_values = {"xnn_enable_sparse": "true"},
10332)
10333
10334# Disables usage of sparse inference.
10335config_setting(
10336 name = "xnn_enable_sparse_explicit_false",
10337 define_values = {"xnn_enable_sparse": "false"},
10338)
10339
Marat Dukhan05702cf2020-03-26 15:41:33 -070010340# Disables usage of HMP-aware optimizations.
10341config_setting(
10342 name = "xnn_enable_hmp_explicit_false",
10343 define_values = {"xnn_enable_hmp": "false"},
10344)
10345
Chao Mei6ddfc602020-05-13 22:29:36 -070010346# Enable usage of optimized memory allocation
10347config_setting(
10348 name = "xnn_enable_memopt_explicit_true",
Marat Dukhan03f46212021-03-30 21:29:49 -070010349 define_values = {"xnn_enable_memopt": "true"},
Chao Mei6ddfc602020-05-13 22:29:36 -070010350)
10351
10352# Disable usage of optimized memory allocation
10353config_setting(
10354 name = "xnn_enable_memopt_explicit_false",
Marat Dukhan03f46212021-03-30 21:29:49 -070010355 define_values = {"xnn_enable_memopt": "false"},
Chao Mei6ddfc602020-05-13 22:29:36 -070010356)
10357
Marat Dukhanb939cdb2021-03-30 18:51:51 -070010358# Enable QS8 inference in TFLite-specific version
10359config_setting(
10360 name = "xnn_enable_qs8_explicit_true",
10361 define_values = {"xnn_enable_qs8": "true"},
10362)
10363
10364# Disable QS8 inference in TFLite-specific version
10365config_setting(
10366 name = "xnn_enable_qs8_explicit_false",
10367 define_values = {"xnn_enable_qs8": "false"},
10368)
10369
Marat Dukhan8c8c1592021-07-13 13:59:02 -070010370# Enable QU8 inference in TFLite-specific version
10371config_setting(
10372 name = "xnn_enable_qu8_explicit_true",
10373 define_values = {"xnn_enable_qu8": "true"},
10374)
10375
10376# Disable QU8 inference in TFLite-specific version
10377config_setting(
10378 name = "xnn_enable_qu8_explicit_false",
10379 define_values = {"xnn_enable_qu8": "false"},
10380)
10381
Marat Dukhan189c1d02021-09-03 15:39:54 -070010382# Target Chrome M87 instructions in WAsm SIMD build
10383config_setting(
10384 name = "xnn_wasmsimd_version_m87",
10385 define_values = {"xnn_wasmsimd_version": "m87"},
10386)
10387
10388# Target Chrome M88 instructions in WAsm SIMD build
10389config_setting(
10390 name = "xnn_wasmsimd_version_m88",
10391 define_values = {"xnn_wasmsimd_version": "m88"},
10392)
10393
10394# Target Chrome M91 instructions in WAsm SIMD build
10395config_setting(
10396 name = "xnn_wasmsimd_version_m91",
10397 define_values = {"xnn_wasmsimd_version": "m91"},
10398)
10399
Marat Dukhanb8642352019-10-30 15:43:02 -070010400# Builds with -c dbg
10401config_setting(
10402 name = "debug_build",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010403 values = {
Marat Dukhanb8642352019-10-30 15:43:02 -070010404 "compilation_mode": "dbg",
10405 },
10406)
10407
10408# Builds with -c opt
10409config_setting(
10410 name = "optimized_build",
10411 values = {
10412 "compilation_mode": "opt",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010413 },
10414)
10415
10416config_setting(
Marat Dukhan52e44432021-08-20 11:58:11 -070010417 name = "linux_arm64",
10418 values = {"cpu": "aarch64"},
10419)
10420
10421config_setting(
Marat Dukhanb8642352019-10-30 15:43:02 -070010422 name = "linux_k8",
10423 values = {"cpu": "k8"},
10424)
10425
10426config_setting(
Marat Dukhan582094e2020-04-30 17:21:25 -070010427 name = "linux_arm",
10428 values = {"cpu": "arm"},
Marat Dukhan4e45e662019-10-03 15:40:24 -070010429)
10430
10431config_setting(
Marat Dukhanf0bd4de2020-06-15 15:53:19 -070010432 name = "linux_armeabi",
10433 values = {"cpu": "armeabi"},
10434)
10435
10436config_setting(
Terry Heo68eef3f2020-04-13 22:53:52 -070010437 name = "linux_armhf",
10438 values = {"cpu": "armhf"},
10439)
10440
10441config_setting(
Marat Dukhana720e932020-06-10 13:01:11 -070010442 name = "linux_armv7a",
10443 values = {"cpu": "armv7a"},
10444)
10445
10446config_setting(
Marat Dukhan08c4a432019-10-03 09:29:21 -070010447 name = "android",
10448 values = {"crosstool_top": "//external:android/crosstool"},
10449)
10450
10451config_setting(
10452 name = "android_armv7",
10453 values = {
10454 "crosstool_top": "//external:android/crosstool",
10455 "cpu": "armeabi-v7a",
10456 },
10457)
10458
10459config_setting(
10460 name = "android_arm64",
10461 values = {
10462 "crosstool_top": "//external:android/crosstool",
10463 "cpu": "arm64-v8a",
10464 },
10465)
10466
10467config_setting(
10468 name = "android_x86",
10469 values = {
10470 "crosstool_top": "//external:android/crosstool",
10471 "cpu": "x86",
10472 },
10473)
10474
10475config_setting(
10476 name = "android_x86_64",
10477 values = {
10478 "crosstool_top": "//external:android/crosstool",
10479 "cpu": "x86_64",
10480 },
10481)
10482
10483config_setting(
Marat Dukhan10a38082020-04-17 03:58:35 -070010484 name = "windows_x86_64",
10485 values = {"cpu": "x64_windows"},
Marat Dukhan9fe932e2020-04-11 17:14:15 -070010486)
10487
10488config_setting(
Marat Dukhan10a38082020-04-17 03:58:35 -070010489 name = "windows_x86_64_clang",
10490 values = {
10491 "compiler": "clang-cl",
10492 "cpu": "x64_windows",
10493 },
10494)
10495
10496config_setting(
10497 name = "windows_x86_64_mingw",
10498 values = {
10499 "compiler": "mingw-gcc",
10500 "cpu": "x64_windows",
10501 },
10502)
10503
10504config_setting(
10505 name = "windows_x86_64_msys",
10506 values = {
10507 "compiler": "msys-gcc",
10508 "cpu": "x64_windows",
10509 },
Marat Dukhan9fe932e2020-04-11 17:14:15 -070010510)
10511
10512config_setting(
Marat Dukhan885ca242019-10-07 09:17:32 -070010513 name = "macos_x86_64",
10514 values = {
10515 "apple_platform_type": "macos",
10516 "cpu": "darwin",
10517 },
10518)
10519
10520config_setting(
Simon Maurerae33ab82021-03-03 23:38:22 +010010521 name = "macos_arm64",
10522 values = {
10523 "apple_platform_type": "macos",
10524 "cpu": "darwin_arm64",
10525 },
10526)
10527
10528config_setting(
Marat Dukhan08c4a432019-10-03 09:29:21 -070010529 name = "emscripten",
XNNPACK Team3bfbdaf2021-03-29 15:26:23 -070010530 values = {"crosstool_top": "@emsdk//emscripten_toolchain:everything"},
Marat Dukhan08c4a432019-10-03 09:29:21 -070010531)
10532
10533config_setting(
10534 name = "emscripten_wasm",
10535 values = {
XNNPACK Team3bfbdaf2021-03-29 15:26:23 -070010536 "crosstool_top": "@emsdk//emscripten_toolchain:everything",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010537 "cpu": "wasm",
10538 },
10539)
10540
10541config_setting(
10542 name = "emscripten_wasmsimd",
10543 values = {
XNNPACK Team3bfbdaf2021-03-29 15:26:23 -070010544 "crosstool_top": "@emsdk//emscripten_toolchain:everything",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010545 "cpu": "wasm",
Marat Dukhan81c62602020-05-29 13:22:49 -070010546 "copt": "-msimd128",
Marat Dukhan08c4a432019-10-03 09:29:21 -070010547 },
10548)
10549
10550config_setting(
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010551 name = "ios_armv7",
10552 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010553 "apple_platform_type": "ios",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010554 "cpu": "ios_armv7",
10555 },
10556)
10557
10558config_setting(
10559 name = "ios_arm64",
10560 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010561 "apple_platform_type": "ios",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010562 "cpu": "ios_arm64",
10563 },
10564)
10565
10566config_setting(
10567 name = "ios_arm64e",
10568 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010569 "apple_platform_type": "ios",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010570 "cpu": "ios_arm64e",
10571 },
10572)
10573
10574config_setting(
10575 name = "ios_x86",
10576 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010577 "apple_platform_type": "ios",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010578 "cpu": "ios_i386",
10579 },
10580)
10581
10582config_setting(
10583 name = "ios_x86_64",
10584 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010585 "apple_platform_type": "ios",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010586 "cpu": "ios_x86_64",
10587 },
10588)
10589
10590config_setting(
10591 name = "watchos_armv7k",
10592 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010593 "apple_platform_type": "watchos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010594 "cpu": "watchos_armv7k",
10595 },
10596)
10597
10598config_setting(
10599 name = "watchos_arm64_32",
10600 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010601 "apple_platform_type": "watchos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010602 "cpu": "watchos_arm64_32",
10603 },
10604)
10605
10606config_setting(
10607 name = "watchos_x86",
10608 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010609 "apple_platform_type": "watchos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010610 "cpu": "watchos_i386",
10611 },
10612)
10613
10614config_setting(
10615 name = "watchos_x86_64",
10616 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010617 "apple_platform_type": "watchos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010618 "cpu": "watchos_x86_64",
10619 },
10620)
10621
10622config_setting(
10623 name = "tvos_arm64",
10624 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010625 "apple_platform_type": "tvos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010626 "cpu": "tvos_arm64",
10627 },
10628)
10629
10630config_setting(
10631 name = "tvos_x86_64",
10632 values = {
Marat Dukhanf85fc332020-02-13 00:05:20 -080010633 "apple_platform_type": "tvos",
Marat Dukhan1498d1d2020-02-11 20:00:05 -080010634 "cpu": "tvos_x86_64",
10635 },
10636)