Blame - lib/Target/ARM/Disassembler/ARMDisassembler.cpp - platform/external/llvm

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Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCContext.h"
				17	#include "llvm/MC/MCExpr.h"
				18	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	19	#include "llvm/MC/MCInst.h"
Benjamin Kramer	eea66f6	2011-11-11 12:39:41 +0000	[diff] [blame]	20	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	75e3b7f	2012-04-03 15:48:14 +0000	[diff] [blame]	21	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	24	#include "llvm/Support/LEB128.h"
Chandler Carruth	d04a8d4	2012-12-03 16:50:05 +0000	[diff] [blame]	25	#include "llvm/Support/MemoryObject.h"
Evan Cheng	3e74d6f	2011-08-24 18:08:43 +0000	[diff] [blame]	26	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	27	#include "llvm/Support/raw_ostream.h"
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	28	#include <vector>
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	29
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	30	using namespace llvm;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	31
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	68	unsigned NumTZ = CountTrailingZeros_32(Mask);
				69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI) :
				94	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
				101	DecodeStatus getInstruction(MCInst &instr,
				102	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	103	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	104	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	105	raw_ostream &vStream,
				106	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	107	};
				108
				109	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				110	class ThumbDisassembler : public MCDisassembler {
				111	public:
				112	/// Constructor - Initializes the disassembler.
				113	///
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	114	ThumbDisassembler(const MCSubtargetInfo &STI) :
				115	MCDisassembler(STI) {
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	116	}
				117
				118	~ThumbDisassembler() {
				119	}
				120
				121	/// getInstruction - See MCDisassembler.
				122	DecodeStatus getInstruction(MCInst &instr,
				123	uint64_t &size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	124	const MemoryObject &region,
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	125	uint64_t address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	126	raw_ostream &vStream,
				127	raw_ostream &cStream) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	128
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	129	private:
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	130	mutable ITStatus ITBlock;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	131	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	a1c1100	2011-09-01 23:35:51 +0000	[diff] [blame]	132	void UpdateThumbVFPPredicate(MCInst&) const;
				133	};
				134	}
				135
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	136	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	137	switch (In) {
				138	case MCDisassembler::Success:
				139	// Out stays the same.
				140	return true;
				141	case MCDisassembler::SoftFail:
				142	Out = In;
				143	return true;
				144	case MCDisassembler::Fail:
				145	Out = In;
				146	return false;
				147	}
David Blaikie	4d6ccb5	2012-01-20 21:51:11 +0000	[diff] [blame]	148	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	149	}
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	150
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	151
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	152	// Forward declare these because the autogenerated code will reference them.
				153	// Definitions are further down.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	154	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	156	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	157	unsigned RegNo, uint64_t Address,
				158	const void *Decoder);
Mihai Popa	f86e436	2013-05-13 14:10:04 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				160	unsigned RegNo, uint64_t Address,
				161	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	164	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	165	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	168	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	169	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	175	unsigned RegNo,
				176	uint64_t Address,
				177	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	178	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	179	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	181	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	183	unsigned RegNo, uint64_t Address,
				184	const void *Decoder);
Johnny Chen	270159f	2010-08-12 01:40:54 +0000	[diff] [blame]	185
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	198
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	199	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	200	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Address,
				206	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
				215
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	216	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	217	unsigned Insn,
				218	uint64_t Adddress,
				219	const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	220	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	221	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	236	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				237	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	238	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	239	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	240	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	241	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Mihai Popa	30a7a7c	2013-05-20 14:57:05 +0000	[diff] [blame]	244	static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
				248	static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
				249	uint64_t Address, const void *Decoder);
				250	static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
				251	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	284	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	285	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Quentin Colombet	7c4cf03	2013-04-17 18:46:12 +0000	[diff] [blame]	322	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				323	const void *Decoder);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	324
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	325
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	326	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	327	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	328	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	329	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	350	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	351	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	352	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	353	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	354	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	355	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	356	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	357	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	374	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	375	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
				388
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	389	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	390	uint64_t Address, const void *Decoder);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	391	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				392	uint64_t Address, const void *Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	393	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	9899f70	2010-04-13 21:21:57 +0000	[diff] [blame]	394
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	395	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				396	return new ARMDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	397	}
				398
James Molloy	b950585	2011-09-07 17:24:38 +0000	[diff] [blame]	399	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				400	return new ThumbDisassembler(STI);
Johnny Chen	b68a3ee	2010-04-02 22:27:38 +0000	[diff] [blame]	401	}
				402
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	403	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	404	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	405	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	406	raw_ostream &os,
				407	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	408	CommentStream = &cs;
				409
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	410	uint8_t bytes[4];
				411
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	412	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				413	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				414
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	415	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	416	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				417	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	418	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	419	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	420
				421	// Encoded as a small-endian 32-bit word in the stream.
				422	uint32_t insn = (bytes[3] << 24) \|
				423	(bytes[2] << 16) \|
				424	(bytes[1] << 8) \|
				425	(bytes[0] << 0);
				426
				427	// Calling the auto-generated decoder function.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	428	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				429	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	430	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	431	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	432	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	433	}
				434
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	435	// VFP and NEON instructions, similarly, are shared between ARM
				436	// and Thumb modes.
				437	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	438	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	439	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	440	Size = 4;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	441	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	442	}
				443
				444	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	445	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				446	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	447	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	448	Size = 4;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	449	// Add a fake predicate operand, because we share these instruction
				450	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	451	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				452	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	453	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	454	}
				455
				456	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	457	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				458	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	459	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	460	Size = 4;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	461	// Add a fake predicate operand, because we share these instruction
				462	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	463	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				464	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	465	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	466	}
				467
				468	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	469	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				470	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	471	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	472	Size = 4;
				473	// Add a fake predicate operand, because we share these instruction
				474	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	475	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				476	return MCDisassembler::Fail;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	477	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	478	}
				479
				480	MI.clear();
				481
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	482	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	483	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	484	}
				485
				486	namespace llvm {
Benjamin Kramer	1a2f988	2011-10-22 16:50:00 +0000	[diff] [blame]	487	extern const MCInstrDesc ARMInsts[];
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	488	}
				489
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	490	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				491	/// immediate Value in the MCInst. The immediate Value has had any PC
				492	/// adjustment made by the caller. If the instruction is a branch instruction
				493	/// then isBranch is true, else false. If the getOpInfo() function was set as
				494	/// part of the setupForSymbolicDisassembly() call then that function is called
				495	/// to get any symbolic information at the Address for this instruction. If
				496	/// that returns non-zero then the symbolic information it returns is used to
				497	/// create an MCExpr and that is added as an operand to the MCInst. If
				498	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				499	/// Value is done and if a symbol is found an MCExpr is created with that, else
				500	/// an MCExpr with Value is created. This function returns true if it adds an
				501	/// operand to the MCInst and false otherwise.
				502	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				503	bool isBranch, uint64_t InstSize,
				504	MCInst &MI, const void *Decoder) {
				505	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				506	LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	507	struct LLVMOpInfo1 SymbolicOp;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	508	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	509	SymbolicOp.Value = Value;
				510	void *DisInfo = Dis->getDisInfoBlock();
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	511
				512	if (!getOpInfo \|\|
				513	!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
				514	// Clear SymbolicOp.Value from above and also all other fields.
				515	memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
				516	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				517	if (!SymbolLookUp)
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	518	return false;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	519	uint64_t ReferenceType;
				520	if (isBranch)
				521	ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
				522	else
				523	ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
				524	const char *ReferenceName;
Kevin Enderby	88d1266	2012-10-18 21:49:18 +0000	[diff] [blame]	525	uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
				526	const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
				527	Address, &ReferenceName);
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	528	if (Name) {
				529	SymbolicOp.AddSymbol.Name = Name;
				530	SymbolicOp.AddSymbol.Present = true;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	531	}
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	532	// For branches always create an MCExpr so it gets printed as hex address.
				533	else if (isBranch) {
				534	SymbolicOp.Value = Value;
				535	}
				536	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
				537	(*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
				538	if (!Name && !isBranch)
				539	return false;
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	540	}
				541
				542	MCContext *Ctx = Dis->getMCContext();
				543	const MCExpr *Add = NULL;
				544	if (SymbolicOp.AddSymbol.Present) {
				545	if (SymbolicOp.AddSymbol.Name) {
				546	StringRef Name(SymbolicOp.AddSymbol.Name);
				547	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				548	Add = MCSymbolRefExpr::Create(Sym, *Ctx);
				549	} else {
				550	Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
				551	}
				552	}
				553
				554	const MCExpr *Sub = NULL;
				555	if (SymbolicOp.SubtractSymbol.Present) {
				556	if (SymbolicOp.SubtractSymbol.Name) {
				557	StringRef Name(SymbolicOp.SubtractSymbol.Name);
				558	MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
				559	Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
				560	} else {
				561	Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
				562	}
				563	}
				564
				565	const MCExpr *Off = NULL;
				566	if (SymbolicOp.Value != 0)
				567	Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
				568
				569	const MCExpr *Expr;
				570	if (Sub) {
				571	const MCExpr *LHS;
				572	if (Add)
				573	LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
				574	else
				575	LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
				576	if (Off != 0)
				577	Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
				578	else
				579	Expr = LHS;
				580	} else if (Add) {
				581	if (Off != 0)
				582	Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
				583	else
				584	Expr = Add;
				585	} else {
				586	if (Off != 0)
				587	Expr = Off;
				588	else
				589	Expr = MCConstantExpr::Create(0, *Ctx);
				590	}
				591
				592	if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
				593	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
				594	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
				595	MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
				596	else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
				597	MI.addOperand(MCOperand::CreateExpr(Expr));
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	598	else
Craig Topper	bc21981	2012-02-07 02:50:20 +0000	[diff] [blame]	599	llvm_unreachable("bad SymbolicOp.VariantKind");
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	600
				601	return true;
				602	}
				603
				604	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				605	/// referenced by a load instruction with the base register that is the Pc.
				606	/// These can often be values in a literal pool near the Address of the
				607	/// instruction. The Address of the instruction and its immediate Value are
				608	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	c8e41c5	2012-07-23 08:51:15 +0000	[diff] [blame]	609	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	610	/// the referenced address is that of a symbol. Or it will return a pointer to
				611	/// a literal 'C' string if the referenced address of the literal pool's entry
				612	/// is an address into a section with 'C' string literals.
				613	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	614	const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	615	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				616	LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
				617	if (SymbolLookUp) {
				618	void *DisInfo = Dis->getDisInfoBlock();
				619	uint64_t ReferenceType;
				620	ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
				621	const char *ReferenceName;
				622	(void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
				623	if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr \|\|
				624	ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
				625	(*Dis->CommentStream) << "literal pool for: " << ReferenceName;
				626	}
				627	}
				628
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	629	// Thumb1 instructions don't have explicit S bits. Rather, they
				630	// implicitly set CPSR. Since it's not represented in the encoding, the
				631	// auto-generated decoder won't inject the CPSR operand. We need to fix
				632	// that as a post-pass.
				633	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				634	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	635	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	636	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	637	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				638	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	639	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	640	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	641	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				642	return;
				643	}
				644	}
				645
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	646	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	647	}
				648
				649	// Most Thumb instructions don't have explicit predicates in the
				650	// encoding, but rather get their predicates from IT context. We need
				651	// to fix up the predicate operands using this context information as a
				652	// post-pass.
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	653	MCDisassembler::DecodeStatus
				654	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	655	MCDisassembler::DecodeStatus S = Success;
				656
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	657	// A few instructions actually have predicates encoded in them. Don't
				658	// try to overwrite it if we're seeing one of those.
				659	switch (MI.getOpcode()) {
				660	case ARM::tBcc:
				661	case ARM::t2Bcc:
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	662	case ARM::tCBZ:
				663	case ARM::tCBNZ:
Owen Anderson	9f666b5	2011-09-19 23:47:10 +0000	[diff] [blame]	664	case ARM::tCPS:
				665	case ARM::t2CPS3p:
				666	case ARM::t2CPS2p:
				667	case ARM::t2CPS1p:
Owen Anderson	d9346fb	2011-09-19 23:57:20 +0000	[diff] [blame]	668	case ARM::tMOVSr:
Owen Anderson	c18e940	2011-10-13 17:58:39 +0000	[diff] [blame]	669	case ARM::tSETEND:
Owen Anderson	441462f	2011-09-08 22:48:37 +0000	[diff] [blame]	670	// Some instructions (mostly conditional branches) are not
				671	// allowed in IT blocks.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	672	if (ITBlock.instrInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	673	S = SoftFail;
				674	else
				675	return Success;
				676	break;
				677	case ARM::tB:
				678	case ARM::t2B:
Owen Anderson	04c7877	2011-09-19 22:34:23 +0000	[diff] [blame]	679	case ARM::t2TBB:
				680	case ARM::t2TBH:
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	681	// Some instructions (mostly unconditional branches) can
				682	// only appears at the end of, or outside of, an IT.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	683	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	684	S = SoftFail;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	685	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	686	default:
				687	break;
				688	}
				689
				690	// If we're in an IT block, base the predicate on that. Otherwise,
				691	// assume a predicate of AL.
				692	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	693	CC = ITBlock.getITCC();
				694	if (CC == 0xF)
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	695	CC = ARMCC::AL;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	696	if (ITBlock.instrInITBlock())
				697	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	698
				699	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	700	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	701	MCInst::iterator I = MI.begin();
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	702	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				703	if (I == MI.end()) break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	704	if (OpInfo[i].isPredicate()) {
				705	I = MI.insert(I, MCOperand::CreateImm(CC));
				706	++I;
				707	if (CC == ARMCC::AL)
				708	MI.insert(I, MCOperand::CreateReg(0));
				709	else
				710	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	711	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	712	}
				713	}
				714
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	715	I = MI.insert(I, MCOperand::CreateImm(CC));
				716	++I;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	717	if (CC == ARMCC::AL)
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	718	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	719	else
Owen Anderson	0aa38ab	2011-08-17 18:14:48 +0000	[diff] [blame]	720	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	721
Owen Anderson	51f6a7a	2011-09-09 21:48:23 +0000	[diff] [blame]	722	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	723	}
				724
				725	// Thumb VFP instructions are a special case. Because we share their
				726	// encodings between ARM and Thumb modes, and they are predicable in ARM
				727	// mode, the auto-generated decoder will give them an (incorrect)
				728	// predicate operand. We need to rewrite these operands based on the IT
				729	// context as a post-pass.
				730	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				731	unsigned CC;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	732	CC = ITBlock.getITCC();
				733	if (ITBlock.instrInITBlock())
				734	ITBlock.advanceITState();
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	735
				736	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				737	MCInst::iterator I = MI.begin();
Owen Anderson	12a1e3b	2011-08-24 21:35:46 +0000	[diff] [blame]	738	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				739	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	740	if (OpInfo[i].isPredicate() ) {
				741	I->setImm(CC);
				742	++I;
				743	if (CC == ARMCC::AL)
				744	I->setReg(0);
				745	else
				746	I->setReg(ARM::CPSR);
				747	return;
				748	}
				749	}
				750	}
				751
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	752	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	adef06a	2012-02-29 01:09:06 +0000	[diff] [blame]	753	const MemoryObject &Region,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	754	uint64_t Address,
Owen Anderson	98c5dda	2011-09-15 23:38:46 +0000	[diff] [blame]	755	raw_ostream &os,
				756	raw_ostream &cs) const {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	757	CommentStream = &cs;
				758
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	759	uint8_t bytes[4];
				760
James Molloy	a5d5856	2011-09-07 19:42:28 +0000	[diff] [blame]	761	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				762	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				763
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	764	// We want to read exactly 2 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	765	if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
				766	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	767	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	768	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	769
				770	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	771	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				772	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	773	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	774	Size = 2;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	775	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	776	return result;
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	777	}
				778
				779	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	780	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				781	Address, this, STI);
Owen Anderson	1628030	2011-08-16 23:45:44 +0000	[diff] [blame]	782	if (result) {
				783	Size = 2;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	784	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	785	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	786	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	787	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	788	}
				789
				790	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	791	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				792	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	793	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	794	Size = 2;
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	795
				796	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				797	// the Thumb predicate.
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	798	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	7011eee	2011-10-06 23:33:11 +0000	[diff] [blame]	799	result = MCDisassembler::SoftFail;
				800
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	801	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	802
				803	// If we find an IT instruction, we need to parse its condition
				804	// code and mask operands so that we can apply them correctly
				805	// to the subsequent instructions.
				806	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	34626ac	2011-09-14 21:06:21 +0000	[diff] [blame]	807
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	808	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	809	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	810	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	811	}
				812
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	813	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	814	}
				815
				816	// We want to read exactly 4 bytes of data.
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	817	if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
				818	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	819	return MCDisassembler::Fail;
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	820	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	821
				822	uint32_t insn32 = (bytes[3] << 8) \|
				823	(bytes[2] << 0) \|
				824	(bytes[1] << 24) \|
				825	(bytes[0] << 16);
				826	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	827	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				828	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	829	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	830	Size = 4;
Richard Barton	f4478f9	2012-04-24 11:13:20 +0000	[diff] [blame]	831	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	832	Check(result, AddThumbPredicate(MI));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	833	AddThumb1SBit(MI, InITBlock);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	834	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	835	}
				836
				837	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	838	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				839	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	840	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	841	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	842	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	843	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	844	}
				845
				846	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	847	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	848	if (result != MCDisassembler::Fail) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	849	Size = 4;
				850	UpdateThumbVFPPredicate(MI);
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	851	return result;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	852	}
				853
				854	MI.clear();
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	855	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				856	this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	857	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	858	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	859	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	860	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	861	}
				862
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	863	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	864	MI.clear();
				865	uint32_t NEONLdStInsn = insn32;
				866	NEONLdStInsn &= 0xF0FFFFFF;
				867	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	868	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				869	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	870	if (result != MCDisassembler::Fail) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	871	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	872	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	873	return result;
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	874	}
				875	}
				876
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	877	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	ef2865a	2011-08-15 23:38:54 +0000	[diff] [blame]	878	MI.clear();
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	879	uint32_t NEONDataInsn = insn32;
				880	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				881	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				882	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	883	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				884	Address, this, STI);
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	885	if (result != MCDisassembler::Fail) {
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	886	Size = 4;
Owen Anderson	d2fc31b	2011-09-08 22:42:49 +0000	[diff] [blame]	887	Check(result, AddThumbPredicate(MI));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	888	return result;
Owen Anderson	8533eba	2011-08-10 19:01:10 +0000	[diff] [blame]	889	}
				890	}
				891
Benjamin Kramer	86ce852	2011-08-26 18:21:36 +0000	[diff] [blame]	892	Size = 0;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	893	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	894	}
				895
				896
				897	extern "C" void LLVMInitializeARMDisassembler() {
				898	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				899	createARMDisassembler);
				900	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				901	createThumbDisassembler);
				902	}
				903
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	904	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	905	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				906	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				907	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				908	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				909	};
				910
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	911	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	912	uint64_t Address, const void *Decoder) {
				913	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	914	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	915
				916	unsigned Register = GPRDecoderTable[RegNo];
				917	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	918	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	919	}
				920
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	921	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	922	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	923	uint64_t Address, const void *Decoder) {
Silviu Baranga	5c062ad	2012-03-20 15:54:56 +0000	[diff] [blame]	924	DecodeStatus S = MCDisassembler::Success;
				925
				926	if (RegNo == 15)
				927	S = MCDisassembler::SoftFail;
				928
				929	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				930
				931	return S;
Owen Anderson	51c9805	2011-08-09 22:48:45 +0000	[diff] [blame]	932	}
				933
Mihai Popa	f86e436	2013-05-13 14:10:04 +0000	[diff] [blame]	934	static DecodeStatus
				935	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				936	uint64_t Address, const void *Decoder) {
				937	DecodeStatus S = MCDisassembler::Success;
				938
				939	if (RegNo == 15)
				940	{
				941	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				942	return MCDisassembler::Success;
				943	}
				944
				945	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				946	return S;
				947	}
				948
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	949	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	950	uint64_t Address, const void *Decoder) {
				951	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	952	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	953	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				954	}
				955
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	956	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	957	uint64_t Address, const void *Decoder) {
				958	unsigned Register = 0;
				959	switch (RegNo) {
				960	case 0:
				961	Register = ARM::R0;
				962	break;
				963	case 1:
				964	Register = ARM::R1;
				965	break;
				966	case 2:
				967	Register = ARM::R2;
				968	break;
				969	case 3:
				970	Register = ARM::R3;
				971	break;
				972	case 9:
				973	Register = ARM::R9;
				974	break;
				975	case 12:
				976	Register = ARM::R12;
				977	break;
				978	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	979	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
				982	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	983	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	984	}
				985
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	986	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	987	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	988	if (RegNo == 13 \|\| RegNo == 15) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	989	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				990	}
				991
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	992	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	993	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				994	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				995	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				996	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				997	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				998	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				999	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				1000	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				1001	};
				1002
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1003	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1004	uint64_t Address, const void *Decoder) {
				1005	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1006	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1007
				1008	unsigned Register = SPRDecoderTable[RegNo];
				1009	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1010	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1011	}
				1012
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1013	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1014	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1015	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1016	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1017	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1018	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1019	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1020	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1021	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1022	};
				1023
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1024	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1025	uint64_t Address, const void *Decoder) {
				1026	if (RegNo > 31)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1027	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1028
				1029	unsigned Register = DPRDecoderTable[RegNo];
				1030	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1031	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1032	}
				1033
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1034	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1035	uint64_t Address, const void *Decoder) {
				1036	if (RegNo > 7)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1037	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1038	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1039	}
				1040
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1041	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1042	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1043	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1044	if (RegNo > 15)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1045	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1046	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1047	}
				1048
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1049	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1050	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1051	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1052	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1053	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1054	};
				1055
				1056
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1057	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1058	uint64_t Address, const void *Decoder) {
Mihai Popa	bac932e	2013-05-20 14:42:43 +0000	[diff] [blame]	1059	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1060	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1061	RegNo >>= 1;
				1062
				1063	unsigned Register = QPRDecoderTable[RegNo];
				1064	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1065	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1066	}
				1067
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1068	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1069	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1070	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1071	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1072	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1073	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1074	ARM::Q15
				1075	};
				1076
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1077	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	1078	uint64_t Address, const void *Decoder) {
				1079	if (RegNo > 30)
				1080	return MCDisassembler::Fail;
				1081
				1082	unsigned Register = DPairDecoderTable[RegNo];
				1083	Inst.addOperand(MCOperand::CreateReg(Register));
				1084	return MCDisassembler::Success;
				1085	}
				1086
Craig Topper	b78ca42	2012-03-11 07:16:55 +0000	[diff] [blame]	1087	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1088	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1089	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1090	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1091	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1092	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1093	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1094	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1095	ARM::D28_D30, ARM::D29_D31
				1096	};
				1097
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1098	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	1099	unsigned RegNo,
				1100	uint64_t Address,
				1101	const void *Decoder) {
				1102	if (RegNo > 29)
				1103	return MCDisassembler::Fail;
				1104
				1105	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1106	Inst.addOperand(MCOperand::CreateReg(Register));
				1107	return MCDisassembler::Success;
				1108	}
				1109
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1110	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1111	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1112	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	bd9091c	2011-08-09 21:07:45 +0000	[diff] [blame]	1113	// AL predicate is not allowed on Thumb1 branches.
				1114	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1115	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1116	Inst.addOperand(MCOperand::CreateImm(Val));
				1117	if (Val == ARMCC::AL) {
				1118	Inst.addOperand(MCOperand::CreateReg(0));
				1119	} else
				1120	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1121	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	}
				1123
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1124	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	uint64_t Address, const void *Decoder) {
				1126	if (Val)
				1127	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1128	else
				1129	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1130	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1131	}
				1132
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1133	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1134	uint64_t Address, const void *Decoder) {
				1135	uint32_t imm = Val & 0xFF;
				1136	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	ecb830e	2011-10-13 23:36:06 +0000	[diff] [blame]	1137	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1138	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1139	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1140	}
				1141
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1142	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1143	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1144	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1145
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1146	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1147	unsigned type = fieldFromInstruction(Val, 5, 2);
				1148	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1149
				1150	// Register-immediate
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1151	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1152	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1153
				1154	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1155	switch (type) {
				1156	case 0:
				1157	Shift = ARM_AM::lsl;
				1158	break;
				1159	case 1:
				1160	Shift = ARM_AM::lsr;
				1161	break;
				1162	case 2:
				1163	Shift = ARM_AM::asr;
				1164	break;
				1165	case 3:
				1166	Shift = ARM_AM::ror;
				1167	break;
				1168	}
				1169
				1170	if (Shift == ARM_AM::ror && imm == 0)
				1171	Shift = ARM_AM::rrx;
				1172
				1173	unsigned Op = Shift \| (imm << 3);
				1174	Inst.addOperand(MCOperand::CreateImm(Op));
				1175
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1176	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1177	}
				1178
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1179	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1180	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1181	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1182
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1183	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1184	unsigned type = fieldFromInstruction(Val, 5, 2);
				1185	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1186
				1187	// Register-register
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1188	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1189	return MCDisassembler::Fail;
				1190	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1191	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1192
				1193	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1194	switch (type) {
				1195	case 0:
				1196	Shift = ARM_AM::lsl;
				1197	break;
				1198	case 1:
				1199	Shift = ARM_AM::lsr;
				1200	break;
				1201	case 2:
				1202	Shift = ARM_AM::asr;
				1203	break;
				1204	case 3:
				1205	Shift = ARM_AM::ror;
				1206	break;
				1207	}
				1208
				1209	Inst.addOperand(MCOperand::CreateImm(Shift));
				1210
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1211	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1212	}
				1213
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1214	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1215	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1216	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1217
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1218	bool writebackLoad = false;
				1219	unsigned writebackReg = 0;
				1220	switch (Inst.getOpcode()) {
				1221	default:
				1222	break;
				1223	case ARM::LDMIA_UPD:
				1224	case ARM::LDMDB_UPD:
				1225	case ARM::LDMIB_UPD:
				1226	case ARM::LDMDA_UPD:
				1227	case ARM::t2LDMIA_UPD:
				1228	case ARM::t2LDMDB_UPD:
				1229	writebackLoad = true;
				1230	writebackReg = Inst.getOperand(0).getReg();
				1231	break;
				1232	}
				1233
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	1234	// Empty register lists are not allowed.
Benjamin Kramer	4dc8bdf	2013-05-19 22:01:57 +0000	[diff] [blame]	1235	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1236	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1237	if (Val & (1 << i)) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1238	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1239	return MCDisassembler::Fail;
Owen Anderson	921d01a	2011-09-09 23:13:33 +0000	[diff] [blame]	1240	// Writeback not allowed if Rn is in the target list.
				1241	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1242	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1243	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1244	}
				1245
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1246	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1247	}
				1248
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1249	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1250	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1251	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1252
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1253	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1254	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1255
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1256	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1257	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1258	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1259	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1260	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1261	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1262
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1263	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1264	}
				1265
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1266	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1267	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1268	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1269
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1270	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1271	unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Baranga	b422d0b	2012-05-03 16:38:40 +0000	[diff] [blame]	1272
				1273	regs = regs >> 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1274
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1275	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1276	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1277	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1278	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1279	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	1280	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1281
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1282	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1283	}
				1284
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1285	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1286	uint64_t Address, const void *Decoder) {
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1287	// This operand encodes a mask of contiguous zeros between a specified MSB
				1288	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1289	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1290	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	1291	// create the final mask.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1292	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1293	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1294
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1295	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	1c83093	2012-11-29 23:47:11 +0000	[diff] [blame]	1296	if (lsb > msb) {
				1297	Check(S, MCDisassembler::SoftFail);
				1298	// The check above will cause the warning for the "potentially undefined
				1299	// instruction encoding" but we can't build a bad MCOperand value here
				1300	// with a lsb > msb or else printing the MCInst will cause a crash.
				1301	lsb = msb;
				1302	}
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1303
Owen Anderson	8b22778	2011-09-16 23:04:48 +0000	[diff] [blame]	1304	uint32_t msb_mask = 0xFFFFFFFF;
				1305	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1306	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	89db0f6	2011-09-16 22:29:48 +0000	[diff] [blame]	1307
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1308	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	cb77551	2011-09-16 23:30:01 +0000	[diff] [blame]	1309	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1310	}
				1311
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1312	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1313	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1314	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1315
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1316	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1317	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1318	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1319	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1320	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1321	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1322
				1323	switch (Inst.getOpcode()) {
				1324	case ARM::LDC_OFFSET:
				1325	case ARM::LDC_PRE:
				1326	case ARM::LDC_POST:
				1327	case ARM::LDC_OPTION:
				1328	case ARM::LDCL_OFFSET:
				1329	case ARM::LDCL_PRE:
				1330	case ARM::LDCL_POST:
				1331	case ARM::LDCL_OPTION:
				1332	case ARM::STC_OFFSET:
				1333	case ARM::STC_PRE:
				1334	case ARM::STC_POST:
				1335	case ARM::STC_OPTION:
				1336	case ARM::STCL_OFFSET:
				1337	case ARM::STCL_PRE:
				1338	case ARM::STCL_POST:
				1339	case ARM::STCL_OPTION:
Owen Anderson	8a83f71	2011-09-07 21:10:42 +0000	[diff] [blame]	1340	case ARM::t2LDC_OFFSET:
				1341	case ARM::t2LDC_PRE:
				1342	case ARM::t2LDC_POST:
				1343	case ARM::t2LDC_OPTION:
				1344	case ARM::t2LDCL_OFFSET:
				1345	case ARM::t2LDCL_PRE:
				1346	case ARM::t2LDCL_POST:
				1347	case ARM::t2LDCL_OPTION:
				1348	case ARM::t2STC_OFFSET:
				1349	case ARM::t2STC_PRE:
				1350	case ARM::t2STC_POST:
				1351	case ARM::t2STC_OPTION:
				1352	case ARM::t2STCL_OFFSET:
				1353	case ARM::t2STCL_PRE:
				1354	case ARM::t2STCL_POST:
				1355	case ARM::t2STCL_OPTION:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1356	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1357	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1358	break;
				1359	default:
				1360	break;
				1361	}
				1362
				1363	Inst.addOperand(MCOperand::CreateImm(coproc));
				1364	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1365	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1366	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1367
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1368	switch (Inst.getOpcode()) {
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1369	case ARM::t2LDC2_OFFSET:
				1370	case ARM::t2LDC2L_OFFSET:
				1371	case ARM::t2LDC2_PRE:
				1372	case ARM::t2LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1373	case ARM::t2STC2_OFFSET:
				1374	case ARM::t2STC2L_OFFSET:
				1375	case ARM::t2STC2_PRE:
				1376	case ARM::t2STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1377	case ARM::LDC2_OFFSET:
				1378	case ARM::LDC2L_OFFSET:
				1379	case ARM::LDC2_PRE:
				1380	case ARM::LDC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1381	case ARM::STC2_OFFSET:
				1382	case ARM::STC2L_OFFSET:
				1383	case ARM::STC2_PRE:
				1384	case ARM::STC2L_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1385	case ARM::t2LDC_OFFSET:
				1386	case ARM::t2LDCL_OFFSET:
				1387	case ARM::t2LDC_PRE:
				1388	case ARM::t2LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1389	case ARM::t2STC_OFFSET:
				1390	case ARM::t2STCL_OFFSET:
				1391	case ARM::t2STC_PRE:
				1392	case ARM::t2STCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1393	case ARM::LDC_OFFSET:
				1394	case ARM::LDCL_OFFSET:
				1395	case ARM::LDC_PRE:
				1396	case ARM::LDCL_PRE:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1397	case ARM::STC_OFFSET:
				1398	case ARM::STCL_OFFSET:
				1399	case ARM::STC_PRE:
				1400	case ARM::STCL_PRE:
Jim Grosbach	81b2928	2011-10-12 21:59:02 +0000	[diff] [blame]	1401	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1402	Inst.addOperand(MCOperand::CreateImm(imm));
				1403	break;
				1404	case ARM::t2LDC2_POST:
				1405	case ARM::t2LDC2L_POST:
				1406	case ARM::t2STC2_POST:
				1407	case ARM::t2STC2L_POST:
				1408	case ARM::LDC2_POST:
				1409	case ARM::LDC2L_POST:
				1410	case ARM::STC2_POST:
				1411	case ARM::STC2L_POST:
				1412	case ARM::t2LDC_POST:
				1413	case ARM::t2LDCL_POST:
				1414	case ARM::t2STC_POST:
				1415	case ARM::t2STCL_POST:
				1416	case ARM::LDC_POST:
				1417	case ARM::LDCL_POST:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1418	case ARM::STC_POST:
				1419	case ARM::STCL_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1420	imm \|= U << 8;
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1421	// fall through.
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1422	default:
Jim Grosbach	c66e7af	2011-10-12 20:54:17 +0000	[diff] [blame]	1423	// The 'option' variant doesn't encode 'U' in the immediate since
				1424	// the immediate is unsigned [0,255].
				1425	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1426	break;
				1427	}
				1428
				1429	switch (Inst.getOpcode()) {
				1430	case ARM::LDC_OFFSET:
				1431	case ARM::LDC_PRE:
				1432	case ARM::LDC_POST:
				1433	case ARM::LDC_OPTION:
				1434	case ARM::LDCL_OFFSET:
				1435	case ARM::LDCL_PRE:
				1436	case ARM::LDCL_POST:
				1437	case ARM::LDCL_OPTION:
				1438	case ARM::STC_OFFSET:
				1439	case ARM::STC_PRE:
				1440	case ARM::STC_POST:
				1441	case ARM::STC_OPTION:
				1442	case ARM::STCL_OFFSET:
				1443	case ARM::STCL_PRE:
				1444	case ARM::STCL_POST:
				1445	case ARM::STCL_OPTION:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1446	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1447	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1448	break;
				1449	default:
				1450	break;
				1451	}
				1452
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1453	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1454	}
				1455
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1456	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1457	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1458	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1459	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1460
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1461	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1462	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1463	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1464	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1465	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1466	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1467	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1468	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1469
				1470	// On stores, the writeback operand precedes Rt.
				1471	switch (Inst.getOpcode()) {
				1472	case ARM::STR_POST_IMM:
				1473	case ARM::STR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1474	case ARM::STRB_POST_IMM:
				1475	case ARM::STRB_POST_REG:
Jim Grosbach	342ebd5	2011-08-11 22:18:00 +0000	[diff] [blame]	1476	case ARM::STRT_POST_REG:
				1477	case ARM::STRT_POST_IMM:
Jim Grosbach	10348e7	2011-08-11 20:04:56 +0000	[diff] [blame]	1478	case ARM::STRBT_POST_REG:
				1479	case ARM::STRBT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1480	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1481	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1482	break;
				1483	default:
				1484	break;
				1485	}
				1486
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1487	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1488	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1489
				1490	// On loads, the writeback operand comes after Rt.
				1491	switch (Inst.getOpcode()) {
				1492	case ARM::LDR_POST_IMM:
				1493	case ARM::LDR_POST_REG:
Owen Anderson	508e1d3	2011-08-11 20:47:56 +0000	[diff] [blame]	1494	case ARM::LDRB_POST_IMM:
				1495	case ARM::LDRB_POST_REG:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1496	case ARM::LDRBT_POST_REG:
				1497	case ARM::LDRBT_POST_IMM:
Jim Grosbach	5999926	2011-08-10 23:43:54 +0000	[diff] [blame]	1498	case ARM::LDRT_POST_REG:
				1499	case ARM::LDRT_POST_IMM:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1500	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1501	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1502	break;
				1503	default:
				1504	break;
				1505	}
				1506
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1507	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1508	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1509
				1510	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1511	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1512	Op = ARM_AM::sub;
				1513
				1514	bool writeback = (P == 0) \|\| (W == 1);
				1515	unsigned idx_mode = 0;
				1516	if (P && writeback)
				1517	idx_mode = ARMII::IndexModePre;
				1518	else if (!P && writeback)
				1519	idx_mode = ARMII::IndexModePost;
				1520
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1521	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1522	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	71156a6	2011-08-11 19:00:18 +0000	[diff] [blame]	1523
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1524	if (reg) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1525	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1526	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1527	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1528	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1529	case 0:
				1530	Opc = ARM_AM::lsl;
				1531	break;
				1532	case 1:
				1533	Opc = ARM_AM::lsr;
				1534	break;
				1535	case 2:
				1536	Opc = ARM_AM::asr;
				1537	break;
				1538	case 3:
				1539	Opc = ARM_AM::ror;
				1540	break;
				1541	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1542	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1543	}
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1544	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame]	1545	if (Opc == ARM_AM::ror && amt == 0)
				1546	Opc = ARM_AM::rrx;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1547	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1548
				1549	Inst.addOperand(MCOperand::CreateImm(imm));
				1550	} else {
				1551	Inst.addOperand(MCOperand::CreateReg(0));
				1552	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1553	Inst.addOperand(MCOperand::CreateImm(tmp));
				1554	}
				1555
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1556	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1557	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1558
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1559	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1560	}
				1561
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1562	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1563	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1564	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1565
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1566	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1567	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1568	unsigned type = fieldFromInstruction(Val, 5, 2);
				1569	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1570	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1571
Owen Anderson	51157d2	2011-08-09 21:38:14 +0000	[diff] [blame]	1572	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1573	switch (type) {
				1574	case 0:
				1575	ShOp = ARM_AM::lsl;
				1576	break;
				1577	case 1:
				1578	ShOp = ARM_AM::lsr;
				1579	break;
				1580	case 2:
				1581	ShOp = ARM_AM::asr;
				1582	break;
				1583	case 3:
				1584	ShOp = ARM_AM::ror;
				1585	break;
				1586	}
				1587
Tim Northover	93c7c44	2012-09-22 11:18:12 +0000	[diff] [blame]	1588	if (ShOp == ARM_AM::ror && imm == 0)
				1589	ShOp = ARM_AM::rrx;
				1590
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1591	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1592	return MCDisassembler::Fail;
				1593	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1594	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1595	unsigned shift;
				1596	if (U)
				1597	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1598	else
				1599	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1600	Inst.addOperand(MCOperand::CreateImm(shift));
				1601
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1602	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1603	}
				1604
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1605	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1606	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	1607	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1608	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1609
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1610	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1611	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1612	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1613	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1614	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1615	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1616	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1617	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1618	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1619	unsigned Rt2 = Rt + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1620
				1621	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1622
				1623	// For {LD,ST}RD, Rt must be even, else undefined.
				1624	switch (Inst.getOpcode()) {
				1625	case ARM::STRD:
				1626	case ARM::STRD_PRE:
				1627	case ARM::STRD_POST:
				1628	case ARM::LDRD:
				1629	case ARM::LDRD_PRE:
				1630	case ARM::LDRD_POST:
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1631	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1632	break;
				1633	default:
				1634	break;
				1635	}
				1636	switch (Inst.getOpcode()) {
				1637	case ARM::STRD:
				1638	case ARM::STRD_PRE:
				1639	case ARM::STRD_POST:
				1640	if (P == 0 && W == 1)
				1641	S = MCDisassembler::SoftFail;
				1642
				1643	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1644	S = MCDisassembler::SoftFail;
				1645	if (type && Rm == 15)
				1646	S = MCDisassembler::SoftFail;
				1647	if (Rt2 == 15)
				1648	S = MCDisassembler::SoftFail;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1649	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	6fe310e	2012-03-22 14:14:49 +0000	[diff] [blame]	1650	S = MCDisassembler::SoftFail;
				1651	break;
				1652	case ARM::STRH:
				1653	case ARM::STRH_PRE:
				1654	case ARM::STRH_POST:
				1655	if (Rt == 15)
				1656	S = MCDisassembler::SoftFail;
				1657	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1658	S = MCDisassembler::SoftFail;
				1659	if (!type && Rm == 15)
				1660	S = MCDisassembler::SoftFail;
				1661	break;
				1662	case ARM::LDRD:
				1663	case ARM::LDRD_PRE:
				1664	case ARM::LDRD_POST:
				1665	if (type && Rn == 15){
				1666	if (Rt2 == 15)
				1667	S = MCDisassembler::SoftFail;
				1668	break;
				1669	}
				1670	if (P == 0 && W == 1)
				1671	S = MCDisassembler::SoftFail;
				1672	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1673	S = MCDisassembler::SoftFail;
				1674	if (!type && writeback && Rn == 15)
				1675	S = MCDisassembler::SoftFail;
				1676	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1677	S = MCDisassembler::SoftFail;
				1678	break;
				1679	case ARM::LDRH:
				1680	case ARM::LDRH_PRE:
				1681	case ARM::LDRH_POST:
				1682	if (type && Rn == 15){
				1683	if (Rt == 15)
				1684	S = MCDisassembler::SoftFail;
				1685	break;
				1686	}
				1687	if (Rt == 15)
				1688	S = MCDisassembler::SoftFail;
				1689	if (!type && Rm == 15)
				1690	S = MCDisassembler::SoftFail;
				1691	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1692	S = MCDisassembler::SoftFail;
				1693	break;
				1694	case ARM::LDRSH:
				1695	case ARM::LDRSH_PRE:
				1696	case ARM::LDRSH_POST:
				1697	case ARM::LDRSB:
				1698	case ARM::LDRSB_PRE:
				1699	case ARM::LDRSB_POST:
				1700	if (type && Rn == 15){
				1701	if (Rt == 15)
				1702	S = MCDisassembler::SoftFail;
				1703	break;
				1704	}
				1705	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1706	S = MCDisassembler::SoftFail;
				1707	if (!type && (Rt == 15 \|\| Rm == 15))
				1708	S = MCDisassembler::SoftFail;
				1709	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1710	S = MCDisassembler::SoftFail;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1711	break;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1712	default:
				1713	break;
Owen Anderson	c537f3b	2011-08-15 20:51:32 +0000	[diff] [blame]	1714	}
				1715
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1716	if (writeback) { // Writeback
				1717	if (P)
				1718	U \|= ARMII::IndexModePre << 9;
				1719	else
				1720	U \|= ARMII::IndexModePost << 9;
				1721
				1722	// On stores, the writeback operand precedes Rt.
				1723	switch (Inst.getOpcode()) {
				1724	case ARM::STRD:
				1725	case ARM::STRD_PRE:
				1726	case ARM::STRD_POST:
Owen Anderson	79628e9	2011-08-12 20:02:50 +0000	[diff] [blame]	1727	case ARM::STRH:
				1728	case ARM::STRH_PRE:
				1729	case ARM::STRH_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1730	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1731	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1732	break;
				1733	default:
				1734	break;
				1735	}
				1736	}
				1737
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1738	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1739	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1740	switch (Inst.getOpcode()) {
				1741	case ARM::STRD:
				1742	case ARM::STRD_PRE:
				1743	case ARM::STRD_POST:
				1744	case ARM::LDRD:
				1745	case ARM::LDRD_PRE:
				1746	case ARM::LDRD_POST:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1747	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1748	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1749	break;
				1750	default:
				1751	break;
				1752	}
				1753
				1754	if (writeback) {
				1755	// On loads, the writeback operand comes after Rt.
				1756	switch (Inst.getOpcode()) {
				1757	case ARM::LDRD:
				1758	case ARM::LDRD_PRE:
				1759	case ARM::LDRD_POST:
Owen Anderson	0d09499	2011-08-12 20:36:11 +0000	[diff] [blame]	1760	case ARM::LDRH:
				1761	case ARM::LDRH_PRE:
				1762	case ARM::LDRH_POST:
				1763	case ARM::LDRSH:
				1764	case ARM::LDRSH_PRE:
				1765	case ARM::LDRSH_POST:
				1766	case ARM::LDRSB:
				1767	case ARM::LDRSB_PRE:
				1768	case ARM::LDRSB_POST:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1769	case ARM::LDRHTr:
				1770	case ARM::LDRSBTr:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1771	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1772	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1773	break;
				1774	default:
				1775	break;
				1776	}
				1777	}
				1778
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1779	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1780	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1781
				1782	if (type) {
				1783	Inst.addOperand(MCOperand::CreateReg(0));
				1784	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1785	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1786	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1787	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1788	Inst.addOperand(MCOperand::CreateImm(U));
				1789	}
				1790
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1791	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1792	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1793
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1794	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1795	}
				1796
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1797	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1798	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1799	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1800
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1801	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1802	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1803
				1804	switch (mode) {
				1805	case 0:
				1806	mode = ARM_AM::da;
				1807	break;
				1808	case 1:
				1809	mode = ARM_AM::ia;
				1810	break;
				1811	case 2:
				1812	mode = ARM_AM::db;
				1813	break;
				1814	case 3:
				1815	mode = ARM_AM::ib;
				1816	break;
				1817	}
				1818
				1819	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1820	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1821	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1822
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1823	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1824	}
				1825
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1826	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1827	unsigned Insn,
				1828	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1829	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1830
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1831	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1832	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1833	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1834
				1835	if (pred == 0xF) {
				1836	switch (Inst.getOpcode()) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1837	case ARM::LDMDA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1838	Inst.setOpcode(ARM::RFEDA);
				1839	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1840	case ARM::LDMDA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1841	Inst.setOpcode(ARM::RFEDA_UPD);
				1842	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1843	case ARM::LDMDB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1844	Inst.setOpcode(ARM::RFEDB);
				1845	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1846	case ARM::LDMDB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1847	Inst.setOpcode(ARM::RFEDB_UPD);
				1848	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1849	case ARM::LDMIA:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1850	Inst.setOpcode(ARM::RFEIA);
				1851	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1852	case ARM::LDMIA_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1853	Inst.setOpcode(ARM::RFEIA_UPD);
				1854	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1855	case ARM::LDMIB:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1856	Inst.setOpcode(ARM::RFEIB);
				1857	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1858	case ARM::LDMIB_UPD:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1859	Inst.setOpcode(ARM::RFEIB_UPD);
				1860	break;
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1861	case ARM::STMDA:
				1862	Inst.setOpcode(ARM::SRSDA);
				1863	break;
				1864	case ARM::STMDA_UPD:
				1865	Inst.setOpcode(ARM::SRSDA_UPD);
				1866	break;
				1867	case ARM::STMDB:
				1868	Inst.setOpcode(ARM::SRSDB);
				1869	break;
				1870	case ARM::STMDB_UPD:
				1871	Inst.setOpcode(ARM::SRSDB_UPD);
				1872	break;
				1873	case ARM::STMIA:
				1874	Inst.setOpcode(ARM::SRSIA);
				1875	break;
				1876	case ARM::STMIA_UPD:
				1877	Inst.setOpcode(ARM::SRSIA_UPD);
				1878	break;
				1879	case ARM::STMIB:
				1880	Inst.setOpcode(ARM::SRSIB);
				1881	break;
				1882	case ARM::STMIB_UPD:
				1883	Inst.setOpcode(ARM::SRSIB_UPD);
				1884	break;
				1885	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1886	if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1887	}
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1888
				1889	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1890	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1891	Inst.addOperand(
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1892	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	846dd95	2011-08-18 22:31:17 +0000	[diff] [blame]	1893	return S;
				1894	}
				1895
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1896	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1897	}
				1898
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1899	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1900	return MCDisassembler::Fail;
				1901	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1902	return MCDisassembler::Fail; // Tied
				1903	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1904	return MCDisassembler::Fail;
				1905	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1906	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1907
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	1908	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1909	}
				1910
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1911	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1912	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1913	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1914	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1915	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1916	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1917
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1918	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	35008c2	2011-08-09 23:05:39 +0000	[diff] [blame]	1919
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1920	// imod == '01' --> UNPREDICTABLE
				1921	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1922	// return failure here. The '01' imod value is unprintable, so there's
				1923	// nothing useful we could do even if we returned UNPREDICTABLE.
				1924
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1925	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1926
				1927	if (imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1928	Inst.setOpcode(ARM::CPS3p);
				1929	Inst.addOperand(MCOperand::CreateImm(imod));
				1930	Inst.addOperand(MCOperand::CreateImm(iflags));
				1931	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1932	} else if (imod && !M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1933	Inst.setOpcode(ARM::CPS2p);
				1934	Inst.addOperand(MCOperand::CreateImm(imod));
				1935	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1936	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1937	} else if (!imod && M) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1938	Inst.setOpcode(ARM::CPS1p);
				1939	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1940	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1941	} else {
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1942	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1943	Inst.setOpcode(ARM::CPS1p);
				1944	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1945	S = MCDisassembler::SoftFail;
Owen Anderson	1dd56f0	2011-08-18 22:15:25 +0000	[diff] [blame]	1946	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1947
Owen Anderson	14090bf	2011-08-18 22:11:02 +0000	[diff] [blame]	1948	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	1949	}
				1950
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1951	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1952	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1953	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1954	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1955	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1956	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1957
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	1958	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1959
				1960	// imod == '01' --> UNPREDICTABLE
				1961	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1962	// return failure here. The '01' imod value is unprintable, so there's
				1963	// nothing useful we could do even if we returned UNPREDICTABLE.
				1964
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1965	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1966
				1967	if (imod && M) {
				1968	Inst.setOpcode(ARM::t2CPS3p);
				1969	Inst.addOperand(MCOperand::CreateImm(imod));
				1970	Inst.addOperand(MCOperand::CreateImm(iflags));
				1971	Inst.addOperand(MCOperand::CreateImm(mode));
				1972	} else if (imod && !M) {
				1973	Inst.setOpcode(ARM::t2CPS2p);
				1974	Inst.addOperand(MCOperand::CreateImm(imod));
				1975	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1976	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1977	} else if (!imod && M) {
				1978	Inst.setOpcode(ARM::t2CPS1p);
				1979	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	1980	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1981	} else {
Quentin Colombet	1ad3a41	2013-04-26 17:54:54 +0000	[diff] [blame]	1982	// imod == '00' && M == '0' --> this is a HINT instruction
				1983	int imm = fieldFromInstruction(Insn, 0, 8);
				1984	// HINT are defined only for immediate in [0..4]
				1985	if(imm > 4) return MCDisassembler::Fail;
				1986	Inst.setOpcode(ARM::t2HINT);
				1987	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	1988	}
				1989
				1990	return S;
				1991	}
				1992
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	1993	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1994	uint64_t Address, const void *Decoder) {
				1995	DecodeStatus S = MCDisassembler::Success;
				1996
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	1997	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	1998	unsigned imm = 0;
				1999
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2000	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2001	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2002	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2003	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2004
				2005	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2006	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2007	return MCDisassembler::Fail;
				2008	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2009	return MCDisassembler::Fail;
				2010
				2011	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2012	Inst.addOperand(MCOperand::CreateImm(imm));
				2013
				2014	return S;
				2015	}
				2016
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2017	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2018	uint64_t Address, const void *Decoder) {
				2019	DecodeStatus S = MCDisassembler::Success;
				2020
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2021	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2022	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2023	unsigned imm = 0;
				2024
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2025	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2026	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2027
				2028	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	4521019	2013-04-19 09:58:09 +0000	[diff] [blame]	2029	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2030	return MCDisassembler::Fail;
Tim Northover	4521019	2013-04-19 09:58:09 +0000	[diff] [blame]	2031
				2032	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2033	return MCDisassembler::Fail;
				2034
				2035	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2036	Inst.addOperand(MCOperand::CreateImm(imm));
				2037
				2038	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2039	return MCDisassembler::Fail;
				2040
				2041	return S;
				2042	}
Owen Anderson	6153a03	2011-08-23 17:45:18 +0000	[diff] [blame]	2043
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2044	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2045	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2046	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2047
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2048	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2049	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2050	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2051	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2052	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2053
				2054	if (pred == 0xF)
				2055	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2056
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2057	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2058	return MCDisassembler::Fail;
				2059	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2060	return MCDisassembler::Fail;
				2061	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2062	return MCDisassembler::Fail;
				2063	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2064	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2065
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2066	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2067	return MCDisassembler::Fail;
Owen Anderson	1fb6673	2011-08-11 22:05:38 +0000	[diff] [blame]	2068
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2069	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2070	}
				2071
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2072	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2073	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2074	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2075
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2076	unsigned add = fieldFromInstruction(Val, 12, 1);
				2077	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2078	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2079
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2080	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2081	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2082
				2083	if (!add) imm *= -1;
				2084	if (imm == 0 && !add) imm = INT32_MIN;
				2085	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2086	if (Rn == 15)
				2087	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2088
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2089	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2090	}
				2091
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2092	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2093	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2094	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2095
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2096	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2097	unsigned U = fieldFromInstruction(Val, 8, 1);
				2098	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2099
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2100	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2101	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2102
				2103	if (U)
				2104	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2105	else
				2106	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2107
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2108	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2109	}
				2110
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2111	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2112	uint64_t Address, const void *Decoder) {
				2113	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2114	}
				2115
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2116	static DecodeStatus
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2117	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2118	uint64_t Address, const void *Decoder) {
Kevin Enderby	445ba85	2012-10-29 23:27:20 +0000	[diff] [blame]	2119	DecodeStatus Status = MCDisassembler::Success;
				2120
				2121	// Note the J1 and J2 values are from the encoded instruction. So here
				2122	// change them to I1 and I2 values via as documented:
				2123	// I1 = NOT(J1 EOR S);
				2124	// I2 = NOT(J2 EOR S);
				2125	// and build the imm32 with one trailing zero as documented:
				2126	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2127	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2128	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2129	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2130	unsigned I1 = !(J1 ^ S);
				2131	unsigned I2 = !(J2 ^ S);
				2132	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2133	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2134	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
				2135	int imm32 = SignExtend32<24>(tmp << 1);
				2136	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2137	true, 4, Inst, Decoder))
Kevin Enderby	445ba85	2012-10-29 23:27:20 +0000	[diff] [blame]	2138	Inst.addOperand(MCOperand::CreateImm(imm32));
				2139
				2140	return Status;
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	2141	}
				2142
				2143	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2144	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2145	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2146	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2147
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2148	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2149	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2150
				2151	if (pred == 0xF) {
				2152	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2153	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2154	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2155	true, 4, Inst, Decoder))
Benjamin Kramer	793b811	2011-08-09 22:02:50 +0000	[diff] [blame]	2156	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2157	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2158	}
				2159
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	2160	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2161	true, 4, Inst, Decoder))
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	2162	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2163	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2164	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2165
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2166	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2167	}
				2168
				2169
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2170	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2171	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2172	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2173
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2174	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2175	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2176
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2177	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2178	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2179	if (!align)
				2180	Inst.addOperand(MCOperand::CreateImm(0));
				2181	else
				2182	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2183
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2184	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2185	}
				2186
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2187	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2188	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2189	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2190
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2191	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2192	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2193	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2194	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2195	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2196	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2197
				2198	// First output register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2199	switch (Inst.getOpcode()) {
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2200	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2201	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2202	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2203	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2204	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2205	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2206	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2207	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2208	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2209	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2210	return MCDisassembler::Fail;
				2211	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2212	case ARM::VLD2b16:
				2213	case ARM::VLD2b32:
				2214	case ARM::VLD2b8:
				2215	case ARM::VLD2b16wb_fixed:
				2216	case ARM::VLD2b16wb_register:
				2217	case ARM::VLD2b32wb_fixed:
				2218	case ARM::VLD2b32wb_register:
				2219	case ARM::VLD2b8wb_fixed:
				2220	case ARM::VLD2b8wb_register:
				2221	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2222	return MCDisassembler::Fail;
				2223	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2224	default:
				2225	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2226	return MCDisassembler::Fail;
				2227	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2228
				2229	// Second output register
				2230	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2231	case ARM::VLD3d8:
				2232	case ARM::VLD3d16:
				2233	case ARM::VLD3d32:
				2234	case ARM::VLD3d8_UPD:
				2235	case ARM::VLD3d16_UPD:
				2236	case ARM::VLD3d32_UPD:
				2237	case ARM::VLD4d8:
				2238	case ARM::VLD4d16:
				2239	case ARM::VLD4d32:
				2240	case ARM::VLD4d8_UPD:
				2241	case ARM::VLD4d16_UPD:
				2242	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2243	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2244	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2245	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2246	case ARM::VLD3q8:
				2247	case ARM::VLD3q16:
				2248	case ARM::VLD3q32:
				2249	case ARM::VLD3q8_UPD:
				2250	case ARM::VLD3q16_UPD:
				2251	case ARM::VLD3q32_UPD:
				2252	case ARM::VLD4q8:
				2253	case ARM::VLD4q16:
				2254	case ARM::VLD4q32:
				2255	case ARM::VLD4q8_UPD:
				2256	case ARM::VLD4q16_UPD:
				2257	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2258	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2259	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2260	default:
				2261	break;
				2262	}
				2263
				2264	// Third output register
				2265	switch(Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2266	case ARM::VLD3d8:
				2267	case ARM::VLD3d16:
				2268	case ARM::VLD3d32:
				2269	case ARM::VLD3d8_UPD:
				2270	case ARM::VLD3d16_UPD:
				2271	case ARM::VLD3d32_UPD:
				2272	case ARM::VLD4d8:
				2273	case ARM::VLD4d16:
				2274	case ARM::VLD4d32:
				2275	case ARM::VLD4d8_UPD:
				2276	case ARM::VLD4d16_UPD:
				2277	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2278	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2279	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2280	break;
				2281	case ARM::VLD3q8:
				2282	case ARM::VLD3q16:
				2283	case ARM::VLD3q32:
				2284	case ARM::VLD3q8_UPD:
				2285	case ARM::VLD3q16_UPD:
				2286	case ARM::VLD3q32_UPD:
				2287	case ARM::VLD4q8:
				2288	case ARM::VLD4q16:
				2289	case ARM::VLD4q32:
				2290	case ARM::VLD4q8_UPD:
				2291	case ARM::VLD4q16_UPD:
				2292	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2293	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2294	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2295	break;
				2296	default:
				2297	break;
				2298	}
				2299
				2300	// Fourth output register
				2301	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2302	case ARM::VLD4d8:
				2303	case ARM::VLD4d16:
				2304	case ARM::VLD4d32:
				2305	case ARM::VLD4d8_UPD:
				2306	case ARM::VLD4d16_UPD:
				2307	case ARM::VLD4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2308	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2309	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2310	break;
				2311	case ARM::VLD4q8:
				2312	case ARM::VLD4q16:
				2313	case ARM::VLD4q32:
				2314	case ARM::VLD4q8_UPD:
				2315	case ARM::VLD4q16_UPD:
				2316	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2317	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2318	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2319	break;
				2320	default:
				2321	break;
				2322	}
				2323
				2324	// Writeback operand
				2325	switch (Inst.getOpcode()) {
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2326	case ARM::VLD1d8wb_fixed:
				2327	case ARM::VLD1d16wb_fixed:
				2328	case ARM::VLD1d32wb_fixed:
				2329	case ARM::VLD1d64wb_fixed:
				2330	case ARM::VLD1d8wb_register:
				2331	case ARM::VLD1d16wb_register:
				2332	case ARM::VLD1d32wb_register:
				2333	case ARM::VLD1d64wb_register:
				2334	case ARM::VLD1q8wb_fixed:
				2335	case ARM::VLD1q16wb_fixed:
				2336	case ARM::VLD1q32wb_fixed:
				2337	case ARM::VLD1q64wb_fixed:
				2338	case ARM::VLD1q8wb_register:
				2339	case ARM::VLD1q16wb_register:
				2340	case ARM::VLD1q32wb_register:
				2341	case ARM::VLD1q64wb_register:
Jim Grosbach	5921675	2011-10-24 23:26:05 +0000	[diff] [blame]	2342	case ARM::VLD1d8Twb_fixed:
				2343	case ARM::VLD1d8Twb_register:
				2344	case ARM::VLD1d16Twb_fixed:
				2345	case ARM::VLD1d16Twb_register:
				2346	case ARM::VLD1d32Twb_fixed:
				2347	case ARM::VLD1d32Twb_register:
				2348	case ARM::VLD1d64Twb_fixed:
				2349	case ARM::VLD1d64Twb_register:
Jim Grosbach	399cdca	2011-10-25 00:14:01 +0000	[diff] [blame]	2350	case ARM::VLD1d8Qwb_fixed:
				2351	case ARM::VLD1d8Qwb_register:
				2352	case ARM::VLD1d16Qwb_fixed:
				2353	case ARM::VLD1d16Qwb_register:
				2354	case ARM::VLD1d32Qwb_fixed:
				2355	case ARM::VLD1d32Qwb_register:
				2356	case ARM::VLD1d64Qwb_fixed:
				2357	case ARM::VLD1d64Qwb_register:
Jim Grosbach	a4e3c7f	2011-12-09 21:28:25 +0000	[diff] [blame]	2358	case ARM::VLD2d8wb_fixed:
				2359	case ARM::VLD2d16wb_fixed:
				2360	case ARM::VLD2d32wb_fixed:
				2361	case ARM::VLD2q8wb_fixed:
				2362	case ARM::VLD2q16wb_fixed:
				2363	case ARM::VLD2q32wb_fixed:
				2364	case ARM::VLD2d8wb_register:
				2365	case ARM::VLD2d16wb_register:
				2366	case ARM::VLD2d32wb_register:
				2367	case ARM::VLD2q8wb_register:
				2368	case ARM::VLD2q16wb_register:
				2369	case ARM::VLD2q32wb_register:
				2370	case ARM::VLD2b8wb_fixed:
				2371	case ARM::VLD2b16wb_fixed:
				2372	case ARM::VLD2b32wb_fixed:
				2373	case ARM::VLD2b8wb_register:
				2374	case ARM::VLD2b16wb_register:
				2375	case ARM::VLD2b32wb_register:
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2376	Inst.addOperand(MCOperand::CreateImm(0));
				2377	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2378	case ARM::VLD3d8_UPD:
				2379	case ARM::VLD3d16_UPD:
				2380	case ARM::VLD3d32_UPD:
				2381	case ARM::VLD3q8_UPD:
				2382	case ARM::VLD3q16_UPD:
				2383	case ARM::VLD3q32_UPD:
				2384	case ARM::VLD4d8_UPD:
				2385	case ARM::VLD4d16_UPD:
				2386	case ARM::VLD4d32_UPD:
				2387	case ARM::VLD4q8_UPD:
				2388	case ARM::VLD4q16_UPD:
				2389	case ARM::VLD4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2390	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2391	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2392	break;
				2393	default:
				2394	break;
				2395	}
				2396
				2397	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2398	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2399	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2400
				2401	// AddrMode6 Offset (register)
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2402	switch (Inst.getOpcode()) {
				2403	default:
				2404	// The below have been updated to have explicit am6offset split
				2405	// between fixed and register offset. For those instructions not
				2406	// yet updated, we need to add an additional reg0 operand for the
				2407	// fixed variant.
				2408	//
				2409	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2410	if (Rm == 0xd) {
				2411	Inst.addOperand(MCOperand::CreateReg(0));
				2412	break;
				2413	}
				2414	// Fall through to handle the register offset variant.
				2415	case ARM::VLD1d8wb_fixed:
				2416	case ARM::VLD1d16wb_fixed:
				2417	case ARM::VLD1d32wb_fixed:
				2418	case ARM::VLD1d64wb_fixed:
Owen Anderson	04b12a4	2011-10-27 22:53:10 +0000	[diff] [blame]	2419	case ARM::VLD1d8Twb_fixed:
				2420	case ARM::VLD1d16Twb_fixed:
				2421	case ARM::VLD1d32Twb_fixed:
				2422	case ARM::VLD1d64Twb_fixed:
Owen Anderson	fb6ab2b	2011-10-31 17:17:32 +0000	[diff] [blame]	2423	case ARM::VLD1d8Qwb_fixed:
				2424	case ARM::VLD1d16Qwb_fixed:
				2425	case ARM::VLD1d32Qwb_fixed:
				2426	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2427	case ARM::VLD1d8wb_register:
				2428	case ARM::VLD1d16wb_register:
				2429	case ARM::VLD1d32wb_register:
				2430	case ARM::VLD1d64wb_register:
				2431	case ARM::VLD1q8wb_fixed:
				2432	case ARM::VLD1q16wb_fixed:
				2433	case ARM::VLD1q32wb_fixed:
				2434	case ARM::VLD1q64wb_fixed:
				2435	case ARM::VLD1q8wb_register:
				2436	case ARM::VLD1q16wb_register:
				2437	case ARM::VLD1q32wb_register:
				2438	case ARM::VLD1q64wb_register:
				2439	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2440	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2441	// increment and we need to add the register operand to the instruction.
				2442	if (Rm != 0xD && Rm != 0xF &&
				2443	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2444	return MCDisassembler::Fail;
Jim Grosbach	10b90a9	2011-10-24 21:45:13 +0000	[diff] [blame]	2445	break;
Kevin Enderby	a69da35	2012-04-11 00:25:40 +0000	[diff] [blame]	2446	case ARM::VLD2d8wb_fixed:
				2447	case ARM::VLD2d16wb_fixed:
				2448	case ARM::VLD2d32wb_fixed:
				2449	case ARM::VLD2b8wb_fixed:
				2450	case ARM::VLD2b16wb_fixed:
				2451	case ARM::VLD2b32wb_fixed:
				2452	case ARM::VLD2q8wb_fixed:
				2453	case ARM::VLD2q16wb_fixed:
				2454	case ARM::VLD2q32wb_fixed:
				2455	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2456	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2457
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2458	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2459	}
				2460
Mihai Popa	30a7a7c	2013-05-20 14:57:05 +0000	[diff] [blame]	2461	static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
				2462	uint64_t Addr, const void* Decoder) {
				2463	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2464	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2465	if(type == 7 && (align & 2)) return MCDisassembler::Fail;
				2466	if(type == 10 && align == 3) return MCDisassembler::Fail;
				2467	if(type == 6 && (align & 2)) return MCDisassembler::Fail;
				2468
				2469	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2470	}
				2471
				2472	static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
				2473	uint64_t Addr, const void* Decoder) {
				2474	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2475	if(size == 3) return MCDisassembler::Fail;
				2476
				2477	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2478	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2479	if(type == 8 && align == 3) return MCDisassembler::Fail;
				2480	if(type == 9 && align == 3) return MCDisassembler::Fail;
				2481
				2482	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2483	}
				2484
				2485	static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
				2486	uint64_t Addr, const void* Decoder) {
				2487	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2488	if(size == 3) return MCDisassembler::Fail;
				2489
				2490	unsigned align = fieldFromInstruction(Insn, 4, 2);
				2491	if(align & 2) return MCDisassembler::Fail;
				2492
				2493	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2494	}
				2495
				2496	static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
				2497	uint64_t Addr, const void* Decoder) {
				2498	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2499	if(size == 3) return MCDisassembler::Fail;
				2500
				2501	return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
				2502	}
				2503
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2504	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2505	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2506	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2507
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2508	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2509	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2510	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2511	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2512	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2513	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2514
				2515	// Writeback Operand
				2516	switch (Inst.getOpcode()) {
Jim Grosbach	4334e03	2011-10-31 21:50:31 +0000	[diff] [blame]	2517	case ARM::VST1d8wb_fixed:
				2518	case ARM::VST1d16wb_fixed:
				2519	case ARM::VST1d32wb_fixed:
				2520	case ARM::VST1d64wb_fixed:
				2521	case ARM::VST1d8wb_register:
				2522	case ARM::VST1d16wb_register:
				2523	case ARM::VST1d32wb_register:
				2524	case ARM::VST1d64wb_register:
				2525	case ARM::VST1q8wb_fixed:
				2526	case ARM::VST1q16wb_fixed:
				2527	case ARM::VST1q32wb_fixed:
				2528	case ARM::VST1q64wb_fixed:
				2529	case ARM::VST1q8wb_register:
				2530	case ARM::VST1q16wb_register:
				2531	case ARM::VST1q32wb_register:
				2532	case ARM::VST1q64wb_register:
Jim Grosbach	d5ca201	2011-11-29 22:38:04 +0000	[diff] [blame]	2533	case ARM::VST1d8Twb_fixed:
				2534	case ARM::VST1d16Twb_fixed:
				2535	case ARM::VST1d32Twb_fixed:
				2536	case ARM::VST1d64Twb_fixed:
				2537	case ARM::VST1d8Twb_register:
				2538	case ARM::VST1d16Twb_register:
				2539	case ARM::VST1d32Twb_register:
				2540	case ARM::VST1d64Twb_register:
Jim Grosbach	4c7edb3	2011-11-29 22:58:48 +0000	[diff] [blame]	2541	case ARM::VST1d8Qwb_fixed:
				2542	case ARM::VST1d16Qwb_fixed:
				2543	case ARM::VST1d32Qwb_fixed:
				2544	case ARM::VST1d64Qwb_fixed:
				2545	case ARM::VST1d8Qwb_register:
				2546	case ARM::VST1d16Qwb_register:
				2547	case ARM::VST1d32Qwb_register:
				2548	case ARM::VST1d64Qwb_register:
Jim Grosbach	bb3a2e4	2011-12-14 21:32:11 +0000	[diff] [blame]	2549	case ARM::VST2d8wb_fixed:
				2550	case ARM::VST2d16wb_fixed:
				2551	case ARM::VST2d32wb_fixed:
				2552	case ARM::VST2d8wb_register:
				2553	case ARM::VST2d16wb_register:
				2554	case ARM::VST2d32wb_register:
				2555	case ARM::VST2q8wb_fixed:
				2556	case ARM::VST2q16wb_fixed:
				2557	case ARM::VST2q32wb_fixed:
				2558	case ARM::VST2q8wb_register:
				2559	case ARM::VST2q16wb_register:
				2560	case ARM::VST2q32wb_register:
				2561	case ARM::VST2b8wb_fixed:
				2562	case ARM::VST2b16wb_fixed:
				2563	case ARM::VST2b32wb_fixed:
				2564	case ARM::VST2b8wb_register:
				2565	case ARM::VST2b16wb_register:
				2566	case ARM::VST2b32wb_register:
Kevin Enderby	b318cc1	2012-04-11 22:40:17 +0000	[diff] [blame]	2567	if (Rm == 0xF)
				2568	return MCDisassembler::Fail;
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2569	Inst.addOperand(MCOperand::CreateImm(0));
				2570	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2571	case ARM::VST3d8_UPD:
				2572	case ARM::VST3d16_UPD:
				2573	case ARM::VST3d32_UPD:
				2574	case ARM::VST3q8_UPD:
				2575	case ARM::VST3q16_UPD:
				2576	case ARM::VST3q32_UPD:
				2577	case ARM::VST4d8_UPD:
				2578	case ARM::VST4d16_UPD:
				2579	case ARM::VST4d32_UPD:
				2580	case ARM::VST4q8_UPD:
				2581	case ARM::VST4q16_UPD:
				2582	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2583	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2584	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2585	break;
				2586	default:
				2587	break;
				2588	}
				2589
				2590	// AddrMode6 Base (register+alignment)
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2591	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2592	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2593
				2594	// AddrMode6 Offset (register)
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2595	switch (Inst.getOpcode()) {
				2596	default:
				2597	if (Rm == 0xD)
				2598	Inst.addOperand(MCOperand::CreateReg(0));
				2599	else if (Rm != 0xF) {
				2600	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2601	return MCDisassembler::Fail;
				2602	}
				2603	break;
				2604	case ARM::VST1d8wb_fixed:
				2605	case ARM::VST1d16wb_fixed:
				2606	case ARM::VST1d32wb_fixed:
				2607	case ARM::VST1d64wb_fixed:
				2608	case ARM::VST1q8wb_fixed:
				2609	case ARM::VST1q16wb_fixed:
				2610	case ARM::VST1q32wb_fixed:
				2611	case ARM::VST1q64wb_fixed:
Kevin Enderby	f0586f0	2012-03-21 20:54:32 +0000	[diff] [blame]	2612	case ARM::VST1d8Twb_fixed:
				2613	case ARM::VST1d16Twb_fixed:
				2614	case ARM::VST1d32Twb_fixed:
				2615	case ARM::VST1d64Twb_fixed:
				2616	case ARM::VST1d8Qwb_fixed:
				2617	case ARM::VST1d16Qwb_fixed:
				2618	case ARM::VST1d32Qwb_fixed:
				2619	case ARM::VST1d64Qwb_fixed:
				2620	case ARM::VST2d8wb_fixed:
				2621	case ARM::VST2d16wb_fixed:
				2622	case ARM::VST2d32wb_fixed:
				2623	case ARM::VST2q8wb_fixed:
				2624	case ARM::VST2q16wb_fixed:
				2625	case ARM::VST2q32wb_fixed:
				2626	case ARM::VST2b8wb_fixed:
				2627	case ARM::VST2b16wb_fixed:
				2628	case ARM::VST2b32wb_fixed:
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2629	break;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2630	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2631
Owen Anderson	60cb643	2011-11-01 22:18:13 +0000	[diff] [blame]	2632
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2633	// First input register
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2634	switch (Inst.getOpcode()) {
				2635	case ARM::VST1q16:
				2636	case ARM::VST1q32:
				2637	case ARM::VST1q64:
				2638	case ARM::VST1q8:
				2639	case ARM::VST1q16wb_fixed:
				2640	case ARM::VST1q16wb_register:
				2641	case ARM::VST1q32wb_fixed:
				2642	case ARM::VST1q32wb_register:
				2643	case ARM::VST1q64wb_fixed:
				2644	case ARM::VST1q64wb_register:
				2645	case ARM::VST1q8wb_fixed:
				2646	case ARM::VST1q8wb_register:
				2647	case ARM::VST2d16:
				2648	case ARM::VST2d32:
				2649	case ARM::VST2d8:
				2650	case ARM::VST2d16wb_fixed:
				2651	case ARM::VST2d16wb_register:
				2652	case ARM::VST2d32wb_fixed:
				2653	case ARM::VST2d32wb_register:
				2654	case ARM::VST2d8wb_fixed:
				2655	case ARM::VST2d8wb_register:
				2656	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2657	return MCDisassembler::Fail;
				2658	break;
Jim Grosbach	c3384c9	2012-03-05 21:43:40 +0000	[diff] [blame]	2659	case ARM::VST2b16:
				2660	case ARM::VST2b32:
				2661	case ARM::VST2b8:
				2662	case ARM::VST2b16wb_fixed:
				2663	case ARM::VST2b16wb_register:
				2664	case ARM::VST2b32wb_fixed:
				2665	case ARM::VST2b32wb_register:
				2666	case ARM::VST2b8wb_fixed:
				2667	case ARM::VST2b8wb_register:
				2668	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2669	return MCDisassembler::Fail;
				2670	break;
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	2671	default:
				2672	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2673	return MCDisassembler::Fail;
				2674	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2675
				2676	// Second input register
				2677	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2678	case ARM::VST3d8:
				2679	case ARM::VST3d16:
				2680	case ARM::VST3d32:
				2681	case ARM::VST3d8_UPD:
				2682	case ARM::VST3d16_UPD:
				2683	case ARM::VST3d32_UPD:
				2684	case ARM::VST4d8:
				2685	case ARM::VST4d16:
				2686	case ARM::VST4d32:
				2687	case ARM::VST4d8_UPD:
				2688	case ARM::VST4d16_UPD:
				2689	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2690	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2691	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2692	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2693	case ARM::VST3q8:
				2694	case ARM::VST3q16:
				2695	case ARM::VST3q32:
				2696	case ARM::VST3q8_UPD:
				2697	case ARM::VST3q16_UPD:
				2698	case ARM::VST3q32_UPD:
				2699	case ARM::VST4q8:
				2700	case ARM::VST4q16:
				2701	case ARM::VST4q32:
				2702	case ARM::VST4q8_UPD:
				2703	case ARM::VST4q16_UPD:
				2704	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2705	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2706	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2707	break;
				2708	default:
				2709	break;
				2710	}
				2711
				2712	// Third input register
				2713	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2714	case ARM::VST3d8:
				2715	case ARM::VST3d16:
				2716	case ARM::VST3d32:
				2717	case ARM::VST3d8_UPD:
				2718	case ARM::VST3d16_UPD:
				2719	case ARM::VST3d32_UPD:
				2720	case ARM::VST4d8:
				2721	case ARM::VST4d16:
				2722	case ARM::VST4d32:
				2723	case ARM::VST4d8_UPD:
				2724	case ARM::VST4d16_UPD:
				2725	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2726	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2727	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2728	break;
				2729	case ARM::VST3q8:
				2730	case ARM::VST3q16:
				2731	case ARM::VST3q32:
				2732	case ARM::VST3q8_UPD:
				2733	case ARM::VST3q16_UPD:
				2734	case ARM::VST3q32_UPD:
				2735	case ARM::VST4q8:
				2736	case ARM::VST4q16:
				2737	case ARM::VST4q32:
				2738	case ARM::VST4q8_UPD:
				2739	case ARM::VST4q16_UPD:
				2740	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2741	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2742	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2743	break;
				2744	default:
				2745	break;
				2746	}
				2747
				2748	// Fourth input register
				2749	switch (Inst.getOpcode()) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2750	case ARM::VST4d8:
				2751	case ARM::VST4d16:
				2752	case ARM::VST4d32:
				2753	case ARM::VST4d8_UPD:
				2754	case ARM::VST4d16_UPD:
				2755	case ARM::VST4d32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2756	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2757	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2758	break;
				2759	case ARM::VST4q8:
				2760	case ARM::VST4q16:
				2761	case ARM::VST4q32:
				2762	case ARM::VST4q8_UPD:
				2763	case ARM::VST4q16_UPD:
				2764	case ARM::VST4q32_UPD:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2765	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2766	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2767	break;
				2768	default:
				2769	break;
				2770	}
				2771
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2772	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2773	}
				2774
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2775	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2776	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2777	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2778
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2779	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2780	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2781	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2782	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2783	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2784	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2785
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2786	if (size == 0 && align == 1)
				2787	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2788	align *= (1 << size);
				2789
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2790	switch (Inst.getOpcode()) {
				2791	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2792	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2793	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2794	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2795	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2796	return MCDisassembler::Fail;
				2797	break;
				2798	default:
				2799	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2800	return MCDisassembler::Fail;
				2801	break;
				2802	}
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2803	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2804	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2805	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2806	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2807
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2808	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2809	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2810	Inst.addOperand(MCOperand::CreateImm(align));
				2811
Jim Grosbach	096334e	2011-11-30 19:35:44 +0000	[diff] [blame]	2812	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2813	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2814	// increment and we need to add the register operand to the instruction.
				2815	if (Rm != 0xD && Rm != 0xF &&
				2816	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2817	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2818
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2819	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2820	}
				2821
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2822	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2823	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2824	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2825
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2826	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2827	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2828	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2829	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2830	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2831	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2832	align = 2size;
				2833
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2834	switch (Inst.getOpcode()) {
				2835	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2836	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2837	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2838	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2839	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2840	return MCDisassembler::Fail;
				2841	break;
Jim Grosbach	4d0983a	2012-03-06 23:10:38 +0000	[diff] [blame]	2842	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2843	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2844	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2845	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2846	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2847	return MCDisassembler::Fail;
				2848	break;
Jim Grosbach	c0fc450	2012-03-06 22:01:44 +0000	[diff] [blame]	2849	default:
				2850	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2851	return MCDisassembler::Fail;
				2852	break;
				2853	}
Kevin Enderby	158c8a4	2012-03-06 18:33:12 +0000	[diff] [blame]	2854
				2855	if (Rm != 0xF)
				2856	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2857
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2858	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2859	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2860	Inst.addOperand(MCOperand::CreateImm(align));
				2861
Kevin Enderby	c5a2a33	2012-04-17 00:49:27 +0000	[diff] [blame]	2862	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2863	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2864	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2865	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2866
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2867	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2868	}
				2869
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2870	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2871	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2872	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2873
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2874	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2875	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2876	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2877	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2878	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2879
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2880	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2881	return MCDisassembler::Fail;
				2882	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2883	return MCDisassembler::Fail;
				2884	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2885	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2886	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2887	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2888	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2889	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2890
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2891	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2892	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2893	Inst.addOperand(MCOperand::CreateImm(0));
				2894
				2895	if (Rm == 0xD)
				2896	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2897	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2898	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2899	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2900	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2901
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2902	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2903	}
				2904
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2905	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2906	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2907	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2908
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2909	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2910	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2911	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2912	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2913	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2914	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2915	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2916
				2917	if (size == 0x3) {
Tim Northover	24b9f25	2012-09-06 15:27:12 +0000	[diff] [blame]	2918	if (align == 0)
				2919	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2920	size = 4;
				2921	align = 16;
				2922	} else {
				2923	if (size == 2) {
				2924	size = 1 << size;
				2925	align *= 8;
				2926	} else {
				2927	size = 1 << size;
				2928	align = 4size;
				2929	}
				2930	}
				2931
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2932	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2933	return MCDisassembler::Fail;
				2934	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2935	return MCDisassembler::Fail;
				2936	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2937	return MCDisassembler::Fail;
				2938	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2939	return MCDisassembler::Fail;
Owen Anderson	f1c8e3e	2011-08-22 18:22:06 +0000	[diff] [blame]	2940	if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2941	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2942	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2943	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2944
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2945	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2946	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2947	Inst.addOperand(MCOperand::CreateImm(align));
				2948
				2949	if (Rm == 0xD)
				2950	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2951	else if (Rm != 0xF) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2952	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2953	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2954	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2955
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2956	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2957	}
				2958
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2959	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	2960	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	2961	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2962	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	2963
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	2964	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2965	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2966	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2967	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2968	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2969	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2970	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2971	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2972
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2973	if (Q) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2974	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2975	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2976	} else {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2977	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2978	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	2979	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2980
				2981	Inst.addOperand(MCOperand::CreateImm(imm));
				2982
				2983	switch (Inst.getOpcode()) {
				2984	case ARM::VORRiv4i16:
				2985	case ARM::VORRiv2i32:
				2986	case ARM::VBICiv4i16:
				2987	case ARM::VBICiv2i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2988	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2989	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2990	break;
				2991	case ARM::VORRiv8i16:
				2992	case ARM::VORRiv4i32:
				2993	case ARM::VBICiv8i16:
				2994	case ARM::VBICiv4i32:
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	2995	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				2996	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	2997	break;
				2998	default:
				2999	break;
				3000	}
				3001
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3002	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3003	}
				3004
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3005	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3006	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3007	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3008
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3009	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3010	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3011	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3012	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3013	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3014
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3015	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3016	return MCDisassembler::Fail;
				3017	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3018	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3019	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3020
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3021	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3022	}
				3023
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3024	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3025	uint64_t Address, const void *Decoder) {
				3026	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3027	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3028	}
				3029
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3030	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3031	uint64_t Address, const void *Decoder) {
				3032	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3033	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3034	}
				3035
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3036	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3037	uint64_t Address, const void *Decoder) {
				3038	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3039	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3040	}
				3041
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3042	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3043	uint64_t Address, const void *Decoder) {
				3044	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3045	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3046	}
				3047
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3048	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3049	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3050	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3051
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3052	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3053	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3054	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3055	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3056	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3057	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3058	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3059
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3060	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3061	return MCDisassembler::Fail;
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	3062	if (op) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3063	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3064	return MCDisassembler::Fail; // Writeback
Owen Anderson	ae0bc5d	2011-08-11 18:24:51 +0000	[diff] [blame]	3065	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3066
Jim Grosbach	28f08c9	2012-03-05 19:33:30 +0000	[diff] [blame]	3067	switch (Inst.getOpcode()) {
				3068	case ARM::VTBL2:
				3069	case ARM::VTBX2:
				3070	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3071	return MCDisassembler::Fail;
				3072	break;
				3073	default:
				3074	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3075	return MCDisassembler::Fail;
				3076	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3077
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3078	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3079	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3080
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3081	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3082	}
				3083
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3084	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3085	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3086	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3087
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3088	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3089	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3090
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3091	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3092	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3093
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3094	switch(Inst.getOpcode()) {
Owen Anderson	1af7f72	2011-08-26 19:39:26 +0000	[diff] [blame]	3095	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3096	return MCDisassembler::Fail;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3097	case ARM::tADR:
Owen Anderson	9f7e831	2011-08-26 21:47:57 +0000	[diff] [blame]	3098	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3099	case ARM::tADDrSPi:
				3100	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3101	break;
Owen Anderson	96425c8	2011-08-26 18:09:22 +0000	[diff] [blame]	3102	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3103
				3104	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3105	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3106	}
				3107
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3108	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3109	uint64_t Address, const void *Decoder) {
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3110	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3111	true, 2, Inst, Decoder))
				3112	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3113	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3114	}
				3115
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3116	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3117	uint64_t Address, const void *Decoder) {
Kevin Enderby	3610a15	2012-05-04 22:09:52 +0000	[diff] [blame]	3118	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3119	true, 4, Inst, Decoder))
				3120	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3121	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3122	}
				3123
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3124	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3125	uint64_t Address, const void *Decoder) {
Gordon Keiser	ce88835	2013-03-28 19:22:28 +0000	[diff] [blame]	3126	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3127	true, 2, Inst, Decoder))
Gordon Keiser	ce88835	2013-03-28 19:22:28 +0000	[diff] [blame]	3128	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3129	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3130	}
				3131
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3132	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3134	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3135
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3136	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3137	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3138
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3139	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3140	return MCDisassembler::Fail;
				3141	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3142	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3143
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3144	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3145	}
				3146
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3147	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3148	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3149	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3150
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3151	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3152	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3153
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3154	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3155	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3156	Inst.addOperand(MCOperand::CreateImm(imm));
				3157
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3158	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3159	}
				3160
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3161	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3162	uint64_t Address, const void *Decoder) {
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3163	unsigned imm = Val << 2;
				3164
				3165	Inst.addOperand(MCOperand::CreateImm(imm));
				3166	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3167
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3168	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3169	}
				3170
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3171	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	uint64_t Address, const void *Decoder) {
				3173	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b113ec5	2011-08-22 17:56:58 +0000	[diff] [blame]	3174	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3175
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3176	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3177	}
				3178
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3179	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3180	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3181	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3182
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3183	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3184	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3185	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3186
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3187	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3188	return MCDisassembler::Fail;
				3189	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3190	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3191	Inst.addOperand(MCOperand::CreateImm(imm));
				3192
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3193	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3194	}
				3195
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3196	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3197	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3198	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3199
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3200	switch (Inst.getOpcode()) {
				3201	case ARM::t2PLDs:
				3202	case ARM::t2PLDWs:
				3203	case ARM::t2PLIs:
				3204	break;
				3205	default: {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3206	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson	31d485e	2011-09-23 21:07:25 +0000	[diff] [blame]	3207	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3208	return MCDisassembler::Fail;
Owen Anderson	82265a2	2011-08-23 17:51:38 +0000	[diff] [blame]	3209	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3210	}
				3211
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3212	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3213	if (Rn == 0xF) {
				3214	switch (Inst.getOpcode()) {
				3215	case ARM::t2LDRBs:
				3216	Inst.setOpcode(ARM::t2LDRBpci);
				3217	break;
				3218	case ARM::t2LDRHs:
				3219	Inst.setOpcode(ARM::t2LDRHpci);
				3220	break;
				3221	case ARM::t2LDRSHs:
				3222	Inst.setOpcode(ARM::t2LDRSHpci);
				3223	break;
				3224	case ARM::t2LDRSBs:
				3225	Inst.setOpcode(ARM::t2LDRSBpci);
				3226	break;
				3227	case ARM::t2PLDs:
				3228	Inst.setOpcode(ARM::t2PLDi12);
				3229	Inst.addOperand(MCOperand::CreateReg(ARM::PC));
				3230	break;
				3231	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3232	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3233	}
				3234
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3235	int imm = fieldFromInstruction(Insn, 0, 12);
				3236	if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3237	Inst.addOperand(MCOperand::CreateImm(imm));
				3238
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3239	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3240	}
				3241
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3242	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3243	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3244	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3245	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3246	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3247
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3248	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3249	}
				3250
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3251	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3252	uint64_t Address, const void *Decoder) {
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3253	if (Val == 0)
				3254	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3255	else {
				3256	int imm = Val & 0xFF;
				3257
				3258	if (!(Val & 0x100)) imm *= -1;
Richard Smith	1144af3	2012-08-24 23:29:28 +0000	[diff] [blame]	3259	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	fd652df	2012-08-02 08:29:50 +0000	[diff] [blame]	3260	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3261
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3262	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3263	}
				3264
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3265	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3266	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3267	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3268
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3269	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3270	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3271
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3272	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3273	return MCDisassembler::Fail;
				3274	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3275	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3276
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3277	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3278	}
				3279
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3280	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3281	uint64_t Address, const void *Decoder) {
				3282	DecodeStatus S = MCDisassembler::Success;
				3283
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3284	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3285	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	b6aed50	2011-09-09 18:37:27 +0000	[diff] [blame]	3286
				3287	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3288	return MCDisassembler::Fail;
				3289
				3290	Inst.addOperand(MCOperand::CreateImm(imm));
				3291
				3292	return S;
				3293	}
				3294
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3295	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3296	uint64_t Address, const void *Decoder) {
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3297	int imm = Val & 0xFF;
Owen Anderson	705b48f	2011-09-16 21:08:33 +0000	[diff] [blame]	3298	if (Val == 0)
				3299	imm = INT32_MIN;
				3300	else if (!(Val & 0x100))
				3301	imm *= -1;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3302	Inst.addOperand(MCOperand::CreateImm(imm));
				3303
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3304	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3305	}
				3306
				3307
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3308	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3309	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3310	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3311
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3312	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3313	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3314
				3315	// Some instructions always use an additive offset.
				3316	switch (Inst.getOpcode()) {
				3317	case ARM::t2LDRT:
				3318	case ARM::t2LDRBT:
				3319	case ARM::t2LDRHT:
				3320	case ARM::t2LDRSBT:
				3321	case ARM::t2LDRSHT:
Owen Anderson	ecd1c55	2011-09-19 18:07:10 +0000	[diff] [blame]	3322	case ARM::t2STRT:
				3323	case ARM::t2STRBT:
				3324	case ARM::t2STRHT:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3325	imm \|= 0x100;
				3326	break;
				3327	default:
				3328	break;
				3329	}
				3330
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3331	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3332	return MCDisassembler::Fail;
				3333	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3334	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3335
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3336	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3337	}
				3338
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3339	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3340	uint64_t Address, const void *Decoder) {
				3341	DecodeStatus S = MCDisassembler::Success;
				3342
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3343	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3344	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3345	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3346	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3347	addr \|= Rn << 9;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3348	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3349
				3350	if (!load) {
				3351	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3352	return MCDisassembler::Fail;
				3353	}
				3354
Joe Abbey	b78821d	2013-03-26 13:58:53 +0000	[diff] [blame]	3355	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a3157b4	2011-09-12 18:56:30 +0000	[diff] [blame]	3356	return MCDisassembler::Fail;
				3357
				3358	if (load) {
				3359	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3360	return MCDisassembler::Fail;
				3361	}
				3362
				3363	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3364	return MCDisassembler::Fail;
				3365
				3366	return S;
				3367	}
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3368
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3369	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3370	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3371	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3372
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3373	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3374	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3375
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3376	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3377	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3378	Inst.addOperand(MCOperand::CreateImm(imm));
				3379
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3380	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3381	}
				3382
				3383
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3384	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3385	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3386	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3387
				3388	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3389	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3390	Inst.addOperand(MCOperand::CreateImm(imm));
				3391
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3392	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3393	}
				3394
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3395	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3396	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3397	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3398
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3399	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3400	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3401	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3402
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3403	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3404	return MCDisassembler::Fail;
Jim Grosbach	bb32f1d	2012-04-27 23:51:33 +0000	[diff] [blame]	3405	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3406	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3407	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3408	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3409	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3410
				3411	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3412	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3413	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3414	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3415	}
				3416
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3417	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3418	}
				3419
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3420	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3421	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3422	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3423	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3424
				3425	Inst.addOperand(MCOperand::CreateImm(imod));
				3426	Inst.addOperand(MCOperand::CreateImm(flags));
				3427
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3428	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3429	}
				3430
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3431	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3432	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3433	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3434	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3435	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3436
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	3437	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3438	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3439	Inst.addOperand(MCOperand::CreateImm(add));
				3440
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3441	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3442	}
				3443
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3444	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3445	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3446	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3447	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3448	// the encoded instruction. So here change to I1 and I2 values via:
				3449	// I1 = NOT(J1 EOR S);
				3450	// I2 = NOT(J2 EOR S);
				3451	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3452	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3453	unsigned S = (Val >> 23) & 1;
				3454	unsigned J1 = (Val >> 22) & 1;
				3455	unsigned J2 = (Val >> 21) & 1;
				3456	unsigned I1 = !(J1 ^ S);
				3457	unsigned I2 = !(J2 ^ S);
				3458	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3459	int imm32 = SignExtend32<25>(tmp << 1);
				3460
Jim Grosbach	01817c3	2011-10-20 17:28:20 +0000	[diff] [blame]	3461	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3462	(Address & ~2u) + imm32 + 4,
Kevin Enderby	9e5887b	2011-10-04 22:44:48 +0000	[diff] [blame]	3463	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3464	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3465	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3466	}
				3467
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3468	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3469	uint64_t Address, const void *Decoder) {
				3470	if (Val == 0xA \|\| Val == 0xB)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3471	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3472
				3473	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3474	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3475	}
				3476
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3477	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3478	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3479	uint64_t Address, const void *Decoder) {
				3480	DecodeStatus S = MCDisassembler::Success;
				3481
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3482	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3483	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	7f739be	2011-09-19 22:21:13 +0000	[diff] [blame]	3484
				3485	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3486	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3487	return MCDisassembler::Fail;
				3488	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3489	return MCDisassembler::Fail;
				3490	return S;
				3491	}
				3492
				3493	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3494	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3495	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3496	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3497
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3498	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3499	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3500	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3501	switch (opc) {
				3502	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3503	return MCDisassembler::Fail;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3504	case 0xf3bf8f4:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3505	Inst.setOpcode(ARM::t2DSB);
				3506	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3507	case 0xf3bf8f5:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3508	Inst.setOpcode(ARM::t2DMB);
				3509	break;
Owen Anderson	b45b11b	2011-08-31 22:00:41 +0000	[diff] [blame]	3510	case 0xf3bf8f6:
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3511	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	6de3c6f	2011-09-07 17:55:19 +0000	[diff] [blame]	3512	break;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3513	}
				3514
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3515	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3516	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3517	}
				3518
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3519	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3520	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3521	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3522	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3523	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3524
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3525	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3526	return MCDisassembler::Fail;
				3527	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3528	return MCDisassembler::Fail;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3529
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3530	return S;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3531	}
				3532
				3533	// Decode a shifted immediate operand. These basically consist
				3534	// of an 8-bit value, and a 4-bit directive that specifies either
				3535	// a splat operation or a rotation.
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3536	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3537	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3538	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3539	if (ctrl == 0) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3540	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3541	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3542	switch (byte) {
				3543	case 0:
				3544	Inst.addOperand(MCOperand::CreateImm(imm));
				3545	break;
				3546	case 1:
				3547	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3548	break;
				3549	case 2:
				3550	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3551	break;
				3552	case 3:
				3553	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3554	(imm << 8) \| imm));
				3555	break;
				3556	}
				3557	} else {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3558	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3559	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3560	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3561	Inst.addOperand(MCOperand::CreateImm(imm));
				3562	}
				3563
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3564	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3565	}
				3566
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3567	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3568	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3569	uint64_t Address, const void *Decoder){
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3570	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	2a7d3a9	2012-04-12 23:13:34 +0000	[diff] [blame]	3571	true, 2, Inst, Decoder))
Richard Barton	c8f2fcc	2012-06-06 09:12:53 +0000	[diff] [blame]	3572	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3573	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3574	}
				3575
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3576	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	10cbaab	2011-08-10 17:36:48 +0000	[diff] [blame]	3577	uint64_t Address, const void *Decoder){
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3578	// Val is passed in as S:J1:J2:imm10:imm11
				3579	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3580	// the encoded instruction. So here change to I1 and I2 values via:
				3581	// I1 = NOT(J1 EOR S);
				3582	// I2 = NOT(J2 EOR S);
				3583	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	dd051a0	2012-05-22 21:47:02 +0000	[diff] [blame]	3584	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3585	unsigned S = (Val >> 23) & 1;
				3586	unsigned J1 = (Val >> 22) & 1;
				3587	unsigned J2 = (Val >> 21) & 1;
				3588	unsigned I1 = !(J1 ^ S);
				3589	unsigned I2 = !(J2 ^ S);
				3590	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3591	int imm32 = SignExtend32<25>(tmp << 1);
				3592
				3593	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	b80d571	2012-02-23 18:18:17 +0000	[diff] [blame]	3594	true, 4, Inst, Decoder))
Kevin Enderby	2d524b0	2012-05-03 22:41:56 +0000	[diff] [blame]	3595	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3596	return MCDisassembler::Success;
Owen Anderson	8d7d2e1	2011-08-09 20:55:18 +0000	[diff] [blame]	3597	}
				3598
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3599	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3600	uint64_t Address, const void *Decoder) {
Jiangning Liu	c1b7ca5	2012-08-02 08:21:27 +0000	[diff] [blame]	3601	if (Val & ~0xf)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3602	return MCDisassembler::Fail;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3603
				3604	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3605	return MCDisassembler::Success;
Owen Anderson	c36481c	2011-08-09 23:25:42 +0000	[diff] [blame]	3606	}
				3607
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3608	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3609	uint64_t Address, const void *Decoder) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3610	if (!Val) return MCDisassembler::Fail;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3611	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3612	return MCDisassembler::Success;
Owen Anderson	26d2f0a	2011-08-11 20:21:46 +0000	[diff] [blame]	3613	}
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3614
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3615	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3616	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3617	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3618
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3619	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3620	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3621	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3622
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3623	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3624
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3625	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3626	return MCDisassembler::Fail;
				3627	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3628	return MCDisassembler::Fail;
				3629	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3630	return MCDisassembler::Fail;
				3631	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3632	return MCDisassembler::Fail;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3633
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3634	return S;
Owen Anderson	3f3570a	2011-08-12 17:58:32 +0000	[diff] [blame]	3635	}
				3636
				3637
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3638	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	c405782	2011-08-17 21:58:18 +0000	[diff] [blame]	3639	uint64_t Address, const void *Decoder){
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3640	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3641
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3642	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3643	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3644	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3645	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3646
Tim Northover	d3af696	2013-04-19 15:44:32 +0000	[diff] [blame]	3647	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3648	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3649
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3650	if ((Rt & 1) \|\| Rt == 0xE \|\| Rn == 0xF) return MCDisassembler::Fail;
				3651	if (Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1) return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3652
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3653	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3654	return MCDisassembler::Fail;
				3655	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				3656	return MCDisassembler::Fail;
				3657	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3658	return MCDisassembler::Fail;
				3659	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3660	return MCDisassembler::Fail;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3661
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3662	return S;
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3663	}
				3664
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3665	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3666	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3667	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3668
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3669	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3670	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3671	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3672	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3673	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3674	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3675
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3676	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3677
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3678	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3679	return MCDisassembler::Fail;
				3680	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3681	return MCDisassembler::Fail;
				3682	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3683	return MCDisassembler::Fail;
				3684	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3685	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3686
				3687	return S;
				3688	}
				3689
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3690	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3691	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3692	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3693
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3694	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3695	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3696	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3697	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3698	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3699	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				3700	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3701
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3702	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				3703	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3704
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3705	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3706	return MCDisassembler::Fail;
				3707	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3708	return MCDisassembler::Fail;
				3709	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3710	return MCDisassembler::Fail;
				3711	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3712	return MCDisassembler::Fail;
Owen Anderson	9ab0f25	2011-08-26 20:43:14 +0000	[diff] [blame]	3713
				3714	return S;
				3715	}
				3716
				3717
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3718	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3719	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3720	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3721
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3722	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3723	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3724	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3725	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3726	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3727	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cbfc044	2011-08-11 21:34:58 +0000	[diff] [blame]	3728
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3729	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3730
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3731	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3732	return MCDisassembler::Fail;
				3733	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3734	return MCDisassembler::Fail;
				3735	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				3736	return MCDisassembler::Fail;
				3737	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3738	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3739
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3740	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3741	}
				3742
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3743	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3744	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3745	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3746
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3747	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3748	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3749	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3750	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				3751	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				3752	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3753
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3754	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3755
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3756	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3757	return MCDisassembler::Fail;
				3758	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3759	return MCDisassembler::Fail;
				3760	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				3761	return MCDisassembler::Fail;
				3762	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3763	return MCDisassembler::Fail;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3764
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3765	return S;
Owen Anderson	7cdbf08	2011-08-12 18:12:39 +0000	[diff] [blame]	3766	}
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3767
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3768	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3769	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3770	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3771
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3772	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3773	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3774	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3775	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3776	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3777
				3778	unsigned align = 0;
				3779	unsigned index = 0;
				3780	switch (size) {
				3781	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3782	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3783	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3784	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3785	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3786	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3787	break;
				3788	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3789	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3790	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3791	index = fieldFromInstruction(Insn, 6, 2);
				3792	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3793	align = 2;
				3794	break;
				3795	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3796	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3797	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3798	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3799
				3800	switch (fieldFromInstruction(Insn, 4, 2)) {
				3801	case 0 :
				3802	align = 0; break;
				3803	case 3:
				3804	align = 4; break;
				3805	default:
				3806	return MCDisassembler::Fail;
				3807	}
				3808	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3809	}
				3810
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3811	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3812	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3813	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3814	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3815	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3816	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3817	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3818	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3819	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3820	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3821	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3822	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3823	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3824	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3825	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3826	}
				3827
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3828	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3829	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3830	Inst.addOperand(MCOperand::CreateImm(index));
				3831
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3832	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3833	}
				3834
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3835	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3836	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3837	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3838
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3839	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3840	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3841	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3842	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3843	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3844
				3845	unsigned align = 0;
				3846	unsigned index = 0;
				3847	switch (size) {
				3848	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3849	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3850	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3851	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3852	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3853	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3854	break;
				3855	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3856	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3857	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3858	index = fieldFromInstruction(Insn, 6, 2);
				3859	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3860	align = 2;
				3861	break;
				3862	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3863	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3864	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3865	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	3866
				3867	switch (fieldFromInstruction(Insn, 4, 2)) {
				3868	case 0:
				3869	align = 0; break;
				3870	case 3:
				3871	align = 4; break;
				3872	default:
				3873	return MCDisassembler::Fail;
				3874	}
				3875	break;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3876	}
				3877
				3878	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3879	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3880	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3881	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3882	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3883	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3884	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3885	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3886	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3887	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3888	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3889	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3890	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3891	}
				3892
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3893	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3894	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3895	Inst.addOperand(MCOperand::CreateImm(index));
				3896
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3897	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3898	}
				3899
				3900
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3901	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3902	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3903	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3904
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3905	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3906	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3907	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3908	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3909	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3910
				3911	unsigned align = 0;
				3912	unsigned index = 0;
				3913	unsigned inc = 1;
				3914	switch (size) {
				3915	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3916	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3917	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3918	index = fieldFromInstruction(Insn, 5, 3);
				3919	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3920	align = 2;
				3921	break;
				3922	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3923	index = fieldFromInstruction(Insn, 6, 2);
				3924	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3925	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3926	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3927	inc = 2;
				3928	break;
				3929	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3930	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3931	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3932	index = fieldFromInstruction(Insn, 7, 1);
				3933	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3934	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3935	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3936	inc = 2;
				3937	break;
				3938	}
				3939
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3940	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3941	return MCDisassembler::Fail;
				3942	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3943	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3944	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3945	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3946	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3947	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3948	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3949	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3950	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3951	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3952	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3953	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3954	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3955	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	3956	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3957	}
				3958
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3959	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3960	return MCDisassembler::Fail;
				3961	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				3962	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3963	Inst.addOperand(MCOperand::CreateImm(index));
				3964
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3965	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3966	}
				3967
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	3968	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3969	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	3970	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	3971
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3972	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3973	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3974	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3975	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3976	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3977
				3978	unsigned align = 0;
				3979	unsigned index = 0;
				3980	unsigned inc = 1;
				3981	switch (size) {
				3982	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3983	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3984	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3985	index = fieldFromInstruction(Insn, 5, 3);
				3986	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3987	align = 2;
				3988	break;
				3989	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3990	index = fieldFromInstruction(Insn, 6, 2);
				3991	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3992	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3993	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	3994	inc = 2;
				3995	break;
				3996	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3997	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	3998	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	3999	index = fieldFromInstruction(Insn, 7, 1);
				4000	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4001	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4002	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4003	inc = 2;
				4004	break;
				4005	}
				4006
				4007	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4008	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4009	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4010	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4011	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4012	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4013	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4014	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4015	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4016	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4017	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4018	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4019	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4020	}
				4021
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4022	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4023	return MCDisassembler::Fail;
				4024	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4025	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4026	Inst.addOperand(MCOperand::CreateImm(index));
				4027
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4028	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4029	}
				4030
				4031
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4032	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4033	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4034	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4035
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4036	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4037	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4038	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4039	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4040	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4041
				4042	unsigned align = 0;
				4043	unsigned index = 0;
				4044	unsigned inc = 1;
				4045	switch (size) {
				4046	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4047	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4048	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4049	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4050	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4051	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4052	break;
				4053	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4054	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4055	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4056	index = fieldFromInstruction(Insn, 6, 2);
				4057	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4058	inc = 2;
				4059	break;
				4060	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4061	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4062	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4063	index = fieldFromInstruction(Insn, 7, 1);
				4064	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4065	inc = 2;
				4066	break;
				4067	}
				4068
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4069	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4070	return MCDisassembler::Fail;
				4071	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4072	return MCDisassembler::Fail;
				4073	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4074	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4075
				4076	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4077	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4078	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4079	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4080	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4081	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4082	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4083	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4084	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4085	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4086	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4087	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4088	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4089	}
				4090
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4091	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4092	return MCDisassembler::Fail;
				4093	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4094	return MCDisassembler::Fail;
				4095	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4096	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4097	Inst.addOperand(MCOperand::CreateImm(index));
				4098
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4099	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4100	}
				4101
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4102	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4103	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4104	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4105
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4106	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4107	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4108	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4109	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4110	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4111
				4112	unsigned align = 0;
				4113	unsigned index = 0;
				4114	unsigned inc = 1;
				4115	switch (size) {
				4116	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4117	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4118	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4119	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4120	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4121	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4122	break;
				4123	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4124	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4125	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4126	index = fieldFromInstruction(Insn, 6, 2);
				4127	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4128	inc = 2;
				4129	break;
				4130	case 2:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4131	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4132	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4133	index = fieldFromInstruction(Insn, 7, 1);
				4134	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4135	inc = 2;
				4136	break;
				4137	}
				4138
				4139	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4140	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4141	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4142	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4143	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4144	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4145	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4146	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4147	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4148	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4149	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4150	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4151	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4152	}
				4153
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4154	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4155	return MCDisassembler::Fail;
				4156	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4157	return MCDisassembler::Fail;
				4158	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4159	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4160	Inst.addOperand(MCOperand::CreateImm(index));
				4161
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4162	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4163	}
				4164
				4165
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4166	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4167	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4168	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4169
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4170	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4171	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4172	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4173	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4174	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4175
				4176	unsigned align = 0;
				4177	unsigned index = 0;
				4178	unsigned inc = 1;
				4179	switch (size) {
				4180	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4181	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4182	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4183	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4184	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4185	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4186	break;
				4187	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4188	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4189	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4190	index = fieldFromInstruction(Insn, 6, 2);
				4191	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4192	inc = 2;
				4193	break;
				4194	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4195	switch (fieldFromInstruction(Insn, 4, 2)) {
				4196	case 0:
				4197	align = 0; break;
				4198	case 3:
				4199	return MCDisassembler::Fail;
				4200	default:
				4201	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4202	}
				4203
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4204	index = fieldFromInstruction(Insn, 7, 1);
				4205	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4206	inc = 2;
				4207	break;
				4208	}
				4209
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4210	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4211	return MCDisassembler::Fail;
				4212	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4213	return MCDisassembler::Fail;
				4214	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4215	return MCDisassembler::Fail;
				4216	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4217	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4218
				4219	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4220	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4221	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4222	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4223	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4224	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4225	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4226	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4227	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4228	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4229	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4230	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4231	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4232	}
				4233
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4234	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4235	return MCDisassembler::Fail;
				4236	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4237	return MCDisassembler::Fail;
				4238	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4239	return MCDisassembler::Fail;
				4240	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4241	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4242	Inst.addOperand(MCOperand::CreateImm(index));
				4243
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4244	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4245	}
				4246
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4247	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4248	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4249	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4250
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4251	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4252	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4253	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4254	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4255	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4256
				4257	unsigned align = 0;
				4258	unsigned index = 0;
				4259	unsigned inc = 1;
				4260	switch (size) {
				4261	default:
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4262	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4263	case 0:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4264	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4265	align = 4;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4266	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4267	break;
				4268	case 1:
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4269	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4270	align = 8;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4271	index = fieldFromInstruction(Insn, 6, 2);
				4272	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4273	inc = 2;
				4274	break;
				4275	case 2:
Tim Northover	eae1d34	2012-09-06 15:17:49 +0000	[diff] [blame]	4276	switch (fieldFromInstruction(Insn, 4, 2)) {
				4277	case 0:
				4278	align = 0; break;
				4279	case 3:
				4280	return MCDisassembler::Fail;
				4281	default:
				4282	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4283	}
				4284
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4285	index = fieldFromInstruction(Insn, 7, 1);
				4286	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4287	inc = 2;
				4288	break;
				4289	}
				4290
				4291	if (Rm != 0xF) { // Writeback
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4292	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4293	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4294	}
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4295	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4296	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4297	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4298	if (Rm != 0xF) {
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4299	if (Rm != 0xD) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4300	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4301	return MCDisassembler::Fail;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4302	} else
Owen Anderson	2cbf210	2011-08-22 18:42:13 +0000	[diff] [blame]	4303	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4304	}
				4305
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4306	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4307	return MCDisassembler::Fail;
				4308	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4309	return MCDisassembler::Fail;
				4310	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4311	return MCDisassembler::Fail;
				4312	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4313	return MCDisassembler::Fail;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4314	Inst.addOperand(MCOperand::CreateImm(index));
				4315
Owen Anderson	83e3f67	2011-08-17 17:44:15 +0000	[diff] [blame]	4316	return S;
Owen Anderson	7a2e177	2011-08-15 18:44:44 +0000	[diff] [blame]	4317	}
				4318
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4319	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4320	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4321	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4322	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4323	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4324	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4325	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4326	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4327
				4328	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4329	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4330
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4331	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4332	return MCDisassembler::Fail;
				4333	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4334	return MCDisassembler::Fail;
				4335	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4336	return MCDisassembler::Fail;
				4337	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4338	return MCDisassembler::Fail;
				4339	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4340	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4341
				4342	return S;
				4343	}
				4344
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4345	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4346	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4347	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4348	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4349	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4350	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4351	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4352	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4353
				4354	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4355	S = MCDisassembler::SoftFail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4356
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4357	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4358	return MCDisassembler::Fail;
				4359	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4360	return MCDisassembler::Fail;
				4361	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4362	return MCDisassembler::Fail;
				4363	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4364	return MCDisassembler::Fail;
				4365	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4366	return MCDisassembler::Fail;
Owen Anderson	357ec68	2011-08-22 20:27:12 +0000	[diff] [blame]	4367
				4368	return S;
				4369	}
Owen Anderson	8e1e60b	2011-08-22 23:44:04 +0000	[diff] [blame]	4370
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4371	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4372	uint64_t Address, const void *Decoder) {
Owen Anderson	a680444	2011-09-01 23:23:50 +0000	[diff] [blame]	4373	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4374	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4375	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4376
				4377	if (pred == 0xF) {
				4378	pred = 0xE;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4379	S = MCDisassembler::SoftFail;
Owen Anderson	e234d02	2011-08-24 17:21:43 +0000	[diff] [blame]	4380	}
				4381
Richard Barton	4d2f077	2012-04-27 08:42:59 +0000	[diff] [blame]	4382	if (mask == 0x0) {
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4383	mask \|= 0x8;
James Molloy	c047dca	2011-09-01 18:02:14 +0000	[diff] [blame]	4384	S = MCDisassembler::SoftFail;
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4385	}
Owen Anderson	eaca928	2011-08-30 22:58:27 +0000	[diff] [blame]	4386
				4387	Inst.addOperand(MCOperand::CreateImm(pred));
				4388	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	f440820	2011-08-24 22:40:22 +0000	[diff] [blame]	4389	return S;
				4390	}
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4391
				4392	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4393	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4394	uint64_t Address, const void *Decoder) {
				4395	DecodeStatus S = MCDisassembler::Success;
				4396
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4397	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4398	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4399	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4400	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4401	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4402	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4403	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4404	bool writeback = (W == 1) \| (P == 0);
				4405
				4406	addr \|= (U << 8) \| (Rn << 9);
				4407
				4408	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4409	Check(S, MCDisassembler::SoftFail);
				4410	if (Rt == Rt2)
				4411	Check(S, MCDisassembler::SoftFail);
				4412
				4413	// Rt
				4414	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4415	return MCDisassembler::Fail;
				4416	// Rt2
				4417	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4418	return MCDisassembler::Fail;
				4419	// Writeback operand
				4420	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4421	return MCDisassembler::Fail;
				4422	// addr
				4423	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4424	return MCDisassembler::Fail;
				4425
				4426	return S;
				4427	}
				4428
				4429	static DecodeStatus
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4430	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4431	uint64_t Address, const void *Decoder) {
				4432	DecodeStatus S = MCDisassembler::Success;
				4433
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4434	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4435	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4436	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4437	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4438	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4439	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4440	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	a77295d	2011-09-08 22:07:06 +0000	[diff] [blame]	4441	bool writeback = (W == 1) \| (P == 0);
				4442
				4443	addr \|= (U << 8) \| (Rn << 9);
				4444
				4445	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4446	Check(S, MCDisassembler::SoftFail);
				4447
				4448	// Writeback operand
				4449	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4450	return MCDisassembler::Fail;
				4451	// Rt
				4452	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4453	return MCDisassembler::Fail;
				4454	// Rt2
				4455	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4456	return MCDisassembler::Fail;
				4457	// addr
				4458	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4459	return MCDisassembler::Fail;
				4460
				4461	return S;
				4462	}
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4463
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4464	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4465	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4466	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4467	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4468	if (sign1 != sign2) return MCDisassembler::Fail;
				4469
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4470	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4471	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4472	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	08fef88	2011-09-09 22:24:36 +0000	[diff] [blame]	4473	Val \|= sign1 << 12;
				4474	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4475
				4476	return MCDisassembler::Success;
				4477	}
				4478
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4479	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	0afa009	2011-09-26 21:06:22 +0000	[diff] [blame]	4480	uint64_t Address,
				4481	const void *Decoder) {
				4482	DecodeStatus S = MCDisassembler::Success;
				4483
				4484	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4485	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4486	Inst.addOperand(MCOperand::CreateImm(Val));
				4487	return S;
				4488	}
				4489
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4490	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4491	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4492	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4493	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4494	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4495	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4496
				4497	if (pred == 0xF)
				4498	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4499
				4500	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	35ee7d2	2012-04-18 14:18:57 +0000	[diff] [blame]	4501
				4502	if (Rt == Rn \|\| Rn == Rt2)
				4503	S = MCDisassembler::SoftFail;
				4504
Owen Anderson	cb9fed6	2011-10-28 18:02:13 +0000	[diff] [blame]	4505	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4506	return MCDisassembler::Fail;
				4507	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4508	return MCDisassembler::Fail;
				4509	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4510	return MCDisassembler::Fail;
				4511	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4512	return MCDisassembler::Fail;
				4513
				4514	return S;
				4515	}
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4516
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4517	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4518	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4519	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4520	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4521	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4522	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4523	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4524	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4525
				4526	DecodeStatus S = MCDisassembler::Success;
				4527
				4528	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	22925d9	2011-11-15 20:30:41 +0000	[diff] [blame]	4529	if (!(imm & 0x38) && cmode == 0xF) {
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4530	Inst.setOpcode(ARM::VMOVv2f32);
				4531	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4532	}
				4533
				4534	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4535
				4536	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4537	return MCDisassembler::Fail;
				4538	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4539	return MCDisassembler::Fail;
				4540	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4541
				4542	return S;
				4543	}
				4544
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4545	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4546	uint64_t Address, const void *Decoder) {
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4547	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4548	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4549	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4550	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4551	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4552	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Anderson	b589be9	2011-11-15 19:55:00 +0000	[diff] [blame]	4553
				4554	DecodeStatus S = MCDisassembler::Success;
				4555
				4556	// VMOVv4f32 is ambiguous with these decodings.
				4557	if (!(imm & 0x38) && cmode == 0xF) {
				4558	Inst.setOpcode(ARM::VMOVv4f32);
				4559	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4560	}
				4561
				4562	if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
				4563
				4564	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4565	return MCDisassembler::Fail;
				4566	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4567	return MCDisassembler::Fail;
				4568	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4569
				4570	return S;
				4571	}
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4572
Quentin Colombet	7c4cf03	2013-04-17 18:46:12 +0000	[diff] [blame]	4573	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				4574	const void *Decoder)
				4575	{
				4576	unsigned Imm = fieldFromInstruction(Insn, 0, 3);
				4577	if (Imm > 4) return MCDisassembler::Fail;
				4578	Inst.addOperand(MCOperand::CreateImm(Imm));
				4579	return MCDisassembler::Success;
				4580	}
				4581
Craig Topper	c89c744	2012-03-27 07:21:54 +0000	[diff] [blame]	4582	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4583	uint64_t Address, const void *Decoder) {
				4584	DecodeStatus S = MCDisassembler::Success;
				4585
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4586	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4587	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4588	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4589	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4590	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4591
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4592	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	b7c2ed6	2012-03-22 13:24:43 +0000	[diff] [blame]	4593	S = MCDisassembler::SoftFail;
				4594
				4595	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4596	return MCDisassembler::Fail;
				4597	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4598	return MCDisassembler::Fail;
				4599	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4600	return MCDisassembler::Fail;
				4601	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4602	return MCDisassembler::Fail;
				4603	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4604	return MCDisassembler::Fail;
				4605
				4606	return S;
				4607	}
				4608
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4609	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4610	uint64_t Address, const void *Decoder) {
				4611
				4612	DecodeStatus S = MCDisassembler::Success;
				4613
Jim Grosbach	fc1a161	2012-08-14 19:06:05 +0000	[diff] [blame]	4614	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4615	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4616	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4617	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4618	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	fa1ebc6	2012-04-18 13:12:50 +0000	[diff] [blame]	4619
				4620	if ((cop & ~0x1) == 0xa)
				4621	return MCDisassembler::Fail;
				4622
				4623	if (Rt == Rt2)
				4624	S = MCDisassembler::SoftFail;
				4625
				4626	Inst.addOperand(MCOperand::CreateImm(cop));
				4627	Inst.addOperand(MCOperand::CreateImm(opc1));
				4628	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4629	return MCDisassembler::Fail;
				4630	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4631	return MCDisassembler::Fail;
				4632	Inst.addOperand(MCOperand::CreateImm(CRm));
				4633
				4634	return S;
				4635	}
				4636