blob: 425b192d0def9cfe737f24237efa1dc986635369 [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
34#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010036#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Egbert Eiche5868a32013-02-28 04:17:12 -050039static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010049 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050050 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
91
92
Zhenyu Wang036a4a72009-06-08 14:40:19 +080093/* For display hotplug interrupt */
Chris Wilson995b6762010-08-20 13:23:26 +010094static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050095ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080096{
Chris Wilson1ec14ad2010-12-04 11:30:53 +000097 if ((dev_priv->irq_mask & mask) != 0) {
98 dev_priv->irq_mask &= ~mask;
99 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000100 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800101 }
102}
103
104static inline void
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500105ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800106{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000107 if ((dev_priv->irq_mask & mask) != mask) {
108 dev_priv->irq_mask |= mask;
109 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000110 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800111 }
112}
113
Keith Packard7c463582008-11-04 02:03:27 -0800114void
115i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
116{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200117 u32 reg = PIPESTAT(pipe);
118 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800119
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200120 if ((pipestat & mask) == mask)
121 return;
122
123 /* Enable the interrupt, clear any pending status */
124 pipestat |= mask | (mask >> 16);
125 I915_WRITE(reg, pipestat);
126 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800127}
128
129void
130i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
131{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200132 u32 reg = PIPESTAT(pipe);
133 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800134
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200135 if ((pipestat & mask) == 0)
136 return;
137
138 pipestat &= ~mask;
139 I915_WRITE(reg, pipestat);
140 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800141}
142
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000143/**
Zhao Yakui01c66882009-10-28 05:10:00 +0000144 * intel_enable_asle - enable ASLE interrupt for OpRegion
145 */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000146void intel_enable_asle(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000147{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000148 drm_i915_private_t *dev_priv = dev->dev_private;
149 unsigned long irqflags;
150
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700151 /* FIXME: opregion/asle for VLV */
152 if (IS_VALLEYVIEW(dev))
153 return;
154
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000155 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000156
Eric Anholtc619eed2010-01-28 16:45:52 -0800157 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500158 ironlake_enable_display_irq(dev_priv, DE_GSE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800159 else {
Zhao Yakui01c66882009-10-28 05:10:00 +0000160 i915_enable_pipestat(dev_priv, 1,
Jesse Barnesd874bcf2010-06-30 13:16:00 -0700161 PIPE_LEGACY_BLC_EVENT_ENABLE);
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100162 if (INTEL_INFO(dev)->gen >= 4)
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800163 i915_enable_pipestat(dev_priv, 0,
Jesse Barnesd874bcf2010-06-30 13:16:00 -0700164 PIPE_LEGACY_BLC_EVENT_ENABLE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800165 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000166
167 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000168}
169
170/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700171 * i915_pipe_enabled - check if a pipe is enabled
172 * @dev: DRM device
173 * @pipe: pipe to check
174 *
175 * Reading certain registers when the pipe is disabled can hang the chip.
176 * Use this routine to make sure the PLL is running and the pipe is active
177 * before reading such registers if unsure.
178 */
179static int
180i915_pipe_enabled(struct drm_device *dev, int pipe)
181{
182 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
184 pipe);
185
186 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700187}
188
Keith Packard42f52ef2008-10-18 19:39:29 -0700189/* Called from drm generic code, passed a 'crtc', which
190 * we use as a pipe index
191 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700192static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700193{
194 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
195 unsigned long high_frame;
196 unsigned long low_frame;
Chris Wilson5eddb702010-09-11 13:48:45 +0100197 u32 high1, high2, low;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700198
199 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800200 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800201 "pipe %c\n", pipe_name(pipe));
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700202 return 0;
203 }
204
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800205 high_frame = PIPEFRAME(pipe);
206 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100207
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700208 /*
209 * High & low register fields aren't synchronized, so make sure
210 * we get a low value that's stable across two reads of the high
211 * register.
212 */
213 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100214 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
215 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
216 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700217 } while (high1 != high2);
218
Chris Wilson5eddb702010-09-11 13:48:45 +0100219 high1 >>= PIPE_FRAME_HIGH_SHIFT;
220 low >>= PIPE_FRAME_LOW_SHIFT;
221 return (high1 << 8) | low;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700222}
223
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700224static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800225{
226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800227 int reg = PIPE_FRMCOUNT_GM45(pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800228
229 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800230 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800231 "pipe %c\n", pipe_name(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800232 return 0;
233 }
234
235 return I915_READ(reg);
236}
237
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700238static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100239 int *vpos, int *hpos)
240{
241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
242 u32 vbl = 0, position = 0;
243 int vbl_start, vbl_end, htotal, vtotal;
244 bool in_vbl = true;
245 int ret = 0;
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
247 pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100248
249 if (!i915_pipe_enabled(dev, pipe)) {
250 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800251 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100252 return 0;
253 }
254
255 /* Get vtotal. */
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200256 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100257
258 if (INTEL_INFO(dev)->gen >= 4) {
259 /* No obvious pixelcount register. Only query vertical
260 * scanout position from Display scan line register.
261 */
262 position = I915_READ(PIPEDSL(pipe));
263
264 /* Decode into vertical scanout position. Don't have
265 * horizontal scanout position.
266 */
267 *vpos = position & 0x1fff;
268 *hpos = 0;
269 } else {
270 /* Have access to pixelcount since start of frame.
271 * We can split this into vertical and horizontal
272 * scanout position.
273 */
274 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
275
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200276 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100277 *vpos = position / htotal;
278 *hpos = position - (*vpos * htotal);
279 }
280
281 /* Query vblank area. */
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200282 vbl = I915_READ(VBLANK(cpu_transcoder));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100283
284 /* Test position against vblank region. */
285 vbl_start = vbl & 0x1fff;
286 vbl_end = (vbl >> 16) & 0x1fff;
287
288 if ((*vpos < vbl_start) || (*vpos > vbl_end))
289 in_vbl = false;
290
291 /* Inside "upper part" of vblank area? Apply corrective offset: */
292 if (in_vbl && (*vpos >= vbl_start))
293 *vpos = *vpos - vtotal;
294
295 /* Readouts valid? */
296 if (vbl > 0)
297 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
298
299 /* In vblank? */
300 if (in_vbl)
301 ret |= DRM_SCANOUTPOS_INVBL;
302
303 return ret;
304}
305
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700306static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100307 int *max_error,
308 struct timeval *vblank_time,
309 unsigned flags)
310{
Chris Wilson4041b852011-01-22 10:07:56 +0000311 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100312
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700313 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000314 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100315 return -EINVAL;
316 }
317
318 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000319 crtc = intel_get_crtc_for_pipe(dev, pipe);
320 if (crtc == NULL) {
321 DRM_ERROR("Invalid crtc %d\n", pipe);
322 return -EINVAL;
323 }
324
325 if (!crtc->enabled) {
326 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
327 return -EBUSY;
328 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100329
330 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000331 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
332 vblank_time, flags,
333 crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100334}
335
Jesse Barnes5ca58282009-03-31 14:11:15 -0700336/*
337 * Handle hotplug events outside the interrupt handler proper.
338 */
339static void i915_hotplug_work_func(struct work_struct *work)
340{
341 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
342 hotplug_work);
343 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700344 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100345 struct intel_encoder *encoder;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700346
Daniel Vetter52d7ece2012-12-01 21:03:22 +0100347 /* HPD irq before everything is fully set up. */
348 if (!dev_priv->enable_hotplug_processing)
349 return;
350
Keith Packarda65e34c2011-07-25 10:04:56 -0700351 mutex_lock(&mode_config->mutex);
Jesse Barnese67189ab2011-02-11 14:44:51 -0800352 DRM_DEBUG_KMS("running encoder hotplug functions\n");
353
Chris Wilson4ef69c72010-09-09 15:14:28 +0100354 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
355 if (encoder->hot_plug)
356 encoder->hot_plug(encoder);
357
Keith Packard40ee3382011-07-28 15:31:19 -0700358 mutex_unlock(&mode_config->mutex);
359
Jesse Barnes5ca58282009-03-31 14:11:15 -0700360 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000361 drm_helper_hpd_irq_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700362}
363
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200364static void ironlake_handle_rps_change(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800365{
366 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000367 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200368 u8 new_delay;
369 unsigned long flags;
370
371 spin_lock_irqsave(&mchdev_lock, flags);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800372
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200373 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
374
Daniel Vetter20e4d402012-08-08 23:35:39 +0200375 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200376
Jesse Barnes7648fa92010-05-20 14:28:11 -0700377 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000378 busy_up = I915_READ(RCPREVBSYTUPAVG);
379 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800380 max_avg = I915_READ(RCBMAXAVG);
381 min_avg = I915_READ(RCBMINAVG);
382
383 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000384 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200385 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
386 new_delay = dev_priv->ips.cur_delay - 1;
387 if (new_delay < dev_priv->ips.max_delay)
388 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000389 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200390 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
391 new_delay = dev_priv->ips.cur_delay + 1;
392 if (new_delay > dev_priv->ips.min_delay)
393 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800394 }
395
Jesse Barnes7648fa92010-05-20 14:28:11 -0700396 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200397 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800398
Daniel Vetter92703882012-08-09 16:46:01 +0200399 spin_unlock_irqrestore(&mchdev_lock, flags);
400
Jesse Barnesf97108d2010-01-29 11:27:07 -0800401 return;
402}
403
Chris Wilson549f7362010-10-19 11:19:32 +0100404static void notify_ring(struct drm_device *dev,
405 struct intel_ring_buffer *ring)
406{
407 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9862e602011-01-04 22:22:17 +0000408
Chris Wilson475553d2011-01-20 09:52:56 +0000409 if (ring->obj == NULL)
410 return;
411
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100412 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
Chris Wilson9862e602011-01-04 22:22:17 +0000413
Chris Wilson549f7362010-10-19 11:19:32 +0100414 wake_up_all(&ring->irq_queue);
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700415 if (i915_enable_hangcheck) {
Daniel Vetter99584db2012-11-14 17:14:04 +0100416 dev_priv->gpu_error.hangcheck_count = 0;
417 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
Chris Wilsoncecc21f2012-10-05 17:02:56 +0100418 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700419 }
Chris Wilson549f7362010-10-19 11:19:32 +0100420}
421
Ben Widawsky4912d042011-04-25 11:25:20 -0700422static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800423{
Ben Widawsky4912d042011-04-25 11:25:20 -0700424 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200425 rps.work);
Ben Widawsky4912d042011-04-25 11:25:20 -0700426 u32 pm_iir, pm_imr;
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100427 u8 new_delay;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800428
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200429 spin_lock_irq(&dev_priv->rps.lock);
430 pm_iir = dev_priv->rps.pm_iir;
431 dev_priv->rps.pm_iir = 0;
Ben Widawsky4912d042011-04-25 11:25:20 -0700432 pm_imr = I915_READ(GEN6_PMIMR);
Daniel Vettera9e26412011-09-08 14:00:21 +0200433 I915_WRITE(GEN6_PMIMR, 0);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200434 spin_unlock_irq(&dev_priv->rps.lock);
Ben Widawsky4912d042011-04-25 11:25:20 -0700435
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100436 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800437 return;
438
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700439 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100440
441 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200442 new_delay = dev_priv->rps.cur_delay + 1;
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100443 else
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200444 new_delay = dev_priv->rps.cur_delay - 1;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800445
Ben Widawsky79249632012-09-07 19:43:42 -0700446 /* sysfs frequency interfaces may have snuck in while servicing the
447 * interrupt
448 */
449 if (!(new_delay > dev_priv->rps.max_delay ||
450 new_delay < dev_priv->rps.min_delay)) {
451 gen6_set_rps(dev_priv->dev, new_delay);
452 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800453
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700454 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800455}
456
Ben Widawskye3689192012-05-25 16:56:22 -0700457
458/**
459 * ivybridge_parity_work - Workqueue called when a parity error interrupt
460 * occurred.
461 * @work: workqueue struct
462 *
463 * Doesn't actually do anything except notify userspace. As a consequence of
464 * this event, userspace should try to remap the bad rows since statistically
465 * it is likely the same row is more likely to go bad again.
466 */
467static void ivybridge_parity_work(struct work_struct *work)
468{
469 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100470 l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -0700471 u32 error_status, row, bank, subbank;
472 char *parity_event[5];
473 uint32_t misccpctl;
474 unsigned long flags;
475
476 /* We must turn off DOP level clock gating to access the L3 registers.
477 * In order to prevent a get/put style interface, acquire struct mutex
478 * any time we access those registers.
479 */
480 mutex_lock(&dev_priv->dev->struct_mutex);
481
482 misccpctl = I915_READ(GEN7_MISCCPCTL);
483 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
484 POSTING_READ(GEN7_MISCCPCTL);
485
486 error_status = I915_READ(GEN7_L3CDERRST1);
487 row = GEN7_PARITY_ERROR_ROW(error_status);
488 bank = GEN7_PARITY_ERROR_BANK(error_status);
489 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
490
491 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
492 GEN7_L3CDERRST1_ENABLE);
493 POSTING_READ(GEN7_L3CDERRST1);
494
495 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
496
497 spin_lock_irqsave(&dev_priv->irq_lock, flags);
498 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
499 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
500 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
501
502 mutex_unlock(&dev_priv->dev->struct_mutex);
503
504 parity_event[0] = "L3_PARITY_ERROR=1";
505 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
506 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
507 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
508 parity_event[4] = NULL;
509
510 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
511 KOBJ_CHANGE, parity_event);
512
513 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
514 row, bank, subbank);
515
516 kfree(parity_event[3]);
517 kfree(parity_event[2]);
518 kfree(parity_event[1]);
519}
520
Daniel Vetterd2ba8472012-05-31 14:57:41 +0200521static void ivybridge_handle_parity_error(struct drm_device *dev)
Ben Widawskye3689192012-05-25 16:56:22 -0700522{
523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
524 unsigned long flags;
525
Ben Widawskye1ef7cc2012-07-24 20:47:31 -0700526 if (!HAS_L3_GPU_CACHE(dev))
Ben Widawskye3689192012-05-25 16:56:22 -0700527 return;
528
529 spin_lock_irqsave(&dev_priv->irq_lock, flags);
530 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
531 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
532 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
533
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100534 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -0700535}
536
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200537static void snb_gt_irq_handler(struct drm_device *dev,
538 struct drm_i915_private *dev_priv,
539 u32 gt_iir)
540{
541
542 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
543 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
544 notify_ring(dev, &dev_priv->ring[RCS]);
545 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
546 notify_ring(dev, &dev_priv->ring[VCS]);
547 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
548 notify_ring(dev, &dev_priv->ring[BCS]);
549
550 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
551 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
552 GT_RENDER_CS_ERROR_INTERRUPT)) {
553 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
554 i915_handle_error(dev, false);
555 }
Ben Widawskye3689192012-05-25 16:56:22 -0700556
557 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
558 ivybridge_handle_parity_error(dev);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200559}
560
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100561static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
562 u32 pm_iir)
563{
564 unsigned long flags;
565
566 /*
567 * IIR bits should never already be set because IMR should
568 * prevent an interrupt from being shown in IIR. The warning
569 * displays a case where we've unsafely cleared
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200570 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100571 * type is not a problem, it displays a problem in the logic.
572 *
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200573 * The mask bit in IMR is cleared by dev_priv->rps.work.
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100574 */
575
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200576 spin_lock_irqsave(&dev_priv->rps.lock, flags);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200577 dev_priv->rps.pm_iir |= pm_iir;
578 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100579 POSTING_READ(GEN6_PMIMR);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200580 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100581
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200582 queue_work(dev_priv->wq, &dev_priv->rps.work);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100583}
584
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100585static void gmbus_irq_handler(struct drm_device *dev)
586{
Daniel Vetter28c70f12012-12-01 13:53:45 +0100587 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
588
Daniel Vetter28c70f12012-12-01 13:53:45 +0100589 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100590}
591
Daniel Vetterce99c252012-12-01 13:53:47 +0100592static void dp_aux_irq_handler(struct drm_device *dev)
593{
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100594 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
595
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100596 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +0100597}
598
Daniel Vetterff1f5252012-10-02 15:10:55 +0200599static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700600{
601 struct drm_device *dev = (struct drm_device *) arg;
602 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
603 u32 iir, gt_iir, pm_iir;
604 irqreturn_t ret = IRQ_NONE;
605 unsigned long irqflags;
606 int pipe;
607 u32 pipe_stats[I915_MAX_PIPES];
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700608
609 atomic_inc(&dev_priv->irq_received);
610
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700611 while (true) {
612 iir = I915_READ(VLV_IIR);
613 gt_iir = I915_READ(GTIIR);
614 pm_iir = I915_READ(GEN6_PMIIR);
615
616 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
617 goto out;
618
619 ret = IRQ_HANDLED;
620
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200621 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700622
623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
624 for_each_pipe(pipe) {
625 int reg = PIPESTAT(pipe);
626 pipe_stats[pipe] = I915_READ(reg);
627
628 /*
629 * Clear the PIPE*STAT regs before the IIR
630 */
631 if (pipe_stats[pipe] & 0x8000ffff) {
632 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
633 DRM_DEBUG_DRIVER("pipe %c underrun\n",
634 pipe_name(pipe));
635 I915_WRITE(reg, pipe_stats[pipe]);
636 }
637 }
638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
639
Jesse Barnes31acc7f2012-06-20 10:53:11 -0700640 for_each_pipe(pipe) {
641 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
642 drm_handle_vblank(dev, pipe);
643
644 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
645 intel_prepare_page_flip(dev, pipe);
646 intel_finish_page_flip(dev, pipe);
647 }
648 }
649
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700650 /* Consume port. Then clear IIR or we'll miss events */
651 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
652 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
653
654 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
655 hotplug_status);
Egbert Eiche5868a32013-02-28 04:17:12 -0500656 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700657 queue_work(dev_priv->wq,
658 &dev_priv->hotplug_work);
659
660 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
661 I915_READ(PORT_HOTPLUG_STAT);
662 }
663
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100664 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
665 gmbus_irq_handler(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700666
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100667 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
668 gen6_queue_rps_work(dev_priv, pm_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700669
670 I915_WRITE(GTIIR, gt_iir);
671 I915_WRITE(GEN6_PMIIR, pm_iir);
672 I915_WRITE(VLV_IIR, iir);
673 }
674
675out:
676 return ret;
677}
678
Adam Jackson23e81d62012-06-06 15:45:44 -0400679static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -0800680{
681 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800682 int pipe;
Jesse Barnes776ad802011-01-04 15:09:39 -0800683
Daniel Vetter76e43832012-10-12 20:14:05 +0200684 if (pch_iir & SDE_HOTPLUG_MASK)
685 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
686
Jesse Barnes776ad802011-01-04 15:09:39 -0800687 if (pch_iir & SDE_AUDIO_POWER_MASK)
688 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
689 (pch_iir & SDE_AUDIO_POWER_MASK) >>
690 SDE_AUDIO_POWER_SHIFT);
691
Daniel Vetterce99c252012-12-01 13:53:47 +0100692 if (pch_iir & SDE_AUX_MASK)
693 dp_aux_irq_handler(dev);
694
Jesse Barnes776ad802011-01-04 15:09:39 -0800695 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100696 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -0800697
698 if (pch_iir & SDE_AUDIO_HDCP_MASK)
699 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
700
701 if (pch_iir & SDE_AUDIO_TRANS_MASK)
702 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
703
704 if (pch_iir & SDE_POISON)
705 DRM_ERROR("PCH poison interrupt\n");
706
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800707 if (pch_iir & SDE_FDI_MASK)
708 for_each_pipe(pipe)
709 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
710 pipe_name(pipe),
711 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -0800712
713 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
714 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
715
716 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
717 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
718
719 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
720 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
721 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
722 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
723}
724
Adam Jackson23e81d62012-06-06 15:45:44 -0400725static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
726{
727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
728 int pipe;
729
Daniel Vetter76e43832012-10-12 20:14:05 +0200730 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
731 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
732
Adam Jackson23e81d62012-06-06 15:45:44 -0400733 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
734 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
735 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
736 SDE_AUDIO_POWER_SHIFT_CPT);
737
738 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +0100739 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -0400740
741 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100742 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -0400743
744 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
745 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
746
747 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
748 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
749
750 if (pch_iir & SDE_FDI_MASK_CPT)
751 for_each_pipe(pipe)
752 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
753 pipe_name(pipe),
754 I915_READ(FDI_RX_IIR(pipe)));
755}
756
Daniel Vetterff1f5252012-10-02 15:10:55 +0200757static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700758{
759 struct drm_device *dev = (struct drm_device *) arg;
760 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300761 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
Chris Wilson0e434062012-05-09 21:45:44 +0100762 irqreturn_t ret = IRQ_NONE;
763 int i;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700764
765 atomic_inc(&dev_priv->irq_received);
766
767 /* disable master interrupt before clearing iir */
768 de_ier = I915_READ(DEIER);
769 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Chris Wilson0e434062012-05-09 21:45:44 +0100770
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300771 /* Disable south interrupts. We'll only write to SDEIIR once, so further
772 * interrupts will will be stored on its back queue, and then we'll be
773 * able to process them after we restore SDEIER (as soon as we restore
774 * it, we'll get an interrupt if SDEIIR still has something to process
775 * due to its back queue). */
776 sde_ier = I915_READ(SDEIER);
777 I915_WRITE(SDEIER, 0);
778 POSTING_READ(SDEIER);
779
Chris Wilson0e434062012-05-09 21:45:44 +0100780 gt_iir = I915_READ(GTIIR);
781 if (gt_iir) {
782 snb_gt_irq_handler(dev, dev_priv, gt_iir);
783 I915_WRITE(GTIIR, gt_iir);
784 ret = IRQ_HANDLED;
785 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700786
787 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +0100788 if (de_iir) {
Daniel Vetterce99c252012-12-01 13:53:47 +0100789 if (de_iir & DE_AUX_CHANNEL_A_IVB)
790 dp_aux_irq_handler(dev);
791
Chris Wilson0e434062012-05-09 21:45:44 +0100792 if (de_iir & DE_GSE_IVB)
793 intel_opregion_gse_intr(dev);
794
795 for (i = 0; i < 3; i++) {
Daniel Vetter74d44442012-10-02 17:54:35 +0200796 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
797 drm_handle_vblank(dev, i);
Chris Wilson0e434062012-05-09 21:45:44 +0100798 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
799 intel_prepare_page_flip(dev, i);
800 intel_finish_page_flip_plane(dev, i);
801 }
Chris Wilson0e434062012-05-09 21:45:44 +0100802 }
803
804 /* check event from PCH */
805 if (de_iir & DE_PCH_EVENT_IVB) {
806 u32 pch_iir = I915_READ(SDEIIR);
807
Adam Jackson23e81d62012-06-06 15:45:44 -0400808 cpt_irq_handler(dev, pch_iir);
Chris Wilson0e434062012-05-09 21:45:44 +0100809
810 /* clear PCH hotplug event before clear CPU irq */
811 I915_WRITE(SDEIIR, pch_iir);
812 }
813
814 I915_WRITE(DEIIR, de_iir);
815 ret = IRQ_HANDLED;
816 }
817
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700818 pm_iir = I915_READ(GEN6_PMIIR);
Chris Wilson0e434062012-05-09 21:45:44 +0100819 if (pm_iir) {
820 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
821 gen6_queue_rps_work(dev_priv, pm_iir);
822 I915_WRITE(GEN6_PMIIR, pm_iir);
823 ret = IRQ_HANDLED;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700824 }
825
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700826 I915_WRITE(DEIER, de_ier);
827 POSTING_READ(DEIER);
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300828 I915_WRITE(SDEIER, sde_ier);
829 POSTING_READ(SDEIER);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -0700830
831 return ret;
832}
833
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200834static void ilk_gt_irq_handler(struct drm_device *dev,
835 struct drm_i915_private *dev_priv,
836 u32 gt_iir)
837{
838 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
839 notify_ring(dev, &dev_priv->ring[RCS]);
840 if (gt_iir & GT_BSD_USER_INTERRUPT)
841 notify_ring(dev, &dev_priv->ring[VCS]);
842}
843
Daniel Vetterff1f5252012-10-02 15:10:55 +0200844static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800845{
Jesse Barnes46979952011-04-07 13:53:55 -0700846 struct drm_device *dev = (struct drm_device *) arg;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800847 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
848 int ret = IRQ_NONE;
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300849 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100850
Jesse Barnes46979952011-04-07 13:53:55 -0700851 atomic_inc(&dev_priv->irq_received);
852
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000853 /* disable master interrupt before clearing iir */
854 de_ier = I915_READ(DEIER);
855 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000856 POSTING_READ(DEIER);
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000857
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300858 /* Disable south interrupts. We'll only write to SDEIIR once, so further
859 * interrupts will will be stored on its back queue, and then we'll be
860 * able to process them after we restore SDEIER (as soon as we restore
861 * it, we'll get an interrupt if SDEIIR still has something to process
862 * due to its back queue). */
863 sde_ier = I915_READ(SDEIER);
864 I915_WRITE(SDEIER, 0);
865 POSTING_READ(SDEIER);
866
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800867 de_iir = I915_READ(DEIIR);
868 gt_iir = I915_READ(GTIIR);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800869 pm_iir = I915_READ(GEN6_PMIIR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800870
Daniel Vetteracd15b62012-11-30 11:24:50 +0100871 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
Zou Nan haic7c85102010-01-15 10:29:06 +0800872 goto done;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800873
Zou Nan haic7c85102010-01-15 10:29:06 +0800874 ret = IRQ_HANDLED;
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800875
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200876 if (IS_GEN5(dev))
877 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
878 else
879 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Zou Nan haic7c85102010-01-15 10:29:06 +0800880
Daniel Vetterce99c252012-12-01 13:53:47 +0100881 if (de_iir & DE_AUX_CHANNEL_A)
882 dp_aux_irq_handler(dev);
883
Zou Nan haic7c85102010-01-15 10:29:06 +0800884 if (de_iir & DE_GSE)
Chris Wilson3b617962010-08-24 09:02:58 +0100885 intel_opregion_gse_intr(dev);
Zou Nan haic7c85102010-01-15 10:29:06 +0800886
Daniel Vetter74d44442012-10-02 17:54:35 +0200887 if (de_iir & DE_PIPEA_VBLANK)
888 drm_handle_vblank(dev, 0);
889
890 if (de_iir & DE_PIPEB_VBLANK)
891 drm_handle_vblank(dev, 1);
892
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800893 if (de_iir & DE_PLANEA_FLIP_DONE) {
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800894 intel_prepare_page_flip(dev, 0);
Chris Wilson2bbda382010-09-02 17:59:39 +0100895 intel_finish_page_flip_plane(dev, 0);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800896 }
897
Zhenyu Wangf072d2e2010-02-09 09:46:19 +0800898 if (de_iir & DE_PLANEB_FLIP_DONE) {
899 intel_prepare_page_flip(dev, 1);
Chris Wilson2bbda382010-09-02 17:59:39 +0100900 intel_finish_page_flip_plane(dev, 1);
Jesse Barnes013d5aa2010-01-29 11:18:31 -0800901 }
Li Pengc062df62010-01-23 00:12:58 +0800902
Zou Nan haic7c85102010-01-15 10:29:06 +0800903 /* check event from PCH */
Jesse Barnes776ad802011-01-04 15:09:39 -0800904 if (de_iir & DE_PCH_EVENT) {
Daniel Vetteracd15b62012-11-30 11:24:50 +0100905 u32 pch_iir = I915_READ(SDEIIR);
906
Adam Jackson23e81d62012-06-06 15:45:44 -0400907 if (HAS_PCH_CPT(dev))
908 cpt_irq_handler(dev, pch_iir);
909 else
910 ibx_irq_handler(dev, pch_iir);
Daniel Vetteracd15b62012-11-30 11:24:50 +0100911
912 /* should clear PCH hotplug event before clear CPU irq */
913 I915_WRITE(SDEIIR, pch_iir);
Jesse Barnes776ad802011-01-04 15:09:39 -0800914 }
Zou Nan haic7c85102010-01-15 10:29:06 +0800915
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200916 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
917 ironlake_handle_rps_change(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800918
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100919 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
920 gen6_queue_rps_work(dev_priv, pm_iir);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800921
Zou Nan haic7c85102010-01-15 10:29:06 +0800922 I915_WRITE(GTIIR, gt_iir);
923 I915_WRITE(DEIIR, de_iir);
Ben Widawsky4912d042011-04-25 11:25:20 -0700924 I915_WRITE(GEN6_PMIIR, pm_iir);
Zou Nan haic7c85102010-01-15 10:29:06 +0800925
926done:
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000927 I915_WRITE(DEIER, de_ier);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000928 POSTING_READ(DEIER);
Paulo Zanoni44498ae2013-02-22 17:05:28 -0300929 I915_WRITE(SDEIER, sde_ier);
930 POSTING_READ(SDEIER);
Zou, Nanhai2d109a82009-11-06 02:13:01 +0000931
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800932 return ret;
933}
934
Jesse Barnes8a905232009-07-11 16:48:03 -0400935/**
936 * i915_error_work_func - do process context error handling work
937 * @work: work struct
938 *
939 * Fire an error uevent so userspace can see that a hang or error
940 * was detected.
941 */
942static void i915_error_work_func(struct work_struct *work)
943{
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100944 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
945 work);
946 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
947 gpu_error);
Jesse Barnes8a905232009-07-11 16:48:03 -0400948 struct drm_device *dev = dev_priv->dev;
Daniel Vetterf69061b2012-12-06 09:01:42 +0100949 struct intel_ring_buffer *ring;
Ben Gamarif316a422009-09-14 17:48:46 -0400950 char *error_event[] = { "ERROR=1", NULL };
951 char *reset_event[] = { "RESET=1", NULL };
952 char *reset_done_event[] = { "ERROR=0", NULL };
Daniel Vetterf69061b2012-12-06 09:01:42 +0100953 int i, ret;
Jesse Barnes8a905232009-07-11 16:48:03 -0400954
Ben Gamarif316a422009-09-14 17:48:46 -0400955 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -0400956
Daniel Vetter7db0ba22012-12-06 16:23:37 +0100957 /*
958 * Note that there's only one work item which does gpu resets, so we
959 * need not worry about concurrent gpu resets potentially incrementing
960 * error->reset_counter twice. We only need to take care of another
961 * racing irq/hangcheck declaring the gpu dead for a second time. A
962 * quick check for that is good enough: schedule_work ensures the
963 * correct ordering between hang detection and this work item, and since
964 * the reset in-progress bit is only ever set by code outside of this
965 * work we don't need to worry about any other races.
966 */
967 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +0100968 DRM_DEBUG_DRIVER("resetting chip\n");
Daniel Vetter7db0ba22012-12-06 16:23:37 +0100969 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
970 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100971
Daniel Vetterf69061b2012-12-06 09:01:42 +0100972 ret = i915_reset(dev);
973
974 if (ret == 0) {
975 /*
976 * After all the gem state is reset, increment the reset
977 * counter and wake up everyone waiting for the reset to
978 * complete.
979 *
980 * Since unlock operations are a one-sided barrier only,
981 * we need to insert a barrier here to order any seqno
982 * updates before
983 * the counter increment.
984 */
985 smp_mb__before_atomic_inc();
986 atomic_inc(&dev_priv->gpu_error.reset_counter);
987
988 kobject_uevent_env(&dev->primary->kdev.kobj,
989 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100990 } else {
991 atomic_set(&error->reset_counter, I915_WEDGED);
Ben Gamarif316a422009-09-14 17:48:46 -0400992 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100993
Daniel Vetterf69061b2012-12-06 09:01:42 +0100994 for_each_ring(ring, dev_priv, i)
995 wake_up_all(&ring->irq_queue);
996
Ville Syrjälä96a02912013-02-18 19:08:49 +0200997 intel_display_handle_reset(dev);
998
Daniel Vetter1f83fee2012-11-15 17:17:22 +0100999 wake_up_all(&dev_priv->gpu_error.reset_queue);
Ben Gamarif316a422009-09-14 17:48:46 -04001000 }
Jesse Barnes8a905232009-07-11 16:48:03 -04001001}
1002
Daniel Vetter85f9e502012-08-31 21:42:26 +02001003/* NB: please notice the memset */
1004static void i915_get_extra_instdone(struct drm_device *dev,
1005 uint32_t *instdone)
1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1009
1010 switch(INTEL_INFO(dev)->gen) {
1011 case 2:
1012 case 3:
1013 instdone[0] = I915_READ(INSTDONE);
1014 break;
1015 case 4:
1016 case 5:
1017 case 6:
1018 instdone[0] = I915_READ(INSTDONE_I965);
1019 instdone[1] = I915_READ(INSTDONE1);
1020 break;
1021 default:
1022 WARN_ONCE(1, "Unsupported platform\n");
1023 case 7:
1024 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1025 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1026 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1027 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1028 break;
1029 }
1030}
1031
Chris Wilson3bd3c932010-08-19 08:19:30 +01001032#ifdef CONFIG_DEBUG_FS
Chris Wilson9df30792010-02-18 10:24:56 +00001033static struct drm_i915_error_object *
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001034i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1035 struct drm_i915_gem_object *src,
1036 const int num_pages)
Chris Wilson9df30792010-02-18 10:24:56 +00001037{
1038 struct drm_i915_error_object *dst;
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001039 int i;
Chris Wilsone56660d2010-08-07 11:01:26 +01001040 u32 reloc_offset;
Chris Wilson9df30792010-02-18 10:24:56 +00001041
Chris Wilson05394f32010-11-08 19:18:58 +00001042 if (src == NULL || src->pages == NULL)
Chris Wilson9df30792010-02-18 10:24:56 +00001043 return NULL;
1044
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001045 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
Chris Wilson9df30792010-02-18 10:24:56 +00001046 if (dst == NULL)
1047 return NULL;
1048
Chris Wilson05394f32010-11-08 19:18:58 +00001049 reloc_offset = src->gtt_offset;
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001050 for (i = 0; i < num_pages; i++) {
Andrew Morton788885a2010-05-11 14:07:05 -07001051 unsigned long flags;
Chris Wilsone56660d2010-08-07 11:01:26 +01001052 void *d;
Andrew Morton788885a2010-05-11 14:07:05 -07001053
Chris Wilsone56660d2010-08-07 11:01:26 +01001054 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
Chris Wilson9df30792010-02-18 10:24:56 +00001055 if (d == NULL)
1056 goto unwind;
Chris Wilsone56660d2010-08-07 11:01:26 +01001057
Andrew Morton788885a2010-05-11 14:07:05 -07001058 local_irq_save(flags);
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001059 if (reloc_offset < dev_priv->gtt.mappable_end &&
Daniel Vetter74898d72012-02-15 23:50:22 +01001060 src->has_global_gtt_mapping) {
Chris Wilson172975aa2011-12-14 13:57:25 +01001061 void __iomem *s;
1062
1063 /* Simply ignore tiling or any overlapping fence.
1064 * It's part of the error state, and this hopefully
1065 * captures what the GPU read.
1066 */
1067
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001068 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
Chris Wilson172975aa2011-12-14 13:57:25 +01001069 reloc_offset);
1070 memcpy_fromio(d, s, PAGE_SIZE);
1071 io_mapping_unmap_atomic(s);
Chris Wilson960e3562012-11-15 11:32:23 +00001072 } else if (src->stolen) {
1073 unsigned long offset;
1074
1075 offset = dev_priv->mm.stolen_base;
1076 offset += src->stolen->start;
1077 offset += i << PAGE_SHIFT;
1078
Daniel Vetter1a240d42012-11-29 22:18:51 +01001079 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
Chris Wilson172975aa2011-12-14 13:57:25 +01001080 } else {
Chris Wilson9da3da62012-06-01 15:20:22 +01001081 struct page *page;
Chris Wilson172975aa2011-12-14 13:57:25 +01001082 void *s;
1083
Chris Wilson9da3da62012-06-01 15:20:22 +01001084 page = i915_gem_object_get_page(src, i);
Chris Wilson172975aa2011-12-14 13:57:25 +01001085
Chris Wilson9da3da62012-06-01 15:20:22 +01001086 drm_clflush_pages(&page, 1);
1087
1088 s = kmap_atomic(page);
Chris Wilson172975aa2011-12-14 13:57:25 +01001089 memcpy(d, s, PAGE_SIZE);
1090 kunmap_atomic(s);
1091
Chris Wilson9da3da62012-06-01 15:20:22 +01001092 drm_clflush_pages(&page, 1);
Chris Wilson172975aa2011-12-14 13:57:25 +01001093 }
Andrew Morton788885a2010-05-11 14:07:05 -07001094 local_irq_restore(flags);
Chris Wilsone56660d2010-08-07 11:01:26 +01001095
Chris Wilson9da3da62012-06-01 15:20:22 +01001096 dst->pages[i] = d;
Chris Wilsone56660d2010-08-07 11:01:26 +01001097
1098 reloc_offset += PAGE_SIZE;
Chris Wilson9df30792010-02-18 10:24:56 +00001099 }
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001100 dst->page_count = num_pages;
Chris Wilson05394f32010-11-08 19:18:58 +00001101 dst->gtt_offset = src->gtt_offset;
Chris Wilson9df30792010-02-18 10:24:56 +00001102
1103 return dst;
1104
1105unwind:
Chris Wilson9da3da62012-06-01 15:20:22 +01001106 while (i--)
1107 kfree(dst->pages[i]);
Chris Wilson9df30792010-02-18 10:24:56 +00001108 kfree(dst);
1109 return NULL;
1110}
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001111#define i915_error_object_create(dev_priv, src) \
1112 i915_error_object_create_sized((dev_priv), (src), \
1113 (src)->base.size>>PAGE_SHIFT)
Chris Wilson9df30792010-02-18 10:24:56 +00001114
1115static void
1116i915_error_object_free(struct drm_i915_error_object *obj)
1117{
1118 int page;
1119
1120 if (obj == NULL)
1121 return;
1122
1123 for (page = 0; page < obj->page_count; page++)
1124 kfree(obj->pages[page]);
1125
1126 kfree(obj);
1127}
1128
Daniel Vetter742cbee2012-04-27 15:17:39 +02001129void
1130i915_error_state_free(struct kref *error_ref)
Chris Wilson9df30792010-02-18 10:24:56 +00001131{
Daniel Vetter742cbee2012-04-27 15:17:39 +02001132 struct drm_i915_error_state *error = container_of(error_ref,
1133 typeof(*error), ref);
Chris Wilsone2f973d2011-01-27 19:15:11 +00001134 int i;
1135
Chris Wilson52d39a22012-02-15 11:25:37 +00001136 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1137 i915_error_object_free(error->ring[i].batchbuffer);
1138 i915_error_object_free(error->ring[i].ringbuffer);
1139 kfree(error->ring[i].requests);
1140 }
Chris Wilsone2f973d2011-01-27 19:15:11 +00001141
Chris Wilson9df30792010-02-18 10:24:56 +00001142 kfree(error->active_bo);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001143 kfree(error->overlay);
Chris Wilson9df30792010-02-18 10:24:56 +00001144 kfree(error);
1145}
Chris Wilson1b502472012-04-24 15:47:30 +01001146static void capture_bo(struct drm_i915_error_buffer *err,
1147 struct drm_i915_gem_object *obj)
1148{
1149 err->size = obj->base.size;
1150 err->name = obj->base.name;
Chris Wilson0201f1e2012-07-20 12:41:01 +01001151 err->rseqno = obj->last_read_seqno;
1152 err->wseqno = obj->last_write_seqno;
Chris Wilson1b502472012-04-24 15:47:30 +01001153 err->gtt_offset = obj->gtt_offset;
1154 err->read_domains = obj->base.read_domains;
1155 err->write_domain = obj->base.write_domain;
1156 err->fence_reg = obj->fence_reg;
1157 err->pinned = 0;
1158 if (obj->pin_count > 0)
1159 err->pinned = 1;
1160 if (obj->user_pin_count > 0)
1161 err->pinned = -1;
1162 err->tiling = obj->tiling_mode;
1163 err->dirty = obj->dirty;
1164 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1165 err->ring = obj->ring ? obj->ring->id : -1;
1166 err->cache_level = obj->cache_level;
1167}
Chris Wilson9df30792010-02-18 10:24:56 +00001168
Chris Wilson1b502472012-04-24 15:47:30 +01001169static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1170 int count, struct list_head *head)
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001171{
1172 struct drm_i915_gem_object *obj;
1173 int i = 0;
1174
1175 list_for_each_entry(obj, head, mm_list) {
Chris Wilson1b502472012-04-24 15:47:30 +01001176 capture_bo(err++, obj);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001177 if (++i == count)
1178 break;
Chris Wilson1b502472012-04-24 15:47:30 +01001179 }
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001180
Chris Wilson1b502472012-04-24 15:47:30 +01001181 return i;
1182}
1183
1184static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1185 int count, struct list_head *head)
1186{
1187 struct drm_i915_gem_object *obj;
1188 int i = 0;
1189
1190 list_for_each_entry(obj, head, gtt_list) {
1191 if (obj->pin_count == 0)
1192 continue;
1193
1194 capture_bo(err++, obj);
1195 if (++i == count)
1196 break;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001197 }
1198
1199 return i;
1200}
1201
Chris Wilson748ebc62010-10-24 10:28:47 +01001202static void i915_gem_record_fences(struct drm_device *dev,
1203 struct drm_i915_error_state *error)
1204{
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 int i;
1207
1208 /* Fences */
1209 switch (INTEL_INFO(dev)->gen) {
Daniel Vetter775d17b2011-10-09 21:52:01 +02001210 case 7:
Chris Wilson748ebc62010-10-24 10:28:47 +01001211 case 6:
1212 for (i = 0; i < 16; i++)
1213 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1214 break;
1215 case 5:
1216 case 4:
1217 for (i = 0; i < 16; i++)
1218 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1219 break;
1220 case 3:
1221 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1222 for (i = 0; i < 8; i++)
1223 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1224 case 2:
1225 for (i = 0; i < 8; i++)
1226 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1227 break;
1228
Ben Widawsky7dbf9d62012-12-18 10:31:22 -08001229 default:
1230 BUG();
Chris Wilson748ebc62010-10-24 10:28:47 +01001231 }
1232}
1233
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001234static struct drm_i915_error_object *
1235i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1236 struct intel_ring_buffer *ring)
1237{
1238 struct drm_i915_gem_object *obj;
1239 u32 seqno;
1240
1241 if (!ring->get_seqno)
1242 return NULL;
1243
Daniel Vetterb45305f2012-12-17 16:21:27 +01001244 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1245 u32 acthd = I915_READ(ACTHD);
1246
1247 if (WARN_ON(ring->id != RCS))
1248 return NULL;
1249
1250 obj = ring->private;
1251 if (acthd >= obj->gtt_offset &&
1252 acthd < obj->gtt_offset + obj->base.size)
1253 return i915_error_object_create(dev_priv, obj);
1254 }
1255
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01001256 seqno = ring->get_seqno(ring, false);
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001257 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1258 if (obj->ring != ring)
1259 continue;
1260
Chris Wilson0201f1e2012-07-20 12:41:01 +01001261 if (i915_seqno_passed(seqno, obj->last_read_seqno))
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001262 continue;
1263
1264 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1265 continue;
1266
1267 /* We need to copy these to an anonymous buffer as the simplest
1268 * method to avoid being overwritten by userspace.
1269 */
1270 return i915_error_object_create(dev_priv, obj);
1271 }
1272
1273 return NULL;
1274}
1275
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001276static void i915_record_ring_state(struct drm_device *dev,
1277 struct drm_i915_error_state *error,
1278 struct intel_ring_buffer *ring)
1279{
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281
Daniel Vetter33f3f512011-12-14 13:57:39 +01001282 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilson12f55812012-07-05 17:14:01 +01001283 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
Daniel Vetter33f3f512011-12-14 13:57:39 +01001284 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
Daniel Vetter7e3b8732012-02-01 22:26:45 +01001285 error->semaphore_mboxes[ring->id][0]
1286 = I915_READ(RING_SYNC_0(ring->mmio_base));
1287 error->semaphore_mboxes[ring->id][1]
1288 = I915_READ(RING_SYNC_1(ring->mmio_base));
Chris Wilsondf2b23d2012-11-27 17:06:54 +00001289 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1290 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
Daniel Vetter33f3f512011-12-14 13:57:39 +01001291 }
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001292
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001293 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001294 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001295 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1296 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1297 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001298 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
Ben Widawsky050ee912012-08-22 11:32:15 -07001299 if (ring->id == RCS)
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001300 error->bbaddr = I915_READ64(BB_ADDR);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001301 } else {
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001302 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001303 error->ipeir[ring->id] = I915_READ(IPEIR);
1304 error->ipehr[ring->id] = I915_READ(IPEHR);
1305 error->instdone[ring->id] = I915_READ(INSTDONE);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001306 }
1307
Ben Widawsky9574b3f2012-04-26 16:03:01 -07001308 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001309 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01001310 error->seqno[ring->id] = ring->get_seqno(ring, false);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001311 error->acthd[ring->id] = intel_ring_get_active_head(ring);
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001312 error->head[ring->id] = I915_READ_HEAD(ring);
1313 error->tail[ring->id] = I915_READ_TAIL(ring);
Chris Wilson0f3b6842013-01-15 12:05:55 +00001314 error->ctl[ring->id] = I915_READ_CTL(ring);
Daniel Vetter7e3b8732012-02-01 22:26:45 +01001315
1316 error->cpu_ring_head[ring->id] = ring->head;
1317 error->cpu_ring_tail[ring->id] = ring->tail;
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001318}
1319
Ben Widawsky8c123e52013-03-04 17:00:29 -08001320
1321static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1322 struct drm_i915_error_state *error,
1323 struct drm_i915_error_ring *ering)
1324{
1325 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1326 struct drm_i915_gem_object *obj;
1327
1328 /* Currently render ring is the only HW context user */
1329 if (ring->id != RCS || !error->ccid)
1330 return;
1331
1332 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1333 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1334 ering->ctx = i915_error_object_create_sized(dev_priv,
1335 obj, 1);
1336 }
1337 }
1338}
1339
Chris Wilson52d39a22012-02-15 11:25:37 +00001340static void i915_gem_record_rings(struct drm_device *dev,
1341 struct drm_i915_error_state *error)
1342{
1343 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb4519512012-05-11 14:29:30 +01001344 struct intel_ring_buffer *ring;
Chris Wilson52d39a22012-02-15 11:25:37 +00001345 struct drm_i915_gem_request *request;
1346 int i, count;
1347
Chris Wilsonb4519512012-05-11 14:29:30 +01001348 for_each_ring(ring, dev_priv, i) {
Chris Wilson52d39a22012-02-15 11:25:37 +00001349 i915_record_ring_state(dev, error, ring);
1350
1351 error->ring[i].batchbuffer =
1352 i915_error_first_batchbuffer(dev_priv, ring);
1353
1354 error->ring[i].ringbuffer =
1355 i915_error_object_create(dev_priv, ring->obj);
1356
Ben Widawsky8c123e52013-03-04 17:00:29 -08001357
1358 i915_gem_record_active_context(ring, error, &error->ring[i]);
1359
Chris Wilson52d39a22012-02-15 11:25:37 +00001360 count = 0;
1361 list_for_each_entry(request, &ring->request_list, list)
1362 count++;
1363
1364 error->ring[i].num_requests = count;
1365 error->ring[i].requests =
1366 kmalloc(count*sizeof(struct drm_i915_error_request),
1367 GFP_ATOMIC);
1368 if (error->ring[i].requests == NULL) {
1369 error->ring[i].num_requests = 0;
1370 continue;
1371 }
1372
1373 count = 0;
1374 list_for_each_entry(request, &ring->request_list, list) {
1375 struct drm_i915_error_request *erq;
1376
1377 erq = &error->ring[i].requests[count++];
1378 erq->seqno = request->seqno;
1379 erq->jiffies = request->emitted_jiffies;
Chris Wilsonee4f42b2012-02-15 11:25:38 +00001380 erq->tail = request->tail;
Chris Wilson52d39a22012-02-15 11:25:37 +00001381 }
1382 }
1383}
1384
Jesse Barnes8a905232009-07-11 16:48:03 -04001385/**
1386 * i915_capture_error_state - capture an error record for later analysis
1387 * @dev: drm device
1388 *
1389 * Should be called when an error is detected (either a hang or an error
1390 * interrupt) to capture error state from the time of the error. Fills
1391 * out a structure which becomes available in debugfs for user level tools
1392 * to pick up.
1393 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001394static void i915_capture_error_state(struct drm_device *dev)
1395{
1396 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00001397 struct drm_i915_gem_object *obj;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001398 struct drm_i915_error_state *error;
1399 unsigned long flags;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001400 int i, pipe;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001401
Daniel Vetter99584db2012-11-14 17:14:04 +01001402 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1403 error = dev_priv->gpu_error.first_error;
1404 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001405 if (error)
1406 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001407
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001408 /* Account for pipe specific data like PIPE*STAT */
Daniel Vetter33f3f512011-12-14 13:57:39 +01001409 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001410 if (!error) {
Chris Wilson9df30792010-02-18 10:24:56 +00001411 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1412 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001413 }
1414
Paulo Zanoni5d83d292013-03-06 20:03:22 -03001415 DRM_INFO("capturing error event; look for more information in "
Ben Widawsky2f86f192013-01-28 15:32:15 -08001416 "/sys/kernel/debug/dri/%d/i915_error_state\n",
Chris Wilsonb6f78332011-02-01 14:15:55 +00001417 dev->primary->index);
Chris Wilson2fa772f2010-10-01 13:23:27 +01001418
Daniel Vetter742cbee2012-04-27 15:17:39 +02001419 kref_init(&error->ref);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001420 error->eir = I915_READ(EIR);
1421 error->pgtbl_er = I915_READ(PGTBL_ER);
Ben Widawsky211816e2013-02-24 18:10:01 -08001422 if (HAS_HW_CONTEXTS(dev))
1423 error->ccid = I915_READ(CCID);
Ben Widawskybe998e22012-04-26 16:03:00 -07001424
1425 if (HAS_PCH_SPLIT(dev))
1426 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1427 else if (IS_VALLEYVIEW(dev))
1428 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1429 else if (IS_GEN2(dev))
1430 error->ier = I915_READ16(IER);
1431 else
1432 error->ier = I915_READ(IER);
1433
Chris Wilson0f3b6842013-01-15 12:05:55 +00001434 if (INTEL_INFO(dev)->gen >= 6)
1435 error->derrmr = I915_READ(DERRMR);
1436
1437 if (IS_VALLEYVIEW(dev))
1438 error->forcewake = I915_READ(FORCEWAKE_VLV);
1439 else if (INTEL_INFO(dev)->gen >= 7)
1440 error->forcewake = I915_READ(FORCEWAKE_MT);
1441 else if (INTEL_INFO(dev)->gen == 6)
1442 error->forcewake = I915_READ(FORCEWAKE);
1443
Paulo Zanoni4f3308b2013-03-22 14:24:16 -03001444 if (!HAS_PCH_SPLIT(dev))
1445 for_each_pipe(pipe)
1446 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001447
Daniel Vetter33f3f512011-12-14 13:57:39 +01001448 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilsonf4068392010-10-27 20:36:41 +01001449 error->error = I915_READ(ERROR_GEN6);
Daniel Vetter33f3f512011-12-14 13:57:39 +01001450 error->done_reg = I915_READ(DONE_REG);
1451 }
Chris Wilsonadd354d2010-10-29 19:00:51 +01001452
Ben Widawsky71e172e2012-08-20 16:15:13 -07001453 if (INTEL_INFO(dev)->gen == 7)
1454 error->err_int = I915_READ(GEN7_ERR_INT);
1455
Ben Widawsky050ee912012-08-22 11:32:15 -07001456 i915_get_extra_instdone(dev, error->extra_instdone);
1457
Chris Wilson748ebc62010-10-24 10:28:47 +01001458 i915_gem_record_fences(dev, error);
Chris Wilson52d39a22012-02-15 11:25:37 +00001459 i915_gem_record_rings(dev, error);
Chris Wilson9df30792010-02-18 10:24:56 +00001460
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001461 /* Record buffers on the active and pinned lists. */
Chris Wilson9df30792010-02-18 10:24:56 +00001462 error->active_bo = NULL;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001463 error->pinned_bo = NULL;
Chris Wilson9df30792010-02-18 10:24:56 +00001464
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001465 i = 0;
1466 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1467 i++;
1468 error->active_bo_count = i;
Chris Wilson6c085a72012-08-20 11:40:46 +02001469 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
Chris Wilson1b502472012-04-24 15:47:30 +01001470 if (obj->pin_count)
1471 i++;
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001472 error->pinned_bo_count = i - error->active_bo_count;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001473
Chris Wilson8e934db2011-01-24 12:34:00 +00001474 error->active_bo = NULL;
1475 error->pinned_bo = NULL;
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001476 if (i) {
1477 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
Chris Wilson9df30792010-02-18 10:24:56 +00001478 GFP_ATOMIC);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001479 if (error->active_bo)
1480 error->pinned_bo =
1481 error->active_bo + error->active_bo_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001482 }
1483
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001484 if (error->active_bo)
1485 error->active_bo_count =
Chris Wilson1b502472012-04-24 15:47:30 +01001486 capture_active_bo(error->active_bo,
1487 error->active_bo_count,
1488 &dev_priv->mm.active_list);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001489
1490 if (error->pinned_bo)
1491 error->pinned_bo_count =
Chris Wilson1b502472012-04-24 15:47:30 +01001492 capture_pinned_bo(error->pinned_bo,
1493 error->pinned_bo_count,
Chris Wilson6c085a72012-08-20 11:40:46 +02001494 &dev_priv->mm.bound_list);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001495
Jesse Barnes8a905232009-07-11 16:48:03 -04001496 do_gettimeofday(&error->time);
1497
Chris Wilson6ef3d422010-08-04 20:26:07 +01001498 error->overlay = intel_overlay_capture_error_state(dev);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00001499 error->display = intel_display_capture_error_state(dev);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001500
Daniel Vetter99584db2012-11-14 17:14:04 +01001501 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1502 if (dev_priv->gpu_error.first_error == NULL) {
1503 dev_priv->gpu_error.first_error = error;
Chris Wilson9df30792010-02-18 10:24:56 +00001504 error = NULL;
1505 }
Daniel Vetter99584db2012-11-14 17:14:04 +01001506 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001507
1508 if (error)
Daniel Vetter742cbee2012-04-27 15:17:39 +02001509 i915_error_state_free(&error->ref);
Chris Wilson9df30792010-02-18 10:24:56 +00001510}
1511
1512void i915_destroy_error_state(struct drm_device *dev)
1513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 struct drm_i915_error_state *error;
Ben Widawsky6dc0e812012-01-23 15:30:02 -08001516 unsigned long flags;
Chris Wilson9df30792010-02-18 10:24:56 +00001517
Daniel Vetter99584db2012-11-14 17:14:04 +01001518 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1519 error = dev_priv->gpu_error.first_error;
1520 dev_priv->gpu_error.first_error = NULL;
1521 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001522
1523 if (error)
Daniel Vetter742cbee2012-04-27 15:17:39 +02001524 kref_put(&error->ref, i915_error_state_free);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001525}
Chris Wilson3bd3c932010-08-19 08:19:30 +01001526#else
1527#define i915_capture_error_state(x)
1528#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001529
Chris Wilson35aed2e2010-05-27 13:18:12 +01001530static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04001531{
1532 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07001533 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04001534 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07001535 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04001536
Chris Wilson35aed2e2010-05-27 13:18:12 +01001537 if (!eir)
1538 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04001539
Joe Perchesa70491c2012-03-18 13:00:11 -07001540 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04001541
Ben Widawskybd9854f2012-08-23 15:18:09 -07001542 i915_get_extra_instdone(dev, instdone);
1543
Jesse Barnes8a905232009-07-11 16:48:03 -04001544 if (IS_G4X(dev)) {
1545 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1546 u32 ipeir = I915_READ(IPEIR_I965);
1547
Joe Perchesa70491c2012-03-18 13:00:11 -07001548 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1549 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07001550 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1551 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07001552 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001553 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001554 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001555 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001556 }
1557 if (eir & GM45_ERROR_PAGE_TABLE) {
1558 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001559 pr_err("page table error\n");
1560 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001561 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001562 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001563 }
1564 }
1565
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001566 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001567 if (eir & I915_ERROR_PAGE_TABLE) {
1568 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001569 pr_err("page table error\n");
1570 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001571 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001572 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001573 }
1574 }
1575
1576 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001577 pr_err("memory refresh error:\n");
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001578 for_each_pipe(pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07001579 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001580 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04001581 /* pipestat has already been acked */
1582 }
1583 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001584 pr_err("instruction error\n");
1585 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07001586 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1587 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001588 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001589 u32 ipeir = I915_READ(IPEIR);
1590
Joe Perchesa70491c2012-03-18 13:00:11 -07001591 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1592 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07001593 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04001594 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001595 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001596 } else {
1597 u32 ipeir = I915_READ(IPEIR_I965);
1598
Joe Perchesa70491c2012-03-18 13:00:11 -07001599 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1600 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07001601 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001602 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001603 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001604 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001605 }
1606 }
1607
1608 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001609 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001610 eir = I915_READ(EIR);
1611 if (eir) {
1612 /*
1613 * some errors might have become stuck,
1614 * mask them.
1615 */
1616 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1617 I915_WRITE(EMR, I915_READ(EMR) | eir);
1618 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1619 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01001620}
1621
1622/**
1623 * i915_handle_error - handle an error interrupt
1624 * @dev: drm device
1625 *
1626 * Do some basic checking of regsiter state at error interrupt time and
1627 * dump it to the syslog. Also call i915_capture_error_state() to make
1628 * sure we get a record and make it available in debugfs. Fire a uevent
1629 * so userspace knows something bad happened (should trigger collection
1630 * of a ring dump etc.).
1631 */
Chris Wilson527f9e92010-11-11 01:16:58 +00001632void i915_handle_error(struct drm_device *dev, bool wedged)
Chris Wilson35aed2e2010-05-27 13:18:12 +01001633{
1634 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb4519512012-05-11 14:29:30 +01001635 struct intel_ring_buffer *ring;
1636 int i;
Chris Wilson35aed2e2010-05-27 13:18:12 +01001637
1638 i915_capture_error_state(dev);
1639 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04001640
Ben Gamariba1234d2009-09-14 17:48:47 -04001641 if (wedged) {
Daniel Vetterf69061b2012-12-06 09:01:42 +01001642 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1643 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04001644
Ben Gamari11ed50e2009-09-14 17:48:45 -04001645 /*
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001646 * Wakeup waiting processes so that the reset work item
1647 * doesn't deadlock trying to grab various locks.
Ben Gamari11ed50e2009-09-14 17:48:45 -04001648 */
Chris Wilsonb4519512012-05-11 14:29:30 +01001649 for_each_ring(ring, dev_priv, i)
1650 wake_up_all(&ring->irq_queue);
Ben Gamari11ed50e2009-09-14 17:48:45 -04001651 }
1652
Daniel Vetter99584db2012-11-14 17:14:04 +01001653 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
Jesse Barnes8a905232009-07-11 16:48:03 -04001654}
1655
Ville Syrjälä21ad8332013-02-19 15:16:39 +02001656static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001657{
1658 drm_i915_private_t *dev_priv = dev->dev_private;
1659 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00001661 struct drm_i915_gem_object *obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001662 struct intel_unpin_work *work;
1663 unsigned long flags;
1664 bool stall_detected;
1665
1666 /* Ignore early vblank irqs */
1667 if (intel_crtc == NULL)
1668 return;
1669
1670 spin_lock_irqsave(&dev->event_lock, flags);
1671 work = intel_crtc->unpin_work;
1672
Chris Wilsone7d841c2012-12-03 11:36:30 +00001673 if (work == NULL ||
1674 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1675 !work->enable_stall_check) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001676 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1677 spin_unlock_irqrestore(&dev->event_lock, flags);
1678 return;
1679 }
1680
1681 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
Chris Wilson05394f32010-11-08 19:18:58 +00001682 obj = work->pending_flip_obj;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001683 if (INTEL_INFO(dev)->gen >= 4) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001684 int dspsurf = DSPSURF(intel_crtc->plane);
Armin Reese446f2542012-03-30 16:20:16 -07001685 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1686 obj->gtt_offset;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001687 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001688 int dspaddr = DSPADDR(intel_crtc->plane);
Chris Wilson05394f32010-11-08 19:18:58 +00001689 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
Ville Syrjälä01f2c772011-12-20 00:06:49 +02001690 crtc->y * crtc->fb->pitches[0] +
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001691 crtc->x * crtc->fb->bits_per_pixel/8);
1692 }
1693
1694 spin_unlock_irqrestore(&dev->event_lock, flags);
1695
1696 if (stall_detected) {
1697 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1698 intel_prepare_page_flip(dev, intel_crtc->plane);
1699 }
1700}
1701
Keith Packard42f52ef2008-10-18 19:39:29 -07001702/* Called from drm generic code, passed 'crtc' which
1703 * we use as a pipe index
1704 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001705static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001706{
1707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001708 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001709
Chris Wilson5eddb702010-09-11 13:48:45 +01001710 if (!i915_pipe_enabled(dev, pipe))
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001711 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001712
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001713 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07001714 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08001715 i915_enable_pipestat(dev_priv, pipe,
1716 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001717 else
Keith Packard7c463582008-11-04 02:03:27 -08001718 i915_enable_pipestat(dev_priv, pipe,
1719 PIPE_VBLANK_INTERRUPT_ENABLE);
Chris Wilson8692d00e2011-02-05 10:08:21 +00001720
1721 /* maintain vblank delivery even in deep C-states */
1722 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02001723 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00001725
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001726 return 0;
1727}
1728
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001729static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07001730{
1731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1732 unsigned long irqflags;
1733
1734 if (!i915_pipe_enabled(dev, pipe))
1735 return -EINVAL;
1736
1737 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1738 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
Akshay Joshi0206e352011-08-16 15:34:10 -04001739 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
Jesse Barnesf796cf82011-04-07 13:58:17 -07001740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1741
1742 return 0;
1743}
1744
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001745static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001746{
1747 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1748 unsigned long irqflags;
1749
1750 if (!i915_pipe_enabled(dev, pipe))
1751 return -EINVAL;
1752
1753 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilsonb615b572012-05-02 09:52:12 +01001754 ironlake_enable_display_irq(dev_priv,
1755 DE_PIPEA_VBLANK_IVB << (5 * pipe));
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001756 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1757
1758 return 0;
1759}
1760
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001761static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1762{
1763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1764 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001765 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001766
1767 if (!i915_pipe_enabled(dev, pipe))
1768 return -EINVAL;
1769
1770 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001771 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001772 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001773 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001774 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001775 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001776 I915_WRITE(VLV_IMR, imr);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001777 i915_enable_pipestat(dev_priv, pipe,
1778 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001779 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1780
1781 return 0;
1782}
1783
Keith Packard42f52ef2008-10-18 19:39:29 -07001784/* Called from drm generic code, passed 'crtc' which
1785 * we use as a pipe index
1786 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001787static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001788{
1789 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001790 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001791
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001792 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00001793 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02001794 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson8692d00e2011-02-05 10:08:21 +00001795
Jesse Barnesf796cf82011-04-07 13:58:17 -07001796 i915_disable_pipestat(dev_priv, pipe,
1797 PIPE_VBLANK_INTERRUPT_ENABLE |
1798 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1799 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1800}
1801
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001802static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07001803{
1804 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1805 unsigned long irqflags;
1806
1807 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1808 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
Akshay Joshi0206e352011-08-16 15:34:10 -04001809 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001810 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001811}
1812
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001813static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001814{
1815 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1816 unsigned long irqflags;
1817
1818 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilsonb615b572012-05-02 09:52:12 +01001819 ironlake_disable_display_irq(dev_priv,
1820 DE_PIPEA_VBLANK_IVB << (pipe * 5));
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001821 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1822}
1823
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001824static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1825{
1826 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1827 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001828 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001829
1830 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001831 i915_disable_pipestat(dev_priv, pipe,
1832 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001833 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001834 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001835 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001836 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001837 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001838 I915_WRITE(VLV_IMR, imr);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001839 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1840}
1841
Chris Wilson893eead2010-10-27 14:44:35 +01001842static u32
1843ring_last_seqno(struct intel_ring_buffer *ring)
Zou Nan hai852835f2010-05-21 09:08:56 +08001844{
Chris Wilson893eead2010-10-27 14:44:35 +01001845 return list_entry(ring->request_list.prev,
1846 struct drm_i915_gem_request, list)->seqno;
1847}
1848
1849static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1850{
1851 if (list_empty(&ring->request_list) ||
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01001852 i915_seqno_passed(ring->get_seqno(ring, false),
1853 ring_last_seqno(ring))) {
Chris Wilson893eead2010-10-27 14:44:35 +01001854 /* Issue a wake-up to catch stuck h/w. */
Ben Widawsky9574b3f2012-04-26 16:03:01 -07001855 if (waitqueue_active(&ring->irq_queue)) {
1856 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1857 ring->name);
Chris Wilson893eead2010-10-27 14:44:35 +01001858 wake_up_all(&ring->irq_queue);
1859 *err = true;
1860 }
1861 return true;
1862 }
1863 return false;
Ben Gamarif65d9422009-09-14 17:48:44 -04001864}
1865
Chris Wilsona24a11e2013-03-14 17:52:05 +02001866static bool semaphore_passed(struct intel_ring_buffer *ring)
1867{
1868 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1869 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1870 struct intel_ring_buffer *signaller;
1871 u32 cmd, ipehr, acthd_min;
1872
1873 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1874 if ((ipehr & ~(0x3 << 16)) !=
1875 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1876 return false;
1877
1878 /* ACTHD is likely pointing to the dword after the actual command,
1879 * so scan backwards until we find the MBOX.
1880 */
1881 acthd_min = max((int)acthd - 3 * 4, 0);
1882 do {
1883 cmd = ioread32(ring->virtual_start + acthd);
1884 if (cmd == ipehr)
1885 break;
1886
1887 acthd -= 4;
1888 if (acthd < acthd_min)
1889 return false;
1890 } while (1);
1891
1892 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1893 return i915_seqno_passed(signaller->get_seqno(signaller, false),
1894 ioread32(ring->virtual_start+acthd+4)+1);
1895}
1896
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001897static bool kick_ring(struct intel_ring_buffer *ring)
1898{
1899 struct drm_device *dev = ring->dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 u32 tmp = I915_READ_CTL(ring);
1902 if (tmp & RING_WAIT) {
1903 DRM_ERROR("Kicking stuck wait on %s\n",
1904 ring->name);
1905 I915_WRITE_CTL(ring, tmp);
1906 return true;
1907 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02001908
1909 if (INTEL_INFO(dev)->gen >= 6 &&
1910 tmp & RING_WAIT_SEMAPHORE &&
1911 semaphore_passed(ring)) {
1912 DRM_ERROR("Kicking stuck semaphore on %s\n",
1913 ring->name);
1914 I915_WRITE_CTL(ring, tmp);
1915 return true;
1916 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001917 return false;
1918}
1919
Chris Wilsond1e61e72012-04-10 17:00:41 +01001920static bool i915_hangcheck_hung(struct drm_device *dev)
1921{
1922 drm_i915_private_t *dev_priv = dev->dev_private;
1923
Daniel Vetter99584db2012-11-14 17:14:04 +01001924 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
Chris Wilsonb4519512012-05-11 14:29:30 +01001925 bool hung = true;
1926
Chris Wilsond1e61e72012-04-10 17:00:41 +01001927 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1928 i915_handle_error(dev, true);
1929
1930 if (!IS_GEN2(dev)) {
Chris Wilsonb4519512012-05-11 14:29:30 +01001931 struct intel_ring_buffer *ring;
1932 int i;
1933
Chris Wilsond1e61e72012-04-10 17:00:41 +01001934 /* Is the chip hanging on a WAIT_FOR_EVENT?
1935 * If so we can simply poke the RB_WAIT bit
1936 * and break the hang. This should work on
1937 * all but the second generation chipsets.
1938 */
Chris Wilsonb4519512012-05-11 14:29:30 +01001939 for_each_ring(ring, dev_priv, i)
1940 hung &= !kick_ring(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01001941 }
1942
Chris Wilsonb4519512012-05-11 14:29:30 +01001943 return hung;
Chris Wilsond1e61e72012-04-10 17:00:41 +01001944 }
1945
1946 return false;
1947}
1948
Ben Gamarif65d9422009-09-14 17:48:44 -04001949/**
1950 * This is called when the chip hasn't reported back with completed
1951 * batchbuffers in a long time. The first time this is called we simply record
1952 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1953 * again, we assume the chip is wedged and try to fix it.
1954 */
1955void i915_hangcheck_elapsed(unsigned long data)
1956{
1957 struct drm_device *dev = (struct drm_device *)data;
1958 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07001959 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
Chris Wilsonb4519512012-05-11 14:29:30 +01001960 struct intel_ring_buffer *ring;
1961 bool err = false, idle;
1962 int i;
Chris Wilson893eead2010-10-27 14:44:35 +01001963
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07001964 if (!i915_enable_hangcheck)
1965 return;
1966
Chris Wilsonb4519512012-05-11 14:29:30 +01001967 memset(acthd, 0, sizeof(acthd));
1968 idle = true;
1969 for_each_ring(ring, dev_priv, i) {
1970 idle &= i915_hangcheck_ring_idle(ring, &err);
1971 acthd[i] = intel_ring_get_active_head(ring);
1972 }
1973
Chris Wilson893eead2010-10-27 14:44:35 +01001974 /* If all work is done then ACTHD clearly hasn't advanced. */
Chris Wilsonb4519512012-05-11 14:29:30 +01001975 if (idle) {
Chris Wilsond1e61e72012-04-10 17:00:41 +01001976 if (err) {
1977 if (i915_hangcheck_hung(dev))
1978 return;
1979
Chris Wilson893eead2010-10-27 14:44:35 +01001980 goto repeat;
Chris Wilsond1e61e72012-04-10 17:00:41 +01001981 }
1982
Daniel Vetter99584db2012-11-14 17:14:04 +01001983 dev_priv->gpu_error.hangcheck_count = 0;
Chris Wilson893eead2010-10-27 14:44:35 +01001984 return;
1985 }
Eric Anholtb9201c12010-01-08 14:25:16 -08001986
Ben Widawskybd9854f2012-08-23 15:18:09 -07001987 i915_get_extra_instdone(dev, instdone);
Daniel Vetter99584db2012-11-14 17:14:04 +01001988 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1989 sizeof(acthd)) == 0 &&
1990 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1991 sizeof(instdone)) == 0) {
Chris Wilsond1e61e72012-04-10 17:00:41 +01001992 if (i915_hangcheck_hung(dev))
Chris Wilsoncbb465e2010-06-06 12:16:24 +01001993 return;
Chris Wilsoncbb465e2010-06-06 12:16:24 +01001994 } else {
Daniel Vetter99584db2012-11-14 17:14:04 +01001995 dev_priv->gpu_error.hangcheck_count = 0;
Chris Wilsoncbb465e2010-06-06 12:16:24 +01001996
Daniel Vetter99584db2012-11-14 17:14:04 +01001997 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1998 sizeof(acthd));
1999 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2000 sizeof(instdone));
Chris Wilsoncbb465e2010-06-06 12:16:24 +01002001 }
Ben Gamarif65d9422009-09-14 17:48:44 -04002002
Chris Wilson893eead2010-10-27 14:44:35 +01002003repeat:
Ben Gamarif65d9422009-09-14 17:48:44 -04002004 /* Reset timer case chip hangs without another request being added */
Daniel Vetter99584db2012-11-14 17:14:04 +01002005 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
Chris Wilsoncecc21f2012-10-05 17:02:56 +01002006 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04002007}
2008
Linus Torvalds1da177e2005-04-16 15:20:36 -07002009/* drm_dma.h hooks
2010*/
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002011static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002012{
2013 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2014
Jesse Barnes46979952011-04-07 13:53:55 -07002015 atomic_set(&dev_priv->irq_received, 0);
2016
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002017 I915_WRITE(HWSTAM, 0xeffe);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01002018
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002019 /* XXX hotplug from PCH */
2020
2021 I915_WRITE(DEIMR, 0xffffffff);
2022 I915_WRITE(DEIER, 0x0);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002023 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002024
2025 /* and GT */
2026 I915_WRITE(GTIMR, 0xffffffff);
2027 I915_WRITE(GTIER, 0x0);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002028 POSTING_READ(GTIER);
Zhenyu Wangc6501562009-11-03 18:57:21 +00002029
2030 /* south display irq */
2031 I915_WRITE(SDEIMR, 0xffffffff);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002032 /*
2033 * SDEIER is also touched by the interrupt handler to work around missed
2034 * PCH interrupts. Hence we can't update it after the interrupt handler
2035 * is enabled - instead we unconditionally enable all PCH interrupt
2036 * sources here, but then only unmask them as needed with SDEIMR.
2037 */
2038 I915_WRITE(SDEIER, 0xffffffff);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002039 POSTING_READ(SDEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002040}
2041
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002042static void valleyview_irq_preinstall(struct drm_device *dev)
2043{
2044 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2045 int pipe;
2046
2047 atomic_set(&dev_priv->irq_received, 0);
2048
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002049 /* VLV magic */
2050 I915_WRITE(VLV_IMR, 0);
2051 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2052 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2053 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2054
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002055 /* and GT */
2056 I915_WRITE(GTIIR, I915_READ(GTIIR));
2057 I915_WRITE(GTIIR, I915_READ(GTIIR));
2058 I915_WRITE(GTIMR, 0xffffffff);
2059 I915_WRITE(GTIER, 0x0);
2060 POSTING_READ(GTIER);
2061
2062 I915_WRITE(DPINVGTT, 0xff);
2063
2064 I915_WRITE(PORT_HOTPLUG_EN, 0);
2065 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2066 for_each_pipe(pipe)
2067 I915_WRITE(PIPESTAT(pipe), 0xffff);
2068 I915_WRITE(VLV_IIR, 0xffffffff);
2069 I915_WRITE(VLV_IMR, 0xffffffff);
2070 I915_WRITE(VLV_IER, 0x0);
2071 POSTING_READ(VLV_IER);
2072}
2073
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002074static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07002075{
2076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002077 struct drm_mode_config *mode_config = &dev->mode_config;
2078 struct intel_encoder *intel_encoder;
2079 u32 mask = ~I915_READ(SDEIMR);
2080 u32 hotplug;
Keith Packard7fe0b972011-09-19 13:31:02 -07002081
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002082 if (HAS_PCH_IBX(dev)) {
2083 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2084 mask |= hpd_ibx[intel_encoder->hpd_pin];
2085 } else {
2086 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2087 mask |= hpd_cpt[intel_encoder->hpd_pin];
2088 }
2089
2090 I915_WRITE(SDEIMR, ~mask);
2091
2092 /*
2093 * Enable digital hotplug on the PCH, and configure the DP short pulse
2094 * duration to 2ms (which is the minimum in the Display Port spec)
2095 *
2096 * This register is the same on all known PCH chips.
2097 */
Keith Packard7fe0b972011-09-19 13:31:02 -07002098 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2099 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2100 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2101 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2102 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2103 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2104}
2105
Paulo Zanonid46da432013-02-08 17:35:15 -02002106static void ibx_irq_postinstall(struct drm_device *dev)
2107{
2108 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002109 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02002110
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002111 if (HAS_PCH_IBX(dev))
2112 mask = SDE_GMBUS | SDE_AUX_MASK;
2113 else
2114 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
Paulo Zanonid46da432013-02-08 17:35:15 -02002115 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2116 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02002117}
2118
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002119static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002120{
2121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2122 /* enable kind of interrupts always enabled */
Jesse Barnes013d5aa2010-01-29 11:18:31 -08002123 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
Daniel Vetterce99c252012-12-01 13:53:47 +01002124 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2125 DE_AUX_CHANNEL_A;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002126 u32 render_irqs;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002127
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002128 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002129
2130 /* should always can generate irq */
2131 I915_WRITE(DEIIR, I915_READ(DEIIR));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002132 I915_WRITE(DEIMR, dev_priv->irq_mask);
2133 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002134 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002135
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002136 dev_priv->gt_irq_mask = ~0;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002137
2138 I915_WRITE(GTIIR, I915_READ(GTIIR));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002139 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002140
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002141 if (IS_GEN6(dev))
2142 render_irqs =
2143 GT_USER_INTERRUPT |
Ben Widawskye2a1e2f2012-03-29 19:11:26 -07002144 GEN6_BSD_USER_INTERRUPT |
2145 GEN6_BLITTER_USER_INTERRUPT;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002146 else
2147 render_irqs =
Chris Wilson88f23b82010-12-05 15:08:31 +00002148 GT_USER_INTERRUPT |
Chris Wilsonc6df5412010-12-15 09:56:50 +00002149 GT_PIPE_NOTIFY |
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002150 GT_BSD_USER_INTERRUPT;
2151 I915_WRITE(GTIER, render_irqs);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002152 POSTING_READ(GTIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002153
Paulo Zanonid46da432013-02-08 17:35:15 -02002154 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07002155
Jesse Barnesf97108d2010-01-29 11:27:07 -08002156 if (IS_IRONLAKE_M(dev)) {
2157 /* Clear & enable PCU event interrupts */
2158 I915_WRITE(DEIIR, DE_PCU_EVENT);
2159 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2160 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2161 }
2162
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002163 return 0;
2164}
2165
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002166static int ivybridge_irq_postinstall(struct drm_device *dev)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002167{
2168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2169 /* enable kind of interrupts always enabled */
Chris Wilsonb615b572012-05-02 09:52:12 +01002170 u32 display_mask =
2171 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2172 DE_PLANEC_FLIP_DONE_IVB |
2173 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetterce99c252012-12-01 13:53:47 +01002174 DE_PLANEA_FLIP_DONE_IVB |
2175 DE_AUX_CHANNEL_A_IVB;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002176 u32 render_irqs;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002177
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002178 dev_priv->irq_mask = ~display_mask;
2179
2180 /* should always can generate irq */
2181 I915_WRITE(DEIIR, I915_READ(DEIIR));
2182 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilsonb615b572012-05-02 09:52:12 +01002183 I915_WRITE(DEIER,
2184 display_mask |
2185 DE_PIPEC_VBLANK_IVB |
2186 DE_PIPEB_VBLANK_IVB |
2187 DE_PIPEA_VBLANK_IVB);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002188 POSTING_READ(DEIER);
2189
Ben Widawsky15b9f802012-05-25 16:56:23 -07002190 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002191
2192 I915_WRITE(GTIIR, I915_READ(GTIIR));
2193 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2194
Ben Widawskye2a1e2f2012-03-29 19:11:26 -07002195 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
Ben Widawsky15b9f802012-05-25 16:56:23 -07002196 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002197 I915_WRITE(GTIER, render_irqs);
2198 POSTING_READ(GTIER);
2199
Paulo Zanonid46da432013-02-08 17:35:15 -02002200 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07002201
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002202 return 0;
2203}
2204
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002205static int valleyview_irq_postinstall(struct drm_device *dev)
2206{
2207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002208 u32 enable_mask;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002209 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
Jesse Barnes3bcedbe2012-09-19 13:29:01 -07002210 u32 render_irqs;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002211 u16 msid;
2212
2213 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002214 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2215 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2216 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002217 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2218
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002219 /*
2220 *Leave vblank interrupts masked initially. enable/disable will
2221 * toggle them based on usage.
2222 */
2223 dev_priv->irq_mask = (~enable_mask) |
2224 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2225 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002226
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002227 /* Hack for broken MSIs on VLV */
2228 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2229 pci_read_config_word(dev->pdev, 0x98, &msid);
2230 msid &= 0xff; /* mask out delivery bits */
2231 msid |= (1<<14);
2232 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2233
Daniel Vetter20afbda2012-12-11 14:05:07 +01002234 I915_WRITE(PORT_HOTPLUG_EN, 0);
2235 POSTING_READ(PORT_HOTPLUG_EN);
2236
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002237 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2238 I915_WRITE(VLV_IER, enable_mask);
2239 I915_WRITE(VLV_IIR, 0xffffffff);
2240 I915_WRITE(PIPESTAT(0), 0xffff);
2241 I915_WRITE(PIPESTAT(1), 0xffff);
2242 POSTING_READ(VLV_IER);
2243
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002244 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002245 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002246 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2247
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002248 I915_WRITE(VLV_IIR, 0xffffffff);
2249 I915_WRITE(VLV_IIR, 0xffffffff);
2250
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002251 I915_WRITE(GTIIR, I915_READ(GTIIR));
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002252 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
Jesse Barnes3bcedbe2012-09-19 13:29:01 -07002253
2254 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2255 GEN6_BLITTER_USER_INTERRUPT;
2256 I915_WRITE(GTIER, render_irqs);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002257 POSTING_READ(GTIER);
2258
2259 /* ack & enable invalid PTE error interrupts */
2260#if 0 /* FIXME: add support to irq handler for checking these bits */
2261 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2262 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2263#endif
2264
2265 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01002266
2267 return 0;
2268}
2269
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002270static void valleyview_irq_uninstall(struct drm_device *dev)
2271{
2272 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273 int pipe;
2274
2275 if (!dev_priv)
2276 return;
2277
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002278 for_each_pipe(pipe)
2279 I915_WRITE(PIPESTAT(pipe), 0xffff);
2280
2281 I915_WRITE(HWSTAM, 0xffffffff);
2282 I915_WRITE(PORT_HOTPLUG_EN, 0);
2283 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2284 for_each_pipe(pipe)
2285 I915_WRITE(PIPESTAT(pipe), 0xffff);
2286 I915_WRITE(VLV_IIR, 0xffffffff);
2287 I915_WRITE(VLV_IMR, 0xffffffff);
2288 I915_WRITE(VLV_IER, 0x0);
2289 POSTING_READ(VLV_IER);
2290}
2291
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002292static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002293{
2294 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07002295
2296 if (!dev_priv)
2297 return;
2298
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002299 I915_WRITE(HWSTAM, 0xffffffff);
2300
2301 I915_WRITE(DEIMR, 0xffffffff);
2302 I915_WRITE(DEIER, 0x0);
2303 I915_WRITE(DEIIR, I915_READ(DEIIR));
2304
2305 I915_WRITE(GTIMR, 0xffffffff);
2306 I915_WRITE(GTIER, 0x0);
2307 I915_WRITE(GTIIR, I915_READ(GTIIR));
Keith Packard192aac1f2011-09-20 10:12:44 -07002308
2309 I915_WRITE(SDEIMR, 0xffffffff);
2310 I915_WRITE(SDEIER, 0x0);
2311 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002312}
2313
Chris Wilsonc2798b12012-04-22 21:13:57 +01002314static void i8xx_irq_preinstall(struct drm_device * dev)
2315{
2316 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2317 int pipe;
2318
2319 atomic_set(&dev_priv->irq_received, 0);
2320
2321 for_each_pipe(pipe)
2322 I915_WRITE(PIPESTAT(pipe), 0);
2323 I915_WRITE16(IMR, 0xffff);
2324 I915_WRITE16(IER, 0x0);
2325 POSTING_READ16(IER);
2326}
2327
2328static int i8xx_irq_postinstall(struct drm_device *dev)
2329{
2330 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2331
Chris Wilsonc2798b12012-04-22 21:13:57 +01002332 I915_WRITE16(EMR,
2333 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2334
2335 /* Unmask the interrupts that we always want on. */
2336 dev_priv->irq_mask =
2337 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2338 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2339 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2340 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2341 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2342 I915_WRITE16(IMR, dev_priv->irq_mask);
2343
2344 I915_WRITE16(IER,
2345 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2346 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2347 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2348 I915_USER_INTERRUPT);
2349 POSTING_READ16(IER);
2350
2351 return 0;
2352}
2353
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002354/*
2355 * Returns true when a page flip has completed.
2356 */
2357static bool i8xx_handle_vblank(struct drm_device *dev,
2358 int pipe, u16 iir)
2359{
2360 drm_i915_private_t *dev_priv = dev->dev_private;
2361 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2362
2363 if (!drm_handle_vblank(dev, pipe))
2364 return false;
2365
2366 if ((iir & flip_pending) == 0)
2367 return false;
2368
2369 intel_prepare_page_flip(dev, pipe);
2370
2371 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2372 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2373 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2374 * the flip is completed (no longer pending). Since this doesn't raise
2375 * an interrupt per se, we watch for the change at vblank.
2376 */
2377 if (I915_READ16(ISR) & flip_pending)
2378 return false;
2379
2380 intel_finish_page_flip(dev, pipe);
2381
2382 return true;
2383}
2384
Daniel Vetterff1f5252012-10-02 15:10:55 +02002385static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01002386{
2387 struct drm_device *dev = (struct drm_device *) arg;
2388 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002389 u16 iir, new_iir;
2390 u32 pipe_stats[2];
2391 unsigned long irqflags;
2392 int irq_received;
2393 int pipe;
2394 u16 flip_mask =
2395 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2396 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2397
2398 atomic_inc(&dev_priv->irq_received);
2399
2400 iir = I915_READ16(IIR);
2401 if (iir == 0)
2402 return IRQ_NONE;
2403
2404 while (iir & ~flip_mask) {
2405 /* Can't rely on pipestat interrupt bit in iir as it might
2406 * have been cleared after the pipestat interrupt was received.
2407 * It doesn't set the bit in iir again, but it still produces
2408 * interrupts (for non-MSI).
2409 */
2410 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2411 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2412 i915_handle_error(dev, false);
2413
2414 for_each_pipe(pipe) {
2415 int reg = PIPESTAT(pipe);
2416 pipe_stats[pipe] = I915_READ(reg);
2417
2418 /*
2419 * Clear the PIPE*STAT regs before the IIR
2420 */
2421 if (pipe_stats[pipe] & 0x8000ffff) {
2422 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2423 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2424 pipe_name(pipe));
2425 I915_WRITE(reg, pipe_stats[pipe]);
2426 irq_received = 1;
2427 }
2428 }
2429 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2430
2431 I915_WRITE16(IIR, iir & ~flip_mask);
2432 new_iir = I915_READ16(IIR); /* Flush posted writes */
2433
Daniel Vetterd05c6172012-04-26 23:28:09 +02002434 i915_update_dri1_breadcrumb(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002435
2436 if (iir & I915_USER_INTERRUPT)
2437 notify_ring(dev, &dev_priv->ring[RCS]);
2438
2439 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002440 i8xx_handle_vblank(dev, 0, iir))
2441 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002442
2443 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002444 i8xx_handle_vblank(dev, 1, iir))
2445 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002446
2447 iir = new_iir;
2448 }
2449
2450 return IRQ_HANDLED;
2451}
2452
2453static void i8xx_irq_uninstall(struct drm_device * dev)
2454{
2455 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2456 int pipe;
2457
Chris Wilsonc2798b12012-04-22 21:13:57 +01002458 for_each_pipe(pipe) {
2459 /* Clear enable bits; then clear status bits */
2460 I915_WRITE(PIPESTAT(pipe), 0);
2461 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2462 }
2463 I915_WRITE16(IMR, 0xffff);
2464 I915_WRITE16(IER, 0x0);
2465 I915_WRITE16(IIR, I915_READ16(IIR));
2466}
2467
Chris Wilsona266c7d2012-04-24 22:59:44 +01002468static void i915_irq_preinstall(struct drm_device * dev)
2469{
2470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2471 int pipe;
2472
2473 atomic_set(&dev_priv->irq_received, 0);
2474
2475 if (I915_HAS_HOTPLUG(dev)) {
2476 I915_WRITE(PORT_HOTPLUG_EN, 0);
2477 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2478 }
2479
Chris Wilson00d98eb2012-04-24 22:59:48 +01002480 I915_WRITE16(HWSTAM, 0xeffe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002481 for_each_pipe(pipe)
2482 I915_WRITE(PIPESTAT(pipe), 0);
2483 I915_WRITE(IMR, 0xffffffff);
2484 I915_WRITE(IER, 0x0);
2485 POSTING_READ(IER);
2486}
2487
2488static int i915_irq_postinstall(struct drm_device *dev)
2489{
2490 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01002491 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002492
Chris Wilson38bde182012-04-24 22:59:50 +01002493 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2494
2495 /* Unmask the interrupts that we always want on. */
2496 dev_priv->irq_mask =
2497 ~(I915_ASLE_INTERRUPT |
2498 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2499 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2500 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2501 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2502 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2503
2504 enable_mask =
2505 I915_ASLE_INTERRUPT |
2506 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2507 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2508 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2509 I915_USER_INTERRUPT;
2510
Chris Wilsona266c7d2012-04-24 22:59:44 +01002511 if (I915_HAS_HOTPLUG(dev)) {
Daniel Vetter20afbda2012-12-11 14:05:07 +01002512 I915_WRITE(PORT_HOTPLUG_EN, 0);
2513 POSTING_READ(PORT_HOTPLUG_EN);
2514
Chris Wilsona266c7d2012-04-24 22:59:44 +01002515 /* Enable in IER... */
2516 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2517 /* and unmask in IMR */
2518 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2519 }
2520
Chris Wilsona266c7d2012-04-24 22:59:44 +01002521 I915_WRITE(IMR, dev_priv->irq_mask);
2522 I915_WRITE(IER, enable_mask);
2523 POSTING_READ(IER);
2524
Daniel Vetter20afbda2012-12-11 14:05:07 +01002525 intel_opregion_enable_asle(dev);
2526
2527 return 0;
2528}
2529
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002530/*
2531 * Returns true when a page flip has completed.
2532 */
2533static bool i915_handle_vblank(struct drm_device *dev,
2534 int plane, int pipe, u32 iir)
2535{
2536 drm_i915_private_t *dev_priv = dev->dev_private;
2537 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2538
2539 if (!drm_handle_vblank(dev, pipe))
2540 return false;
2541
2542 if ((iir & flip_pending) == 0)
2543 return false;
2544
2545 intel_prepare_page_flip(dev, plane);
2546
2547 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2548 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2549 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2550 * the flip is completed (no longer pending). Since this doesn't raise
2551 * an interrupt per se, we watch for the change at vblank.
2552 */
2553 if (I915_READ(ISR) & flip_pending)
2554 return false;
2555
2556 intel_finish_page_flip(dev, pipe);
2557
2558 return true;
2559}
2560
Daniel Vetterff1f5252012-10-02 15:10:55 +02002561static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01002562{
2563 struct drm_device *dev = (struct drm_device *) arg;
2564 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01002565 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01002566 unsigned long irqflags;
Chris Wilson38bde182012-04-24 22:59:50 +01002567 u32 flip_mask =
2568 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2569 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01002570 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002571
2572 atomic_inc(&dev_priv->irq_received);
2573
2574 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01002575 do {
2576 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01002577 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002578
2579 /* Can't rely on pipestat interrupt bit in iir as it might
2580 * have been cleared after the pipestat interrupt was received.
2581 * It doesn't set the bit in iir again, but it still produces
2582 * interrupts (for non-MSI).
2583 */
2584 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2585 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2586 i915_handle_error(dev, false);
2587
2588 for_each_pipe(pipe) {
2589 int reg = PIPESTAT(pipe);
2590 pipe_stats[pipe] = I915_READ(reg);
2591
Chris Wilson38bde182012-04-24 22:59:50 +01002592 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01002593 if (pipe_stats[pipe] & 0x8000ffff) {
2594 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2595 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2596 pipe_name(pipe));
2597 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01002598 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002599 }
2600 }
2601 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2602
2603 if (!irq_received)
2604 break;
2605
Chris Wilsona266c7d2012-04-24 22:59:44 +01002606 /* Consume port. Then clear IIR or we'll miss events */
2607 if ((I915_HAS_HOTPLUG(dev)) &&
2608 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2609 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2610
2611 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2612 hotplug_status);
Egbert Eiche5868a32013-02-28 04:17:12 -05002613 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
Chris Wilsona266c7d2012-04-24 22:59:44 +01002614 queue_work(dev_priv->wq,
2615 &dev_priv->hotplug_work);
2616
2617 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
Chris Wilson38bde182012-04-24 22:59:50 +01002618 POSTING_READ(PORT_HOTPLUG_STAT);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002619 }
2620
Chris Wilson38bde182012-04-24 22:59:50 +01002621 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002622 new_iir = I915_READ(IIR); /* Flush posted writes */
2623
Chris Wilsona266c7d2012-04-24 22:59:44 +01002624 if (iir & I915_USER_INTERRUPT)
2625 notify_ring(dev, &dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002626
Chris Wilsona266c7d2012-04-24 22:59:44 +01002627 for_each_pipe(pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01002628 int plane = pipe;
2629 if (IS_MOBILE(dev))
2630 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02002631
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002632 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2633 i915_handle_vblank(dev, plane, pipe, iir))
2634 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002635
2636 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2637 blc_event = true;
2638 }
2639
Chris Wilsona266c7d2012-04-24 22:59:44 +01002640 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2641 intel_opregion_asle_intr(dev);
2642
2643 /* With MSI, interrupts are only generated when iir
2644 * transitions from zero to nonzero. If another bit got
2645 * set while we were handling the existing iir bits, then
2646 * we would never get another interrupt.
2647 *
2648 * This is fine on non-MSI as well, as if we hit this path
2649 * we avoid exiting the interrupt handler only to generate
2650 * another one.
2651 *
2652 * Note that for MSI this could cause a stray interrupt report
2653 * if an interrupt landed in the time between writing IIR and
2654 * the posting read. This should be rare enough to never
2655 * trigger the 99% of 100,000 interrupts test for disabling
2656 * stray interrupts.
2657 */
Chris Wilson38bde182012-04-24 22:59:50 +01002658 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002659 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01002660 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002661
Daniel Vetterd05c6172012-04-26 23:28:09 +02002662 i915_update_dri1_breadcrumb(dev);
Chris Wilson8291ee92012-04-24 22:59:47 +01002663
Chris Wilsona266c7d2012-04-24 22:59:44 +01002664 return ret;
2665}
2666
2667static void i915_irq_uninstall(struct drm_device * dev)
2668{
2669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2670 int pipe;
2671
Chris Wilsona266c7d2012-04-24 22:59:44 +01002672 if (I915_HAS_HOTPLUG(dev)) {
2673 I915_WRITE(PORT_HOTPLUG_EN, 0);
2674 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2675 }
2676
Chris Wilson00d98eb2012-04-24 22:59:48 +01002677 I915_WRITE16(HWSTAM, 0xffff);
Chris Wilson55b39752012-04-24 22:59:49 +01002678 for_each_pipe(pipe) {
2679 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01002680 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01002681 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2682 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01002683 I915_WRITE(IMR, 0xffffffff);
2684 I915_WRITE(IER, 0x0);
2685
Chris Wilsona266c7d2012-04-24 22:59:44 +01002686 I915_WRITE(IIR, I915_READ(IIR));
2687}
2688
2689static void i965_irq_preinstall(struct drm_device * dev)
2690{
2691 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2692 int pipe;
2693
2694 atomic_set(&dev_priv->irq_received, 0);
2695
Chris Wilsonadca4732012-05-11 18:01:31 +01002696 I915_WRITE(PORT_HOTPLUG_EN, 0);
2697 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01002698
2699 I915_WRITE(HWSTAM, 0xeffe);
2700 for_each_pipe(pipe)
2701 I915_WRITE(PIPESTAT(pipe), 0);
2702 I915_WRITE(IMR, 0xffffffff);
2703 I915_WRITE(IER, 0x0);
2704 POSTING_READ(IER);
2705}
2706
2707static int i965_irq_postinstall(struct drm_device *dev)
2708{
2709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01002710 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002711 u32 error_mask;
2712
Chris Wilsona266c7d2012-04-24 22:59:44 +01002713 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01002714 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01002715 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01002716 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2717 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2718 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2719 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2720 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2721
2722 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02002723 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2724 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01002725 enable_mask |= I915_USER_INTERRUPT;
2726
2727 if (IS_G4X(dev))
2728 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002729
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002730 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002731
Chris Wilsona266c7d2012-04-24 22:59:44 +01002732 /*
2733 * Enable some error detection, note the instruction error mask
2734 * bit is reserved, so we leave it masked.
2735 */
2736 if (IS_G4X(dev)) {
2737 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2738 GM45_ERROR_MEM_PRIV |
2739 GM45_ERROR_CP_PRIV |
2740 I915_ERROR_MEMORY_REFRESH);
2741 } else {
2742 error_mask = ~(I915_ERROR_PAGE_TABLE |
2743 I915_ERROR_MEMORY_REFRESH);
2744 }
2745 I915_WRITE(EMR, error_mask);
2746
2747 I915_WRITE(IMR, dev_priv->irq_mask);
2748 I915_WRITE(IER, enable_mask);
2749 POSTING_READ(IER);
2750
Daniel Vetter20afbda2012-12-11 14:05:07 +01002751 I915_WRITE(PORT_HOTPLUG_EN, 0);
2752 POSTING_READ(PORT_HOTPLUG_EN);
2753
2754 intel_opregion_enable_asle(dev);
2755
2756 return 0;
2757}
2758
Egbert Eichbac56d52013-02-25 12:06:51 -05002759static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01002760{
2761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Egbert Eiche5868a32013-02-28 04:17:12 -05002762 struct drm_mode_config *mode_config = &dev->mode_config;
2763 struct intel_encoder *encoder;
Daniel Vetter20afbda2012-12-11 14:05:07 +01002764 u32 hotplug_en;
2765
Egbert Eichbac56d52013-02-25 12:06:51 -05002766 if (I915_HAS_HOTPLUG(dev)) {
2767 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2768 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2769 /* Note HDMI and DP share hotplug bits */
Egbert Eiche5868a32013-02-28 04:17:12 -05002770 /* enable bits are the same for all generations */
Egbert Eichbac56d52013-02-25 12:06:51 -05002771 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2772 hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2773 /* Programming the CRT detection parameters tends
2774 to generate a spurious hotplug event about three
2775 seconds later. So just do it once.
2776 */
2777 if (IS_G4X(dev))
2778 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Daniel Vetter85fc95b2013-03-27 15:47:11 +01002779 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
Egbert Eichbac56d52013-02-25 12:06:51 -05002780 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002781
Egbert Eichbac56d52013-02-25 12:06:51 -05002782 /* Ignore TV since it's buggy */
2783 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2784 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01002785}
2786
Daniel Vetterff1f5252012-10-02 15:10:55 +02002787static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01002788{
2789 struct drm_device *dev = (struct drm_device *) arg;
2790 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002791 u32 iir, new_iir;
2792 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01002793 unsigned long irqflags;
2794 int irq_received;
2795 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02002796 u32 flip_mask =
2797 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2798 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002799
2800 atomic_inc(&dev_priv->irq_received);
2801
2802 iir = I915_READ(IIR);
2803
Chris Wilsona266c7d2012-04-24 22:59:44 +01002804 for (;;) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01002805 bool blc_event = false;
2806
Ville Syrjälä21ad8332013-02-19 15:16:39 +02002807 irq_received = (iir & ~flip_mask) != 0;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002808
2809 /* Can't rely on pipestat interrupt bit in iir as it might
2810 * have been cleared after the pipestat interrupt was received.
2811 * It doesn't set the bit in iir again, but it still produces
2812 * interrupts (for non-MSI).
2813 */
2814 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2815 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2816 i915_handle_error(dev, false);
2817
2818 for_each_pipe(pipe) {
2819 int reg = PIPESTAT(pipe);
2820 pipe_stats[pipe] = I915_READ(reg);
2821
2822 /*
2823 * Clear the PIPE*STAT regs before the IIR
2824 */
2825 if (pipe_stats[pipe] & 0x8000ffff) {
2826 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2827 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2828 pipe_name(pipe));
2829 I915_WRITE(reg, pipe_stats[pipe]);
2830 irq_received = 1;
2831 }
2832 }
2833 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2834
2835 if (!irq_received)
2836 break;
2837
2838 ret = IRQ_HANDLED;
2839
2840 /* Consume port. Then clear IIR or we'll miss events */
Chris Wilsonadca4732012-05-11 18:01:31 +01002841 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01002842 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2843
2844 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2845 hotplug_status);
Egbert Eiche5868a32013-02-28 04:17:12 -05002846 if (hotplug_status & (IS_G4X(dev) ?
2847 HOTPLUG_INT_STATUS_G4X :
2848 HOTPLUG_INT_STATUS_I965))
Chris Wilsona266c7d2012-04-24 22:59:44 +01002849 queue_work(dev_priv->wq,
2850 &dev_priv->hotplug_work);
2851
2852 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2853 I915_READ(PORT_HOTPLUG_STAT);
2854 }
2855
Ville Syrjälä21ad8332013-02-19 15:16:39 +02002856 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002857 new_iir = I915_READ(IIR); /* Flush posted writes */
2858
Chris Wilsona266c7d2012-04-24 22:59:44 +01002859 if (iir & I915_USER_INTERRUPT)
2860 notify_ring(dev, &dev_priv->ring[RCS]);
2861 if (iir & I915_BSD_USER_INTERRUPT)
2862 notify_ring(dev, &dev_priv->ring[VCS]);
2863
Chris Wilsona266c7d2012-04-24 22:59:44 +01002864 for_each_pipe(pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01002865 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002866 i915_handle_vblank(dev, pipe, pipe, iir))
2867 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002868
2869 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2870 blc_event = true;
2871 }
2872
2873
2874 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2875 intel_opregion_asle_intr(dev);
2876
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002877 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2878 gmbus_irq_handler(dev);
2879
Chris Wilsona266c7d2012-04-24 22:59:44 +01002880 /* With MSI, interrupts are only generated when iir
2881 * transitions from zero to nonzero. If another bit got
2882 * set while we were handling the existing iir bits, then
2883 * we would never get another interrupt.
2884 *
2885 * This is fine on non-MSI as well, as if we hit this path
2886 * we avoid exiting the interrupt handler only to generate
2887 * another one.
2888 *
2889 * Note that for MSI this could cause a stray interrupt report
2890 * if an interrupt landed in the time between writing IIR and
2891 * the posting read. This should be rare enough to never
2892 * trigger the 99% of 100,000 interrupts test for disabling
2893 * stray interrupts.
2894 */
2895 iir = new_iir;
2896 }
2897
Daniel Vetterd05c6172012-04-26 23:28:09 +02002898 i915_update_dri1_breadcrumb(dev);
Chris Wilson2c8ba292012-04-24 22:59:46 +01002899
Chris Wilsona266c7d2012-04-24 22:59:44 +01002900 return ret;
2901}
2902
2903static void i965_irq_uninstall(struct drm_device * dev)
2904{
2905 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2906 int pipe;
2907
2908 if (!dev_priv)
2909 return;
2910
Chris Wilsonadca4732012-05-11 18:01:31 +01002911 I915_WRITE(PORT_HOTPLUG_EN, 0);
2912 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01002913
2914 I915_WRITE(HWSTAM, 0xffffffff);
2915 for_each_pipe(pipe)
2916 I915_WRITE(PIPESTAT(pipe), 0);
2917 I915_WRITE(IMR, 0xffffffff);
2918 I915_WRITE(IER, 0x0);
2919
2920 for_each_pipe(pipe)
2921 I915_WRITE(PIPESTAT(pipe),
2922 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2923 I915_WRITE(IIR, I915_READ(IIR));
2924}
2925
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002926void intel_irq_init(struct drm_device *dev)
2927{
Chris Wilson8b2e3262012-04-24 22:59:41 +01002928 struct drm_i915_private *dev_priv = dev->dev_private;
2929
2930 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Daniel Vetter99584db2012-11-14 17:14:04 +01002931 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02002932 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01002933 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01002934
Daniel Vetter99584db2012-11-14 17:14:04 +01002935 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2936 i915_hangcheck_elapsed,
Daniel Vetter61bac782012-12-01 21:03:21 +01002937 (unsigned long) dev);
2938
Tomas Janousek97a19a22012-12-08 13:48:13 +01002939 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01002940
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002941 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2942 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Eugeni Dodonov7d4e1462012-05-09 15:37:09 -03002943 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002944 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2945 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2946 }
2947
Keith Packardc3613de2011-08-12 17:05:54 -07002948 if (drm_core_check_feature(dev, DRIVER_MODESET))
2949 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2950 else
2951 dev->driver->get_vblank_timestamp = NULL;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002952 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2953
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002954 if (IS_VALLEYVIEW(dev)) {
2955 dev->driver->irq_handler = valleyview_irq_handler;
2956 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2957 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2958 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2959 dev->driver->enable_vblank = valleyview_enable_vblank;
2960 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05002961 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetter4a06e202012-12-01 13:53:40 +01002962 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002963 /* Share pre & uninstall handlers with ILK/SNB */
2964 dev->driver->irq_handler = ivybridge_irq_handler;
2965 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2966 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2967 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2968 dev->driver->enable_vblank = ivybridge_enable_vblank;
2969 dev->driver->disable_vblank = ivybridge_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002970 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002971 } else if (HAS_PCH_SPLIT(dev)) {
2972 dev->driver->irq_handler = ironlake_irq_handler;
2973 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2974 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2975 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2976 dev->driver->enable_vblank = ironlake_enable_vblank;
2977 dev->driver->disable_vblank = ironlake_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002978 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002979 } else {
Chris Wilsonc2798b12012-04-22 21:13:57 +01002980 if (INTEL_INFO(dev)->gen == 2) {
2981 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2982 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2983 dev->driver->irq_handler = i8xx_irq_handler;
2984 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002985 } else if (INTEL_INFO(dev)->gen == 3) {
2986 dev->driver->irq_preinstall = i915_irq_preinstall;
2987 dev->driver->irq_postinstall = i915_irq_postinstall;
2988 dev->driver->irq_uninstall = i915_irq_uninstall;
2989 dev->driver->irq_handler = i915_irq_handler;
Daniel Vetter20afbda2012-12-11 14:05:07 +01002990 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002991 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01002992 dev->driver->irq_preinstall = i965_irq_preinstall;
2993 dev->driver->irq_postinstall = i965_irq_postinstall;
2994 dev->driver->irq_uninstall = i965_irq_uninstall;
2995 dev->driver->irq_handler = i965_irq_handler;
Egbert Eichbac56d52013-02-25 12:06:51 -05002996 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002997 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002998 dev->driver->enable_vblank = i915_enable_vblank;
2999 dev->driver->disable_vblank = i915_disable_vblank;
3000 }
3001}
Daniel Vetter20afbda2012-12-11 14:05:07 +01003002
3003void intel_hpd_init(struct drm_device *dev)
3004{
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006
3007 if (dev_priv->display.hpd_irq_setup)
3008 dev_priv->display.hpd_irq_setup(dev);
3009}