blob: 0497841f841e2d7b7b29c5eca87a1939d04d4cb3 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Akshay Joshi0206e352011-08-16 15:34:10 -040044bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020045static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010046static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080047
48typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040049 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080050} intel_range_t;
51
52typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040053 int dot_limit;
54 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080055} intel_p2_t;
56
57#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080058typedef struct intel_limit intel_limit_t;
59struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040060 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080062};
Jesse Barnes79e53942008-11-07 14:24:08 -080063
Jesse Barnes2377b742010-07-07 14:06:43 -070064/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
Daniel Vetterd2acd212012-10-20 20:57:43 +020067int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
Chris Wilson021357a2010-09-07 20:54:59 +010077static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
Chris Wilson8b99e682010-10-13 09:59:17 +010080 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +010085}
86
Keith Packarde4b36692009-06-05 19:22:17 -070087static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -040088 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -070096 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -070098};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700111};
Eric Anholt273e27c2011-03-30 13:01:10 -0700112
Keith Packarde4b36692009-06-05 19:22:17 -0700113static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700137};
138
Eric Anholt273e27c2011-03-30 13:01:10 -0700139
Keith Packarde4b36692009-06-05 19:22:17 -0700140static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800152 },
Keith Packarde4b36692009-06-05 19:22:17 -0700153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800179 },
Keith Packarde4b36692009-06-05 19:22:17 -0700180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800193 },
Keith Packarde4b36692009-06-05 19:22:17 -0700194};
195
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500196static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700199 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700202 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700209};
210
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500211static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700222};
223
Eric Anholt273e27c2011-03-30 13:01:10 -0700224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800229static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700240};
241
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800242static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800266};
267
Eric Anholt273e27c2011-03-30 13:01:10 -0700268/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400277 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400290 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800293};
294
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200303 .p1 = { .min = 1, .max = 3 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
Daniel Vetter75e53982013-04-18 21:10:43 +0200309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700324 .n = { .min = 1, .max = 7 },
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530325 .m = { .min = 22, .max = 450 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200329 .p1 = { .min = 1, .max = 3 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700332};
333
Chris Wilson1b894b52010-12-14 20:04:54 +0000334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800336{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800337 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800338 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100341 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000342 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000347 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200352 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800353 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800354
355 return limit;
356}
357
Ma Ling044c7c42009-03-18 20:13:23 +0800358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100364 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700365 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800366 else
Keith Packarde4b36692009-06-05 19:22:17 -0700367 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700370 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700372 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800373 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700374 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800375
376 return limit;
377}
378
Chris Wilson1b894b52010-12-14 20:04:54 +0000379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
Eric Anholtbad720f2009-10-22 16:11:14 -0700384 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000385 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800386 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800387 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500388 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500390 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800391 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500392 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700407 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800408 else
Keith Packarde4b36692009-06-05 19:22:17 -0700409 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800410 }
411 return limit;
412}
413
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800416{
Shaohua Li21778322009-02-23 15:19:16 +0800417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200428static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800429{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200430 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
Jesse Barnes79e53942008-11-07 14:24:08 -0800436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800440{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100441 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100442 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800443
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100446 return true;
447
448 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800449}
450
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
Chris Wilson1b894b52010-12-14 20:04:54 +0000457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800460{
Jesse Barnes79e53942008-11-07 14:24:08 -0800461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400462 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800463 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400464 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400466 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400468 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400470 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800471 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400472 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800473 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400474 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400476 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400481 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800482
483 return true;
484}
485
Ma Lingd4906092009-03-18 20:13:27 +0800486static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800490{
491 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800492 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800493 int err = target;
494
Daniel Vettera210b022012-11-26 17:22:08 +0100495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800496 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800500 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100501 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
Akshay Joshi0206e352011-08-16 15:34:10 -0400512 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800513
Zhao Yakui42158662009-11-20 11:24:18 +0800514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200518 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800524 int this_err;
525
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200526 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800529 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
Ma Lingd4906092009-03-18 20:13:27 +0800547static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200551{
552 struct drm_device *dev = crtc->dev;
553 intel_clock_t clock;
554 int err = target;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 /*
558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
561 */
562 if (intel_is_dual_link_lvds(dev))
563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
573 memset(best_clock, 0, sizeof(*best_clock));
574
575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
583 int this_err;
584
585 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
588 continue;
589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
Ma Lingd4906092009-03-18 20:13:27 +0800606static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800610{
611 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800612 intel_clock_t clock;
613 int max_n;
614 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100620 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200633 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200635 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200644 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800647 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000648
649 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800660 return found;
661}
Ma Lingd4906092009-03-18 20:13:27 +0800662
Zhenyu Wang2c072452009-06-05 15:38:42 +0800663static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
Alan Coxaf447bd2012-07-25 13:49:18 +0100674 flag = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700731
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
Daniel Vetter3b117c82013-04-17 20:15:07 +0200738 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200739}
740
Paulo Zanonia928d532012-05-04 17:18:15 -0300741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800761{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700762 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800763 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700764
Paulo Zanonia928d532012-05-04 17:18:15 -0300765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
Chris Wilson300387c2010-09-05 20:25:43 +0100770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700786 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
Keith Packardab7ad7f2010-10-03 00:33:06 -0700793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100808 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700809 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700815
Keith Packardab7ad7f2010-10-03 00:33:06 -0700816 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200817 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700818
Keith Packardab7ad7f2010-10-03 00:33:06 -0700819 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200822 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700823 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300824 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100825 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
Paulo Zanoni837ba002012-05-04 17:18:14 -0300828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
Keith Packardab7ad7f2010-10-03 00:33:06 -0700833 /* Wait for the display line to settle */
834 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300835 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700836 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -0300837 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
Daniel Vetter284637d2012-07-09 09:51:57 +0200840 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700841 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800842}
843
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
Damien Lespiauc36346e2012-12-13 16:09:03 +0000856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
Jesse Barnesb24e7172011-01-04 15:09:30 -0800889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +0200895void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
Jesse Barnesb24e7172011-01-04 15:09:30 -0800909
Daniel Vetter55607e82013-06-16 21:42:39 +0200910struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +0200911intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -0800912{
Daniel Vettere2b78262013-06-07 23:10:03 +0200913 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
914
Daniel Vettera43f6e02013-06-07 23:10:32 +0200915 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +0200916 return NULL;
917
Daniel Vettera43f6e02013-06-07 23:10:32 +0200918 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +0200919}
920
Jesse Barnesb24e7172011-01-04 15:09:30 -0800921/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +0200922void assert_shared_dpll(struct drm_i915_private *dev_priv,
923 struct intel_shared_dpll *pll,
924 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -0800925{
Jesse Barnes040484a2011-01-03 12:14:26 -0800926 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +0200927 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -0800928
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -0300929 if (HAS_PCH_LPT(dev_priv->dev)) {
930 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
931 return;
932 }
933
Chris Wilson92b27b02012-05-20 18:10:50 +0100934 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +0200935 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100936 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100937
Daniel Vetter53589012013-06-05 13:34:16 +0200938 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +0100939 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +0200940 "%s assertion failure (expected %s, current %s)\n",
941 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -0800942}
Jesse Barnes040484a2011-01-03 12:14:26 -0800943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -0200950 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
951 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -0800952
Paulo Zanoniaffa9352012-11-23 15:30:39 -0200953 if (HAS_DDI(dev_priv->dev)) {
954 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -0200955 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300956 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -0200957 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300958 } else {
959 reg = FDI_TX_CTL(pipe);
960 val = I915_READ(reg);
961 cur_state = !!(val & FDI_TX_ENABLE);
962 }
Jesse Barnes040484a2011-01-03 12:14:26 -0800963 WARN(cur_state != state,
964 "FDI TX state assertion failure (expected %s, current %s)\n",
965 state_string(state), state_string(cur_state));
966}
967#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
968#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
969
970static void assert_fdi_rx(struct drm_i915_private *dev_priv,
971 enum pipe pipe, bool state)
972{
973 int reg;
974 u32 val;
975 bool cur_state;
976
Paulo Zanonid63fa0d2012-11-20 13:27:35 -0200977 reg = FDI_RX_CTL(pipe);
978 val = I915_READ(reg);
979 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -0800980 WARN(cur_state != state,
981 "FDI RX state assertion failure (expected %s, current %s)\n",
982 state_string(state), state_string(cur_state));
983}
984#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
985#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
986
987static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
988 enum pipe pipe)
989{
990 int reg;
991 u32 val;
992
993 /* ILK FDI PLL is always enabled */
994 if (dev_priv->info->gen == 5)
995 return;
996
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300997 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -0200998 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300999 return;
1000
Jesse Barnes040484a2011-01-03 12:14:26 -08001001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004}
1005
Daniel Vetter55607e82013-06-16 21:42:39 +02001006void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001008{
1009 int reg;
1010 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001011 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001012
1013 reg = FDI_RX_CTL(pipe);
1014 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001015 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016 WARN(cur_state != state,
1017 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001019}
1020
Jesse Barnesea0760c2011-01-04 15:09:32 -08001021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001027 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001047 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001048}
1049
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001052{
1053 int reg;
1054 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001055 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001058
Daniel Vetter8e636782012-01-22 01:36:48 +01001059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
Paulo Zanonib97186f2013-05-03 12:15:36 -03001063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001074 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001075}
1076
Chris Wilson931872f2012-01-16 23:01:13 +00001077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001079{
1080 int reg;
1081 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001082 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001090}
1091
Chris Wilson931872f2012-01-16 23:01:13 +00001092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
Jesse Barnesb24e7172011-01-04 15:09:30 -08001095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001098 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
Ville Syrjälä653e1022013-06-04 13:49:05 +03001103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001110 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001111 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001112
Jesse Barnesb24e7172011-01-04 15:09:30 -08001113 /* Need to check both planes against the pipe */
Ville Syrjälä653e1022013-06-04 13:49:05 +03001114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001122 }
1123}
1124
Jesse Barnes19332d72013-03-28 09:55:38 -07001125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001128 struct drm_device *dev = dev_priv->dev;
Jesse Barnes19332d72013-03-28 09:55:38 -07001129 int reg, i;
1130 u32 val;
1131
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001142 val = I915_READ(reg);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001143 WARN((val & SPRITE_ENABLE),
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DVS_ENABLE),
1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001152 }
1153}
1154
Jesse Barnes92f25842011-01-04 15:09:34 -08001155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
Jesse Barnes92f25842011-01-04 15:09:34 -08001165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
Daniel Vetterab9412b2013-05-03 11:49:46 +02001171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
Daniel Vetterab9412b2013-05-03 11:49:46 +02001178 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001184}
1185
Keith Packard4e634382011-08-06 10:39:45 -07001186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
Keith Packard1519b992011-08-06 10:35:34 -07001204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001207 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001212 return false;
1213 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
Jesse Barnes291906f2011-02-02 12:28:03 -08001251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001252 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001253{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001254 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001257 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001258
Daniel Vetter75c5da22012-09-10 21:58:29 +02001259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001261 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001267 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001270 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001271
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001273 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001274 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001282
Keith Packardf0575e92011-07-25 22:12:43 -07001283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001290 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001291 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001297 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001298
Paulo Zanonie2debe92013-02-18 19:00:27 -03001299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001302}
1303
Daniel Vetter87442f72013-06-06 00:52:17 +02001304static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001305{
1306 int reg;
1307 u32 val;
1308
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001309 assert_pipe_disabled(dev_priv, pipe);
1310
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001311 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001312 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314 /* PLL is protected by panel, make sure we can write it */
1315 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316 assert_panel_unlocked(dev_priv, pipe);
1317
1318 reg = DPLL(pipe);
1319 val = I915_READ(reg);
1320 val |= DPLL_VCO_ENABLE;
1321
1322 /* We do this three times for luck */
1323 I915_WRITE(reg, val);
1324 POSTING_READ(reg);
1325 udelay(150); /* wait for warmup */
1326 I915_WRITE(reg, val);
1327 POSTING_READ(reg);
1328 udelay(150); /* wait for warmup */
1329 I915_WRITE(reg, val);
1330 POSTING_READ(reg);
1331 udelay(150); /* wait for warmup */
1332}
1333
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001334static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001335{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001336 struct drm_device *dev = crtc->base.dev;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int reg = DPLL(crtc->pipe);
1339 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001340
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001341 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001342
1343 /* No really, not for ILK+ */
1344 BUG_ON(dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001345
1346 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001347 if (IS_MOBILE(dev) && !IS_I830(dev))
1348 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001349
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001350 I915_WRITE(reg, dpll);
1351
1352 /* Wait for the clocks to stabilize. */
1353 POSTING_READ(reg);
1354 udelay(150);
1355
1356 if (INTEL_INFO(dev)->gen >= 4) {
1357 I915_WRITE(DPLL_MD(crtc->pipe),
1358 crtc->config.dpll_hw_state.dpll_md);
1359 } else {
1360 /* The pixel multiplier can only be updated once the
1361 * DPLL is enabled and the clocks are stable.
1362 *
1363 * So write it again.
1364 */
1365 I915_WRITE(reg, dpll);
1366 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001367
1368 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001369 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001370 POSTING_READ(reg);
1371 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001372 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001373 POSTING_READ(reg);
1374 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001375 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001376 POSTING_READ(reg);
1377 udelay(150); /* wait for warmup */
1378}
1379
1380/**
1381 * intel_disable_pll - disable a PLL
1382 * @dev_priv: i915 private structure
1383 * @pipe: pipe PLL to disable
1384 *
1385 * Disable the PLL for @pipe, making sure the pipe is off first.
1386 *
1387 * Note! This is for pre-ILK only.
1388 */
1389static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1390{
1391 int reg;
1392 u32 val;
1393
1394 /* Don't disable pipe A or pipe A PLLs if needed */
1395 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1396 return;
1397
1398 /* Make sure the pipe isn't still relying on us */
1399 assert_pipe_disabled(dev_priv, pipe);
1400
1401 reg = DPLL(pipe);
1402 val = I915_READ(reg);
1403 val &= ~DPLL_VCO_ENABLE;
1404 I915_WRITE(reg, val);
1405 POSTING_READ(reg);
1406}
1407
Jesse Barnes89b667f2013-04-18 14:51:36 -07001408void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1409{
1410 u32 port_mask;
1411
1412 if (!port)
1413 port_mask = DPLL_PORTB_READY_MASK;
1414 else
1415 port_mask = DPLL_PORTC_READY_MASK;
1416
1417 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1418 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1419 'B' + port, I915_READ(DPLL(0)));
1420}
1421
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001422/**
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001423 * ironlake_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1428 * drives the transcoder clock.
1429 */
Daniel Vettere2b78262013-06-07 23:10:03 +02001430static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001431{
Daniel Vettere2b78262013-06-07 23:10:03 +02001432 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1433 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001434
Chris Wilson48da64a2012-05-13 20:16:12 +01001435 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001436 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001437 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001438 return;
1439
1440 if (WARN_ON(pll->refcount == 0))
1441 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001442
Daniel Vetter46edb022013-06-05 13:34:12 +02001443 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1444 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001445 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001446
Daniel Vettercdbd2312013-06-05 13:34:03 +02001447 if (pll->active++) {
1448 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001449 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001450 return;
1451 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001452 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001453
Daniel Vetter46edb022013-06-05 13:34:12 +02001454 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001455 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001456 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001457}
1458
Daniel Vettere2b78262013-06-07 23:10:03 +02001459static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001460{
Daniel Vettere2b78262013-06-07 23:10:03 +02001461 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1462 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001463
Jesse Barnes92f25842011-01-04 15:09:34 -08001464 /* PCH only available on ILK+ */
1465 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001466 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001467 return;
1468
Chris Wilson48da64a2012-05-13 20:16:12 +01001469 if (WARN_ON(pll->refcount == 0))
1470 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001471
Daniel Vetter46edb022013-06-05 13:34:12 +02001472 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1473 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001474 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001475
Chris Wilson48da64a2012-05-13 20:16:12 +01001476 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001477 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001478 return;
1479 }
1480
Daniel Vettere9d69442013-06-05 13:34:15 +02001481 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001482 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001483 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001484 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001485
Daniel Vetter46edb022013-06-05 13:34:12 +02001486 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001487 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001488 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001489}
1490
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001493{
Daniel Vetter23670b322012-11-01 09:15:30 +01001494 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001497 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001498
1499 /* PCH only available on ILK+ */
1500 BUG_ON(dev_priv->info->gen < 5);
1501
1502 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001503 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001504 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
Daniel Vetter23670b322012-11-01 09:15:30 +01001510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001517 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001518
Daniel Vetterab9412b2013-05-03 11:49:46 +02001519 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001520 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001521 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001530 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001539 else
1540 val |= TRANS_PROGRESSIVE;
1541
Jesse Barnes040484a2011-01-03 12:14:26 -08001542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001545}
1546
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001548 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001549{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001550 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001555 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001558
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001564 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001566
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001569 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001570 else
1571 val |= TRANS_PROGRESSIVE;
1572
Daniel Vetterab9412b2013-05-03 11:49:46 +02001573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001575 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001576}
1577
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001580{
Daniel Vetter23670b322012-11-01 09:15:30 +01001581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
Jesse Barnes291906f2011-02-02 12:28:03 -08001588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
Daniel Vetterab9412b2013-05-03 11:49:46 +02001591 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001606}
1607
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001609{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001610 u32 val;
1611
Daniel Vetterab9412b2013-05-03 11:49:46 +02001612 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001613 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001614 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001615 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001617 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001622 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001623}
1624
1625/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001626 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001641{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001644 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001645 int reg;
1646 u32 val;
1647
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
Paulo Zanoni681e5812012-12-06 11:12:38 -02001651 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
Jesse Barnesb24e7172011-01-04 15:09:30 -08001656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001672
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001673 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001674 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001683 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001707 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001713 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001714 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
Keith Packardd74362c2011-07-28 14:47:14 -07001722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001727 enum plane plane)
1728{
Damien Lespiau14f86142012-10-29 15:24:49 +00001729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
Keith Packardd74362c2011-07-28 14:47:14 -07001733}
1734
Jesse Barnesb24e7172011-01-04 15:09:30 -08001735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001758 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
Jesse Barnesb24e7172011-01-04 15:09:30 -08001762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
Chris Wilson693db182013-03-05 14:52:39 +00001786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
Chris Wilson127bd2a2010-07-23 23:32:05 +01001795int
Chris Wilson48b956c2010-09-14 12:50:34 +01001796intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001797 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001798 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001799{
Chris Wilsonce453d82011-02-21 14:43:56 +00001800 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001801 u32 alignment;
1802 int ret;
1803
Chris Wilson05394f32010-11-08 19:18:58 +00001804 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001805 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001808 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
Daniel Vetter8bb6e952013-04-06 23:54:56 +02001818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
Chris Wilson693db182013-03-05 14:52:39 +00001827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
Chris Wilsonce453d82011-02-21 14:43:56 +00001835 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001837 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001838 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
Chris Wilson06d98132012-04-17 15:31:24 +01001845 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001846 if (ret)
1847 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001848
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001849 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001850
Chris Wilsonce453d82011-02-21 14:43:56 +00001851 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001852 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001856err_interruptible:
1857 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001858 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001859}
1860
Chris Wilson1690e1e2011-12-14 13:57:08 +01001861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
Daniel Vetterc2c75132012-07-05 12:17:30 +02001867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00001869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02001873{
Chris Wilsonbc752862013-02-21 20:04:31 +00001874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001876
Chris Wilsonbc752862013-02-21 20:04:31 +00001877 tile_rows = *y / 8;
1878 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001879
Chris Wilsonbc752862013-02-21 20:04:31 +00001880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02001892}
1893
Jesse Barnes17638cd2011-06-24 12:19:23 -07001894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001901 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001902 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02001903 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07001904 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01001905 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07001906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes81255562010-08-02 12:07:50 -07001913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001918
Chris Wilson5eddb702010-09-11 13:48:45 +01001919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07001925 dspcntr |= DISPPLANE_8BPP;
1926 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07001930 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07001949 break;
1950 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01001951 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07001952 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02001953
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001954 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00001955 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07001956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
Ville Syrjäläde1aa622013-06-07 10:47:01 +03001961 if (IS_G4X(dev))
1962 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
Chris Wilson5eddb702010-09-11 13:48:45 +01001964 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07001965
Daniel Vettere506a0c2012-07-05 12:17:29 +02001966 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07001967
Daniel Vetterc2c75132012-07-05 12:17:30 +02001968 if (INTEL_INFO(dev)->gen >= 4) {
1969 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00001970 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971 fb->bits_per_pixel / 8,
1972 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02001973 linear_offset -= intel_crtc->dspaddr_offset;
1974 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02001975 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001976 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02001977
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02001980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001981 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02001982 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001984 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02001985 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001986 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02001987 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001988 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001989
Jesse Barnes17638cd2011-06-24 12:19:23 -07001990 return 0;
1991}
1992
1993static int ironlake_update_plane(struct drm_crtc *crtc,
1994 struct drm_framebuffer *fb, int x, int y)
1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
2000 struct drm_i915_gem_object *obj;
2001 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002002 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002003 u32 dspcntr;
2004 u32 reg;
2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002009 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002010 break;
2011 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes17638cd2011-06-24 12:19:23 -07002013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002025 dspcntr |= DISPPLANE_8BPP;
2026 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002027 case DRM_FORMAT_RGB565:
2028 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002029 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002030 case DRM_FORMAT_XRGB8888:
2031 case DRM_FORMAT_ARGB8888:
2032 dspcntr |= DISPPLANE_BGRX888;
2033 break;
2034 case DRM_FORMAT_XBGR8888:
2035 case DRM_FORMAT_ABGR8888:
2036 dspcntr |= DISPPLANE_RGBX888;
2037 break;
2038 case DRM_FORMAT_XRGB2101010:
2039 case DRM_FORMAT_ARGB2101010:
2040 dspcntr |= DISPPLANE_BGRX101010;
2041 break;
2042 case DRM_FORMAT_XBGR2101010:
2043 case DRM_FORMAT_ABGR2101010:
2044 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002045 break;
2046 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002047 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002048 }
2049
2050 if (obj->tiling_mode != I915_TILING_NONE)
2051 dspcntr |= DISPPLANE_TILED;
2052 else
2053 dspcntr &= ~DISPPLANE_TILED;
2054
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
Daniel Vettere506a0c2012-07-05 12:17:29 +02002060 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002061 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002065 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002066
Daniel Vettere506a0c2012-07-05 12:17:29 +02002067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002070 I915_MODIFY_DISPBASE(DSPSURF(plane),
2071 obj->gtt_offset + intel_crtc->dspaddr_offset);
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002072 if (IS_HASWELL(dev)) {
2073 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074 } else {
2075 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002078 POSTING_READ(reg);
2079
2080 return 0;
2081}
2082
2083/* Assume fb object is pinned & idle & fenced and just update base pointers */
2084static int
2085intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086 int x, int y, enum mode_set_atomic state)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002090
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002091 if (dev_priv->display.disable_fbc)
2092 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002093 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002094
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002095 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002096}
2097
Ville Syrjälä96a02912013-02-18 19:08:49 +02002098void intel_display_handle_reset(struct drm_device *dev)
2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102
2103 /*
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2107 *
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2111 *
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2115 */
2116
2117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 enum plane plane = intel_crtc->plane;
2120
2121 intel_prepare_page_flip(dev, plane);
2122 intel_finish_page_flip_plane(dev, plane);
2123 }
2124
2125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128 mutex_lock(&crtc->mutex);
2129 if (intel_crtc->active)
2130 dev_priv->display.update_plane(crtc, crtc->fb,
2131 crtc->x, crtc->y);
2132 mutex_unlock(&crtc->mutex);
2133 }
2134}
2135
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002136static int
Chris Wilson14667a42012-04-03 17:58:35 +01002137intel_finish_fb(struct drm_framebuffer *old_fb)
2138{
2139 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 bool was_interruptible = dev_priv->mm.interruptible;
2142 int ret;
2143
Chris Wilson14667a42012-04-03 17:58:35 +01002144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2147 * framebuffer.
2148 *
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2151 */
2152 dev_priv->mm.interruptible = false;
2153 ret = i915_gem_object_finish_gpu(obj);
2154 dev_priv->mm.interruptible = was_interruptible;
2155
2156 return ret;
2157}
2158
Ville Syrjälä198598d2012-10-31 17:50:24 +02002159static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_master_private *master_priv;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165 if (!dev->primary->master)
2166 return;
2167
2168 master_priv = dev->primary->master->driver_priv;
2169 if (!master_priv->sarea_priv)
2170 return;
2171
2172 switch (intel_crtc->pipe) {
2173 case 0:
2174 master_priv->sarea_priv->pipeA_x = x;
2175 master_priv->sarea_priv->pipeA_y = y;
2176 break;
2177 case 1:
2178 master_priv->sarea_priv->pipeB_x = x;
2179 master_priv->sarea_priv->pipeB_y = y;
2180 break;
2181 default:
2182 break;
2183 }
2184}
2185
Chris Wilson14667a42012-04-03 17:58:35 +01002186static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002188 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002189{
2190 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002191 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002193 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002194 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002195
2196 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002197 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002198 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002199 return 0;
2200 }
2201
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002202 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc->plane),
2205 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002206 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002207 }
2208
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002209 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002210 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002211 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002212 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002213 if (ret != 0) {
2214 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002215 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002216 return ret;
2217 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002218
Daniel Vetter94352cf2012-07-05 22:51:56 +02002219 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002220 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002221 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002222 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002223 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002224 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002225 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002226
Daniel Vetter94352cf2012-07-05 22:51:56 +02002227 old_fb = crtc->fb;
2228 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002229 crtc->x = x;
2230 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002231
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002232 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002233 if (intel_crtc->active && old_fb != fb)
2234 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002236 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002237
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002238 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002239 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002240
Ville Syrjälä198598d2012-10-31 17:50:24 +02002241 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002242
2243 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002244}
2245
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002246static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
2252 u32 reg, temp;
2253
2254 /* enable normal train */
2255 reg = FDI_TX_CTL(pipe);
2256 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002257 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002258 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002260 } else {
2261 temp &= ~FDI_LINK_TRAIN_NONE;
2262 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002263 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002264 I915_WRITE(reg, temp);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 if (HAS_PCH_CPT(dev)) {
2269 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271 } else {
2272 temp &= ~FDI_LINK_TRAIN_NONE;
2273 temp |= FDI_LINK_TRAIN_NONE;
2274 }
2275 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277 /* wait one idle pattern time */
2278 POSTING_READ(reg);
2279 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002280
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev))
2283 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002285}
2286
Daniel Vetter1e833f42013-02-19 22:31:57 +01002287static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288{
2289 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290}
2291
Daniel Vetter01a415f2012-10-27 15:58:40 +02002292static void ivb_modeset_global_resources(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *pipe_B_crtc =
2296 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297 struct intel_crtc *pipe_C_crtc =
2298 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299 uint32_t temp;
2300
Daniel Vetter1e833f42013-02-19 22:31:57 +01002301 /*
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2305 */
2306 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 }
2316}
2317
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002318/* The FDI link training functions for ILK/Ibexpeak. */
2319static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320{
2321 struct drm_device *dev = crtc->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002325 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002326 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002327
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv, pipe);
2330 assert_plane_enabled(dev_priv, plane);
2331
Adam Jacksone1a44742010-06-25 15:32:14 -04002332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002334 reg = FDI_RX_IMR(pipe);
2335 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002336 temp &= ~FDI_RX_SYMBOL_LOCK;
2337 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002338 I915_WRITE(reg, temp);
2339 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002340 udelay(150);
2341
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002342 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002345 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002349 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002350
Chris Wilson5eddb702010-09-11 13:48:45 +01002351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002355 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002358 udelay(150);
2359
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002360 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002364
Chris Wilson5eddb702010-09-11 13:48:45 +01002365 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002366 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002367 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370 if ((temp & FDI_RX_BIT_LOCK)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002372 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002373 break;
2374 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002375 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002376 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002377 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002378
2379 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002384 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002385
Chris Wilson5eddb702010-09-11 13:48:45 +01002386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002390 I915_WRITE(reg, temp);
2391
2392 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002393 udelay(150);
2394
Chris Wilson5eddb702010-09-11 13:48:45 +01002395 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002396 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002397 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403 break;
2404 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002405 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002406 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002407 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002408
2409 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002410
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002411}
2412
Akshay Joshi0206e352011-08-16 15:34:10 -04002413static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002414 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418};
2419
2420/* The FDI link training functions for SNB/Cougarpoint. */
2421static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002427 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002428
Adam Jacksone1a44742010-06-25 15:32:14 -04002429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002431 reg = FDI_RX_IMR(pipe);
2432 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002433 temp &= ~FDI_RX_SYMBOL_LOCK;
2434 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002438 udelay(150);
2439
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002440 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 /* SNB-B */
2449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002451
Daniel Vetterd74cf322012-10-26 10:58:13 +02002452 I915_WRITE(FDI_RX_MISC(pipe),
2453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
Chris Wilson5eddb702010-09-11 13:48:45 +01002455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002457 if (HAS_PCH_CPT(dev)) {
2458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460 } else {
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002467 udelay(150);
2468
Akshay Joshi0206e352011-08-16 15:34:10 -04002469 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002477 udelay(500);
2478
Sean Paulfa37d392012-03-02 12:53:39 -05002479 for (retry = 0; retry < 5; retry++) {
2480 reg = FDI_RX_IIR(pipe);
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483 if (temp & FDI_RX_BIT_LOCK) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002489 }
Sean Paulfa37d392012-03-02 12:53:39 -05002490 if (retry < 5)
2491 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002492 }
2493 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002494 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002495
2496 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 if (IS_GEN6(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002506 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002507
Chris Wilson5eddb702010-09-11 13:48:45 +01002508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002520 udelay(150);
2521
Akshay Joshi0206e352011-08-16 15:34:10 -04002522 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002530 udelay(500);
2531
Sean Paulfa37d392012-03-02 12:53:39 -05002532 for (retry = 0; retry < 5; retry++) {
2533 reg = FDI_RX_IIR(pipe);
2534 temp = I915_READ(reg);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002542 }
Sean Paulfa37d392012-03-02 12:53:39 -05002543 if (retry < 5)
2544 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002545 }
2546 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002547 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002548
2549 DRM_DEBUG_KMS("FDI train done.\n");
2550}
2551
Jesse Barnes357555c2011-04-28 15:09:55 -07002552/* Manual link training for Ivy Bridge A0 parts */
2553static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
2559 u32 reg, temp, i;
2560
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
2570 udelay(150);
2571
Daniel Vetter01a415f2012-10-27 15:58:40 +02002572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe)));
2574
Jesse Barnes357555c2011-04-28 15:09:55 -07002575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Jesse Barnes357555c2011-04-28 15:09:55 -07002580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002584 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
Daniel Vetterd74cf322012-10-26 10:58:13 +02002587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
Jesse Barnes357555c2011-04-28 15:09:55 -07002590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~FDI_LINK_TRAIN_AUTO;
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002595 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
Akshay Joshi0206e352011-08-16 15:34:10 -04002601 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615 if (temp & FDI_RX_BIT_LOCK ||
2616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002619 break;
2620 }
2621 }
2622 if (i == 4)
2623 DRM_ERROR("FDI train 1 fail!\n");
2624
2625 /* Train 2 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
Akshay Joshi0206e352011-08-16 15:34:10 -04002643 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_SYMBOL_LOCK) {
2658 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 2 fail!\n");
2665
2666 DRM_DEBUG_KMS("FDI train done.\n");
2667}
2668
Daniel Vetter88cefb62012-08-12 19:27:14 +02002669static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002670{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002671 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002672 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002673 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002674 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002675
Jesse Barnesc64e3112010-09-10 11:27:03 -07002676
Jesse Barnes0e23b992010-09-10 11:10:00 -07002677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002680 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002682 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01002683 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002686 udelay(200);
2687
2688 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002689 temp = I915_READ(reg);
2690 I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002693 udelay(200);
2694
Paulo Zanoni20749732012-11-23 15:30:38 -02002695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002700
Paulo Zanoni20749732012-11-23 15:30:38 -02002701 POSTING_READ(reg);
2702 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002703 }
2704}
2705
Daniel Vetter88cefb62012-08-12 19:27:14 +02002706static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707{
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int pipe = intel_crtc->pipe;
2711 u32 reg, temp;
2712
2713 /* Switch from PCDclk to Rawclk */
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718 /* Disable CPU FDI TX PLL */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730 /* Wait for the clocks to turn off. */
2731 POSTING_READ(reg);
2732 udelay(100);
2733}
2734
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002735static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp;
2742
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747 POSTING_READ(reg);
2748
2749 reg = FDI_RX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755 POSTING_READ(reg);
2756 udelay(100);
2757
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002759 if (HAS_PCH_IBX(dev)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002761 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
Chris Wilson5bb61642012-09-27 21:25:58 +01002788static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä10d83732013-01-29 18:13:34 +02002792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5bb61642012-09-27 21:25:58 +01002793 unsigned long flags;
2794 bool pending;
2795
Ville Syrjälä10d83732013-01-29 18:13:34 +02002796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
Chris Wilson5bb61642012-09-27 21:25:58 +01002798 return false;
2799
2800 spin_lock_irqsave(&dev->event_lock, flags);
2801 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802 spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804 return pending;
2805}
2806
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
Chris Wilson0f911282012-04-17 10:05:38 +01002809 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002810 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002811
2812 if (crtc->fb == NULL)
2813 return;
2814
Daniel Vetter2c10d572012-12-20 21:24:07 +01002815 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
Chris Wilson5bb61642012-09-27 21:25:58 +01002817 wait_event(dev_priv->pending_flip_queue,
2818 !intel_crtc_has_pending_flip(crtc));
2819
Chris Wilson0f911282012-04-17 10:05:38 +01002820 mutex_lock(&dev->struct_mutex);
2821 intel_finish_fb(crtc->fb);
2822 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002823}
2824
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002825/* Program iCLKIP clock to the desired frequency */
2826static void lpt_program_iclkip(struct drm_crtc *crtc)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831 u32 temp;
2832
Daniel Vetter09153002012-12-12 14:06:44 +01002833 mutex_lock(&dev_priv->dpio_lock);
2834
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2837 */
2838 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002842 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843 SBI_SSCCTL_DISABLE,
2844 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002845
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc->mode.clock == 20000) {
2848 auxdiv = 1;
2849 divsel = 0x41;
2850 phaseinc = 0x20;
2851 } else {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2856 * precision.
2857 */
2858 u32 iclk_virtual_root_freq = 172800 * 1000;
2859 u32 iclk_pi_range = 64;
2860 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863 msb_divisor_value = desired_divisor / iclk_pi_range;
2864 pi_value = desired_divisor % iclk_pi_range;
2865
2866 auxdiv = 0;
2867 divsel = msb_divisor_value - 2;
2868 phaseinc = pi_value;
2869 }
2870
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878 crtc->mode.clock,
2879 auxdiv,
2880 divsel,
2881 phasedir,
2882 phaseinc);
2883
2884 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002885 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002886 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002892 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002893
2894 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002895 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002896 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002898 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002899
2900 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002901 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002902 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002903 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002904
2905 /* Wait for initialization time */
2906 udelay(24);
2907
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01002909
2910 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002911}
2912
Daniel Vetter275f01b22013-05-03 11:49:47 +02002913static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914 enum pipe pch_transcoder)
2915{
2916 struct drm_device *dev = crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921 I915_READ(HTOTAL(cpu_transcoder)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923 I915_READ(HBLANK(cpu_transcoder)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925 I915_READ(HSYNC(cpu_transcoder)));
2926
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928 I915_READ(VTOTAL(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930 I915_READ(VBLANK(cpu_transcoder)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932 I915_READ(VSYNC(cpu_transcoder)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935}
2936
Jesse Barnesf67a5592011-01-05 10:31:48 -08002937/*
2938 * Enable PCH resources required for PCH ports:
2939 * - PCH PLLs
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2943 * - transcoder
2944 */
2945static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002946{
2947 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002951 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002952
Daniel Vetterab9412b2013-05-03 11:49:46 +02002953 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01002954
Daniel Vettercd986ab2012-10-26 10:58:12 +02002955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002960 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002961 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002962
Daniel Vetter572deb32012-10-27 18:46:14 +02002963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2966 *
Daniel Vettere72f9fb2013-06-05 13:34:06 +02002967 * Note that enable_shared_dpll tries to do the right thing, but
2968 * get_shared_dpll unconditionally resets the pll - we need that to have
2969 * the right LVDS enable sequence. */
2970 ironlake_enable_shared_dpll(intel_crtc);
Chris Wilson6f13b7b2012-05-13 09:54:09 +01002971
Paulo Zanoni303b81e2012-10-31 18:12:23 -02002972 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002973 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07002974
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002975 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02002976 temp |= TRANS_DPLL_ENABLE(pipe);
2977 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02002978 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002979 temp |= sel;
2980 else
2981 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002982 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002983 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002984
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002985 /* set transcoder timing, panel must allow it */
2986 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02002987 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002988
Paulo Zanoni303b81e2012-10-31 18:12:23 -02002989 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002990
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002991 /* For PCH DP, enable TRANS_DP_CTL */
2992 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07002993 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2994 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002995 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01002996 reg = TRANS_DP_CTL(pipe);
2997 temp = I915_READ(reg);
2998 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002999 TRANS_DP_SYNC_MASK |
3000 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003001 temp |= (TRANS_DP_OUTPUT_ENABLE |
3002 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003003 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003004
3005 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003006 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003007 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003008 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003009
3010 switch (intel_trans_dp_port_sel(crtc)) {
3011 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003012 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003013 break;
3014 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003015 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003016 break;
3017 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003018 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003019 break;
3020 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003021 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003022 }
3023
Chris Wilson5eddb702010-09-11 13:48:45 +01003024 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003025 }
3026
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003027 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003028}
3029
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003030static void lpt_pch_enable(struct drm_crtc *crtc)
3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003035 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003036
Daniel Vetterab9412b2013-05-03 11:49:46 +02003037 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003038
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003039 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003040
Paulo Zanoni0540e482012-10-31 18:12:40 -02003041 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003042 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003043
Paulo Zanoni937bb612012-10-31 18:12:47 -02003044 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003045}
3046
Daniel Vettere2b78262013-06-07 23:10:03 +02003047static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003048{
Daniel Vettere2b78262013-06-07 23:10:03 +02003049 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003050
3051 if (pll == NULL)
3052 return;
3053
3054 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003055 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003056 return;
3057 }
3058
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003059 if (--pll->refcount == 0) {
3060 WARN_ON(pll->on);
3061 WARN_ON(pll->active);
3062 }
3063
Daniel Vettera43f6e02013-06-07 23:10:32 +02003064 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003065}
3066
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003067static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003068{
Daniel Vettere2b78262013-06-07 23:10:03 +02003069 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3070 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3071 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003072
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003073 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003074 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3075 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003076 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003077 }
3078
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003079 if (HAS_PCH_IBX(dev_priv->dev)) {
3080 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vettere2b78262013-06-07 23:10:03 +02003081 i = crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003082 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003083
Daniel Vetter46edb022013-06-05 13:34:12 +02003084 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3085 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003086
3087 goto found;
3088 }
3089
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003090 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3091 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003092
3093 /* Only want to check enabled timings first */
3094 if (pll->refcount == 0)
3095 continue;
3096
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003097 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3098 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003099 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003100 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003101 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003102
3103 goto found;
3104 }
3105 }
3106
3107 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003108 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3109 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003110 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003111 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3112 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003113 goto found;
3114 }
3115 }
3116
3117 return NULL;
3118
3119found:
Daniel Vettera43f6e02013-06-07 23:10:32 +02003120 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003121 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3122 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003123
Daniel Vettercdbd2312013-06-05 13:34:03 +02003124 if (pll->active == 0) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02003125 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3126 sizeof(pll->hw_state));
3127
Daniel Vetter46edb022013-06-05 13:34:12 +02003128 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003129 WARN_ON(pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02003130 assert_shared_dpll_disabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003131
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02003132 pll->mode_set(dev_priv, pll);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003133 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003134 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003135
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003136 return pll;
3137}
3138
Daniel Vettera1520312013-05-03 11:49:50 +02003139static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003140{
3141 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003142 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003143 u32 temp;
3144
3145 temp = I915_READ(dslreg);
3146 udelay(500);
3147 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003148 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003149 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003150 }
3151}
3152
Jesse Barnesb074cec2013-04-25 12:55:02 -07003153static void ironlake_pfit_enable(struct intel_crtc *crtc)
3154{
3155 struct drm_device *dev = crtc->base.dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 int pipe = crtc->pipe;
3158
Jesse Barnes0ef37f32013-05-03 13:26:37 -07003159 if (crtc->config.pch_pfit.size) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003160 /* Force use of hard-coded filter coefficients
3161 * as some pre-programmed values are broken,
3162 * e.g. x201.
3163 */
3164 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3165 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3166 PF_PIPE_SEL_IVB(pipe));
3167 else
3168 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3169 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3170 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003171 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003172}
3173
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003174static void intel_enable_planes(struct drm_crtc *crtc)
3175{
3176 struct drm_device *dev = crtc->dev;
3177 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3178 struct intel_plane *intel_plane;
3179
3180 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3181 if (intel_plane->pipe == pipe)
3182 intel_plane_restore(&intel_plane->base);
3183}
3184
3185static void intel_disable_planes(struct drm_crtc *crtc)
3186{
3187 struct drm_device *dev = crtc->dev;
3188 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3189 struct intel_plane *intel_plane;
3190
3191 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3192 if (intel_plane->pipe == pipe)
3193 intel_plane_disable(&intel_plane->base);
3194}
3195
Jesse Barnesf67a5592011-01-05 10:31:48 -08003196static void ironlake_crtc_enable(struct drm_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003201 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003202 int pipe = intel_crtc->pipe;
3203 int plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003204
Daniel Vetter08a48462012-07-02 11:43:47 +02003205 WARN_ON(!crtc->enabled);
3206
Jesse Barnesf67a5592011-01-05 10:31:48 -08003207 if (intel_crtc->active)
3208 return;
3209
3210 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003211
3212 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3213 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3214
Jesse Barnesf67a5592011-01-05 10:31:48 -08003215 intel_update_watermarks(dev);
3216
Daniel Vetterf6736a12013-06-05 13:34:30 +02003217 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003218 if (encoder->pre_enable)
3219 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003220
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003221 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003222 /* Note: FDI PLL enabling _must_ be done before we enable the
3223 * cpu pipes, hence this is separate from all the other fdi/pch
3224 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003225 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003226 } else {
3227 assert_fdi_tx_disabled(dev_priv, pipe);
3228 assert_fdi_rx_disabled(dev_priv, pipe);
3229 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003230
Jesse Barnesb074cec2013-04-25 12:55:02 -07003231 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003232
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003233 /*
3234 * On ILK+ LUT must be loaded before the pipe is running but with
3235 * clocks enabled
3236 */
3237 intel_crtc_load_lut(crtc);
3238
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003239 intel_enable_pipe(dev_priv, pipe,
3240 intel_crtc->config.has_pch_encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003241 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003242 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003243 intel_crtc_update_cursor(crtc, true);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003244
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003245 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003246 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003247
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003248 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003249 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003250 mutex_unlock(&dev->struct_mutex);
3251
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003252 for_each_encoder_on_crtc(dev, crtc, encoder)
3253 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003254
3255 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003256 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003257
3258 /*
3259 * There seems to be a race in PCH platform hw (at least on some
3260 * outputs) where an enabled pipe still completes any pageflip right
3261 * away (as if the pipe is off) instead of waiting for vblank. As soon
3262 * as the first vblank happend, everything works as expected. Hence just
3263 * wait for one vblank before returning to avoid strange things
3264 * happening.
3265 */
3266 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003267}
3268
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003269/* IPS only exists on ULT machines and is tied to pipe A. */
3270static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3271{
Damien Lespiauf5adf942013-06-24 18:29:34 +01003272 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003273}
3274
3275static void hsw_enable_ips(struct intel_crtc *crtc)
3276{
3277 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3278
3279 if (!crtc->config.ips_enabled)
3280 return;
3281
3282 /* We can only enable IPS after we enable a plane and wait for a vblank.
3283 * We guarantee that the plane is enabled by calling intel_enable_ips
3284 * only after intel_enable_plane. And intel_enable_plane already waits
3285 * for a vblank, so all we need to do here is to enable the IPS bit. */
3286 assert_plane_enabled(dev_priv, crtc->plane);
3287 I915_WRITE(IPS_CTL, IPS_ENABLE);
3288}
3289
3290static void hsw_disable_ips(struct intel_crtc *crtc)
3291{
3292 struct drm_device *dev = crtc->base.dev;
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294
3295 if (!crtc->config.ips_enabled)
3296 return;
3297
3298 assert_plane_enabled(dev_priv, crtc->plane);
3299 I915_WRITE(IPS_CTL, 0);
3300
3301 /* We need to wait for a vblank before we can disable the plane. */
3302 intel_wait_for_vblank(dev, crtc->pipe);
3303}
3304
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003305static void haswell_crtc_enable(struct drm_crtc *crtc)
3306{
3307 struct drm_device *dev = crtc->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3310 struct intel_encoder *encoder;
3311 int pipe = intel_crtc->pipe;
3312 int plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003313
3314 WARN_ON(!crtc->enabled);
3315
3316 if (intel_crtc->active)
3317 return;
3318
3319 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003320
3321 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3322 if (intel_crtc->config.has_pch_encoder)
3323 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3324
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003325 intel_update_watermarks(dev);
3326
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003327 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02003328 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003329
3330 for_each_encoder_on_crtc(dev, crtc, encoder)
3331 if (encoder->pre_enable)
3332 encoder->pre_enable(encoder);
3333
Paulo Zanoni1f544382012-10-24 11:32:00 -02003334 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003335
Jesse Barnesb074cec2013-04-25 12:55:02 -07003336 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003337
3338 /*
3339 * On ILK+ LUT must be loaded before the pipe is running but with
3340 * clocks enabled
3341 */
3342 intel_crtc_load_lut(crtc);
3343
Paulo Zanoni1f544382012-10-24 11:32:00 -02003344 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00003345 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003346
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003347 intel_enable_pipe(dev_priv, pipe,
3348 intel_crtc->config.has_pch_encoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003349 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003350 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003351 intel_crtc_update_cursor(crtc, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003352
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003353 hsw_enable_ips(intel_crtc);
3354
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003355 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003356 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003357
3358 mutex_lock(&dev->struct_mutex);
3359 intel_update_fbc(dev);
3360 mutex_unlock(&dev->struct_mutex);
3361
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003362 for_each_encoder_on_crtc(dev, crtc, encoder)
3363 encoder->enable(encoder);
3364
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003365 /*
3366 * There seems to be a race in PCH platform hw (at least on some
3367 * outputs) where an enabled pipe still completes any pageflip right
3368 * away (as if the pipe is off) instead of waiting for vblank. As soon
3369 * as the first vblank happend, everything works as expected. Hence just
3370 * wait for one vblank before returning to avoid strange things
3371 * happening.
3372 */
3373 intel_wait_for_vblank(dev, intel_crtc->pipe);
3374}
3375
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003376static void ironlake_pfit_disable(struct intel_crtc *crtc)
3377{
3378 struct drm_device *dev = crtc->base.dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 int pipe = crtc->pipe;
3381
3382 /* To avoid upsetting the power well on haswell only disable the pfit if
3383 * it's in use. The hw state code will make sure we get this right. */
3384 if (crtc->config.pch_pfit.size) {
3385 I915_WRITE(PF_CTL(pipe), 0);
3386 I915_WRITE(PF_WIN_POS(pipe), 0);
3387 I915_WRITE(PF_WIN_SZ(pipe), 0);
3388 }
3389}
3390
Jesse Barnes6be4a602010-09-10 10:26:01 -07003391static void ironlake_crtc_disable(struct drm_crtc *crtc)
3392{
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003396 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003397 int pipe = intel_crtc->pipe;
3398 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003399 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003400
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003401
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003402 if (!intel_crtc->active)
3403 return;
3404
Daniel Vetterea9d7582012-07-10 10:42:52 +02003405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->disable(encoder);
3407
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003408 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003409 drm_vblank_off(dev, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003410
Chris Wilson973d04f2011-07-08 12:22:37 +01003411 if (dev_priv->cfb_plane == plane)
3412 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003413
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003414 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003415 intel_disable_planes(crtc);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003416 intel_disable_plane(dev_priv, plane, pipe);
3417
Daniel Vetterd925c592013-06-05 13:34:04 +02003418 if (intel_crtc->config.has_pch_encoder)
3419 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3420
Jesse Barnesb24e7172011-01-04 15:09:30 -08003421 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003422
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003423 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003424
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->post_disable)
3427 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003428
Daniel Vetterd925c592013-06-05 13:34:04 +02003429 if (intel_crtc->config.has_pch_encoder) {
3430 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003431
Daniel Vetterd925c592013-06-05 13:34:04 +02003432 ironlake_disable_pch_transcoder(dev_priv, pipe);
3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003434
Daniel Vetterd925c592013-06-05 13:34:04 +02003435 if (HAS_PCH_CPT(dev)) {
3436 /* disable TRANS_DP_CTL */
3437 reg = TRANS_DP_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3440 TRANS_DP_PORT_SEL_MASK);
3441 temp |= TRANS_DP_PORT_SEL_NONE;
3442 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003443
Daniel Vetterd925c592013-06-05 13:34:04 +02003444 /* disable DPLL_SEL */
3445 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003446 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02003447 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003448 }
Daniel Vetterd925c592013-06-05 13:34:04 +02003449
3450 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003451 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02003452
3453 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003454 }
3455
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003456 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003457 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003458
3459 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003460 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003461 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003462}
3463
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003464static void haswell_crtc_disable(struct drm_crtc *crtc)
3465{
3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3469 struct intel_encoder *encoder;
3470 int pipe = intel_crtc->pipe;
3471 int plane = intel_crtc->plane;
Daniel Vetter3b117c82013-04-17 20:15:07 +02003472 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003473
3474 if (!intel_crtc->active)
3475 return;
3476
3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->disable(encoder);
3479
3480 intel_crtc_wait_for_pending_flips(crtc);
3481 drm_vblank_off(dev, pipe);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003482
Rodrigo Vivi891348b2013-05-06 19:37:36 -03003483 /* FBC must be disabled before disabling the plane on HSW. */
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003484 if (dev_priv->cfb_plane == plane)
3485 intel_disable_fbc(dev);
3486
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003487 hsw_disable_ips(intel_crtc);
3488
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003489 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003490 intel_disable_planes(crtc);
Rodrigo Vivi891348b2013-05-06 19:37:36 -03003491 intel_disable_plane(dev_priv, plane, pipe);
3492
Paulo Zanoni86642812013-04-12 17:57:57 -03003493 if (intel_crtc->config.has_pch_encoder)
3494 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003495 intel_disable_pipe(dev_priv, pipe);
3496
Paulo Zanoniad80a812012-10-24 16:06:19 -02003497 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003498
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003499 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003500
Paulo Zanoni1f544382012-10-24 11:32:00 -02003501 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003502
3503 for_each_encoder_on_crtc(dev, crtc, encoder)
3504 if (encoder->post_disable)
3505 encoder->post_disable(encoder);
3506
Daniel Vetter88adfff2013-03-28 10:42:01 +01003507 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003508 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03003509 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003510 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003511 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003512
3513 intel_crtc->active = false;
3514 intel_update_watermarks(dev);
3515
3516 mutex_lock(&dev->struct_mutex);
3517 intel_update_fbc(dev);
3518 mutex_unlock(&dev->struct_mutex);
3519}
3520
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003521static void ironlake_crtc_off(struct drm_crtc *crtc)
3522{
3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003524 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003525}
3526
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003527static void haswell_crtc_off(struct drm_crtc *crtc)
3528{
3529 intel_ddi_put_crtc_pll(crtc);
3530}
3531
Daniel Vetter02e792f2009-09-15 22:57:34 +02003532static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3533{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003534 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003535 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003536 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003537
Chris Wilson23f09ce2010-08-12 13:53:37 +01003538 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003539 dev_priv->mm.interruptible = false;
3540 (void) intel_overlay_switch_off(intel_crtc->overlay);
3541 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003542 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003543 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003544
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003545 /* Let userspace switch the overlay on again. In most cases userspace
3546 * has to recompute where to put it anyway.
3547 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003548}
3549
Egbert Eich61bc95c2013-03-04 09:24:38 -05003550/**
3551 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3552 * cursor plane briefly if not already running after enabling the display
3553 * plane.
3554 * This workaround avoids occasional blank screens when self refresh is
3555 * enabled.
3556 */
3557static void
3558g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3559{
3560 u32 cntl = I915_READ(CURCNTR(pipe));
3561
3562 if ((cntl & CURSOR_MODE) == 0) {
3563 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3564
3565 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3566 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3567 intel_wait_for_vblank(dev_priv->dev, pipe);
3568 I915_WRITE(CURCNTR(pipe), cntl);
3569 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3570 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3571 }
3572}
3573
Jesse Barnes2dd24552013-04-25 12:55:01 -07003574static void i9xx_pfit_enable(struct intel_crtc *crtc)
3575{
3576 struct drm_device *dev = crtc->base.dev;
3577 struct drm_i915_private *dev_priv = dev->dev_private;
3578 struct intel_crtc_config *pipe_config = &crtc->config;
3579
Daniel Vetter328d8e82013-05-08 10:36:31 +02003580 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07003581 return;
3582
Daniel Vetterc0b03412013-05-28 12:05:54 +02003583 /*
3584 * The panel fitter should only be adjusted whilst the pipe is disabled,
3585 * according to register description and PRM.
3586 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07003587 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3588 assert_pipe_disabled(dev_priv, crtc->pipe);
3589
Jesse Barnesb074cec2013-04-25 12:55:02 -07003590 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3591 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02003592
3593 /* Border color in case we don't scale up to the full screen. Black by
3594 * default, change to something else for debugging. */
3595 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07003596}
3597
Jesse Barnes89b667f2013-04-18 14:51:36 -07003598static void valleyview_crtc_enable(struct drm_crtc *crtc)
3599{
3600 struct drm_device *dev = crtc->dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 struct intel_encoder *encoder;
3604 int pipe = intel_crtc->pipe;
3605 int plane = intel_crtc->plane;
3606
3607 WARN_ON(!crtc->enabled);
3608
3609 if (intel_crtc->active)
3610 return;
3611
3612 intel_crtc->active = true;
3613 intel_update_watermarks(dev);
3614
3615 mutex_lock(&dev_priv->dpio_lock);
3616
3617 for_each_encoder_on_crtc(dev, crtc, encoder)
3618 if (encoder->pre_pll_enable)
3619 encoder->pre_pll_enable(encoder);
3620
Daniel Vetter87442f72013-06-06 00:52:17 +02003621 vlv_enable_pll(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07003622
3623 for_each_encoder_on_crtc(dev, crtc, encoder)
3624 if (encoder->pre_enable)
3625 encoder->pre_enable(encoder);
3626
3627 /* VLV wants encoder enabling _before_ the pipe is up. */
3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 encoder->enable(encoder);
3630
Jesse Barnes2dd24552013-04-25 12:55:01 -07003631 i9xx_pfit_enable(intel_crtc);
3632
Ville Syrjälä63cbb072013-06-04 13:48:59 +03003633 intel_crtc_load_lut(crtc);
3634
Jesse Barnes89b667f2013-04-18 14:51:36 -07003635 intel_enable_pipe(dev_priv, pipe, false);
3636 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003637 intel_enable_planes(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07003638 intel_crtc_update_cursor(crtc, true);
3639
Ville Syrjäläf440eb12013-06-04 13:49:01 +03003640 intel_update_fbc(dev);
3641
Jesse Barnes89b667f2013-04-18 14:51:36 -07003642 mutex_unlock(&dev_priv->dpio_lock);
3643}
3644
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003645static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003646{
3647 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003650 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003651 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003652 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003653
Daniel Vetter08a48462012-07-02 11:43:47 +02003654 WARN_ON(!crtc->enabled);
3655
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003656 if (intel_crtc->active)
3657 return;
3658
3659 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003660 intel_update_watermarks(dev);
3661
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02003662 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02003663 if (encoder->pre_enable)
3664 encoder->pre_enable(encoder);
3665
Daniel Vetterf6736a12013-06-05 13:34:30 +02003666 i9xx_enable_pll(intel_crtc);
3667
Jesse Barnes2dd24552013-04-25 12:55:01 -07003668 i9xx_pfit_enable(intel_crtc);
3669
Ville Syrjälä63cbb072013-06-04 13:48:59 +03003670 intel_crtc_load_lut(crtc);
3671
Jesse Barnes040484a2011-01-03 12:14:26 -08003672 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003673 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003674 intel_enable_planes(crtc);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03003675 /* The fixup needs to happen before cursor is enabled */
Egbert Eich61bc95c2013-03-04 09:24:38 -05003676 if (IS_G4X(dev))
3677 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03003678 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003679
3680 /* Give the overlay scaler a chance to enable if it's on this pipe */
3681 intel_crtc_dpms_overlay(intel_crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003682
Ville Syrjäläf440eb12013-06-04 13:49:01 +03003683 intel_update_fbc(dev);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003684
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003685 for_each_encoder_on_crtc(dev, crtc, encoder)
3686 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003687}
3688
Daniel Vetter87476d62013-04-11 16:29:06 +02003689static void i9xx_pfit_disable(struct intel_crtc *crtc)
3690{
3691 struct drm_device *dev = crtc->base.dev;
3692 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02003693
3694 if (!crtc->config.gmch_pfit.control)
3695 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02003696
3697 assert_pipe_disabled(dev_priv, crtc->pipe);
3698
Daniel Vetter328d8e82013-05-08 10:36:31 +02003699 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3700 I915_READ(PFIT_CONTROL));
3701 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02003702}
3703
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003704static void i9xx_crtc_disable(struct drm_crtc *crtc)
3705{
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003709 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003710 int pipe = intel_crtc->pipe;
3711 int plane = intel_crtc->plane;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003712
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003713 if (!intel_crtc->active)
3714 return;
3715
Daniel Vetterea9d7582012-07-10 10:42:52 +02003716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->disable(encoder);
3718
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003719 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003720 intel_crtc_wait_for_pending_flips(crtc);
3721 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003722
Chris Wilson973d04f2011-07-08 12:22:37 +01003723 if (dev_priv->cfb_plane == plane)
3724 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003725
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003726 intel_crtc_dpms_overlay(intel_crtc, false);
3727 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003728 intel_disable_planes(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003729 intel_disable_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003730
Jesse Barnesb24e7172011-01-04 15:09:30 -08003731 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003732
Daniel Vetter87476d62013-04-11 16:29:06 +02003733 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003734
Jesse Barnes89b667f2013-04-18 14:51:36 -07003735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 if (encoder->post_disable)
3737 encoder->post_disable(encoder);
3738
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003739 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003740
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003741 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003742 intel_update_fbc(dev);
3743 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003744}
3745
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003746static void i9xx_crtc_off(struct drm_crtc *crtc)
3747{
3748}
3749
Daniel Vetter976f8a22012-07-08 22:34:21 +02003750static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3751 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003752{
3753 struct drm_device *dev = crtc->dev;
3754 struct drm_i915_master_private *master_priv;
3755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003757
3758 if (!dev->primary->master)
3759 return;
3760
3761 master_priv = dev->primary->master->driver_priv;
3762 if (!master_priv->sarea_priv)
3763 return;
3764
Jesse Barnes79e53942008-11-07 14:24:08 -08003765 switch (pipe) {
3766 case 0:
3767 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3768 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3769 break;
3770 case 1:
3771 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3772 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3773 break;
3774 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003775 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003776 break;
3777 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003778}
3779
Daniel Vetter976f8a22012-07-08 22:34:21 +02003780/**
3781 * Sets the power management mode of the pipe and plane.
3782 */
3783void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01003784{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003785 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003786 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003787 struct intel_encoder *intel_encoder;
3788 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003789
Daniel Vetter976f8a22012-07-08 22:34:21 +02003790 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3791 enable |= intel_encoder->connectors_active;
3792
3793 if (enable)
3794 dev_priv->display.crtc_enable(crtc);
3795 else
3796 dev_priv->display.crtc_disable(crtc);
3797
3798 intel_crtc_update_sarea(crtc, enable);
3799}
3800
Daniel Vetter976f8a22012-07-08 22:34:21 +02003801static void intel_crtc_disable(struct drm_crtc *crtc)
3802{
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_connector *connector;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08003806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003807
3808 /* crtc should still be enabled when we disable it. */
3809 WARN_ON(!crtc->enabled);
3810
3811 dev_priv->display.crtc_disable(crtc);
Paulo Zanonic77bf562013-05-03 12:15:40 -03003812 intel_crtc->eld_vld = false;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003813 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003814 dev_priv->display.off(crtc);
3815
Chris Wilson931872f2012-01-16 23:01:13 +00003816 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3817 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003818
3819 if (crtc->fb) {
3820 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003821 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003822 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003823 crtc->fb = NULL;
3824 }
3825
3826 /* Update computed state. */
3827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3828 if (!connector->encoder || !connector->encoder->crtc)
3829 continue;
3830
3831 if (connector->encoder->crtc != crtc)
3832 continue;
3833
3834 connector->dpms = DRM_MODE_DPMS_OFF;
3835 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003836 }
3837}
3838
Daniel Vettera261b242012-07-26 19:21:47 +02003839void intel_modeset_disable(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003840{
Daniel Vettera261b242012-07-26 19:21:47 +02003841 struct drm_crtc *crtc;
3842
3843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3844 if (crtc->enabled)
3845 intel_crtc_disable(crtc);
3846 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003847}
3848
Chris Wilsonea5b2132010-08-04 13:50:23 +01003849void intel_encoder_destroy(struct drm_encoder *encoder)
3850{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003851 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003852
Chris Wilsonea5b2132010-08-04 13:50:23 +01003853 drm_encoder_cleanup(encoder);
3854 kfree(intel_encoder);
3855}
3856
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003857/* Simple dpms helper for encodres with just one connector, no cloning and only
3858 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3859 * state of the entire output pipe. */
3860void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3861{
3862 if (mode == DRM_MODE_DPMS_ON) {
3863 encoder->connectors_active = true;
3864
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003865 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003866 } else {
3867 encoder->connectors_active = false;
3868
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003869 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003870 }
3871}
3872
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003873/* Cross check the actual hw state with our own modeset state tracking (and it's
3874 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02003875static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003876{
3877 if (connector->get_hw_state(connector)) {
3878 struct intel_encoder *encoder = connector->encoder;
3879 struct drm_crtc *crtc;
3880 bool encoder_enabled;
3881 enum pipe pipe;
3882
3883 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3884 connector->base.base.id,
3885 drm_get_connector_name(&connector->base));
3886
3887 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3888 "wrong connector dpms state\n");
3889 WARN(connector->base.encoder != &encoder->base,
3890 "active connector not linked to encoder\n");
3891 WARN(!encoder->connectors_active,
3892 "encoder->connectors_active not set\n");
3893
3894 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3895 WARN(!encoder_enabled, "encoder not enabled\n");
3896 if (WARN_ON(!encoder->base.crtc))
3897 return;
3898
3899 crtc = encoder->base.crtc;
3900
3901 WARN(!crtc->enabled, "crtc not enabled\n");
3902 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3903 WARN(pipe != to_intel_crtc(crtc)->pipe,
3904 "encoder active on the wrong pipe\n");
3905 }
3906}
3907
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003908/* Even simpler default implementation, if there's really no special case to
3909 * consider. */
3910void intel_connector_dpms(struct drm_connector *connector, int mode)
3911{
3912 struct intel_encoder *encoder = intel_attached_encoder(connector);
3913
3914 /* All the simple cases only support two dpms states. */
3915 if (mode != DRM_MODE_DPMS_ON)
3916 mode = DRM_MODE_DPMS_OFF;
3917
3918 if (mode == connector->dpms)
3919 return;
3920
3921 connector->dpms = mode;
3922
3923 /* Only need to change hw state when actually enabled */
3924 if (encoder->base.crtc)
3925 intel_encoder_dpms(encoder, mode);
3926 else
Daniel Vetter8af6cf82012-07-10 09:50:11 +02003927 WARN_ON(encoder->connectors_active != false);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003928
Daniel Vetterb9805142012-08-31 17:37:33 +02003929 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003930}
3931
Daniel Vetterf0947c32012-07-02 13:10:34 +02003932/* Simple connector->get_hw_state implementation for encoders that support only
3933 * one connector and no cloning and hence the encoder state determines the state
3934 * of the connector. */
3935bool intel_connector_get_hw_state(struct intel_connector *connector)
3936{
Daniel Vetter24929352012-07-02 20:28:59 +02003937 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02003938 struct intel_encoder *encoder = connector->encoder;
3939
3940 return encoder->get_hw_state(encoder, &pipe);
3941}
3942
Daniel Vetter1857e1d2013-04-29 19:34:16 +02003943static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3944 struct intel_crtc_config *pipe_config)
3945{
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *pipe_B_crtc =
3948 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3949
3950 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3951 pipe_name(pipe), pipe_config->fdi_lanes);
3952 if (pipe_config->fdi_lanes > 4) {
3953 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3954 pipe_name(pipe), pipe_config->fdi_lanes);
3955 return false;
3956 }
3957
3958 if (IS_HASWELL(dev)) {
3959 if (pipe_config->fdi_lanes > 2) {
3960 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3961 pipe_config->fdi_lanes);
3962 return false;
3963 } else {
3964 return true;
3965 }
3966 }
3967
3968 if (INTEL_INFO(dev)->num_pipes == 2)
3969 return true;
3970
3971 /* Ivybridge 3 pipe is really complicated */
3972 switch (pipe) {
3973 case PIPE_A:
3974 return true;
3975 case PIPE_B:
3976 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3977 pipe_config->fdi_lanes > 2) {
3978 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3979 pipe_name(pipe), pipe_config->fdi_lanes);
3980 return false;
3981 }
3982 return true;
3983 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01003984 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02003985 pipe_B_crtc->config.fdi_lanes <= 2) {
3986 if (pipe_config->fdi_lanes > 2) {
3987 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3988 pipe_name(pipe), pipe_config->fdi_lanes);
3989 return false;
3990 }
3991 } else {
3992 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3993 return false;
3994 }
3995 return true;
3996 default:
3997 BUG();
3998 }
3999}
4000
Daniel Vettere29c22c2013-02-21 00:00:16 +01004001#define RETRY 1
4002static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4003 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02004004{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004005 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004006 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02004007 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01004008 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004009
Daniel Vettere29c22c2013-02-21 00:00:16 +01004010retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02004011 /* FDI is a binary signal running at ~2.7GHz, encoding
4012 * each output octet as 10 bits. The actual frequency
4013 * is stored as a divider into a 100MHz clock, and the
4014 * mode pixel clock is stored in units of 1KHz.
4015 * Hence the bw of each lane in terms of the mode signal
4016 * is:
4017 */
4018 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4019
Daniel Vetterff9a6752013-06-01 17:16:21 +02004020 fdi_dotclock = adjusted_mode->clock;
Daniel Vetteref1b4602013-06-01 17:17:04 +02004021 fdi_dotclock /= pipe_config->pixel_multiplier;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004022
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004023 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004024 pipe_config->pipe_bpp);
4025
4026 pipe_config->fdi_lanes = lane;
4027
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004028 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004029 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004030
Daniel Vettere29c22c2013-02-21 00:00:16 +01004031 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4032 intel_crtc->pipe, pipe_config);
4033 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4034 pipe_config->pipe_bpp -= 2*3;
4035 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4036 pipe_config->pipe_bpp);
4037 needs_recompute = true;
4038 pipe_config->bw_constrained = true;
4039
4040 goto retry;
4041 }
4042
4043 if (needs_recompute)
4044 return RETRY;
4045
4046 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004047}
4048
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004049static void hsw_compute_ips_config(struct intel_crtc *crtc,
4050 struct intel_crtc_config *pipe_config)
4051{
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03004052 pipe_config->ips_enabled = i915_enable_ips &&
4053 hsw_crtc_supports_ips(crtc) &&
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004054 pipe_config->pipe_bpp == 24;
4055}
4056
Daniel Vettera43f6e02013-06-07 23:10:32 +02004057static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01004058 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08004059{
Daniel Vettera43f6e02013-06-07 23:10:32 +02004060 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004061 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01004062
Eric Anholtbad720f2009-10-22 16:11:14 -07004063 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004064 /* FDI link clock is fixed at 2.7G */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004065 if (pipe_config->requested_mode.clock * 3
4066 > IRONLAKE_FDI_FREQ * 4)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004067 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004068 }
Chris Wilson89749352010-09-12 18:25:19 +01004069
Daniel Vetterf9bef082012-04-15 19:53:19 +02004070 /* All interlaced capable intel hw wants timings in frames. Note though
4071 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4072 * timings, so we need to be careful not to clobber these.*/
Daniel Vetter7ae89232013-03-27 00:44:52 +01004073 if (!pipe_config->timings_set)
Daniel Vetterf9bef082012-04-15 19:53:19 +02004074 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01004075
Damien Lespiau8693a822013-05-03 18:48:11 +01004076 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4077 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03004078 */
4079 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4080 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004081 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03004082
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004083 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004084 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004085 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004086 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4087 * for lvds. */
4088 pipe_config->pipe_bpp = 8*3;
4089 }
4090
Damien Lespiauf5adf942013-06-24 18:29:34 +01004091 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02004092 hsw_compute_ips_config(crtc, pipe_config);
4093
4094 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4095 * clock survives for now. */
4096 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4097 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004098
Daniel Vetter877d48d2013-04-19 11:24:43 +02004099 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02004100 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02004101
Daniel Vettere29c22c2013-02-21 00:00:16 +01004102 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004103}
4104
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07004105static int valleyview_get_display_clock_speed(struct drm_device *dev)
4106{
4107 return 400000; /* FIXME */
4108}
4109
Jesse Barnese70236a2009-09-21 10:42:27 -07004110static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08004111{
Jesse Barnese70236a2009-09-21 10:42:27 -07004112 return 400000;
4113}
Jesse Barnes79e53942008-11-07 14:24:08 -08004114
Jesse Barnese70236a2009-09-21 10:42:27 -07004115static int i915_get_display_clock_speed(struct drm_device *dev)
4116{
4117 return 333000;
4118}
Jesse Barnes79e53942008-11-07 14:24:08 -08004119
Jesse Barnese70236a2009-09-21 10:42:27 -07004120static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4121{
4122 return 200000;
4123}
Jesse Barnes79e53942008-11-07 14:24:08 -08004124
Jesse Barnese70236a2009-09-21 10:42:27 -07004125static int i915gm_get_display_clock_speed(struct drm_device *dev)
4126{
4127 u16 gcfgc = 0;
4128
4129 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4130
4131 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08004132 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07004133 else {
4134 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4135 case GC_DISPLAY_CLOCK_333_MHZ:
4136 return 333000;
4137 default:
4138 case GC_DISPLAY_CLOCK_190_200_MHZ:
4139 return 190000;
4140 }
4141 }
4142}
Jesse Barnes79e53942008-11-07 14:24:08 -08004143
Jesse Barnese70236a2009-09-21 10:42:27 -07004144static int i865_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 266000;
4147}
4148
4149static int i855_get_display_clock_speed(struct drm_device *dev)
4150{
4151 u16 hpllcc = 0;
4152 /* Assume that the hardware is in the high speed state. This
4153 * should be the default.
4154 */
4155 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4156 case GC_CLOCK_133_200:
4157 case GC_CLOCK_100_200:
4158 return 200000;
4159 case GC_CLOCK_166_250:
4160 return 250000;
4161 case GC_CLOCK_100_133:
4162 return 133000;
4163 }
4164
4165 /* Shouldn't happen */
4166 return 0;
4167}
4168
4169static int i830_get_display_clock_speed(struct drm_device *dev)
4170{
4171 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004172}
4173
Zhenyu Wang2c072452009-06-05 15:38:42 +08004174static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004175intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004176{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004177 while (*num > DATA_LINK_M_N_MASK ||
4178 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004179 *num >>= 1;
4180 *den >>= 1;
4181 }
4182}
4183
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004184static void compute_m_n(unsigned int m, unsigned int n,
4185 uint32_t *ret_m, uint32_t *ret_n)
4186{
4187 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4188 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4189 intel_reduce_m_n_ratio(ret_m, ret_n);
4190}
4191
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004192void
4193intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4194 int pixel_clock, int link_clock,
4195 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004196{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004197 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004198
4199 compute_m_n(bits_per_pixel * pixel_clock,
4200 link_clock * nlanes * 8,
4201 &m_n->gmch_m, &m_n->gmch_n);
4202
4203 compute_m_n(pixel_clock, link_clock,
4204 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004205}
4206
Chris Wilsona7615032011-01-12 17:04:08 +00004207static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4208{
Keith Packard72bbe582011-09-26 16:09:45 -07004209 if (i915_panel_use_ssc >= 0)
4210 return i915_panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004211 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004212 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004213}
4214
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004215static int vlv_get_refclk(struct drm_crtc *crtc)
4216{
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 int refclk = 27000; /* for DP & HDMI */
4220
4221 return 100000; /* only one validated so far */
4222
4223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4224 refclk = 96000;
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 if (intel_panel_use_ssc(dev_priv))
4227 refclk = 100000;
4228 else
4229 refclk = 96000;
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4231 refclk = 100000;
4232 }
4233
4234 return refclk;
4235}
4236
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004237static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4238{
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 int refclk;
4242
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004243 if (IS_VALLEYVIEW(dev)) {
4244 refclk = vlv_get_refclk(crtc);
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004246 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004247 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4249 refclk / 1000);
4250 } else if (!IS_GEN2(dev)) {
4251 refclk = 96000;
4252 } else {
4253 refclk = 48000;
4254 }
4255
4256 return refclk;
4257}
4258
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004259static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004260{
Daniel Vetter7df00d72013-05-21 21:54:55 +02004261 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004262}
Daniel Vetterf47709a2013-03-28 10:42:02 +01004263
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004264static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4265{
4266 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004267}
4268
Daniel Vetterf47709a2013-03-28 10:42:02 +01004269static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08004270 intel_clock_t *reduced_clock)
4271{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004272 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004273 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004274 int pipe = crtc->pipe;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004275 u32 fp, fp2 = 0;
4276
4277 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004278 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004279 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004280 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004281 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004282 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004283 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004284 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004285 }
4286
4287 I915_WRITE(FP0(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004288 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004289
Daniel Vetterf47709a2013-03-28 10:42:02 +01004290 crtc->lowfreq_avail = false;
4291 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jesse Barnesa7516a02011-12-15 12:30:37 -08004292 reduced_clock && i915_powersave) {
4293 I915_WRITE(FP1(pipe), fp2);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004294 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004295 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004296 } else {
4297 I915_WRITE(FP1(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004298 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004299 }
4300}
4301
Jesse Barnes89b667f2013-04-18 14:51:36 -07004302static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4303{
4304 u32 reg_val;
4305
4306 /*
4307 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4308 * and set it to a reasonable value instead.
4309 */
Jani Nikulaae992582013-05-22 15:36:19 +03004310 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004311 reg_val &= 0xffffff00;
4312 reg_val |= 0x00000030;
Jani Nikulaae992582013-05-22 15:36:19 +03004313 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004314
Jani Nikulaae992582013-05-22 15:36:19 +03004315 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004316 reg_val &= 0x8cffffff;
4317 reg_val = 0x8c000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004318 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004319
Jani Nikulaae992582013-05-22 15:36:19 +03004320 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004321 reg_val &= 0xffffff00;
Jani Nikulaae992582013-05-22 15:36:19 +03004322 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004323
Jani Nikulaae992582013-05-22 15:36:19 +03004324 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004325 reg_val &= 0x00ffffff;
4326 reg_val |= 0xb0000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004327 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004328}
4329
Daniel Vetterb5518422013-05-03 11:49:48 +02004330static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4331 struct intel_link_m_n *m_n)
4332{
4333 struct drm_device *dev = crtc->base.dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 int pipe = crtc->pipe;
4336
Daniel Vettere3b95f12013-05-03 11:49:49 +02004337 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4338 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4339 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4340 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004341}
4342
4343static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4344 struct intel_link_m_n *m_n)
4345{
4346 struct drm_device *dev = crtc->base.dev;
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 int pipe = crtc->pipe;
4349 enum transcoder transcoder = crtc->config.cpu_transcoder;
4350
4351 if (INTEL_INFO(dev)->gen >= 5) {
4352 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4353 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4354 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4355 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4356 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02004357 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4359 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4360 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004361 }
4362}
4363
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004364static void intel_dp_set_m_n(struct intel_crtc *crtc)
4365{
4366 if (crtc->config.has_pch_encoder)
4367 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4368 else
4369 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4370}
4371
Daniel Vetterf47709a2013-03-28 10:42:02 +01004372static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004373{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004374 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004375 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004376 struct intel_encoder *encoder;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004377 int pipe = crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004378 u32 dpll, mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004379 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004380 bool is_hdmi;
Daniel Vetter198a037f2013-04-19 11:14:37 +02004381 u32 coreclk, reg_val, dpll_md;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004382
Daniel Vetter09153002012-12-12 14:06:44 +01004383 mutex_lock(&dev_priv->dpio_lock);
4384
Jesse Barnes89b667f2013-04-18 14:51:36 -07004385 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004386
Daniel Vetterf47709a2013-03-28 10:42:02 +01004387 bestn = crtc->config.dpll.n;
4388 bestm1 = crtc->config.dpll.m1;
4389 bestm2 = crtc->config.dpll.m2;
4390 bestp1 = crtc->config.dpll.p1;
4391 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004392
Jesse Barnes89b667f2013-04-18 14:51:36 -07004393 /* See eDP HDMI DPIO driver vbios notes doc */
4394
4395 /* PLL B needs special handling */
4396 if (pipe)
4397 vlv_pllb_recal_opamp(dev_priv);
4398
4399 /* Set up Tx target for periodic Rcomp update */
Jani Nikulaae992582013-05-22 15:36:19 +03004400 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004401
4402 /* Disable target IRef on PLL */
Jani Nikulaae992582013-05-22 15:36:19 +03004403 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004404 reg_val &= 0x00ffffff;
Jani Nikulaae992582013-05-22 15:36:19 +03004405 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004406
4407 /* Disable fast lock */
Jani Nikulaae992582013-05-22 15:36:19 +03004408 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004409
4410 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004411 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4412 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4413 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004414 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07004415
4416 /*
4417 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4418 * but we don't support that).
4419 * Note: don't use the DAC post divider as it seems unstable.
4420 */
4421 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Jani Nikulaae992582013-05-22 15:36:19 +03004422 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004423
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004424 mdiv |= DPIO_ENABLE_CALIBRATION;
Jani Nikulaae992582013-05-22 15:36:19 +03004425 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004426
Jesse Barnes89b667f2013-04-18 14:51:36 -07004427 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02004428 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03004429 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07004430 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Ville Syrjälä4abb2c32013-06-14 14:02:53 +03004431 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004432 0x005f0021);
4433 else
Ville Syrjälä4abb2c32013-06-14 14:02:53 +03004434 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004435 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004436
Jesse Barnes89b667f2013-04-18 14:51:36 -07004437 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4438 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4439 /* Use SSC source */
4440 if (!pipe)
Jani Nikulaae992582013-05-22 15:36:19 +03004441 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004442 0x0df40000);
4443 else
Jani Nikulaae992582013-05-22 15:36:19 +03004444 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004445 0x0df70000);
4446 } else { /* HDMI or VGA */
4447 /* Use bend source */
4448 if (!pipe)
Jani Nikulaae992582013-05-22 15:36:19 +03004449 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004450 0x0df70000);
4451 else
Jani Nikulaae992582013-05-22 15:36:19 +03004452 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004453 0x0df40000);
4454 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004455
Jani Nikulaae992582013-05-22 15:36:19 +03004456 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004457 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4458 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4460 coreclk |= 0x01000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004461 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004462
Jani Nikulaae992582013-05-22 15:36:19 +03004463 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004464
4465 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4466 if (encoder->pre_pll_enable)
4467 encoder->pre_pll_enable(encoder);
4468
4469 /* Enable DPIO clock input */
4470 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4471 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4472 if (pipe)
4473 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004474
4475 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004476 crtc->config.dpll_hw_state.dpll = dpll;
4477
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004478 I915_WRITE(DPLL(pipe), dpll);
4479 POSTING_READ(DPLL(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004480 udelay(150);
4481
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004482 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4483 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4484
Daniel Vetteref1b4602013-06-01 17:17:04 +02004485 dpll_md = (crtc->config.pixel_multiplier - 1)
4486 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004487 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4488
Daniel Vetter198a037f2013-04-19 11:14:37 +02004489 I915_WRITE(DPLL_MD(pipe), dpll_md);
4490 POSTING_READ(DPLL_MD(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004491
Daniel Vetterf47709a2013-03-28 10:42:02 +01004492 if (crtc->config.has_dp_encoder)
4493 intel_dp_set_m_n(crtc);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304494
Daniel Vetter09153002012-12-12 14:06:44 +01004495 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004496}
4497
Daniel Vetterf47709a2013-03-28 10:42:02 +01004498static void i9xx_update_pll(struct intel_crtc *crtc,
4499 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004500 int num_connectors)
4501{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004502 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004503 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004504 u32 dpll;
4505 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004506 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004507
Daniel Vetterf47709a2013-03-28 10:42:02 +01004508 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304509
Daniel Vetterf47709a2013-03-28 10:42:02 +01004510 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4511 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004512
4513 dpll = DPLL_VGA_MODE_DIS;
4514
Daniel Vetterf47709a2013-03-28 10:42:02 +01004515 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004516 dpll |= DPLLB_MODE_LVDS;
4517 else
4518 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004519
Daniel Vetteref1b4602013-06-01 17:17:04 +02004520 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02004521 dpll |= (crtc->config.pixel_multiplier - 1)
4522 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004523 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02004524
4525 if (is_sdvo)
4526 dpll |= DPLL_DVO_HIGH_SPEED;
4527
Daniel Vetterf47709a2013-03-28 10:42:02 +01004528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004529 dpll |= DPLL_DVO_HIGH_SPEED;
4530
4531 /* compute bitmask from p1 value */
4532 if (IS_PINEVIEW(dev))
4533 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4534 else {
4535 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4536 if (IS_G4X(dev) && reduced_clock)
4537 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4538 }
4539 switch (clock->p2) {
4540 case 5:
4541 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4542 break;
4543 case 7:
4544 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4545 break;
4546 case 10:
4547 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4548 break;
4549 case 14:
4550 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4551 break;
4552 }
4553 if (INTEL_INFO(dev)->gen >= 4)
4554 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4555
Daniel Vetter09ede542013-04-30 14:01:45 +02004556 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004557 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004558 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004559 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4560 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4561 else
4562 dpll |= PLL_REF_INPUT_DREFCLK;
4563
4564 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004565 crtc->config.dpll_hw_state.dpll = dpll;
4566
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004567 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02004568 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4569 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004570 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004571 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004572
4573 if (crtc->config.has_dp_encoder)
4574 intel_dp_set_m_n(crtc);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004575}
4576
Daniel Vetterf47709a2013-03-28 10:42:02 +01004577static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01004578 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004579 int num_connectors)
4580{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004581 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004582 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004583 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004584 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004585
Daniel Vetterf47709a2013-03-28 10:42:02 +01004586 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304587
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004588 dpll = DPLL_VGA_MODE_DIS;
4589
Daniel Vetterf47709a2013-03-28 10:42:02 +01004590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 } else {
4593 if (clock->p1 == 2)
4594 dpll |= PLL_P1_DIVIDE_BY_TWO;
4595 else
4596 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 if (clock->p2 == 4)
4598 dpll |= PLL_P2_DIVIDE_BY_4;
4599 }
4600
Daniel Vetterf47709a2013-03-28 10:42:02 +01004601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604 else
4605 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004608 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004609}
4610
Daniel Vetter8a654f32013-06-01 17:16:22 +02004611static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004612{
4613 struct drm_device *dev = intel_crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004616 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02004617 struct drm_display_mode *adjusted_mode =
4618 &intel_crtc->config.adjusted_mode;
4619 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004620 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4621
4622 /* We need to be careful not to changed the adjusted mode, for otherwise
4623 * the hw state checker will get angry at the mismatch. */
4624 crtc_vtotal = adjusted_mode->crtc_vtotal;
4625 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004626
4627 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4628 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004629 crtc_vtotal -= 1;
4630 crtc_vblank_end -= 1;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004631 vsyncshift = adjusted_mode->crtc_hsync_start
4632 - adjusted_mode->crtc_htotal / 2;
4633 } else {
4634 vsyncshift = 0;
4635 }
4636
4637 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004638 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004639
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004640 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004641 (adjusted_mode->crtc_hdisplay - 1) |
4642 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004643 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004644 (adjusted_mode->crtc_hblank_start - 1) |
4645 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004646 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004647 (adjusted_mode->crtc_hsync_start - 1) |
4648 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4649
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004650 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004651 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004652 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004653 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004654 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004655 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004656 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004657 (adjusted_mode->crtc_vsync_start - 1) |
4658 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4659
Paulo Zanonib5e508d2012-10-24 11:34:43 -02004660 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4661 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4662 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4663 * bits. */
4664 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4665 (pipe == PIPE_B || pipe == PIPE_C))
4666 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4667
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004668 /* pipesrc controls the size that is scaled from, which should
4669 * always be the user's requested size.
4670 */
4671 I915_WRITE(PIPESRC(pipe),
4672 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4673}
4674
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004675static void intel_get_pipe_timings(struct intel_crtc *crtc,
4676 struct intel_crtc_config *pipe_config)
4677{
4678 struct drm_device *dev = crtc->base.dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4681 uint32_t tmp;
4682
4683 tmp = I915_READ(HTOTAL(cpu_transcoder));
4684 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4685 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4686 tmp = I915_READ(HBLANK(cpu_transcoder));
4687 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4688 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4689 tmp = I915_READ(HSYNC(cpu_transcoder));
4690 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4691 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4692
4693 tmp = I915_READ(VTOTAL(cpu_transcoder));
4694 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4695 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4696 tmp = I915_READ(VBLANK(cpu_transcoder));
4697 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4698 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4699 tmp = I915_READ(VSYNC(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4702
4703 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4704 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4705 pipe_config->adjusted_mode.crtc_vtotal += 1;
4706 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4707 }
4708
4709 tmp = I915_READ(PIPESRC(crtc->pipe));
4710 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4712}
4713
Daniel Vetter84b046f2013-02-19 18:48:54 +01004714static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4715{
4716 struct drm_device *dev = intel_crtc->base.dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 uint32_t pipeconf;
4719
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02004720 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004721
4722 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4723 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4724 * core speed.
4725 *
4726 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4727 * pipe == 0 check?
4728 */
4729 if (intel_crtc->config.requested_mode.clock >
4730 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4731 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004732 }
4733
Daniel Vetterff9ce462013-04-24 14:57:17 +02004734 /* only g4x and later have fancy bpc/dither controls */
4735 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02004736 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4737 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4738 pipeconf |= PIPECONF_DITHER_EN |
4739 PIPECONF_DITHER_TYPE_SP;
4740
4741 switch (intel_crtc->config.pipe_bpp) {
4742 case 18:
4743 pipeconf |= PIPECONF_6BPC;
4744 break;
4745 case 24:
4746 pipeconf |= PIPECONF_8BPC;
4747 break;
4748 case 30:
4749 pipeconf |= PIPECONF_10BPC;
4750 break;
4751 default:
4752 /* Case prevented by intel_choose_pipe_bpp_dither. */
4753 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01004754 }
4755 }
4756
4757 if (HAS_PIPE_CXSR(dev)) {
4758 if (intel_crtc->lowfreq_avail) {
4759 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4760 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4761 } else {
4762 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01004763 }
4764 }
4765
Daniel Vetter84b046f2013-02-19 18:48:54 +01004766 if (!IS_GEN2(dev) &&
4767 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4768 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4769 else
4770 pipeconf |= PIPECONF_PROGRESSIVE;
4771
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02004772 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4773 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03004774
Daniel Vetter84b046f2013-02-19 18:48:54 +01004775 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4776 POSTING_READ(PIPECONF(intel_crtc->pipe));
4777}
4778
Eric Anholtf564048e2011-03-30 13:01:02 -07004779static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07004780 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004781 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004782{
4783 struct drm_device *dev = crtc->dev;
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004786 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08004787 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004788 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004789 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004790 intel_clock_t clock, reduced_clock;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004791 u32 dspcntr;
Daniel Vettera16af7212013-04-30 14:01:44 +02004792 bool ok, has_reduced_clock = false;
4793 bool is_lvds = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004794 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004795 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004796 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004797
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004798 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004799 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004800 case INTEL_OUTPUT_LVDS:
4801 is_lvds = true;
4802 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004803 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004804
Eric Anholtc751ce42010-03-25 11:48:48 -07004805 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004806 }
4807
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004808 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004809
Ma Lingd4906092009-03-18 20:13:27 +08004810 /*
4811 * Returns a set of divisors for the desired target clock with the given
4812 * refclk, or FALSE. The returned values represent the clock equation:
4813 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4814 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004815 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02004816 ok = dev_priv->display.find_dpll(limit, crtc,
4817 intel_crtc->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02004818 refclk, NULL, &clock);
4819 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004820 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004821 return -EINVAL;
4822 }
4823
4824 /* Ensure that the cursor is valid for the new mode before changing... */
4825 intel_crtc_update_cursor(crtc, true);
4826
4827 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004828 /*
4829 * Ensure we match the reduced clock's P to the target clock.
4830 * If the clocks don't match, we can't switch the display clock
4831 * by using the FP0/FP1. In such case we will disable the LVDS
4832 * downclock feature.
4833 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02004834 has_reduced_clock =
4835 dev_priv->display.find_dpll(limit, crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07004836 dev_priv->lvds_downclock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02004837 refclk, &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004838 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004839 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01004840 /* Compat-code for transition, will disappear. */
4841 if (!intel_crtc->config.clock_set) {
4842 intel_crtc->config.dpll.n = clock.n;
4843 intel_crtc->config.dpll.m1 = clock.m1;
4844 intel_crtc->config.dpll.m2 = clock.m2;
4845 intel_crtc->config.dpll.p1 = clock.p1;
4846 intel_crtc->config.dpll.p2 = clock.p2;
4847 }
Eric Anholtf564048e2011-03-30 13:01:02 -07004848
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004849 if (IS_GEN2(dev))
Daniel Vetter8a654f32013-06-01 17:16:22 +02004850 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304851 has_reduced_clock ? &reduced_clock : NULL,
4852 num_connectors);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004853 else if (IS_VALLEYVIEW(dev))
Daniel Vetterf47709a2013-03-28 10:42:02 +01004854 vlv_update_pll(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07004855 else
Daniel Vetterf47709a2013-03-28 10:42:02 +01004856 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004857 has_reduced_clock ? &reduced_clock : NULL,
Jesse Barnes89b667f2013-04-18 14:51:36 -07004858 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004859
Eric Anholtf564048e2011-03-30 13:01:02 -07004860 /* Set up the display plane register */
4861 dspcntr = DISPPLANE_GAMMA_ENABLE;
4862
Jesse Barnesda6ecc52013-03-08 10:46:00 -08004863 if (!IS_VALLEYVIEW(dev)) {
4864 if (pipe == 0)
4865 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4866 else
4867 dspcntr |= DISPPLANE_SEL_PIPE_B;
4868 }
Eric Anholtf564048e2011-03-30 13:01:02 -07004869
Daniel Vetter8a654f32013-06-01 17:16:22 +02004870 intel_set_pipe_timings(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07004871
4872 /* pipesrc and dspsize control the size that is scaled from,
4873 * which should always be the user's requested size.
4874 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004875 I915_WRITE(DSPSIZE(plane),
4876 ((mode->vdisplay - 1) << 16) |
4877 (mode->hdisplay - 1));
4878 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004879
Daniel Vetter84b046f2013-02-19 18:48:54 +01004880 i9xx_set_pipeconf(intel_crtc);
4881
Eric Anholtf564048e2011-03-30 13:01:02 -07004882 I915_WRITE(DSPCNTR(plane), dspcntr);
4883 POSTING_READ(DSPCNTR(plane));
4884
Daniel Vetter94352cf2012-07-05 22:51:56 +02004885 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07004886
4887 intel_update_watermarks(dev);
4888
Eric Anholtf564048e2011-03-30 13:01:02 -07004889 return ret;
4890}
4891
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02004892static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4893 struct intel_crtc_config *pipe_config)
4894{
4895 struct drm_device *dev = crtc->base.dev;
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897 uint32_t tmp;
4898
4899 tmp = I915_READ(PFIT_CONTROL);
4900
4901 if (INTEL_INFO(dev)->gen < 4) {
4902 if (crtc->pipe != PIPE_B)
4903 return;
4904
4905 /* gen2/3 store dither state in pfit control, needs to match */
4906 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4907 } else {
4908 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4909 return;
4910 }
4911
4912 if (!(tmp & PFIT_ENABLE))
4913 return;
4914
4915 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4916 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4917 if (INTEL_INFO(dev)->gen < 5)
4918 pipe_config->gmch_pfit.lvds_border_bits =
4919 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4920}
4921
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01004922static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4923 struct intel_crtc_config *pipe_config)
4924{
4925 struct drm_device *dev = crtc->base.dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 uint32_t tmp;
4928
Daniel Vettereccb1402013-05-22 00:50:22 +02004929 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02004930 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02004931
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01004932 tmp = I915_READ(PIPECONF(crtc->pipe));
4933 if (!(tmp & PIPECONF_ENABLE))
4934 return false;
4935
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004936 intel_get_pipe_timings(crtc, pipe_config);
4937
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02004938 i9xx_get_pfit_config(crtc, pipe_config);
4939
Daniel Vetter6c49f242013-06-06 12:45:25 +02004940 if (INTEL_INFO(dev)->gen >= 4) {
4941 tmp = I915_READ(DPLL_MD(crtc->pipe));
4942 pipe_config->pixel_multiplier =
4943 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4944 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004945 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02004946 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4947 tmp = I915_READ(DPLL(crtc->pipe));
4948 pipe_config->pixel_multiplier =
4949 ((tmp & SDVO_MULTIPLIER_MASK)
4950 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4951 } else {
4952 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4953 * port and will be fixed up in the encoder->get_config
4954 * function. */
4955 pipe_config->pixel_multiplier = 1;
4956 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004957 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4958 if (!IS_VALLEYVIEW(dev)) {
4959 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4960 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
4961 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02004962
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01004963 return true;
4964}
4965
Paulo Zanonidde86e22012-12-01 12:04:25 -02004966static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004967{
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004970 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07004971 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004972 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004973 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004974 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004975 bool has_ck505 = false;
4976 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004977
4978 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004979 list_for_each_entry(encoder, &mode_config->encoder_list,
4980 base.head) {
4981 switch (encoder->type) {
4982 case INTEL_OUTPUT_LVDS:
4983 has_panel = true;
4984 has_lvds = true;
4985 break;
4986 case INTEL_OUTPUT_EDP:
4987 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03004988 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07004989 has_cpu_edp = true;
4990 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004991 }
4992 }
4993
Keith Packard99eb6a02011-09-26 14:29:12 -07004994 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004995 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07004996 can_ssc = has_ck505;
4997 } else {
4998 has_ck505 = false;
4999 can_ssc = true;
5000 }
5001
Imre Deak2de69052013-05-08 13:14:04 +03005002 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5003 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005004
5005 /* Ironlake: try to setup display ref clock before DPLL
5006 * enabling. This is only under driver's control after
5007 * PCH B stepping, previous chipset stepping should be
5008 * ignoring this setting.
5009 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005010 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005011
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005012 /* As we must carefully and slowly disable/enable each source in turn,
5013 * compute the final state we want first and check if we need to
5014 * make any changes at all.
5015 */
5016 final = val;
5017 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07005018 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005019 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07005020 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005021 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5022
5023 final &= ~DREF_SSC_SOURCE_MASK;
5024 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5025 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005026
Keith Packard199e5d72011-09-22 12:01:57 -07005027 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005028 final |= DREF_SSC_SOURCE_ENABLE;
5029
5030 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5031 final |= DREF_SSC1_ENABLE;
5032
5033 if (has_cpu_edp) {
5034 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5035 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5036 else
5037 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5038 } else
5039 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5040 } else {
5041 final |= DREF_SSC_SOURCE_DISABLE;
5042 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5043 }
5044
5045 if (final == val)
5046 return;
5047
5048 /* Always enable nonspread source */
5049 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5050
5051 if (has_ck505)
5052 val |= DREF_NONSPREAD_CK505_ENABLE;
5053 else
5054 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5055
5056 if (has_panel) {
5057 val &= ~DREF_SSC_SOURCE_MASK;
5058 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005059
Keith Packard199e5d72011-09-22 12:01:57 -07005060 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005061 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005062 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005063 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02005064 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005065 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005066
5067 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005068 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005069 POSTING_READ(PCH_DREF_CONTROL);
5070 udelay(200);
5071
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005072 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005073
5074 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005075 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005076 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005077 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005078 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005079 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005080 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005081 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005082 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005083 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005084
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005085 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005086 POSTING_READ(PCH_DREF_CONTROL);
5087 udelay(200);
5088 } else {
5089 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5090
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005091 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07005092
5093 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005094 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005095
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005096 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005097 POSTING_READ(PCH_DREF_CONTROL);
5098 udelay(200);
5099
5100 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005101 val &= ~DREF_SSC_SOURCE_MASK;
5102 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005103
5104 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005105 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005106
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005107 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005108 POSTING_READ(PCH_DREF_CONTROL);
5109 udelay(200);
5110 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005111
5112 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005113}
5114
Paulo Zanonidde86e22012-12-01 12:04:25 -02005115/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5116static void lpt_init_pch_refclk(struct drm_device *dev)
5117{
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct drm_mode_config *mode_config = &dev->mode_config;
5120 struct intel_encoder *encoder;
5121 bool has_vga = false;
5122 bool is_sdv = false;
5123 u32 tmp;
5124
5125 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5126 switch (encoder->type) {
5127 case INTEL_OUTPUT_ANALOG:
5128 has_vga = true;
5129 break;
5130 }
5131 }
5132
5133 if (!has_vga)
5134 return;
5135
Daniel Vetterc00db242013-01-22 15:33:27 +01005136 mutex_lock(&dev_priv->dpio_lock);
5137
Paulo Zanonidde86e22012-12-01 12:04:25 -02005138 /* XXX: Rip out SDV support once Haswell ships for real. */
5139 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5140 is_sdv = true;
5141
5142 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5143 tmp &= ~SBI_SSCCTL_DISABLE;
5144 tmp |= SBI_SSCCTL_PATHALT;
5145 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5146
5147 udelay(24);
5148
5149 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5150 tmp &= ~SBI_SSCCTL_PATHALT;
5151 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5152
5153 if (!is_sdv) {
5154 tmp = I915_READ(SOUTH_CHICKEN2);
5155 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5156 I915_WRITE(SOUTH_CHICKEN2, tmp);
5157
5158 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5159 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5160 DRM_ERROR("FDI mPHY reset assert timeout\n");
5161
5162 tmp = I915_READ(SOUTH_CHICKEN2);
5163 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5164 I915_WRITE(SOUTH_CHICKEN2, tmp);
5165
5166 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5167 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5168 100))
5169 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5170 }
5171
5172 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5173 tmp &= ~(0xFF << 24);
5174 tmp |= (0x12 << 24);
5175 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5176
Paulo Zanonidde86e22012-12-01 12:04:25 -02005177 if (is_sdv) {
5178 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5179 tmp |= 0x7FFF;
5180 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5181 }
5182
5183 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5184 tmp |= (1 << 11);
5185 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5186
5187 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5188 tmp |= (1 << 11);
5189 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5190
5191 if (is_sdv) {
5192 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5193 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5194 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5195
5196 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5197 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5198 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5199
5200 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5201 tmp |= (0x3F << 8);
5202 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5203
5204 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5205 tmp |= (0x3F << 8);
5206 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5207 }
5208
5209 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5210 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5211 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5214 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216
5217 if (!is_sdv) {
5218 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5219 tmp &= ~(7 << 13);
5220 tmp |= (5 << 13);
5221 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5224 tmp &= ~(7 << 13);
5225 tmp |= (5 << 13);
5226 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5227 }
5228
5229 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5230 tmp &= ~0xFF;
5231 tmp |= 0x1C;
5232 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5235 tmp &= ~0xFF;
5236 tmp |= 0x1C;
5237 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5240 tmp &= ~(0xFF << 16);
5241 tmp |= (0x1C << 16);
5242 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5245 tmp &= ~(0xFF << 16);
5246 tmp |= (0x1C << 16);
5247 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5248
5249 if (!is_sdv) {
5250 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5251 tmp |= (1 << 27);
5252 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5255 tmp |= (1 << 27);
5256 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5259 tmp &= ~(0xF << 28);
5260 tmp |= (4 << 28);
5261 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5264 tmp &= ~(0xF << 28);
5265 tmp |= (4 << 28);
5266 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5267 }
5268
5269 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5270 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5271 tmp |= SBI_DBUFF0_ENABLE;
5272 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01005273
5274 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005275}
5276
5277/*
5278 * Initialize reference clocks when the driver loads
5279 */
5280void intel_init_pch_refclk(struct drm_device *dev)
5281{
5282 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5283 ironlake_init_pch_refclk(dev);
5284 else if (HAS_PCH_LPT(dev))
5285 lpt_init_pch_refclk(dev);
5286}
5287
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005288static int ironlake_get_refclk(struct drm_crtc *crtc)
5289{
5290 struct drm_device *dev = crtc->dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005293 int num_connectors = 0;
5294 bool is_lvds = false;
5295
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005296 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005297 switch (encoder->type) {
5298 case INTEL_OUTPUT_LVDS:
5299 is_lvds = true;
5300 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005301 }
5302 num_connectors++;
5303 }
5304
5305 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5306 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005307 dev_priv->vbt.lvds_ssc_freq);
5308 return dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005309 }
5310
5311 return 120000;
5312}
5313
Daniel Vetter6ff93602013-04-19 11:24:36 +02005314static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03005315{
5316 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 int pipe = intel_crtc->pipe;
5319 uint32_t val;
5320
Daniel Vetter78114072013-06-13 00:54:57 +02005321 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03005322
Daniel Vetter965e0c42013-03-27 00:44:57 +01005323 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03005324 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005325 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005326 break;
5327 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005328 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005329 break;
5330 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005331 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005332 break;
5333 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005334 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005335 break;
5336 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005337 /* Case prevented by intel_choose_pipe_bpp_dither. */
5338 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005339 }
5340
Daniel Vetterd8b32242013-04-25 17:54:44 +02005341 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03005342 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5343
Daniel Vetter6ff93602013-04-19 11:24:36 +02005344 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03005345 val |= PIPECONF_INTERLACED_ILK;
5346 else
5347 val |= PIPECONF_PROGRESSIVE;
5348
Daniel Vetter50f3b012013-03-27 00:44:56 +01005349 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005350 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005351
Paulo Zanonic8203562012-09-12 10:06:29 -03005352 I915_WRITE(PIPECONF(pipe), val);
5353 POSTING_READ(PIPECONF(pipe));
5354}
5355
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005356/*
5357 * Set up the pipe CSC unit.
5358 *
5359 * Currently only full range RGB to limited range RGB conversion
5360 * is supported, but eventually this should handle various
5361 * RGB<->YCbCr scenarios as well.
5362 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01005363static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005364{
5365 struct drm_device *dev = crtc->dev;
5366 struct drm_i915_private *dev_priv = dev->dev_private;
5367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5368 int pipe = intel_crtc->pipe;
5369 uint16_t coeff = 0x7800; /* 1.0 */
5370
5371 /*
5372 * TODO: Check what kind of values actually come out of the pipe
5373 * with these coeff/postoff values and adjust to get the best
5374 * accuracy. Perhaps we even need to take the bpc value into
5375 * consideration.
5376 */
5377
Daniel Vetter50f3b012013-03-27 00:44:56 +01005378 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005379 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5380
5381 /*
5382 * GY/GU and RY/RU should be the other way around according
5383 * to BSpec, but reality doesn't agree. Just set them up in
5384 * a way that results in the correct picture.
5385 */
5386 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5387 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5388
5389 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5390 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5391
5392 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5393 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5394
5395 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5396 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5397 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5398
5399 if (INTEL_INFO(dev)->gen > 6) {
5400 uint16_t postoff = 0;
5401
Daniel Vetter50f3b012013-03-27 00:44:56 +01005402 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005403 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5404
5405 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5406 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5407 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5408
5409 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5410 } else {
5411 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5412
Daniel Vetter50f3b012013-03-27 00:44:56 +01005413 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005414 mode |= CSC_BLACK_SCREEN_OFFSET;
5415
5416 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5417 }
5418}
5419
Daniel Vetter6ff93602013-04-19 11:24:36 +02005420static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005421{
5422 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02005424 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005425 uint32_t val;
5426
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005427 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005428
Daniel Vetterd8b32242013-04-25 17:54:44 +02005429 if (intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005430 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5431
Daniel Vetter6ff93602013-04-19 11:24:36 +02005432 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005433 val |= PIPECONF_INTERLACED_ILK;
5434 else
5435 val |= PIPECONF_PROGRESSIVE;
5436
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005437 I915_WRITE(PIPECONF(cpu_transcoder), val);
5438 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005439
5440 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5441 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005442}
5443
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005444static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005445 intel_clock_t *clock,
5446 bool *has_reduced_clock,
5447 intel_clock_t *reduced_clock)
5448{
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct intel_encoder *intel_encoder;
5452 int refclk;
5453 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02005454 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005455
5456 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5457 switch (intel_encoder->type) {
5458 case INTEL_OUTPUT_LVDS:
5459 is_lvds = true;
5460 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005461 }
5462 }
5463
5464 refclk = ironlake_get_refclk(crtc);
5465
5466 /*
5467 * Returns a set of divisors for the desired target clock with the given
5468 * refclk, or FALSE. The returned values represent the clock equation:
5469 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5470 */
5471 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02005472 ret = dev_priv->display.find_dpll(limit, crtc,
5473 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02005474 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005475 if (!ret)
5476 return false;
5477
5478 if (is_lvds && dev_priv->lvds_downclock_avail) {
5479 /*
5480 * Ensure we match the reduced clock's P to the target clock.
5481 * If the clocks don't match, we can't switch the display clock
5482 * by using the FP0/FP1. In such case we will disable the LVDS
5483 * downclock feature.
5484 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02005485 *has_reduced_clock =
5486 dev_priv->display.find_dpll(limit, crtc,
5487 dev_priv->lvds_downclock,
5488 refclk, clock,
5489 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005490 }
5491
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005492 return true;
5493}
5494
Daniel Vetter01a415f2012-10-27 15:58:40 +02005495static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5496{
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 uint32_t temp;
5499
5500 temp = I915_READ(SOUTH_CHICKEN1);
5501 if (temp & FDI_BC_BIFURCATION_SELECT)
5502 return;
5503
5504 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5505 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5506
5507 temp |= FDI_BC_BIFURCATION_SELECT;
5508 DRM_DEBUG_KMS("enabling fdi C rx\n");
5509 I915_WRITE(SOUTH_CHICKEN1, temp);
5510 POSTING_READ(SOUTH_CHICKEN1);
5511}
5512
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005513static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
Daniel Vetter01a415f2012-10-27 15:58:40 +02005514{
5515 struct drm_device *dev = intel_crtc->base.dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005517
5518 switch (intel_crtc->pipe) {
5519 case PIPE_A:
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005520 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005521 case PIPE_B:
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005522 if (intel_crtc->config.fdi_lanes > 2)
Daniel Vetter01a415f2012-10-27 15:58:40 +02005523 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5524 else
5525 cpt_enable_fdi_bc_bifurcation(dev);
5526
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005527 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005528 case PIPE_C:
Daniel Vetter01a415f2012-10-27 15:58:40 +02005529 cpt_enable_fdi_bc_bifurcation(dev);
5530
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005531 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005532 default:
5533 BUG();
5534 }
5535}
5536
Paulo Zanonid4b19312012-11-29 11:29:32 -02005537int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5538{
5539 /*
5540 * Account for spread spectrum to avoid
5541 * oversubscribing the link. Max center spread
5542 * is 2.5%; use 5% for safety's sake.
5543 */
5544 u32 bps = target_clock * bpp * 21 / 20;
5545 return bps / (link_bw * 8) + 1;
5546}
5547
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005548static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005549{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005550 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005551}
5552
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005553static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005554 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02005555 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005556{
5557 struct drm_crtc *crtc = &intel_crtc->base;
5558 struct drm_device *dev = crtc->dev;
5559 struct drm_i915_private *dev_priv = dev->dev_private;
5560 struct intel_encoder *intel_encoder;
5561 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005562 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02005563 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005564
5565 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5566 switch (intel_encoder->type) {
5567 case INTEL_OUTPUT_LVDS:
5568 is_lvds = true;
5569 break;
5570 case INTEL_OUTPUT_SDVO:
5571 case INTEL_OUTPUT_HDMI:
5572 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005573 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005574 }
5575
5576 num_connectors++;
5577 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005578
Chris Wilsonc1858122010-12-03 21:35:48 +00005579 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005580 factor = 21;
5581 if (is_lvds) {
5582 if ((intel_panel_use_ssc(dev_priv) &&
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005583 dev_priv->vbt.lvds_ssc_freq == 100) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02005584 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07005585 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02005586 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07005587 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005588
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005589 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02005590 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005591
Daniel Vetter9a7c7892013-04-04 22:20:34 +02005592 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5593 *fp2 |= FP_CB_TUNE;
5594
Chris Wilson5eddb702010-09-11 13:48:45 +01005595 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005596
Eric Anholta07d6782011-03-30 13:01:08 -07005597 if (is_lvds)
5598 dpll |= DPLLB_MODE_LVDS;
5599 else
5600 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005601
Daniel Vetteref1b4602013-06-01 17:17:04 +02005602 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5603 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005604
5605 if (is_sdvo)
5606 dpll |= DPLL_DVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02005607 if (intel_crtc->config.has_dp_encoder)
Eric Anholta07d6782011-03-30 13:01:08 -07005608 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005609
Eric Anholta07d6782011-03-30 13:01:08 -07005610 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005611 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005612 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005613 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005614
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005615 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07005616 case 5:
5617 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5618 break;
5619 case 7:
5620 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5621 break;
5622 case 10:
5623 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5624 break;
5625 case 14:
5626 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5627 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005628 }
5629
Daniel Vetterb4c09f32013-04-30 14:01:42 +02005630 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005631 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08005632 else
5633 dpll |= PLL_REF_INPUT_DREFCLK;
5634
Daniel Vetter959e16d2013-06-05 13:34:21 +02005635 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005636}
5637
Jesse Barnes79e53942008-11-07 14:24:08 -08005638static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08005639 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005640 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005641{
5642 struct drm_device *dev = crtc->dev;
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5645 int pipe = intel_crtc->pipe;
5646 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005647 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005648 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005649 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005650 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01005651 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005652 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02005653 struct intel_shared_dpll *pll;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005654 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005655
5656 for_each_encoder_on_crtc(dev, crtc, encoder) {
5657 switch (encoder->type) {
5658 case INTEL_OUTPUT_LVDS:
5659 is_lvds = true;
5660 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005661 }
5662
5663 num_connectors++;
5664 }
5665
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005666 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5667 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5668
Daniel Vetterff9a6752013-06-01 17:16:21 +02005669 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005670 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02005671 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005672 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5673 return -EINVAL;
5674 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01005675 /* Compat-code for transition, will disappear. */
5676 if (!intel_crtc->config.clock_set) {
5677 intel_crtc->config.dpll.n = clock.n;
5678 intel_crtc->config.dpll.m1 = clock.m1;
5679 intel_crtc->config.dpll.m2 = clock.m2;
5680 intel_crtc->config.dpll.p1 = clock.p1;
5681 intel_crtc->config.dpll.p2 = clock.p2;
5682 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005683
5684 /* Ensure that the cursor is valid for the new mode before changing... */
5685 intel_crtc_update_cursor(crtc, true);
5686
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005687 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01005688 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005689 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005690 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005691 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005692
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005693 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005694 &fp, &reduced_clock,
5695 has_reduced_clock ? &fp2 : NULL);
5696
Daniel Vetter959e16d2013-06-05 13:34:21 +02005697 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02005698 intel_crtc->config.dpll_hw_state.fp0 = fp;
5699 if (has_reduced_clock)
5700 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5701 else
5702 intel_crtc->config.dpll_hw_state.fp1 = fp;
5703
Daniel Vetterb89a1d32013-06-05 13:34:24 +02005704 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005705 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03005706 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5707 pipe_name(pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07005708 return -EINVAL;
5709 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005710 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02005711 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005712
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005713 if (intel_crtc->config.has_dp_encoder)
5714 intel_dp_set_m_n(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005715
Daniel Vetterbcd644e2013-06-05 13:34:22 +02005716 if (is_lvds && has_reduced_clock && i915_powersave)
5717 intel_crtc->lowfreq_avail = true;
5718 else
5719 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02005720
5721 if (intel_crtc->config.has_pch_encoder) {
5722 pll = intel_crtc_to_shared_dpll(intel_crtc);
5723
Jesse Barnes79e53942008-11-07 14:24:08 -08005724 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005725
Daniel Vetter8a654f32013-06-01 17:16:22 +02005726 intel_set_pipe_timings(intel_crtc);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005727
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005728 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005729 intel_cpu_transcoder_set_m_n(intel_crtc,
5730 &intel_crtc->config.fdi_m_n);
5731 }
Chris Wilson5eddb702010-09-11 13:48:45 +01005732
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005733 if (IS_IVYBRIDGE(dev))
5734 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005735
Daniel Vetter6ff93602013-04-19 11:24:36 +02005736 ironlake_set_pipeconf(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005737
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005738 /* Set up the display plane register */
5739 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005740 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005741
Daniel Vetter94352cf2012-07-05 22:51:56 +02005742 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005743
5744 intel_update_watermarks(dev);
5745
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005746 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005747}
5748
Daniel Vetter72419202013-04-04 13:28:53 +02005749static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5750 struct intel_crtc_config *pipe_config)
5751{
5752 struct drm_device *dev = crtc->base.dev;
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 enum transcoder transcoder = pipe_config->cpu_transcoder;
5755
5756 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5757 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5758 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5759 & ~TU_SIZE_MASK;
5760 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5761 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5762 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5763}
5764
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005765static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5766 struct intel_crtc_config *pipe_config)
5767{
5768 struct drm_device *dev = crtc->base.dev;
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 uint32_t tmp;
5771
5772 tmp = I915_READ(PF_CTL(crtc->pipe));
5773
5774 if (tmp & PF_ENABLE) {
5775 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5776 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02005777
5778 /* We currently do not free assignements of panel fitters on
5779 * ivb/hsw (since we don't use the higher upscaling modes which
5780 * differentiates them) so just WARN about this case for now. */
5781 if (IS_GEN7(dev)) {
5782 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5783 PF_PIPE_SEL_IVB(crtc->pipe));
5784 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005785 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005786}
5787
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005788static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5789 struct intel_crtc_config *pipe_config)
5790{
5791 struct drm_device *dev = crtc->base.dev;
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 uint32_t tmp;
5794
Daniel Vettereccb1402013-05-22 00:50:22 +02005795 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005796 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02005797
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005798 tmp = I915_READ(PIPECONF(crtc->pipe));
5799 if (!(tmp & PIPECONF_ENABLE))
5800 return false;
5801
Daniel Vetterab9412b2013-05-03 11:49:46 +02005802 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02005803 struct intel_shared_dpll *pll;
5804
Daniel Vetter88adfff2013-03-28 10:42:01 +01005805 pipe_config->has_pch_encoder = true;
5806
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005807 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5808 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5809 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02005810
5811 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02005812
5813 /* XXX: Can't properly read out the pch dpll pixel multiplier
5814 * since we don't have state tracking for pch clocks yet. */
5815 pipe_config->pixel_multiplier = 1;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005816
5817 if (HAS_PCH_IBX(dev_priv->dev)) {
5818 pipe_config->shared_dpll = crtc->pipe;
5819 } else {
5820 tmp = I915_READ(PCH_DPLL_SEL);
5821 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5822 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5823 else
5824 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5825 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02005826
5827 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5828
5829 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5830 &pipe_config->dpll_hw_state));
Daniel Vetter6c49f242013-06-06 12:45:25 +02005831 } else {
5832 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005833 }
5834
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005835 intel_get_pipe_timings(crtc, pipe_config);
5836
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005837 ironlake_get_pfit_config(crtc, pipe_config);
5838
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005839 return true;
5840}
5841
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005842static void haswell_modeset_global_resources(struct drm_device *dev)
5843{
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005844 bool enable = false;
5845 struct intel_crtc *crtc;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005846
5847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Daniel Vettere7a639c2013-05-31 17:49:17 +02005848 if (!crtc->base.enabled)
5849 continue;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005850
Daniel Vettere7a639c2013-05-31 17:49:17 +02005851 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5852 crtc->config.cpu_transcoder != TRANSCODER_EDP)
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005853 enable = true;
5854 }
5855
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005856 intel_set_power_well(dev, enable);
5857}
5858
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005859static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005860 int x, int y,
5861 struct drm_framebuffer *fb)
5862{
5863 struct drm_device *dev = crtc->dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005866 int plane = intel_crtc->plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005867 int ret;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005868
Daniel Vetterff9a6752013-06-01 17:16:21 +02005869 if (!intel_ddi_pll_mode_set(crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005870 return -EINVAL;
5871
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005872 /* Ensure that the cursor is valid for the new mode before changing... */
5873 intel_crtc_update_cursor(crtc, true);
5874
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005875 if (intel_crtc->config.has_dp_encoder)
5876 intel_dp_set_m_n(intel_crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005877
5878 intel_crtc->lowfreq_avail = false;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005879
Daniel Vetter8a654f32013-06-01 17:16:22 +02005880 intel_set_pipe_timings(intel_crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005881
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005882 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005883 intel_cpu_transcoder_set_m_n(intel_crtc,
5884 &intel_crtc->config.fdi_m_n);
5885 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005886
Daniel Vetter6ff93602013-04-19 11:24:36 +02005887 haswell_set_pipeconf(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005888
Daniel Vetter50f3b012013-03-27 00:44:56 +01005889 intel_set_pipe_csc(crtc);
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005890
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005891 /* Set up the display plane register */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005892 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005893 POSTING_READ(DSPCNTR(plane));
5894
5895 ret = intel_pipe_set_base(crtc, x, y, fb);
5896
5897 intel_update_watermarks(dev);
5898
Jesse Barnes79e53942008-11-07 14:24:08 -08005899 return ret;
5900}
5901
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005902static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5903 struct intel_crtc_config *pipe_config)
5904{
5905 struct drm_device *dev = crtc->base.dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005907 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005908 uint32_t tmp;
5909
Daniel Vettereccb1402013-05-22 00:50:22 +02005910 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005911 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5912
Daniel Vettereccb1402013-05-22 00:50:22 +02005913 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5914 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5915 enum pipe trans_edp_pipe;
5916 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5917 default:
5918 WARN(1, "unknown pipe linked to edp transcoder\n");
5919 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5920 case TRANS_DDI_EDP_INPUT_A_ON:
5921 trans_edp_pipe = PIPE_A;
5922 break;
5923 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5924 trans_edp_pipe = PIPE_B;
5925 break;
5926 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5927 trans_edp_pipe = PIPE_C;
5928 break;
5929 }
5930
5931 if (trans_edp_pipe == crtc->pipe)
5932 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5933 }
5934
Paulo Zanonib97186f2013-05-03 12:15:36 -03005935 if (!intel_display_power_enabled(dev,
Daniel Vettereccb1402013-05-22 00:50:22 +02005936 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03005937 return false;
5938
Daniel Vettereccb1402013-05-22 00:50:22 +02005939 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005940 if (!(tmp & PIPECONF_ENABLE))
5941 return false;
5942
Daniel Vetter88adfff2013-03-28 10:42:01 +01005943 /*
Paulo Zanonif196e6b2013-04-18 16:35:41 -03005944 * Haswell has only FDI/PCH transcoder A. It is which is connected to
Daniel Vetter88adfff2013-03-28 10:42:01 +01005945 * DDI E. So just check whether this pipe is wired to DDI E and whether
5946 * the PCH transcoder is on.
5947 */
Daniel Vettereccb1402013-05-22 00:50:22 +02005948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
Daniel Vetter88adfff2013-03-28 10:42:01 +01005949 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
Daniel Vetterab9412b2013-05-03 11:49:46 +02005950 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01005951 pipe_config->has_pch_encoder = true;
5952
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005953 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5954 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5955 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02005956
5957 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005958 }
5959
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005960 intel_get_pipe_timings(crtc, pipe_config);
5961
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005962 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5963 if (intel_display_power_enabled(dev, pfit_domain))
5964 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01005965
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005966 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5967 (I915_READ(IPS_CTL) & IPS_ENABLE);
5968
Daniel Vetter6c49f242013-06-06 12:45:25 +02005969 pipe_config->pixel_multiplier = 1;
5970
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005971 return true;
5972}
5973
Eric Anholtf564048e2011-03-30 13:01:02 -07005974static int intel_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005975 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005976 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07005977{
5978 struct drm_device *dev = crtc->dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9256aa12012-10-31 19:26:13 +01005980 struct drm_encoder_helper_funcs *encoder_funcs;
5981 struct intel_encoder *encoder;
Eric Anholt0b701d22011-03-30 13:01:03 -07005982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005983 struct drm_display_mode *adjusted_mode =
5984 &intel_crtc->config.adjusted_mode;
5985 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Eric Anholt0b701d22011-03-30 13:01:03 -07005986 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005987 int ret;
5988
Eric Anholt0b701d22011-03-30 13:01:03 -07005989 drm_vblank_pre_modeset(dev, pipe);
5990
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01005991 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5992
Jesse Barnes79e53942008-11-07 14:24:08 -08005993 drm_vblank_post_modeset(dev, pipe);
5994
Daniel Vetter9256aa12012-10-31 19:26:13 +01005995 if (ret != 0)
5996 return ret;
5997
5998 for_each_encoder_on_crtc(dev, crtc, encoder) {
5999 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6000 encoder->base.base.id,
6001 drm_get_encoder_name(&encoder->base),
6002 mode->base.id, mode->name);
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006003 if (encoder->mode_set) {
6004 encoder->mode_set(encoder);
6005 } else {
6006 encoder_funcs = encoder->base.helper_private;
6007 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6008 }
Daniel Vetter9256aa12012-10-31 19:26:13 +01006009 }
6010
6011 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006012}
6013
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006014static bool intel_eld_uptodate(struct drm_connector *connector,
6015 int reg_eldv, uint32_t bits_eldv,
6016 int reg_elda, uint32_t bits_elda,
6017 int reg_edid)
6018{
6019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6020 uint8_t *eld = connector->eld;
6021 uint32_t i;
6022
6023 i = I915_READ(reg_eldv);
6024 i &= bits_eldv;
6025
6026 if (!eld[0])
6027 return !i;
6028
6029 if (!i)
6030 return false;
6031
6032 i = I915_READ(reg_elda);
6033 i &= ~bits_elda;
6034 I915_WRITE(reg_elda, i);
6035
6036 for (i = 0; i < eld[2]; i++)
6037 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6038 return false;
6039
6040 return true;
6041}
6042
Wu Fengguange0dac652011-09-05 14:25:34 +08006043static void g4x_write_eld(struct drm_connector *connector,
6044 struct drm_crtc *crtc)
6045{
6046 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6047 uint8_t *eld = connector->eld;
6048 uint32_t eldv;
6049 uint32_t len;
6050 uint32_t i;
6051
6052 i = I915_READ(G4X_AUD_VID_DID);
6053
6054 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6055 eldv = G4X_ELDV_DEVCL_DEVBLC;
6056 else
6057 eldv = G4X_ELDV_DEVCTG;
6058
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006059 if (intel_eld_uptodate(connector,
6060 G4X_AUD_CNTL_ST, eldv,
6061 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6062 G4X_HDMIW_HDMIEDID))
6063 return;
6064
Wu Fengguange0dac652011-09-05 14:25:34 +08006065 i = I915_READ(G4X_AUD_CNTL_ST);
6066 i &= ~(eldv | G4X_ELD_ADDR);
6067 len = (i >> 9) & 0x1f; /* ELD buffer size */
6068 I915_WRITE(G4X_AUD_CNTL_ST, i);
6069
6070 if (!eld[0])
6071 return;
6072
6073 len = min_t(uint8_t, eld[2], len);
6074 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6075 for (i = 0; i < len; i++)
6076 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6077
6078 i = I915_READ(G4X_AUD_CNTL_ST);
6079 i |= eldv;
6080 I915_WRITE(G4X_AUD_CNTL_ST, i);
6081}
6082
Wang Xingchao83358c852012-08-16 22:43:37 +08006083static void haswell_write_eld(struct drm_connector *connector,
6084 struct drm_crtc *crtc)
6085{
6086 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6087 uint8_t *eld = connector->eld;
6088 struct drm_device *dev = crtc->dev;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08006089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Wang Xingchao83358c852012-08-16 22:43:37 +08006090 uint32_t eldv;
6091 uint32_t i;
6092 int len;
6093 int pipe = to_intel_crtc(crtc)->pipe;
6094 int tmp;
6095
6096 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6097 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6098 int aud_config = HSW_AUD_CFG(pipe);
6099 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6100
6101
6102 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6103
6104 /* Audio output enable */
6105 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6106 tmp = I915_READ(aud_cntrl_st2);
6107 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6108 I915_WRITE(aud_cntrl_st2, tmp);
6109
6110 /* Wait for 1 vertical blank */
6111 intel_wait_for_vblank(dev, pipe);
6112
6113 /* Set ELD valid state */
6114 tmp = I915_READ(aud_cntrl_st2);
6115 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6116 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6117 I915_WRITE(aud_cntrl_st2, tmp);
6118 tmp = I915_READ(aud_cntrl_st2);
6119 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6120
6121 /* Enable HDMI mode */
6122 tmp = I915_READ(aud_config);
6123 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6124 /* clear N_programing_enable and N_value_index */
6125 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6126 I915_WRITE(aud_config, tmp);
6127
6128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6129
6130 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08006131 intel_crtc->eld_vld = true;
Wang Xingchao83358c852012-08-16 22:43:37 +08006132
6133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6134 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6135 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6136 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6137 } else
6138 I915_WRITE(aud_config, 0);
6139
6140 if (intel_eld_uptodate(connector,
6141 aud_cntrl_st2, eldv,
6142 aud_cntl_st, IBX_ELD_ADDRESS,
6143 hdmiw_hdmiedid))
6144 return;
6145
6146 i = I915_READ(aud_cntrl_st2);
6147 i &= ~eldv;
6148 I915_WRITE(aud_cntrl_st2, i);
6149
6150 if (!eld[0])
6151 return;
6152
6153 i = I915_READ(aud_cntl_st);
6154 i &= ~IBX_ELD_ADDRESS;
6155 I915_WRITE(aud_cntl_st, i);
6156 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6157 DRM_DEBUG_DRIVER("port num:%d\n", i);
6158
6159 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6161 for (i = 0; i < len; i++)
6162 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6163
6164 i = I915_READ(aud_cntrl_st2);
6165 i |= eldv;
6166 I915_WRITE(aud_cntrl_st2, i);
6167
6168}
6169
Wu Fengguange0dac652011-09-05 14:25:34 +08006170static void ironlake_write_eld(struct drm_connector *connector,
6171 struct drm_crtc *crtc)
6172{
6173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6174 uint8_t *eld = connector->eld;
6175 uint32_t eldv;
6176 uint32_t i;
6177 int len;
6178 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006179 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08006180 int aud_cntl_st;
6181 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08006182 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08006183
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08006184 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006185 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6186 aud_config = IBX_AUD_CFG(pipe);
6187 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006188 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006189 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006190 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6191 aud_config = CPT_AUD_CFG(pipe);
6192 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006193 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006194 }
6195
Wang Xingchao9b138a82012-08-09 16:52:18 +08006196 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08006197
6198 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08006199 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08006200 if (!i) {
6201 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6202 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006203 eldv = IBX_ELD_VALIDB;
6204 eldv |= IBX_ELD_VALIDB << 4;
6205 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08006206 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03006207 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006208 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08006209 }
6210
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6212 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6213 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06006214 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6215 } else
6216 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006217
6218 if (intel_eld_uptodate(connector,
6219 aud_cntrl_st2, eldv,
6220 aud_cntl_st, IBX_ELD_ADDRESS,
6221 hdmiw_hdmiedid))
6222 return;
6223
Wu Fengguange0dac652011-09-05 14:25:34 +08006224 i = I915_READ(aud_cntrl_st2);
6225 i &= ~eldv;
6226 I915_WRITE(aud_cntrl_st2, i);
6227
6228 if (!eld[0])
6229 return;
6230
Wu Fengguange0dac652011-09-05 14:25:34 +08006231 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006232 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08006233 I915_WRITE(aud_cntl_st, i);
6234
6235 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6236 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6237 for (i = 0; i < len; i++)
6238 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6239
6240 i = I915_READ(aud_cntrl_st2);
6241 i |= eldv;
6242 I915_WRITE(aud_cntrl_st2, i);
6243}
6244
6245void intel_write_eld(struct drm_encoder *encoder,
6246 struct drm_display_mode *mode)
6247{
6248 struct drm_crtc *crtc = encoder->crtc;
6249 struct drm_connector *connector;
6250 struct drm_device *dev = encoder->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252
6253 connector = drm_select_eld(encoder, mode);
6254 if (!connector)
6255 return;
6256
6257 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6258 connector->base.id,
6259 drm_get_connector_name(connector),
6260 connector->encoder->base.id,
6261 drm_get_encoder_name(connector->encoder));
6262
6263 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6264
6265 if (dev_priv->display.write_eld)
6266 dev_priv->display.write_eld(connector, crtc);
6267}
6268
Jesse Barnes79e53942008-11-07 14:24:08 -08006269/** Loads the palette/gamma unit for the CRTC with the prepared values */
6270void intel_crtc_load_lut(struct drm_crtc *crtc)
6271{
6272 struct drm_device *dev = crtc->dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006275 enum pipe pipe = intel_crtc->pipe;
6276 int palreg = PALETTE(pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006277 int i;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006278 bool reenable_ips = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006279
6280 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00006281 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08006282 return;
6283
Ville Syrjälä14420bd2013-06-04 13:49:07 +03006284 if (!HAS_PCH_SPLIT(dev_priv->dev))
6285 assert_pll_enabled(dev_priv, pipe);
6286
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006287 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07006288 if (HAS_PCH_SPLIT(dev))
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006289 palreg = LGC_PALETTE(pipe);
6290
6291 /* Workaround : Do not read or write the pipe palette/gamma data while
6292 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6293 */
6294 if (intel_crtc->config.ips_enabled &&
6295 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6296 GAMMA_MODE_MODE_SPLIT)) {
6297 hsw_disable_ips(intel_crtc);
6298 reenable_ips = true;
6299 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08006300
Jesse Barnes79e53942008-11-07 14:24:08 -08006301 for (i = 0; i < 256; i++) {
6302 I915_WRITE(palreg + 4 * i,
6303 (intel_crtc->lut_r[i] << 16) |
6304 (intel_crtc->lut_g[i] << 8) |
6305 intel_crtc->lut_b[i]);
6306 }
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006307
6308 if (reenable_ips)
6309 hsw_enable_ips(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006310}
6311
Chris Wilson560b85b2010-08-07 11:01:38 +01006312static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6313{
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317 bool visible = base != 0;
6318 u32 cntl;
6319
6320 if (intel_crtc->cursor_visible == visible)
6321 return;
6322
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006323 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01006324 if (visible) {
6325 /* On these chipsets we can only modify the base whilst
6326 * the cursor is disabled.
6327 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006328 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006329
6330 cntl &= ~(CURSOR_FORMAT_MASK);
6331 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6332 cntl |= CURSOR_ENABLE |
6333 CURSOR_GAMMA_ENABLE |
6334 CURSOR_FORMAT_ARGB;
6335 } else
6336 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006337 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006338
6339 intel_crtc->cursor_visible = visible;
6340}
6341
6342static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6343{
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 int pipe = intel_crtc->pipe;
6348 bool visible = base != 0;
6349
6350 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08006351 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01006352 if (base) {
6353 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6354 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6355 cntl |= pipe << 28; /* Connect to correct pipe */
6356 } else {
6357 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6358 cntl |= CURSOR_MODE_DISABLE;
6359 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006360 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006361
6362 intel_crtc->cursor_visible = visible;
6363 }
6364 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006365 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006366}
6367
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006368static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6369{
6370 struct drm_device *dev = crtc->dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6373 int pipe = intel_crtc->pipe;
6374 bool visible = base != 0;
6375
6376 if (intel_crtc->cursor_visible != visible) {
6377 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6378 if (base) {
6379 cntl &= ~CURSOR_MODE;
6380 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6381 } else {
6382 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6383 cntl |= CURSOR_MODE_DISABLE;
6384 }
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006385 if (IS_HASWELL(dev))
6386 cntl |= CURSOR_PIPE_CSC_ENABLE;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006387 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6388
6389 intel_crtc->cursor_visible = visible;
6390 }
6391 /* and commit changes on next vblank */
6392 I915_WRITE(CURBASE_IVB(pipe), base);
6393}
6394
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006395/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01006396static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6397 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006398{
6399 struct drm_device *dev = crtc->dev;
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402 int pipe = intel_crtc->pipe;
6403 int x = intel_crtc->cursor_x;
6404 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01006405 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006406 bool visible;
6407
6408 pos = 0;
6409
Chris Wilson6b383a72010-09-13 13:54:26 +01006410 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006411 base = intel_crtc->cursor_addr;
6412 if (x > (int) crtc->fb->width)
6413 base = 0;
6414
6415 if (y > (int) crtc->fb->height)
6416 base = 0;
6417 } else
6418 base = 0;
6419
6420 if (x < 0) {
6421 if (x + intel_crtc->cursor_width < 0)
6422 base = 0;
6423
6424 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6425 x = -x;
6426 }
6427 pos |= x << CURSOR_X_SHIFT;
6428
6429 if (y < 0) {
6430 if (y + intel_crtc->cursor_height < 0)
6431 base = 0;
6432
6433 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6434 y = -y;
6435 }
6436 pos |= y << CURSOR_Y_SHIFT;
6437
6438 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006439 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006440 return;
6441
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03006442 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006443 I915_WRITE(CURPOS_IVB(pipe), pos);
6444 ivb_update_cursor(crtc, base);
6445 } else {
6446 I915_WRITE(CURPOS(pipe), pos);
6447 if (IS_845G(dev) || IS_I865G(dev))
6448 i845_update_cursor(crtc, base);
6449 else
6450 i9xx_update_cursor(crtc, base);
6451 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006452}
6453
Jesse Barnes79e53942008-11-07 14:24:08 -08006454static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006455 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006456 uint32_t handle,
6457 uint32_t width, uint32_t height)
6458{
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006462 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006463 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006464 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006465
Jesse Barnes79e53942008-11-07 14:24:08 -08006466 /* if we want to turn off the cursor ignore width and height */
6467 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006468 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006469 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006470 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006471 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006472 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006473 }
6474
6475 /* Currently we only support 64x64 cursors */
6476 if (width != 64 || height != 64) {
6477 DRM_ERROR("we currently only support 64x64 cursors\n");
6478 return -EINVAL;
6479 }
6480
Chris Wilson05394f32010-11-08 19:18:58 +00006481 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006482 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006483 return -ENOENT;
6484
Chris Wilson05394f32010-11-08 19:18:58 +00006485 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006486 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006487 ret = -ENOMEM;
6488 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006489 }
6490
Dave Airlie71acb5e2008-12-30 20:31:46 +10006491 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006492 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006493 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00006494 unsigned alignment;
6495
Chris Wilsond9e86c02010-11-10 16:40:20 +00006496 if (obj->tiling_mode) {
6497 DRM_ERROR("cursor cannot be tiled\n");
6498 ret = -EINVAL;
6499 goto fail_locked;
6500 }
6501
Chris Wilson693db182013-03-05 14:52:39 +00006502 /* Note that the w/a also requires 2 PTE of padding following
6503 * the bo. We currently fill all unused PTE with the shadow
6504 * page and so we should always have valid PTE following the
6505 * cursor preventing the VT-d warning.
6506 */
6507 alignment = 0;
6508 if (need_vtd_wa(dev))
6509 alignment = 64*1024;
6510
6511 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006512 if (ret) {
6513 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006514 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006515 }
6516
Chris Wilsond9e86c02010-11-10 16:40:20 +00006517 ret = i915_gem_object_put_fence(obj);
6518 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006519 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006520 goto fail_unpin;
6521 }
6522
Chris Wilson05394f32010-11-08 19:18:58 +00006523 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006524 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006525 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006526 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006527 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6528 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006529 if (ret) {
6530 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006531 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006532 }
Chris Wilson05394f32010-11-08 19:18:58 +00006533 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006534 }
6535
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006536 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006537 I915_WRITE(CURSIZE, (height << 12) | width);
6538
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006539 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006540 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006541 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006542 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006543 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6544 } else
6545 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006546 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006547 }
Jesse Barnes80824002009-09-10 15:28:06 -07006548
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006549 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006550
6551 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006552 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006553 intel_crtc->cursor_width = width;
6554 intel_crtc->cursor_height = height;
6555
Mika Kuoppala40ccc722013-04-23 17:27:08 +03006556 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006557
Jesse Barnes79e53942008-11-07 14:24:08 -08006558 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006559fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006560 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006561fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006562 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006563fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006564 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006565 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006566}
6567
6568static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6569{
Jesse Barnes79e53942008-11-07 14:24:08 -08006570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006571
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006572 intel_crtc->cursor_x = x;
6573 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006574
Mika Kuoppala40ccc722013-04-23 17:27:08 +03006575 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08006576
6577 return 0;
6578}
6579
6580/** Sets the color ramps on behalf of RandR */
6581void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6582 u16 blue, int regno)
6583{
6584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6585
6586 intel_crtc->lut_r[regno] = red >> 8;
6587 intel_crtc->lut_g[regno] = green >> 8;
6588 intel_crtc->lut_b[regno] = blue >> 8;
6589}
6590
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006591void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6592 u16 *blue, int regno)
6593{
6594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6595
6596 *red = intel_crtc->lut_r[regno] << 8;
6597 *green = intel_crtc->lut_g[regno] << 8;
6598 *blue = intel_crtc->lut_b[regno] << 8;
6599}
6600
Jesse Barnes79e53942008-11-07 14:24:08 -08006601static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006602 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006603{
James Simmons72034252010-08-03 01:33:19 +01006604 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006606
James Simmons72034252010-08-03 01:33:19 +01006607 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006608 intel_crtc->lut_r[i] = red[i] >> 8;
6609 intel_crtc->lut_g[i] = green[i] >> 8;
6610 intel_crtc->lut_b[i] = blue[i] >> 8;
6611 }
6612
6613 intel_crtc_load_lut(crtc);
6614}
6615
Jesse Barnes79e53942008-11-07 14:24:08 -08006616/* VESA 640x480x72Hz mode to set on the pipe */
6617static struct drm_display_mode load_detect_mode = {
6618 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6619 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6620};
6621
Chris Wilsond2dff872011-04-19 08:36:26 +01006622static struct drm_framebuffer *
6623intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006624 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01006625 struct drm_i915_gem_object *obj)
6626{
6627 struct intel_framebuffer *intel_fb;
6628 int ret;
6629
6630 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6631 if (!intel_fb) {
6632 drm_gem_object_unreference_unlocked(&obj->base);
6633 return ERR_PTR(-ENOMEM);
6634 }
6635
6636 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6637 if (ret) {
6638 drm_gem_object_unreference_unlocked(&obj->base);
6639 kfree(intel_fb);
6640 return ERR_PTR(ret);
6641 }
6642
6643 return &intel_fb->base;
6644}
6645
6646static u32
6647intel_framebuffer_pitch_for_width(int width, int bpp)
6648{
6649 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6650 return ALIGN(pitch, 64);
6651}
6652
6653static u32
6654intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6655{
6656 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6657 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6658}
6659
6660static struct drm_framebuffer *
6661intel_framebuffer_create_for_mode(struct drm_device *dev,
6662 struct drm_display_mode *mode,
6663 int depth, int bpp)
6664{
6665 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00006666 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01006667
6668 obj = i915_gem_alloc_object(dev,
6669 intel_framebuffer_size_for_mode(mode, bpp));
6670 if (obj == NULL)
6671 return ERR_PTR(-ENOMEM);
6672
6673 mode_cmd.width = mode->hdisplay;
6674 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006675 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6676 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00006677 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01006678
6679 return intel_framebuffer_create(dev, &mode_cmd, obj);
6680}
6681
6682static struct drm_framebuffer *
6683mode_fits_in_fbdev(struct drm_device *dev,
6684 struct drm_display_mode *mode)
6685{
6686 struct drm_i915_private *dev_priv = dev->dev_private;
6687 struct drm_i915_gem_object *obj;
6688 struct drm_framebuffer *fb;
6689
6690 if (dev_priv->fbdev == NULL)
6691 return NULL;
6692
6693 obj = dev_priv->fbdev->ifb.obj;
6694 if (obj == NULL)
6695 return NULL;
6696
6697 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006698 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6699 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006700 return NULL;
6701
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006702 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006703 return NULL;
6704
6705 return fb;
6706}
6707
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006708bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01006709 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006710 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006711{
6712 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006713 struct intel_encoder *intel_encoder =
6714 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08006715 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006716 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006717 struct drm_crtc *crtc = NULL;
6718 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02006719 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006720 int i = -1;
6721
Chris Wilsond2dff872011-04-19 08:36:26 +01006722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6723 connector->base.id, drm_get_connector_name(connector),
6724 encoder->base.id, drm_get_encoder_name(encoder));
6725
Jesse Barnes79e53942008-11-07 14:24:08 -08006726 /*
6727 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006728 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006729 * - if the connector already has an assigned crtc, use it (but make
6730 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006731 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006732 * - try to find the first unused crtc that can drive this connector,
6733 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006734 */
6735
6736 /* See if we already have a CRTC for this connector */
6737 if (encoder->crtc) {
6738 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006739
Daniel Vetter7b240562012-12-12 00:35:33 +01006740 mutex_lock(&crtc->mutex);
6741
Daniel Vetter24218aa2012-08-12 19:27:11 +02006742 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006743 old->load_detect_temp = false;
6744
6745 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006746 if (connector->dpms != DRM_MODE_DPMS_ON)
6747 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01006748
Chris Wilson71731882011-04-19 23:10:58 +01006749 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006750 }
6751
6752 /* Find an unused one (if possible) */
6753 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6754 i++;
6755 if (!(encoder->possible_crtcs & (1 << i)))
6756 continue;
6757 if (!possible_crtc->enabled) {
6758 crtc = possible_crtc;
6759 break;
6760 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006761 }
6762
6763 /*
6764 * If we didn't find an unused CRTC, don't use any.
6765 */
6766 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006767 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6768 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006769 }
6770
Daniel Vetter7b240562012-12-12 00:35:33 +01006771 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02006772 intel_encoder->new_crtc = to_intel_crtc(crtc);
6773 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006774
6775 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006776 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006777 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006778 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006779
Chris Wilson64927112011-04-20 07:25:26 +01006780 if (!mode)
6781 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006782
Chris Wilsond2dff872011-04-19 08:36:26 +01006783 /* We need a framebuffer large enough to accommodate all accesses
6784 * that the plane may generate whilst we perform load detection.
6785 * We can not rely on the fbcon either being present (we get called
6786 * during its initialisation to detect all boot displays, or it may
6787 * not even exist) or that it is large enough to satisfy the
6788 * requested mode.
6789 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02006790 fb = mode_fits_in_fbdev(dev, mode);
6791 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006792 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006793 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6794 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01006795 } else
6796 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006797 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006798 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter7b240562012-12-12 00:35:33 +01006799 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006800 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006801 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006802
Chris Wilsonc0c36b942012-12-19 16:08:43 +00006803 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006804 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006805 if (old->release_fb)
6806 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter7b240562012-12-12 00:35:33 +01006807 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006808 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006809 }
Chris Wilson71731882011-04-19 23:10:58 +01006810
Jesse Barnes79e53942008-11-07 14:24:08 -08006811 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006812 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01006813 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006814}
6815
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006816void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01006817 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006818{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006819 struct intel_encoder *intel_encoder =
6820 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01006821 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01006822 struct drm_crtc *crtc = encoder->crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -08006823
Chris Wilsond2dff872011-04-19 08:36:26 +01006824 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6825 connector->base.id, drm_get_connector_name(connector),
6826 encoder->base.id, drm_get_encoder_name(encoder));
6827
Chris Wilson8261b192011-04-19 23:18:09 +01006828 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02006829 to_intel_connector(connector)->new_encoder = NULL;
6830 intel_encoder->new_crtc = NULL;
6831 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01006832
Daniel Vetter36206362012-12-10 20:42:17 +01006833 if (old->release_fb) {
6834 drm_framebuffer_unregister_private(old->release_fb);
6835 drm_framebuffer_unreference(old->release_fb);
6836 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006837
Daniel Vetter67c96402013-01-23 16:25:09 +00006838 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01006839 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006840 }
6841
Eric Anholtc751ce42010-03-25 11:48:48 -07006842 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006843 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6844 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01006845
6846 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08006847}
6848
6849/* Returns the clock of the currently programmed mode of the given pipe. */
6850static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6851{
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6854 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006855 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006856 u32 fp;
6857 intel_clock_t clock;
6858
6859 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006860 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006861 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006862 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006863
6864 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006865 if (IS_PINEVIEW(dev)) {
6866 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6867 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006868 } else {
6869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6870 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6871 }
6872
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006873 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006874 if (IS_PINEVIEW(dev))
6875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6876 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006877 else
6878 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006879 DPLL_FPA01_P1_POST_DIV_SHIFT);
6880
6881 switch (dpll & DPLL_MODE_MASK) {
6882 case DPLLB_MODE_DAC_SERIAL:
6883 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6884 5 : 10;
6885 break;
6886 case DPLLB_MODE_LVDS:
6887 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6888 7 : 14;
6889 break;
6890 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006891 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006892 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6893 return 0;
6894 }
6895
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006896 if (IS_PINEVIEW(dev))
6897 pineview_clock(96000, &clock);
6898 else
6899 i9xx_clock(96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006900 } else {
6901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6902
6903 if (is_lvds) {
6904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6905 DPLL_FPA01_P1_POST_DIV_SHIFT);
6906 clock.p2 = 14;
6907
6908 if ((dpll & PLL_REF_INPUT_MASK) ==
6909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6910 /* XXX: might not be 66MHz */
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006911 i9xx_clock(66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006912 } else
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006913 i9xx_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006914 } else {
6915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6916 clock.p1 = 2;
6917 else {
6918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6920 }
6921 if (dpll & PLL_P2_DIVIDE_BY_4)
6922 clock.p2 = 4;
6923 else
6924 clock.p2 = 2;
6925
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006926 i9xx_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006927 }
6928 }
6929
6930 /* XXX: It would be nice to validate the clocks, but we can't reuse
6931 * i830PllIsValid() because it relies on the xf86_config connector
6932 * configuration being accurate, which it isn't necessarily.
6933 */
6934
6935 return clock.dot;
6936}
6937
6938/** Returns the currently programmed mode of the given pipe. */
6939struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6940 struct drm_crtc *crtc)
6941{
Jesse Barnes548f2452011-02-17 10:40:53 -08006942 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02006944 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006945 struct drm_display_mode *mode;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006946 int htot = I915_READ(HTOTAL(cpu_transcoder));
6947 int hsync = I915_READ(HSYNC(cpu_transcoder));
6948 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6949 int vsync = I915_READ(VSYNC(cpu_transcoder));
Jesse Barnes79e53942008-11-07 14:24:08 -08006950
6951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6952 if (!mode)
6953 return NULL;
6954
6955 mode->clock = intel_crtc_clock_get(dev, crtc);
6956 mode->hdisplay = (htot & 0xffff) + 1;
6957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6958 mode->hsync_start = (hsync & 0xffff) + 1;
6959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6960 mode->vdisplay = (vtot & 0xffff) + 1;
6961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6962 mode->vsync_start = (vsync & 0xffff) + 1;
6963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6964
6965 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006966
6967 return mode;
6968}
6969
Daniel Vetter3dec0092010-08-20 21:40:52 +02006970static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006971{
6972 struct drm_device *dev = crtc->dev;
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006976 int dpll_reg = DPLL(pipe);
6977 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006978
Eric Anholtbad720f2009-10-22 16:11:14 -07006979 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006980 return;
6981
6982 if (!dev_priv->lvds_downclock_avail)
6983 return;
6984
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006985 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006988
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006989 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006990
6991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6992 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006993 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006994
Jesse Barnes652c3932009-08-17 13:31:43 -07006995 dpll = I915_READ(dpll_reg);
6996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006998 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006999}
7000
7001static void intel_decrease_pllclock(struct drm_crtc *crtc)
7002{
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007006
Eric Anholtbad720f2009-10-22 16:11:14 -07007007 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007008 return;
7009
7010 if (!dev_priv->lvds_downclock_avail)
7011 return;
7012
7013 /*
7014 * Since this is called by a timer, we should never get here in
7015 * the manual case.
7016 */
7017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01007018 int pipe = intel_crtc->pipe;
7019 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02007020 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01007021
Zhao Yakui44d98a62009-10-09 11:39:40 +08007022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007023
Sean Paul8ac5a6d2012-02-13 13:14:51 -05007024 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007025
Chris Wilson074b5e12012-05-02 12:07:06 +01007026 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07007027 dpll |= DISPLAY_RATE_SELECT_FPA1;
7028 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007029 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007030 dpll = I915_READ(dpll_reg);
7031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08007032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007033 }
7034
7035}
7036
Chris Wilsonf047e392012-07-21 12:31:41 +01007037void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07007038{
Chris Wilsonf047e392012-07-21 12:31:41 +01007039 i915_update_gfx_val(dev->dev_private);
7040}
7041
7042void intel_mark_idle(struct drm_device *dev)
7043{
Chris Wilson725a5b52013-01-08 11:02:57 +00007044 struct drm_crtc *crtc;
7045
7046 if (!i915_powersave)
7047 return;
7048
7049 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7050 if (!crtc->fb)
7051 continue;
7052
7053 intel_decrease_pllclock(crtc);
7054 }
Chris Wilsonf047e392012-07-21 12:31:41 +01007055}
7056
Chris Wilsonc65355b2013-06-06 16:53:41 -03007057void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7058 struct intel_ring_buffer *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01007059{
7060 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07007061 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07007062
7063 if (!i915_powersave)
7064 return;
7065
Jesse Barnes652c3932009-08-17 13:31:43 -07007066 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007067 if (!crtc->fb)
7068 continue;
7069
Chris Wilsonc65355b2013-06-06 16:53:41 -03007070 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7071 continue;
7072
7073 intel_increase_pllclock(crtc);
7074 if (ring && intel_fbc_enabled(dev))
7075 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07007076 }
Jesse Barnes652c3932009-08-17 13:31:43 -07007077}
7078
Jesse Barnes79e53942008-11-07 14:24:08 -08007079static void intel_crtc_destroy(struct drm_crtc *crtc)
7080{
7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007082 struct drm_device *dev = crtc->dev;
7083 struct intel_unpin_work *work;
7084 unsigned long flags;
7085
7086 spin_lock_irqsave(&dev->event_lock, flags);
7087 work = intel_crtc->unpin_work;
7088 intel_crtc->unpin_work = NULL;
7089 spin_unlock_irqrestore(&dev->event_lock, flags);
7090
7091 if (work) {
7092 cancel_work_sync(&work->work);
7093 kfree(work);
7094 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007095
Mika Kuoppala40ccc722013-04-23 17:27:08 +03007096 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7097
Jesse Barnes79e53942008-11-07 14:24:08 -08007098 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007099
Jesse Barnes79e53942008-11-07 14:24:08 -08007100 kfree(intel_crtc);
7101}
7102
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007103static void intel_unpin_work_fn(struct work_struct *__work)
7104{
7105 struct intel_unpin_work *work =
7106 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007107 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007108
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007109 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01007110 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00007111 drm_gem_object_unreference(&work->pending_flip_obj->base);
7112 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00007113
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007114 intel_update_fbc(dev);
7115 mutex_unlock(&dev->struct_mutex);
7116
7117 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7118 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7119
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007120 kfree(work);
7121}
7122
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007123static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01007124 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007125{
7126 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007129 unsigned long flags;
7130
7131 /* Ignore early vblank irqs */
7132 if (intel_crtc == NULL)
7133 return;
7134
7135 spin_lock_irqsave(&dev->event_lock, flags);
7136 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00007137
7138 /* Ensure we don't miss a work->pending update ... */
7139 smp_rmb();
7140
7141 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007142 spin_unlock_irqrestore(&dev->event_lock, flags);
7143 return;
7144 }
7145
Chris Wilsone7d841c2012-12-03 11:36:30 +00007146 /* and that the unpin work is consistent wrt ->pending. */
7147 smp_rmb();
7148
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007149 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007150
Rob Clark45a066e2012-10-08 14:50:40 -05007151 if (work->event)
7152 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007153
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007154 drm_vblank_put(dev, intel_crtc->pipe);
7155
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007156 spin_unlock_irqrestore(&dev->event_lock, flags);
7157
Daniel Vetter2c10d572012-12-20 21:24:07 +01007158 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007159
7160 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07007161
7162 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007163}
7164
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007165void intel_finish_page_flip(struct drm_device *dev, int pipe)
7166{
7167 drm_i915_private_t *dev_priv = dev->dev_private;
7168 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7169
Mario Kleiner49b14a52010-12-09 07:00:07 +01007170 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007171}
7172
7173void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7174{
7175 drm_i915_private_t *dev_priv = dev->dev_private;
7176 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7177
Mario Kleiner49b14a52010-12-09 07:00:07 +01007178 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007179}
7180
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007181void intel_prepare_page_flip(struct drm_device *dev, int plane)
7182{
7183 drm_i915_private_t *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc =
7185 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7186 unsigned long flags;
7187
Chris Wilsone7d841c2012-12-03 11:36:30 +00007188 /* NB: An MMIO update of the plane base pointer will also
7189 * generate a page-flip completion irq, i.e. every modeset
7190 * is also accompanied by a spurious intel_prepare_page_flip().
7191 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007192 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007193 if (intel_crtc->unpin_work)
7194 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007195 spin_unlock_irqrestore(&dev->event_lock, flags);
7196}
7197
Chris Wilsone7d841c2012-12-03 11:36:30 +00007198inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7199{
7200 /* Ensure that the work item is consistent when activating it ... */
7201 smp_wmb();
7202 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7203 /* and that it is marked active as soon as the irq could fire. */
7204 smp_wmb();
7205}
7206
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007207static int intel_gen2_queue_flip(struct drm_device *dev,
7208 struct drm_crtc *crtc,
7209 struct drm_framebuffer *fb,
7210 struct drm_i915_gem_object *obj)
7211{
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007214 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007215 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007216 int ret;
7217
Daniel Vetter6d90c952012-04-26 23:28:05 +02007218 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007219 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007220 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007221
Daniel Vetter6d90c952012-04-26 23:28:05 +02007222 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007223 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007224 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007225
7226 /* Can't queue multiple flips, so wait for the previous
7227 * one to finish before executing the next.
7228 */
7229 if (intel_crtc->plane)
7230 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7231 else
7232 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007233 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7234 intel_ring_emit(ring, MI_NOOP);
7235 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7236 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7237 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007238 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007239 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00007240
7241 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007242 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007243 return 0;
7244
7245err_unpin:
7246 intel_unpin_fb_obj(obj);
7247err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007248 return ret;
7249}
7250
7251static int intel_gen3_queue_flip(struct drm_device *dev,
7252 struct drm_crtc *crtc,
7253 struct drm_framebuffer *fb,
7254 struct drm_i915_gem_object *obj)
7255{
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007258 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007259 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007260 int ret;
7261
Daniel Vetter6d90c952012-04-26 23:28:05 +02007262 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007263 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007264 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007265
Daniel Vetter6d90c952012-04-26 23:28:05 +02007266 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007267 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007268 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007269
7270 if (intel_crtc->plane)
7271 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7272 else
7273 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007274 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7275 intel_ring_emit(ring, MI_NOOP);
7276 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7277 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7278 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007279 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007280 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007281
Chris Wilsone7d841c2012-12-03 11:36:30 +00007282 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007283 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007284 return 0;
7285
7286err_unpin:
7287 intel_unpin_fb_obj(obj);
7288err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007289 return ret;
7290}
7291
7292static int intel_gen4_queue_flip(struct drm_device *dev,
7293 struct drm_crtc *crtc,
7294 struct drm_framebuffer *fb,
7295 struct drm_i915_gem_object *obj)
7296{
7297 struct drm_i915_private *dev_priv = dev->dev_private;
7298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7299 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007300 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007301 int ret;
7302
Daniel Vetter6d90c952012-04-26 23:28:05 +02007303 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007304 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007305 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007306
Daniel Vetter6d90c952012-04-26 23:28:05 +02007307 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007308 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007309 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007310
7311 /* i965+ uses the linear or tiled offsets from the
7312 * Display Registers (which do not change across a page-flip)
7313 * so we need only reprogram the base address.
7314 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02007315 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7317 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007318 intel_ring_emit(ring,
7319 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7320 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007321
7322 /* XXX Enabling the panel-fitter across page-flip is so far
7323 * untested on non-native modes, so ignore it for now.
7324 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7325 */
7326 pf = 0;
7327 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007328 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007329
7330 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007331 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007337 return ret;
7338}
7339
7340static int intel_gen6_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344{
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007347 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007348 uint32_t pf, pipesrc;
7349 int ret;
7350
Daniel Vetter6d90c952012-04-26 23:28:05 +02007351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007352 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007353 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007354
Daniel Vetter6d90c952012-04-26 23:28:05 +02007355 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007356 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007357 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007358
Daniel Vetter6d90c952012-04-26 23:28:05 +02007359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7361 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007362 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007363
Chris Wilson99d9acd2012-04-17 20:37:00 +01007364 /* Contrary to the suggestions in the documentation,
7365 * "Enable Panel Fitter" does not seem to be required when page
7366 * flipping with a non-native mode, and worse causes a normal
7367 * modeset to fail.
7368 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7369 */
7370 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007371 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007372 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007373
7374 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007375 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007376 return 0;
7377
7378err_unpin:
7379 intel_unpin_fb_obj(obj);
7380err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007381 return ret;
7382}
7383
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007384/*
7385 * On gen7 we currently use the blit ring because (in early silicon at least)
7386 * the render ring doesn't give us interrpts for page flip completion, which
7387 * means clients will hang after the first flip is queued. Fortunately the
7388 * blit ring generates interrupts properly, so use it instead.
7389 */
7390static int intel_gen7_queue_flip(struct drm_device *dev,
7391 struct drm_crtc *crtc,
7392 struct drm_framebuffer *fb,
7393 struct drm_i915_gem_object *obj)
7394{
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7397 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007398 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007399 int ret;
7400
7401 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7402 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007403 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007404
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007405 switch(intel_crtc->plane) {
7406 case PLANE_A:
7407 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7408 break;
7409 case PLANE_B:
7410 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7411 break;
7412 case PLANE_C:
7413 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7414 break;
7415 default:
7416 WARN_ONCE(1, "unknown plane in flip command\n");
7417 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03007418 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007419 }
7420
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007421 ret = intel_ring_begin(ring, 4);
7422 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007423 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007424
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007425 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007426 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02007427 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007428 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00007429
7430 intel_mark_page_flip_active(intel_crtc);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007431 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007432 return 0;
7433
7434err_unpin:
7435 intel_unpin_fb_obj(obj);
7436err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007437 return ret;
7438}
7439
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007440static int intel_default_queue_flip(struct drm_device *dev,
7441 struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_i915_gem_object *obj)
7444{
7445 return -ENODEV;
7446}
7447
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007448static int intel_crtc_page_flip(struct drm_crtc *crtc,
7449 struct drm_framebuffer *fb,
7450 struct drm_pending_vblank_event *event)
7451{
7452 struct drm_device *dev = crtc->dev;
7453 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007454 struct drm_framebuffer *old_fb = crtc->fb;
7455 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007458 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007459 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007460
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03007461 /* Can't change pixel format via MI display flips. */
7462 if (fb->pixel_format != crtc->fb->pixel_format)
7463 return -EINVAL;
7464
7465 /*
7466 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7467 * Note that pitch changes could also affect these register.
7468 */
7469 if (INTEL_INFO(dev)->gen > 3 &&
7470 (fb->offsets[0] != crtc->fb->offsets[0] ||
7471 fb->pitches[0] != crtc->fb->pitches[0]))
7472 return -EINVAL;
7473
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007474 work = kzalloc(sizeof *work, GFP_KERNEL);
7475 if (work == NULL)
7476 return -ENOMEM;
7477
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007478 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007479 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007480 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007481 INIT_WORK(&work->work, intel_unpin_work_fn);
7482
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007483 ret = drm_vblank_get(dev, intel_crtc->pipe);
7484 if (ret)
7485 goto free_work;
7486
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007487 /* We borrow the event spin lock for protecting unpin_work */
7488 spin_lock_irqsave(&dev->event_lock, flags);
7489 if (intel_crtc->unpin_work) {
7490 spin_unlock_irqrestore(&dev->event_lock, flags);
7491 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007492 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01007493
7494 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007495 return -EBUSY;
7496 }
7497 intel_crtc->unpin_work = work;
7498 spin_unlock_irqrestore(&dev->event_lock, flags);
7499
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007500 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7501 flush_workqueue(dev_priv->wq);
7502
Chris Wilson79158102012-05-23 11:13:58 +01007503 ret = i915_mutex_lock_interruptible(dev);
7504 if (ret)
7505 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007506
Jesse Barnes75dfca82010-02-10 15:09:44 -08007507 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007508 drm_gem_object_reference(&work->old_fb_obj->base);
7509 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007510
7511 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007512
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007513 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007514
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007515 work->enable_stall_check = true;
7516
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007517 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02007518 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007519
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007520 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7521 if (ret)
7522 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007523
Chris Wilson7782de32011-07-08 12:22:41 +01007524 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03007525 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007526 mutex_unlock(&dev->struct_mutex);
7527
Jesse Barnese5510fa2010-07-01 16:48:37 -07007528 trace_i915_flip_request(intel_crtc->plane, obj);
7529
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007530 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007531
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007532cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007533 atomic_dec(&intel_crtc->unpin_work_count);
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007534 crtc->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007535 drm_gem_object_unreference(&work->old_fb_obj->base);
7536 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007537 mutex_unlock(&dev->struct_mutex);
7538
Chris Wilson79158102012-05-23 11:13:58 +01007539cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01007540 spin_lock_irqsave(&dev->event_lock, flags);
7541 intel_crtc->unpin_work = NULL;
7542 spin_unlock_irqrestore(&dev->event_lock, flags);
7543
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007544 drm_vblank_put(dev, intel_crtc->pipe);
7545free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01007546 kfree(work);
7547
7548 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007549}
7550
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007551static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007552 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7553 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007554};
7555
Daniel Vetter50f56112012-07-02 09:35:43 +02007556static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7557 struct drm_crtc *crtc)
7558{
7559 struct drm_device *dev;
7560 struct drm_crtc *tmp;
7561 int crtc_mask = 1;
7562
7563 WARN(!crtc, "checking null crtc?\n");
7564
7565 dev = crtc->dev;
7566
7567 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7568 if (tmp == crtc)
7569 break;
7570 crtc_mask <<= 1;
7571 }
7572
7573 if (encoder->possible_crtcs & crtc_mask)
7574 return true;
7575 return false;
7576}
7577
Daniel Vetter9a935852012-07-05 22:34:27 +02007578/**
7579 * intel_modeset_update_staged_output_state
7580 *
7581 * Updates the staged output configuration state, e.g. after we've read out the
7582 * current hw state.
7583 */
7584static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7585{
7586 struct intel_encoder *encoder;
7587 struct intel_connector *connector;
7588
7589 list_for_each_entry(connector, &dev->mode_config.connector_list,
7590 base.head) {
7591 connector->new_encoder =
7592 to_intel_encoder(connector->base.encoder);
7593 }
7594
7595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7596 base.head) {
7597 encoder->new_crtc =
7598 to_intel_crtc(encoder->base.crtc);
7599 }
7600}
7601
7602/**
7603 * intel_modeset_commit_output_state
7604 *
7605 * This function copies the stage display pipe configuration to the real one.
7606 */
7607static void intel_modeset_commit_output_state(struct drm_device *dev)
7608{
7609 struct intel_encoder *encoder;
7610 struct intel_connector *connector;
7611
7612 list_for_each_entry(connector, &dev->mode_config.connector_list,
7613 base.head) {
7614 connector->base.encoder = &connector->new_encoder->base;
7615 }
7616
7617 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7618 base.head) {
7619 encoder->base.crtc = &encoder->new_crtc->base;
7620 }
7621}
7622
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007623static void
7624connected_sink_compute_bpp(struct intel_connector * connector,
7625 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007626{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007627 int bpp = pipe_config->pipe_bpp;
7628
7629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7630 connector->base.base.id,
7631 drm_get_connector_name(&connector->base));
7632
7633 /* Don't use an invalid EDID bpc value */
7634 if (connector->base.display_info.bpc &&
7635 connector->base.display_info.bpc * 3 < bpp) {
7636 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7637 bpp, connector->base.display_info.bpc*3);
7638 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7639 }
7640
7641 /* Clamp bpp to 8 on screens without EDID 1.4 */
7642 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7643 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7644 bpp);
7645 pipe_config->pipe_bpp = 24;
7646 }
7647}
7648
7649static int
7650compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7651 struct drm_framebuffer *fb,
7652 struct intel_crtc_config *pipe_config)
7653{
7654 struct drm_device *dev = crtc->base.dev;
7655 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007656 int bpp;
7657
Daniel Vetterd42264b2013-03-28 16:38:08 +01007658 switch (fb->pixel_format) {
7659 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007660 bpp = 8*3; /* since we go through a colormap */
7661 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007662 case DRM_FORMAT_XRGB1555:
7663 case DRM_FORMAT_ARGB1555:
7664 /* checked in intel_framebuffer_init already */
7665 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7666 return -EINVAL;
7667 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007668 bpp = 6*3; /* min is 18bpp */
7669 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007670 case DRM_FORMAT_XBGR8888:
7671 case DRM_FORMAT_ABGR8888:
7672 /* checked in intel_framebuffer_init already */
7673 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7674 return -EINVAL;
7675 case DRM_FORMAT_XRGB8888:
7676 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007677 bpp = 8*3;
7678 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007679 case DRM_FORMAT_XRGB2101010:
7680 case DRM_FORMAT_ARGB2101010:
7681 case DRM_FORMAT_XBGR2101010:
7682 case DRM_FORMAT_ABGR2101010:
7683 /* checked in intel_framebuffer_init already */
7684 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01007685 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007686 bpp = 10*3;
7687 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01007688 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007689 default:
7690 DRM_DEBUG_KMS("unsupported depth\n");
7691 return -EINVAL;
7692 }
7693
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007694 pipe_config->pipe_bpp = bpp;
7695
7696 /* Clamp display bpp to EDID value */
7697 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007698 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02007699 if (!connector->new_encoder ||
7700 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007701 continue;
7702
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007703 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007704 }
7705
7706 return bpp;
7707}
7708
Daniel Vetterc0b03412013-05-28 12:05:54 +02007709static void intel_dump_pipe_config(struct intel_crtc *crtc,
7710 struct intel_crtc_config *pipe_config,
7711 const char *context)
7712{
7713 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7714 context, pipe_name(crtc->pipe));
7715
7716 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7717 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7718 pipe_config->pipe_bpp, pipe_config->dither);
7719 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7720 pipe_config->has_pch_encoder,
7721 pipe_config->fdi_lanes,
7722 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7723 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7724 pipe_config->fdi_m_n.tu);
7725 DRM_DEBUG_KMS("requested mode:\n");
7726 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7727 DRM_DEBUG_KMS("adjusted mode:\n");
7728 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7729 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7730 pipe_config->gmch_pfit.control,
7731 pipe_config->gmch_pfit.pgm_ratios,
7732 pipe_config->gmch_pfit.lvds_border_bits);
7733 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7734 pipe_config->pch_pfit.pos,
7735 pipe_config->pch_pfit.size);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007736 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Daniel Vetterc0b03412013-05-28 12:05:54 +02007737}
7738
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02007739static bool check_encoder_cloning(struct drm_crtc *crtc)
7740{
7741 int num_encoders = 0;
7742 bool uncloneable_encoders = false;
7743 struct intel_encoder *encoder;
7744
7745 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7746 base.head) {
7747 if (&encoder->new_crtc->base != crtc)
7748 continue;
7749
7750 num_encoders++;
7751 if (!encoder->cloneable)
7752 uncloneable_encoders = true;
7753 }
7754
7755 return !(num_encoders > 1 && uncloneable_encoders);
7756}
7757
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007758static struct intel_crtc_config *
7759intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007760 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007761 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02007762{
7763 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02007764 struct drm_encoder_helper_funcs *encoder_funcs;
7765 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007766 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01007767 int plane_bpp, ret = -EINVAL;
7768 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02007769
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02007770 if (!check_encoder_cloning(crtc)) {
7771 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7772 return ERR_PTR(-EINVAL);
7773 }
7774
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007775 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7776 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02007777 return ERR_PTR(-ENOMEM);
7778
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007779 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7780 drm_mode_copy(&pipe_config->requested_mode, mode);
Daniel Vettereccb1402013-05-22 00:50:22 +02007781 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007782 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007783
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007784 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7785 * plane pixel format and any sink constraints into account. Returns the
7786 * source plane bpp so that dithering can be selected on mismatches
7787 * after encoders and crtc also have had their say. */
7788 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7789 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007790 if (plane_bpp < 0)
7791 goto fail;
7792
Daniel Vettere29c22c2013-02-21 00:00:16 +01007793encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02007794 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02007795 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02007796 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02007797
Daniel Vetter7758a112012-07-08 19:40:39 +02007798 /* Pass our mode to the connectors and the CRTC to give them a chance to
7799 * adjust it according to limitations or connector properties, and also
7800 * a chance to reject the mode entirely.
7801 */
7802 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7803 base.head) {
7804
7805 if (&encoder->new_crtc->base != crtc)
7806 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01007807
7808 if (encoder->compute_config) {
7809 if (!(encoder->compute_config(encoder, pipe_config))) {
7810 DRM_DEBUG_KMS("Encoder config failure\n");
7811 goto fail;
7812 }
7813
7814 continue;
7815 }
7816
Daniel Vetter7758a112012-07-08 19:40:39 +02007817 encoder_funcs = encoder->base.helper_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007818 if (!(encoder_funcs->mode_fixup(&encoder->base,
7819 &pipe_config->requested_mode,
7820 &pipe_config->adjusted_mode))) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007821 DRM_DEBUG_KMS("Encoder fixup failed\n");
7822 goto fail;
7823 }
7824 }
7825
Daniel Vetterff9a6752013-06-01 17:16:21 +02007826 /* Set default port clock if not overwritten by the encoder. Needs to be
7827 * done afterwards in case the encoder adjusts the mode. */
7828 if (!pipe_config->port_clock)
7829 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7830
Daniel Vettera43f6e02013-06-07 23:10:32 +02007831 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01007832 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007833 DRM_DEBUG_KMS("CRTC fixup failed\n");
7834 goto fail;
7835 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01007836
7837 if (ret == RETRY) {
7838 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7839 ret = -EINVAL;
7840 goto fail;
7841 }
7842
7843 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7844 retry = false;
7845 goto encoder_retry;
7846 }
7847
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007848 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7849 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7850 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7851
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007852 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02007853fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007854 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01007855 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02007856}
7857
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007858/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7859 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7860static void
7861intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7862 unsigned *prepare_pipes, unsigned *disable_pipes)
7863{
7864 struct intel_crtc *intel_crtc;
7865 struct drm_device *dev = crtc->dev;
7866 struct intel_encoder *encoder;
7867 struct intel_connector *connector;
7868 struct drm_crtc *tmp_crtc;
7869
7870 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7871
7872 /* Check which crtcs have changed outputs connected to them, these need
7873 * to be part of the prepare_pipes mask. We don't (yet) support global
7874 * modeset across multiple crtcs, so modeset_pipes will only have one
7875 * bit set at most. */
7876 list_for_each_entry(connector, &dev->mode_config.connector_list,
7877 base.head) {
7878 if (connector->base.encoder == &connector->new_encoder->base)
7879 continue;
7880
7881 if (connector->base.encoder) {
7882 tmp_crtc = connector->base.encoder->crtc;
7883
7884 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7885 }
7886
7887 if (connector->new_encoder)
7888 *prepare_pipes |=
7889 1 << connector->new_encoder->new_crtc->pipe;
7890 }
7891
7892 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7893 base.head) {
7894 if (encoder->base.crtc == &encoder->new_crtc->base)
7895 continue;
7896
7897 if (encoder->base.crtc) {
7898 tmp_crtc = encoder->base.crtc;
7899
7900 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7901 }
7902
7903 if (encoder->new_crtc)
7904 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7905 }
7906
7907 /* Check for any pipes that will be fully disabled ... */
7908 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7909 base.head) {
7910 bool used = false;
7911
7912 /* Don't try to disable disabled crtcs. */
7913 if (!intel_crtc->base.enabled)
7914 continue;
7915
7916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7917 base.head) {
7918 if (encoder->new_crtc == intel_crtc)
7919 used = true;
7920 }
7921
7922 if (!used)
7923 *disable_pipes |= 1 << intel_crtc->pipe;
7924 }
7925
7926
7927 /* set_mode is also used to update properties on life display pipes. */
7928 intel_crtc = to_intel_crtc(crtc);
7929 if (crtc->enabled)
7930 *prepare_pipes |= 1 << intel_crtc->pipe;
7931
Daniel Vetterb6c51642013-04-12 18:48:43 +02007932 /*
7933 * For simplicity do a full modeset on any pipe where the output routing
7934 * changed. We could be more clever, but that would require us to be
7935 * more careful with calling the relevant encoder->mode_set functions.
7936 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007937 if (*prepare_pipes)
7938 *modeset_pipes = *prepare_pipes;
7939
7940 /* ... and mask these out. */
7941 *modeset_pipes &= ~(*disable_pipes);
7942 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02007943
7944 /*
7945 * HACK: We don't (yet) fully support global modesets. intel_set_config
7946 * obies this rule, but the modeset restore mode of
7947 * intel_modeset_setup_hw_state does not.
7948 */
7949 *modeset_pipes &= 1 << intel_crtc->pipe;
7950 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02007951
7952 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7953 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007954}
7955
Daniel Vetterea9d7582012-07-10 10:42:52 +02007956static bool intel_crtc_in_use(struct drm_crtc *crtc)
7957{
7958 struct drm_encoder *encoder;
7959 struct drm_device *dev = crtc->dev;
7960
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7962 if (encoder->crtc == crtc)
7963 return true;
7964
7965 return false;
7966}
7967
7968static void
7969intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7970{
7971 struct intel_encoder *intel_encoder;
7972 struct intel_crtc *intel_crtc;
7973 struct drm_connector *connector;
7974
7975 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7976 base.head) {
7977 if (!intel_encoder->base.crtc)
7978 continue;
7979
7980 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7981
7982 if (prepare_pipes & (1 << intel_crtc->pipe))
7983 intel_encoder->connectors_active = false;
7984 }
7985
7986 intel_modeset_commit_output_state(dev);
7987
7988 /* Update computed state. */
7989 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7990 base.head) {
7991 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7992 }
7993
7994 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7995 if (!connector->encoder || !connector->encoder->crtc)
7996 continue;
7997
7998 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7999
8000 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02008001 struct drm_property *dpms_property =
8002 dev->mode_config.dpms_property;
8003
Daniel Vetterea9d7582012-07-10 10:42:52 +02008004 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05008005 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02008006 dpms_property,
8007 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02008008
8009 intel_encoder = to_intel_encoder(connector->encoder);
8010 intel_encoder->connectors_active = true;
8011 }
8012 }
8013
8014}
8015
Daniel Vetter25c5b262012-07-08 22:08:04 +02008016#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8017 list_for_each_entry((intel_crtc), \
8018 &(dev)->mode_config.crtc_list, \
8019 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02008020 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02008021
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008022static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008023intel_pipe_config_compare(struct drm_device *dev,
8024 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008025 struct intel_crtc_config *pipe_config)
8026{
Daniel Vetter66e985c2013-06-05 13:34:20 +02008027#define PIPE_CONF_CHECK_X(name) \
8028 if (current_config->name != pipe_config->name) { \
8029 DRM_ERROR("mismatch in " #name " " \
8030 "(expected 0x%08x, found 0x%08x)\n", \
8031 current_config->name, \
8032 pipe_config->name); \
8033 return false; \
8034 }
8035
Daniel Vetter08a24032013-04-19 11:25:34 +02008036#define PIPE_CONF_CHECK_I(name) \
8037 if (current_config->name != pipe_config->name) { \
8038 DRM_ERROR("mismatch in " #name " " \
8039 "(expected %i, found %i)\n", \
8040 current_config->name, \
8041 pipe_config->name); \
8042 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01008043 }
8044
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008045#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8046 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8047 DRM_ERROR("mismatch in " #name " " \
8048 "(expected %i, found %i)\n", \
8049 current_config->name & (mask), \
8050 pipe_config->name & (mask)); \
8051 return false; \
8052 }
8053
Daniel Vetterbb760062013-06-06 14:55:52 +02008054#define PIPE_CONF_QUIRK(quirk) \
8055 ((current_config->quirks | pipe_config->quirks) & (quirk))
8056
Daniel Vettereccb1402013-05-22 00:50:22 +02008057 PIPE_CONF_CHECK_I(cpu_transcoder);
8058
Daniel Vetter08a24032013-04-19 11:25:34 +02008059 PIPE_CONF_CHECK_I(has_pch_encoder);
8060 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02008061 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8062 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8063 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8064 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8065 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02008066
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008067 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8068 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8069 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8070 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8071 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8072 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8073
8074 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8075 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8076 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8077 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8078 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8079 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8080
Daniel Vetter6c49f242013-06-06 12:45:25 +02008081 if (!HAS_PCH_SPLIT(dev))
8082 PIPE_CONF_CHECK_I(pixel_multiplier);
8083
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008084 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8085 DRM_MODE_FLAG_INTERLACE);
8086
Daniel Vetterbb760062013-06-06 14:55:52 +02008087 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8088 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8089 DRM_MODE_FLAG_PHSYNC);
8090 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8091 DRM_MODE_FLAG_NHSYNC);
8092 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8093 DRM_MODE_FLAG_PVSYNC);
8094 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8095 DRM_MODE_FLAG_NVSYNC);
8096 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07008097
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008098 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8099 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8100
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008101 PIPE_CONF_CHECK_I(gmch_pfit.control);
8102 /* pfit ratios are autocomputed by the hw on gen4+ */
8103 if (INTEL_INFO(dev)->gen < 4)
8104 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8105 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8106 PIPE_CONF_CHECK_I(pch_pfit.pos);
8107 PIPE_CONF_CHECK_I(pch_pfit.size);
8108
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008109 PIPE_CONF_CHECK_I(ips_enabled);
8110
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008111 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008112 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008113 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008114 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8115 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008116
Daniel Vetter66e985c2013-06-05 13:34:20 +02008117#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +02008118#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008119#undef PIPE_CONF_CHECK_FLAGS
Daniel Vetterbb760062013-06-06 14:55:52 +02008120#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008121
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008122 return true;
8123}
8124
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008125static void
8126check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008127{
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008128 struct intel_connector *connector;
8129
8130 list_for_each_entry(connector, &dev->mode_config.connector_list,
8131 base.head) {
8132 /* This also checks the encoder/connector hw state with the
8133 * ->get_hw_state callbacks. */
8134 intel_connector_check_state(connector);
8135
8136 WARN(&connector->new_encoder->base != connector->base.encoder,
8137 "connector's staged encoder doesn't match current encoder\n");
8138 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008139}
8140
8141static void
8142check_encoder_state(struct drm_device *dev)
8143{
8144 struct intel_encoder *encoder;
8145 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008146
8147 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8148 base.head) {
8149 bool enabled = false;
8150 bool active = false;
8151 enum pipe pipe, tracked_pipe;
8152
8153 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8154 encoder->base.base.id,
8155 drm_get_encoder_name(&encoder->base));
8156
8157 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8158 "encoder's stage crtc doesn't match current crtc\n");
8159 WARN(encoder->connectors_active && !encoder->base.crtc,
8160 "encoder's active_connectors set, but no crtc\n");
8161
8162 list_for_each_entry(connector, &dev->mode_config.connector_list,
8163 base.head) {
8164 if (connector->base.encoder != &encoder->base)
8165 continue;
8166 enabled = true;
8167 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8168 active = true;
8169 }
8170 WARN(!!encoder->base.crtc != enabled,
8171 "encoder's enabled state mismatch "
8172 "(expected %i, found %i)\n",
8173 !!encoder->base.crtc, enabled);
8174 WARN(active && !encoder->base.crtc,
8175 "active encoder with no crtc\n");
8176
8177 WARN(encoder->connectors_active != active,
8178 "encoder's computed active state doesn't match tracked active state "
8179 "(expected %i, found %i)\n", active, encoder->connectors_active);
8180
8181 active = encoder->get_hw_state(encoder, &pipe);
8182 WARN(active != encoder->connectors_active,
8183 "encoder's hw state doesn't match sw tracking "
8184 "(expected %i, found %i)\n",
8185 encoder->connectors_active, active);
8186
8187 if (!encoder->base.crtc)
8188 continue;
8189
8190 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8191 WARN(active && pipe != tracked_pipe,
8192 "active encoder's pipe doesn't match"
8193 "(expected %i, found %i)\n",
8194 tracked_pipe, pipe);
8195
8196 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008197}
8198
8199static void
8200check_crtc_state(struct drm_device *dev)
8201{
8202 drm_i915_private_t *dev_priv = dev->dev_private;
8203 struct intel_crtc *crtc;
8204 struct intel_encoder *encoder;
8205 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008206
8207 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8208 base.head) {
8209 bool enabled = false;
8210 bool active = false;
8211
Jesse Barnes045ac3b2013-05-14 17:08:26 -07008212 memset(&pipe_config, 0, sizeof(pipe_config));
8213
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008214 DRM_DEBUG_KMS("[CRTC:%d]\n",
8215 crtc->base.base.id);
8216
8217 WARN(crtc->active && !crtc->base.enabled,
8218 "active crtc, but not enabled in sw tracking\n");
8219
8220 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8221 base.head) {
8222 if (encoder->base.crtc != &crtc->base)
8223 continue;
8224 enabled = true;
8225 if (encoder->connectors_active)
8226 active = true;
8227 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008228
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008229 WARN(active != crtc->active,
8230 "crtc's computed active state doesn't match tracked active state "
8231 "(expected %i, found %i)\n", active, crtc->active);
8232 WARN(enabled != crtc->base.enabled,
8233 "crtc's computed enabled state doesn't match tracked enabled state "
8234 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8235
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008236 active = dev_priv->display.get_pipe_config(crtc,
8237 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +02008238
8239 /* hw state is inconsistent with the pipe A quirk */
8240 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8241 active = crtc->active;
8242
Daniel Vetter6c49f242013-06-06 12:45:25 +02008243 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8244 base.head) {
8245 if (encoder->base.crtc != &crtc->base)
8246 continue;
8247 if (encoder->get_config)
8248 encoder->get_config(encoder, &pipe_config);
8249 }
8250
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008251 WARN(crtc->active != active,
8252 "crtc active state doesn't match with hw state "
8253 "(expected %i, found %i)\n", crtc->active, active);
8254
Daniel Vetterc0b03412013-05-28 12:05:54 +02008255 if (active &&
8256 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8257 WARN(1, "pipe state doesn't match!\n");
8258 intel_dump_pipe_config(crtc, &pipe_config,
8259 "[hw state]");
8260 intel_dump_pipe_config(crtc, &crtc->config,
8261 "[sw state]");
8262 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008263 }
8264}
8265
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008266static void
8267check_shared_dpll_state(struct drm_device *dev)
8268{
8269 drm_i915_private_t *dev_priv = dev->dev_private;
8270 struct intel_crtc *crtc;
8271 struct intel_dpll_hw_state dpll_hw_state;
8272 int i;
Daniel Vetter53589012013-06-05 13:34:16 +02008273
8274 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8275 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8276 int enabled_crtcs = 0, active_crtcs = 0;
8277 bool active;
8278
8279 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8280
8281 DRM_DEBUG_KMS("%s\n", pll->name);
8282
8283 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8284
8285 WARN(pll->active > pll->refcount,
8286 "more active pll users than references: %i vs %i\n",
8287 pll->active, pll->refcount);
8288 WARN(pll->active && !pll->on,
8289 "pll in active use but not on in sw tracking\n");
8290 WARN(pll->on != active,
8291 "pll on state mismatch (expected %i, found %i)\n",
8292 pll->on, active);
8293
8294 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8295 base.head) {
8296 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8297 enabled_crtcs++;
8298 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8299 active_crtcs++;
8300 }
8301 WARN(pll->active != active_crtcs,
8302 "pll active crtcs mismatch (expected %i, found %i)\n",
8303 pll->active, active_crtcs);
8304 WARN(pll->refcount != enabled_crtcs,
8305 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8306 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008307
8308 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8309 sizeof(dpll_hw_state)),
8310 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +02008311 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008312}
8313
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008314void
8315intel_modeset_check_state(struct drm_device *dev)
8316{
8317 check_connector_state(dev);
8318 check_encoder_state(dev);
8319 check_crtc_state(dev);
8320 check_shared_dpll_state(dev);
8321}
8322
Daniel Vetterf30da182013-04-11 20:22:50 +02008323static int __intel_set_mode(struct drm_crtc *crtc,
8324 struct drm_display_mode *mode,
8325 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02008326{
8327 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02008328 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008329 struct drm_display_mode *saved_mode, *saved_hwmode;
8330 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +02008331 struct intel_crtc *intel_crtc;
8332 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008333 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +02008334
Tim Gardner3ac18232012-12-07 07:54:26 -07008335 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008336 if (!saved_mode)
8337 return -ENOMEM;
Tim Gardner3ac18232012-12-07 07:54:26 -07008338 saved_hwmode = saved_mode + 1;
Daniel Vettera6778b32012-07-02 09:56:42 +02008339
Daniel Vettere2e1ed42012-07-08 21:14:38 +02008340 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02008341 &prepare_pipes, &disable_pipes);
8342
Tim Gardner3ac18232012-12-07 07:54:26 -07008343 *saved_hwmode = crtc->hwmode;
8344 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008345
Daniel Vetter25c5b262012-07-08 22:08:04 +02008346 /* Hack: Because we don't (yet) support global modeset on multiple
8347 * crtcs, we don't keep track of the new mode for more than one crtc.
8348 * Hence simply check whether any bit is set in modeset_pipes in all the
8349 * pieces of code that are not yet converted to deal with mutliple crtcs
8350 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008351 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008352 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008353 if (IS_ERR(pipe_config)) {
8354 ret = PTR_ERR(pipe_config);
8355 pipe_config = NULL;
8356
Tim Gardner3ac18232012-12-07 07:54:26 -07008357 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +02008358 }
Daniel Vetterc0b03412013-05-28 12:05:54 +02008359 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8360 "[modeset]");
Daniel Vettera6778b32012-07-02 09:56:42 +02008361 }
8362
Daniel Vetter460da9162013-03-27 00:44:51 +01008363 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8364 intel_crtc_disable(&intel_crtc->base);
8365
Daniel Vetterea9d7582012-07-10 10:42:52 +02008366 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8367 if (intel_crtc->base.enabled)
8368 dev_priv->display.crtc_disable(&intel_crtc->base);
8369 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008370
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02008371 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8372 * to set it here already despite that we pass it down the callchain.
8373 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008374 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +02008375 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008376 /* mode_set/enable/disable functions rely on a correct pipe
8377 * config. */
8378 to_intel_crtc(crtc)->config = *pipe_config;
8379 }
Daniel Vetter7758a112012-07-08 19:40:39 +02008380
Daniel Vetterea9d7582012-07-10 10:42:52 +02008381 /* Only after disabling all output pipelines that will be changed can we
8382 * update the the output configuration. */
8383 intel_modeset_update_state(dev, prepare_pipes);
8384
Daniel Vetter47fab732012-10-26 10:58:18 +02008385 if (dev_priv->display.modeset_global_resources)
8386 dev_priv->display.modeset_global_resources(dev);
8387
Daniel Vettera6778b32012-07-02 09:56:42 +02008388 /* Set up the DPLL and any encoders state that needs to adjust or depend
8389 * on the DPLL.
8390 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008391 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008392 ret = intel_crtc_mode_set(&intel_crtc->base,
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008393 x, y, fb);
8394 if (ret)
8395 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02008396 }
8397
8398 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008399 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8400 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02008401
Daniel Vetter25c5b262012-07-08 22:08:04 +02008402 if (modeset_pipes) {
8403 /* Store real post-adjustment hardware mode. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008404 crtc->hwmode = pipe_config->adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008405
Daniel Vetter25c5b262012-07-08 22:08:04 +02008406 /* Calculate and store various constants which
8407 * are later needed by vblank and swap-completion
8408 * timestamping. They are derived from true hwmode.
8409 */
8410 drm_calc_timestamping_constants(crtc);
8411 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008412
8413 /* FIXME: add subpixel order */
8414done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008415 if (ret && crtc->enabled) {
Tim Gardner3ac18232012-12-07 07:54:26 -07008416 crtc->hwmode = *saved_hwmode;
8417 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008418 }
8419
Tim Gardner3ac18232012-12-07 07:54:26 -07008420out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008421 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -07008422 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +02008423 return ret;
8424}
8425
Daniel Vetterf30da182013-04-11 20:22:50 +02008426int intel_set_mode(struct drm_crtc *crtc,
8427 struct drm_display_mode *mode,
8428 int x, int y, struct drm_framebuffer *fb)
8429{
8430 int ret;
8431
8432 ret = __intel_set_mode(crtc, mode, x, y, fb);
8433
8434 if (ret == 0)
8435 intel_modeset_check_state(crtc->dev);
8436
8437 return ret;
8438}
8439
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008440void intel_crtc_restore_mode(struct drm_crtc *crtc)
8441{
8442 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8443}
8444
Daniel Vetter25c5b262012-07-08 22:08:04 +02008445#undef for_each_intel_crtc_masked
8446
Daniel Vetterd9e55602012-07-04 22:16:09 +02008447static void intel_set_config_free(struct intel_set_config *config)
8448{
8449 if (!config)
8450 return;
8451
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008452 kfree(config->save_connector_encoders);
8453 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02008454 kfree(config);
8455}
8456
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008457static int intel_set_config_save_state(struct drm_device *dev,
8458 struct intel_set_config *config)
8459{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008460 struct drm_encoder *encoder;
8461 struct drm_connector *connector;
8462 int count;
8463
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008464 config->save_encoder_crtcs =
8465 kcalloc(dev->mode_config.num_encoder,
8466 sizeof(struct drm_crtc *), GFP_KERNEL);
8467 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008468 return -ENOMEM;
8469
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008470 config->save_connector_encoders =
8471 kcalloc(dev->mode_config.num_connector,
8472 sizeof(struct drm_encoder *), GFP_KERNEL);
8473 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008474 return -ENOMEM;
8475
8476 /* Copy data. Note that driver private data is not affected.
8477 * Should anything bad happen only the expected state is
8478 * restored, not the drivers personal bookkeeping.
8479 */
8480 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008481 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008482 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008483 }
8484
8485 count = 0;
8486 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008487 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008488 }
8489
8490 return 0;
8491}
8492
8493static void intel_set_config_restore_state(struct drm_device *dev,
8494 struct intel_set_config *config)
8495{
Daniel Vetter9a935852012-07-05 22:34:27 +02008496 struct intel_encoder *encoder;
8497 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008498 int count;
8499
8500 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008501 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8502 encoder->new_crtc =
8503 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008504 }
8505
8506 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008507 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8508 connector->new_encoder =
8509 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008510 }
8511}
8512
Imre Deake3de42b2013-05-03 19:44:07 +02008513static bool
8514is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8515 int num_connectors)
8516{
8517 int i;
8518
8519 for (i = 0; i < num_connectors; i++)
8520 if (connectors[i].encoder &&
8521 connectors[i].encoder->crtc == crtc &&
8522 connectors[i].dpms != DRM_MODE_DPMS_ON)
8523 return true;
8524
8525 return false;
8526}
8527
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008528static void
8529intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8530 struct intel_set_config *config)
8531{
8532
8533 /* We should be able to check here if the fb has the same properties
8534 * and then just flip_or_move it */
Imre Deake3de42b2013-05-03 19:44:07 +02008535 if (set->connectors != NULL &&
8536 is_crtc_connector_off(set->crtc, *set->connectors,
8537 set->num_connectors)) {
8538 config->mode_changed = true;
8539 } else if (set->crtc->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008540 /* If we have no fb then treat it as a full mode set */
8541 if (set->crtc->fb == NULL) {
8542 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8543 config->mode_changed = true;
8544 } else if (set->fb == NULL) {
8545 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +01008546 } else if (set->fb->pixel_format !=
8547 set->crtc->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008548 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02008549 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008550 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02008551 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008552 }
8553
Daniel Vetter835c5872012-07-10 18:11:08 +02008554 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008555 config->fb_changed = true;
8556
8557 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8558 DRM_DEBUG_KMS("modes are different, full mode set\n");
8559 drm_mode_debug_printmodeline(&set->crtc->mode);
8560 drm_mode_debug_printmodeline(set->mode);
8561 config->mode_changed = true;
8562 }
8563}
8564
Daniel Vetter2e431052012-07-04 22:42:15 +02008565static int
Daniel Vetter9a935852012-07-05 22:34:27 +02008566intel_modeset_stage_output_state(struct drm_device *dev,
8567 struct drm_mode_set *set,
8568 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02008569{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008570 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02008571 struct intel_connector *connector;
8572 struct intel_encoder *encoder;
Daniel Vetter2e431052012-07-04 22:42:15 +02008573 int count, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02008574
Damien Lespiau9abdda72013-02-13 13:29:23 +00008575 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +02008576 * of connectors. For paranoia, double-check this. */
8577 WARN_ON(!set->fb && (set->num_connectors != 0));
8578 WARN_ON(set->fb && (set->num_connectors == 0));
8579
Daniel Vetter50f56112012-07-02 09:35:43 +02008580 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008581 list_for_each_entry(connector, &dev->mode_config.connector_list,
8582 base.head) {
8583 /* Otherwise traverse passed in connector list and get encoders
8584 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008585 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008586 if (set->connectors[ro] == &connector->base) {
8587 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02008588 break;
8589 }
8590 }
8591
Daniel Vetter9a935852012-07-05 22:34:27 +02008592 /* If we disable the crtc, disable all its connectors. Also, if
8593 * the connector is on the changing crtc but not on the new
8594 * connector list, disable it. */
8595 if ((!set->fb || ro == set->num_connectors) &&
8596 connector->base.encoder &&
8597 connector->base.encoder->crtc == set->crtc) {
8598 connector->new_encoder = NULL;
8599
8600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8601 connector->base.base.id,
8602 drm_get_connector_name(&connector->base));
8603 }
8604
8605
8606 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008607 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008608 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008609 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008610 }
8611 /* connector->new_encoder is now updated for all connectors. */
8612
8613 /* Update crtc of enabled connectors. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008614 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008615 list_for_each_entry(connector, &dev->mode_config.connector_list,
8616 base.head) {
8617 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02008618 continue;
8619
Daniel Vetter9a935852012-07-05 22:34:27 +02008620 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02008621
8622 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008623 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02008624 new_crtc = set->crtc;
8625 }
8626
8627 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02008628 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8629 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008630 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02008631 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008632 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8633
8634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8635 connector->base.base.id,
8636 drm_get_connector_name(&connector->base),
8637 new_crtc->base.id);
8638 }
8639
8640 /* Check for any encoders that needs to be disabled. */
8641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8642 base.head) {
8643 list_for_each_entry(connector,
8644 &dev->mode_config.connector_list,
8645 base.head) {
8646 if (connector->new_encoder == encoder) {
8647 WARN_ON(!connector->new_encoder->new_crtc);
8648
8649 goto next_encoder;
8650 }
8651 }
8652 encoder->new_crtc = NULL;
8653next_encoder:
8654 /* Only now check for crtc changes so we don't miss encoders
8655 * that will be disabled. */
8656 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008657 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008658 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008659 }
8660 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008661 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008662
Daniel Vetter2e431052012-07-04 22:42:15 +02008663 return 0;
8664}
8665
8666static int intel_crtc_set_config(struct drm_mode_set *set)
8667{
8668 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02008669 struct drm_mode_set save_set;
8670 struct intel_set_config *config;
8671 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02008672
Daniel Vetter8d3e3752012-07-05 16:09:09 +02008673 BUG_ON(!set);
8674 BUG_ON(!set->crtc);
8675 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02008676
Daniel Vetter7e53f3a2013-01-21 10:52:17 +01008677 /* Enforce sane interface api - has been abused by the fb helper. */
8678 BUG_ON(!set->mode && set->fb);
8679 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +02008680
Daniel Vetter2e431052012-07-04 22:42:15 +02008681 if (set->fb) {
8682 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8683 set->crtc->base.id, set->fb->base.id,
8684 (int)set->num_connectors, set->x, set->y);
8685 } else {
8686 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02008687 }
8688
8689 dev = set->crtc->dev;
8690
8691 ret = -ENOMEM;
8692 config = kzalloc(sizeof(*config), GFP_KERNEL);
8693 if (!config)
8694 goto out_config;
8695
8696 ret = intel_set_config_save_state(dev, config);
8697 if (ret)
8698 goto out_config;
8699
8700 save_set.crtc = set->crtc;
8701 save_set.mode = &set->crtc->mode;
8702 save_set.x = set->crtc->x;
8703 save_set.y = set->crtc->y;
8704 save_set.fb = set->crtc->fb;
8705
8706 /* Compute whether we need a full modeset, only an fb base update or no
8707 * change at all. In the future we might also check whether only the
8708 * mode changed, e.g. for LVDS where we only change the panel fitter in
8709 * such cases. */
8710 intel_set_config_compute_mode_changes(set, config);
8711
Daniel Vetter9a935852012-07-05 22:34:27 +02008712 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02008713 if (ret)
8714 goto fail;
8715
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008716 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008717 ret = intel_set_mode(set->crtc, set->mode,
8718 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008719 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +02008720 intel_crtc_wait_for_pending_flips(set->crtc);
8721
Daniel Vetter4f660f42012-07-02 09:47:37 +02008722 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02008723 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02008724 }
8725
Chris Wilson2d05eae2013-05-03 17:36:25 +01008726 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +02008727 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8728 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +02008729fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +01008730 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008731
Chris Wilson2d05eae2013-05-03 17:36:25 +01008732 /* Try to restore the config */
8733 if (config->mode_changed &&
8734 intel_set_mode(save_set.crtc, save_set.mode,
8735 save_set.x, save_set.y, save_set.fb))
8736 DRM_ERROR("failed to restore config after modeset failure\n");
8737 }
Daniel Vetter50f56112012-07-02 09:35:43 +02008738
Daniel Vetterd9e55602012-07-04 22:16:09 +02008739out_config:
8740 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008741 return ret;
8742}
8743
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008744static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008745 .cursor_set = intel_crtc_cursor_set,
8746 .cursor_move = intel_crtc_cursor_move,
8747 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02008748 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008749 .destroy = intel_crtc_destroy,
8750 .page_flip = intel_crtc_page_flip,
8751};
8752
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008753static void intel_cpu_pll_init(struct drm_device *dev)
8754{
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008755 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008756 intel_ddi_pll_init(dev);
8757}
8758
Daniel Vetter53589012013-06-05 13:34:16 +02008759static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8760 struct intel_shared_dpll *pll,
8761 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008762{
Daniel Vetter53589012013-06-05 13:34:16 +02008763 uint32_t val;
8764
8765 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +02008766 hw_state->dpll = val;
8767 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8768 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +02008769
8770 return val & DPLL_VCO_ENABLE;
8771}
8772
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008773static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8774 struct intel_shared_dpll *pll)
8775{
8776 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8777 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8778}
8779
Daniel Vettere7b903d2013-06-05 13:34:14 +02008780static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8781 struct intel_shared_dpll *pll)
8782{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008783 /* PCH refclock must be enabled first */
8784 assert_pch_refclk_enabled(dev_priv);
8785
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008786 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8787
8788 /* Wait for the clocks to stabilize. */
8789 POSTING_READ(PCH_DPLL(pll->id));
8790 udelay(150);
8791
8792 /* The pixel multiplier can only be updated once the
8793 * DPLL is enabled and the clocks are stable.
8794 *
8795 * So write it again.
8796 */
8797 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8798 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02008799 udelay(200);
8800}
8801
8802static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8803 struct intel_shared_dpll *pll)
8804{
8805 struct drm_device *dev = dev_priv->dev;
8806 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +02008807
8808 /* Make sure no transcoder isn't still depending on us. */
8809 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8810 if (intel_crtc_to_shared_dpll(crtc) == pll)
8811 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8812 }
8813
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008814 I915_WRITE(PCH_DPLL(pll->id), 0);
8815 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02008816 udelay(200);
8817}
8818
Daniel Vetter46edb022013-06-05 13:34:12 +02008819static char *ibx_pch_dpll_names[] = {
8820 "PCH DPLL A",
8821 "PCH DPLL B",
8822};
8823
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008824static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008825{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008826 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008827 int i;
8828
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008829 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008830
Daniel Vettere72f9fb2013-06-05 13:34:06 +02008831 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +02008832 dev_priv->shared_dplls[i].id = i;
8833 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008834 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +02008835 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8836 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +02008837 dev_priv->shared_dplls[i].get_hw_state =
8838 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008839 }
8840}
8841
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008842static void intel_shared_dpll_init(struct drm_device *dev)
8843{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008844 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008845
8846 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8847 ibx_pch_dpll_init(dev);
8848 else
8849 dev_priv->num_shared_dpll = 0;
8850
8851 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8852 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8853 dev_priv->num_shared_dpll);
8854}
8855
Hannes Ederb358d0a2008-12-18 21:18:47 +01008856static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08008857{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008858 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008859 struct intel_crtc *intel_crtc;
8860 int i;
8861
8862 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8863 if (intel_crtc == NULL)
8864 return;
8865
8866 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8867
8868 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08008869 for (i = 0; i < 256; i++) {
8870 intel_crtc->lut_r[i] = i;
8871 intel_crtc->lut_g[i] = i;
8872 intel_crtc->lut_b[i] = i;
8873 }
8874
Jesse Barnes80824002009-09-10 15:28:06 -07008875 /* Swap pipes & planes for FBC on pre-965 */
8876 intel_crtc->pipe = pipe;
8877 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01008878 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008879 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01008880 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07008881 }
8882
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008883 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8884 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8885 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8886 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8887
Jesse Barnes79e53942008-11-07 14:24:08 -08008888 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08008889}
8890
Carl Worth08d7b3d2009-04-29 14:43:54 -07008891int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00008892 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07008893{
Carl Worth08d7b3d2009-04-29 14:43:54 -07008894 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02008895 struct drm_mode_object *drmmode_obj;
8896 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008897
Daniel Vetter1cff8f62012-04-24 09:55:08 +02008898 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8899 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008900
Daniel Vetterc05422d2009-08-11 16:05:30 +02008901 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8902 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07008903
Daniel Vetterc05422d2009-08-11 16:05:30 +02008904 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07008905 DRM_ERROR("no such CRTC id\n");
8906 return -EINVAL;
8907 }
8908
Daniel Vetterc05422d2009-08-11 16:05:30 +02008909 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8910 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008911
Daniel Vetterc05422d2009-08-11 16:05:30 +02008912 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008913}
8914
Daniel Vetter66a92782012-07-12 20:08:18 +02008915static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008916{
Daniel Vetter66a92782012-07-12 20:08:18 +02008917 struct drm_device *dev = encoder->base.dev;
8918 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008919 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008920 int entry = 0;
8921
Daniel Vetter66a92782012-07-12 20:08:18 +02008922 list_for_each_entry(source_encoder,
8923 &dev->mode_config.encoder_list, base.head) {
8924
8925 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008926 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02008927
8928 /* Intel hw has only one MUX where enocoders could be cloned. */
8929 if (encoder->cloneable && source_encoder->cloneable)
8930 index_mask |= (1 << entry);
8931
Jesse Barnes79e53942008-11-07 14:24:08 -08008932 entry++;
8933 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01008934
Jesse Barnes79e53942008-11-07 14:24:08 -08008935 return index_mask;
8936}
8937
Chris Wilson4d302442010-12-14 19:21:29 +00008938static bool has_edp_a(struct drm_device *dev)
8939{
8940 struct drm_i915_private *dev_priv = dev->dev_private;
8941
8942 if (!IS_MOBILE(dev))
8943 return false;
8944
8945 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8946 return false;
8947
8948 if (IS_GEN5(dev) &&
8949 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8950 return false;
8951
8952 return true;
8953}
8954
Jesse Barnes79e53942008-11-07 14:24:08 -08008955static void intel_setup_outputs(struct drm_device *dev)
8956{
Eric Anholt725e30a2009-01-22 13:01:02 -08008957 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008958 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008959 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08008960
Daniel Vetterc9093352013-06-06 22:22:47 +02008961 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008962
Paulo Zanonic40c0f52013-04-12 18:16:53 -03008963 if (!IS_ULT(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -02008964 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008965
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008966 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03008967 int found;
8968
8969 /* Haswell uses DDI functions to detect digital outputs */
8970 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8971 /* DDI A only supports eDP */
8972 if (found)
8973 intel_ddi_init(dev, PORT_A);
8974
8975 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8976 * register */
8977 found = I915_READ(SFUSE_STRAP);
8978
8979 if (found & SFUSE_STRAP_DDIB_DETECTED)
8980 intel_ddi_init(dev, PORT_B);
8981 if (found & SFUSE_STRAP_DDIC_DETECTED)
8982 intel_ddi_init(dev, PORT_C);
8983 if (found & SFUSE_STRAP_DDID_DETECTED)
8984 intel_ddi_init(dev, PORT_D);
8985 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008986 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +02008987 dpd_is_edp = intel_dpd_is_edp(dev);
8988
8989 if (has_edp_a(dev))
8990 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008991
Paulo Zanonidc0fa712013-02-19 16:21:46 -03008992 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08008993 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01008994 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008995 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -03008996 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008997 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008998 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008999 }
9000
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009001 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03009002 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009003
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009004 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03009005 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009006
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009007 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009008 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009009
Daniel Vetter270b3042012-10-27 15:52:05 +02009010 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009011 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07009012 } else if (IS_VALLEYVIEW(dev)) {
Gajanan Bhat19c03922012-09-27 19:13:07 +05309013 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
Ville Syrjälä67cfc202013-01-25 21:44:44 +02009014 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9015 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +05309016
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009017 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
Paulo Zanonie2debe92013-02-18 19:00:27 -03009018 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9019 PORT_B);
Ville Syrjälä67cfc202013-01-25 21:44:44 +02009020 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9021 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07009022 }
Zhenyu Wang103a1962009-11-27 11:44:36 +08009023 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08009024 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08009025
Paulo Zanonie2debe92013-02-18 19:00:27 -03009026 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009027 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009028 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009029 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9030 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009031 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009032 }
Ma Ling27185ae2009-08-24 13:50:23 +08009033
Imre Deake7281ea2013-05-08 13:14:08 +03009034 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009035 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -08009036 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04009037
9038 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04009039
Paulo Zanonie2debe92013-02-18 19:00:27 -03009040 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009041 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009042 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009043 }
Ma Ling27185ae2009-08-24 13:50:23 +08009044
Paulo Zanonie2debe92013-02-18 19:00:27 -03009045 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +08009046
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009047 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9048 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009049 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009050 }
Imre Deake7281ea2013-05-08 13:14:08 +03009051 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009052 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -08009053 }
Ma Ling27185ae2009-08-24 13:50:23 +08009054
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009055 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +03009056 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009057 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -07009058 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08009059 intel_dvo_init(dev);
9060
Zhenyu Wang103a1962009-11-27 11:44:36 +08009061 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08009062 intel_tv_init(dev);
9063
Chris Wilson4ef69c72010-09-09 15:14:28 +01009064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9065 encoder->base.possible_crtcs = encoder->crtc_mask;
9066 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02009067 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08009068 }
Chris Wilson47356eb2011-01-11 17:06:04 +00009069
Paulo Zanonidde86e22012-12-01 12:04:25 -02009070 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +02009071
9072 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009073}
9074
9075static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9076{
9077 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08009078
9079 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00009080 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009081
9082 kfree(intel_fb);
9083}
9084
9085static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00009086 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08009087 unsigned int *handle)
9088{
9089 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00009090 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08009091
Chris Wilson05394f32010-11-08 19:18:58 +00009092 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08009093}
9094
9095static const struct drm_framebuffer_funcs intel_fb_funcs = {
9096 .destroy = intel_user_framebuffer_destroy,
9097 .create_handle = intel_user_framebuffer_create_handle,
9098};
9099
Dave Airlie38651672010-03-30 05:34:13 +00009100int intel_framebuffer_init(struct drm_device *dev,
9101 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009102 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00009103 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08009104{
Chris Wilsona35cdaa2013-06-25 17:26:45 +01009105 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08009106 int ret;
9107
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009108 if (obj->tiling_mode == I915_TILING_Y) {
9109 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +01009110 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009111 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009112
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009113 if (mode_cmd->pitches[0] & 63) {
9114 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9115 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +01009116 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009117 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009118
Chris Wilsona35cdaa2013-06-25 17:26:45 +01009119 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9120 pitch_limit = 32*1024;
9121 } else if (INTEL_INFO(dev)->gen >= 4) {
9122 if (obj->tiling_mode)
9123 pitch_limit = 16*1024;
9124 else
9125 pitch_limit = 32*1024;
9126 } else if (INTEL_INFO(dev)->gen >= 3) {
9127 if (obj->tiling_mode)
9128 pitch_limit = 8*1024;
9129 else
9130 pitch_limit = 16*1024;
9131 } else
9132 /* XXX DSPC is limited to 4k tiled */
9133 pitch_limit = 8*1024;
9134
9135 if (mode_cmd->pitches[0] > pitch_limit) {
9136 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9137 obj->tiling_mode ? "tiled" : "linear",
9138 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009139 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009140 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009141
9142 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009143 mode_cmd->pitches[0] != obj->stride) {
9144 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9145 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009146 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009147 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009148
Ville Syrjälä57779d02012-10-31 17:50:14 +02009149 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009150 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +02009151 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +02009152 case DRM_FORMAT_RGB565:
9153 case DRM_FORMAT_XRGB8888:
9154 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02009155 break;
9156 case DRM_FORMAT_XRGB1555:
9157 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009158 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009159 DRM_DEBUG("unsupported pixel format: %s\n",
9160 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009161 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009162 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02009163 break;
9164 case DRM_FORMAT_XBGR8888:
9165 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02009166 case DRM_FORMAT_XRGB2101010:
9167 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02009168 case DRM_FORMAT_XBGR2101010:
9169 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009170 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009171 DRM_DEBUG("unsupported pixel format: %s\n",
9172 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009173 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009174 }
Jesse Barnesb5626742011-06-24 12:19:27 -07009175 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02009176 case DRM_FORMAT_YUYV:
9177 case DRM_FORMAT_UYVY:
9178 case DRM_FORMAT_YVYU:
9179 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009180 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009181 DRM_DEBUG("unsupported pixel format: %s\n",
9182 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009183 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009184 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009185 break;
9186 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009187 DRM_DEBUG("unsupported pixel format: %s\n",
9188 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +01009189 return -EINVAL;
9190 }
9191
Ville Syrjälä90f9a332012-10-31 17:50:19 +02009192 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9193 if (mode_cmd->offsets[0] != 0)
9194 return -EINVAL;
9195
Daniel Vetterc7d73f62012-12-13 23:38:38 +01009196 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9197 intel_fb->obj = obj;
9198
Jesse Barnes79e53942008-11-07 14:24:08 -08009199 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9200 if (ret) {
9201 DRM_ERROR("framebuffer init failed %d\n", ret);
9202 return ret;
9203 }
9204
Jesse Barnes79e53942008-11-07 14:24:08 -08009205 return 0;
9206}
9207
Jesse Barnes79e53942008-11-07 14:24:08 -08009208static struct drm_framebuffer *
9209intel_user_framebuffer_create(struct drm_device *dev,
9210 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009211 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08009212{
Chris Wilson05394f32010-11-08 19:18:58 +00009213 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08009214
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009215 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9216 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00009217 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01009218 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08009219
Chris Wilsond2dff872011-04-19 08:36:26 +01009220 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08009221}
9222
Jesse Barnes79e53942008-11-07 14:24:08 -08009223static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08009224 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00009225 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08009226};
9227
Jesse Barnese70236a2009-09-21 10:42:27 -07009228/* Set up chip specific display functions */
9229static void intel_init_display(struct drm_device *dev)
9230{
9231 struct drm_i915_private *dev_priv = dev->dev_private;
9232
Daniel Vetteree9300b2013-06-03 22:40:22 +02009233 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9234 dev_priv->display.find_dpll = g4x_find_best_dpll;
9235 else if (IS_VALLEYVIEW(dev))
9236 dev_priv->display.find_dpll = vlv_find_best_dpll;
9237 else if (IS_PINEVIEW(dev))
9238 dev_priv->display.find_dpll = pnv_find_best_dpll;
9239 else
9240 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9241
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009242 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009243 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009244 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02009245 dev_priv->display.crtc_enable = haswell_crtc_enable;
9246 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009247 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009248 dev_priv->display.update_plane = ironlake_update_plane;
9249 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009250 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -07009251 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02009252 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9253 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009254 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07009255 dev_priv->display.update_plane = ironlake_update_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -07009256 } else if (IS_VALLEYVIEW(dev)) {
9257 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9258 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9259 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9260 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9261 dev_priv->display.off = i9xx_crtc_off;
9262 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07009263 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009264 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -07009265 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02009266 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9267 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009268 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07009269 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07009270 }
Jesse Barnese70236a2009-09-21 10:42:27 -07009271
Jesse Barnese70236a2009-09-21 10:42:27 -07009272 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07009273 if (IS_VALLEYVIEW(dev))
9274 dev_priv->display.get_display_clock_speed =
9275 valleyview_get_display_clock_speed;
9276 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07009277 dev_priv->display.get_display_clock_speed =
9278 i945_get_display_clock_speed;
9279 else if (IS_I915G(dev))
9280 dev_priv->display.get_display_clock_speed =
9281 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05009282 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07009283 dev_priv->display.get_display_clock_speed =
9284 i9xx_misc_get_display_clock_speed;
9285 else if (IS_I915GM(dev))
9286 dev_priv->display.get_display_clock_speed =
9287 i915gm_get_display_clock_speed;
9288 else if (IS_I865G(dev))
9289 dev_priv->display.get_display_clock_speed =
9290 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02009291 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07009292 dev_priv->display.get_display_clock_speed =
9293 i855_get_display_clock_speed;
9294 else /* 852, 830 */
9295 dev_priv->display.get_display_clock_speed =
9296 i830_get_display_clock_speed;
9297
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08009298 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01009299 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07009300 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009301 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08009302 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07009303 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009304 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07009305 } else if (IS_IVYBRIDGE(dev)) {
9306 /* FIXME: detect B0+ stepping and use auto training */
9307 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009308 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +02009309 dev_priv->display.modeset_global_resources =
9310 ivb_modeset_global_resources;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03009311 } else if (IS_HASWELL(dev)) {
9312 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08009313 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02009314 dev_priv->display.modeset_global_resources =
9315 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -02009316 }
Jesse Barnes6067aae2011-04-28 15:04:31 -07009317 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08009318 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07009319 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009320
9321 /* Default just returns -ENODEV to indicate unsupported */
9322 dev_priv->display.queue_flip = intel_default_queue_flip;
9323
9324 switch (INTEL_INFO(dev)->gen) {
9325 case 2:
9326 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9327 break;
9328
9329 case 3:
9330 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9331 break;
9332
9333 case 4:
9334 case 5:
9335 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9336 break;
9337
9338 case 6:
9339 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9340 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009341 case 7:
9342 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9343 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009344 }
Jesse Barnese70236a2009-09-21 10:42:27 -07009345}
9346
Jesse Barnesb690e962010-07-19 13:53:12 -07009347/*
9348 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9349 * resume, or other times. This quirk makes sure that's the case for
9350 * affected systems.
9351 */
Akshay Joshi0206e352011-08-16 15:34:10 -04009352static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07009353{
9354 struct drm_i915_private *dev_priv = dev->dev_private;
9355
9356 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009357 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07009358}
9359
Keith Packard435793d2011-07-12 14:56:22 -07009360/*
9361 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9362 */
9363static void quirk_ssc_force_disable(struct drm_device *dev)
9364{
9365 struct drm_i915_private *dev_priv = dev->dev_private;
9366 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009367 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07009368}
9369
Carsten Emde4dca20e2012-03-15 15:56:26 +01009370/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01009371 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9372 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01009373 */
9374static void quirk_invert_brightness(struct drm_device *dev)
9375{
9376 struct drm_i915_private *dev_priv = dev->dev_private;
9377 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009378 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07009379}
9380
9381struct intel_quirk {
9382 int device;
9383 int subsystem_vendor;
9384 int subsystem_device;
9385 void (*hook)(struct drm_device *dev);
9386};
9387
Egbert Eich5f85f1762012-10-14 15:46:38 +02009388/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9389struct intel_dmi_quirk {
9390 void (*hook)(struct drm_device *dev);
9391 const struct dmi_system_id (*dmi_id_list)[];
9392};
9393
9394static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9395{
9396 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9397 return 1;
9398}
9399
9400static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9401 {
9402 .dmi_id_list = &(const struct dmi_system_id[]) {
9403 {
9404 .callback = intel_dmi_reverse_brightness,
9405 .ident = "NCR Corporation",
9406 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9407 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9408 },
9409 },
9410 { } /* terminating entry */
9411 },
9412 .hook = quirk_invert_brightness,
9413 },
9414};
9415
Ben Widawskyc43b5632012-04-16 14:07:40 -07009416static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07009417 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04009418 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07009419
Jesse Barnesb690e962010-07-19 13:53:12 -07009420 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9421 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9422
Jesse Barnesb690e962010-07-19 13:53:12 -07009423 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9424 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9425
Daniel Vetterccd0d362012-10-10 23:13:59 +02009426 /* 830/845 need to leave pipe A & dpll A up */
Jesse Barnesb690e962010-07-19 13:53:12 -07009427 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02009428 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07009429
9430 /* Lenovo U160 cannot use SSC on LVDS */
9431 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02009432
9433 /* Sony Vaio Y cannot use SSC on LVDS */
9434 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01009435
9436 /* Acer Aspire 5734Z must invert backlight brightness */
9437 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jani Nikula1ffff602013-01-22 12:50:34 +02009438
9439 /* Acer/eMachines G725 */
9440 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
Jani Nikula01e3a8f2013-01-22 12:50:35 +02009441
9442 /* Acer/eMachines e725 */
9443 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
Jani Nikula5559eca2013-01-22 12:50:36 +02009444
9445 /* Acer/Packard Bell NCL20 */
9446 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
Daniel Vetterac4199e2013-02-15 18:35:30 +01009447
9448 /* Acer Aspire 4736Z */
9449 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07009450};
9451
9452static void intel_init_quirks(struct drm_device *dev)
9453{
9454 struct pci_dev *d = dev->pdev;
9455 int i;
9456
9457 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9458 struct intel_quirk *q = &intel_quirks[i];
9459
9460 if (d->device == q->device &&
9461 (d->subsystem_vendor == q->subsystem_vendor ||
9462 q->subsystem_vendor == PCI_ANY_ID) &&
9463 (d->subsystem_device == q->subsystem_device ||
9464 q->subsystem_device == PCI_ANY_ID))
9465 q->hook(dev);
9466 }
Egbert Eich5f85f1762012-10-14 15:46:38 +02009467 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9468 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9469 intel_dmi_quirks[i].hook(dev);
9470 }
Jesse Barnesb690e962010-07-19 13:53:12 -07009471}
9472
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009473/* Disable the VGA plane that we never use */
9474static void i915_disable_vga(struct drm_device *dev)
9475{
9476 struct drm_i915_private *dev_priv = dev->dev_private;
9477 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02009478 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009479
9480 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07009481 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009482 sr1 = inb(VGA_SR_DATA);
9483 outb(sr1 | 1<<5, VGA_SR_DATA);
9484 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9485 udelay(300);
9486
9487 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9488 POSTING_READ(vga_reg);
9489}
9490
Daniel Vetterf8175862012-04-10 15:50:11 +02009491void intel_modeset_init_hw(struct drm_device *dev)
9492{
Paulo Zanonifa42e232013-01-25 16:59:11 -02009493 intel_init_power_well(dev);
Eugeni Dodonov0232e922012-07-06 15:42:36 -03009494
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03009495 intel_prepare_ddi(dev);
9496
Daniel Vetterf8175862012-04-10 15:50:11 +02009497 intel_init_clock_gating(dev);
9498
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02009499 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02009500 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02009501 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02009502}
9503
Imre Deak7d708ee2013-04-17 14:04:50 +03009504void intel_modeset_suspend_hw(struct drm_device *dev)
9505{
9506 intel_suspend_hw(dev);
9507}
9508
Jesse Barnes79e53942008-11-07 14:24:08 -08009509void intel_modeset_init(struct drm_device *dev)
9510{
Jesse Barnes652c3932009-08-17 13:31:43 -07009511 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009512 int i, j, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08009513
9514 drm_mode_config_init(dev);
9515
9516 dev->mode_config.min_width = 0;
9517 dev->mode_config.min_height = 0;
9518
Dave Airlie019d96c2011-09-29 16:20:42 +01009519 dev->mode_config.preferred_depth = 24;
9520 dev->mode_config.prefer_shadow = 1;
9521
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02009522 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08009523
Jesse Barnesb690e962010-07-19 13:53:12 -07009524 intel_init_quirks(dev);
9525
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03009526 intel_init_pm(dev);
9527
Ben Widawskye3c74752013-04-05 13:12:39 -07009528 if (INTEL_INFO(dev)->num_pipes == 0)
9529 return;
9530
Jesse Barnese70236a2009-09-21 10:42:27 -07009531 intel_init_display(dev);
9532
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009533 if (IS_GEN2(dev)) {
9534 dev->mode_config.max_width = 2048;
9535 dev->mode_config.max_height = 2048;
9536 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07009537 dev->mode_config.max_width = 4096;
9538 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08009539 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009540 dev->mode_config.max_width = 8192;
9541 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08009542 }
Ben Widawsky5d4545a2013-01-17 12:45:15 -08009543 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -08009544
Zhao Yakui28c97732009-10-09 11:39:41 +08009545 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009546 INTEL_INFO(dev)->num_pipes,
9547 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08009548
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009549 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009550 intel_crtc_init(dev, i);
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009551 for (j = 0; j < dev_priv->num_plane; j++) {
9552 ret = intel_plane_init(dev, i, j);
9553 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +03009554 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9555 pipe_name(i), sprite_name(i, j), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009556 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009557 }
9558
Paulo Zanoni79f689a2012-10-05 12:05:52 -03009559 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02009560 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009561
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009562 /* Just disable it once at startup */
9563 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009564 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00009565
9566 /* Just in case the BIOS is doing something questionable. */
9567 intel_disable_fbc(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009568}
Jesse Barnesd5bb0812011-01-05 12:01:26 -08009569
Daniel Vetter24929352012-07-02 20:28:59 +02009570static void
9571intel_connector_break_all_links(struct intel_connector *connector)
9572{
9573 connector->base.dpms = DRM_MODE_DPMS_OFF;
9574 connector->base.encoder = NULL;
9575 connector->encoder->connectors_active = false;
9576 connector->encoder->base.crtc = NULL;
9577}
9578
Daniel Vetter7fad7982012-07-04 17:51:47 +02009579static void intel_enable_pipe_a(struct drm_device *dev)
9580{
9581 struct intel_connector *connector;
9582 struct drm_connector *crt = NULL;
9583 struct intel_load_detect_pipe load_detect_temp;
9584
9585 /* We can't just switch on the pipe A, we need to set things up with a
9586 * proper mode and output configuration. As a gross hack, enable pipe A
9587 * by enabling the load detect pipe once. */
9588 list_for_each_entry(connector,
9589 &dev->mode_config.connector_list,
9590 base.head) {
9591 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9592 crt = &connector->base;
9593 break;
9594 }
9595 }
9596
9597 if (!crt)
9598 return;
9599
9600 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9601 intel_release_load_detect_pipe(crt, &load_detect_temp);
9602
9603
9604}
9605
Daniel Vetterfa555832012-10-10 23:14:00 +02009606static bool
9607intel_check_plane_mapping(struct intel_crtc *crtc)
9608{
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009609 struct drm_device *dev = crtc->base.dev;
9610 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009611 u32 reg, val;
9612
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009613 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +02009614 return true;
9615
9616 reg = DSPCNTR(!crtc->plane);
9617 val = I915_READ(reg);
9618
9619 if ((val & DISPLAY_PLANE_ENABLE) &&
9620 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9621 return false;
9622
9623 return true;
9624}
9625
Daniel Vetter24929352012-07-02 20:28:59 +02009626static void intel_sanitize_crtc(struct intel_crtc *crtc)
9627{
9628 struct drm_device *dev = crtc->base.dev;
9629 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009630 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +02009631
Daniel Vetter24929352012-07-02 20:28:59 +02009632 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +02009633 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +02009634 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9635
9636 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +02009637 * disable the crtc (and hence change the state) if it is wrong. Note
9638 * that gen4+ has a fixed plane -> pipe mapping. */
9639 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +02009640 struct intel_connector *connector;
9641 bool plane;
9642
Daniel Vetter24929352012-07-02 20:28:59 +02009643 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9644 crtc->base.base.id);
9645
9646 /* Pipe has the wrong plane attached and the plane is active.
9647 * Temporarily change the plane mapping and disable everything
9648 * ... */
9649 plane = crtc->plane;
9650 crtc->plane = !plane;
9651 dev_priv->display.crtc_disable(&crtc->base);
9652 crtc->plane = plane;
9653
9654 /* ... and break all links. */
9655 list_for_each_entry(connector, &dev->mode_config.connector_list,
9656 base.head) {
9657 if (connector->encoder->base.crtc != &crtc->base)
9658 continue;
9659
9660 intel_connector_break_all_links(connector);
9661 }
9662
9663 WARN_ON(crtc->active);
9664 crtc->base.enabled = false;
9665 }
Daniel Vetter24929352012-07-02 20:28:59 +02009666
Daniel Vetter7fad7982012-07-04 17:51:47 +02009667 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9668 crtc->pipe == PIPE_A && !crtc->active) {
9669 /* BIOS forgot to enable pipe A, this mostly happens after
9670 * resume. Force-enable the pipe to fix this, the update_dpms
9671 * call below we restore the pipe to the right state, but leave
9672 * the required bits on. */
9673 intel_enable_pipe_a(dev);
9674 }
9675
Daniel Vetter24929352012-07-02 20:28:59 +02009676 /* Adjust the state of the output pipe according to whether we
9677 * have active connectors/encoders. */
9678 intel_crtc_update_dpms(&crtc->base);
9679
9680 if (crtc->active != crtc->base.enabled) {
9681 struct intel_encoder *encoder;
9682
9683 /* This can happen either due to bugs in the get_hw_state
9684 * functions or because the pipe is force-enabled due to the
9685 * pipe A quirk. */
9686 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9687 crtc->base.base.id,
9688 crtc->base.enabled ? "enabled" : "disabled",
9689 crtc->active ? "enabled" : "disabled");
9690
9691 crtc->base.enabled = crtc->active;
9692
9693 /* Because we only establish the connector -> encoder ->
9694 * crtc links if something is active, this means the
9695 * crtc is now deactivated. Break the links. connector
9696 * -> encoder links are only establish when things are
9697 * actually up, hence no need to break them. */
9698 WARN_ON(crtc->active);
9699
9700 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9701 WARN_ON(encoder->connectors_active);
9702 encoder->base.crtc = NULL;
9703 }
9704 }
9705}
9706
9707static void intel_sanitize_encoder(struct intel_encoder *encoder)
9708{
9709 struct intel_connector *connector;
9710 struct drm_device *dev = encoder->base.dev;
9711
9712 /* We need to check both for a crtc link (meaning that the
9713 * encoder is active and trying to read from a pipe) and the
9714 * pipe itself being active. */
9715 bool has_active_crtc = encoder->base.crtc &&
9716 to_intel_crtc(encoder->base.crtc)->active;
9717
9718 if (encoder->connectors_active && !has_active_crtc) {
9719 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9720 encoder->base.base.id,
9721 drm_get_encoder_name(&encoder->base));
9722
9723 /* Connector is active, but has no active pipe. This is
9724 * fallout from our resume register restoring. Disable
9725 * the encoder manually again. */
9726 if (encoder->base.crtc) {
9727 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9728 encoder->base.base.id,
9729 drm_get_encoder_name(&encoder->base));
9730 encoder->disable(encoder);
9731 }
9732
9733 /* Inconsistent output/port/pipe state happens presumably due to
9734 * a bug in one of the get_hw_state functions. Or someplace else
9735 * in our code, like the register restore mess on resume. Clamp
9736 * things to off as a safer default. */
9737 list_for_each_entry(connector,
9738 &dev->mode_config.connector_list,
9739 base.head) {
9740 if (connector->encoder != encoder)
9741 continue;
9742
9743 intel_connector_break_all_links(connector);
9744 }
9745 }
9746 /* Enabled encoders without active connectors will be fixed in
9747 * the crtc fixup. */
9748}
9749
Daniel Vetter44cec742013-01-25 17:53:21 +01009750void i915_redisable_vga(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009751{
9752 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02009753 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009754
9755 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9756 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
Ville Syrjälä209d5212013-01-25 21:44:48 +02009757 i915_disable_vga(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009758 }
9759}
9760
Daniel Vetter30e984d2013-06-05 13:34:17 +02009761static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +02009762{
9763 struct drm_i915_private *dev_priv = dev->dev_private;
9764 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +02009765 struct intel_crtc *crtc;
9766 struct intel_encoder *encoder;
9767 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +02009768 int i;
Daniel Vetter24929352012-07-02 20:28:59 +02009769
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009770 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9771 base.head) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01009772 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +02009773
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009774 crtc->active = dev_priv->display.get_pipe_config(crtc,
9775 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +02009776
9777 crtc->base.enabled = crtc->active;
9778
9779 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9780 crtc->base.base.id,
9781 crtc->active ? "enabled" : "disabled");
9782 }
9783
Daniel Vetter53589012013-06-05 13:34:16 +02009784 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009785 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009786 intel_ddi_setup_hw_pll_state(dev);
9787
Daniel Vetter53589012013-06-05 13:34:16 +02009788 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9789 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9790
9791 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9792 pll->active = 0;
9793 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9794 base.head) {
9795 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9796 pll->active++;
9797 }
9798 pll->refcount = pll->active;
9799
9800 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9801 pll->name, pll->refcount);
9802 }
9803
Daniel Vetter24929352012-07-02 20:28:59 +02009804 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9805 base.head) {
9806 pipe = 0;
9807
9808 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009809 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9810 encoder->base.crtc = &crtc->base;
9811 if (encoder->get_config)
9812 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +02009813 } else {
9814 encoder->base.crtc = NULL;
9815 }
9816
9817 encoder->connectors_active = false;
9818 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9819 encoder->base.base.id,
9820 drm_get_encoder_name(&encoder->base),
9821 encoder->base.crtc ? "enabled" : "disabled",
9822 pipe);
9823 }
9824
9825 list_for_each_entry(connector, &dev->mode_config.connector_list,
9826 base.head) {
9827 if (connector->get_hw_state(connector)) {
9828 connector->base.dpms = DRM_MODE_DPMS_ON;
9829 connector->encoder->connectors_active = true;
9830 connector->base.encoder = &connector->encoder->base;
9831 } else {
9832 connector->base.dpms = DRM_MODE_DPMS_OFF;
9833 connector->base.encoder = NULL;
9834 }
9835 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9836 connector->base.base.id,
9837 drm_get_connector_name(&connector->base),
9838 connector->base.encoder ? "enabled" : "disabled");
9839 }
Daniel Vetter30e984d2013-06-05 13:34:17 +02009840}
9841
9842/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9843 * and i915 state tracking structures. */
9844void intel_modeset_setup_hw_state(struct drm_device *dev,
9845 bool force_restore)
9846{
9847 struct drm_i915_private *dev_priv = dev->dev_private;
9848 enum pipe pipe;
9849 struct drm_plane *plane;
9850 struct intel_crtc *crtc;
9851 struct intel_encoder *encoder;
9852
9853 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02009854
9855 /* HW state is read out, now we need to sanitize this mess. */
9856 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9857 base.head) {
9858 intel_sanitize_encoder(encoder);
9859 }
9860
9861 for_each_pipe(pipe) {
9862 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9863 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +02009864 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +02009865 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009866
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009867 if (force_restore) {
Daniel Vetterf30da182013-04-11 20:22:50 +02009868 /*
9869 * We need to use raw interfaces for restoring state to avoid
9870 * checking (bogus) intermediate states.
9871 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009872 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -07009873 struct drm_crtc *crtc =
9874 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +02009875
9876 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9877 crtc->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009878 }
Jesse Barnesb5644d02013-03-26 13:25:27 -07009879 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9880 intel_plane_restore(plane);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009881
9882 i915_redisable_vga(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009883 } else {
9884 intel_modeset_update_staged_output_state(dev);
9885 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009886
9887 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +02009888
9889 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009890}
9891
9892void intel_modeset_gem_init(struct drm_device *dev)
9893{
Chris Wilson1833b132012-05-09 11:56:28 +01009894 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02009895
9896 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02009897
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009898 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -08009899}
9900
9901void intel_modeset_cleanup(struct drm_device *dev)
9902{
Jesse Barnes652c3932009-08-17 13:31:43 -07009903 struct drm_i915_private *dev_priv = dev->dev_private;
9904 struct drm_crtc *crtc;
9905 struct intel_crtc *intel_crtc;
9906
Daniel Vetterfd0c0642013-04-24 11:13:35 +02009907 /*
9908 * Interrupts and polling as the first thing to avoid creating havoc.
9909 * Too much stuff here (turning of rps, connectors, ...) would
9910 * experience fancy races otherwise.
9911 */
9912 drm_irq_uninstall(dev);
9913 cancel_work_sync(&dev_priv->hotplug_work);
9914 /*
9915 * Due to the hpd irq storm handling the hotplug work can re-arm the
9916 * poll handlers. Hence disable polling after hpd handling is shut down.
9917 */
Keith Packardf87ea762010-10-03 19:36:26 -07009918 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +02009919
Jesse Barnes652c3932009-08-17 13:31:43 -07009920 mutex_lock(&dev->struct_mutex);
9921
Jesse Barnes723bfd72010-10-07 16:01:13 -07009922 intel_unregister_dsm_handler();
9923
Jesse Barnes652c3932009-08-17 13:31:43 -07009924 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9925 /* Skip inactive CRTCs */
9926 if (!crtc->fb)
9927 continue;
9928
9929 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02009930 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07009931 }
9932
Chris Wilson973d04f2011-07-08 12:22:37 +01009933 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07009934
Daniel Vetter8090c6b2012-06-24 16:42:32 +02009935 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00009936
Daniel Vetter930ebb42012-06-29 23:32:16 +02009937 ironlake_teardown_rc6(dev);
9938
Kristian Høgsberg69341a52009-11-11 12:19:17 -05009939 mutex_unlock(&dev->struct_mutex);
9940
Chris Wilson1630fe72011-07-08 12:22:42 +01009941 /* flush any delayed tasks or pending work */
9942 flush_scheduled_work();
9943
Jani Nikuladc652f92013-04-12 15:18:38 +03009944 /* destroy backlight, if any, before the connectors */
9945 intel_panel_destroy_backlight(dev);
9946
Jesse Barnes79e53942008-11-07 14:24:08 -08009947 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +01009948
9949 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009950}
9951
Dave Airlie28d52042009-09-21 14:33:58 +10009952/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08009953 * Return which encoder is currently attached for connector.
9954 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01009955struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08009956{
Chris Wilsondf0e9242010-09-09 16:20:55 +01009957 return &intel_attached_encoder(connector)->base;
9958}
Jesse Barnes79e53942008-11-07 14:24:08 -08009959
Chris Wilsondf0e9242010-09-09 16:20:55 +01009960void intel_connector_attach_encoder(struct intel_connector *connector,
9961 struct intel_encoder *encoder)
9962{
9963 connector->encoder = encoder;
9964 drm_mode_connector_attach_encoder(&connector->base,
9965 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009966}
Dave Airlie28d52042009-09-21 14:33:58 +10009967
9968/*
9969 * set vga decode state - true == enable VGA decode
9970 */
9971int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9972{
9973 struct drm_i915_private *dev_priv = dev->dev_private;
9974 u16 gmch_ctrl;
9975
9976 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9977 if (state)
9978 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9979 else
9980 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9981 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9982 return 0;
9983}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009984
9985#ifdef CONFIG_DEBUG_FS
9986#include <linux/seq_file.h>
9987
9988struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -03009989
9990 u32 power_well_driver;
9991
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009992 struct intel_cursor_error_state {
9993 u32 control;
9994 u32 position;
9995 u32 base;
9996 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +01009997 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009998
9999 struct intel_pipe_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010000 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010001 u32 conf;
10002 u32 source;
10003
10004 u32 htotal;
10005 u32 hblank;
10006 u32 hsync;
10007 u32 vtotal;
10008 u32 vblank;
10009 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +010010010 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010011
10012 struct intel_plane_error_state {
10013 u32 control;
10014 u32 stride;
10015 u32 size;
10016 u32 pos;
10017 u32 addr;
10018 u32 surface;
10019 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010010020 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010021};
10022
10023struct intel_display_error_state *
10024intel_display_capture_error_state(struct drm_device *dev)
10025{
Akshay Joshi0206e352011-08-16 15:34:10 -040010026 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010027 struct intel_display_error_state *error;
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010028 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010029 int i;
10030
10031 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10032 if (error == NULL)
10033 return NULL;
10034
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010035 if (HAS_POWER_WELL(dev))
10036 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10037
Damien Lespiau52331302012-08-15 19:23:25 +010010038 for_each_pipe(i) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010039 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010040 error->pipe[i].cpu_transcoder = cpu_transcoder;
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010041
Paulo Zanonia18c4c32013-03-06 20:03:12 -030010042 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10043 error->cursor[i].control = I915_READ(CURCNTR(i));
10044 error->cursor[i].position = I915_READ(CURPOS(i));
10045 error->cursor[i].base = I915_READ(CURBASE(i));
10046 } else {
10047 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10048 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10049 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10050 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010051
10052 error->plane[i].control = I915_READ(DSPCNTR(i));
10053 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010054 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030010055 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010056 error->plane[i].pos = I915_READ(DSPPOS(i));
10057 }
Paulo Zanonica291362013-03-06 20:03:14 -030010058 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10059 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010060 if (INTEL_INFO(dev)->gen >= 4) {
10061 error->plane[i].surface = I915_READ(DSPSURF(i));
10062 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10063 }
10064
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010065 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010066 error->pipe[i].source = I915_READ(PIPESRC(i));
Paulo Zanonife2b8f92012-10-23 18:30:02 -020010067 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10068 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10069 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10070 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10071 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10072 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010073 }
10074
Paulo Zanoni12d217c2013-05-03 12:15:38 -030010075 /* In the code above we read the registers without checking if the power
10076 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10077 * prevent the next I915_WRITE from detecting it and printing an error
10078 * message. */
10079 if (HAS_POWER_WELL(dev))
10080 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10081
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010082 return error;
10083}
10084
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010085#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10086
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010087void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010088intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010089 struct drm_device *dev,
10090 struct intel_display_error_state *error)
10091{
10092 int i;
10093
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010094 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010095 if (HAS_POWER_WELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010096 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010097 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010010098 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010099 err_printf(m, "Pipe [%d]:\n", i);
10100 err_printf(m, " CPU transcoder: %c\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010101 transcoder_name(error->pipe[i].cpu_transcoder));
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010102 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10103 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10104 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10105 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10106 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10107 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10108 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10109 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010110
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010111 err_printf(m, "Plane [%d]:\n", i);
10112 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10113 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010114 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010115 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10116 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010117 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030010118 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010119 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010120 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010121 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10122 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010123 }
10124
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010125 err_printf(m, "Cursor [%d]:\n", i);
10126 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10127 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10128 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010129 }
10130}
10131#endif