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gerrit-public.fairphone.software / platform / external / llvm / 54c74823885eade8173965f8bb99f026aacb9657 / . / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
blob: 0a7d5eeb8709de2146f5ac55e4f171706a0e73eb [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]9
10#define DEBUG_TYPE "arm-disassembler"
11
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]12#include "llvm/MC/MCDisassembler.h"
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]15#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Benjamin Kramereea66f62011-11-11 12:39:41 +0000[diff] [blame]20#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith75e3b7f2012-04-03 15:48:14 +0000[diff] [blame]21#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]23#include "llvm/Support/ErrorHandling.h"
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]24#include "llvm/Support/LEB128.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +0000[diff] [blame]25#include "llvm/Support/MemoryObject.h"
Evan Cheng3e74d6f2011-08-24 18:08:43 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]28#include <vector>
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]29
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]30using namespace llvm;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]31
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]32typedef MCDisassembler::DecodeStatus DecodeStatus;
33
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]34namespace {
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]35 // Handles the condition code status of instructions in IT blocks
36 class ITStatus
37 {
38 public:
39 // Returns the condition code for instruction in IT block
40 unsigned getITCC() {
41 unsigned CC = ARMCC::AL;
42 if (instrInITBlock())
43 CC = ITStates.back();
44 return CC;
45 }
46
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
49 ITStates.pop_back();
50 }
51
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
55 }
56
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
60 }
61
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]67 unsigned CondBit0 = Firstcond & 1;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]68 unsigned NumTZ = CountTrailingZeros_32(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 if (T)
75 ITStates.push_back(CCBits);
76 else
77 ITStates.push_back(CCBits ^ 1);
78 }
79 ITStates.push_back(CCBits);
80 }
81
82 private:
83 std::vector<unsigned char> ITStates;
84 };
85}
86
87namespace {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]88/// ARMDisassembler - ARM disassembler for all ARM platforms.
89class ARMDisassembler : public MCDisassembler {
90public:
91 /// Constructor - Initializes the disassembler.
92 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]93 ARMDisassembler(const MCSubtargetInfo &STI) :
94 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]95 }
96
97 ~ARMDisassembler() {
98 }
99
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
102 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]103 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]104 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]107};
108
109/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110class ThumbDisassembler : public MCDisassembler {
111public:
112 /// Constructor - Initializes the disassembler.
113 ///
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]116 }
117
118 ~ThumbDisassembler() {
119 }
120
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
123 uint64_t &size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]124 const MemoryObject &region,
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]125 uint64_t address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]128
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]129private:
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]130 mutable ITStatus ITBlock;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]131 DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Andersona1c11002011-09-01 23:35:51 +0000[diff] [blame]132 void UpdateThumbVFPPredicate(MCInst&) const;
133};
134}
135
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]136static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]137 switch (In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
140 return true;
141 case MCDisassembler::SoftFail:
142 Out = In;
143 return true;
144 case MCDisassembler::Fail:
145 Out = In;
146 return false;
147 }
David Blaikie4d6ccb52012-01-20 21:51:11 +0000[diff] [blame]148 llvm_unreachable("Invalid DecodeStatus!");
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]149}
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]150
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]151
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]152// Forward declare these because the autogenerated code will reference them.
153// Definitions are further down.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]154static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]155 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]156static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
Mihai Popaf86e4362013-05-13 14:10:04 +0000[diff] [blame]159static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]162static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]163 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]164static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]165 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]166static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]167 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]168static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]169 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]170static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]171 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]172static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]173 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]174static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]175 unsigned RegNo,
176 uint64_t Address,
177 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]178static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]179 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]180static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]181 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]182static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]183 unsigned RegNo, uint64_t Address,
184 const void *Decoder);
Johnny Chen270159f2010-08-12 01:40:54 +0000[diff] [blame]185
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]186static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]187 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]188static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]189 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]190static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]191 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]192static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]193 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]194static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]195 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]196static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]197 uint64_t Address, const void *Decoder);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]198
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]199static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]200 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]201static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]202 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]203static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]204 unsigned Insn,
205 uint64_t Address,
206 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]207static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]208 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]209static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]210 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]211static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]212 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]213static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]214 uint64_t Address, const void *Decoder);
215
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]216static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]217 unsigned Insn,
218 uint64_t Adddress,
219 const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]220static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]221 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]222static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]223 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]224static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]225 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]226static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]227 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]228static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]229 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]230static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]231 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]232static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]233 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]234static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]235 uint64_t Address, const void *Decoder);
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]236static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]238static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]239 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]240static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]241 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]242static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]243 uint64_t Address, const void *Decoder);
Mihai Popa30a7a7c2013-05-20 14:57:05 +0000[diff] [blame]244static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]252static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]253 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]254static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]255 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]256static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]257 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]258static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]259 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]260static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]261 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]262static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]263 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]264static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]265 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]266static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]267 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]268static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]269 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]270static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]271 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]272static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]273 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]274static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]275 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]276static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]277 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]278static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]279 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]280static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]281 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]282static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]283 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]284static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]285 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]286static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]287 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]288static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]289 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]290static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]291 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]292static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]293 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]294static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]295 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]296static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]297 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]298static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]299 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]300static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]301 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]302static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]303 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]304static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]305 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]306static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]307 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]308static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]309 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]310static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]311 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]312static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]313 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]314static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]315 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]316static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]317 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]318static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]319 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]320static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]321 uint64_t Address, const void *Decoder);
Quentin Colombet7c4cf032013-04-17 18:46:12 +0000[diff] [blame]322static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
323 const void *Decoder);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]324
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]325
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]326static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]327 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]328static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]329 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]330static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]331 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]332static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]333 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]334static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]335 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]336static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]337 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]338static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]339 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]340static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]341 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]342static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]343 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]344static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]345 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]346static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]347 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]348static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]349 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]350static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]351 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]352static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]353 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]354static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]355 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]356static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]357 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]358static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]359 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]360static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]361 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]362static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]363 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]364static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]365 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]366static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]367 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]368static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]369 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]370static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]371 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]372static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]373 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]374static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]375 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]376static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]377 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]378static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]379 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]380static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]381 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]382static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]383 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]384static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]385 uint64_t Address, const void *Decoder);
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]386static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]387 uint64_t Address, const void *Decoder);
388
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]389static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]390 uint64_t Address, const void *Decoder);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]391static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]393#include "ARMGenDisassemblerTables.inc"
Sean Callanan9899f702010-04-13 21:21:57 +0000[diff] [blame]394
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]395static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
396 return new ARMDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]397}
398
James Molloyb9505852011-09-07 17:24:38 +0000[diff] [blame]399static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
400 return new ThumbDisassembler(STI);
Johnny Chenb68a3ee2010-04-02 22:27:38 +0000[diff] [blame]401}
402
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]403DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]404 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]405 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]406 raw_ostream &os,
407 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]408 CommentStream = &cs;
409
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]410 uint8_t bytes[4];
411
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]412 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
413 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
414
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]415 // We want to read exactly 4 bytes of data.
Benjamin Kramer49a6a8d2013-05-24 10:54:58 +0000[diff] [blame]416 if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]417 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]418 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]419 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]420
421 // Encoded as a small-endian 32-bit word in the stream.
422 uint32_t insn = (bytes[3] << 24) |
423 (bytes[2] << 16) |
424 (bytes[1] << 8) |
425 (bytes[0] << 0);
426
427 // Calling the auto-generated decoder function.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]428 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
429 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]430 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]431 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]432 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]433 }
434
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]435 // VFP and NEON instructions, similarly, are shared between ARM
436 // and Thumb modes.
437 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]438 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]439 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]440 Size = 4;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]441 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]442 }
443
444 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]445 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
446 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]447 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]448 Size = 4;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]453 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]454 }
455
456 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]457 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
458 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]459 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]460 Size = 4;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]461 // Add a fake predicate operand, because we share these instruction
462 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]463 if (!DecodePredicateOperand(MI, 0xE, Address, this))
464 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]465 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]466 }
467
468 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]469 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
470 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]471 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]472 Size = 4;
473 // Add a fake predicate operand, because we share these instruction
474 // definitions with Thumb2 where these instructions are predicable.
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]475 if (!DecodePredicateOperand(MI, 0xE, Address, this))
476 return MCDisassembler::Fail;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]477 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]478 }
479
480 MI.clear();
481
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]482 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]483 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]484}
485
486namespace llvm {
Benjamin Kramer1a2f9882011-10-22 16:50:00 +0000[diff] [blame]487extern const MCInstrDesc ARMInsts[];
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]488}
489
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]490/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
491/// immediate Value in the MCInst. The immediate Value has had any PC
492/// adjustment made by the caller. If the instruction is a branch instruction
493/// then isBranch is true, else false. If the getOpInfo() function was set as
494/// part of the setupForSymbolicDisassembly() call then that function is called
495/// to get any symbolic information at the Address for this instruction. If
496/// that returns non-zero then the symbolic information it returns is used to
497/// create an MCExpr and that is added as an operand to the MCInst. If
498/// getOpInfo() returns zero and isBranch is true then a symbol look up for
499/// Value is done and if a symbol is found an MCExpr is created with that, else
500/// an MCExpr with Value is created. This function returns true if it adds an
501/// operand to the MCInst and false otherwise.
502static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
503 bool isBranch, uint64_t InstSize,
504 MCInst &MI, const void *Decoder) {
505 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougacha2c94d0f2013-05-24 00:39:57 +0000[diff] [blame]506 // FIXME: Does it make sense for value to be negative?
507 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
508 /* Offset */ 0, InstSize);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]509}
510
511/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
512/// referenced by a load instruction with the base register that is the Pc.
513/// These can often be values in a literal pool near the Address of the
514/// instruction. The Address of the instruction and its immediate Value are
515/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledruc8e41c52012-07-23 08:51:15 +0000[diff] [blame]516/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]517/// the referenced address is that of a symbol. Or it will return a pointer to
518/// a literal 'C' string if the referenced address of the literal pool's entry
519/// is an address into a section with 'C' string literals.
520static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]521 const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]522 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
Ahmed Bougacha2c94d0f2013-05-24 00:39:57 +0000[diff] [blame]523 Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]524}
525
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]526// Thumb1 instructions don't have explicit S bits. Rather, they
527// implicitly set CPSR. Since it's not represented in the encoding, the
528// auto-generated decoder won't inject the CPSR operand. We need to fix
529// that as a post-pass.
530static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
531 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]532 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]533 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]534 for (unsigned i = 0; i < NumOps; ++i, ++I) {
535 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]536 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]537 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]538 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
539 return;
540 }
541 }
542
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]543 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]544}
545
546// Most Thumb instructions don't have explicit predicates in the
547// encoding, but rather get their predicates from IT context. We need
548// to fix up the predicate operands using this context information as a
549// post-pass.
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]550MCDisassembler::DecodeStatus
551ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]552 MCDisassembler::DecodeStatus S = Success;
553
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]554 // A few instructions actually have predicates encoded in them. Don't
555 // try to overwrite it if we're seeing one of those.
556 switch (MI.getOpcode()) {
557 case ARM::tBcc:
558 case ARM::t2Bcc:
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]559 case ARM::tCBZ:
560 case ARM::tCBNZ:
Owen Anderson9f666b52011-09-19 23:47:10 +0000[diff] [blame]561 case ARM::tCPS:
562 case ARM::t2CPS3p:
563 case ARM::t2CPS2p:
564 case ARM::t2CPS1p:
Owen Andersond9346fb2011-09-19 23:57:20 +0000[diff] [blame]565 case ARM::tMOVSr:
Owen Andersonc18e9402011-10-13 17:58:39 +0000[diff] [blame]566 case ARM::tSETEND:
Owen Anderson441462f2011-09-08 22:48:37 +0000[diff] [blame]567 // Some instructions (mostly conditional branches) are not
568 // allowed in IT blocks.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]569 if (ITBlock.instrInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]570 S = SoftFail;
571 else
572 return Success;
573 break;
574 case ARM::tB:
575 case ARM::t2B:
Owen Anderson04c78772011-09-19 22:34:23 +0000[diff] [blame]576 case ARM::t2TBB:
577 case ARM::t2TBH:
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]578 // Some instructions (mostly unconditional branches) can
579 // only appears at the end of, or outside of, an IT.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]580 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]581 S = SoftFail;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]582 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]583 default:
584 break;
585 }
586
587 // If we're in an IT block, base the predicate on that. Otherwise,
588 // assume a predicate of AL.
589 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]590 CC = ITBlock.getITCC();
591 if (CC == 0xF)
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]592 CC = ARMCC::AL;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]593 if (ITBlock.instrInITBlock())
594 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]595
596 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]597 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]598 MCInst::iterator I = MI.begin();
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]599 for (unsigned i = 0; i < NumOps; ++i, ++I) {
600 if (I == MI.end()) break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]601 if (OpInfo[i].isPredicate()) {
602 I = MI.insert(I, MCOperand::CreateImm(CC));
603 ++I;
604 if (CC == ARMCC::AL)
605 MI.insert(I, MCOperand::CreateReg(0));
606 else
607 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]608 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]609 }
610 }
611
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]612 I = MI.insert(I, MCOperand::CreateImm(CC));
613 ++I;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]614 if (CC == ARMCC::AL)
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]615 MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]616 else
Owen Anderson0aa38ab2011-08-17 18:14:48 +0000[diff] [blame]617 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]618
Owen Anderson51f6a7a2011-09-09 21:48:23 +0000[diff] [blame]619 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]620}
621
622// Thumb VFP instructions are a special case. Because we share their
623// encodings between ARM and Thumb modes, and they are predicable in ARM
624// mode, the auto-generated decoder will give them an (incorrect)
625// predicate operand. We need to rewrite these operands based on the IT
626// context as a post-pass.
627void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
628 unsigned CC;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]629 CC = ITBlock.getITCC();
630 if (ITBlock.instrInITBlock())
631 ITBlock.advanceITState();
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]632
633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
634 MCInst::iterator I = MI.begin();
Owen Anderson12a1e3b2011-08-24 21:35:46 +0000[diff] [blame]635 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
636 for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]637 if (OpInfo[i].isPredicate() ) {
638 I->setImm(CC);
639 ++I;
640 if (CC == ARMCC::AL)
641 I->setReg(0);
642 else
643 I->setReg(ARM::CPSR);
644 return;
645 }
646 }
647}
648
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]649DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuffadef06a2012-02-29 01:09:06 +0000[diff] [blame]650 const MemoryObject &Region,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]651 uint64_t Address,
Owen Anderson98c5dda2011-09-15 23:38:46 +0000[diff] [blame]652 raw_ostream &os,
653 raw_ostream &cs) const {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]654 CommentStream = &cs;
655
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]656 uint8_t bytes[4];
657
James Molloya5d58562011-09-07 19:42:28 +0000[diff] [blame]658 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
659 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
660
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]661 // We want to read exactly 2 bytes of data.
Benjamin Kramer49a6a8d2013-05-24 10:54:58 +0000[diff] [blame]662 if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]663 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]664 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]665 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]666
667 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]668 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
669 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]670 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]671 Size = 2;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]672 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]673 return result;
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]674 }
675
676 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]677 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
678 Address, this, STI);
Owen Anderson16280302011-08-16 23:45:44 +0000[diff] [blame]679 if (result) {
680 Size = 2;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]681 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]682 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]683 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]684 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]685 }
686
687 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]688 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
689 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]690 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]691 Size = 2;
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]692
693 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
694 // the Thumb predicate.
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]695 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson7011eee2011-10-06 23:33:11 +0000[diff] [blame]696 result = MCDisassembler::SoftFail;
697
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]698 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]699
700 // If we find an IT instruction, we need to parse its condition
701 // code and mask operands so that we can apply them correctly
702 // to the subsequent instructions.
703 if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson34626ac2011-09-14 21:06:21 +0000[diff] [blame]704
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]705 unsigned Firstcond = MI.getOperand(0).getImm();
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]706 unsigned Mask = MI.getOperand(1).getImm();
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]707 ITBlock.setITState(Firstcond, Mask);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]708 }
709
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]710 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]711 }
712
713 // We want to read exactly 4 bytes of data.
Benjamin Kramer49a6a8d2013-05-24 10:54:58 +0000[diff] [blame]714 if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]715 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]716 return MCDisassembler::Fail;
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]717 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]718
719 uint32_t insn32 = (bytes[3] << 8) |
720 (bytes[2] << 0) |
721 (bytes[1] << 24) |
722 (bytes[0] << 16);
723 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]724 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
725 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]726 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]727 Size = 4;
Richard Bartonf4478f92012-04-24 11:13:20 +0000[diff] [blame]728 bool InITBlock = ITBlock.instrInITBlock();
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]729 Check(result, AddThumbPredicate(MI));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]730 AddThumb1SBit(MI, InITBlock);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]731 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]732 }
733
734 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]735 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
736 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]737 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]738 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]739 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]740 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]741 }
742
743 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]744 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]745 if (result != MCDisassembler::Fail) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]746 Size = 4;
747 UpdateThumbVFPPredicate(MI);
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]748 return result;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]749 }
750
751 MI.clear();
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]752 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
753 this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]754 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]755 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]756 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]757 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]758 }
759
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]760 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]761 MI.clear();
762 uint32_t NEONLdStInsn = insn32;
763 NEONLdStInsn &= 0xF0FFFFFF;
764 NEONLdStInsn |= 0x04000000;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]765 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
766 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]767 if (result != MCDisassembler::Fail) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]768 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]769 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]770 return result;
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]771 }
772 }
773
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]774 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Andersonef2865a2011-08-15 23:38:54 +0000[diff] [blame]775 MI.clear();
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]776 uint32_t NEONDataInsn = insn32;
777 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
778 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
779 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]780 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
781 Address, this, STI);
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]782 if (result != MCDisassembler::Fail) {
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]783 Size = 4;
Owen Andersond2fc31b2011-09-08 22:42:49 +0000[diff] [blame]784 Check(result, AddThumbPredicate(MI));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]785 return result;
Owen Anderson8533eba2011-08-10 19:01:10 +0000[diff] [blame]786 }
787 }
788
Benjamin Kramer86ce8522011-08-26 18:21:36 +0000[diff] [blame]789 Size = 0;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]790 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]791}
792
793
794extern "C" void LLVMInitializeARMDisassembler() {
795 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
796 createARMDisassembler);
797 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
798 createThumbDisassembler);
799}
800
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]801static const uint16_t GPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]802 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
803 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
804 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
805 ARM::R12, ARM::SP, ARM::LR, ARM::PC
806};
807
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]808static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]809 uint64_t Address, const void *Decoder) {
810 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]811 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]812
813 unsigned Register = GPRDecoderTable[RegNo];
814 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]815 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]816}
817
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]818static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]819DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]820 uint64_t Address, const void *Decoder) {
Silviu Baranga5c062ad2012-03-20 15:54:56 +0000[diff] [blame]821 DecodeStatus S = MCDisassembler::Success;
822
823 if (RegNo == 15)
824 S = MCDisassembler::SoftFail;
825
826 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
827
828 return S;
Owen Anderson51c98052011-08-09 22:48:45 +0000[diff] [blame]829}
830
Mihai Popaf86e4362013-05-13 14:10:04 +0000[diff] [blame]831static DecodeStatus
832DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
833 uint64_t Address, const void *Decoder) {
834 DecodeStatus S = MCDisassembler::Success;
835
836 if (RegNo == 15)
837 {
838 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
839 return MCDisassembler::Success;
840 }
841
842 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
843 return S;
844}
845
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]846static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]847 uint64_t Address, const void *Decoder) {
848 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]849 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]850 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
851}
852
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]853static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]854 uint64_t Address, const void *Decoder) {
855 unsigned Register = 0;
856 switch (RegNo) {
857 case 0:
858 Register = ARM::R0;
859 break;
860 case 1:
861 Register = ARM::R1;
862 break;
863 case 2:
864 Register = ARM::R2;
865 break;
866 case 3:
867 Register = ARM::R3;
868 break;
869 case 9:
870 Register = ARM::R9;
871 break;
872 case 12:
873 Register = ARM::R12;
874 break;
875 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]876 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]877 }
878
879 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]880 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]881}
882
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]883static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]884 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]885 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
887}
888
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]889static const uint16_t SPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]890 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
891 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
892 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
893 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
894 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
895 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
896 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
897 ARM::S28, ARM::S29, ARM::S30, ARM::S31
898};
899
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]900static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]901 uint64_t Address, const void *Decoder) {
902 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]903 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]904
905 unsigned Register = SPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]907 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]908}
909
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]910static const uint16_t DPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]911 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
912 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
913 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
914 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
915 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
916 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
917 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
918 ARM::D28, ARM::D29, ARM::D30, ARM::D31
919};
920
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]921static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]922 uint64_t Address, const void *Decoder) {
923 if (RegNo > 31)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]924 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]925
926 unsigned Register = DPRDecoderTable[RegNo];
927 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]928 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]929}
930
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]931static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]932 uint64_t Address, const void *Decoder) {
933 if (RegNo > 7)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]934 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]935 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
936}
937
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]938static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]939DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]940 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]941 if (RegNo > 15)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]942 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]943 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
944}
945
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]946static const uint16_t QPRDecoderTable[] = {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]947 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
948 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
949 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
950 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
951};
952
953
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]954static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]955 uint64_t Address, const void *Decoder) {
Mihai Popabac932e2013-05-20 14:42:43 +0000[diff] [blame]956 if (RegNo > 31 || (RegNo & 1) != 0)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]957 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]958 RegNo >>= 1;
959
960 unsigned Register = QPRDecoderTable[RegNo];
961 Inst.addOperand(MCOperand::CreateReg(Register));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]962 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]963}
964
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]965static const uint16_t DPairDecoderTable[] = {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]966 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
967 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
968 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
969 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
970 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
971 ARM::Q15
972};
973
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]974static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]975 uint64_t Address, const void *Decoder) {
976 if (RegNo > 30)
977 return MCDisassembler::Fail;
978
979 unsigned Register = DPairDecoderTable[RegNo];
980 Inst.addOperand(MCOperand::CreateReg(Register));
981 return MCDisassembler::Success;
982}
983
Craig Topperb78ca422012-03-11 07:16:55 +0000[diff] [blame]984static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]985 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
986 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
987 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
988 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
989 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
990 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
991 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
992 ARM::D28_D30, ARM::D29_D31
993};
994
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]995static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]996 unsigned RegNo,
997 uint64_t Address,
998 const void *Decoder) {
999 if (RegNo > 29)
1000 return MCDisassembler::Fail;
1001
1002 unsigned Register = DPairSpacedDecoderTable[RegNo];
1003 Inst.addOperand(MCOperand::CreateReg(Register));
1004 return MCDisassembler::Success;
1005}
1006
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1007static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1008 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1009 if (Val == 0xF) return MCDisassembler::Fail;
Owen Andersonbd9091c2011-08-09 21:07:45 +0000[diff] [blame]1010 // AL predicate is not allowed on Thumb1 branches.
1011 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1012 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1013 Inst.addOperand(MCOperand::CreateImm(Val));
1014 if (Val == ARMCC::AL) {
1015 Inst.addOperand(MCOperand::CreateReg(0));
1016 } else
1017 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1018 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1019}
1020
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1021static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1022 uint64_t Address, const void *Decoder) {
1023 if (Val)
1024 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1025 else
1026 Inst.addOperand(MCOperand::CreateReg(0));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1027 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1028}
1029
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1030static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1031 uint64_t Address, const void *Decoder) {
1032 uint32_t imm = Val & 0xFF;
1033 uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedmanecb830e2011-10-13 23:36:06 +0000[diff] [blame]1034 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1035 Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1036 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1037}
1038
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1039static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1040 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1041 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1042
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1043 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1044 unsigned type = fieldFromInstruction(Val, 5, 2);
1045 unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1046
1047 // Register-immediate
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1049 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1050
1051 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1052 switch (type) {
1053 case 0:
1054 Shift = ARM_AM::lsl;
1055 break;
1056 case 1:
1057 Shift = ARM_AM::lsr;
1058 break;
1059 case 2:
1060 Shift = ARM_AM::asr;
1061 break;
1062 case 3:
1063 Shift = ARM_AM::ror;
1064 break;
1065 }
1066
1067 if (Shift == ARM_AM::ror && imm == 0)
1068 Shift = ARM_AM::rrx;
1069
1070 unsigned Op = Shift | (imm << 3);
1071 Inst.addOperand(MCOperand::CreateImm(Op));
1072
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1073 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1074}
1075
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1076static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1077 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1078 DecodeStatus S = MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1079
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1080 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1081 unsigned type = fieldFromInstruction(Val, 5, 2);
1082 unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1083
1084 // Register-register
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1086 return MCDisassembler::Fail;
1087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1088 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1089
1090 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1091 switch (type) {
1092 case 0:
1093 Shift = ARM_AM::lsl;
1094 break;
1095 case 1:
1096 Shift = ARM_AM::lsr;
1097 break;
1098 case 2:
1099 Shift = ARM_AM::asr;
1100 break;
1101 case 3:
1102 Shift = ARM_AM::ror;
1103 break;
1104 }
1105
1106 Inst.addOperand(MCOperand::CreateImm(Shift));
1107
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1108 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1109}
1110
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1111static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1112 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1113 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1114
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1115 bool writebackLoad = false;
1116 unsigned writebackReg = 0;
1117 switch (Inst.getOpcode()) {
1118 default:
1119 break;
1120 case ARM::LDMIA_UPD:
1121 case ARM::LDMDB_UPD:
1122 case ARM::LDMIB_UPD:
1123 case ARM::LDMDA_UPD:
1124 case ARM::t2LDMIA_UPD:
1125 case ARM::t2LDMDB_UPD:
1126 writebackLoad = true;
1127 writebackReg = Inst.getOperand(0).getReg();
1128 break;
1129 }
1130
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]1131 // Empty register lists are not allowed.
Benjamin Kramer4dc8bdf2013-05-19 22:01:57 +0000[diff] [blame]1132 if (Val == 0) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1133 for (unsigned i = 0; i < 16; ++i) {
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1134 if (Val & (1 << i)) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1135 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1136 return MCDisassembler::Fail;
Owen Anderson921d01a2011-09-09 23:13:33 +0000[diff] [blame]1137 // Writeback not allowed if Rn is in the target list.
1138 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1139 Check(S, MCDisassembler::SoftFail);
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1140 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1141 }
1142
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1143 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1144}
1145
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1146static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1147 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1148 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1149
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1150 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1151 unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1152
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1153 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1154 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1155 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1156 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1157 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1158 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1159
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1160 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1161}
1162
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1163static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1164 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1165 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1166
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1167 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1168 unsigned regs = fieldFromInstruction(Val, 0, 8);
Silviu Barangab422d0b2012-05-03 16:38:40 +0000[diff] [blame]1169
1170 regs = regs >> 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1171
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1172 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1173 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1174 for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1175 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1176 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]1177 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1178
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1179 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1180}
1181
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1182static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1183 uint64_t Address, const void *Decoder) {
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1184 // This operand encodes a mask of contiguous zeros between a specified MSB
1185 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1186 // the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1187 // the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]1188 // create the final mask.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1189 unsigned msb = fieldFromInstruction(Val, 5, 5);
1190 unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1191
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1192 DecodeStatus S = MCDisassembler::Success;
Kevin Enderby1c830932012-11-29 23:47:11 +0000[diff] [blame]1193 if (lsb > msb) {
1194 Check(S, MCDisassembler::SoftFail);
1195 // The check above will cause the warning for the "potentially undefined
1196 // instruction encoding" but we can't build a bad MCOperand value here
1197 // with a lsb > msb or else printing the MCInst will cause a crash.
1198 lsb = msb;
1199 }
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1200
Owen Anderson8b227782011-09-16 23:04:48 +0000[diff] [blame]1201 uint32_t msb_mask = 0xFFFFFFFF;
1202 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1203 uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson89db0f62011-09-16 22:29:48 +0000[diff] [blame]1204
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1205 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Andersoncb775512011-09-16 23:30:01 +0000[diff] [blame]1206 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1207}
1208
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1209static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1210 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1211 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1212
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1213 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1214 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1215 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1216 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1217 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1218 unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1219
1220 switch (Inst.getOpcode()) {
1221 case ARM::LDC_OFFSET:
1222 case ARM::LDC_PRE:
1223 case ARM::LDC_POST:
1224 case ARM::LDC_OPTION:
1225 case ARM::LDCL_OFFSET:
1226 case ARM::LDCL_PRE:
1227 case ARM::LDCL_POST:
1228 case ARM::LDCL_OPTION:
1229 case ARM::STC_OFFSET:
1230 case ARM::STC_PRE:
1231 case ARM::STC_POST:
1232 case ARM::STC_OPTION:
1233 case ARM::STCL_OFFSET:
1234 case ARM::STCL_PRE:
1235 case ARM::STCL_POST:
1236 case ARM::STCL_OPTION:
Owen Anderson8a83f712011-09-07 21:10:42 +0000[diff] [blame]1237 case ARM::t2LDC_OFFSET:
1238 case ARM::t2LDC_PRE:
1239 case ARM::t2LDC_POST:
1240 case ARM::t2LDC_OPTION:
1241 case ARM::t2LDCL_OFFSET:
1242 case ARM::t2LDCL_PRE:
1243 case ARM::t2LDCL_POST:
1244 case ARM::t2LDCL_OPTION:
1245 case ARM::t2STC_OFFSET:
1246 case ARM::t2STC_PRE:
1247 case ARM::t2STC_POST:
1248 case ARM::t2STC_OPTION:
1249 case ARM::t2STCL_OFFSET:
1250 case ARM::t2STCL_PRE:
1251 case ARM::t2STCL_POST:
1252 case ARM::t2STCL_OPTION:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1253 if (coproc == 0xA || coproc == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1254 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1255 break;
1256 default:
1257 break;
1258 }
1259
1260 Inst.addOperand(MCOperand::CreateImm(coproc));
1261 Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1263 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1264
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1265 switch (Inst.getOpcode()) {
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1266 case ARM::t2LDC2_OFFSET:
1267 case ARM::t2LDC2L_OFFSET:
1268 case ARM::t2LDC2_PRE:
1269 case ARM::t2LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1270 case ARM::t2STC2_OFFSET:
1271 case ARM::t2STC2L_OFFSET:
1272 case ARM::t2STC2_PRE:
1273 case ARM::t2STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1274 case ARM::LDC2_OFFSET:
1275 case ARM::LDC2L_OFFSET:
1276 case ARM::LDC2_PRE:
1277 case ARM::LDC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1278 case ARM::STC2_OFFSET:
1279 case ARM::STC2L_OFFSET:
1280 case ARM::STC2_PRE:
1281 case ARM::STC2L_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1282 case ARM::t2LDC_OFFSET:
1283 case ARM::t2LDCL_OFFSET:
1284 case ARM::t2LDC_PRE:
1285 case ARM::t2LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1286 case ARM::t2STC_OFFSET:
1287 case ARM::t2STCL_OFFSET:
1288 case ARM::t2STC_PRE:
1289 case ARM::t2STCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1290 case ARM::LDC_OFFSET:
1291 case ARM::LDCL_OFFSET:
1292 case ARM::LDC_PRE:
1293 case ARM::LDCL_PRE:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1294 case ARM::STC_OFFSET:
1295 case ARM::STCL_OFFSET:
1296 case ARM::STC_PRE:
1297 case ARM::STCL_PRE:
Jim Grosbach81b29282011-10-12 21:59:02 +0000[diff] [blame]1298 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1299 Inst.addOperand(MCOperand::CreateImm(imm));
1300 break;
1301 case ARM::t2LDC2_POST:
1302 case ARM::t2LDC2L_POST:
1303 case ARM::t2STC2_POST:
1304 case ARM::t2STC2L_POST:
1305 case ARM::LDC2_POST:
1306 case ARM::LDC2L_POST:
1307 case ARM::STC2_POST:
1308 case ARM::STC2L_POST:
1309 case ARM::t2LDC_POST:
1310 case ARM::t2LDCL_POST:
1311 case ARM::t2STC_POST:
1312 case ARM::t2STCL_POST:
1313 case ARM::LDC_POST:
1314 case ARM::LDCL_POST:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1315 case ARM::STC_POST:
1316 case ARM::STCL_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1317 imm |= U << 8;
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1318 // fall through.
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1319 default:
Jim Grosbachc66e7af2011-10-12 20:54:17 +0000[diff] [blame]1320 // The 'option' variant doesn't encode 'U' in the immediate since
1321 // the immediate is unsigned [0,255].
1322 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1323 break;
1324 }
1325
1326 switch (Inst.getOpcode()) {
1327 case ARM::LDC_OFFSET:
1328 case ARM::LDC_PRE:
1329 case ARM::LDC_POST:
1330 case ARM::LDC_OPTION:
1331 case ARM::LDCL_OFFSET:
1332 case ARM::LDCL_PRE:
1333 case ARM::LDCL_POST:
1334 case ARM::LDCL_OPTION:
1335 case ARM::STC_OFFSET:
1336 case ARM::STC_PRE:
1337 case ARM::STC_POST:
1338 case ARM::STC_OPTION:
1339 case ARM::STCL_OFFSET:
1340 case ARM::STCL_PRE:
1341 case ARM::STCL_POST:
1342 case ARM::STCL_OPTION:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1344 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1345 break;
1346 default:
1347 break;
1348 }
1349
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1350 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1351}
1352
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1353static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1354DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1355 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1356 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1357
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1358 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1359 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1360 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1361 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1362 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1363 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1364 unsigned P = fieldFromInstruction(Insn, 24, 1);
1365 unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1366
1367 // On stores, the writeback operand precedes Rt.
1368 switch (Inst.getOpcode()) {
1369 case ARM::STR_POST_IMM:
1370 case ARM::STR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1371 case ARM::STRB_POST_IMM:
1372 case ARM::STRB_POST_REG:
Jim Grosbach342ebd52011-08-11 22:18:00 +0000[diff] [blame]1373 case ARM::STRT_POST_REG:
1374 case ARM::STRT_POST_IMM:
Jim Grosbach10348e72011-08-11 20:04:56 +0000[diff] [blame]1375 case ARM::STRBT_POST_REG:
1376 case ARM::STRBT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1378 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1379 break;
1380 default:
1381 break;
1382 }
1383
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1385 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1386
1387 // On loads, the writeback operand comes after Rt.
1388 switch (Inst.getOpcode()) {
1389 case ARM::LDR_POST_IMM:
1390 case ARM::LDR_POST_REG:
Owen Anderson508e1d32011-08-11 20:47:56 +0000[diff] [blame]1391 case ARM::LDRB_POST_IMM:
1392 case ARM::LDRB_POST_REG:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1393 case ARM::LDRBT_POST_REG:
1394 case ARM::LDRBT_POST_IMM:
Jim Grosbach59999262011-08-10 23:43:54 +0000[diff] [blame]1395 case ARM::LDRT_POST_REG:
1396 case ARM::LDRT_POST_IMM:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1398 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1399 break;
1400 default:
1401 break;
1402 }
1403
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1405 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1406
1407 ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1408 if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1409 Op = ARM_AM::sub;
1410
1411 bool writeback = (P == 0) || (W == 1);
1412 unsigned idx_mode = 0;
1413 if (P && writeback)
1414 idx_mode = ARMII::IndexModePre;
1415 else if (!P && writeback)
1416 idx_mode = ARMII::IndexModePost;
1417
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1418 if (writeback && (Rn == 15 || Rn == Rt))
1419 S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson71156a62011-08-11 19:00:18 +0000[diff] [blame]1420
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1421 if (reg) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1422 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1423 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1424 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1425 switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1426 case 0:
1427 Opc = ARM_AM::lsl;
1428 break;
1429 case 1:
1430 Opc = ARM_AM::lsr;
1431 break;
1432 case 2:
1433 Opc = ARM_AM::asr;
1434 break;
1435 case 3:
1436 Opc = ARM_AM::ror;
1437 break;
1438 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1439 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1440 }
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1441 unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1442 if (Opc == ARM_AM::ror && amt == 0)
1443 Opc = ARM_AM::rrx;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1444 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1445
1446 Inst.addOperand(MCOperand::CreateImm(imm));
1447 } else {
1448 Inst.addOperand(MCOperand::CreateReg(0));
1449 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1450 Inst.addOperand(MCOperand::CreateImm(tmp));
1451 }
1452
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1454 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1455
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1456 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1457}
1458
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1459static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1460 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1461 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1462
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1463 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1464 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1465 unsigned type = fieldFromInstruction(Val, 5, 2);
1466 unsigned imm = fieldFromInstruction(Val, 7, 5);
1467 unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1468
Owen Anderson51157d22011-08-09 21:38:14 +0000[diff] [blame]1469 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1470 switch (type) {
1471 case 0:
1472 ShOp = ARM_AM::lsl;
1473 break;
1474 case 1:
1475 ShOp = ARM_AM::lsr;
1476 break;
1477 case 2:
1478 ShOp = ARM_AM::asr;
1479 break;
1480 case 3:
1481 ShOp = ARM_AM::ror;
1482 break;
1483 }
1484
Tim Northover93c7c442012-09-22 11:18:12 +0000[diff] [blame]1485 if (ShOp == ARM_AM::ror && imm == 0)
1486 ShOp = ARM_AM::rrx;
1487
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1489 return MCDisassembler::Fail;
1490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1491 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1492 unsigned shift;
1493 if (U)
1494 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1495 else
1496 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1497 Inst.addOperand(MCOperand::CreateImm(shift));
1498
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1499 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1500}
1501
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1502static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1503DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]1504 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1505 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1506
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1507 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1508 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1509 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1510 unsigned type = fieldFromInstruction(Insn, 22, 1);
1511 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1512 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1513 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1514 unsigned W = fieldFromInstruction(Insn, 21, 1);
1515 unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1516 unsigned Rt2 = Rt + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1517
1518 bool writeback = (W == 1) | (P == 0);
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1519
1520 // For {LD,ST}RD, Rt must be even, else undefined.
1521 switch (Inst.getOpcode()) {
1522 case ARM::STRD:
1523 case ARM::STRD_PRE:
1524 case ARM::STRD_POST:
1525 case ARM::LDRD:
1526 case ARM::LDRD_PRE:
1527 case ARM::LDRD_POST:
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1528 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1529 break;
1530 default:
1531 break;
1532 }
1533 switch (Inst.getOpcode()) {
1534 case ARM::STRD:
1535 case ARM::STRD_PRE:
1536 case ARM::STRD_POST:
1537 if (P == 0 && W == 1)
1538 S = MCDisassembler::SoftFail;
1539
1540 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1541 S = MCDisassembler::SoftFail;
1542 if (type && Rm == 15)
1543 S = MCDisassembler::SoftFail;
1544 if (Rt2 == 15)
1545 S = MCDisassembler::SoftFail;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1546 if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga6fe310e2012-03-22 14:14:49 +0000[diff] [blame]1547 S = MCDisassembler::SoftFail;
1548 break;
1549 case ARM::STRH:
1550 case ARM::STRH_PRE:
1551 case ARM::STRH_POST:
1552 if (Rt == 15)
1553 S = MCDisassembler::SoftFail;
1554 if (writeback && (Rn == 15 || Rn == Rt))
1555 S = MCDisassembler::SoftFail;
1556 if (!type && Rm == 15)
1557 S = MCDisassembler::SoftFail;
1558 break;
1559 case ARM::LDRD:
1560 case ARM::LDRD_PRE:
1561 case ARM::LDRD_POST:
1562 if (type && Rn == 15){
1563 if (Rt2 == 15)
1564 S = MCDisassembler::SoftFail;
1565 break;
1566 }
1567 if (P == 0 && W == 1)
1568 S = MCDisassembler::SoftFail;
1569 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1570 S = MCDisassembler::SoftFail;
1571 if (!type && writeback && Rn == 15)
1572 S = MCDisassembler::SoftFail;
1573 if (writeback && (Rn == Rt || Rn == Rt2))
1574 S = MCDisassembler::SoftFail;
1575 break;
1576 case ARM::LDRH:
1577 case ARM::LDRH_PRE:
1578 case ARM::LDRH_POST:
1579 if (type && Rn == 15){
1580 if (Rt == 15)
1581 S = MCDisassembler::SoftFail;
1582 break;
1583 }
1584 if (Rt == 15)
1585 S = MCDisassembler::SoftFail;
1586 if (!type && Rm == 15)
1587 S = MCDisassembler::SoftFail;
1588 if (!type && writeback && (Rn == 15 || Rn == Rt))
1589 S = MCDisassembler::SoftFail;
1590 break;
1591 case ARM::LDRSH:
1592 case ARM::LDRSH_PRE:
1593 case ARM::LDRSH_POST:
1594 case ARM::LDRSB:
1595 case ARM::LDRSB_PRE:
1596 case ARM::LDRSB_POST:
1597 if (type && Rn == 15){
1598 if (Rt == 15)
1599 S = MCDisassembler::SoftFail;
1600 break;
1601 }
1602 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1603 S = MCDisassembler::SoftFail;
1604 if (!type && (Rt == 15 || Rm == 15))
1605 S = MCDisassembler::SoftFail;
1606 if (!type && writeback && (Rn == 15 || Rn == Rt))
1607 S = MCDisassembler::SoftFail;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1608 break;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1609 default:
1610 break;
Owen Andersonc537f3b2011-08-15 20:51:32 +0000[diff] [blame]1611 }
1612
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1613 if (writeback) { // Writeback
1614 if (P)
1615 U |= ARMII::IndexModePre << 9;
1616 else
1617 U |= ARMII::IndexModePost << 9;
1618
1619 // On stores, the writeback operand precedes Rt.
1620 switch (Inst.getOpcode()) {
1621 case ARM::STRD:
1622 case ARM::STRD_PRE:
1623 case ARM::STRD_POST:
Owen Anderson79628e92011-08-12 20:02:50 +0000[diff] [blame]1624 case ARM::STRH:
1625 case ARM::STRH_PRE:
1626 case ARM::STRH_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1628 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1629 break;
1630 default:
1631 break;
1632 }
1633 }
1634
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1636 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1637 switch (Inst.getOpcode()) {
1638 case ARM::STRD:
1639 case ARM::STRD_PRE:
1640 case ARM::STRD_POST:
1641 case ARM::LDRD:
1642 case ARM::LDRD_PRE:
1643 case ARM::LDRD_POST:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1645 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1646 break;
1647 default:
1648 break;
1649 }
1650
1651 if (writeback) {
1652 // On loads, the writeback operand comes after Rt.
1653 switch (Inst.getOpcode()) {
1654 case ARM::LDRD:
1655 case ARM::LDRD_PRE:
1656 case ARM::LDRD_POST:
Owen Anderson0d094992011-08-12 20:36:11 +0000[diff] [blame]1657 case ARM::LDRH:
1658 case ARM::LDRH_PRE:
1659 case ARM::LDRH_POST:
1660 case ARM::LDRSH:
1661 case ARM::LDRSH_PRE:
1662 case ARM::LDRSH_POST:
1663 case ARM::LDRSB:
1664 case ARM::LDRSB_PRE:
1665 case ARM::LDRSB_POST:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1666 case ARM::LDRHTr:
1667 case ARM::LDRSBTr:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1669 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1670 break;
1671 default:
1672 break;
1673 }
1674 }
1675
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1677 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1678
1679 if (type) {
1680 Inst.addOperand(MCOperand::CreateReg(0));
1681 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1682 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1684 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1685 Inst.addOperand(MCOperand::CreateImm(U));
1686 }
1687
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1688 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1689 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1690
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1691 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1692}
1693
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1694static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1695 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1696 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1697
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1698 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1699 unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1700
1701 switch (mode) {
1702 case 0:
1703 mode = ARM_AM::da;
1704 break;
1705 case 1:
1706 mode = ARM_AM::ia;
1707 break;
1708 case 2:
1709 mode = ARM_AM::db;
1710 break;
1711 case 3:
1712 mode = ARM_AM::ib;
1713 break;
1714 }
1715
1716 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1718 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1719
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1720 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1721}
1722
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1723static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1724 unsigned Insn,
1725 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1726 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1727
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1728 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1729 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1730 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1731
1732 if (pred == 0xF) {
1733 switch (Inst.getOpcode()) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1734 case ARM::LDMDA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1735 Inst.setOpcode(ARM::RFEDA);
1736 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1737 case ARM::LDMDA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1738 Inst.setOpcode(ARM::RFEDA_UPD);
1739 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1740 case ARM::LDMDB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1741 Inst.setOpcode(ARM::RFEDB);
1742 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1743 case ARM::LDMDB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1744 Inst.setOpcode(ARM::RFEDB_UPD);
1745 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1746 case ARM::LDMIA:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1747 Inst.setOpcode(ARM::RFEIA);
1748 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1749 case ARM::LDMIA_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1750 Inst.setOpcode(ARM::RFEIA_UPD);
1751 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1752 case ARM::LDMIB:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1753 Inst.setOpcode(ARM::RFEIB);
1754 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1755 case ARM::LDMIB_UPD:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1756 Inst.setOpcode(ARM::RFEIB_UPD);
1757 break;
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1758 case ARM::STMDA:
1759 Inst.setOpcode(ARM::SRSDA);
1760 break;
1761 case ARM::STMDA_UPD:
1762 Inst.setOpcode(ARM::SRSDA_UPD);
1763 break;
1764 case ARM::STMDB:
1765 Inst.setOpcode(ARM::SRSDB);
1766 break;
1767 case ARM::STMDB_UPD:
1768 Inst.setOpcode(ARM::SRSDB_UPD);
1769 break;
1770 case ARM::STMIA:
1771 Inst.setOpcode(ARM::SRSIA);
1772 break;
1773 case ARM::STMIA_UPD:
1774 Inst.setOpcode(ARM::SRSIA_UPD);
1775 break;
1776 case ARM::STMIB:
1777 Inst.setOpcode(ARM::SRSIB);
1778 break;
1779 case ARM::STMIB_UPD:
1780 Inst.setOpcode(ARM::SRSIB_UPD);
1781 break;
1782 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1783 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1784 }
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1785
1786 // For stores (which become SRS's, the only operand is the mode.
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1787 if (fieldFromInstruction(Insn, 20, 1) == 0) {
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1788 Inst.addOperand(
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1789 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson846dd952011-08-18 22:31:17 +0000[diff] [blame]1790 return S;
1791 }
1792
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1793 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1794 }
1795
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1797 return MCDisassembler::Fail;
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1799 return MCDisassembler::Fail; // Tied
1800 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1801 return MCDisassembler::Fail;
1802 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1803 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1804
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1805 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1806}
1807
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1808static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1809 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1810 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1811 unsigned M = fieldFromInstruction(Insn, 17, 1);
1812 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1813 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1814
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1815 DecodeStatus S = MCDisassembler::Success;
Owen Anderson35008c22011-08-09 23:05:39 +0000[diff] [blame]1816
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1817 // imod == '01' --> UNPREDICTABLE
1818 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1819 // return failure here. The '01' imod value is unprintable, so there's
1820 // nothing useful we could do even if we returned UNPREDICTABLE.
1821
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1822 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1823
1824 if (imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1825 Inst.setOpcode(ARM::CPS3p);
1826 Inst.addOperand(MCOperand::CreateImm(imod));
1827 Inst.addOperand(MCOperand::CreateImm(iflags));
1828 Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1829 } else if (imod && !M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1830 Inst.setOpcode(ARM::CPS2p);
1831 Inst.addOperand(MCOperand::CreateImm(imod));
1832 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1833 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1834 } else if (!imod && M) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1835 Inst.setOpcode(ARM::CPS1p);
1836 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1837 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1838 } else {
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1839 // imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1840 Inst.setOpcode(ARM::CPS1p);
1841 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1842 S = MCDisassembler::SoftFail;
Owen Anderson1dd56f02011-08-18 22:15:25 +0000[diff] [blame]1843 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1844
Owen Anderson14090bf2011-08-18 22:11:02 +0000[diff] [blame]1845 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1846}
1847
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1848static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1849 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1850 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1851 unsigned M = fieldFromInstruction(Insn, 8, 1);
1852 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1853 unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1854
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1855 DecodeStatus S = MCDisassembler::Success;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1856
1857 // imod == '01' --> UNPREDICTABLE
1858 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1859 // return failure here. The '01' imod value is unprintable, so there's
1860 // nothing useful we could do even if we returned UNPREDICTABLE.
1861
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1862 if (imod == 1) return MCDisassembler::Fail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1863
1864 if (imod && M) {
1865 Inst.setOpcode(ARM::t2CPS3p);
1866 Inst.addOperand(MCOperand::CreateImm(imod));
1867 Inst.addOperand(MCOperand::CreateImm(iflags));
1868 Inst.addOperand(MCOperand::CreateImm(mode));
1869 } else if (imod && !M) {
1870 Inst.setOpcode(ARM::t2CPS2p);
1871 Inst.addOperand(MCOperand::CreateImm(imod));
1872 Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1873 if (mode) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1874 } else if (!imod && M) {
1875 Inst.setOpcode(ARM::t2CPS1p);
1876 Inst.addOperand(MCOperand::CreateImm(mode));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]1877 if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1878 } else {
Quentin Colombet1ad3a412013-04-26 17:54:54 +0000[diff] [blame]1879 // imod == '00' && M == '0' --> this is a HINT instruction
1880 int imm = fieldFromInstruction(Insn, 0, 8);
1881 // HINT are defined only for immediate in [0..4]
1882 if(imm > 4) return MCDisassembler::Fail;
1883 Inst.setOpcode(ARM::t2HINT);
1884 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1885 }
1886
1887 return S;
1888}
1889
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1890static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1891 uint64_t Address, const void *Decoder) {
1892 DecodeStatus S = MCDisassembler::Success;
1893
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1894 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1895 unsigned imm = 0;
1896
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1897 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1898 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1899 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1900 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1901
1902 if (Inst.getOpcode() == ARM::t2MOVTi16)
1903 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1904 return MCDisassembler::Fail;
1905 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1906 return MCDisassembler::Fail;
1907
1908 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1909 Inst.addOperand(MCOperand::CreateImm(imm));
1910
1911 return S;
1912}
1913
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1914static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1915 uint64_t Address, const void *Decoder) {
1916 DecodeStatus S = MCDisassembler::Success;
1917
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1918 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1919 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1920 unsigned imm = 0;
1921
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1922 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
1923 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1924
1925 if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover45210192013-04-19 09:58:09 +0000[diff] [blame]1926 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1927 return MCDisassembler::Fail;
Tim Northover45210192013-04-19 09:58:09 +0000[diff] [blame]1928
1929 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1930 return MCDisassembler::Fail;
1931
1932 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1933 Inst.addOperand(MCOperand::CreateImm(imm));
1934
1935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1936 return MCDisassembler::Fail;
1937
1938 return S;
1939}
Owen Anderson6153a032011-08-23 17:45:18 +0000[diff] [blame]1940
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1941static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1942 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1943 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1944
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1945 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
1946 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
1947 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
1948 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
1949 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1950
1951 if (pred == 0xF)
1952 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1953
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1954 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1955 return MCDisassembler::Fail;
1956 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1957 return MCDisassembler::Fail;
1958 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1959 return MCDisassembler::Fail;
1960 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1961 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1962
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1964 return MCDisassembler::Fail;
Owen Anderson1fb66732011-08-11 22:05:38 +0000[diff] [blame]1965
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1966 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1967}
1968
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1969static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1970 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1971 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1972
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1973 unsigned add = fieldFromInstruction(Val, 12, 1);
1974 unsigned imm = fieldFromInstruction(Val, 0, 12);
1975 unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1976
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1979
1980 if (!add) imm *= -1;
1981 if (imm == 0 && !add) imm = INT32_MIN;
1982 Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]1983 if (Rn == 15)
1984 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1985
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1986 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1987}
1988
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]1989static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1990 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1991 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]1992
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]1993 unsigned Rn = fieldFromInstruction(Val, 9, 4);
1994 unsigned U = fieldFromInstruction(Val, 8, 1);
1995 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1996
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]1997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1998 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]1999
2000 if (U)
2001 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2002 else
2003 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2004
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2005 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2006}
2007
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2008static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2009 uint64_t Address, const void *Decoder) {
2010 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2011}
2012
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2013static DecodeStatus
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2014DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2015 uint64_t Address, const void *Decoder) {
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame]2016 DecodeStatus Status = MCDisassembler::Success;
2017
2018 // Note the J1 and J2 values are from the encoded instruction. So here
2019 // change them to I1 and I2 values via as documented:
2020 // I1 = NOT(J1 EOR S);
2021 // I2 = NOT(J2 EOR S);
2022 // and build the imm32 with one trailing zero as documented:
2023 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2024 unsigned S = fieldFromInstruction(Insn, 26, 1);
2025 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2026 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2027 unsigned I1 = !(J1 ^ S);
2028 unsigned I2 = !(J2 ^ S);
2029 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2030 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2031 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2032 int imm32 = SignExtend32<24>(tmp << 1);
2033 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2034 true, 4, Inst, Decoder))
Kevin Enderby445ba852012-10-29 23:27:20 +0000[diff] [blame]2035 Inst.addOperand(MCOperand::CreateImm(imm32));
2036
2037 return Status;
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]2038}
2039
2040static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2041DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2042 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2043 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2044
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2045 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2046 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2047
2048 if (pred == 0xF) {
2049 Inst.setOpcode(ARM::BLXi);
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2050 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2051 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2052 true, 4, Inst, Decoder))
Benjamin Kramer793b8112011-08-09 22:02:50 +0000[diff] [blame]2053 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2054 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2055 }
2056
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]2057 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2058 true, 4, Inst, Decoder))
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]2059 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2060 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2061 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2062
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2063 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2064}
2065
2066
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2067static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2068 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2069 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2070
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2071 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2072 unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2073
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2075 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2076 if (!align)
2077 Inst.addOperand(MCOperand::CreateImm(0));
2078 else
2079 Inst.addOperand(MCOperand::CreateImm(4 << align));
2080
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2081 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2082}
2083
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2084static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2085 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2086 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2087
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2088 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2089 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2090 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2091 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2092 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2093 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2094
2095 // First output register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2096 switch (Inst.getOpcode()) {
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2097 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2098 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2099 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2100 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2101 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2102 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2103 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2104 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2105 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2106 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2107 return MCDisassembler::Fail;
2108 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2109 case ARM::VLD2b16:
2110 case ARM::VLD2b32:
2111 case ARM::VLD2b8:
2112 case ARM::VLD2b16wb_fixed:
2113 case ARM::VLD2b16wb_register:
2114 case ARM::VLD2b32wb_fixed:
2115 case ARM::VLD2b32wb_register:
2116 case ARM::VLD2b8wb_fixed:
2117 case ARM::VLD2b8wb_register:
2118 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2119 return MCDisassembler::Fail;
2120 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2121 default:
2122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2123 return MCDisassembler::Fail;
2124 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2125
2126 // Second output register
2127 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2128 case ARM::VLD3d8:
2129 case ARM::VLD3d16:
2130 case ARM::VLD3d32:
2131 case ARM::VLD3d8_UPD:
2132 case ARM::VLD3d16_UPD:
2133 case ARM::VLD3d32_UPD:
2134 case ARM::VLD4d8:
2135 case ARM::VLD4d16:
2136 case ARM::VLD4d32:
2137 case ARM::VLD4d8_UPD:
2138 case ARM::VLD4d16_UPD:
2139 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2140 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2141 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2142 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2143 case ARM::VLD3q8:
2144 case ARM::VLD3q16:
2145 case ARM::VLD3q32:
2146 case ARM::VLD3q8_UPD:
2147 case ARM::VLD3q16_UPD:
2148 case ARM::VLD3q32_UPD:
2149 case ARM::VLD4q8:
2150 case ARM::VLD4q16:
2151 case ARM::VLD4q32:
2152 case ARM::VLD4q8_UPD:
2153 case ARM::VLD4q16_UPD:
2154 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2155 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2156 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2157 default:
2158 break;
2159 }
2160
2161 // Third output register
2162 switch(Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2163 case ARM::VLD3d8:
2164 case ARM::VLD3d16:
2165 case ARM::VLD3d32:
2166 case ARM::VLD3d8_UPD:
2167 case ARM::VLD3d16_UPD:
2168 case ARM::VLD3d32_UPD:
2169 case ARM::VLD4d8:
2170 case ARM::VLD4d16:
2171 case ARM::VLD4d32:
2172 case ARM::VLD4d8_UPD:
2173 case ARM::VLD4d16_UPD:
2174 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2175 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2176 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2177 break;
2178 case ARM::VLD3q8:
2179 case ARM::VLD3q16:
2180 case ARM::VLD3q32:
2181 case ARM::VLD3q8_UPD:
2182 case ARM::VLD3q16_UPD:
2183 case ARM::VLD3q32_UPD:
2184 case ARM::VLD4q8:
2185 case ARM::VLD4q16:
2186 case ARM::VLD4q32:
2187 case ARM::VLD4q8_UPD:
2188 case ARM::VLD4q16_UPD:
2189 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2190 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2191 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2192 break;
2193 default:
2194 break;
2195 }
2196
2197 // Fourth output register
2198 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2199 case ARM::VLD4d8:
2200 case ARM::VLD4d16:
2201 case ARM::VLD4d32:
2202 case ARM::VLD4d8_UPD:
2203 case ARM::VLD4d16_UPD:
2204 case ARM::VLD4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2205 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2206 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2207 break;
2208 case ARM::VLD4q8:
2209 case ARM::VLD4q16:
2210 case ARM::VLD4q32:
2211 case ARM::VLD4q8_UPD:
2212 case ARM::VLD4q16_UPD:
2213 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2215 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2216 break;
2217 default:
2218 break;
2219 }
2220
2221 // Writeback operand
2222 switch (Inst.getOpcode()) {
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2223 case ARM::VLD1d8wb_fixed:
2224 case ARM::VLD1d16wb_fixed:
2225 case ARM::VLD1d32wb_fixed:
2226 case ARM::VLD1d64wb_fixed:
2227 case ARM::VLD1d8wb_register:
2228 case ARM::VLD1d16wb_register:
2229 case ARM::VLD1d32wb_register:
2230 case ARM::VLD1d64wb_register:
2231 case ARM::VLD1q8wb_fixed:
2232 case ARM::VLD1q16wb_fixed:
2233 case ARM::VLD1q32wb_fixed:
2234 case ARM::VLD1q64wb_fixed:
2235 case ARM::VLD1q8wb_register:
2236 case ARM::VLD1q16wb_register:
2237 case ARM::VLD1q32wb_register:
2238 case ARM::VLD1q64wb_register:
Jim Grosbach59216752011-10-24 23:26:05 +0000[diff] [blame]2239 case ARM::VLD1d8Twb_fixed:
2240 case ARM::VLD1d8Twb_register:
2241 case ARM::VLD1d16Twb_fixed:
2242 case ARM::VLD1d16Twb_register:
2243 case ARM::VLD1d32Twb_fixed:
2244 case ARM::VLD1d32Twb_register:
2245 case ARM::VLD1d64Twb_fixed:
2246 case ARM::VLD1d64Twb_register:
Jim Grosbach399cdca2011-10-25 00:14:01 +0000[diff] [blame]2247 case ARM::VLD1d8Qwb_fixed:
2248 case ARM::VLD1d8Qwb_register:
2249 case ARM::VLD1d16Qwb_fixed:
2250 case ARM::VLD1d16Qwb_register:
2251 case ARM::VLD1d32Qwb_fixed:
2252 case ARM::VLD1d32Qwb_register:
2253 case ARM::VLD1d64Qwb_fixed:
2254 case ARM::VLD1d64Qwb_register:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000[diff] [blame]2255 case ARM::VLD2d8wb_fixed:
2256 case ARM::VLD2d16wb_fixed:
2257 case ARM::VLD2d32wb_fixed:
2258 case ARM::VLD2q8wb_fixed:
2259 case ARM::VLD2q16wb_fixed:
2260 case ARM::VLD2q32wb_fixed:
2261 case ARM::VLD2d8wb_register:
2262 case ARM::VLD2d16wb_register:
2263 case ARM::VLD2d32wb_register:
2264 case ARM::VLD2q8wb_register:
2265 case ARM::VLD2q16wb_register:
2266 case ARM::VLD2q32wb_register:
2267 case ARM::VLD2b8wb_fixed:
2268 case ARM::VLD2b16wb_fixed:
2269 case ARM::VLD2b32wb_fixed:
2270 case ARM::VLD2b8wb_register:
2271 case ARM::VLD2b16wb_register:
2272 case ARM::VLD2b32wb_register:
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2273 Inst.addOperand(MCOperand::CreateImm(0));
2274 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2275 case ARM::VLD3d8_UPD:
2276 case ARM::VLD3d16_UPD:
2277 case ARM::VLD3d32_UPD:
2278 case ARM::VLD3q8_UPD:
2279 case ARM::VLD3q16_UPD:
2280 case ARM::VLD3q32_UPD:
2281 case ARM::VLD4d8_UPD:
2282 case ARM::VLD4d16_UPD:
2283 case ARM::VLD4d32_UPD:
2284 case ARM::VLD4q8_UPD:
2285 case ARM::VLD4q16_UPD:
2286 case ARM::VLD4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2287 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2288 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2289 break;
2290 default:
2291 break;
2292 }
2293
2294 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2295 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2296 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2297
2298 // AddrMode6 Offset (register)
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2299 switch (Inst.getOpcode()) {
2300 default:
2301 // The below have been updated to have explicit am6offset split
2302 // between fixed and register offset. For those instructions not
2303 // yet updated, we need to add an additional reg0 operand for the
2304 // fixed variant.
2305 //
2306 // The fixed offset encodes as Rm == 0xd, so we check for that.
2307 if (Rm == 0xd) {
2308 Inst.addOperand(MCOperand::CreateReg(0));
2309 break;
2310 }
2311 // Fall through to handle the register offset variant.
2312 case ARM::VLD1d8wb_fixed:
2313 case ARM::VLD1d16wb_fixed:
2314 case ARM::VLD1d32wb_fixed:
2315 case ARM::VLD1d64wb_fixed:
Owen Anderson04b12a42011-10-27 22:53:10 +0000[diff] [blame]2316 case ARM::VLD1d8Twb_fixed:
2317 case ARM::VLD1d16Twb_fixed:
2318 case ARM::VLD1d32Twb_fixed:
2319 case ARM::VLD1d64Twb_fixed:
Owen Andersonfb6ab2b2011-10-31 17:17:32 +0000[diff] [blame]2320 case ARM::VLD1d8Qwb_fixed:
2321 case ARM::VLD1d16Qwb_fixed:
2322 case ARM::VLD1d32Qwb_fixed:
2323 case ARM::VLD1d64Qwb_fixed:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2324 case ARM::VLD1d8wb_register:
2325 case ARM::VLD1d16wb_register:
2326 case ARM::VLD1d32wb_register:
2327 case ARM::VLD1d64wb_register:
2328 case ARM::VLD1q8wb_fixed:
2329 case ARM::VLD1q16wb_fixed:
2330 case ARM::VLD1q32wb_fixed:
2331 case ARM::VLD1q64wb_fixed:
2332 case ARM::VLD1q8wb_register:
2333 case ARM::VLD1q16wb_register:
2334 case ARM::VLD1q32wb_register:
2335 case ARM::VLD1q64wb_register:
2336 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2337 // variant encodes Rm == 0xf. Anything else is a register offset post-
2338 // increment and we need to add the register operand to the instruction.
2339 if (Rm != 0xD && Rm != 0xF &&
2340 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2341 return MCDisassembler::Fail;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000[diff] [blame]2342 break;
Kevin Enderbya69da352012-04-11 00:25:40 +0000[diff] [blame]2343 case ARM::VLD2d8wb_fixed:
2344 case ARM::VLD2d16wb_fixed:
2345 case ARM::VLD2d32wb_fixed:
2346 case ARM::VLD2b8wb_fixed:
2347 case ARM::VLD2b16wb_fixed:
2348 case ARM::VLD2b32wb_fixed:
2349 case ARM::VLD2q8wb_fixed:
2350 case ARM::VLD2q16wb_fixed:
2351 case ARM::VLD2q32wb_fixed:
2352 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2353 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2354
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2355 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2356}
2357
Mihai Popa30a7a7c2013-05-20 14:57:05 +0000[diff] [blame]2358static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
2359 uint64_t Addr, const void* Decoder) {
2360 unsigned type = fieldFromInstruction(Insn, 8, 4);
2361 unsigned align = fieldFromInstruction(Insn, 4, 2);
2362 if(type == 7 && (align & 2)) return MCDisassembler::Fail;
2363 if(type == 10 && align == 3) return MCDisassembler::Fail;
2364 if(type == 6 && (align & 2)) return MCDisassembler::Fail;
2365
2366 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2367}
2368
2369static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
2370 uint64_t Addr, const void* Decoder) {
2371 unsigned size = fieldFromInstruction(Insn, 6, 2);
2372 if(size == 3) return MCDisassembler::Fail;
2373
2374 unsigned type = fieldFromInstruction(Insn, 8, 4);
2375 unsigned align = fieldFromInstruction(Insn, 4, 2);
2376 if(type == 8 && align == 3) return MCDisassembler::Fail;
2377 if(type == 9 && align == 3) return MCDisassembler::Fail;
2378
2379 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2380}
2381
2382static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
2383 uint64_t Addr, const void* Decoder) {
2384 unsigned size = fieldFromInstruction(Insn, 6, 2);
2385 if(size == 3) return MCDisassembler::Fail;
2386
2387 unsigned align = fieldFromInstruction(Insn, 4, 2);
2388 if(align & 2) return MCDisassembler::Fail;
2389
2390 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2391}
2392
2393static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
2394 uint64_t Addr, const void* Decoder) {
2395 unsigned size = fieldFromInstruction(Insn, 6, 2);
2396 if(size == 3) return MCDisassembler::Fail;
2397
2398 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2399}
2400
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2401static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2402 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2403 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2404
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2405 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2406 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2407 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2408 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2409 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2410 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2411
2412 // Writeback Operand
2413 switch (Inst.getOpcode()) {
Jim Grosbach4334e032011-10-31 21:50:31 +0000[diff] [blame]2414 case ARM::VST1d8wb_fixed:
2415 case ARM::VST1d16wb_fixed:
2416 case ARM::VST1d32wb_fixed:
2417 case ARM::VST1d64wb_fixed:
2418 case ARM::VST1d8wb_register:
2419 case ARM::VST1d16wb_register:
2420 case ARM::VST1d32wb_register:
2421 case ARM::VST1d64wb_register:
2422 case ARM::VST1q8wb_fixed:
2423 case ARM::VST1q16wb_fixed:
2424 case ARM::VST1q32wb_fixed:
2425 case ARM::VST1q64wb_fixed:
2426 case ARM::VST1q8wb_register:
2427 case ARM::VST1q16wb_register:
2428 case ARM::VST1q32wb_register:
2429 case ARM::VST1q64wb_register:
Jim Grosbachd5ca2012011-11-29 22:38:04 +0000[diff] [blame]2430 case ARM::VST1d8Twb_fixed:
2431 case ARM::VST1d16Twb_fixed:
2432 case ARM::VST1d32Twb_fixed:
2433 case ARM::VST1d64Twb_fixed:
2434 case ARM::VST1d8Twb_register:
2435 case ARM::VST1d16Twb_register:
2436 case ARM::VST1d32Twb_register:
2437 case ARM::VST1d64Twb_register:
Jim Grosbach4c7edb32011-11-29 22:58:48 +0000[diff] [blame]2438 case ARM::VST1d8Qwb_fixed:
2439 case ARM::VST1d16Qwb_fixed:
2440 case ARM::VST1d32Qwb_fixed:
2441 case ARM::VST1d64Qwb_fixed:
2442 case ARM::VST1d8Qwb_register:
2443 case ARM::VST1d16Qwb_register:
2444 case ARM::VST1d32Qwb_register:
2445 case ARM::VST1d64Qwb_register:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +0000[diff] [blame]2446 case ARM::VST2d8wb_fixed:
2447 case ARM::VST2d16wb_fixed:
2448 case ARM::VST2d32wb_fixed:
2449 case ARM::VST2d8wb_register:
2450 case ARM::VST2d16wb_register:
2451 case ARM::VST2d32wb_register:
2452 case ARM::VST2q8wb_fixed:
2453 case ARM::VST2q16wb_fixed:
2454 case ARM::VST2q32wb_fixed:
2455 case ARM::VST2q8wb_register:
2456 case ARM::VST2q16wb_register:
2457 case ARM::VST2q32wb_register:
2458 case ARM::VST2b8wb_fixed:
2459 case ARM::VST2b16wb_fixed:
2460 case ARM::VST2b32wb_fixed:
2461 case ARM::VST2b8wb_register:
2462 case ARM::VST2b16wb_register:
2463 case ARM::VST2b32wb_register:
Kevin Enderbyb318cc12012-04-11 22:40:17 +0000[diff] [blame]2464 if (Rm == 0xF)
2465 return MCDisassembler::Fail;
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2466 Inst.addOperand(MCOperand::CreateImm(0));
2467 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2468 case ARM::VST3d8_UPD:
2469 case ARM::VST3d16_UPD:
2470 case ARM::VST3d32_UPD:
2471 case ARM::VST3q8_UPD:
2472 case ARM::VST3q16_UPD:
2473 case ARM::VST3q32_UPD:
2474 case ARM::VST4d8_UPD:
2475 case ARM::VST4d16_UPD:
2476 case ARM::VST4d32_UPD:
2477 case ARM::VST4q8_UPD:
2478 case ARM::VST4q16_UPD:
2479 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2480 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2481 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2482 break;
2483 default:
2484 break;
2485 }
2486
2487 // AddrMode6 Base (register+alignment)
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2488 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2489 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2490
2491 // AddrMode6 Offset (register)
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2492 switch (Inst.getOpcode()) {
2493 default:
2494 if (Rm == 0xD)
2495 Inst.addOperand(MCOperand::CreateReg(0));
2496 else if (Rm != 0xF) {
2497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2498 return MCDisassembler::Fail;
2499 }
2500 break;
2501 case ARM::VST1d8wb_fixed:
2502 case ARM::VST1d16wb_fixed:
2503 case ARM::VST1d32wb_fixed:
2504 case ARM::VST1d64wb_fixed:
2505 case ARM::VST1q8wb_fixed:
2506 case ARM::VST1q16wb_fixed:
2507 case ARM::VST1q32wb_fixed:
2508 case ARM::VST1q64wb_fixed:
Kevin Enderbyf0586f02012-03-21 20:54:32 +0000[diff] [blame]2509 case ARM::VST1d8Twb_fixed:
2510 case ARM::VST1d16Twb_fixed:
2511 case ARM::VST1d32Twb_fixed:
2512 case ARM::VST1d64Twb_fixed:
2513 case ARM::VST1d8Qwb_fixed:
2514 case ARM::VST1d16Qwb_fixed:
2515 case ARM::VST1d32Qwb_fixed:
2516 case ARM::VST1d64Qwb_fixed:
2517 case ARM::VST2d8wb_fixed:
2518 case ARM::VST2d16wb_fixed:
2519 case ARM::VST2d32wb_fixed:
2520 case ARM::VST2q8wb_fixed:
2521 case ARM::VST2q16wb_fixed:
2522 case ARM::VST2q32wb_fixed:
2523 case ARM::VST2b8wb_fixed:
2524 case ARM::VST2b16wb_fixed:
2525 case ARM::VST2b32wb_fixed:
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2526 break;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2527 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2528
Owen Anderson60cb6432011-11-01 22:18:13 +0000[diff] [blame]2529
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2530 // First input register
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2531 switch (Inst.getOpcode()) {
2532 case ARM::VST1q16:
2533 case ARM::VST1q32:
2534 case ARM::VST1q64:
2535 case ARM::VST1q8:
2536 case ARM::VST1q16wb_fixed:
2537 case ARM::VST1q16wb_register:
2538 case ARM::VST1q32wb_fixed:
2539 case ARM::VST1q32wb_register:
2540 case ARM::VST1q64wb_fixed:
2541 case ARM::VST1q64wb_register:
2542 case ARM::VST1q8wb_fixed:
2543 case ARM::VST1q8wb_register:
2544 case ARM::VST2d16:
2545 case ARM::VST2d32:
2546 case ARM::VST2d8:
2547 case ARM::VST2d16wb_fixed:
2548 case ARM::VST2d16wb_register:
2549 case ARM::VST2d32wb_fixed:
2550 case ARM::VST2d32wb_register:
2551 case ARM::VST2d8wb_fixed:
2552 case ARM::VST2d8wb_register:
2553 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2554 return MCDisassembler::Fail;
2555 break;
Jim Grosbachc3384c92012-03-05 21:43:40 +0000[diff] [blame]2556 case ARM::VST2b16:
2557 case ARM::VST2b32:
2558 case ARM::VST2b8:
2559 case ARM::VST2b16wb_fixed:
2560 case ARM::VST2b16wb_register:
2561 case ARM::VST2b32wb_fixed:
2562 case ARM::VST2b32wb_register:
2563 case ARM::VST2b8wb_fixed:
2564 case ARM::VST2b8wb_register:
2565 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2566 return MCDisassembler::Fail;
2567 break;
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2568 default:
2569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2570 return MCDisassembler::Fail;
2571 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2572
2573 // Second input register
2574 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2575 case ARM::VST3d8:
2576 case ARM::VST3d16:
2577 case ARM::VST3d32:
2578 case ARM::VST3d8_UPD:
2579 case ARM::VST3d16_UPD:
2580 case ARM::VST3d32_UPD:
2581 case ARM::VST4d8:
2582 case ARM::VST4d16:
2583 case ARM::VST4d32:
2584 case ARM::VST4d8_UPD:
2585 case ARM::VST4d16_UPD:
2586 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2587 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2588 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2589 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2590 case ARM::VST3q8:
2591 case ARM::VST3q16:
2592 case ARM::VST3q32:
2593 case ARM::VST3q8_UPD:
2594 case ARM::VST3q16_UPD:
2595 case ARM::VST3q32_UPD:
2596 case ARM::VST4q8:
2597 case ARM::VST4q16:
2598 case ARM::VST4q32:
2599 case ARM::VST4q8_UPD:
2600 case ARM::VST4q16_UPD:
2601 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2602 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2603 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2604 break;
2605 default:
2606 break;
2607 }
2608
2609 // Third input register
2610 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2611 case ARM::VST3d8:
2612 case ARM::VST3d16:
2613 case ARM::VST3d32:
2614 case ARM::VST3d8_UPD:
2615 case ARM::VST3d16_UPD:
2616 case ARM::VST3d32_UPD:
2617 case ARM::VST4d8:
2618 case ARM::VST4d16:
2619 case ARM::VST4d32:
2620 case ARM::VST4d8_UPD:
2621 case ARM::VST4d16_UPD:
2622 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2623 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2624 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2625 break;
2626 case ARM::VST3q8:
2627 case ARM::VST3q16:
2628 case ARM::VST3q32:
2629 case ARM::VST3q8_UPD:
2630 case ARM::VST3q16_UPD:
2631 case ARM::VST3q32_UPD:
2632 case ARM::VST4q8:
2633 case ARM::VST4q16:
2634 case ARM::VST4q32:
2635 case ARM::VST4q8_UPD:
2636 case ARM::VST4q16_UPD:
2637 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2639 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2640 break;
2641 default:
2642 break;
2643 }
2644
2645 // Fourth input register
2646 switch (Inst.getOpcode()) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2647 case ARM::VST4d8:
2648 case ARM::VST4d16:
2649 case ARM::VST4d32:
2650 case ARM::VST4d8_UPD:
2651 case ARM::VST4d16_UPD:
2652 case ARM::VST4d32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2653 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2654 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2655 break;
2656 case ARM::VST4q8:
2657 case ARM::VST4q16:
2658 case ARM::VST4q32:
2659 case ARM::VST4q8_UPD:
2660 case ARM::VST4q16_UPD:
2661 case ARM::VST4q32_UPD:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2662 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2663 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2664 break;
2665 default:
2666 break;
2667 }
2668
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2669 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2670}
2671
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2672static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2673 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2674 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2675
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2676 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2677 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2678 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2679 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2680 unsigned align = fieldFromInstruction(Insn, 4, 1);
2681 unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2682
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2683 if (size == 0 && align == 1)
2684 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2685 align *= (1 << size);
2686
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2687 switch (Inst.getOpcode()) {
2688 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2689 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2690 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2691 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2692 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2693 return MCDisassembler::Fail;
2694 break;
2695 default:
2696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2697 return MCDisassembler::Fail;
2698 break;
2699 }
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2700 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2702 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2703 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2704
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2706 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2707 Inst.addOperand(MCOperand::CreateImm(align));
2708
Jim Grosbach096334e2011-11-30 19:35:44 +0000[diff] [blame]2709 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2710 // variant encodes Rm == 0xf. Anything else is a register offset post-
2711 // increment and we need to add the register operand to the instruction.
2712 if (Rm != 0xD && Rm != 0xF &&
2713 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2714 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2715
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2716 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2717}
2718
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2719static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2720 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2721 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2722
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2723 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2725 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2726 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2727 unsigned align = fieldFromInstruction(Insn, 4, 1);
2728 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2729 align *= 2*size;
2730
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2731 switch (Inst.getOpcode()) {
2732 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2733 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2734 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2735 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2736 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2737 return MCDisassembler::Fail;
2738 break;
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000[diff] [blame]2739 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2740 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2741 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2742 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2743 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2744 return MCDisassembler::Fail;
2745 break;
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000[diff] [blame]2746 default:
2747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2748 return MCDisassembler::Fail;
2749 break;
2750 }
Kevin Enderby158c8a42012-03-06 18:33:12 +0000[diff] [blame]2751
2752 if (Rm != 0xF)
2753 Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2754
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2756 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2757 Inst.addOperand(MCOperand::CreateImm(align));
2758
Kevin Enderbyc5a2a332012-04-17 00:49:27 +0000[diff] [blame]2759 if (Rm != 0xD && Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2761 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2762 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2763
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2764 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2765}
2766
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2767static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2768 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2769 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2770
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2771 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2772 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2773 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2774 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2775 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2776
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2778 return MCDisassembler::Fail;
2779 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2780 return MCDisassembler::Fail;
2781 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2782 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2783 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2785 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2786 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2787
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2789 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2790 Inst.addOperand(MCOperand::CreateImm(0));
2791
2792 if (Rm == 0xD)
2793 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2794 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2796 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2797 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2798
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2799 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2800}
2801
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2802static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2803 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2804 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2805
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2806 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2807 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2808 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2809 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2810 unsigned size = fieldFromInstruction(Insn, 6, 2);
2811 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2812 unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2813
2814 if (size == 0x3) {
Tim Northover24b9f252012-09-06 15:27:12 +0000[diff] [blame]2815 if (align == 0)
2816 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2817 size = 4;
2818 align = 16;
2819 } else {
2820 if (size == 2) {
2821 size = 1 << size;
2822 align *= 8;
2823 } else {
2824 size = 1 << size;
2825 align *= 4*size;
2826 }
2827 }
2828
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2830 return MCDisassembler::Fail;
2831 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2832 return MCDisassembler::Fail;
2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2836 return MCDisassembler::Fail;
Owen Andersonf1c8e3e2011-08-22 18:22:06 +0000[diff] [blame]2837 if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2839 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2840 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2841
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2843 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2844 Inst.addOperand(MCOperand::CreateImm(align));
2845
2846 if (Rm == 0xD)
2847 Inst.addOperand(MCOperand::CreateReg(0));
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2848 else if (Rm != 0xF) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2850 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2851 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2852
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2853 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2854}
2855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2856static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2857DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]2858 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2859 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2860
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2861 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2862 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2863 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2864 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2865 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2866 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2867 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2868 unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2869
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2870 if (Q) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2871 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2872 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2873 } else {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2875 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2876 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2877
2878 Inst.addOperand(MCOperand::CreateImm(imm));
2879
2880 switch (Inst.getOpcode()) {
2881 case ARM::VORRiv4i16:
2882 case ARM::VORRiv2i32:
2883 case ARM::VBICiv4i16:
2884 case ARM::VBICiv2i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2886 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2887 break;
2888 case ARM::VORRiv8i16:
2889 case ARM::VORRiv4i32:
2890 case ARM::VBICiv8i16:
2891 case ARM::VBICiv4i32:
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2892 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2893 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2894 break;
2895 default:
2896 break;
2897 }
2898
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2899 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2900}
2901
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2902static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2903 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2904 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2905
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2906 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2907 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2908 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2909 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2910 unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2911
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2912 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2913 return MCDisassembler::Fail;
2914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2915 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2916 Inst.addOperand(MCOperand::CreateImm(8 << size));
2917
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2918 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2919}
2920
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2921static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2922 uint64_t Address, const void *Decoder) {
2923 Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2924 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2925}
2926
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2927static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2928 uint64_t Address, const void *Decoder) {
2929 Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2930 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2931}
2932
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2933static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2934 uint64_t Address, const void *Decoder) {
2935 Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2936 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2937}
2938
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2939static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2940 uint64_t Address, const void *Decoder) {
2941 Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2942 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2943}
2944
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2945static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2946 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2947 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2948
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2949 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2950 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2951 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2952 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2953 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2954 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2955 unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2956
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2958 return MCDisassembler::Fail;
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2959 if (op) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2961 return MCDisassembler::Fail; // Writeback
Owen Andersonae0bc5d2011-08-11 18:24:51 +0000[diff] [blame]2962 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2963
Jim Grosbach28f08c92012-03-05 19:33:30 +0000[diff] [blame]2964 switch (Inst.getOpcode()) {
2965 case ARM::VTBL2:
2966 case ARM::VTBX2:
2967 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2968 return MCDisassembler::Fail;
2969 break;
2970 default:
2971 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2972 return MCDisassembler::Fail;
2973 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2974
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2976 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2977
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2978 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2979}
2980
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]2981static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2982 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2983 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]2984
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]2985 unsigned dst = fieldFromInstruction(Insn, 8, 3);
2986 unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]2988 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2989 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]2990
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2991 switch(Inst.getOpcode()) {
Owen Anderson1af7f722011-08-26 19:39:26 +0000[diff] [blame]2992 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]2993 return MCDisassembler::Fail;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2994 case ARM::tADR:
Owen Anderson9f7e8312011-08-26 21:47:57 +0000[diff] [blame]2995 break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2996 case ARM::tADDrSPi:
2997 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2998 break;
Owen Anderson96425c82011-08-26 18:09:22 +0000[diff] [blame]2999 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3000
3001 Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3002 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3003}
3004
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3005static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3006 uint64_t Address, const void *Decoder) {
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3007 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3008 true, 2, Inst, Decoder))
3009 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3010 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3011}
3012
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3013static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3014 uint64_t Address, const void *Decoder) {
Kevin Enderby3610a152012-05-04 22:09:52 +0000[diff] [blame]3015 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3016 true, 4, Inst, Decoder))
3017 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3018 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3019}
3020
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3021static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3022 uint64_t Address, const void *Decoder) {
Gordon Keiserce888352013-03-28 19:22:28 +0000[diff] [blame]3023 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3024 true, 2, Inst, Decoder))
Gordon Keiserce888352013-03-28 19:22:28 +0000[diff] [blame]3025 Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3026 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3027}
3028
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3029static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3030 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3031 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3032
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3033 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3034 unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3035
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3036 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3037 return MCDisassembler::Fail;
3038 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3039 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3040
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3041 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3042}
3043
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3044static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3045 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3046 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3047
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3048 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3049 unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3050
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3051 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3052 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3053 Inst.addOperand(MCOperand::CreateImm(imm));
3054
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3055 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3056}
3057
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3058static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3059 uint64_t Address, const void *Decoder) {
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3060 unsigned imm = Val << 2;
3061
3062 Inst.addOperand(MCOperand::CreateImm(imm));
3063 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3064
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3065 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3066}
3067
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3068static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3069 uint64_t Address, const void *Decoder) {
3070 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersonb113ec52011-08-22 17:56:58 +0000[diff] [blame]3071 Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3072
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3073 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3074}
3075
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3076static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3077 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3078 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3079
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3080 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3081 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3082 unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3083
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3085 return MCDisassembler::Fail;
3086 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3087 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3088 Inst.addOperand(MCOperand::CreateImm(imm));
3089
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3090 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3091}
3092
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3093static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3094 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3095 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3096
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3097 switch (Inst.getOpcode()) {
3098 case ARM::t2PLDs:
3099 case ARM::t2PLDWs:
3100 case ARM::t2PLIs:
3101 break;
3102 default: {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3103 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Owen Anderson31d485e2011-09-23 21:07:25 +0000[diff] [blame]3104 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3105 return MCDisassembler::Fail;
Owen Anderson82265a22011-08-23 17:51:38 +0000[diff] [blame]3106 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3107 }
3108
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3109 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3110 if (Rn == 0xF) {
3111 switch (Inst.getOpcode()) {
3112 case ARM::t2LDRBs:
3113 Inst.setOpcode(ARM::t2LDRBpci);
3114 break;
3115 case ARM::t2LDRHs:
3116 Inst.setOpcode(ARM::t2LDRHpci);
3117 break;
3118 case ARM::t2LDRSHs:
3119 Inst.setOpcode(ARM::t2LDRSHpci);
3120 break;
3121 case ARM::t2LDRSBs:
3122 Inst.setOpcode(ARM::t2LDRSBpci);
3123 break;
3124 case ARM::t2PLDs:
3125 Inst.setOpcode(ARM::t2PLDi12);
3126 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3127 break;
3128 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3129 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3130 }
3131
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3132 int imm = fieldFromInstruction(Insn, 0, 12);
3133 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3134 Inst.addOperand(MCOperand::CreateImm(imm));
3135
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3136 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3137 }
3138
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3139 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3140 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3141 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3142 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3143 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3144
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3145 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3146}
3147
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3148static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3149 uint64_t Address, const void *Decoder) {
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3150 if (Val == 0)
3151 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3152 else {
3153 int imm = Val & 0xFF;
3154
3155 if (!(Val & 0x100)) imm *= -1;
Richard Smith1144af32012-08-24 23:29:28 +0000[diff] [blame]3156 Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liufd652df2012-08-02 08:29:50 +0000[diff] [blame]3157 }
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3158
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3159 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3160}
3161
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3162static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3163 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3164 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3165
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3166 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3167 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3168
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3170 return MCDisassembler::Fail;
3171 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3172 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3173
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3174 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3175}
3176
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3177static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3178 uint64_t Address, const void *Decoder) {
3179 DecodeStatus S = MCDisassembler::Success;
3180
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3181 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3182 unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbachb6aed502011-09-09 18:37:27 +0000[diff] [blame]3183
3184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3185 return MCDisassembler::Fail;
3186
3187 Inst.addOperand(MCOperand::CreateImm(imm));
3188
3189 return S;
3190}
3191
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3192static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3193 uint64_t Address, const void *Decoder) {
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3194 int imm = Val & 0xFF;
Owen Anderson705b48f2011-09-16 21:08:33 +0000[diff] [blame]3195 if (Val == 0)
3196 imm = INT32_MIN;
3197 else if (!(Val & 0x100))
3198 imm *= -1;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3199 Inst.addOperand(MCOperand::CreateImm(imm));
3200
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3201 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3202}
3203
3204
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3205static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3206 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3207 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3208
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3209 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3210 unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3211
3212 // Some instructions always use an additive offset.
3213 switch (Inst.getOpcode()) {
3214 case ARM::t2LDRT:
3215 case ARM::t2LDRBT:
3216 case ARM::t2LDRHT:
3217 case ARM::t2LDRSBT:
3218 case ARM::t2LDRSHT:
Owen Andersonecd1c552011-09-19 18:07:10 +0000[diff] [blame]3219 case ARM::t2STRT:
3220 case ARM::t2STRBT:
3221 case ARM::t2STRHT:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3222 imm |= 0x100;
3223 break;
3224 default:
3225 break;
3226 }
3227
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3229 return MCDisassembler::Fail;
3230 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3231 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3232
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3233 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3234}
3235
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3236static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3237 uint64_t Address, const void *Decoder) {
3238 DecodeStatus S = MCDisassembler::Success;
3239
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3240 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3241 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3242 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3243 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3244 addr |= Rn << 9;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3245 unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3246
3247 if (!load) {
3248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3249 return MCDisassembler::Fail;
3250 }
3251
Joe Abbeyb78821d2013-03-26 13:58:53 +0000[diff] [blame]3252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Andersona3157b42011-09-12 18:56:30 +0000[diff] [blame]3253 return MCDisassembler::Fail;
3254
3255 if (load) {
3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3257 return MCDisassembler::Fail;
3258 }
3259
3260 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3261 return MCDisassembler::Fail;
3262
3263 return S;
3264}
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3265
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3266static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3267 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3268 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3269
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3270 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3271 unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3272
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3274 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3275 Inst.addOperand(MCOperand::CreateImm(imm));
3276
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3277 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3278}
3279
3280
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3281static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3282 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3283 unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3284
3285 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3286 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3287 Inst.addOperand(MCOperand::CreateImm(imm));
3288
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3289 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3290}
3291
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3292static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3293 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3294 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3295
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3296 if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3297 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3298 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3299
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3301 return MCDisassembler::Fail;
Jim Grosbachbb32f1d2012-04-27 23:51:33 +0000[diff] [blame]3302 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3304 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3305 } else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3306 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3307
3308 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3309 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3311 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3312 }
3313
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3314 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3315}
3316
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3317static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3318 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3319 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3320 unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3321
3322 Inst.addOperand(MCOperand::CreateImm(imod));
3323 Inst.addOperand(MCOperand::CreateImm(flags));
3324
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3325 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3326}
3327
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3328static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3329 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3330 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3331 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3332 unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3333
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]3334 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3335 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3336 Inst.addOperand(MCOperand::CreateImm(add));
3337
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3338 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3339}
3340
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3341static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3342 uint64_t Address, const void *Decoder) {
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3343 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3344 // Note only one trailing zero not two. Also the J1 and J2 values are from
3345 // the encoded instruction. So here change to I1 and I2 values via:
3346 // I1 = NOT(J1 EOR S);
3347 // I2 = NOT(J2 EOR S);
3348 // and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3349 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3350 unsigned S = (Val >> 23) & 1;
3351 unsigned J1 = (Val >> 22) & 1;
3352 unsigned J2 = (Val >> 21) & 1;
3353 unsigned I1 = !(J1 ^ S);
3354 unsigned I2 = !(J2 ^ S);
3355 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3356 int imm32 = SignExtend32<25>(tmp << 1);
3357
Jim Grosbach01817c32011-10-20 17:28:20 +0000[diff] [blame]3358 if (!tryAddingSymbolicOperand(Address,
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3359 (Address & ~2u) + imm32 + 4,
Kevin Enderby9e5887b2011-10-04 22:44:48 +0000[diff] [blame]3360 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3361 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3362 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3363}
3364
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3365static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3366 uint64_t Address, const void *Decoder) {
3367 if (Val == 0xA || Val == 0xB)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3368 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3369
3370 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3371 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3372}
3373
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3374static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3375DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3376 uint64_t Address, const void *Decoder) {
3377 DecodeStatus S = MCDisassembler::Success;
3378
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3379 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3380 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach7f739be2011-09-19 22:21:13 +0000[diff] [blame]3381
3382 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3384 return MCDisassembler::Fail;
3385 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3386 return MCDisassembler::Fail;
3387 return S;
3388}
3389
3390static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3391DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3392 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3393 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3394
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3395 unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3396 if (pred == 0xE || pred == 0xF) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3397 unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3398 switch (opc) {
3399 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3400 return MCDisassembler::Fail;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3401 case 0xf3bf8f4:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3402 Inst.setOpcode(ARM::t2DSB);
3403 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3404 case 0xf3bf8f5:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3405 Inst.setOpcode(ARM::t2DMB);
3406 break;
Owen Andersonb45b11b2011-08-31 22:00:41 +0000[diff] [blame]3407 case 0xf3bf8f6:
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3408 Inst.setOpcode(ARM::t2ISB);
Owen Anderson6de3c6f2011-09-07 17:55:19 +0000[diff] [blame]3409 break;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3410 }
3411
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3412 unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3413 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3414 }
3415
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3416 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3417 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3418 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3419 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3420 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3421
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3422 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3423 return MCDisassembler::Fail;
3424 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3425 return MCDisassembler::Fail;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3426
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3427 return S;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3428}
3429
3430// Decode a shifted immediate operand. These basically consist
3431// of an 8-bit value, and a 4-bit directive that specifies either
3432// a splat operation or a rotation.
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3433static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3434 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3435 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3436 if (ctrl == 0) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3437 unsigned byte = fieldFromInstruction(Val, 8, 2);
3438 unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3439 switch (byte) {
3440 case 0:
3441 Inst.addOperand(MCOperand::CreateImm(imm));
3442 break;
3443 case 1:
3444 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3445 break;
3446 case 2:
3447 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3448 break;
3449 case 3:
3450 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3451 (imm << 8) | imm));
3452 break;
3453 }
3454 } else {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3455 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3456 unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3457 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3458 Inst.addOperand(MCOperand::CreateImm(imm));
3459 }
3460
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3461 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3462}
3463
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3464static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3465DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3466 uint64_t Address, const void *Decoder){
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3467 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby2a7d3a92012-04-12 23:13:34 +0000[diff] [blame]3468 true, 2, Inst, Decoder))
Richard Bartonc8f2fcc2012-06-06 09:12:53 +0000[diff] [blame]3469 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3470 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3471}
3472
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3473static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson10cbaab2011-08-10 17:36:48 +0000[diff] [blame]3474 uint64_t Address, const void *Decoder){
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3475 // Val is passed in as S:J1:J2:imm10:imm11
3476 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3477 // the encoded instruction. So here change to I1 and I2 values via:
3478 // I1 = NOT(J1 EOR S);
3479 // I2 = NOT(J2 EOR S);
3480 // and build the imm32 with one trailing zero as documented:
NAKAMURA Takumidd051a02012-05-22 21:47:02 +0000[diff] [blame]3481 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3482 unsigned S = (Val >> 23) & 1;
3483 unsigned J1 = (Val >> 22) & 1;
3484 unsigned J2 = (Val >> 21) & 1;
3485 unsigned I1 = !(J1 ^ S);
3486 unsigned I2 = !(J2 ^ S);
3487 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3488 int imm32 = SignExtend32<25>(tmp << 1);
3489
3490 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderbyb80d5712012-02-23 18:18:17 +0000[diff] [blame]3491 true, 4, Inst, Decoder))
Kevin Enderby2d524b02012-05-03 22:41:56 +0000[diff] [blame]3492 Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3493 return MCDisassembler::Success;
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000[diff] [blame]3494}
3495
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3496static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3497 uint64_t Address, const void *Decoder) {
Jiangning Liuc1b7ca52012-08-02 08:21:27 +0000[diff] [blame]3498 if (Val & ~0xf)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3499 return MCDisassembler::Fail;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3500
3501 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3502 return MCDisassembler::Success;
Owen Andersonc36481c2011-08-09 23:25:42 +0000[diff] [blame]3503}
3504
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3505static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3506 uint64_t Address, const void *Decoder) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3507 if (!Val) return MCDisassembler::Fail;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3508 Inst.addOperand(MCOperand::CreateImm(Val));
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3509 return MCDisassembler::Success;
Owen Anderson26d2f0a2011-08-11 20:21:46 +0000[diff] [blame]3510}
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3511
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3512static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3513 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3514 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3515
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3516 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3517 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3518 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3519
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3520 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3521
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3523 return MCDisassembler::Fail;
3524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3525 return MCDisassembler::Fail;
3526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3527 return MCDisassembler::Fail;
3528 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3529 return MCDisassembler::Fail;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3530
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3531 return S;
Owen Anderson3f3570a2011-08-12 17:58:32 +0000[diff] [blame]3532}
3533
3534
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3535static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbachc4057822011-08-17 21:58:18 +0000[diff] [blame]3536 uint64_t Address, const void *Decoder){
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3537 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3538
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3539 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3540 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3541 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3542 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3543
Tim Northoverd3af6962013-04-19 15:44:32 +0000[diff] [blame]3544 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3545 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3546
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3547 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3548 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3549
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3551 return MCDisassembler::Fail;
3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3553 return MCDisassembler::Fail;
3554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3555 return MCDisassembler::Fail;
3556 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3557 return MCDisassembler::Fail;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3558
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3559 return S;
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3560}
3561
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3562static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3563 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3564 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3565
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3566 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3567 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3568 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3569 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3570 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3571 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3572
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3573 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3574
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3578 return MCDisassembler::Fail;
3579 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3580 return MCDisassembler::Fail;
3581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3582 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3583
3584 return S;
3585}
3586
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3587static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3588 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3589 DecodeStatus S = MCDisassembler::Success;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3590
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3591 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3592 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3593 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3594 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3595 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3596 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3597 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3598
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3599 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3600 if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3601
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3603 return MCDisassembler::Fail;
3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3605 return MCDisassembler::Fail;
3606 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3607 return MCDisassembler::Fail;
3608 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3609 return MCDisassembler::Fail;
Owen Anderson9ab0f252011-08-26 20:43:14 +0000[diff] [blame]3610
3611 return S;
3612}
3613
3614
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3615static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3616 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3617 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3618
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3619 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3620 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3621 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3622 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3623 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3624 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncbfc0442011-08-11 21:34:58 +0000[diff] [blame]3625
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3626 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3627
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3629 return MCDisassembler::Fail;
3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3631 return MCDisassembler::Fail;
3632 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3633 return MCDisassembler::Fail;
3634 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3635 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3636
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3637 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3638}
3639
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3640static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3641 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3642 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3643
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3644 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3645 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3646 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3647 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3648 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3649 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3650
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3651 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3652
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3654 return MCDisassembler::Fail;
3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3658 return MCDisassembler::Fail;
3659 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3660 return MCDisassembler::Fail;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3661
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3662 return S;
Owen Anderson7cdbf082011-08-12 18:12:39 +0000[diff] [blame]3663}
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3664
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3665static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3666 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3667 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3668
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3669 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3670 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3671 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3672 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3673 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3674
3675 unsigned align = 0;
3676 unsigned index = 0;
3677 switch (size) {
3678 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3679 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3680 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3681 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3682 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3683 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3684 break;
3685 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3686 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3687 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3688 index = fieldFromInstruction(Insn, 6, 2);
3689 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3690 align = 2;
3691 break;
3692 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3693 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3694 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3695 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3696
3697 switch (fieldFromInstruction(Insn, 4, 2)) {
3698 case 0 :
3699 align = 0; break;
3700 case 3:
3701 align = 4; break;
3702 default:
3703 return MCDisassembler::Fail;
3704 }
3705 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3706 }
3707
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3709 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3710 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3712 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3713 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3715 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3716 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3717 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3718 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3720 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3721 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3722 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3723 }
3724
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3726 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3727 Inst.addOperand(MCOperand::CreateImm(index));
3728
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3729 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3730}
3731
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3732static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3733 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3734 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3735
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3736 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3737 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3738 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3739 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3740 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3741
3742 unsigned align = 0;
3743 unsigned index = 0;
3744 switch (size) {
3745 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3746 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3747 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3748 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3749 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3750 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3751 break;
3752 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3753 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3754 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3755 index = fieldFromInstruction(Insn, 6, 2);
3756 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3757 align = 2;
3758 break;
3759 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3760 if (fieldFromInstruction(Insn, 6, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3761 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3762 index = fieldFromInstruction(Insn, 7, 1);
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]3763
3764 switch (fieldFromInstruction(Insn, 4, 2)) {
3765 case 0:
3766 align = 0; break;
3767 case 3:
3768 align = 4; break;
3769 default:
3770 return MCDisassembler::Fail;
3771 }
3772 break;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3773 }
3774
3775 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3777 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3778 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3780 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3781 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3782 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3783 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3785 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3786 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3787 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3788 }
3789
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3791 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3792 Inst.addOperand(MCOperand::CreateImm(index));
3793
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3794 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3795}
3796
3797
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3798static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3799 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3800 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3801
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3803 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3804 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3805 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3806 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3807
3808 unsigned align = 0;
3809 unsigned index = 0;
3810 unsigned inc = 1;
3811 switch (size) {
3812 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3813 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3814 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3815 index = fieldFromInstruction(Insn, 5, 3);
3816 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3817 align = 2;
3818 break;
3819 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3820 index = fieldFromInstruction(Insn, 6, 2);
3821 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3822 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3823 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3824 inc = 2;
3825 break;
3826 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3827 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3828 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3829 index = fieldFromInstruction(Insn, 7, 1);
3830 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3831 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3832 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3833 inc = 2;
3834 break;
3835 }
3836
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3838 return MCDisassembler::Fail;
3839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3840 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3841 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3843 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3844 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3846 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3847 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3848 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3849 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3851 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3852 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3853 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3854 }
3855
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3856 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3857 return MCDisassembler::Fail;
3858 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3859 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3860 Inst.addOperand(MCOperand::CreateImm(index));
3861
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3862 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3863}
3864
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3865static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3866 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3867 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3868
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3869 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3870 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3871 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3872 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3873 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3874
3875 unsigned align = 0;
3876 unsigned index = 0;
3877 unsigned inc = 1;
3878 switch (size) {
3879 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3880 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3881 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3882 index = fieldFromInstruction(Insn, 5, 3);
3883 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3884 align = 2;
3885 break;
3886 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3887 index = fieldFromInstruction(Insn, 6, 2);
3888 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3889 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3890 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3891 inc = 2;
3892 break;
3893 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3894 if (fieldFromInstruction(Insn, 5, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3895 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3896 index = fieldFromInstruction(Insn, 7, 1);
3897 if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3898 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3899 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3900 inc = 2;
3901 break;
3902 }
3903
3904 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3906 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3907 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3909 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3910 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3911 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3912 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3914 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3915 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3916 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3917 }
3918
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3920 return MCDisassembler::Fail;
3921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3922 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3923 Inst.addOperand(MCOperand::CreateImm(index));
3924
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3925 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3926}
3927
3928
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3929static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3930 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3931 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3932
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3933 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3934 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3935 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3936 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3937 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3938
3939 unsigned align = 0;
3940 unsigned index = 0;
3941 unsigned inc = 1;
3942 switch (size) {
3943 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3944 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3945 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3946 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3947 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3948 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3949 break;
3950 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3951 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3952 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3953 index = fieldFromInstruction(Insn, 6, 2);
3954 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3955 inc = 2;
3956 break;
3957 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3958 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3959 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]3960 index = fieldFromInstruction(Insn, 7, 1);
3961 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3962 inc = 2;
3963 break;
3964 }
3965
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3967 return MCDisassembler::Fail;
3968 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3969 return MCDisassembler::Fail;
3970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3971 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3972
3973 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3975 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3976 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3978 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3979 Inst.addOperand(MCOperand::CreateImm(align));
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]3980 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3981 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3983 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]3984 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]3985 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3986 }
3987
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]3988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3989 return MCDisassembler::Fail;
3990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3991 return MCDisassembler::Fail;
3992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3993 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3994 Inst.addOperand(MCOperand::CreateImm(index));
3995
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]3996 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]3997}
3998
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]3999static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4000 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4001 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4002
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4004 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4005 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4006 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4007 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4008
4009 unsigned align = 0;
4010 unsigned index = 0;
4011 unsigned inc = 1;
4012 switch (size) {
4013 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4014 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4015 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4016 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4017 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4018 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4019 break;
4020 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4021 if (fieldFromInstruction(Insn, 4, 1))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4022 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4023 index = fieldFromInstruction(Insn, 6, 2);
4024 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4025 inc = 2;
4026 break;
4027 case 2:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4028 if (fieldFromInstruction(Insn, 4, 2))
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4029 return MCDisassembler::Fail; // UNDEFINED
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4030 index = fieldFromInstruction(Insn, 7, 1);
4031 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4032 inc = 2;
4033 break;
4034 }
4035
4036 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4038 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4039 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4041 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4042 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4043 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4044 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4045 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4046 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4047 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4048 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4049 }
4050
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4052 return MCDisassembler::Fail;
4053 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4054 return MCDisassembler::Fail;
4055 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4056 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4057 Inst.addOperand(MCOperand::CreateImm(index));
4058
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4059 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4060}
4061
4062
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4063static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4064 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4065 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4066
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4067 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4068 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4069 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4070 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4071 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4072
4073 unsigned align = 0;
4074 unsigned index = 0;
4075 unsigned inc = 1;
4076 switch (size) {
4077 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4078 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4079 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4080 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4081 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4082 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4083 break;
4084 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4085 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4086 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4087 index = fieldFromInstruction(Insn, 6, 2);
4088 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4089 inc = 2;
4090 break;
4091 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4092 switch (fieldFromInstruction(Insn, 4, 2)) {
4093 case 0:
4094 align = 0; break;
4095 case 3:
4096 return MCDisassembler::Fail;
4097 default:
4098 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4099 }
4100
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4101 index = fieldFromInstruction(Insn, 7, 1);
4102 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4103 inc = 2;
4104 break;
4105 }
4106
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4108 return MCDisassembler::Fail;
4109 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4110 return MCDisassembler::Fail;
4111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4112 return MCDisassembler::Fail;
4113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4114 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4115
4116 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4118 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4119 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4121 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4122 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4123 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4124 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4126 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4127 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4128 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4129 }
4130
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4132 return MCDisassembler::Fail;
4133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4134 return MCDisassembler::Fail;
4135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4136 return MCDisassembler::Fail;
4137 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4138 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4139 Inst.addOperand(MCOperand::CreateImm(index));
4140
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4141 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4142}
4143
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4144static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4145 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4146 DecodeStatus S = MCDisassembler::Success;
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4147
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4148 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4149 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4150 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4151 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4152 unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4153
4154 unsigned align = 0;
4155 unsigned index = 0;
4156 unsigned inc = 1;
4157 switch (size) {
4158 default:
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4159 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4160 case 0:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4161 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4162 align = 4;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4163 index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4164 break;
4165 case 1:
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4166 if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4167 align = 8;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4168 index = fieldFromInstruction(Insn, 6, 2);
4169 if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4170 inc = 2;
4171 break;
4172 case 2:
Tim Northovereae1d342012-09-06 15:17:49 +0000[diff] [blame]4173 switch (fieldFromInstruction(Insn, 4, 2)) {
4174 case 0:
4175 align = 0; break;
4176 case 3:
4177 return MCDisassembler::Fail;
4178 default:
4179 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4180 }
4181
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4182 index = fieldFromInstruction(Insn, 7, 1);
4183 if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4184 inc = 2;
4185 break;
4186 }
4187
4188 if (Rm != 0xF) { // Writeback
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4190 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4191 }
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4193 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4194 Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4195 if (Rm != 0xF) {
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4196 if (Rm != 0xD) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4198 return MCDisassembler::Fail;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4199 } else
Owen Anderson2cbf2102011-08-22 18:42:13 +0000[diff] [blame]4200 Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4201 }
4202
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4204 return MCDisassembler::Fail;
4205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4206 return MCDisassembler::Fail;
4207 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4208 return MCDisassembler::Fail;
4209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4210 return MCDisassembler::Fail;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4211 Inst.addOperand(MCOperand::CreateImm(index));
4212
Owen Anderson83e3f672011-08-17 17:44:15 +0000[diff] [blame]4213 return S;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000[diff] [blame]4214}
4215
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4216static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4217 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4218 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4219 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4220 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4221 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4222 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4223 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4224
4225 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4226 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4227
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4228 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4237 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4238
4239 return S;
4240}
4241
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4242static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4243 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4244 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4245 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4246 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4247 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4248 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4249 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4250
4251 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4252 S = MCDisassembler::SoftFail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4253
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4257 return MCDisassembler::Fail;
4258 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4259 return MCDisassembler::Fail;
4260 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4261 return MCDisassembler::Fail;
4262 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4263 return MCDisassembler::Fail;
Owen Anderson357ec682011-08-22 20:27:12 +0000[diff] [blame]4264
4265 return S;
4266}
Owen Anderson8e1e60b2011-08-22 23:44:04 +0000[diff] [blame]4267
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4268static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4269 uint64_t Address, const void *Decoder) {
Owen Andersona6804442011-09-01 23:23:50 +0000[diff] [blame]4270 DecodeStatus S = MCDisassembler::Success;
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4271 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4272 unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4273
4274 if (pred == 0xF) {
4275 pred = 0xE;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4276 S = MCDisassembler::SoftFail;
Owen Andersone234d022011-08-24 17:21:43 +0000[diff] [blame]4277 }
4278
Richard Barton4d2f0772012-04-27 08:42:59 +0000[diff] [blame]4279 if (mask == 0x0) {
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4280 mask |= 0x8;
James Molloyc047dca2011-09-01 18:02:14 +0000[diff] [blame]4281 S = MCDisassembler::SoftFail;
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4282 }
Owen Andersoneaca9282011-08-30 22:58:27 +0000[diff] [blame]4283
4284 Inst.addOperand(MCOperand::CreateImm(pred));
4285 Inst.addOperand(MCOperand::CreateImm(mask));
Owen Andersonf4408202011-08-24 22:40:22 +0000[diff] [blame]4286 return S;
4287}
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4288
4289static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4290DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4291 uint64_t Address, const void *Decoder) {
4292 DecodeStatus S = MCDisassembler::Success;
4293
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4294 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4295 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4296 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4297 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4298 unsigned W = fieldFromInstruction(Insn, 21, 1);
4299 unsigned U = fieldFromInstruction(Insn, 23, 1);
4300 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4301 bool writeback = (W == 1) | (P == 0);
4302
4303 addr |= (U << 8) | (Rn << 9);
4304
4305 if (writeback && (Rn == Rt || Rn == Rt2))
4306 Check(S, MCDisassembler::SoftFail);
4307 if (Rt == Rt2)
4308 Check(S, MCDisassembler::SoftFail);
4309
4310 // Rt
4311 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4312 return MCDisassembler::Fail;
4313 // Rt2
4314 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4315 return MCDisassembler::Fail;
4316 // Writeback operand
4317 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319 // addr
4320 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4321 return MCDisassembler::Fail;
4322
4323 return S;
4324}
4325
4326static DecodeStatus
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4327DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4328 uint64_t Address, const void *Decoder) {
4329 DecodeStatus S = MCDisassembler::Success;
4330
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4331 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4332 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4333 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4334 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4335 unsigned W = fieldFromInstruction(Insn, 21, 1);
4336 unsigned U = fieldFromInstruction(Insn, 23, 1);
4337 unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbacha77295d2011-09-08 22:07:06 +0000[diff] [blame]4338 bool writeback = (W == 1) | (P == 0);
4339
4340 addr |= (U << 8) | (Rn << 9);
4341
4342 if (writeback && (Rn == Rt || Rn == Rt2))
4343 Check(S, MCDisassembler::SoftFail);
4344
4345 // Writeback operand
4346 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4347 return MCDisassembler::Fail;
4348 // Rt
4349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4350 return MCDisassembler::Fail;
4351 // Rt2
4352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4353 return MCDisassembler::Fail;
4354 // addr
4355 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4356 return MCDisassembler::Fail;
4357
4358 return S;
4359}
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4360
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4361static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4362 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4363 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4364 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4365 if (sign1 != sign2) return MCDisassembler::Fail;
4366
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4367 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4368 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4369 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson08fef882011-09-09 22:24:36 +0000[diff] [blame]4370 Val |= sign1 << 12;
4371 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4372
4373 return MCDisassembler::Success;
4374}
4375
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4376static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson0afa0092011-09-26 21:06:22 +0000[diff] [blame]4377 uint64_t Address,
4378 const void *Decoder) {
4379 DecodeStatus S = MCDisassembler::Success;
4380
4381 // Shift of "asr #32" is not allowed in Thumb2 mode.
4382 if (Val == 0x20) S = MCDisassembler::SoftFail;
4383 Inst.addOperand(MCOperand::CreateImm(Val));
4384 return S;
4385}
4386
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4387static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4388 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4389 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4390 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4391 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4392 unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4393
4394 if (pred == 0xF)
4395 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4396
4397 DecodeStatus S = MCDisassembler::Success;
Silviu Baranga35ee7d22012-04-18 14:18:57 +0000[diff] [blame]4398
4399 if (Rt == Rn || Rn == Rt2)
4400 S = MCDisassembler::SoftFail;
4401
Owen Andersoncb9fed62011-10-28 18:02:13 +0000[diff] [blame]4402 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4405 return MCDisassembler::Fail;
4406 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4407 return MCDisassembler::Fail;
4408 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4409 return MCDisassembler::Fail;
4410
4411 return S;
4412}
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4413
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4414static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4415 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4416 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4417 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4418 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4419 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4420 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4421 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4422
4423 DecodeStatus S = MCDisassembler::Success;
4424
4425 // VMOVv2f32 is ambiguous with these decodings.
Owen Anderson22925d92011-11-15 20:30:41 +0000[diff] [blame]4426 if (!(imm & 0x38) && cmode == 0xF) {
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4427 Inst.setOpcode(ARM::VMOVv2f32);
4428 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4429 }
4430
4431 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4432
4433 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4438
4439 return S;
4440}
4441
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4442static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4443 uint64_t Address, const void *Decoder) {
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4444 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4445 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4446 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4447 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4448 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4449 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Owen Andersonb589be92011-11-15 19:55:00 +0000[diff] [blame]4450
4451 DecodeStatus S = MCDisassembler::Success;
4452
4453 // VMOVv4f32 is ambiguous with these decodings.
4454 if (!(imm & 0x38) && cmode == 0xF) {
4455 Inst.setOpcode(ARM::VMOVv4f32);
4456 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4457 }
4458
4459 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4460
4461 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4462 return MCDisassembler::Fail;
4463 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4464 return MCDisassembler::Fail;
4465 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4466
4467 return S;
4468}
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4469
Quentin Colombet7c4cf032013-04-17 18:46:12 +0000[diff] [blame]4470static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4471 const void *Decoder)
4472{
4473 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4474 if (Imm > 4) return MCDisassembler::Fail;
4475 Inst.addOperand(MCOperand::CreateImm(Imm));
4476 return MCDisassembler::Success;
4477}
4478
Craig Topperc89c7442012-03-27 07:21:54 +0000[diff] [blame]4479static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4480 uint64_t Address, const void *Decoder) {
4481 DecodeStatus S = MCDisassembler::Success;
4482
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4483 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4484 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4485 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4486 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4487 unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4488
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4489 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
Silviu Barangab7c2ed62012-03-22 13:24:43 +0000[diff] [blame]4490 S = MCDisassembler::SoftFail;
4491
4492 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4493 return MCDisassembler::Fail;
4494 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4495 return MCDisassembler::Fail;
4496 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4497 return MCDisassembler::Fail;
4498 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4499 return MCDisassembler::Fail;
4500 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4501 return MCDisassembler::Fail;
4502
4503 return S;
4504}
4505
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4506static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4507 uint64_t Address, const void *Decoder) {
4508
4509 DecodeStatus S = MCDisassembler::Success;
4510
Jim Grosbachfc1a1612012-08-14 19:06:05 +0000[diff] [blame]4511 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4512 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4513 unsigned cop = fieldFromInstruction(Val, 8, 4);
4514 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4515 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Barangafa1ebc62012-04-18 13:12:50 +0000[diff] [blame]4516
4517 if ((cop & ~0x1) == 0xa)
4518 return MCDisassembler::Fail;
4519
4520 if (Rt == Rt2)
4521 S = MCDisassembler::SoftFail;
4522
4523 Inst.addOperand(MCOperand::CreateImm(cop));
4524 Inst.addOperand(MCOperand::CreateImm(opc1));
4525 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4526 return MCDisassembler::Fail;
4527 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4528 return MCDisassembler::Fail;
4529 Inst.addOperand(MCOperand::CreateImm(CRm));
4530
4531 return S;
4532}
4533