blob: e2bea710614f72ed8fe9c7ce3bbd1460ffb09020 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
Clint Taylor01527b32014-07-07 13:01:46 -070031#include <linux/notifier.h>
32#include <linux/reboot.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
Matt Roperc6f95f22015-01-22 16:50:32 -080034#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070038#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010039#include <drm/i915_drm.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070040#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070041
Keith Packarda4fc5ed2009-04-07 16:16:42 -070042#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
Todd Previte559be302015-05-04 07:48:20 -070044/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080050struct dp_link_dpll {
Ville Syrjälä840b32b2015-08-11 20:21:46 +030051 int clock;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080052 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
Ville Syrjälä840b32b2015-08-11 20:21:46 +030056 { 162000,
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080057 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
Ville Syrjälä840b32b2015-08-11 20:21:46 +030058 { 270000,
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080059 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
Ville Syrjälä840b32b2015-08-11 20:21:46 +030063 { 162000,
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080064 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
Ville Syrjälä840b32b2015-08-11 20:21:46 +030065 { 270000,
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080066 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080069static const struct dp_link_dpll vlv_dpll[] = {
Ville Syrjälä840b32b2015-08-11 20:21:46 +030070 { 162000,
Chon Ming Lee58f6e632013-09-25 15:47:51 +080071 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
Ville Syrjälä840b32b2015-08-11 20:21:46 +030072 { 270000,
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080073 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
Chon Ming Leeef9348c2014-04-09 13:28:18 +030076/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
Ville Syrjälä840b32b2015-08-11 20:21:46 +030086 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
Chon Ming Leeef9348c2014-04-09 13:28:18 +030087 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
Ville Syrjälä840b32b2015-08-11 20:21:46 +030088 { 270000, /* m2_int = 27, m2_fraction = 0 */
Chon Ming Leeef9348c2014-04-09 13:28:18 +030089 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
Ville Syrjälä840b32b2015-08-11 20:21:46 +030090 { 540000, /* m2_int = 27, m2_fraction = 0 */
Chon Ming Leeef9348c2014-04-09 13:28:18 +030091 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
Sonika Jindal637a9c62015-05-07 09:52:08 +053093
Sonika Jindal64987fc2015-05-26 17:50:13 +053094static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
Sonika Jindal637a9c62015-05-07 09:52:08 +053096static const int skl_rates[] = { 162000, 216000, 270000,
Ville Syrjäläf4896f12015-03-12 17:10:27 +020097 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
Chon Ming Leeef9348c2014-04-09 13:28:18 +030099
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700112}
113
Imre Deak68b4d822013-05-08 13:14:06 +0300114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700115{
Imre Deak68b4d822013-05-08 13:14:06 +0300116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700119}
120
Chris Wilsondf0e9242010-09-09 16:20:55 +0100121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
Paulo Zanonifa90ece2012-10-26 19:05:44 -0200123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +0100124}
125
Chris Wilsonea5b2132010-08-04 13:50:23 +0100126static void intel_dp_link_down(struct intel_dp *intel_dp);
Ville Syrjälä1e0560e2014-08-19 13:24:25 +0300127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +0100128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Ville Syrjälä093e3f12014-10-16 21:27:33 +0300129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
Ville Syrjäläa8c33442014-10-16 21:29:59 +0300130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700132
Ville Syrjäläe0fce782015-07-08 23:45:54 +0300133static unsigned int intel_dp_unused_lane_mask(int lane_count)
134{
135 return ~((1 << lane_count) - 1) & 0xf;
136}
137
Ville Syrjäläed4e9c12015-03-12 17:10:36 +0200138static int
139intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700140{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700142
143 switch (max_link_bw) {
144 case DP_LINK_BW_1_62:
145 case DP_LINK_BW_2_7:
Ville Syrjälä1db10e22015-03-12 17:10:32 +0200146 case DP_LINK_BW_5_4:
Imre Deakd4eead52013-07-09 17:05:26 +0300147 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700148 default:
Imre Deakd4eead52013-07-09 17:05:26 +0300149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
150 max_link_bw);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700151 max_link_bw = DP_LINK_BW_1_62;
152 break;
153 }
154 return max_link_bw;
155}
156
Paulo Zanonieeb63242014-05-06 14:56:50 +0300157static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158{
159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Paulo Zanonieeb63242014-05-06 14:56:50 +0300160 u8 source_max, sink_max;
161
Ville Syrjäläccb1a832015-12-08 19:59:38 +0200162 source_max = intel_dig_port->max_lanes;
Paulo Zanonieeb63242014-05-06 14:56:50 +0300163 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
164
165 return min(source_max, sink_max);
166}
167
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400168/*
169 * The units on the numbers in the next two are... bizarre. Examples will
170 * make it clearer; this one parallels an example in the eDP spec.
171 *
172 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
173 *
174 * 270000 * 1 * 8 / 10 == 216000
175 *
176 * The actual data capacity of that configuration is 2.16Gbit/s, so the
177 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
178 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
179 * 119000. At 18bpp that's 2142000 kilobits per second.
180 *
181 * Thus the strange-looking division by 10 in intel_dp_link_required, to
182 * get the result in decakilobits instead of kilobits.
183 */
184
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700185static int
Keith Packardc8982612012-01-25 08:16:25 -0800186intel_dp_link_required(int pixel_clock, int bpp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700187{
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400188 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700189}
190
191static int
Dave Airliefe27d532010-06-30 11:46:17 +1000192intel_dp_max_data_rate(int max_link_clock, int max_lanes)
193{
194 return (max_link_clock * max_lanes * 8) / 10;
195}
196
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000197static enum drm_mode_status
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700198intel_dp_mode_valid(struct drm_connector *connector,
199 struct drm_display_mode *mode)
200{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100201 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +0300202 struct intel_connector *intel_connector = to_intel_connector(connector);
203 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Daniel Vetter36008362013-03-27 00:44:59 +0100204 int target_clock = mode->clock;
205 int max_rate, mode_rate, max_lanes, max_link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700206
Jani Nikuladd06f902012-10-19 14:51:50 +0300207 if (is_edp(intel_dp) && fixed_mode) {
208 if (mode->hdisplay > fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100209 return MODE_PANEL;
210
Jani Nikuladd06f902012-10-19 14:51:50 +0300211 if (mode->vdisplay > fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100212 return MODE_PANEL;
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200213
214 target_clock = fixed_mode->clock;
Zhao Yakui7de56f42010-07-19 09:43:14 +0100215 }
216
Ville Syrjälä50fec212015-03-12 17:10:34 +0200217 max_link_clock = intel_dp_max_link_rate(intel_dp);
Paulo Zanonieeb63242014-05-06 14:56:50 +0300218 max_lanes = intel_dp_max_lane_count(intel_dp);
Daniel Vetter36008362013-03-27 00:44:59 +0100219
220 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
221 mode_rate = intel_dp_link_required(target_clock, 18);
222
223 if (mode_rate > max_rate)
Daniel Vetterc4867932012-04-10 10:42:36 +0200224 return MODE_CLOCK_HIGH;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700225
226 if (mode->clock < 10000)
227 return MODE_CLOCK_LOW;
228
Daniel Vetter0af78a22012-05-23 11:30:55 +0200229 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
230 return MODE_H_ILLEGAL;
231
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700232 return MODE_OK;
233}
234
Rodrigo Vivia4f12892014-11-14 08:52:27 -0800235uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700236{
237 int i;
238 uint32_t v = 0;
239
240 if (src_bytes > 4)
241 src_bytes = 4;
242 for (i = 0; i < src_bytes; i++)
243 v |= ((uint32_t) src[i]) << ((3-i) * 8);
244 return v;
245}
246
Damien Lespiauc2af70e2015-02-10 19:32:23 +0000247static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700248{
249 int i;
250 if (dst_bytes > 4)
251 dst_bytes = 4;
252 for (i = 0; i < dst_bytes; i++)
253 dst[i] = src >> ((3-i) * 8);
254}
255
Jani Nikulabf13e812013-09-06 07:40:05 +0300256static void
257intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300258 struct intel_dp *intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +0300259static void
260intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300261 struct intel_dp *intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +0300262
Ville Syrjälä773538e82014-09-04 14:54:56 +0300263static void pps_lock(struct intel_dp *intel_dp)
264{
265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
266 struct intel_encoder *encoder = &intel_dig_port->base;
267 struct drm_device *dev = encoder->base.dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 enum intel_display_power_domain power_domain;
270
271 /*
272 * See vlv_power_sequencer_reset() why we need
273 * a power domain reference here.
274 */
Ville Syrjälä25f78f52015-11-16 15:01:04 +0100275 power_domain = intel_display_port_aux_power_domain(encoder);
Ville Syrjälä773538e82014-09-04 14:54:56 +0300276 intel_display_power_get(dev_priv, power_domain);
277
278 mutex_lock(&dev_priv->pps_mutex);
279}
280
281static void pps_unlock(struct intel_dp *intel_dp)
282{
283 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
284 struct intel_encoder *encoder = &intel_dig_port->base;
285 struct drm_device *dev = encoder->base.dev;
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 enum intel_display_power_domain power_domain;
288
289 mutex_unlock(&dev_priv->pps_mutex);
290
Ville Syrjälä25f78f52015-11-16 15:01:04 +0100291 power_domain = intel_display_port_aux_power_domain(encoder);
Ville Syrjälä773538e82014-09-04 14:54:56 +0300292 intel_display_power_put(dev_priv, power_domain);
293}
294
Ville Syrjälä961a0db2014-10-16 21:29:42 +0300295static void
296vlv_power_sequencer_kick(struct intel_dp *intel_dp)
297{
298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
299 struct drm_device *dev = intel_dig_port->base.base.dev;
300 struct drm_i915_private *dev_priv = dev->dev_private;
301 enum pipe pipe = intel_dp->pps_pipe;
Ville Syrjälä0047eed2015-07-10 10:56:24 +0300302 bool pll_enabled, release_cl_override = false;
303 enum dpio_phy phy = DPIO_PHY(pipe);
304 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
Ville Syrjälä961a0db2014-10-16 21:29:42 +0300305 uint32_t DP;
306
307 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
308 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
309 pipe_name(pipe), port_name(intel_dig_port->port)))
310 return;
311
312 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
313 pipe_name(pipe), port_name(intel_dig_port->port));
314
315 /* Preserve the BIOS-computed detected bit. This is
316 * supposed to be read-only.
317 */
318 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
319 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
320 DP |= DP_PORT_WIDTH(1);
321 DP |= DP_LINK_TRAIN_PAT_1;
322
323 if (IS_CHERRYVIEW(dev))
324 DP |= DP_PIPE_SELECT_CHV(pipe);
325 else if (pipe == PIPE_B)
326 DP |= DP_PIPEB_SELECT;
327
Ville Syrjäläd288f652014-10-28 13:20:22 +0200328 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
329
330 /*
331 * The DPLL for the pipe must be enabled for this to work.
332 * So enable temporarily it if it's not already enabled.
333 */
Ville Syrjälä0047eed2015-07-10 10:56:24 +0300334 if (!pll_enabled) {
335 release_cl_override = IS_CHERRYVIEW(dev) &&
336 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
337
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +0000338 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
339 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
340 DRM_ERROR("Failed to force on pll for pipe %c!\n",
341 pipe_name(pipe));
342 return;
343 }
Ville Syrjälä0047eed2015-07-10 10:56:24 +0300344 }
Ville Syrjäläd288f652014-10-28 13:20:22 +0200345
Ville Syrjälä961a0db2014-10-16 21:29:42 +0300346 /*
347 * Similar magic as in intel_dp_enable_port().
348 * We _must_ do this port enable + disable trick
349 * to make this power seqeuencer lock onto the port.
350 * Otherwise even VDD force bit won't work.
351 */
352 I915_WRITE(intel_dp->output_reg, DP);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
357
358 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
359 POSTING_READ(intel_dp->output_reg);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200360
Ville Syrjälä0047eed2015-07-10 10:56:24 +0300361 if (!pll_enabled) {
Ville Syrjäläd288f652014-10-28 13:20:22 +0200362 vlv_force_pll_off(dev, pipe);
Ville Syrjälä0047eed2015-07-10 10:56:24 +0300363
364 if (release_cl_override)
365 chv_phy_powergate_ch(dev_priv, phy, ch, false);
366 }
Ville Syrjälä961a0db2014-10-16 21:29:42 +0300367}
368
Jani Nikulabf13e812013-09-06 07:40:05 +0300369static enum pipe
370vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
371{
372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +0300373 struct drm_device *dev = intel_dig_port->base.base.dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300375 struct intel_encoder *encoder;
376 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
Ville Syrjäläa8c33442014-10-16 21:29:59 +0300377 enum pipe pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +0300378
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300379 lockdep_assert_held(&dev_priv->pps_mutex);
380
Ville Syrjäläa8c33442014-10-16 21:29:59 +0300381 /* We should never land here with regular DP ports */
382 WARN_ON(!is_edp(intel_dp));
383
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300384 if (intel_dp->pps_pipe != INVALID_PIPE)
385 return intel_dp->pps_pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +0300386
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300387 /*
388 * We don't have power sequencer currently.
389 * Pick one that's not used by other ports.
390 */
Jani Nikula19c80542015-12-16 12:48:16 +0200391 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300392 struct intel_dp *tmp;
393
394 if (encoder->type != INTEL_OUTPUT_EDP)
395 continue;
396
397 tmp = enc_to_intel_dp(&encoder->base);
398
399 if (tmp->pps_pipe != INVALID_PIPE)
400 pipes &= ~(1 << tmp->pps_pipe);
401 }
402
403 /*
404 * Didn't find one. This should not happen since there
405 * are two power sequencers and up to two eDP ports.
406 */
407 if (WARN_ON(pipes == 0))
Ville Syrjäläa8c33442014-10-16 21:29:59 +0300408 pipe = PIPE_A;
409 else
410 pipe = ffs(pipes) - 1;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300411
Ville Syrjäläa8c33442014-10-16 21:29:59 +0300412 vlv_steal_power_sequencer(dev, pipe);
413 intel_dp->pps_pipe = pipe;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300414
415 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
416 pipe_name(intel_dp->pps_pipe),
417 port_name(intel_dig_port->port));
418
419 /* init power sequencer on this pipe and port */
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300420 intel_dp_init_panel_power_sequencer(dev, intel_dp);
421 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300422
Ville Syrjälä961a0db2014-10-16 21:29:42 +0300423 /*
424 * Even vdd force doesn't work until we've made
425 * the power sequencer lock in on the port.
426 */
427 vlv_power_sequencer_kick(intel_dp);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300428
429 return intel_dp->pps_pipe;
430}
431
Ville Syrjälä6491ab22014-08-18 22:16:06 +0300432typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
433 enum pipe pipe);
434
435static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
436 enum pipe pipe)
437{
438 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
439}
440
441static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
442 enum pipe pipe)
443{
444 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
445}
446
447static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
448 enum pipe pipe)
449{
450 return true;
451}
452
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300453static enum pipe
Ville Syrjälä6491ab22014-08-18 22:16:06 +0300454vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
455 enum port port,
456 vlv_pipe_check pipe_check)
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300457{
Jani Nikulabf13e812013-09-06 07:40:05 +0300458 enum pipe pipe;
459
Jani Nikulabf13e812013-09-06 07:40:05 +0300460 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
461 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
462 PANEL_PORT_SELECT_MASK;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300463
464 if (port_sel != PANEL_PORT_SELECT_VLV(port))
465 continue;
466
Ville Syrjälä6491ab22014-08-18 22:16:06 +0300467 if (!pipe_check(dev_priv, pipe))
468 continue;
469
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300470 return pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +0300471 }
472
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300473 return INVALID_PIPE;
474}
475
476static void
477vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
478{
479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
480 struct drm_device *dev = intel_dig_port->base.base.dev;
481 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300482 enum port port = intel_dig_port->port;
483
484 lockdep_assert_held(&dev_priv->pps_mutex);
485
486 /* try to find a pipe with this port selected */
Ville Syrjälä6491ab22014-08-18 22:16:06 +0300487 /* first pick one where the panel is on */
488 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
489 vlv_pipe_has_pp_on);
490 /* didn't find one? pick one where vdd is on */
491 if (intel_dp->pps_pipe == INVALID_PIPE)
492 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
493 vlv_pipe_has_vdd_on);
494 /* didn't find one? pick one with just the correct port */
495 if (intel_dp->pps_pipe == INVALID_PIPE)
496 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
497 vlv_pipe_any);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300498
499 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
500 if (intel_dp->pps_pipe == INVALID_PIPE) {
501 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
502 port_name(port));
503 return;
504 }
505
506 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
507 port_name(port), pipe_name(intel_dp->pps_pipe));
508
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300509 intel_dp_init_panel_power_sequencer(dev, intel_dp);
510 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +0300511}
512
Ville Syrjälä773538e82014-09-04 14:54:56 +0300513void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
514{
515 struct drm_device *dev = dev_priv->dev;
516 struct intel_encoder *encoder;
517
Wayne Boyer666a4532015-12-09 12:29:35 -0800518 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
Ville Syrjälä773538e82014-09-04 14:54:56 +0300519 return;
520
521 /*
522 * We can't grab pps_mutex here due to deadlock with power_domain
523 * mutex when power_domain functions are called while holding pps_mutex.
524 * That also means that in order to use pps_pipe the code needs to
525 * hold both a power domain reference and pps_mutex, and the power domain
526 * reference get/put must be done while _not_ holding pps_mutex.
527 * pps_{lock,unlock}() do these steps in the correct order, so one
528 * should use them always.
529 */
530
Jani Nikula19c80542015-12-16 12:48:16 +0200531 for_each_intel_encoder(dev, encoder) {
Ville Syrjälä773538e82014-09-04 14:54:56 +0300532 struct intel_dp *intel_dp;
533
534 if (encoder->type != INTEL_OUTPUT_EDP)
535 continue;
536
537 intel_dp = enc_to_intel_dp(&encoder->base);
538 intel_dp->pps_pipe = INVALID_PIPE;
539 }
Jani Nikulabf13e812013-09-06 07:40:05 +0300540}
541
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200542static i915_reg_t
543_pp_ctrl_reg(struct intel_dp *intel_dp)
Jani Nikulabf13e812013-09-06 07:40:05 +0300544{
545 struct drm_device *dev = intel_dp_to_dev(intel_dp);
546
Vandana Kannanb0a08be2015-06-18 11:00:55 +0530547 if (IS_BROXTON(dev))
548 return BXT_PP_CONTROL(0);
549 else if (HAS_PCH_SPLIT(dev))
Jani Nikulabf13e812013-09-06 07:40:05 +0300550 return PCH_PP_CONTROL;
551 else
552 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
553}
554
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200555static i915_reg_t
556_pp_stat_reg(struct intel_dp *intel_dp)
Jani Nikulabf13e812013-09-06 07:40:05 +0300557{
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559
Vandana Kannanb0a08be2015-06-18 11:00:55 +0530560 if (IS_BROXTON(dev))
561 return BXT_PP_STATUS(0);
562 else if (HAS_PCH_SPLIT(dev))
Jani Nikulabf13e812013-09-06 07:40:05 +0300563 return PCH_PP_STATUS;
564 else
565 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
566}
567
Clint Taylor01527b32014-07-07 13:01:46 -0700568/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
569 This function only applicable when panel PM state is not to be tracked */
570static int edp_notify_handler(struct notifier_block *this, unsigned long code,
571 void *unused)
572{
573 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
574 edp_notifier);
575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
576 struct drm_i915_private *dev_priv = dev->dev_private;
Clint Taylor01527b32014-07-07 13:01:46 -0700577
578 if (!is_edp(intel_dp) || code != SYS_RESTART)
579 return 0;
580
Ville Syrjälä773538e82014-09-04 14:54:56 +0300581 pps_lock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300582
Wayne Boyer666a4532015-12-09 12:29:35 -0800583 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200585 i915_reg_t pp_ctrl_reg, pp_div_reg;
Ville Syrjälä649636e2015-09-22 19:50:01 +0300586 u32 pp_div;
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300587
Clint Taylor01527b32014-07-07 13:01:46 -0700588 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
590 pp_div = I915_READ(pp_div_reg);
591 pp_div &= PP_REFERENCE_DIVIDER_MASK;
592
593 /* 0x1F write to PP_DIV_REG sets max cycle delay */
594 I915_WRITE(pp_div_reg, pp_div | 0x1F);
595 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
596 msleep(intel_dp->panel_power_cycle_delay);
597 }
598
Ville Syrjälä773538e82014-09-04 14:54:56 +0300599 pps_unlock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300600
Clint Taylor01527b32014-07-07 13:01:46 -0700601 return 0;
602}
603
Daniel Vetter4be73782014-01-17 14:39:48 +0100604static bool edp_have_panel_power(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700605{
Paulo Zanoni30add222012-10-26 19:05:45 -0200606 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700607 struct drm_i915_private *dev_priv = dev->dev_private;
608
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300609 lockdep_assert_held(&dev_priv->pps_mutex);
610
Wayne Boyer666a4532015-12-09 12:29:35 -0800611 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
Ville Syrjälä9a423562014-10-16 21:29:48 +0300612 intel_dp->pps_pipe == INVALID_PIPE)
613 return false;
614
Jani Nikulabf13e812013-09-06 07:40:05 +0300615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700616}
617
Daniel Vetter4be73782014-01-17 14:39:48 +0100618static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700619{
Paulo Zanoni30add222012-10-26 19:05:45 -0200620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700621 struct drm_i915_private *dev_priv = dev->dev_private;
622
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300623 lockdep_assert_held(&dev_priv->pps_mutex);
624
Wayne Boyer666a4532015-12-09 12:29:35 -0800625 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
Ville Syrjälä9a423562014-10-16 21:29:48 +0300626 intel_dp->pps_pipe == INVALID_PIPE)
627 return false;
628
Ville Syrjälä773538e82014-09-04 14:54:56 +0300629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -0700630}
631
Keith Packard9b984da2011-09-19 13:54:47 -0700632static void
633intel_dp_check_edp(struct intel_dp *intel_dp)
634{
Paulo Zanoni30add222012-10-26 19:05:45 -0200635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard9b984da2011-09-19 13:54:47 -0700636 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700637
Keith Packard9b984da2011-09-19 13:54:47 -0700638 if (!is_edp(intel_dp))
639 return;
Jesse Barnes453c5422013-03-28 09:55:41 -0700640
Daniel Vetter4be73782014-01-17 14:39:48 +0100641 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700642 WARN(1, "eDP powered off while attempting aux channel communication.\n");
643 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Jani Nikulabf13e812013-09-06 07:40:05 +0300644 I915_READ(_pp_stat_reg(intel_dp)),
645 I915_READ(_pp_ctrl_reg(intel_dp)));
Keith Packard9b984da2011-09-19 13:54:47 -0700646 }
647}
648
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100649static uint32_t
650intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
651{
652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
653 struct drm_device *dev = intel_dig_port->base.base.dev;
654 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200655 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100656 uint32_t status;
657 bool done;
658
Daniel Vetteref04f002012-12-01 21:03:59 +0100659#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100660 if (has_aux_irq)
Paulo Zanonib18ac462013-02-18 19:00:24 -0300661 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
Imre Deak35987062013-05-21 20:03:20 +0300662 msecs_to_jiffies_timeout(10));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100663 else
664 done = wait_for_atomic(C, 10) == 0;
665 if (!done)
666 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
667 has_aux_irq);
668#undef C
669
670 return status;
671}
672
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000673static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
674{
675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
676 struct drm_device *dev = intel_dig_port->base.base.dev;
677
678 /*
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2 and use that
681 */
Ville Syrjäläfce18c42015-11-30 16:23:46 +0200682 return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2);
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000683}
684
685static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
Ville Syrjälä469d4b22015-03-31 14:11:59 +0300689 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000690
691 if (index)
692 return 0;
693
694 if (intel_dig_port->port == PORT_A) {
Ville Syrjäläfce18c42015-11-30 16:23:46 +0200695 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
Ville Syrjälä05024da2015-06-03 15:45:08 +0300696
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000697 } else {
Ville Syrjäläfce18c42015-11-30 16:23:46 +0200698 return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000699 }
700}
701
702static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300703{
704 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
705 struct drm_device *dev = intel_dig_port->base.base.dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000708 if (intel_dig_port->port == PORT_A) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100709 if (index)
710 return 0;
Ville Syrjälä05024da2015-06-03 15:45:08 +0300711 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
Ville Syrjälä56f5f702015-11-30 16:23:44 +0200712 } else if (HAS_PCH_LPT_H(dev_priv)) {
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300713 /* Workaround for non-ULT HSW */
Chris Wilsonbc866252013-07-21 16:00:03 +0100714 switch (index) {
715 case 0: return 63;
716 case 1: return 72;
717 default: return 0;
718 }
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000719 } else {
Ville Syrjäläfce18c42015-11-30 16:23:46 +0200720 return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300721 }
722}
723
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000724static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 return index ? 0 : 100;
727}
728
Damien Lespiaub6b5e382014-01-20 16:00:59 +0000729static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
730{
731 /*
732 * SKL doesn't need us to program the AUX clock divider (Hardware will
733 * derive the clock from CDCLK automatically). We still implement the
734 * get_aux_clock_divider vfunc to plug-in into the existing code.
735 */
736 return index ? 0 : 1;
737}
738
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000739static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
740 bool has_aux_irq,
741 int send_bytes,
742 uint32_t aux_clock_divider)
743{
744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
745 struct drm_device *dev = intel_dig_port->base.base.dev;
746 uint32_t precharge, timeout;
747
748 if (IS_GEN6(dev))
749 precharge = 3;
750 else
751 precharge = 5;
752
Ville Syrjäläf3c6a3a2015-11-11 20:34:10 +0200753 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000754 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
755 else
756 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
757
758 return DP_AUX_CH_CTL_SEND_BUSY |
Damien Lespiau788d4432014-01-20 15:52:31 +0000759 DP_AUX_CH_CTL_DONE |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000760 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000761 DP_AUX_CH_CTL_TIME_OUT_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000762 timeout |
Damien Lespiau788d4432014-01-20 15:52:31 +0000763 DP_AUX_CH_CTL_RECEIVE_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000764 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
765 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000766 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000767}
768
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +0000769static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
770 bool has_aux_irq,
771 int send_bytes,
772 uint32_t unused)
773{
774 return DP_AUX_CH_CTL_SEND_BUSY |
775 DP_AUX_CH_CTL_DONE |
776 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
777 DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_TIME_OUT_1600us |
779 DP_AUX_CH_CTL_RECEIVE_ERROR |
780 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
781 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
782}
783
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700784static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100785intel_dp_aux_ch(struct intel_dp *intel_dp,
Daniel Vetterbd9f74a2014-10-02 09:45:35 +0200786 const uint8_t *send, int send_bytes,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700787 uint8_t *recv, int recv_size)
788{
Paulo Zanoni174edf12012-10-26 19:05:50 -0200789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
790 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700791 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200792 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Chris Wilsonbc866252013-07-21 16:00:03 +0100793 uint32_t aux_clock_divider;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100794 int i, ret, recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700795 uint32_t status;
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000796 int try, clock = 0;
Daniel Vetter4e6b7882014-02-07 16:33:20 +0100797 bool has_aux_irq = HAS_AUX_IRQ(dev);
Jani Nikula884f19e2014-03-14 16:51:14 +0200798 bool vdd;
799
Ville Syrjälä773538e82014-09-04 14:54:56 +0300800 pps_lock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300801
Ville Syrjälä72c35002014-08-18 22:16:00 +0300802 /*
803 * We will be called with VDD already enabled for dpcd/edid/oui reads.
804 * In such cases we want to leave VDD enabled and it's up to upper layers
805 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
806 * ourselves.
807 */
Ville Syrjälä1e0560e2014-08-19 13:24:25 +0300808 vdd = edp_panel_vdd_on(intel_dp);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100809
810 /* dp aux is extremely sensitive to irq latency, hence request the
811 * lowest possible wakeup latency and so prevent the cpu from going into
812 * deep sleep states.
813 */
814 pm_qos_update_request(&dev_priv->pm_qos, 0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700815
Keith Packard9b984da2011-09-19 13:54:47 -0700816 intel_dp_check_edp(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800817
Jesse Barnes11bee432011-08-01 15:02:20 -0700818 /* Try to wait for any previous AUX channel activity */
819 for (try = 0; try < 3; try++) {
Daniel Vetteref04f002012-12-01 21:03:59 +0100820 status = I915_READ_NOTRACE(ch_ctl);
Jesse Barnes11bee432011-08-01 15:02:20 -0700821 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
822 break;
823 msleep(1);
824 }
825
826 if (try == 3) {
Mika Kuoppala02196c72015-08-06 16:48:58 +0300827 static u32 last_status = -1;
828 const u32 status = I915_READ(ch_ctl);
829
830 if (status != last_status) {
831 WARN(1, "dp_aux_ch not started status 0x%08x\n",
832 status);
833 last_status = status;
834 }
835
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100836 ret = -EBUSY;
837 goto out;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100838 }
839
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300840 /* Only 5 data registers! */
841 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
842 ret = -E2BIG;
843 goto out;
844 }
845
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000846 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Damien Lespiau153b1102014-01-21 13:37:15 +0000847 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
848 has_aux_irq,
849 send_bytes,
850 aux_clock_divider);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000851
Chris Wilsonbc866252013-07-21 16:00:03 +0100852 /* Must try at least 3 times according to DP spec */
853 for (try = 0; try < 5; try++) {
854 /* Load the send data into the aux channel data registers */
855 for (i = 0; i < send_bytes; i += 4)
Ville Syrjälä330e20e2015-11-11 20:34:14 +0200856 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
Rodrigo Vivia4f12892014-11-14 08:52:27 -0800857 intel_dp_pack_aux(send + i,
858 send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400859
Chris Wilsonbc866252013-07-21 16:00:03 +0100860 /* Send the command and wait for it to complete */
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000861 I915_WRITE(ch_ctl, send_ctl);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100862
Chris Wilsonbc866252013-07-21 16:00:03 +0100863 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
Akshay Joshi0206e352011-08-16 15:34:10 -0400864
Chris Wilsonbc866252013-07-21 16:00:03 +0100865 /* Clear done status and any errors */
866 I915_WRITE(ch_ctl,
867 status |
868 DP_AUX_CH_CTL_DONE |
869 DP_AUX_CH_CTL_TIME_OUT_ERROR |
870 DP_AUX_CH_CTL_RECEIVE_ERROR);
Adam Jacksond7e96fe2011-07-26 15:39:46 -0400871
Todd Previte74ebf292015-04-15 08:38:41 -0700872 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
Chris Wilsonbc866252013-07-21 16:00:03 +0100873 continue;
Todd Previte74ebf292015-04-15 08:38:41 -0700874
875 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
876 * 400us delay required for errors and timeouts
877 * Timeout errors from the HW already meet this
878 * requirement so skip to next iteration
879 */
880 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
881 usleep_range(400, 500);
882 continue;
883 }
Chris Wilsonbc866252013-07-21 16:00:03 +0100884 if (status & DP_AUX_CH_CTL_DONE)
Jim Bridee058c942015-05-27 10:21:48 -0700885 goto done;
Chris Wilsonbc866252013-07-21 16:00:03 +0100886 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700887 }
888
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100891 ret = -EBUSY;
892 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700893 }
894
Jim Bridee058c942015-05-27 10:21:48 -0700895done:
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100901 ret = -EIO;
902 goto out;
Keith Packarda5b3da52009-06-11 22:30:32 -0700903 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100909 ret = -ETIMEDOUT;
910 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Rodrigo Vivi14e01882015-12-10 11:12:27 -0800916
917 /*
918 * By BSpec: "Message sizes of 0 or >20 are not allowed."
919 * We have no idea of what happened so we return -EBUSY so
920 * drm layer takes care for the necessary retries.
921 */
922 if (recv_bytes == 0 || recv_bytes > 20) {
923 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
924 recv_bytes);
925 /*
926 * FIXME: This patch was created on top of a series that
927 * organize the retries at drm level. There EBUSY should
928 * also take care for 1ms wait before retrying.
929 * That aux retries re-org is still needed and after that is
930 * merged we remove this sleep from here.
931 */
932 usleep_range(1000, 1500);
933 ret = -EBUSY;
934 goto out;
935 }
936
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700937 if (recv_bytes > recv_size)
938 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400939
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100940 for (i = 0; i < recv_bytes; i += 4)
Ville Syrjälä330e20e2015-11-11 20:34:14 +0200941 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
Rodrigo Vivia4f12892014-11-14 08:52:27 -0800942 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700943
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100944 ret = recv_bytes;
945out:
946 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
947
Jani Nikula884f19e2014-03-14 16:51:14 +0200948 if (vdd)
949 edp_panel_vdd_off(intel_dp, false);
950
Ville Syrjälä773538e82014-09-04 14:54:56 +0300951 pps_unlock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +0300952
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100953 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700954}
955
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300956#define BARE_ADDRESS_SIZE 3
957#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
Jani Nikula9d1a1032014-03-14 16:51:15 +0200958static ssize_t
959intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700960{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200961 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
962 uint8_t txbuf[20], rxbuf[20];
963 size_t txsize, rxsize;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700964 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700965
Ville Syrjäläd2d9cbb2015-03-19 11:44:06 +0200966 txbuf[0] = (msg->request << 4) |
967 ((msg->address >> 16) & 0xf);
968 txbuf[1] = (msg->address >> 8) & 0xff;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200969 txbuf[2] = msg->address & 0xff;
970 txbuf[3] = msg->size - 1;
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300971
Jani Nikula9d1a1032014-03-14 16:51:15 +0200972 switch (msg->request & ~DP_AUX_I2C_MOT) {
973 case DP_AUX_NATIVE_WRITE:
974 case DP_AUX_I2C_WRITE:
Ville Syrjäläc1e741222015-08-27 17:23:27 +0300975 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300976 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
Jani Nikulaa1ddefd2015-03-17 17:18:54 +0200977 rxsize = 2; /* 0 or 1 data bytes */
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200978
Jani Nikula9d1a1032014-03-14 16:51:15 +0200979 if (WARN_ON(txsize > 20))
980 return -E2BIG;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700981
Jani Nikula9d1a1032014-03-14 16:51:15 +0200982 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700983
Jani Nikula9d1a1032014-03-14 16:51:15 +0200984 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
985 if (ret > 0) {
986 msg->reply = rxbuf[0] >> 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700987
Jani Nikulaa1ddefd2015-03-17 17:18:54 +0200988 if (ret > 1) {
989 /* Number of bytes written in a short write. */
990 ret = clamp_t(int, rxbuf[1], 0, msg->size);
991 } else {
992 /* Return payload size. */
993 ret = msg->size;
994 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700995 }
Jani Nikula9d1a1032014-03-14 16:51:15 +0200996 break;
997
998 case DP_AUX_NATIVE_READ:
999 case DP_AUX_I2C_READ:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +03001000 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +02001001 rxsize = msg->size + 1;
1002
1003 if (WARN_ON(rxsize > 20))
1004 return -E2BIG;
1005
1006 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007 if (ret > 0) {
1008 msg->reply = rxbuf[0] >> 4;
1009 /*
1010 * Assume happy day, and copy the data. The caller is
1011 * expected to check msg->reply before touching it.
1012 *
1013 * Return payload size.
1014 */
1015 ret--;
1016 memcpy(msg->buffer, rxbuf + 1, ret);
1017 }
1018 break;
1019
1020 default:
1021 ret = -EINVAL;
1022 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001023 }
Jani Nikulaf51a44b2014-02-11 11:52:05 +02001024
Jani Nikula9d1a1032014-03-14 16:51:15 +02001025 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001026}
1027
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001028static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029 enum port port)
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02001030{
1031 switch (port) {
1032 case PORT_B:
1033 case PORT_C:
1034 case PORT_D:
1035 return DP_AUX_CH_CTL(port);
1036 default:
1037 MISSING_CASE(port);
1038 return DP_AUX_CH_CTL(PORT_B);
1039 }
1040}
1041
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001042static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043 enum port port, int index)
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001044{
1045 switch (port) {
1046 case PORT_B:
1047 case PORT_C:
1048 case PORT_D:
1049 return DP_AUX_CH_DATA(port, index);
1050 default:
1051 MISSING_CASE(port);
1052 return DP_AUX_CH_DATA(PORT_B, index);
1053 }
1054}
1055
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001056static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057 enum port port)
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02001058{
1059 switch (port) {
1060 case PORT_A:
1061 return DP_AUX_CH_CTL(port);
1062 case PORT_B:
1063 case PORT_C:
1064 case PORT_D:
1065 return PCH_DP_AUX_CH_CTL(port);
1066 default:
1067 MISSING_CASE(port);
1068 return DP_AUX_CH_CTL(PORT_A);
1069 }
1070}
1071
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001072static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073 enum port port, int index)
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001074{
1075 switch (port) {
1076 case PORT_A:
1077 return DP_AUX_CH_DATA(port, index);
1078 case PORT_B:
1079 case PORT_C:
1080 case PORT_D:
1081 return PCH_DP_AUX_CH_DATA(port, index);
1082 default:
1083 MISSING_CASE(port);
1084 return DP_AUX_CH_DATA(PORT_A, index);
1085 }
1086}
1087
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02001088/*
1089 * On SKL we don't have Aux for port E so we rely
1090 * on VBT to set a proper alternate aux channel.
1091 */
1092static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093{
1094 const struct ddi_vbt_port_info *info =
1095 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097 switch (info->alternate_aux_channel) {
1098 case DP_AUX_A:
1099 return PORT_A;
1100 case DP_AUX_B:
1101 return PORT_B;
1102 case DP_AUX_C:
1103 return PORT_C;
1104 case DP_AUX_D:
1105 return PORT_D;
1106 default:
1107 MISSING_CASE(info->alternate_aux_channel);
1108 return PORT_A;
1109 }
1110}
1111
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001112static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113 enum port port)
Ville Syrjäläda00bdc2015-11-11 20:34:13 +02001114{
1115 if (port == PORT_E)
1116 port = skl_porte_aux_port(dev_priv);
1117
1118 switch (port) {
1119 case PORT_A:
1120 case PORT_B:
1121 case PORT_C:
1122 case PORT_D:
1123 return DP_AUX_CH_CTL(port);
1124 default:
1125 MISSING_CASE(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1127 }
1128}
1129
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001130static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001132{
1133 if (port == PORT_E)
1134 port = skl_porte_aux_port(dev_priv);
1135
1136 switch (port) {
1137 case PORT_A:
1138 case PORT_B:
1139 case PORT_C:
1140 case PORT_D:
1141 return DP_AUX_CH_DATA(port, index);
1142 default:
1143 MISSING_CASE(port);
1144 return DP_AUX_CH_DATA(PORT_A, index);
1145 }
1146}
1147
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001148static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149 enum port port)
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001150{
1151 if (INTEL_INFO(dev_priv)->gen >= 9)
1152 return skl_aux_ctl_reg(dev_priv, port);
1153 else if (HAS_PCH_SPLIT(dev_priv))
1154 return ilk_aux_ctl_reg(dev_priv, port);
1155 else
1156 return g4x_aux_ctl_reg(dev_priv, port);
1157}
1158
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001159static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160 enum port port, int index)
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001161{
1162 if (INTEL_INFO(dev_priv)->gen >= 9)
1163 return skl_aux_data_reg(dev_priv, port, index);
1164 else if (HAS_PCH_SPLIT(dev_priv))
1165 return ilk_aux_data_reg(dev_priv, port, index);
1166 else
1167 return g4x_aux_data_reg(dev_priv, port, index);
1168}
1169
1170static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171{
1172 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173 enum port port = dp_to_dig_port(intel_dp)->port;
1174 int i;
1175
1176 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179}
1180
Jani Nikula9d1a1032014-03-14 16:51:15 +02001181static void
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001182intel_dp_aux_fini(struct intel_dp *intel_dp)
1183{
1184 drm_dp_aux_unregister(&intel_dp->aux);
1185 kfree(intel_dp->aux.name);
1186}
1187
1188static int
Jani Nikula9d1a1032014-03-14 16:51:15 +02001189intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001190{
Jani Nikula9d1a1032014-03-14 16:51:15 +02001191 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jani Nikula33ad6622014-03-14 16:51:16 +02001192 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1193 enum port port = intel_dig_port->port;
Dave Airlieab2c0672009-12-04 10:55:24 +10001194 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001195
Ville Syrjälä330e20e2015-11-11 20:34:14 +02001196 intel_aux_reg_init(intel_dp);
David Flynn8316f332010-12-08 16:10:21 +00001197
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001198 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1199 if (!intel_dp->aux.name)
1200 return -ENOMEM;
1201
Jani Nikula9d1a1032014-03-14 16:51:15 +02001202 intel_dp->aux.dev = dev->dev;
1203 intel_dp->aux.transfer = intel_dp_aux_transfer;
David Flynn8316f332010-12-08 16:10:21 +00001204
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001205 DRM_DEBUG_KMS("registering %s bus for %s\n",
1206 intel_dp->aux.name,
Jani Nikula0b998362014-03-14 16:51:17 +02001207 connector->base.kdev->kobj.name);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001208
Dave Airlie4f71d0c2014-06-04 16:02:28 +10001209 ret = drm_dp_aux_register(&intel_dp->aux);
Jani Nikula0b998362014-03-14 16:51:17 +02001210 if (ret < 0) {
Dave Airlie4f71d0c2014-06-04 16:02:28 +10001211 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001212 intel_dp->aux.name, ret);
1213 kfree(intel_dp->aux.name);
1214 return ret;
Dave Airlieab2c0672009-12-04 10:55:24 +10001215 }
David Flynn8316f332010-12-08 16:10:21 +00001216
Jani Nikula0b998362014-03-14 16:51:17 +02001217 ret = sysfs_create_link(&connector->base.kdev->kobj,
1218 &intel_dp->aux.ddc.dev.kobj,
1219 intel_dp->aux.ddc.dev.kobj.name);
1220 if (ret < 0) {
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001221 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1222 intel_dp->aux.name, ret);
1223 intel_dp_aux_fini(intel_dp);
1224 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001225 }
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02001226
1227 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001228}
1229
Imre Deak80f65de2014-02-11 17:12:49 +02001230static void
1231intel_dp_connector_unregister(struct intel_connector *intel_connector)
1232{
1233 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1234
Dave Airlie0e32b392014-05-02 14:02:48 +10001235 if (!intel_connector->mst_port)
1236 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1237 intel_dp->aux.ddc.dev.kobj.name);
Imre Deak80f65de2014-02-11 17:12:49 +02001238 intel_connector_unregister(intel_connector);
1239}
1240
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001241static void
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001242skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
Damien Lespiau5416d872014-11-14 17:24:33 +00001243{
1244 u32 ctrl1;
1245
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03001246 memset(&pipe_config->dpll_hw_state, 0,
1247 sizeof(pipe_config->dpll_hw_state));
1248
Damien Lespiau5416d872014-11-14 17:24:33 +00001249 pipe_config->ddi_pll_sel = SKL_DPLL0;
1250 pipe_config->dpll_hw_state.cfgcr1 = 0;
1251 pipe_config->dpll_hw_state.cfgcr2 = 0;
1252
1253 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001254 switch (pipe_config->port_clock / 2) {
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301255 case 81000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001256 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
Damien Lespiau5416d872014-11-14 17:24:33 +00001257 SKL_DPLL0);
1258 break;
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301259 case 135000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001260 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
Damien Lespiau5416d872014-11-14 17:24:33 +00001261 SKL_DPLL0);
1262 break;
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301263 case 270000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001264 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
Damien Lespiau5416d872014-11-14 17:24:33 +00001265 SKL_DPLL0);
1266 break;
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301267 case 162000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001268 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301269 SKL_DPLL0);
1270 break;
1271 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1272 results in CDCLK change. Need to handle the change of CDCLK by
1273 disabling pipes and re-enabling them */
1274 case 108000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001275 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301276 SKL_DPLL0);
1277 break;
1278 case 216000:
Damien Lespiau71cd8422015-04-30 16:39:17 +01001279 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
Sonika Jindalc3346ef2015-02-21 11:12:13 +05301280 SKL_DPLL0);
1281 break;
1282
Damien Lespiau5416d872014-11-14 17:24:33 +00001283 }
1284 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1285}
1286
Ander Conselvan de Oliveira6fa2d192015-08-31 11:23:28 +03001287void
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001288hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
Daniel Vetter0e503382014-07-04 11:26:04 -03001289{
Ander Conselvan de Oliveiraee46f3c72015-06-30 16:10:38 +03001290 memset(&pipe_config->dpll_hw_state, 0,
1291 sizeof(pipe_config->dpll_hw_state));
1292
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001293 switch (pipe_config->port_clock / 2) {
1294 case 81000:
Daniel Vetter0e503382014-07-04 11:26:04 -03001295 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1296 break;
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001297 case 135000:
Daniel Vetter0e503382014-07-04 11:26:04 -03001298 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1299 break;
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001300 case 270000:
Daniel Vetter0e503382014-07-04 11:26:04 -03001301 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1302 break;
1303 }
1304}
1305
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05301306static int
Ville Syrjälä12f6a2e2015-03-12 17:10:30 +02001307intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05301308{
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001309 if (intel_dp->num_sink_rates) {
1310 *sink_rates = intel_dp->sink_rates;
1311 return intel_dp->num_sink_rates;
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05301312 }
Ville Syrjälä12f6a2e2015-03-12 17:10:30 +02001313
1314 *sink_rates = default_rates;
1315
1316 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05301317}
1318
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001319bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
Thulasimani,Sivakumared63baa2015-08-18 15:30:37 +05301320{
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001321 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1322 struct drm_device *dev = dig_port->base.base.dev;
1323
Thulasimani,Sivakumared63baa2015-08-18 15:30:37 +05301324 /* WaDisableHBR2:skl */
Jani Nikulae87a0052015-10-20 15:22:02 +03001325 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
Thulasimani,Sivakumared63baa2015-08-18 15:30:37 +05301326 return false;
1327
1328 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1329 (INTEL_INFO(dev)->gen >= 9))
1330 return true;
1331 else
1332 return false;
1333}
1334
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301335static int
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001336intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301337{
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001338 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1339 struct drm_device *dev = dig_port->base.base.dev;
Thulasimani,Sivakumaraf7080f2015-08-18 11:07:59 +05301340 int size;
1341
Sonika Jindal64987fc2015-05-26 17:50:13 +05301342 if (IS_BROXTON(dev)) {
1343 *source_rates = bxt_rates;
Thulasimani,Sivakumaraf7080f2015-08-18 11:07:59 +05301344 size = ARRAY_SIZE(bxt_rates);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001345 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Sonika Jindal637a9c62015-05-07 09:52:08 +05301346 *source_rates = skl_rates;
Thulasimani,Sivakumaraf7080f2015-08-18 11:07:59 +05301347 size = ARRAY_SIZE(skl_rates);
1348 } else {
1349 *source_rates = default_rates;
1350 size = ARRAY_SIZE(default_rates);
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301351 }
Ville Syrjälä636280b2015-03-12 17:10:29 +02001352
Thulasimani,Sivakumared63baa2015-08-18 15:30:37 +05301353 /* This depends on the fact that 5.4 is last value in the array */
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001354 if (!intel_dp_source_supports_hbr2(intel_dp))
Thulasimani,Sivakumaraf7080f2015-08-18 11:07:59 +05301355 size--;
Ville Syrjälä636280b2015-03-12 17:10:29 +02001356
Thulasimani,Sivakumaraf7080f2015-08-18 11:07:59 +05301357 return size;
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301358}
1359
Daniel Vetter0e503382014-07-04 11:26:04 -03001360static void
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001361intel_dp_set_clock(struct intel_encoder *encoder,
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001362 struct intel_crtc_state *pipe_config)
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001363{
1364 struct drm_device *dev = encoder->base.dev;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +08001365 const struct dp_link_dpll *divisor = NULL;
1366 int i, count = 0;
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001367
1368 if (IS_G4X(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +08001369 divisor = gen4_dpll;
1370 count = ARRAY_SIZE(gen4_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001371 } else if (HAS_PCH_SPLIT(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +08001372 divisor = pch_dpll;
1373 count = ARRAY_SIZE(pch_dpll);
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001374 } else if (IS_CHERRYVIEW(dev)) {
1375 divisor = chv_dpll;
1376 count = ARRAY_SIZE(chv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001377 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +08001378 divisor = vlv_dpll;
1379 count = ARRAY_SIZE(vlv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001380 }
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +08001381
1382 if (divisor && count) {
1383 for (i = 0; i < count; i++) {
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001384 if (pipe_config->port_clock == divisor[i].clock) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +08001385 pipe_config->dpll = divisor[i].dpll;
1386 pipe_config->clock_set = true;
1387 break;
1388 }
1389 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001390 }
1391}
1392
Ville Syrjälä2ecae762015-03-12 17:10:33 +02001393static int intersect_rates(const int *source_rates, int source_len,
1394 const int *sink_rates, int sink_len,
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001395 int *common_rates)
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301396{
1397 int i = 0, j = 0, k = 0;
1398
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301399 while (i < source_len && j < sink_len) {
1400 if (source_rates[i] == sink_rates[j]) {
Ville Syrjäläe6bda3e2015-03-12 17:10:37 +02001401 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1402 return k;
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001403 common_rates[k] = source_rates[i];
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301404 ++k;
1405 ++i;
1406 ++j;
1407 } else if (source_rates[i] < sink_rates[j]) {
1408 ++i;
1409 } else {
1410 ++j;
1411 }
1412 }
1413 return k;
1414}
1415
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001416static int intel_dp_common_rates(struct intel_dp *intel_dp,
1417 int *common_rates)
Ville Syrjälä2ecae762015-03-12 17:10:33 +02001418{
Ville Syrjälä2ecae762015-03-12 17:10:33 +02001419 const int *source_rates, *sink_rates;
1420 int source_len, sink_len;
1421
1422 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001423 source_len = intel_dp_source_rates(intel_dp, &source_rates);
Ville Syrjälä2ecae762015-03-12 17:10:33 +02001424
1425 return intersect_rates(source_rates, source_len,
1426 sink_rates, sink_len,
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001427 common_rates);
Ville Syrjälä2ecae762015-03-12 17:10:33 +02001428}
1429
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001430static void snprintf_int_array(char *str, size_t len,
1431 const int *array, int nelem)
1432{
1433 int i;
1434
1435 str[0] = '\0';
1436
1437 for (i = 0; i < nelem; i++) {
Jani Nikulab2f505b2015-05-18 16:01:45 +03001438 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001439 if (r >= len)
1440 return;
1441 str += r;
1442 len -= r;
1443 }
1444}
1445
1446static void intel_dp_print_rates(struct intel_dp *intel_dp)
1447{
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001448 const int *source_rates, *sink_rates;
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001449 int source_len, sink_len, common_len;
1450 int common_rates[DP_MAX_SUPPORTED_RATES];
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001451 char str[128]; /* FIXME: too big for stack? */
1452
1453 if ((drm_debug & DRM_UT_KMS) == 0)
1454 return;
1455
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001456 source_len = intel_dp_source_rates(intel_dp, &source_rates);
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001457 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1458 DRM_DEBUG_KMS("source rates: %s\n", str);
1459
1460 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1461 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1462 DRM_DEBUG_KMS("sink rates: %s\n", str);
1463
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001464 common_len = intel_dp_common_rates(intel_dp, common_rates);
1465 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1466 DRM_DEBUG_KMS("common rates: %s\n", str);
Ville Syrjälä0336400e2015-03-12 17:10:39 +02001467}
1468
Ville Syrjäläf4896f12015-03-12 17:10:27 +02001469static int rate_to_index(int find, const int *rates)
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301470{
1471 int i = 0;
1472
1473 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1474 if (find == rates[i])
1475 break;
1476
1477 return i;
1478}
1479
Ville Syrjälä50fec212015-03-12 17:10:34 +02001480int
1481intel_dp_max_link_rate(struct intel_dp *intel_dp)
1482{
1483 int rates[DP_MAX_SUPPORTED_RATES] = {};
1484 int len;
1485
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001486 len = intel_dp_common_rates(intel_dp, rates);
Ville Syrjälä50fec212015-03-12 17:10:34 +02001487 if (WARN_ON(len <= 0))
1488 return 162000;
1489
1490 return rates[rate_to_index(0, rates) - 1];
1491}
1492
Ville Syrjäläed4e9c12015-03-12 17:10:36 +02001493int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1494{
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001495 return rate_to_index(rate, intel_dp->sink_rates);
Ville Syrjäläed4e9c12015-03-12 17:10:36 +02001496}
1497
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03001498void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1499 uint8_t *link_bw, uint8_t *rate_select)
Ville Syrjälä04a60f92015-07-06 15:10:06 +03001500{
1501 if (intel_dp->num_sink_rates) {
1502 *link_bw = 0;
1503 *rate_select =
1504 intel_dp_rate_select(intel_dp, port_clock);
1505 } else {
1506 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1507 *rate_select = 0;
1508 }
1509}
1510
Paulo Zanoni00c09d72012-10-26 19:05:52 -02001511bool
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001512intel_dp_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001513 struct intel_crtc_state *pipe_config)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001514{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001515 struct drm_device *dev = encoder->base.dev;
Daniel Vetter36008362013-03-27 00:44:59 +01001516 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02001517 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001518 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001519 enum port port = dp_to_dig_port(intel_dp)->port;
Ander Conselvan de Oliveira84556d52015-03-20 16:18:10 +02001520 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
Jani Nikuladd06f902012-10-19 14:51:50 +03001521 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001522 int lane_count, clock;
Jani Nikula56071a22014-05-06 14:56:52 +03001523 int min_lane_count = 1;
Paulo Zanonieeb63242014-05-06 14:56:50 +03001524 int max_lane_count = intel_dp_max_lane_count(intel_dp);
Todd Previte06ea66b2014-01-20 10:19:39 -07001525 /* Conveniently, the link BW constants become indices with a shift...*/
Jani Nikula56071a22014-05-06 14:56:52 +03001526 int min_clock = 0;
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301527 int max_clock;
Daniel Vetter083f9562012-04-20 20:23:49 +02001528 int bpp, mode_rate;
Daniel Vetterff9a6752013-06-01 17:16:21 +02001529 int link_avail, link_clock;
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001530 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1531 int common_len;
Ville Syrjälä04a60f92015-07-06 15:10:06 +03001532 uint8_t link_bw, rate_select;
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301533
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001534 common_len = intel_dp_common_rates(intel_dp, common_rates);
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301535
1536 /* No common link rates between source and sink */
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001537 WARN_ON(common_len <= 0);
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301538
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001539 max_clock = common_len - 1;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001540
Imre Deakbc7d38a2013-05-16 14:40:36 +03001541 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01001542 pipe_config->has_pch_encoder = true;
1543
Daniel Vetter03afc4a2013-04-02 23:42:31 +02001544 pipe_config->has_dp_encoder = true;
Vandana Kannanf769cd22014-08-05 07:51:22 -07001545 pipe_config->has_drrs = false;
Jani Nikula9fcb1702015-05-05 16:32:12 +03001546 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001547
Jani Nikuladd06f902012-10-19 14:51:50 +03001548 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1549 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1550 adjusted_mode);
Chandra Kondurua1b22782015-04-07 15:28:45 -07001551
1552 if (INTEL_INFO(dev)->gen >= 9) {
1553 int ret;
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02001554 ret = skl_update_scaler_crtc(pipe_config);
Chandra Kondurua1b22782015-04-07 15:28:45 -07001555 if (ret)
1556 return ret;
1557 }
1558
Matt Roperb56676272015-11-04 09:05:27 -08001559 if (HAS_GMCH_DISPLAY(dev))
Jesse Barnes2dd24552013-04-25 12:55:01 -07001560 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1561 intel_connector->panel.fitting_mode);
1562 else
Jesse Barnesb074cec2013-04-25 12:55:02 -07001563 intel_pch_panel_fitting(intel_crtc, pipe_config,
1564 intel_connector->panel.fitting_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +01001565 }
1566
Daniel Vettercb1793c2012-06-04 18:39:21 +02001567 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
Daniel Vetter0af78a22012-05-23 11:30:55 +02001568 return false;
1569
Daniel Vetter083f9562012-04-20 20:23:49 +02001570 DRM_DEBUG_KMS("DP link computation with max lane count %i "
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301571 "max bw %d pixel clock %iKHz\n",
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001572 max_lane_count, common_rates[max_clock],
Damien Lespiau241bfc32013-09-25 16:45:37 +01001573 adjusted_mode->crtc_clock);
Daniel Vetter083f9562012-04-20 20:23:49 +02001574
Daniel Vetter36008362013-03-27 00:44:59 +01001575 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1576 * bpc in between. */
Daniel Vetter3e7ca982013-06-01 19:45:56 +02001577 bpp = pipe_config->pipe_bpp;
Jani Nikula56071a22014-05-06 14:56:52 +03001578 if (is_edp(intel_dp)) {
Thulasimani,Sivakumar22ce5622015-07-31 11:05:27 +05301579
1580 /* Get bpp from vbt only for panels that dont have bpp in edid */
1581 if (intel_connector->base.display_info.bpc == 0 &&
1582 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
Jani Nikula56071a22014-05-06 14:56:52 +03001583 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1584 dev_priv->vbt.edp_bpp);
1585 bpp = dev_priv->vbt.edp_bpp;
1586 }
1587
Jani Nikula344c5bb2014-09-09 11:25:13 +03001588 /*
1589 * Use the maximum clock and number of lanes the eDP panel
1590 * advertizes being capable of. The panels are generally
1591 * designed to support only a single clock and lane
1592 * configuration, and typically these values correspond to the
1593 * native resolution of the panel.
1594 */
1595 min_lane_count = max_lane_count;
1596 min_clock = max_clock;
Imre Deak79842112013-07-18 17:44:13 +03001597 }
Daniel Vetter657445f2013-05-04 10:09:18 +02001598
Daniel Vetter36008362013-03-27 00:44:59 +01001599 for (; bpp >= 6*3; bpp -= 2*3) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01001600 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1601 bpp);
Daniel Vetterc4867932012-04-10 10:42:36 +02001602
Dave Airliec6930992014-07-14 11:04:39 +10001603 for (clock = min_clock; clock <= max_clock; clock++) {
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301604 for (lane_count = min_lane_count;
1605 lane_count <= max_lane_count;
1606 lane_count <<= 1) {
1607
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001608 link_clock = common_rates[clock];
Daniel Vetter36008362013-03-27 00:44:59 +01001609 link_avail = intel_dp_max_data_rate(link_clock,
1610 lane_count);
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02001611
Daniel Vetter36008362013-03-27 00:44:59 +01001612 if (mode_rate <= link_avail) {
1613 goto found;
1614 }
1615 }
1616 }
1617 }
1618
1619 return false;
1620
1621found:
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001622 if (intel_dp->color_range_auto) {
1623 /*
1624 * See:
1625 * CEA-861-E - 5.1 Default Encoding Parameters
1626 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1627 */
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001628 pipe_config->limited_color_range =
1629 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1630 } else {
1631 pipe_config->limited_color_range =
1632 intel_dp->limited_color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02001633 }
1634
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001635 pipe_config->lane_count = lane_count;
Sonika Jindala8f3ef62015-03-05 10:02:30 +05301636
Daniel Vetter657445f2013-05-04 10:09:18 +02001637 pipe_config->pipe_bpp = bpp;
Ville Syrjälä94ca7192015-03-13 19:40:31 +02001638 pipe_config->port_clock = common_rates[clock];
Daniel Vetterc4867932012-04-10 10:42:36 +02001639
Ville Syrjälä04a60f92015-07-06 15:10:06 +03001640 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1641 &link_bw, &rate_select);
1642
1643 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1644 link_bw, rate_select, pipe_config->lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +02001645 pipe_config->port_clock, bpp);
Daniel Vetter36008362013-03-27 00:44:59 +01001646 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1647 mode_rate, link_avail);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001648
Daniel Vetter03afc4a2013-04-02 23:42:31 +02001649 intel_link_compute_m_n(bpp, lane_count,
Damien Lespiau241bfc32013-09-25 16:45:37 +01001650 adjusted_mode->crtc_clock,
1651 pipe_config->port_clock,
Daniel Vetter03afc4a2013-04-02 23:42:31 +02001652 &pipe_config->dp_m_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001653
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301654 if (intel_connector->panel.downclock_mode != NULL &&
Vandana Kannan96178ee2015-01-10 02:25:56 +05301655 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
Vandana Kannanf769cd22014-08-05 07:51:22 -07001656 pipe_config->has_drrs = true;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301657 intel_link_compute_m_n(bpp, lane_count,
1658 intel_connector->panel.downclock_mode->clock,
1659 pipe_config->port_clock,
1660 &pipe_config->dp_m2_n2);
1661 }
1662
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07001663 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001664 skl_edp_set_pll_config(pipe_config);
Satheeshakrishna M977bb382014-08-22 09:49:12 +05301665 else if (IS_BROXTON(dev))
1666 /* handled in ddi */;
Damien Lespiau5416d872014-11-14 17:24:33 +00001667 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001668 hsw_dp_set_ddi_pll_sel(pipe_config);
Daniel Vetter0e503382014-07-04 11:26:04 -03001669 else
Ville Syrjälä840b32b2015-08-11 20:21:46 +03001670 intel_dp_set_clock(encoder, pipe_config);
Daniel Vetterc6bb3532013-04-19 11:14:33 +02001671
Daniel Vetter36008362013-03-27 00:44:59 +01001672 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001673}
1674
Ville Syrjälä901c2da2015-08-17 18:05:12 +03001675void intel_dp_set_link_params(struct intel_dp *intel_dp,
1676 const struct intel_crtc_state *pipe_config)
1677{
1678 intel_dp->link_rate = pipe_config->port_clock;
1679 intel_dp->lane_count = pipe_config->lane_count;
1680}
1681
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02001682static void intel_dp_prepare(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001683{
Daniel Vetterb934223d2013-07-21 21:37:05 +02001684 struct drm_device *dev = encoder->base.dev;
Keith Packard417e8222011-11-01 19:54:11 -07001685 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb934223d2013-07-21 21:37:05 +02001686 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001687 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetterb934223d2013-07-21 21:37:05 +02001688 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03001689 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001690
Ville Syrjälä901c2da2015-08-17 18:05:12 +03001691 intel_dp_set_link_params(intel_dp, crtc->config);
1692
Keith Packard417e8222011-11-01 19:54:11 -07001693 /*
Keith Packard1a2eb462011-11-16 16:26:07 -08001694 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -07001695 *
1696 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -08001697 * SNB CPU
1698 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -07001699 * CPT PCH
1700 *
1701 * IBX PCH and CPU are the same for almost everything,
1702 * except that the CPU DP PLL is configured in this
1703 * register
1704 *
1705 * CPT PCH is quite different, having many bits moved
1706 * to the TRANS_DP_CTL register instead. That
1707 * configuration happens (oddly) in ironlake_pch_enable
1708 */
Adam Jackson9c9e7922010-04-05 17:57:59 -04001709
Keith Packard417e8222011-11-01 19:54:11 -07001710 /* Preserve the BIOS-computed detected bit. This is
1711 * supposed to be read-only.
1712 */
1713 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001714
Keith Packard417e8222011-11-01 19:54:11 -07001715 /* Handle DP bits in common between all three register formats */
Keith Packard417e8222011-11-01 19:54:11 -07001716 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03001717 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001718
Keith Packard417e8222011-11-01 19:54:11 -07001719 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001720
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001721 if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08001722 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1723 intel_dp->DP |= DP_SYNC_HS_HIGH;
1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1725 intel_dp->DP |= DP_SYNC_VS_HIGH;
1726 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1727
Jani Nikula6aba5b62013-10-04 15:08:10 +03001728 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard1a2eb462011-11-16 16:26:07 -08001729 intel_dp->DP |= DP_ENHANCED_FRAMING;
1730
Daniel Vetter7c62a162013-06-01 17:16:20 +02001731 intel_dp->DP |= crtc->pipe << 29;
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001732 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
Ville Syrjäläe3ef4472015-05-05 17:17:31 +03001733 u32 trans_dp;
1734
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001735 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Ville Syrjäläe3ef4472015-05-05 17:17:31 +03001736
1737 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1738 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1739 trans_dp |= TRANS_DP_ENH_FRAMING;
1740 else
1741 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1742 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001743 } else {
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001744 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
Wayne Boyer666a4532015-12-09 12:29:35 -08001745 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03001746 intel_dp->DP |= DP_COLOR_RANGE_16_235;
Keith Packard417e8222011-11-01 19:54:11 -07001747
1748 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1749 intel_dp->DP |= DP_SYNC_HS_HIGH;
1750 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1751 intel_dp->DP |= DP_SYNC_VS_HIGH;
1752 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1753
Jani Nikula6aba5b62013-10-04 15:08:10 +03001754 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard417e8222011-11-01 19:54:11 -07001755 intel_dp->DP |= DP_ENHANCED_FRAMING;
1756
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001757 if (IS_CHERRYVIEW(dev))
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001758 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03001759 else if (crtc->pipe == PIPE_B)
1760 intel_dp->DP |= DP_PIPEB_SELECT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001761 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001762}
1763
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001764#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1765#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001766
Paulo Zanoni1a5ef5b2013-12-19 14:29:43 -02001767#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1768#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
Keith Packard99ea7122011-11-01 19:57:50 -07001769
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001770#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1771#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001772
Daniel Vetter4be73782014-01-17 14:39:48 +01001773static void wait_panel_status(struct intel_dp *intel_dp,
Keith Packard99ea7122011-11-01 19:57:50 -07001774 u32 mask,
1775 u32 value)
1776{
Paulo Zanoni30add222012-10-26 19:05:45 -02001777 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001778 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001779 i915_reg_t pp_stat_reg, pp_ctrl_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07001780
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001781 lockdep_assert_held(&dev_priv->pps_mutex);
1782
Jani Nikulabf13e812013-09-06 07:40:05 +03001783 pp_stat_reg = _pp_stat_reg(intel_dp);
1784 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001785
1786 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001787 mask, value,
1788 I915_READ(pp_stat_reg),
1789 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001790
Jesse Barnes453c5422013-03-28 09:55:41 -07001791 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001792 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001793 I915_READ(pp_stat_reg),
1794 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001795 }
Chris Wilson54c136d2013-12-02 09:57:16 +00001796
1797 DRM_DEBUG_KMS("Wait complete\n");
Keith Packard99ea7122011-11-01 19:57:50 -07001798}
1799
Daniel Vetter4be73782014-01-17 14:39:48 +01001800static void wait_panel_on(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001801{
1802 DRM_DEBUG_KMS("Wait for panel power on\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001803 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001804}
1805
Daniel Vetter4be73782014-01-17 14:39:48 +01001806static void wait_panel_off(struct intel_dp *intel_dp)
Keith Packardbd943152011-09-18 23:09:52 -07001807{
Keith Packardbd943152011-09-18 23:09:52 -07001808 DRM_DEBUG_KMS("Wait for panel power off time\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001809 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -07001810}
Keith Packardbd943152011-09-18 23:09:52 -07001811
Daniel Vetter4be73782014-01-17 14:39:48 +01001812static void wait_panel_power_cycle(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001813{
1814 DRM_DEBUG_KMS("Wait for panel power cycle\n");
Paulo Zanonidce56b32013-12-19 14:29:40 -02001815
1816 /* When we disable the VDD override bit last we have to do the manual
1817 * wait. */
1818 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1819 intel_dp->panel_power_cycle_delay);
1820
Daniel Vetter4be73782014-01-17 14:39:48 +01001821 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001822}
Keith Packardbd943152011-09-18 23:09:52 -07001823
Daniel Vetter4be73782014-01-17 14:39:48 +01001824static void wait_backlight_on(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001825{
1826 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1827 intel_dp->backlight_on_delay);
1828}
1829
Daniel Vetter4be73782014-01-17 14:39:48 +01001830static void edp_wait_backlight_off(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001831{
1832 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1833 intel_dp->backlight_off_delay);
1834}
Keith Packard99ea7122011-11-01 19:57:50 -07001835
Keith Packard832dd3c2011-11-01 19:34:06 -07001836/* Read the current pp_control value, unlocking the register if it
1837 * is locked
1838 */
1839
Jesse Barnes453c5422013-03-28 09:55:41 -07001840static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
Keith Packard832dd3c2011-11-01 19:34:06 -07001841{
Jesse Barnes453c5422013-03-28 09:55:41 -07001842 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844 u32 control;
Jesse Barnes453c5422013-03-28 09:55:41 -07001845
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001846 lockdep_assert_held(&dev_priv->pps_mutex);
1847
Jani Nikulabf13e812013-09-06 07:40:05 +03001848 control = I915_READ(_pp_ctrl_reg(intel_dp));
Vandana Kannanb0a08be2015-06-18 11:00:55 +05301849 if (!IS_BROXTON(dev)) {
1850 control &= ~PANEL_UNLOCK_MASK;
1851 control |= PANEL_UNLOCK_REGS;
1852 }
Keith Packard832dd3c2011-11-01 19:34:06 -07001853 return control;
Keith Packardbd943152011-09-18 23:09:52 -07001854}
1855
Ville Syrjälä951468f2014-09-04 14:55:31 +03001856/*
1857 * Must be paired with edp_panel_vdd_off().
1858 * Must hold pps_mutex around the whole on/off sequence.
1859 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1860 */
Ville Syrjälä1e0560e2014-08-19 13:24:25 +03001861static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001862{
Paulo Zanoni30add222012-10-26 19:05:45 -02001863 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001864 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1865 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jesse Barnes5d613502011-01-24 17:10:54 -08001866 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001867 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001868 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001869 i915_reg_t pp_stat_reg, pp_ctrl_reg;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001870 bool need_to_disable = !intel_dp->want_panel_vdd;
Jesse Barnes5d613502011-01-24 17:10:54 -08001871
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001872 lockdep_assert_held(&dev_priv->pps_mutex);
1873
Keith Packard97af61f572011-09-28 16:23:51 -07001874 if (!is_edp(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001875 return false;
Keith Packardbd943152011-09-18 23:09:52 -07001876
Egbert Eich2c623c12014-11-25 12:54:57 +01001877 cancel_delayed_work(&intel_dp->panel_vdd_work);
Keith Packardbd943152011-09-18 23:09:52 -07001878 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -07001879
Daniel Vetter4be73782014-01-17 14:39:48 +01001880 if (edp_have_panel_vdd(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001881 return need_to_disable;
Paulo Zanonib0665d52013-10-30 19:50:27 -02001882
Ville Syrjälä25f78f52015-11-16 15:01:04 +01001883 power_domain = intel_display_port_aux_power_domain(intel_encoder);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001884 intel_display_power_get(dev_priv, power_domain);
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001885
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03001886 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1887 port_name(intel_dig_port->port));
Keith Packardbd943152011-09-18 23:09:52 -07001888
Daniel Vetter4be73782014-01-17 14:39:48 +01001889 if (!edp_have_panel_power(intel_dp))
1890 wait_panel_power_cycle(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001891
Jesse Barnes453c5422013-03-28 09:55:41 -07001892 pp = ironlake_get_pp_control(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001893 pp |= EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -07001894
Jani Nikulabf13e812013-09-06 07:40:05 +03001895 pp_stat_reg = _pp_stat_reg(intel_dp);
1896 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001897
1898 I915_WRITE(pp_ctrl_reg, pp);
1899 POSTING_READ(pp_ctrl_reg);
1900 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1901 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packardebf33b12011-09-29 15:53:27 -07001902 /*
1903 * If the panel wasn't on, delay before accessing aux channel
1904 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001905 if (!edp_have_panel_power(intel_dp)) {
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03001906 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1907 port_name(intel_dig_port->port));
Keith Packardf01eca22011-09-28 16:48:10 -07001908 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001909 }
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001910
1911 return need_to_disable;
1912}
1913
Ville Syrjälä951468f2014-09-04 14:55:31 +03001914/*
1915 * Must be paired with intel_edp_panel_vdd_off() or
1916 * intel_edp_panel_off().
1917 * Nested calls to these functions are not allowed since
1918 * we drop the lock. Caller must use some higher level
1919 * locking to prevent nested calls from other threads.
1920 */
Daniel Vetterb80d6c72014-03-19 15:54:37 +01001921void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001922{
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001923 bool vdd;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001924
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001925 if (!is_edp(intel_dp))
1926 return;
1927
Ville Syrjälä773538e82014-09-04 14:54:56 +03001928 pps_lock(intel_dp);
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001929 vdd = edp_panel_vdd_on(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03001930 pps_unlock(intel_dp);
Ville Syrjäläc695b6b2014-08-18 22:16:03 +03001931
Rob Clarke2c719b2014-12-15 13:56:32 -05001932 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03001933 port_name(dp_to_dig_port(intel_dp)->port));
Jesse Barnes5d613502011-01-24 17:10:54 -08001934}
1935
Daniel Vetter4be73782014-01-17 14:39:48 +01001936static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001937{
Paulo Zanoni30add222012-10-26 19:05:45 -02001938 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001939 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001940 struct intel_digital_port *intel_dig_port =
1941 dp_to_dig_port(intel_dp);
1942 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1943 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001944 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001945 i915_reg_t pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001946
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001947 lockdep_assert_held(&dev_priv->pps_mutex);
Daniel Vettera0e99e62012-12-02 01:05:46 +01001948
Ville Syrjälä15e899a2014-08-18 22:16:02 +03001949 WARN_ON(intel_dp->want_panel_vdd);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001950
Ville Syrjälä15e899a2014-08-18 22:16:02 +03001951 if (!edp_have_panel_vdd(intel_dp))
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001952 return;
Paulo Zanonib0665d52013-10-30 19:50:27 -02001953
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03001954 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1955 port_name(intel_dig_port->port));
Jesse Barnes453c5422013-03-28 09:55:41 -07001956
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001957 pp = ironlake_get_pp_control(intel_dp);
1958 pp &= ~EDP_FORCE_VDD;
Jesse Barnes453c5422013-03-28 09:55:41 -07001959
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001960 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1961 pp_stat_reg = _pp_stat_reg(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001962
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001963 I915_WRITE(pp_ctrl_reg, pp);
1964 POSTING_READ(pp_ctrl_reg);
Paulo Zanoni90791a52013-12-06 17:32:42 -02001965
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001966 /* Make sure sequencer is idle before allowing subsequent activity */
1967 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1968 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001969
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001970 if ((pp & POWER_TARGET_ON) == 0)
1971 intel_dp->last_power_cycle = jiffies;
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001972
Ville Syrjälä25f78f52015-11-16 15:01:04 +01001973 power_domain = intel_display_port_aux_power_domain(intel_encoder);
Ville Syrjäläbe2c9192014-08-18 22:16:01 +03001974 intel_display_power_put(dev_priv, power_domain);
Keith Packardbd943152011-09-18 23:09:52 -07001975}
1976
Daniel Vetter4be73782014-01-17 14:39:48 +01001977static void edp_panel_vdd_work(struct work_struct *__work)
Keith Packardbd943152011-09-18 23:09:52 -07001978{
1979 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1980 struct intel_dp, panel_vdd_work);
Keith Packardbd943152011-09-18 23:09:52 -07001981
Ville Syrjälä773538e82014-09-04 14:54:56 +03001982 pps_lock(intel_dp);
Ville Syrjälä15e899a2014-08-18 22:16:02 +03001983 if (!intel_dp->want_panel_vdd)
1984 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03001985 pps_unlock(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001986}
1987
Imre Deakaba86892014-07-30 15:57:31 +03001988static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1989{
1990 unsigned long delay;
1991
1992 /*
1993 * Queue the timer to fire a long time from now (relative to the power
1994 * down delay) to keep the panel power up across a sequence of
1995 * operations.
1996 */
1997 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1998 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1999}
2000
Ville Syrjälä951468f2014-09-04 14:55:31 +03002001/*
2002 * Must be paired with edp_panel_vdd_on().
2003 * Must hold pps_mutex around the whole on/off sequence.
2004 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2005 */
Daniel Vetter4be73782014-01-17 14:39:48 +01002006static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
Keith Packardbd943152011-09-18 23:09:52 -07002007{
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002008 struct drm_i915_private *dev_priv =
2009 intel_dp_to_dev(intel_dp)->dev_private;
2010
2011 lockdep_assert_held(&dev_priv->pps_mutex);
2012
Keith Packard97af61f572011-09-28 16:23:51 -07002013 if (!is_edp(intel_dp))
2014 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08002015
Rob Clarke2c719b2014-12-15 13:56:32 -05002016 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03002017 port_name(dp_to_dig_port(intel_dp)->port));
Keith Packardf2e8b182011-11-01 20:01:35 -07002018
Keith Packardbd943152011-09-18 23:09:52 -07002019 intel_dp->want_panel_vdd = false;
2020
Imre Deakaba86892014-07-30 15:57:31 +03002021 if (sync)
Daniel Vetter4be73782014-01-17 14:39:48 +01002022 edp_panel_vdd_off_sync(intel_dp);
Imre Deakaba86892014-07-30 15:57:31 +03002023 else
2024 edp_panel_vdd_schedule_off(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08002025}
2026
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002027static void edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07002028{
Paulo Zanoni30add222012-10-26 19:05:45 -02002029 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07002030 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07002031 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002032 i915_reg_t pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07002033
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002034 lockdep_assert_held(&dev_priv->pps_mutex);
2035
Keith Packard97af61f572011-09-28 16:23:51 -07002036 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07002037 return;
Keith Packard99ea7122011-11-01 19:57:50 -07002038
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03002039 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2040 port_name(dp_to_dig_port(intel_dp)->port));
Keith Packard99ea7122011-11-01 19:57:50 -07002041
Ville Syrjäläe7a89ac2014-10-16 21:30:07 +03002042 if (WARN(edp_have_panel_power(intel_dp),
2043 "eDP port %c panel power already on\n",
2044 port_name(dp_to_dig_port(intel_dp)->port)))
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002045 return;
Jesse Barnes9934c132010-07-22 13:18:19 -07002046
Daniel Vetter4be73782014-01-17 14:39:48 +01002047 wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07002048
Jani Nikulabf13e812013-09-06 07:40:05 +03002049 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07002050 pp = ironlake_get_pp_control(intel_dp);
Keith Packard05ce1a42011-09-29 16:33:01 -07002051 if (IS_GEN5(dev)) {
2052 /* ILK workaround: disable reset around power sequence */
2053 pp &= ~PANEL_POWER_RESET;
Jani Nikulabf13e812013-09-06 07:40:05 +03002054 I915_WRITE(pp_ctrl_reg, pp);
2055 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07002056 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07002057
Keith Packard1c0ae802011-09-19 13:59:29 -07002058 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07002059 if (!IS_GEN5(dev))
2060 pp |= PANEL_POWER_RESET;
2061
Jesse Barnes453c5422013-03-28 09:55:41 -07002062 I915_WRITE(pp_ctrl_reg, pp);
2063 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07002064
Daniel Vetter4be73782014-01-17 14:39:48 +01002065 wait_panel_on(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02002066 intel_dp->last_power_on = jiffies;
Jesse Barnes9934c132010-07-22 13:18:19 -07002067
Keith Packard05ce1a42011-09-29 16:33:01 -07002068 if (IS_GEN5(dev)) {
2069 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
Jani Nikulabf13e812013-09-06 07:40:05 +03002070 I915_WRITE(pp_ctrl_reg, pp);
2071 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07002072 }
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002073}
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002074
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002075void intel_edp_panel_on(struct intel_dp *intel_dp)
2076{
2077 if (!is_edp(intel_dp))
2078 return;
2079
2080 pps_lock(intel_dp);
2081 edp_panel_on(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03002082 pps_unlock(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07002083}
2084
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002085
2086static void edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07002087{
Imre Deak4e6e1a52014-03-27 17:45:11 +02002088 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2089 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanoni30add222012-10-26 19:05:45 -02002090 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07002091 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02002092 enum intel_display_power_domain power_domain;
Keith Packard99ea7122011-11-01 19:57:50 -07002093 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002094 i915_reg_t pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07002095
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002096 lockdep_assert_held(&dev_priv->pps_mutex);
2097
Keith Packard97af61f572011-09-28 16:23:51 -07002098 if (!is_edp(intel_dp))
2099 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07002100
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03002101 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2102 port_name(dp_to_dig_port(intel_dp)->port));
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07002103
Ville Syrjälä3936fcf2014-10-16 21:30:02 +03002104 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2105 port_name(dp_to_dig_port(intel_dp)->port));
Jani Nikula24f3e092014-03-17 16:43:36 +02002106
Jesse Barnes453c5422013-03-28 09:55:41 -07002107 pp = ironlake_get_pp_control(intel_dp);
Daniel Vetter35a38552012-08-12 22:17:14 +02002108 /* We need to switch off panel power _and_ force vdd, for otherwise some
2109 * panels get very unhappy and cease to work. */
Patrik Jakobssonb3064152014-03-04 00:42:44 +01002110 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2111 EDP_BLC_ENABLE);
Jesse Barnes453c5422013-03-28 09:55:41 -07002112
Jani Nikulabf13e812013-09-06 07:40:05 +03002113 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07002114
Paulo Zanoni849e39f2014-03-07 20:05:20 -03002115 intel_dp->want_panel_vdd = false;
2116
Jesse Barnes453c5422013-03-28 09:55:41 -07002117 I915_WRITE(pp_ctrl_reg, pp);
2118 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07002119
Paulo Zanonidce56b32013-12-19 14:29:40 -02002120 intel_dp->last_power_cycle = jiffies;
Daniel Vetter4be73782014-01-17 14:39:48 +01002121 wait_panel_off(intel_dp);
Paulo Zanoni849e39f2014-03-07 20:05:20 -03002122
2123 /* We got a reference when we enabled the VDD. */
Ville Syrjälä25f78f52015-11-16 15:01:04 +01002124 power_domain = intel_display_port_aux_power_domain(intel_encoder);
Imre Deak4e6e1a52014-03-27 17:45:11 +02002125 intel_display_power_put(dev_priv, power_domain);
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002126}
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002127
Ville Syrjälä9f0fb5b2014-10-16 21:27:32 +03002128void intel_edp_panel_off(struct intel_dp *intel_dp)
2129{
2130 if (!is_edp(intel_dp))
2131 return;
2132
2133 pps_lock(intel_dp);
2134 edp_panel_off(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03002135 pps_unlock(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07002136}
2137
Jani Nikula1250d102014-08-12 17:11:39 +03002138/* Enable backlight in the panel power control. */
2139static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002140{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002141 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2142 struct drm_device *dev = intel_dig_port->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002145 i915_reg_t pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002146
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002147 /*
2148 * If we enable the backlight right away following a panel power
2149 * on, we may see slight flicker as the panel syncs with the eDP
2150 * link. So delay a bit to make sure the image is solid before
2151 * allowing it to appear.
2152 */
Daniel Vetter4be73782014-01-17 14:39:48 +01002153 wait_backlight_on(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002154
Ville Syrjälä773538e82014-09-04 14:54:56 +03002155 pps_lock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002156
Jesse Barnes453c5422013-03-28 09:55:41 -07002157 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002158 pp |= EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07002159
Jani Nikulabf13e812013-09-06 07:40:05 +03002160 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07002161
2162 I915_WRITE(pp_ctrl_reg, pp);
2163 POSTING_READ(pp_ctrl_reg);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002164
Ville Syrjälä773538e82014-09-04 14:54:56 +03002165 pps_unlock(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002166}
2167
Jani Nikula1250d102014-08-12 17:11:39 +03002168/* Enable backlight PWM and backlight PP control. */
2169void intel_edp_backlight_on(struct intel_dp *intel_dp)
2170{
2171 if (!is_edp(intel_dp))
2172 return;
2173
2174 DRM_DEBUG_KMS("\n");
2175
2176 intel_panel_enable_backlight(intel_dp->attached_connector);
2177 _intel_edp_backlight_on(intel_dp);
2178}
2179
2180/* Disable backlight in the panel power control. */
2181static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002182{
Paulo Zanoni30add222012-10-26 19:05:45 -02002183 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 u32 pp;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002186 i915_reg_t pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002187
Keith Packardf01eca22011-09-28 16:48:10 -07002188 if (!is_edp(intel_dp))
2189 return;
2190
Ville Syrjälä773538e82014-09-04 14:54:56 +03002191 pps_lock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002192
Jesse Barnes453c5422013-03-28 09:55:41 -07002193 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002194 pp &= ~EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07002195
Jani Nikulabf13e812013-09-06 07:40:05 +03002196 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07002197
2198 I915_WRITE(pp_ctrl_reg, pp);
2199 POSTING_READ(pp_ctrl_reg);
Jesse Barnesf7d23232014-03-31 11:13:56 -07002200
Ville Syrjälä773538e82014-09-04 14:54:56 +03002201 pps_unlock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002202
Paulo Zanonidce56b32013-12-19 14:29:40 -02002203 intel_dp->last_backlight_off = jiffies;
Jesse Barnesf7d23232014-03-31 11:13:56 -07002204 edp_wait_backlight_off(intel_dp);
Jani Nikula1250d102014-08-12 17:11:39 +03002205}
Jesse Barnesf7d23232014-03-31 11:13:56 -07002206
Jani Nikula1250d102014-08-12 17:11:39 +03002207/* Disable backlight PP control and backlight PWM. */
2208void intel_edp_backlight_off(struct intel_dp *intel_dp)
2209{
2210 if (!is_edp(intel_dp))
2211 return;
2212
2213 DRM_DEBUG_KMS("\n");
2214
2215 _intel_edp_backlight_off(intel_dp);
Jesse Barnesf7d23232014-03-31 11:13:56 -07002216 intel_panel_disable_backlight(intel_dp->attached_connector);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002217}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002218
Jani Nikula73580fb72014-08-12 17:11:41 +03002219/*
2220 * Hook for controlling the panel power control backlight through the bl_power
2221 * sysfs attribute. Take care to handle multiple calls.
2222 */
2223static void intel_edp_backlight_power(struct intel_connector *connector,
2224 bool enable)
2225{
2226 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002227 bool is_enabled;
2228
Ville Syrjälä773538e82014-09-04 14:54:56 +03002229 pps_lock(intel_dp);
Ville Syrjäläe39b9992014-09-04 14:53:14 +03002230 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
Ville Syrjälä773538e82014-09-04 14:54:56 +03002231 pps_unlock(intel_dp);
Jani Nikula73580fb72014-08-12 17:11:41 +03002232
2233 if (is_enabled == enable)
2234 return;
2235
Jani Nikula23ba9372014-08-27 14:08:43 +03002236 DRM_DEBUG_KMS("panel power control backlight %s\n",
2237 enable ? "enable" : "disable");
Jani Nikula73580fb72014-08-12 17:11:41 +03002238
2239 if (enable)
2240 _intel_edp_backlight_on(intel_dp);
2241 else
2242 _intel_edp_backlight_off(intel_dp);
2243}
2244
Ville Syrjälä64e10772015-10-29 21:26:01 +02002245static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2246{
2247 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2248 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2249 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2250
2251 I915_STATE_WARN(cur_state != state,
2252 "DP port %c state assertion failure (expected %s, current %s)\n",
2253 port_name(dig_port->port),
Jani Nikula87ad3212016-01-14 12:53:34 +02002254 onoff(state), onoff(cur_state));
Ville Syrjälä64e10772015-10-29 21:26:01 +02002255}
2256#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2257
2258static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2259{
2260 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2261
2262 I915_STATE_WARN(cur_state != state,
2263 "eDP PLL state assertion failure (expected %s, current %s)\n",
Jani Nikula87ad3212016-01-14 12:53:34 +02002264 onoff(state), onoff(cur_state));
Ville Syrjälä64e10772015-10-29 21:26:01 +02002265}
2266#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2267#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2268
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002269static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07002270{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002271 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Ville Syrjälä64e10772015-10-29 21:26:01 +02002272 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2273 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Jesse Barnesd240f202010-08-13 15:43:26 -07002274
Ville Syrjälä64e10772015-10-29 21:26:01 +02002275 assert_pipe_disabled(dev_priv, crtc->pipe);
2276 assert_dp_port_disabled(intel_dp);
2277 assert_edp_pll_disabled(dev_priv);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002278
Ville Syrjäläabfce942015-10-29 21:26:03 +02002279 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2280 crtc->config->port_clock);
2281
2282 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2283
2284 if (crtc->config->port_clock == 162000)
2285 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2286 else
2287 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2288
2289 I915_WRITE(DP_A, intel_dp->DP);
2290 POSTING_READ(DP_A);
2291 udelay(500);
2292
Daniel Vetter07679352012-09-06 22:15:42 +02002293 intel_dp->DP |= DP_PLL_ENABLE;
Ville Syrjälä6fec7662015-11-10 16:16:17 +02002294
Daniel Vetter07679352012-09-06 22:15:42 +02002295 I915_WRITE(DP_A, intel_dp->DP);
Jesse Barnes298b0b32010-10-07 16:01:24 -07002296 POSTING_READ(DP_A);
2297 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07002298}
2299
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002300static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07002301{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Ville Syrjälä64e10772015-10-29 21:26:01 +02002303 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2304 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Jesse Barnesd240f202010-08-13 15:43:26 -07002305
Ville Syrjälä64e10772015-10-29 21:26:01 +02002306 assert_pipe_disabled(dev_priv, crtc->pipe);
2307 assert_dp_port_disabled(intel_dp);
2308 assert_edp_pll_enabled(dev_priv);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002309
Ville Syrjäläabfce942015-10-29 21:26:03 +02002310 DRM_DEBUG_KMS("disabling eDP PLL\n");
2311
Ville Syrjälä6fec7662015-11-10 16:16:17 +02002312 intel_dp->DP &= ~DP_PLL_ENABLE;
Daniel Vetter07679352012-09-06 22:15:42 +02002313
Ville Syrjälä6fec7662015-11-10 16:16:17 +02002314 I915_WRITE(DP_A, intel_dp->DP);
Chris Wilson1af5fa12010-09-08 21:07:28 +01002315 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07002316 udelay(200);
2317}
2318
Jesse Barnesc7ad3812011-07-07 11:11:03 -07002319/* If the sink supports it, try to set the power state appropriately */
Paulo Zanonic19b0662012-10-15 15:51:41 -03002320void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
Jesse Barnesc7ad3812011-07-07 11:11:03 -07002321{
2322 int ret, i;
2323
2324 /* Should have a valid DPCD by this point */
2325 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2326 return;
2327
2328 if (mode != DRM_MODE_DPMS_ON) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02002329 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2330 DP_SET_POWER_D3);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07002331 } else {
2332 /*
2333 * When turning on, we need to retry for 1ms to give the sink
2334 * time to wake up.
2335 */
2336 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02002337 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2338 DP_SET_POWER_D0);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07002339 if (ret == 1)
2340 break;
2341 msleep(1);
2342 }
2343 }
Jani Nikulaf9cac722014-09-02 16:33:52 +03002344
2345 if (ret != 1)
2346 DRM_DEBUG_KMS("failed to %s sink power state\n",
2347 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
Jesse Barnesc7ad3812011-07-07 11:11:03 -07002348}
2349
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002350static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2351 enum pipe *pipe)
Jesse Barnesd240f202010-08-13 15:43:26 -07002352{
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002354 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002355 struct drm_device *dev = encoder->base.dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak6d129be2014-03-05 16:20:54 +02002357 enum intel_display_power_domain power_domain;
2358 u32 tmp;
2359
2360 power_domain = intel_display_port_power_domain(encoder);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02002361 if (!intel_display_power_is_enabled(dev_priv, power_domain))
Imre Deak6d129be2014-03-05 16:20:54 +02002362 return false;
2363
2364 tmp = I915_READ(intel_dp->output_reg);
Jesse Barnesd240f202010-08-13 15:43:26 -07002365
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002366 if (!(tmp & DP_PORT_EN))
2367 return false;
2368
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002369 if (IS_GEN7(dev) && port == PORT_A) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002370 *pipe = PORT_TO_PIPE_CPT(tmp);
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002371 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
Ville Syrjäläadc289d2015-05-05 17:17:30 +03002372 enum pipe p;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002373
Ville Syrjäläadc289d2015-05-05 17:17:30 +03002374 for_each_pipe(dev_priv, p) {
2375 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2376 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2377 *pipe = p;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002378 return true;
2379 }
2380 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002381
Daniel Vetter4a0833e2012-10-26 10:58:11 +02002382 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002383 i915_mmio_reg_offset(intel_dp->output_reg));
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002384 } else if (IS_CHERRYVIEW(dev)) {
2385 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2386 } else {
2387 *pipe = PORT_TO_PIPE(tmp);
Daniel Vetter4a0833e2012-10-26 10:58:11 +02002388 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02002389
2390 return true;
2391}
2392
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002393static void intel_dp_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02002394 struct intel_crtc_state *pipe_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002395{
2396 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002397 u32 tmp, flags = 0;
Xiong Zhang63000ef2013-06-28 12:59:06 +08002398 struct drm_device *dev = encoder->base.dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 enum port port = dp_to_dig_port(intel_dp)->port;
2401 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä18442d02013-09-13 16:00:08 +03002402 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002403
Daniel Vetter9ed109a2014-04-24 23:54:52 +02002404 tmp = I915_READ(intel_dp->output_reg);
Jani Nikula9fcb1702015-05-05 16:32:12 +03002405
2406 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
Daniel Vetter9ed109a2014-04-24 23:54:52 +02002407
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002408 if (HAS_PCH_CPT(dev) && port != PORT_A) {
Ville Syrjäläb81e34c2015-07-06 15:10:03 +03002409 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2410
2411 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
Xiong Zhang63000ef2013-06-28 12:59:06 +08002412 flags |= DRM_MODE_FLAG_PHSYNC;
2413 else
2414 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002415
Ville Syrjäläb81e34c2015-07-06 15:10:03 +03002416 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
Xiong Zhang63000ef2013-06-28 12:59:06 +08002417 flags |= DRM_MODE_FLAG_PVSYNC;
2418 else
2419 flags |= DRM_MODE_FLAG_NVSYNC;
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002420 } else {
2421 if (tmp & DP_SYNC_HS_HIGH)
2422 flags |= DRM_MODE_FLAG_PHSYNC;
2423 else
2424 flags |= DRM_MODE_FLAG_NHSYNC;
2425
2426 if (tmp & DP_SYNC_VS_HIGH)
2427 flags |= DRM_MODE_FLAG_PVSYNC;
2428 else
2429 flags |= DRM_MODE_FLAG_NVSYNC;
Xiong Zhang63000ef2013-06-28 12:59:06 +08002430 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002431
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02002432 pipe_config->base.adjusted_mode.flags |= flags;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03002433
Ville Syrjälä8c875fc2014-09-12 15:46:29 +03002434 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
Wayne Boyer666a4532015-12-09 12:29:35 -08002435 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
Ville Syrjälä8c875fc2014-09-12 15:46:29 +03002436 pipe_config->limited_color_range = true;
2437
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002438 pipe_config->has_dp_encoder = true;
2439
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03002440 pipe_config->lane_count =
2441 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2442
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03002443 intel_dp_get_m_n(crtc, pipe_config);
2444
Ville Syrjälä18442d02013-09-13 16:00:08 +03002445 if (port == PORT_A) {
Ville Syrjäläb377e0d2015-10-29 21:25:59 +02002446 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03002447 pipe_config->port_clock = 162000;
2448 else
2449 pipe_config->port_clock = 270000;
2450 }
Ville Syrjälä18442d02013-09-13 16:00:08 +03002451
2452 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2453 &pipe_config->dp_m_n);
2454
2455 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2456 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2457
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02002458 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
Daniel Vetter7f16e5c2013-11-04 16:28:47 +01002459
Jani Nikulac6cd2ee2013-10-21 10:52:07 +03002460 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2461 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2462 /*
2463 * This is a big fat ugly hack.
2464 *
2465 * Some machines in UEFI boot mode provide us a VBT that has 18
2466 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2467 * unknown we fail to light up. Yet the same BIOS boots up with
2468 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2469 * max, not what it tells us to use.
2470 *
2471 * Note: This will still be broken if the eDP panel is not lit
2472 * up by the BIOS, and thus we can't get the mode at module
2473 * load.
2474 */
2475 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2476 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2477 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2478 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07002479}
2480
Daniel Vettere8cb4552012-07-01 13:05:48 +02002481static void intel_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002482{
Daniel Vettere8cb4552012-07-01 13:05:48 +02002483 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03002484 struct drm_device *dev = encoder->base.dev;
Jani Nikula495a5bb2014-10-27 16:26:55 +02002485 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2486
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002487 if (crtc->config->has_audio)
Jani Nikula495a5bb2014-10-27 16:26:55 +02002488 intel_audio_codec_disable(encoder);
Daniel Vetter6cb49832012-05-20 17:14:50 +02002489
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002490 if (HAS_PSR(dev) && !HAS_DDI(dev))
2491 intel_psr_disable(intel_dp);
2492
Daniel Vetter6cb49832012-05-20 17:14:50 +02002493 /* Make sure the panel is off before trying to change the mode. But also
2494 * ensure that we have vdd while we switch off the panel. */
Jani Nikula24f3e092014-03-17 16:43:36 +02002495 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01002496 intel_edp_backlight_off(intel_dp);
Jani Nikulafdbc3b12013-11-12 17:10:13 +02002497 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Daniel Vetter4be73782014-01-17 14:39:48 +01002498 intel_edp_panel_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02002499
Ville Syrjälä08aff3f2014-08-18 22:16:09 +03002500 /* disable the port before the pipe on g4x */
2501 if (INTEL_INFO(dev)->gen < 5)
Daniel Vetter37398502012-09-06 22:15:44 +02002502 intel_dp_link_down(intel_dp);
Jesse Barnesd240f202010-08-13 15:43:26 -07002503}
2504
Ville Syrjälä08aff3f2014-08-18 22:16:09 +03002505static void ilk_post_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002506{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002507 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03002508 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002509
Ville Syrjälä49277c32014-03-31 18:21:26 +03002510 intel_dp_link_down(intel_dp);
Ville Syrjäläabfce942015-10-29 21:26:03 +02002511
2512 /* Only ilk+ has port A */
Ville Syrjälä08aff3f2014-08-18 22:16:09 +03002513 if (port == PORT_A)
2514 ironlake_edp_pll_off(intel_dp);
Ville Syrjälä49277c32014-03-31 18:21:26 +03002515}
2516
2517static void vlv_post_disable_dp(struct intel_encoder *encoder)
2518{
2519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520
2521 intel_dp_link_down(intel_dp);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002522}
2523
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03002524static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2525 bool reset)
2526{
2527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2528 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2529 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2530 enum pipe pipe = crtc->pipe;
2531 uint32_t val;
2532
2533 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2534 if (reset)
2535 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2536 else
2537 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2538 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2539
2540 if (crtc->config->lane_count > 2) {
2541 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2542 if (reset)
2543 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2544 else
2545 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2546 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2547 }
2548
2549 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2550 val |= CHV_PCS_REQ_SOFTRESET_EN;
2551 if (reset)
2552 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2553 else
2554 val |= DPIO_PCS_CLK_SOFT_RESET;
2555 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2556
2557 if (crtc->config->lane_count > 2) {
2558 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2559 val |= CHV_PCS_REQ_SOFTRESET_EN;
2560 if (reset)
2561 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2562 else
2563 val |= DPIO_PCS_CLK_SOFT_RESET;
2564 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2565 }
2566}
2567
Ville Syrjälä580d3812014-04-09 13:29:00 +03002568static void chv_post_disable_dp(struct intel_encoder *encoder)
2569{
2570 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Ville Syrjälä580d3812014-04-09 13:29:00 +03002571 struct drm_device *dev = encoder->base.dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä580d3812014-04-09 13:29:00 +03002573
2574 intel_dp_link_down(intel_dp);
2575
Ville Syrjäläa5805162015-05-26 20:42:30 +03002576 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä580d3812014-04-09 13:29:00 +03002577
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03002578 /* Assert data lane reset */
2579 chv_data_lane_soft_reset(encoder, true);
Ville Syrjälä580d3812014-04-09 13:29:00 +03002580
Ville Syrjäläa5805162015-05-26 20:42:30 +03002581 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä580d3812014-04-09 13:29:00 +03002582}
2583
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002584static void
2585_intel_dp_set_link_train(struct intel_dp *intel_dp,
2586 uint32_t *DP,
2587 uint8_t dp_train_pat)
2588{
2589 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2590 struct drm_device *dev = intel_dig_port->base.base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 enum port port = intel_dig_port->port;
2593
2594 if (HAS_DDI(dev)) {
2595 uint32_t temp = I915_READ(DP_TP_CTL(port));
2596
2597 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2598 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2599 else
2600 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2601
2602 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2603 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2604 case DP_TRAINING_PATTERN_DISABLE:
2605 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2606
2607 break;
2608 case DP_TRAINING_PATTERN_1:
2609 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2610 break;
2611 case DP_TRAINING_PATTERN_2:
2612 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2613 break;
2614 case DP_TRAINING_PATTERN_3:
2615 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2616 break;
2617 }
2618 I915_WRITE(DP_TP_CTL(port), temp);
2619
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03002620 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2621 (HAS_PCH_CPT(dev) && port != PORT_A)) {
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002622 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2623
2624 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2625 case DP_TRAINING_PATTERN_DISABLE:
2626 *DP |= DP_LINK_TRAIN_OFF_CPT;
2627 break;
2628 case DP_TRAINING_PATTERN_1:
2629 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2630 break;
2631 case DP_TRAINING_PATTERN_2:
2632 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2633 break;
2634 case DP_TRAINING_PATTERN_3:
2635 DRM_ERROR("DP training pattern 3 not supported\n");
2636 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2637 break;
2638 }
2639
2640 } else {
2641 if (IS_CHERRYVIEW(dev))
2642 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2643 else
2644 *DP &= ~DP_LINK_TRAIN_MASK;
2645
2646 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2647 case DP_TRAINING_PATTERN_DISABLE:
2648 *DP |= DP_LINK_TRAIN_OFF;
2649 break;
2650 case DP_TRAINING_PATTERN_1:
2651 *DP |= DP_LINK_TRAIN_PAT_1;
2652 break;
2653 case DP_TRAINING_PATTERN_2:
2654 *DP |= DP_LINK_TRAIN_PAT_2;
2655 break;
2656 case DP_TRAINING_PATTERN_3:
2657 if (IS_CHERRYVIEW(dev)) {
2658 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2659 } else {
2660 DRM_ERROR("DP training pattern 3 not supported\n");
2661 *DP |= DP_LINK_TRAIN_PAT_2;
2662 }
2663 break;
2664 }
2665 }
2666}
2667
2668static void intel_dp_enable_port(struct intel_dp *intel_dp)
2669{
2670 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2671 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä6fec7662015-11-10 16:16:17 +02002672 struct intel_crtc *crtc =
2673 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002674
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002675 /* enable with pattern 1 (as per spec) */
2676 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2677 DP_TRAINING_PATTERN_1);
2678
2679 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2680 POSTING_READ(intel_dp->output_reg);
Ville Syrjälä7b713f52014-10-16 21:27:35 +03002681
2682 /*
2683 * Magic for VLV/CHV. We _must_ first set up the register
2684 * without actually enabling the port, and then do another
2685 * write to enable the port. Otherwise link training will
2686 * fail when the power sequencer is freshly used for this port.
2687 */
2688 intel_dp->DP |= DP_PORT_EN;
Ville Syrjälä6fec7662015-11-10 16:16:17 +02002689 if (crtc->config->has_audio)
2690 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Ville Syrjälä7b713f52014-10-16 21:27:35 +03002691
2692 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2693 POSTING_READ(intel_dp->output_reg);
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002694}
2695
Daniel Vettere8cb4552012-07-01 13:05:48 +02002696static void intel_enable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07002697{
Daniel Vettere8cb4552012-07-01 13:05:48 +02002698 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2699 struct drm_device *dev = encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002700 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulac1dec792014-10-27 16:26:56 +02002701 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +01002702 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002703 enum port port = dp_to_dig_port(intel_dp)->port;
2704 enum pipe pipe = crtc->pipe;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002705
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02002706 if (WARN_ON(dp_reg & DP_PORT_EN))
2707 return;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002708
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002709 pps_lock(intel_dp);
2710
Wayne Boyer666a4532015-12-09 12:29:35 -08002711 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002712 vlv_init_panel_power_sequencer(intel_dp);
2713
Ville Syrjälä78645782015-11-20 22:09:19 +02002714 /*
2715 * We get an occasional spurious underrun between the port
2716 * enable and vdd enable, when enabling port A eDP.
2717 *
2718 * FIXME: Not sure if this applies to (PCH) port D eDP as well
2719 */
2720 if (port == PORT_A)
2721 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2722
Ville Syrjälä7b13b582014-08-18 22:16:08 +03002723 intel_dp_enable_port(intel_dp);
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002724
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002725 if (port == PORT_A && IS_GEN5(dev_priv)) {
2726 /*
2727 * Underrun reporting for the other pipe was disabled in
2728 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2729 * enabled, so it's now safe to re-enable underrun reporting.
2730 */
2731 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2732 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2733 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2734 }
2735
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002736 edp_panel_vdd_on(intel_dp);
2737 edp_panel_on(intel_dp);
2738 edp_panel_vdd_off(intel_dp, true);
2739
Ville Syrjälä78645782015-11-20 22:09:19 +02002740 if (port == PORT_A)
2741 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2742
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002743 pps_unlock(intel_dp);
2744
Wayne Boyer666a4532015-12-09 12:29:35 -08002745 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002746 unsigned int lane_mask = 0x0;
2747
2748 if (IS_CHERRYVIEW(dev))
2749 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2750
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03002751 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2752 lane_mask);
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002753 }
Ville Syrjälä61234fa2014-10-16 21:27:34 +03002754
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002755 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2756 intel_dp_start_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03002757 intel_dp_stop_link_train(intel_dp);
Jani Nikulac1dec792014-10-27 16:26:56 +02002758
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002759 if (crtc->config->has_audio) {
Jani Nikulac1dec792014-10-27 16:26:56 +02002760 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002761 pipe_name(pipe));
Jani Nikulac1dec792014-10-27 16:26:56 +02002762 intel_audio_codec_enable(encoder);
2763 }
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002764}
Jesse Barnes89b667f2013-04-18 14:51:36 -07002765
Jani Nikulaecff4f32013-09-06 07:38:29 +03002766static void g4x_enable_dp(struct intel_encoder *encoder)
2767{
Jani Nikula828f5c62013-09-05 16:44:45 +03002768 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2769
Jani Nikulaecff4f32013-09-06 07:38:29 +03002770 intel_enable_dp(encoder);
Daniel Vetter4be73782014-01-17 14:39:48 +01002771 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002772}
Jesse Barnes89b667f2013-04-18 14:51:36 -07002773
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002774static void vlv_enable_dp(struct intel_encoder *encoder)
2775{
Jani Nikula828f5c62013-09-05 16:44:45 +03002776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2777
Daniel Vetter4be73782014-01-17 14:39:48 +01002778 intel_edp_backlight_on(intel_dp);
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002779 intel_psr_enable(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002780}
2781
Jani Nikulaecff4f32013-09-06 07:38:29 +03002782static void g4x_pre_enable_dp(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002783{
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002784 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02002785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002786 enum port port = dp_to_dig_port(intel_dp)->port;
2787 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002788
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02002789 intel_dp_prepare(encoder);
2790
Ville Syrjäläd6fbdd12015-10-29 21:25:58 +02002791 if (port == PORT_A && IS_GEN5(dev_priv)) {
2792 /*
2793 * We get FIFO underruns on the other pipe when
2794 * enabling the CPU eDP PLL, and when enabling CPU
2795 * eDP port. We could potentially avoid the PLL
2796 * underrun with a vblank wait just prior to enabling
2797 * the PLL, but that doesn't appear to help the port
2798 * enable case. Just sweep it all under the rug.
2799 */
2800 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2801 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2802 }
2803
Daniel Vetterd41f1ef2014-04-24 23:54:53 +02002804 /* Only ilk+ has port A */
Ville Syrjäläabfce942015-10-29 21:26:03 +02002805 if (port == PORT_A)
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002806 ironlake_edp_pll_on(intel_dp);
2807}
2808
Ville Syrjälä83b84592014-10-16 21:29:51 +03002809static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2810{
2811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2812 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2813 enum pipe pipe = intel_dp->pps_pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002814 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
Ville Syrjälä83b84592014-10-16 21:29:51 +03002815
2816 edp_panel_vdd_off_sync(intel_dp);
2817
2818 /*
2819 * VLV seems to get confused when multiple power seqeuencers
2820 * have the same port selected (even if only one has power/vdd
2821 * enabled). The failure manifests as vlv_wait_port_ready() failing
2822 * CHV on the other hand doesn't seem to mind having the same port
2823 * selected in multiple power seqeuencers, but let's clear the
2824 * port select always when logically disconnecting a power sequencer
2825 * from a port.
2826 */
2827 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2828 pipe_name(pipe), port_name(intel_dig_port->port));
2829 I915_WRITE(pp_on_reg, 0);
2830 POSTING_READ(pp_on_reg);
2831
2832 intel_dp->pps_pipe = INVALID_PIPE;
2833}
2834
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002835static void vlv_steal_power_sequencer(struct drm_device *dev,
2836 enum pipe pipe)
2837{
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 struct intel_encoder *encoder;
2840
2841 lockdep_assert_held(&dev_priv->pps_mutex);
2842
Ville Syrjäläac3c12e2014-10-16 21:29:56 +03002843 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2844 return;
2845
Jani Nikula19c80542015-12-16 12:48:16 +02002846 for_each_intel_encoder(dev, encoder) {
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002847 struct intel_dp *intel_dp;
Ville Syrjälä773538e82014-09-04 14:54:56 +03002848 enum port port;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002849
2850 if (encoder->type != INTEL_OUTPUT_EDP)
2851 continue;
2852
2853 intel_dp = enc_to_intel_dp(&encoder->base);
Ville Syrjälä773538e82014-09-04 14:54:56 +03002854 port = dp_to_dig_port(intel_dp)->port;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002855
2856 if (intel_dp->pps_pipe != pipe)
2857 continue;
2858
2859 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
Ville Syrjälä773538e82014-09-04 14:54:56 +03002860 pipe_name(pipe), port_name(port));
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002861
Maarten Lankhorste02f9a02015-08-05 12:37:08 +02002862 WARN(encoder->base.crtc,
Ville Syrjälä034e43c2014-10-16 21:27:28 +03002863 "stealing pipe %c power sequencer from active eDP port %c\n",
2864 pipe_name(pipe), port_name(port));
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002865
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002866 /* make sure vdd is off before we steal it */
Ville Syrjälä83b84592014-10-16 21:29:51 +03002867 vlv_detach_power_sequencer(intel_dp);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002868 }
2869}
2870
2871static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2872{
2873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2874 struct intel_encoder *encoder = &intel_dig_port->base;
2875 struct drm_device *dev = encoder->base.dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002878
2879 lockdep_assert_held(&dev_priv->pps_mutex);
2880
Ville Syrjälä093e3f12014-10-16 21:27:33 +03002881 if (!is_edp(intel_dp))
2882 return;
2883
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002884 if (intel_dp->pps_pipe == crtc->pipe)
2885 return;
2886
2887 /*
2888 * If another power sequencer was being used on this
2889 * port previously make sure to turn off vdd there while
2890 * we still have control of it.
2891 */
2892 if (intel_dp->pps_pipe != INVALID_PIPE)
Ville Syrjälä83b84592014-10-16 21:29:51 +03002893 vlv_detach_power_sequencer(intel_dp);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002894
2895 /*
2896 * We may be stealing the power
2897 * sequencer from another port.
2898 */
2899 vlv_steal_power_sequencer(dev, crtc->pipe);
2900
2901 /* now it's all ours */
2902 intel_dp->pps_pipe = crtc->pipe;
2903
2904 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2905 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2906
2907 /* init power sequencer on this pipe and port */
Ville Syrjälä36b5f422014-10-16 21:27:30 +03002908 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2909 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03002910}
2911
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002912static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2913{
2914 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07002916 struct drm_device *dev = encoder->base.dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07002917 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002918 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002919 enum dpio_channel port = vlv_dport_to_channel(dport);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002920 int pipe = intel_crtc->pipe;
2921 u32 val;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002922
Ville Syrjäläa5805162015-05-26 20:42:30 +03002923 mutex_lock(&dev_priv->sb_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002924
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002925 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002926 val = 0;
2927 if (pipe)
2928 val |= (1<<21);
2929 else
2930 val &= ~(1<<21);
2931 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002932 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2933 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2934 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002935
Ville Syrjäläa5805162015-05-26 20:42:30 +03002936 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002937
Jani Nikulaab1f90f2013-07-30 12:20:30 +03002938 intel_enable_dp(encoder);
Jesse Barnes89b667f2013-04-18 14:51:36 -07002939}
2940
Jani Nikulaecff4f32013-09-06 07:38:29 +03002941static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07002942{
2943 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2944 struct drm_device *dev = encoder->base.dev;
2945 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002946 struct intel_crtc *intel_crtc =
2947 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002948 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002949 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07002950
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02002951 intel_dp_prepare(encoder);
2952
Jesse Barnes89b667f2013-04-18 14:51:36 -07002953 /* Program Tx lane resets to default */
Ville Syrjäläa5805162015-05-26 20:42:30 +03002954 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002955 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07002956 DPIO_PCS_TX_LANE2_RESET |
2957 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07002959 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2960 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2961 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2962 DPIO_PCS_CLK_SOFT_RESET);
2963
2964 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002965 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2966 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2967 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Ville Syrjäläa5805162015-05-26 20:42:30 +03002968 mutex_unlock(&dev_priv->sb_lock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002969}
2970
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002971static void chv_pre_enable_dp(struct intel_encoder *encoder)
2972{
2973 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2974 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2975 struct drm_device *dev = encoder->base.dev;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002977 struct intel_crtc *intel_crtc =
2978 to_intel_crtc(encoder->base.crtc);
2979 enum dpio_channel ch = vlv_dport_to_channel(dport);
2980 int pipe = intel_crtc->pipe;
Ville Syrjälä2e523e92015-04-10 18:21:27 +03002981 int data, i, stagger;
Ville Syrjälä949c1d42014-04-09 13:28:58 +03002982 u32 val;
2983
Ville Syrjäläa5805162015-05-26 20:42:30 +03002984 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä949c1d42014-04-09 13:28:58 +03002985
Ville Syrjälä570e2a72014-08-18 14:42:46 +03002986 /* allow hardware to manage TX FIFO reset source */
2987 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2988 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2989 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2990
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002991 if (intel_crtc->config->lane_count > 2) {
2992 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2993 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2994 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2995 }
Ville Syrjälä570e2a72014-08-18 14:42:46 +03002996
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002997 /* Program Tx lane latency optimal setting*/
Ville Syrjäläe0fce782015-07-08 23:45:54 +03002998 for (i = 0; i < intel_crtc->config->lane_count; i++) {
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002999 /* Set the upar bit */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003000 if (intel_crtc->config->lane_count == 1)
3001 data = 0x0;
3002 else
3003 data = (i == 1) ? 0x0 : 0x1;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003004 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
3005 data << DPIO_UPAR_SHIFT);
3006 }
3007
3008 /* Data lane stagger programming */
Ville Syrjälä2e523e92015-04-10 18:21:27 +03003009 if (intel_crtc->config->port_clock > 270000)
3010 stagger = 0x18;
3011 else if (intel_crtc->config->port_clock > 135000)
3012 stagger = 0xd;
3013 else if (intel_crtc->config->port_clock > 67500)
3014 stagger = 0x7;
3015 else if (intel_crtc->config->port_clock > 33750)
3016 stagger = 0x4;
3017 else
3018 stagger = 0x2;
3019
3020 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
3021 val |= DPIO_TX2_STAGGER_MASK(0x1f);
3022 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
3023
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003024 if (intel_crtc->config->lane_count > 2) {
3025 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
3026 val |= DPIO_TX2_STAGGER_MASK(0x1f);
3027 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
3028 }
Ville Syrjälä2e523e92015-04-10 18:21:27 +03003029
3030 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
3031 DPIO_LANESTAGGER_STRAP(stagger) |
3032 DPIO_LANESTAGGER_STRAP_OVRD |
3033 DPIO_TX1_STAGGER_MASK(0x1f) |
3034 DPIO_TX1_STAGGER_MULT(6) |
3035 DPIO_TX2_STAGGER_MULT(0));
3036
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003037 if (intel_crtc->config->lane_count > 2) {
3038 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
3039 DPIO_LANESTAGGER_STRAP(stagger) |
3040 DPIO_LANESTAGGER_STRAP_OVRD |
3041 DPIO_TX1_STAGGER_MASK(0x1f) |
3042 DPIO_TX1_STAGGER_MULT(7) |
3043 DPIO_TX2_STAGGER_MULT(5));
3044 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003045
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03003046 /* Deassert data lane reset */
3047 chv_data_lane_soft_reset(encoder, false);
3048
Ville Syrjäläa5805162015-05-26 20:42:30 +03003049 mutex_unlock(&dev_priv->sb_lock);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003050
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003051 intel_enable_dp(encoder);
Ville Syrjäläb0b33842015-07-08 23:45:55 +03003052
3053 /* Second common lane will stay alive on its own now */
3054 if (dport->release_cl2_override) {
3055 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
3056 dport->release_cl2_override = false;
3057 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003058}
3059
Ville Syrjälä9197c882014-04-09 13:29:05 +03003060static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
3061{
3062 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
3063 struct drm_device *dev = encoder->base.dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc =
3066 to_intel_crtc(encoder->base.crtc);
3067 enum dpio_channel ch = vlv_dport_to_channel(dport);
3068 enum pipe pipe = intel_crtc->pipe;
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003069 unsigned int lane_mask =
3070 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
Ville Syrjälä9197c882014-04-09 13:29:05 +03003071 u32 val;
3072
Ville Syrjälä625695f2014-06-28 02:04:02 +03003073 intel_dp_prepare(encoder);
3074
Ville Syrjäläb0b33842015-07-08 23:45:55 +03003075 /*
3076 * Must trick the second common lane into life.
3077 * Otherwise we can't even access the PLL.
3078 */
3079 if (ch == DPIO_CH0 && pipe == PIPE_B)
3080 dport->release_cl2_override =
3081 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3082
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003083 chv_phy_powergate_lanes(encoder, true, lane_mask);
3084
Ville Syrjäläa5805162015-05-26 20:42:30 +03003085 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä9197c882014-04-09 13:29:05 +03003086
Ville Syrjäläa8f327f2015-07-09 20:14:11 +03003087 /* Assert data lane reset */
3088 chv_data_lane_soft_reset(encoder, true);
3089
Ville Syrjäläb9e5ac32014-05-27 16:30:18 +03003090 /* program left/right clock distribution */
3091 if (pipe != PIPE_B) {
3092 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3093 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3094 if (ch == DPIO_CH0)
3095 val |= CHV_BUFLEFTENA1_FORCE;
3096 if (ch == DPIO_CH1)
3097 val |= CHV_BUFRIGHTENA1_FORCE;
3098 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3099 } else {
3100 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3101 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3102 if (ch == DPIO_CH0)
3103 val |= CHV_BUFLEFTENA2_FORCE;
3104 if (ch == DPIO_CH1)
3105 val |= CHV_BUFRIGHTENA2_FORCE;
3106 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3107 }
3108
Ville Syrjälä9197c882014-04-09 13:29:05 +03003109 /* program clock channel usage */
3110 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3111 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3112 if (pipe != PIPE_B)
3113 val &= ~CHV_PCS_USEDCLKCHANNEL;
3114 else
3115 val |= CHV_PCS_USEDCLKCHANNEL;
3116 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3117
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003118 if (intel_crtc->config->lane_count > 2) {
3119 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3120 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3121 if (pipe != PIPE_B)
3122 val &= ~CHV_PCS_USEDCLKCHANNEL;
3123 else
3124 val |= CHV_PCS_USEDCLKCHANNEL;
3125 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3126 }
Ville Syrjälä9197c882014-04-09 13:29:05 +03003127
3128 /*
3129 * This a a bit weird since generally CL
3130 * matches the pipe, but here we need to
3131 * pick the CL based on the port.
3132 */
3133 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3134 if (pipe != PIPE_B)
3135 val &= ~CHV_CMN_USEDCLKCHANNEL;
3136 else
3137 val |= CHV_CMN_USEDCLKCHANNEL;
3138 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3139
Ville Syrjäläa5805162015-05-26 20:42:30 +03003140 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä9197c882014-04-09 13:29:05 +03003141}
3142
Ville Syrjäläd6db9952015-07-08 23:45:49 +03003143static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3144{
3145 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3146 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3147 u32 val;
3148
3149 mutex_lock(&dev_priv->sb_lock);
3150
3151 /* disable left/right clock distribution */
3152 if (pipe != PIPE_B) {
3153 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3154 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3155 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3156 } else {
3157 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3158 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3159 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3160 }
3161
3162 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003163
Ville Syrjäläb0b33842015-07-08 23:45:55 +03003164 /*
3165 * Leave the power down bit cleared for at least one
3166 * lane so that chv_powergate_phy_ch() will power
3167 * on something when the channel is otherwise unused.
3168 * When the port is off and the override is removed
3169 * the lanes power down anyway, so otherwise it doesn't
3170 * really matter what the state of power down bits is
3171 * after this.
3172 */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003173 chv_phy_powergate_lanes(encoder, false, 0x0);
Ville Syrjäläd6db9952015-07-08 23:45:49 +03003174}
3175
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003176/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003177 * Native read with retry for link status and receiver capability reads for
3178 * cases where the sink may still be asleep.
Jani Nikula9d1a1032014-03-14 16:51:15 +02003179 *
3180 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3181 * supposed to retry 3 times per the spec.
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003182 */
Jani Nikula9d1a1032014-03-14 16:51:15 +02003183static ssize_t
3184intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3185 void *buffer, size_t size)
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003186{
Jani Nikula9d1a1032014-03-14 16:51:15 +02003187 ssize_t ret;
3188 int i;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003189
Ville Syrjäläf6a19062014-10-16 20:46:09 +03003190 /*
3191 * Sometime we just get the same incorrect byte repeated
3192 * over the entire buffer. Doing just one throw away read
3193 * initially seems to "solve" it.
3194 */
3195 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3196
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003197 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02003198 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3199 if (ret == size)
3200 return ret;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07003201 msleep(1);
3202 }
3203
Jani Nikula9d1a1032014-03-14 16:51:15 +02003204 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003205}
3206
3207/*
3208 * Fetch AUX CH registers 0x202 - 0x207 which contain
3209 * link status information
3210 */
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003211bool
Keith Packard93f62da2011-11-01 19:45:03 -07003212intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003213{
Jani Nikula9d1a1032014-03-14 16:51:15 +02003214 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3215 DP_LANE0_1_STATUS,
3216 link_status,
3217 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003218}
3219
Paulo Zanoni11002442014-06-13 18:45:41 -03003220/* These are source-specific values. */
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003221uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08003222intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003223{
Paulo Zanoni30add222012-10-26 19:05:45 -02003224 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Sonika Jindal7ad14a22015-02-25 10:29:12 +05303225 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003226 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08003227
Vandana Kannan93147262014-11-18 15:45:29 +05303228 if (IS_BROXTON(dev))
3229 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3230 else if (INTEL_INFO(dev)->gen >= 9) {
Sonika Jindal9e458032015-05-06 17:35:48 +05303231 if (dev_priv->edp_low_vswing && port == PORT_A)
Sonika Jindal7ad14a22015-02-25 10:29:12 +05303232 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
Damien Lespiau5a9d1f12013-12-03 13:56:26 +00003233 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
Wayne Boyer666a4532015-12-09 12:29:35 -08003234 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Sonika Jindalbd600182014-08-08 16:23:41 +05303235 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003236 else if (IS_GEN7(dev) && port == PORT_A)
Sonika Jindalbd600182014-08-08 16:23:41 +05303237 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003238 else if (HAS_PCH_CPT(dev) && port != PORT_A)
Sonika Jindalbd600182014-08-08 16:23:41 +05303239 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
Keith Packard1a2eb462011-11-16 16:26:07 -08003240 else
Sonika Jindalbd600182014-08-08 16:23:41 +05303241 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
Keith Packard1a2eb462011-11-16 16:26:07 -08003242}
3243
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003244uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08003245intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3246{
Paulo Zanoni30add222012-10-26 19:05:45 -02003247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03003248 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08003249
Damien Lespiau5a9d1f12013-12-03 13:56:26 +00003250 if (INTEL_INFO(dev)->gen >= 9) {
3251 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3253 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3255 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3257 return DP_TRAIN_PRE_EMPH_LEVEL_1;
Sonika Jindal7ad14a22015-02-25 10:29:12 +05303258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3259 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Damien Lespiau5a9d1f12013-12-03 13:56:26 +00003260 default:
3261 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3262 }
3263 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003264 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3266 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3268 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3270 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003272 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05303273 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Paulo Zanonid6c0d722012-10-15 15:51:34 -03003274 }
Wayne Boyer666a4532015-12-09 12:29:35 -08003275 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003276 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3278 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3280 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3282 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003284 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05303285 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003286 }
Imre Deakbc7d38a2013-05-16 14:40:36 +03003287 } else if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08003288 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3290 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3293 return DP_TRAIN_PRE_EMPH_LEVEL_1;
Keith Packard1a2eb462011-11-16 16:26:07 -08003294 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05303295 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Keith Packard1a2eb462011-11-16 16:26:07 -08003296 }
3297 } else {
3298 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3300 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3302 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3304 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Keith Packard1a2eb462011-11-16 16:26:07 -08003306 default:
Sonika Jindalbd600182014-08-08 16:23:41 +05303307 return DP_TRAIN_PRE_EMPH_LEVEL_0;
Keith Packard1a2eb462011-11-16 16:26:07 -08003308 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003309 }
3310}
3311
Daniel Vetter5829975c2015-04-16 11:36:52 +02003312static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003313{
3314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003317 struct intel_crtc *intel_crtc =
3318 to_intel_crtc(dport->base.base.crtc);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003319 unsigned long demph_reg_value, preemph_reg_value,
3320 uniqtranscale_reg_value;
3321 uint8_t train_set = intel_dp->train_set[0];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08003322 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003323 int pipe = intel_crtc->pipe;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003324
3325 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303326 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003327 preemph_reg_value = 0x0004000;
3328 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003330 demph_reg_value = 0x2B405555;
3331 uniqtranscale_reg_value = 0x552AB83A;
3332 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003334 demph_reg_value = 0x2B404040;
3335 uniqtranscale_reg_value = 0x5548B83A;
3336 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003338 demph_reg_value = 0x2B245555;
3339 uniqtranscale_reg_value = 0x5560B83A;
3340 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003342 demph_reg_value = 0x2B405555;
3343 uniqtranscale_reg_value = 0x5598DA3A;
3344 break;
3345 default:
3346 return 0;
3347 }
3348 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303349 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003350 preemph_reg_value = 0x0002000;
3351 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003353 demph_reg_value = 0x2B404040;
3354 uniqtranscale_reg_value = 0x5552B83A;
3355 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003357 demph_reg_value = 0x2B404848;
3358 uniqtranscale_reg_value = 0x5580B83A;
3359 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003361 demph_reg_value = 0x2B404040;
3362 uniqtranscale_reg_value = 0x55ADDA3A;
3363 break;
3364 default:
3365 return 0;
3366 }
3367 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303368 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003369 preemph_reg_value = 0x0000000;
3370 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003372 demph_reg_value = 0x2B305555;
3373 uniqtranscale_reg_value = 0x5570B83A;
3374 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003376 demph_reg_value = 0x2B2B4040;
3377 uniqtranscale_reg_value = 0x55ADDA3A;
3378 break;
3379 default:
3380 return 0;
3381 }
3382 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303383 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003384 preemph_reg_value = 0x0006000;
3385 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003387 demph_reg_value = 0x1B405555;
3388 uniqtranscale_reg_value = 0x55ADDA3A;
3389 break;
3390 default:
3391 return 0;
3392 }
3393 break;
3394 default:
3395 return 0;
3396 }
3397
Ville Syrjäläa5805162015-05-26 20:42:30 +03003398 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08003399 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3400 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3401 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003402 uniqtranscale_reg_value);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08003403 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3404 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3405 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3406 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
Ville Syrjäläa5805162015-05-26 20:42:30 +03003407 mutex_unlock(&dev_priv->sb_lock);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003408
3409 return 0;
3410}
3411
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003412static bool chv_need_uniq_trans_scale(uint8_t train_set)
3413{
3414 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3415 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3416}
3417
Daniel Vetter5829975c2015-04-16 11:36:52 +02003418static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003419{
3420 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3423 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003424 u32 deemph_reg_value, margin_reg_value, val;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003425 uint8_t train_set = intel_dp->train_set[0];
3426 enum dpio_channel ch = vlv_dport_to_channel(dport);
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003427 enum pipe pipe = intel_crtc->pipe;
3428 int i;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003429
3430 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303431 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003432 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003434 deemph_reg_value = 128;
3435 margin_reg_value = 52;
3436 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003438 deemph_reg_value = 128;
3439 margin_reg_value = 77;
3440 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003442 deemph_reg_value = 128;
3443 margin_reg_value = 102;
3444 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003446 deemph_reg_value = 128;
3447 margin_reg_value = 154;
3448 /* FIXME extra to set for 1200 */
3449 break;
3450 default:
3451 return 0;
3452 }
3453 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303454 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003455 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003457 deemph_reg_value = 85;
3458 margin_reg_value = 78;
3459 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003461 deemph_reg_value = 85;
3462 margin_reg_value = 116;
3463 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003465 deemph_reg_value = 85;
3466 margin_reg_value = 154;
3467 break;
3468 default:
3469 return 0;
3470 }
3471 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303472 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003473 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003475 deemph_reg_value = 64;
3476 margin_reg_value = 104;
3477 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303478 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003479 deemph_reg_value = 64;
3480 margin_reg_value = 154;
3481 break;
3482 default:
3483 return 0;
3484 }
3485 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303486 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003487 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003489 deemph_reg_value = 43;
3490 margin_reg_value = 154;
3491 break;
3492 default:
3493 return 0;
3494 }
3495 break;
3496 default:
3497 return 0;
3498 }
3499
Ville Syrjäläa5805162015-05-26 20:42:30 +03003500 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003501
3502 /* Clear calc init */
Ville Syrjälä1966e592014-04-09 13:29:04 +03003503 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3504 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03003505 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3506 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
Ville Syrjälä1966e592014-04-09 13:29:04 +03003507 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3508
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003509 if (intel_crtc->config->lane_count > 2) {
3510 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3511 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3512 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3513 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3514 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3515 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003516
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03003517 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3518 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3519 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3520 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3521
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003522 if (intel_crtc->config->lane_count > 2) {
3523 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3524 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3525 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3526 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3527 }
Ville Syrjäläa02ef3c2014-08-18 14:42:45 +03003528
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003529 /* Program swing deemph */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003530 for (i = 0; i < intel_crtc->config->lane_count; i++) {
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003531 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3532 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3533 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3534 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3535 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003536
3537 /* Program swing margin */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003538 for (i = 0; i < intel_crtc->config->lane_count; i++) {
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003539 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003540
Ville Syrjälä1fb44502014-06-28 02:04:03 +03003541 val &= ~DPIO_SWING_MARGIN000_MASK;
3542 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003543
3544 /*
3545 * Supposedly this value shouldn't matter when unique transition
3546 * scale is disabled, but in fact it does matter. Let's just
3547 * always program the same value and hope it's OK.
3548 */
3549 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3550 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3551
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003552 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3553 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003554
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003555 /*
3556 * The document said it needs to set bit 27 for ch0 and bit 26
3557 * for ch1. Might be a typo in the doc.
3558 * For now, for this unique transition scale selection, set bit
3559 * 27 for ch0 and ch1.
3560 */
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003561 for (i = 0; i < intel_crtc->config->lane_count; i++) {
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003562 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003563 if (chv_need_uniq_trans_scale(train_set))
Ville Syrjäläf72df8d2014-04-09 13:29:03 +03003564 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
Ville Syrjälä67fa24b2015-07-08 23:45:48 +03003565 else
3566 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3567 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003568 }
3569
3570 /* Start swing calculation */
Ville Syrjälä1966e592014-04-09 13:29:04 +03003571 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3572 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3573 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3574
Ville Syrjäläe0fce782015-07-08 23:45:54 +03003575 if (intel_crtc->config->lane_count > 2) {
3576 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3577 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3578 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3579 }
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003580
Ville Syrjäläa5805162015-05-26 20:42:30 +03003581 mutex_unlock(&dev_priv->sb_lock);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003582
3583 return 0;
3584}
3585
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003586static uint32_t
Daniel Vetter5829975c2015-04-16 11:36:52 +02003587gen4_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003588{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003589 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003590
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003591 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303592 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003593 default:
3594 signal_levels |= DP_VOLTAGE_0_4;
3595 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303596 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003597 signal_levels |= DP_VOLTAGE_0_6;
3598 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303599 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003600 signal_levels |= DP_VOLTAGE_0_8;
3601 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303602 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003603 signal_levels |= DP_VOLTAGE_1_2;
3604 break;
3605 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00003606 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303607 case DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003608 default:
3609 signal_levels |= DP_PRE_EMPHASIS_0;
3610 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303611 case DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003612 signal_levels |= DP_PRE_EMPHASIS_3_5;
3613 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303614 case DP_TRAIN_PRE_EMPH_LEVEL_2:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003615 signal_levels |= DP_PRE_EMPHASIS_6;
3616 break;
Sonika Jindalbd600182014-08-08 16:23:41 +05303617 case DP_TRAIN_PRE_EMPH_LEVEL_3:
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003618 signal_levels |= DP_PRE_EMPHASIS_9_5;
3619 break;
3620 }
3621 return signal_levels;
3622}
3623
Zhenyu Wange3421a12010-04-08 09:43:27 +08003624/* Gen6's DP voltage swing and pre-emphasis control */
3625static uint32_t
Daniel Vetter5829975c2015-04-16 11:36:52 +02003626gen6_edp_signal_levels(uint8_t train_set)
Zhenyu Wange3421a12010-04-08 09:43:27 +08003627{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003628 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3629 DP_TRAIN_PRE_EMPHASIS_MASK);
3630 switch (signal_levels) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303631 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003633 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05303634 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003635 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05303636 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3637 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003638 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05303639 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3640 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003641 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Sonika Jindalbd600182014-08-08 16:23:41 +05303642 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3643 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003644 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003645 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003646 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3647 "0x%x\n", signal_levels);
3648 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003649 }
3650}
3651
Keith Packard1a2eb462011-11-16 16:26:07 -08003652/* Gen7's DP voltage swing and pre-emphasis control */
3653static uint32_t
Daniel Vetter5829975c2015-04-16 11:36:52 +02003654gen7_edp_signal_levels(uint8_t train_set)
Keith Packard1a2eb462011-11-16 16:26:07 -08003655{
3656 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3657 DP_TRAIN_PRE_EMPHASIS_MASK);
3658 switch (signal_levels) {
Sonika Jindalbd600182014-08-08 16:23:41 +05303659 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08003660 return EDP_LINK_TRAIN_400MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05303661 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08003662 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05303663 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
Keith Packard1a2eb462011-11-16 16:26:07 -08003664 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3665
Sonika Jindalbd600182014-08-08 16:23:41 +05303666 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08003667 return EDP_LINK_TRAIN_600MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05303668 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08003669 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3670
Sonika Jindalbd600182014-08-08 16:23:41 +05303671 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
Keith Packard1a2eb462011-11-16 16:26:07 -08003672 return EDP_LINK_TRAIN_800MV_0DB_IVB;
Sonika Jindalbd600182014-08-08 16:23:41 +05303673 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
Keith Packard1a2eb462011-11-16 16:26:07 -08003674 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3675
3676 default:
3677 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3678 "0x%x\n", signal_levels);
3679 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3680 }
3681}
3682
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003683void
Ander Conselvan de Oliveiraf4eb6922015-10-23 13:01:44 +03003684intel_dp_set_signal_levels(struct intel_dp *intel_dp)
Paulo Zanonif0a34242012-12-06 16:51:50 -02003685{
3686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03003687 enum port port = intel_dig_port->port;
Paulo Zanonif0a34242012-12-06 16:51:50 -02003688 struct drm_device *dev = intel_dig_port->base.base.dev;
Ander Conselvan de Oliveirab905a912015-10-23 13:01:47 +03003689 struct drm_i915_private *dev_priv = to_i915(dev);
David Weinehallf8896f52015-06-25 11:11:03 +03003690 uint32_t signal_levels, mask = 0;
Paulo Zanonif0a34242012-12-06 16:51:50 -02003691 uint8_t train_set = intel_dp->train_set[0];
3692
David Weinehallf8896f52015-06-25 11:11:03 +03003693 if (HAS_DDI(dev)) {
3694 signal_levels = ddi_signal_levels(intel_dp);
3695
3696 if (IS_BROXTON(dev))
3697 signal_levels = 0;
3698 else
3699 mask = DDI_BUF_EMP_MASK;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03003700 } else if (IS_CHERRYVIEW(dev)) {
Daniel Vetter5829975c2015-04-16 11:36:52 +02003701 signal_levels = chv_signal_levels(intel_dp);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07003702 } else if (IS_VALLEYVIEW(dev)) {
Daniel Vetter5829975c2015-04-16 11:36:52 +02003703 signal_levels = vlv_signal_levels(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03003704 } else if (IS_GEN7(dev) && port == PORT_A) {
Daniel Vetter5829975c2015-04-16 11:36:52 +02003705 signal_levels = gen7_edp_signal_levels(train_set);
Paulo Zanonif0a34242012-12-06 16:51:50 -02003706 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003707 } else if (IS_GEN6(dev) && port == PORT_A) {
Daniel Vetter5829975c2015-04-16 11:36:52 +02003708 signal_levels = gen6_edp_signal_levels(train_set);
Paulo Zanonif0a34242012-12-06 16:51:50 -02003709 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3710 } else {
Daniel Vetter5829975c2015-04-16 11:36:52 +02003711 signal_levels = gen4_signal_levels(train_set);
Paulo Zanonif0a34242012-12-06 16:51:50 -02003712 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3713 }
3714
Vandana Kannan96fb9f92014-11-18 15:45:27 +05303715 if (mask)
3716 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3717
3718 DRM_DEBUG_KMS("Using vswing level %d\n",
3719 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3720 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3721 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3722 DP_TRAIN_PRE_EMPHASIS_SHIFT);
Paulo Zanonif0a34242012-12-06 16:51:50 -02003723
Ander Conselvan de Oliveiraf4eb6922015-10-23 13:01:44 +03003724 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
Ander Conselvan de Oliveirab905a912015-10-23 13:01:47 +03003725
3726 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3727 POSTING_READ(intel_dp->output_reg);
Paulo Zanonif0a34242012-12-06 16:51:50 -02003728}
3729
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003730void
Ander Conselvan de Oliveirae9c176d2015-10-23 13:01:45 +03003731intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3732 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003733{
Paulo Zanoni174edf12012-10-26 19:05:50 -02003734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03003735 struct drm_i915_private *dev_priv =
3736 to_i915(intel_dig_port->base.base.dev);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003737
Ander Conselvan de Oliveiraf4eb6922015-10-23 13:01:44 +03003738 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
Paulo Zanoni47ea7542012-07-17 16:55:16 -03003739
Ander Conselvan de Oliveiraf4eb6922015-10-23 13:01:44 +03003740 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003741 POSTING_READ(intel_dp->output_reg);
Ander Conselvan de Oliveirae9c176d2015-10-23 13:01:45 +03003742}
3743
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03003744void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
Imre Deak3ab9c632013-05-03 12:57:41 +03003745{
3746 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3747 struct drm_device *dev = intel_dig_port->base.base.dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 enum port port = intel_dig_port->port;
3750 uint32_t val;
3751
3752 if (!HAS_DDI(dev))
3753 return;
3754
3755 val = I915_READ(DP_TP_CTL(port));
3756 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3757 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3758 I915_WRITE(DP_TP_CTL(port), val);
3759
3760 /*
3761 * On PORT_A we can have only eDP in SST mode. There the only reason
3762 * we need to set idle transmission mode is to work around a HW issue
3763 * where we enable the pipe while not in idle link-training mode.
3764 * In this case there is requirement to wait for a minimum number of
3765 * idle patterns to be sent.
3766 */
3767 if (port == PORT_A)
3768 return;
3769
3770 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3771 1))
3772 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3773}
3774
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003775static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01003776intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003777{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003779 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
Imre Deakbc7d38a2013-05-16 14:40:36 +03003780 enum port port = intel_dig_port->port;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003781 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003782 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003783 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003784
Daniel Vetterbc76e3202014-05-20 22:46:50 +02003785 if (WARN_ON(HAS_DDI(dev)))
Paulo Zanonic19b0662012-10-15 15:51:41 -03003786 return;
3787
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02003788 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
Chris Wilson1b39d6f2010-12-06 11:20:45 +00003789 return;
3790
Zhao Yakui28c97732009-10-09 11:39:41 +08003791 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003792
Ville Syrjälä39e5fa82015-05-05 17:17:29 +03003793 if ((IS_GEN7(dev) && port == PORT_A) ||
3794 (HAS_PCH_CPT(dev) && port != PORT_A)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08003795 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003796 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003797 } else {
Ville Syrjäläaad3d142014-06-28 02:04:25 +03003798 if (IS_CHERRYVIEW(dev))
3799 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3800 else
3801 DP &= ~DP_LINK_TRAIN_MASK;
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003802 DP |= DP_LINK_TRAIN_PAT_IDLE;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003803 }
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003804 I915_WRITE(intel_dp->output_reg, DP);
Chris Wilsonfe255d02010-09-11 21:37:48 +01003805 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003806
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003807 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3808 I915_WRITE(intel_dp->output_reg, DP);
3809 POSTING_READ(intel_dp->output_reg);
3810
3811 /*
3812 * HW workaround for IBX, we need to move the port
3813 * to transcoder A after disabling it to allow the
3814 * matching HDMI port to be enabled on transcoder A.
3815 */
3816 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
Ville Syrjälä0c241d52015-10-30 19:23:22 +02003817 /*
3818 * We get CPU/PCH FIFO underruns on the other pipe when
3819 * doing the workaround. Sweep them under the rug.
3820 */
3821 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3822 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3823
Ville Syrjälä1612c8b2015-05-05 17:17:34 +03003824 /* always enable with pattern 1 (as per spec) */
3825 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3826 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3827 I915_WRITE(intel_dp->output_reg, DP);
3828 POSTING_READ(intel_dp->output_reg);
3829
3830 DP &= ~DP_PORT_EN;
Eric Anholt5bddd172010-11-18 09:32:59 +08003831 I915_WRITE(intel_dp->output_reg, DP);
Daniel Vetter0ca09682014-11-24 16:54:11 +01003832 POSTING_READ(intel_dp->output_reg);
Ville Syrjälä0c241d52015-10-30 19:23:22 +02003833
3834 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3835 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3836 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
Eric Anholt5bddd172010-11-18 09:32:59 +08003837 }
3838
Keith Packardf01eca22011-09-28 16:48:10 -07003839 msleep(intel_dp->panel_power_down_delay);
Ville Syrjälä6fec7662015-11-10 16:16:17 +02003840
3841 intel_dp->DP = DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003842}
3843
Keith Packard26d61aa2011-07-25 20:01:09 -07003844static bool
3845intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07003846{
Rodrigo Vivia031d702013-10-03 16:15:06 -03003847 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3848 struct drm_device *dev = dig_port->base.base.dev;
3849 struct drm_i915_private *dev_priv = dev->dev_private;
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05303850 uint8_t rev;
Rodrigo Vivia031d702013-10-03 16:15:06 -03003851
Jani Nikula9d1a1032014-03-14 16:51:15 +02003852 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3853 sizeof(intel_dp->dpcd)) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003854 return false; /* aux transfer failed */
Keith Packard92fd8fd2011-07-25 19:50:10 -07003855
Andy Shevchenkoa8e98152014-09-01 14:12:01 +03003856 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
Damien Lespiau577c7a52012-12-13 16:09:02 +00003857
Adam Jacksonedb39242012-09-18 10:58:49 -04003858 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3859 return false; /* DPCD not present */
3860
Shobhit Kumar2293bb52013-07-11 18:44:56 -03003861 /* Check if the panel supports PSR */
3862 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
Jani Nikula50003932013-09-20 16:42:17 +03003863 if (is_edp(intel_dp)) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02003864 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3865 intel_dp->psr_dpcd,
3866 sizeof(intel_dp->psr_dpcd));
Rodrigo Vivia031d702013-10-03 16:15:06 -03003867 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3868 dev_priv->psr.sink_support = true;
Jani Nikula50003932013-09-20 16:42:17 +03003869 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
Rodrigo Vivia031d702013-10-03 16:15:06 -03003870 }
Sonika Jindal474d1ec2015-04-02 11:02:44 +05303871
3872 if (INTEL_INFO(dev)->gen >= 9 &&
3873 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3874 uint8_t frame_sync_cap;
3875
3876 dev_priv->psr.sink_support = true;
3877 intel_dp_dpcd_read_wake(&intel_dp->aux,
3878 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3879 &frame_sync_cap, 1);
3880 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3881 /* PSR2 needs frame sync as well */
3882 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3883 DRM_DEBUG_KMS("PSR2 %s on sink",
3884 dev_priv->psr.psr2_support ? "supported" : "not supported");
3885 }
Jani Nikula50003932013-09-20 16:42:17 +03003886 }
3887
Jani Nikulabc5133d2015-09-03 11:16:07 +03003888 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03003889 yesno(intel_dp_source_supports_hbr2(intel_dp)),
Jani Nikula742f4912015-09-03 11:16:09 +03003890 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
Todd Previte06ea66b2014-01-20 10:19:39 -07003891
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05303892 /* Intermediate frequency support */
3893 if (is_edp(intel_dp) &&
3894 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3895 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3896 (rev >= 0x03)) { /* eDp v1.4 or higher */
Ville Syrjälä94ca7192015-03-13 19:40:31 +02003897 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
Ville Syrjäläea2d8a42015-03-12 17:10:28 +02003898 int i;
3899
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05303900 intel_dp_dpcd_read_wake(&intel_dp->aux,
3901 DP_SUPPORTED_LINK_RATES,
Ville Syrjälä94ca7192015-03-13 19:40:31 +02003902 sink_rates,
3903 sizeof(sink_rates));
Ville Syrjäläea2d8a42015-03-12 17:10:28 +02003904
Ville Syrjälä94ca7192015-03-13 19:40:31 +02003905 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3906 int val = le16_to_cpu(sink_rates[i]);
Ville Syrjäläea2d8a42015-03-12 17:10:28 +02003907
3908 if (val == 0)
3909 break;
3910
Sonika Jindalaf77b972015-05-07 13:59:28 +05303911 /* Value read is in kHz while drm clock is saved in deca-kHz */
3912 intel_dp->sink_rates[i] = (val * 200) / 10;
Ville Syrjäläea2d8a42015-03-12 17:10:28 +02003913 }
Ville Syrjälä94ca7192015-03-13 19:40:31 +02003914 intel_dp->num_sink_rates = i;
Sonika Jindalfc0f8e22015-03-05 10:03:58 +05303915 }
Ville Syrjälä0336400e2015-03-12 17:10:39 +02003916
3917 intel_dp_print_rates(intel_dp);
3918
Adam Jacksonedb39242012-09-18 10:58:49 -04003919 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3920 DP_DWN_STRM_PORT_PRESENT))
3921 return true; /* native DP sink */
3922
3923 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3924 return true; /* no per-port downstream info */
3925
Jani Nikula9d1a1032014-03-14 16:51:15 +02003926 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3927 intel_dp->downstream_ports,
3928 DP_MAX_DOWNSTREAM_PORTS) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003929 return false; /* downstream port status fetch failed */
3930
3931 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07003932}
3933
Adam Jackson0d198322012-05-14 16:05:47 -04003934static void
3935intel_dp_probe_oui(struct intel_dp *intel_dp)
3936{
3937 u8 buf[3];
3938
3939 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3940 return;
3941
Jani Nikula9d1a1032014-03-14 16:51:15 +02003942 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003943 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3944 buf[0], buf[1], buf[2]);
3945
Jani Nikula9d1a1032014-03-14 16:51:15 +02003946 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003947 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3948 buf[0], buf[1], buf[2]);
3949}
3950
Dave Airlie0e32b392014-05-02 14:02:48 +10003951static bool
3952intel_dp_probe_mst(struct intel_dp *intel_dp)
3953{
3954 u8 buf[1];
3955
3956 if (!intel_dp->can_mst)
3957 return false;
3958
3959 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3960 return false;
3961
Dave Airlie0e32b392014-05-02 14:02:48 +10003962 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3963 if (buf[0] & DP_MST_CAP) {
3964 DRM_DEBUG_KMS("Sink is MST capable\n");
3965 intel_dp->is_mst = true;
3966 } else {
3967 DRM_DEBUG_KMS("Sink is not MST capable\n");
3968 intel_dp->is_mst = false;
3969 }
3970 }
Dave Airlie0e32b392014-05-02 14:02:48 +10003971
3972 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3973 return intel_dp->is_mst;
3974}
3975
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07003976static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003977{
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07003978 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
Rodrigo Vivid72f9d92015-11-05 10:50:19 -08003979 struct drm_device *dev = dig_port->base.base.dev;
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07003980 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
Rodrigo Viviad9dc912014-09-16 19:18:12 -04003981 u8 buf;
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07003982 int ret = 0;
Rodrigo Vivic6297842015-11-05 10:50:20 -08003983 int count = 0;
3984 int attempts = 10;
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03003985
3986 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07003987 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07003988 ret = -EIO;
3989 goto out;
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03003990 }
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003991
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003992 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07003993 buf & ~DP_TEST_SINK_START) < 0) {
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07003994 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07003995 ret = -EIO;
3996 goto out;
3997 }
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07003998
Rodrigo Vivic6297842015-11-05 10:50:20 -08003999 do {
4000 intel_wait_for_vblank(dev, intel_crtc->pipe);
4001
4002 if (drm_dp_dpcd_readb(&intel_dp->aux,
4003 DP_TEST_SINK_MISC, &buf) < 0) {
4004 ret = -EIO;
4005 goto out;
4006 }
4007 count = buf & DP_TEST_COUNT_MASK;
4008 } while (--attempts && count);
4009
4010 if (attempts == 0) {
4011 DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
4012 ret = -ETIMEDOUT;
4013 }
4014
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07004015 out:
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004016 hsw_enable_ips(intel_crtc);
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07004017 return ret;
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004018}
4019
4020static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4021{
4022 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
Rodrigo Vivid72f9d92015-11-05 10:50:19 -08004023 struct drm_device *dev = dig_port->base.base.dev;
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004024 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4025 u8 buf;
Rodrigo Vivie5a1cab2015-07-23 16:35:48 -07004026 int ret;
4027
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004028 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4029 return -EIO;
4030
4031 if (!(buf & DP_TEST_CRC_SUPPORTED))
4032 return -ENOTTY;
4033
4034 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4035 return -EIO;
4036
Rodrigo Vivi6d8175d2015-11-05 10:50:22 -08004037 if (buf & DP_TEST_SINK_START) {
4038 ret = intel_dp_sink_crc_stop(intel_dp);
4039 if (ret)
4040 return ret;
4041 }
4042
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004043 hsw_disable_ips(intel_crtc);
4044
4045 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4046 buf | DP_TEST_SINK_START) < 0) {
4047 hsw_enable_ips(intel_crtc);
4048 return -EIO;
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03004049 }
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02004050
Rodrigo Vivid72f9d92015-11-05 10:50:19 -08004051 intel_wait_for_vblank(dev, intel_crtc->pipe);
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004052 return 0;
4053}
4054
4055int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4056{
4057 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4058 struct drm_device *dev = dig_port->base.base.dev;
4059 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4060 u8 buf;
Rodrigo Vivi621d4c72015-07-23 16:35:49 -07004061 int count, ret;
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004062 int attempts = 6;
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004063
4064 ret = intel_dp_sink_crc_start(intel_dp);
4065 if (ret)
4066 return ret;
4067
Rodrigo Viviad9dc912014-09-16 19:18:12 -04004068 do {
Rodrigo Vivi621d4c72015-07-23 16:35:49 -07004069 intel_wait_for_vblank(dev, intel_crtc->pipe);
4070
Rodrigo Vivi1dda5f92014-10-01 07:32:37 -07004071 if (drm_dp_dpcd_readb(&intel_dp->aux,
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03004072 DP_TEST_SINK_MISC, &buf) < 0) {
4073 ret = -EIO;
Rodrigo Viviafe0d672015-07-23 16:35:45 -07004074 goto stop;
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03004075 }
Rodrigo Vivi621d4c72015-07-23 16:35:49 -07004076 count = buf & DP_TEST_COUNT_MASK;
Rodrigo Viviaabc95d2015-07-23 16:35:50 -07004077
Rodrigo Vivi7e38eef2015-11-05 10:50:21 -08004078 } while (--attempts && count == 0);
Rodrigo Viviad9dc912014-09-16 19:18:12 -04004079
4080 if (attempts == 0) {
Rodrigo Vivi7e38eef2015-11-05 10:50:21 -08004081 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4082 ret = -ETIMEDOUT;
4083 goto stop;
4084 }
4085
4086 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4087 ret = -EIO;
4088 goto stop;
Rodrigo Viviad9dc912014-09-16 19:18:12 -04004089 }
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02004090
Rodrigo Viviafe0d672015-07-23 16:35:45 -07004091stop:
Rodrigo Vivi082dcc72015-07-30 16:26:39 -07004092 intel_dp_sink_crc_stop(intel_dp);
Paulo Zanoni4373f0f2015-05-25 18:52:29 -03004093 return ret;
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02004094}
4095
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004096static bool
4097intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4098{
Jani Nikula9d1a1032014-03-14 16:51:15 +02004099 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4100 DP_DEVICE_SERVICE_IRQ_VECTOR,
4101 sink_irq_vector, 1) == 1;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004102}
4103
Dave Airlie0e32b392014-05-02 14:02:48 +10004104static bool
4105intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4106{
4107 int ret;
4108
4109 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4110 DP_SINK_COUNT_ESI,
4111 sink_irq_vector, 14);
4112 if (ret != 14)
4113 return false;
4114
4115 return true;
4116}
4117
Todd Previtec5d5ab72015-04-15 08:38:38 -07004118static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004119{
Todd Previtec5d5ab72015-04-15 08:38:38 -07004120 uint8_t test_result = DP_TEST_ACK;
4121 return test_result;
4122}
4123
4124static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4125{
4126 uint8_t test_result = DP_TEST_NAK;
4127 return test_result;
4128}
4129
4130static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4131{
4132 uint8_t test_result = DP_TEST_NAK;
Todd Previte559be302015-05-04 07:48:20 -07004133 struct intel_connector *intel_connector = intel_dp->attached_connector;
4134 struct drm_connector *connector = &intel_connector->base;
4135
4136 if (intel_connector->detect_edid == NULL ||
Daniel Vetterac6f2e22015-05-08 16:15:41 +02004137 connector->edid_corrupt ||
Todd Previte559be302015-05-04 07:48:20 -07004138 intel_dp->aux.i2c_defer_count > 6) {
4139 /* Check EDID read for NACKs, DEFERs and corruption
4140 * (DP CTS 1.2 Core r1.1)
4141 * 4.2.2.4 : Failed EDID read, I2C_NAK
4142 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4143 * 4.2.2.6 : EDID corruption detected
4144 * Use failsafe mode for all cases
4145 */
4146 if (intel_dp->aux.i2c_nack_count > 0 ||
4147 intel_dp->aux.i2c_defer_count > 0)
4148 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4149 intel_dp->aux.i2c_nack_count,
4150 intel_dp->aux.i2c_defer_count);
4151 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4152 } else {
Thulasimani,Sivakumarf79b468e2015-08-07 15:14:30 +05304153 struct edid *block = intel_connector->detect_edid;
4154
4155 /* We have to write the checksum
4156 * of the last block read
4157 */
4158 block += intel_connector->detect_edid->extensions;
4159
Todd Previte559be302015-05-04 07:48:20 -07004160 if (!drm_dp_dpcd_write(&intel_dp->aux,
4161 DP_TEST_EDID_CHECKSUM,
Thulasimani,Sivakumarf79b468e2015-08-07 15:14:30 +05304162 &block->checksum,
Dan Carpenter5a1cc652015-05-12 21:07:37 +03004163 1))
Todd Previte559be302015-05-04 07:48:20 -07004164 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4165
4166 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4167 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4168 }
4169
4170 /* Set test active flag here so userspace doesn't interrupt things */
4171 intel_dp->compliance_test_active = 1;
4172
Todd Previtec5d5ab72015-04-15 08:38:38 -07004173 return test_result;
4174}
4175
4176static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4177{
4178 uint8_t test_result = DP_TEST_NAK;
4179 return test_result;
4180}
4181
4182static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4183{
4184 uint8_t response = DP_TEST_NAK;
4185 uint8_t rxdata = 0;
4186 int status = 0;
4187
Todd Previtec5d5ab72015-04-15 08:38:38 -07004188 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4189 if (status <= 0) {
4190 DRM_DEBUG_KMS("Could not read test request from sink\n");
4191 goto update_status;
4192 }
4193
4194 switch (rxdata) {
4195 case DP_TEST_LINK_TRAINING:
4196 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4197 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4198 response = intel_dp_autotest_link_training(intel_dp);
4199 break;
4200 case DP_TEST_LINK_VIDEO_PATTERN:
4201 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4202 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4203 response = intel_dp_autotest_video_pattern(intel_dp);
4204 break;
4205 case DP_TEST_LINK_EDID_READ:
4206 DRM_DEBUG_KMS("EDID test requested\n");
4207 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4208 response = intel_dp_autotest_edid(intel_dp);
4209 break;
4210 case DP_TEST_LINK_PHY_TEST_PATTERN:
4211 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4212 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4213 response = intel_dp_autotest_phy_pattern(intel_dp);
4214 break;
4215 default:
4216 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4217 break;
4218 }
4219
4220update_status:
4221 status = drm_dp_dpcd_write(&intel_dp->aux,
4222 DP_TEST_RESPONSE,
4223 &response, 1);
4224 if (status <= 0)
4225 DRM_DEBUG_KMS("Could not write test response to sink\n");
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004226}
4227
Dave Airlie0e32b392014-05-02 14:02:48 +10004228static int
4229intel_dp_check_mst_status(struct intel_dp *intel_dp)
4230{
4231 bool bret;
4232
4233 if (intel_dp->is_mst) {
4234 u8 esi[16] = { 0 };
4235 int ret = 0;
4236 int retry;
4237 bool handled;
4238 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4239go_again:
4240 if (bret == true) {
4241
4242 /* check link status - esi[10] = 0x200c */
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +03004243 if (intel_dp->active_mst_links &&
Ville Syrjälä901c2da2015-08-17 18:05:12 +03004244 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
Dave Airlie0e32b392014-05-02 14:02:48 +10004245 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4246 intel_dp_start_link_train(intel_dp);
Dave Airlie0e32b392014-05-02 14:02:48 +10004247 intel_dp_stop_link_train(intel_dp);
4248 }
4249
Andy Shevchenko6f34cc32015-01-15 13:45:09 +02004250 DRM_DEBUG_KMS("got esi %3ph\n", esi);
Dave Airlie0e32b392014-05-02 14:02:48 +10004251 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4252
4253 if (handled) {
4254 for (retry = 0; retry < 3; retry++) {
4255 int wret;
4256 wret = drm_dp_dpcd_write(&intel_dp->aux,
4257 DP_SINK_COUNT_ESI+1,
4258 &esi[1], 3);
4259 if (wret == 3) {
4260 break;
4261 }
4262 }
4263
4264 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4265 if (bret == true) {
Andy Shevchenko6f34cc32015-01-15 13:45:09 +02004266 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
Dave Airlie0e32b392014-05-02 14:02:48 +10004267 goto go_again;
4268 }
4269 } else
4270 ret = 0;
4271
4272 return ret;
4273 } else {
4274 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4275 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4276 intel_dp->is_mst = false;
4277 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4278 /* send a hotplug event */
4279 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4280 }
4281 }
4282 return -EINVAL;
4283}
4284
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004285/*
4286 * According to DP spec
4287 * 5.1.2:
4288 * 1. Read DPCD
4289 * 2. Configure link according to Receiver Capabilities
4290 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4291 * 4. Check link status on receipt of hot-plug interrupt
4292 */
Damien Lespiaua5146202015-02-10 19:32:22 +00004293static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01004294intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004295{
Dave Airlie5b215bc2014-08-05 10:40:20 +10004296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004297 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004298 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07004299 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004300
Dave Airlie5b215bc2014-08-05 10:40:20 +10004301 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4302
Shubhangi Shrivastava4df69602015-10-28 15:30:36 +05304303 /*
4304 * Clearing compliance test variables to allow capturing
4305 * of values for next automated test request.
4306 */
4307 intel_dp->compliance_test_active = 0;
4308 intel_dp->compliance_test_type = 0;
4309 intel_dp->compliance_test_data = 0;
4310
Maarten Lankhorste02f9a02015-08-05 12:37:08 +02004311 if (!intel_encoder->base.crtc)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004312 return;
4313
Imre Deak1a125d82014-08-18 14:42:46 +03004314 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4315 return;
4316
Keith Packard92fd8fd2011-07-25 19:50:10 -07004317 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07004318 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004319 return;
4320 }
4321
Keith Packard92fd8fd2011-07-25 19:50:10 -07004322 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07004323 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07004324 return;
4325 }
4326
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004327 /* Try to read the source of the interrupt */
4328 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4329 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4330 /* Clear interrupt source */
Jani Nikula9d1a1032014-03-14 16:51:15 +02004331 drm_dp_dpcd_writeb(&intel_dp->aux,
4332 DP_DEVICE_SERVICE_IRQ_VECTOR,
4333 sink_irq_vector);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004334
4335 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
Todd Previte09b1eb12015-04-20 15:27:34 -07004336 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
Jesse Barnesa60f0e32011-10-20 15:09:17 -07004337 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4338 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4339 }
4340
Shubhangi Shrivastava14631e92015-10-14 14:56:49 +05304341 /* if link training is requested we should perform it always */
4342 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4343 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07004344 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
Jani Nikula8e329a02014-06-03 14:56:21 +03004345 intel_encoder->base.name);
Jesse Barnes33a34e42010-09-08 12:42:02 -07004346 intel_dp_start_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03004347 intel_dp_stop_link_train(intel_dp);
Jesse Barnes33a34e42010-09-08 12:42:02 -07004348 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004349}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004350
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004351/* XXX this is probably wrong for multiple downstream ports */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004352static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07004353intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04004354{
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004355 uint8_t *dpcd = intel_dp->dpcd;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004356 uint8_t type;
4357
4358 if (!intel_dp_get_dpcd(intel_dp))
4359 return connector_status_disconnected;
4360
4361 /* if there's no downstream port, we're done */
4362 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
Keith Packard26d61aa2011-07-25 20:01:09 -07004363 return connector_status_connected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004364
4365 /* If we're HPD-aware, SINK_COUNT changes dynamically */
Jani Nikulac9ff1602013-09-27 14:48:42 +03004366 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4367 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
Adam Jackson23235172012-09-20 16:42:45 -04004368 uint8_t reg;
Jani Nikula9d1a1032014-03-14 16:51:15 +02004369
4370 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4371 &reg, 1) < 0)
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004372 return connector_status_unknown;
Jani Nikula9d1a1032014-03-14 16:51:15 +02004373
Adam Jackson23235172012-09-20 16:42:45 -04004374 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4375 : connector_status_disconnected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004376 }
4377
4378 /* If no HPD, poke DDC gently */
Jani Nikula0b998362014-03-14 16:51:17 +02004379 if (drm_probe_ddc(&intel_dp->aux.ddc))
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004380 return connector_status_connected;
4381
4382 /* Well we tried, say unknown for unreliable port types */
Jani Nikulac9ff1602013-09-27 14:48:42 +03004383 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4384 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4385 if (type == DP_DS_PORT_TYPE_VGA ||
4386 type == DP_DS_PORT_TYPE_NON_EDID)
4387 return connector_status_unknown;
4388 } else {
4389 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4390 DP_DWN_STRM_PORT_TYPE_MASK;
4391 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4392 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4393 return connector_status_unknown;
4394 }
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04004395
4396 /* Anything else is out of spec, warn and ignore */
4397 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
Keith Packard26d61aa2011-07-25 20:01:09 -07004398 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04004399}
4400
4401static enum drm_connector_status
Chris Wilsond410b562014-09-02 20:03:59 +01004402edp_detect(struct intel_dp *intel_dp)
4403{
4404 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4405 enum drm_connector_status status;
4406
4407 status = intel_panel_detect(dev);
4408 if (status == connector_status_unknown)
4409 status = connector_status_connected;
4410
4411 return status;
4412}
4413
Jani Nikulab93433c2015-08-20 10:47:36 +03004414static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4415 struct intel_digital_port *port)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004416{
Jani Nikulab93433c2015-08-20 10:47:36 +03004417 u32 bit;
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07004418
Jani Nikula0df53b72015-08-20 10:47:40 +03004419 switch (port->port) {
4420 case PORT_A:
4421 return true;
4422 case PORT_B:
4423 bit = SDE_PORTB_HOTPLUG;
4424 break;
4425 case PORT_C:
4426 bit = SDE_PORTC_HOTPLUG;
4427 break;
4428 case PORT_D:
4429 bit = SDE_PORTD_HOTPLUG;
4430 break;
4431 default:
4432 MISSING_CASE(port->port);
4433 return false;
4434 }
4435
4436 return I915_READ(SDEISR) & bit;
4437}
4438
4439static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4440 struct intel_digital_port *port)
4441{
4442 u32 bit;
4443
4444 switch (port->port) {
4445 case PORT_A:
4446 return true;
4447 case PORT_B:
4448 bit = SDE_PORTB_HOTPLUG_CPT;
4449 break;
4450 case PORT_C:
4451 bit = SDE_PORTC_HOTPLUG_CPT;
4452 break;
4453 case PORT_D:
4454 bit = SDE_PORTD_HOTPLUG_CPT;
4455 break;
Jani Nikulaa78695d2015-09-18 15:54:50 +03004456 case PORT_E:
4457 bit = SDE_PORTE_HOTPLUG_SPT;
4458 break;
Jani Nikula0df53b72015-08-20 10:47:40 +03004459 default:
4460 MISSING_CASE(port->port);
4461 return false;
Jani Nikulab93433c2015-08-20 10:47:36 +03004462 }
Damien Lespiau1b469632012-12-13 16:09:01 +00004463
Jani Nikulab93433c2015-08-20 10:47:36 +03004464 return I915_READ(SDEISR) & bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004465}
4466
Jani Nikula7e66bcf2015-08-20 10:47:39 +03004467static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
Jani Nikula1d245982015-08-20 10:47:37 +03004468 struct intel_digital_port *port)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004469{
Jani Nikula9642c812015-08-20 10:47:41 +03004470 u32 bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004471
Jani Nikula9642c812015-08-20 10:47:41 +03004472 switch (port->port) {
4473 case PORT_B:
4474 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4475 break;
4476 case PORT_C:
4477 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4478 break;
4479 case PORT_D:
4480 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4481 break;
4482 default:
4483 MISSING_CASE(port->port);
4484 return false;
4485 }
4486
4487 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4488}
4489
4490static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4491 struct intel_digital_port *port)
4492{
4493 u32 bit;
4494
4495 switch (port->port) {
4496 case PORT_B:
4497 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4498 break;
4499 case PORT_C:
4500 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4501 break;
4502 case PORT_D:
4503 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4504 break;
4505 default:
4506 MISSING_CASE(port->port);
4507 return false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004508 }
4509
Jani Nikula1d245982015-08-20 10:47:37 +03004510 return I915_READ(PORT_HOTPLUG_STAT) & bit;
Dave Airlie2a592be2014-09-01 16:58:12 +10004511}
4512
Jani Nikulae464bfd2015-08-20 10:47:42 +03004513static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
Sonika Jindale2ec35a2015-09-11 16:58:32 +05304514 struct intel_digital_port *intel_dig_port)
Jani Nikulae464bfd2015-08-20 10:47:42 +03004515{
Sonika Jindale2ec35a2015-09-11 16:58:32 +05304516 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4517 enum port port;
Jani Nikulae464bfd2015-08-20 10:47:42 +03004518 u32 bit;
4519
Sonika Jindale2ec35a2015-09-11 16:58:32 +05304520 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4521 switch (port) {
Jani Nikulae464bfd2015-08-20 10:47:42 +03004522 case PORT_A:
4523 bit = BXT_DE_PORT_HP_DDIA;
4524 break;
4525 case PORT_B:
4526 bit = BXT_DE_PORT_HP_DDIB;
4527 break;
4528 case PORT_C:
4529 bit = BXT_DE_PORT_HP_DDIC;
4530 break;
4531 default:
Sonika Jindale2ec35a2015-09-11 16:58:32 +05304532 MISSING_CASE(port);
Jani Nikulae464bfd2015-08-20 10:47:42 +03004533 return false;
4534 }
4535
4536 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4537}
4538
Jani Nikula7e66bcf2015-08-20 10:47:39 +03004539/*
4540 * intel_digital_port_connected - is the specified port connected?
4541 * @dev_priv: i915 private structure
4542 * @port: the port to test
4543 *
4544 * Return %true if @port is connected, %false otherwise.
4545 */
Sonika Jindal237ed862015-09-15 09:44:20 +05304546bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
Jani Nikula7e66bcf2015-08-20 10:47:39 +03004547 struct intel_digital_port *port)
4548{
Jani Nikula0df53b72015-08-20 10:47:40 +03004549 if (HAS_PCH_IBX(dev_priv))
Jani Nikula7e66bcf2015-08-20 10:47:39 +03004550 return ibx_digital_port_connected(dev_priv, port);
Jani Nikula0df53b72015-08-20 10:47:40 +03004551 if (HAS_PCH_SPLIT(dev_priv))
4552 return cpt_digital_port_connected(dev_priv, port);
Jani Nikulae464bfd2015-08-20 10:47:42 +03004553 else if (IS_BROXTON(dev_priv))
4554 return bxt_digital_port_connected(dev_priv, port);
Wayne Boyer666a4532015-12-09 12:29:35 -08004555 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Jani Nikula9642c812015-08-20 10:47:41 +03004556 return vlv_digital_port_connected(dev_priv, port);
Jani Nikula7e66bcf2015-08-20 10:47:39 +03004557 else
4558 return g4x_digital_port_connected(dev_priv, port);
4559}
4560
Keith Packard8c241fe2011-09-28 16:38:44 -07004561static struct edid *
Chris Wilsonbeb60602014-09-02 20:04:00 +01004562intel_dp_get_edid(struct intel_dp *intel_dp)
Keith Packard8c241fe2011-09-28 16:38:44 -07004563{
Chris Wilsonbeb60602014-09-02 20:04:00 +01004564 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packard8c241fe2011-09-28 16:38:44 -07004565
Jani Nikula9cd300e2012-10-19 14:51:52 +03004566 /* use cached edid if we have one */
4567 if (intel_connector->edid) {
Jani Nikula9cd300e2012-10-19 14:51:52 +03004568 /* invalid edid */
4569 if (IS_ERR(intel_connector->edid))
Jesse Barnesd6f24d02012-06-14 15:28:33 -04004570 return NULL;
4571
Jani Nikula55e9ede2013-10-01 10:38:54 +03004572 return drm_edid_duplicate(intel_connector->edid);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004573 } else
4574 return drm_get_edid(&intel_connector->base,
4575 &intel_dp->aux.ddc);
Keith Packard8c241fe2011-09-28 16:38:44 -07004576}
4577
Chris Wilsonbeb60602014-09-02 20:04:00 +01004578static void
4579intel_dp_set_edid(struct intel_dp *intel_dp)
Keith Packard8c241fe2011-09-28 16:38:44 -07004580{
Chris Wilsonbeb60602014-09-02 20:04:00 +01004581 struct intel_connector *intel_connector = intel_dp->attached_connector;
4582 struct edid *edid;
Keith Packard8c241fe2011-09-28 16:38:44 -07004583
Chris Wilsonbeb60602014-09-02 20:04:00 +01004584 edid = intel_dp_get_edid(intel_dp);
4585 intel_connector->detect_edid = edid;
Jani Nikula9cd300e2012-10-19 14:51:52 +03004586
Chris Wilsonbeb60602014-09-02 20:04:00 +01004587 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4588 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4589 else
4590 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4591}
Jesse Barnesd6f24d02012-06-14 15:28:33 -04004592
Chris Wilsonbeb60602014-09-02 20:04:00 +01004593static void
4594intel_dp_unset_edid(struct intel_dp *intel_dp)
4595{
4596 struct intel_connector *intel_connector = intel_dp->attached_connector;
4597
4598 kfree(intel_connector->detect_edid);
4599 intel_connector->detect_edid = NULL;
4600
4601 intel_dp->has_audio = false;
4602}
4603
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004604static enum drm_connector_status
4605intel_dp_detect(struct drm_connector *connector, bool force)
4606{
4607 struct intel_dp *intel_dp = intel_attached_dp(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -02004608 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4609 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02004610 struct drm_device *dev = connector->dev;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004611 enum drm_connector_status status;
Imre Deak671dedd2014-03-05 16:20:53 +02004612 enum intel_display_power_domain power_domain;
Dave Airlie0e32b392014-05-02 14:02:48 +10004613 bool ret;
Todd Previte09b1eb12015-04-20 15:27:34 -07004614 u8 sink_irq_vector;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004615
Chris Wilson164c8592013-07-20 20:27:08 +01004616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03004617 connector->base.id, connector->name);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004618 intel_dp_unset_edid(intel_dp);
Chris Wilson164c8592013-07-20 20:27:08 +01004619
Dave Airlie0e32b392014-05-02 14:02:48 +10004620 if (intel_dp->is_mst) {
4621 /* MST devices are disconnected from a monitor POV */
4622 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4623 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Chris Wilsonbeb60602014-09-02 20:04:00 +01004624 return connector_status_disconnected;
Dave Airlie0e32b392014-05-02 14:02:48 +10004625 }
4626
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004627 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4628 intel_display_power_get(to_i915(dev), power_domain);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004629
Chris Wilsond410b562014-09-02 20:03:59 +01004630 /* Can't disconnect eDP, but you can close the lid... */
4631 if (is_edp(intel_dp))
4632 status = edp_detect(intel_dp);
Ander Conselvan de Oliveirac555a812015-11-18 17:19:30 +02004633 else if (intel_digital_port_connected(to_i915(dev),
4634 dp_to_dig_port(intel_dp)))
4635 status = intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004636 else
Ander Conselvan de Oliveirac555a812015-11-18 17:19:30 +02004637 status = connector_status_disconnected;
4638
Shubhangi Shrivastava4df69602015-10-28 15:30:36 +05304639 if (status != connector_status_connected) {
4640 intel_dp->compliance_test_active = 0;
4641 intel_dp->compliance_test_type = 0;
4642 intel_dp->compliance_test_data = 0;
4643
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004644 goto out;
Shubhangi Shrivastava4df69602015-10-28 15:30:36 +05304645 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004646
Adam Jackson0d198322012-05-14 16:05:47 -04004647 intel_dp_probe_oui(intel_dp);
4648
Dave Airlie0e32b392014-05-02 14:02:48 +10004649 ret = intel_dp_probe_mst(intel_dp);
4650 if (ret) {
4651 /* if we are in MST mode then this connector
4652 won't appear connected or have anything with EDID on it */
4653 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4654 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4655 status = connector_status_disconnected;
4656 goto out;
4657 }
4658
Shubhangi Shrivastava4df69602015-10-28 15:30:36 +05304659 /*
4660 * Clearing NACK and defer counts to get their exact values
4661 * while reading EDID which are required by Compliance tests
4662 * 4.2.2.4 and 4.2.2.5
4663 */
4664 intel_dp->aux.i2c_nack_count = 0;
4665 intel_dp->aux.i2c_defer_count = 0;
4666
Chris Wilsonbeb60602014-09-02 20:04:00 +01004667 intel_dp_set_edid(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08004668
Paulo Zanonid63885d2012-10-26 19:05:49 -02004669 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4670 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004671 status = connector_status_connected;
4672
Todd Previte09b1eb12015-04-20 15:27:34 -07004673 /* Try to read the source of the interrupt */
4674 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4675 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4676 /* Clear interrupt source */
4677 drm_dp_dpcd_writeb(&intel_dp->aux,
4678 DP_DEVICE_SERVICE_IRQ_VECTOR,
4679 sink_irq_vector);
4680
4681 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4682 intel_dp_handle_test_request(intel_dp);
4683 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4684 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4685 }
4686
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004687out:
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004688 intel_display_power_put(to_i915(dev), power_domain);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02004689 return status;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004690}
4691
Chris Wilsonbeb60602014-09-02 20:04:00 +01004692static void
4693intel_dp_force(struct drm_connector *connector)
4694{
4695 struct intel_dp *intel_dp = intel_attached_dp(connector);
4696 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004697 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004698 enum intel_display_power_domain power_domain;
4699
4700 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4701 connector->base.id, connector->name);
4702 intel_dp_unset_edid(intel_dp);
4703
4704 if (connector->status != connector_status_connected)
4705 return;
4706
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004707 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4708 intel_display_power_get(dev_priv, power_domain);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004709
4710 intel_dp_set_edid(intel_dp);
4711
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004712 intel_display_power_put(dev_priv, power_domain);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004713
4714 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4715 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4716}
4717
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004718static int intel_dp_get_modes(struct drm_connector *connector)
4719{
Jani Nikuladd06f902012-10-19 14:51:50 +03004720 struct intel_connector *intel_connector = to_intel_connector(connector);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004721 struct edid *edid;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004722
Chris Wilsonbeb60602014-09-02 20:04:00 +01004723 edid = intel_connector->detect_edid;
4724 if (edid) {
4725 int ret = intel_connector_update_modes(connector, edid);
4726 if (ret)
4727 return ret;
4728 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004729
Jani Nikulaf8779fd2012-10-19 14:51:48 +03004730 /* if eDP has no EDID, fall back to fixed mode */
Chris Wilsonbeb60602014-09-02 20:04:00 +01004731 if (is_edp(intel_attached_dp(connector)) &&
4732 intel_connector->panel.fixed_mode) {
Jani Nikulaf8779fd2012-10-19 14:51:48 +03004733 struct drm_display_mode *mode;
Chris Wilsonbeb60602014-09-02 20:04:00 +01004734
4735 mode = drm_mode_duplicate(connector->dev,
Jani Nikuladd06f902012-10-19 14:51:50 +03004736 intel_connector->panel.fixed_mode);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03004737 if (mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004738 drm_mode_probed_add(connector, mode);
4739 return 1;
4740 }
4741 }
Chris Wilsonbeb60602014-09-02 20:04:00 +01004742
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004743 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004744}
4745
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004746static bool
4747intel_dp_detect_audio(struct drm_connector *connector)
4748{
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004749 bool has_audio = false;
Chris Wilsonbeb60602014-09-02 20:04:00 +01004750 struct edid *edid;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004751
Chris Wilsonbeb60602014-09-02 20:04:00 +01004752 edid = to_intel_connector(connector)->detect_edid;
4753 if (edid)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004754 has_audio = drm_detect_monitor_audio(edid);
Imre Deak671dedd2014-03-05 16:20:53 +02004755
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004756 return has_audio;
4757}
4758
Chris Wilsonf6849602010-09-19 09:29:33 +01004759static int
4760intel_dp_set_property(struct drm_connector *connector,
4761 struct drm_property *property,
4762 uint64_t val)
4763{
Chris Wilsone953fd72011-02-21 22:23:52 +00004764 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Yuly Novikov53b41832012-10-26 12:04:00 +03004765 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004766 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4767 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonf6849602010-09-19 09:29:33 +01004768 int ret;
4769
Rob Clark662595d2012-10-11 20:36:04 -05004770 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilsonf6849602010-09-19 09:29:33 +01004771 if (ret)
4772 return ret;
4773
Chris Wilson3f43c482011-05-12 22:17:24 +01004774 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004775 int i = val;
4776 bool has_audio;
4777
4778 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01004779 return 0;
4780
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004781 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01004782
Daniel Vetterc3e5f672012-02-23 17:14:47 +01004783 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004784 has_audio = intel_dp_detect_audio(connector);
4785 else
Daniel Vetterc3e5f672012-02-23 17:14:47 +01004786 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004787
4788 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01004789 return 0;
4790
Chris Wilson1aad7ac2011-02-09 18:46:58 +00004791 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01004792 goto done;
4793 }
4794
Chris Wilsone953fd72011-02-21 22:23:52 +00004795 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02004796 bool old_auto = intel_dp->color_range_auto;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03004797 bool old_range = intel_dp->limited_color_range;
Daniel Vetterae4edb82013-04-22 17:07:23 +02004798
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004799 switch (val) {
4800 case INTEL_BROADCAST_RGB_AUTO:
4801 intel_dp->color_range_auto = true;
4802 break;
4803 case INTEL_BROADCAST_RGB_FULL:
4804 intel_dp->color_range_auto = false;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03004805 intel_dp->limited_color_range = false;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004806 break;
4807 case INTEL_BROADCAST_RGB_LIMITED:
4808 intel_dp->color_range_auto = false;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03004809 intel_dp->limited_color_range = true;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02004810 break;
4811 default:
4812 return -EINVAL;
4813 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02004814
4815 if (old_auto == intel_dp->color_range_auto &&
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +03004816 old_range == intel_dp->limited_color_range)
Daniel Vetterae4edb82013-04-22 17:07:23 +02004817 return 0;
4818
Chris Wilsone953fd72011-02-21 22:23:52 +00004819 goto done;
4820 }
4821
Yuly Novikov53b41832012-10-26 12:04:00 +03004822 if (is_edp(intel_dp) &&
4823 property == connector->dev->mode_config.scaling_mode_property) {
4824 if (val == DRM_MODE_SCALE_NONE) {
4825 DRM_DEBUG_KMS("no scaling not supported\n");
4826 return -EINVAL;
4827 }
4828
4829 if (intel_connector->panel.fitting_mode == val) {
4830 /* the eDP scaling property is not changed */
4831 return 0;
4832 }
4833 intel_connector->panel.fitting_mode = val;
4834
4835 goto done;
4836 }
4837
Chris Wilsonf6849602010-09-19 09:29:33 +01004838 return -EINVAL;
4839
4840done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00004841 if (intel_encoder->base.crtc)
4842 intel_crtc_restore_mode(intel_encoder->base.crtc);
Chris Wilsonf6849602010-09-19 09:29:33 +01004843
4844 return 0;
4845}
4846
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004847static void
Paulo Zanoni73845ad2013-06-12 17:27:30 -03004848intel_dp_connector_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004849{
Jani Nikula1d508702012-10-19 14:51:49 +03004850 struct intel_connector *intel_connector = to_intel_connector(connector);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02004851
Chris Wilson10e972d2014-09-04 21:43:45 +01004852 kfree(intel_connector->detect_edid);
Chris Wilsonbeb60602014-09-02 20:04:00 +01004853
Jani Nikula9cd300e2012-10-19 14:51:52 +03004854 if (!IS_ERR_OR_NULL(intel_connector->edid))
4855 kfree(intel_connector->edid);
4856
Paulo Zanoniacd8db102013-06-12 17:27:23 -03004857 /* Can't call is_edp() since the encoder may have been destroyed
4858 * already. */
4859 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
Jani Nikula1d508702012-10-19 14:51:49 +03004860 intel_panel_fini(&intel_connector->panel);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02004861
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004862 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08004863 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004864}
4865
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004866void intel_dp_encoder_destroy(struct drm_encoder *encoder)
Daniel Vetter24d05922010-08-20 18:08:28 +02004867{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004868 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4869 struct intel_dp *intel_dp = &intel_dig_port->dp;
Daniel Vetter24d05922010-08-20 18:08:28 +02004870
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02004871 intel_dp_aux_fini(intel_dp);
Dave Airlie0e32b392014-05-02 14:02:48 +10004872 intel_dp_mst_encoder_cleanup(intel_dig_port);
Keith Packardbd943152011-09-18 23:09:52 -07004873 if (is_edp(intel_dp)) {
4874 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Ville Syrjälä951468f2014-09-04 14:55:31 +03004875 /*
4876 * vdd might still be enabled do to the delayed vdd off.
4877 * Make sure vdd is actually turned off here.
4878 */
Ville Syrjälä773538e82014-09-04 14:54:56 +03004879 pps_lock(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01004880 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03004881 pps_unlock(intel_dp);
4882
Clint Taylor01527b32014-07-07 13:01:46 -07004883 if (intel_dp->edp_notifier.notifier_call) {
4884 unregister_reboot_notifier(&intel_dp->edp_notifier);
4885 intel_dp->edp_notifier.notifier_call = NULL;
4886 }
Keith Packardbd943152011-09-18 23:09:52 -07004887 }
Imre Deakc8bd0e42014-12-12 17:57:38 +02004888 drm_encoder_cleanup(encoder);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02004889 kfree(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02004890}
4891
Imre Deak07f9cd02014-08-18 14:42:45 +03004892static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4893{
4894 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4895
4896 if (!is_edp(intel_dp))
4897 return;
4898
Ville Syrjälä951468f2014-09-04 14:55:31 +03004899 /*
4900 * vdd might still be enabled do to the delayed vdd off.
4901 * Make sure vdd is actually turned off here.
4902 */
Ville Syrjäläafa4e532014-11-25 15:43:48 +02004903 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Ville Syrjälä773538e82014-09-04 14:54:56 +03004904 pps_lock(intel_dp);
Imre Deak07f9cd02014-08-18 14:42:45 +03004905 edp_panel_vdd_off_sync(intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03004906 pps_unlock(intel_dp);
Imre Deak07f9cd02014-08-18 14:42:45 +03004907}
4908
Ville Syrjälä49e6bc52014-10-28 16:15:52 +02004909static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4910{
4911 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4912 struct drm_device *dev = intel_dig_port->base.base.dev;
4913 struct drm_i915_private *dev_priv = dev->dev_private;
4914 enum intel_display_power_domain power_domain;
4915
4916 lockdep_assert_held(&dev_priv->pps_mutex);
4917
4918 if (!edp_have_panel_vdd(intel_dp))
4919 return;
4920
4921 /*
4922 * The VDD bit needs a power domain reference, so if the bit is
4923 * already enabled when we boot or resume, grab this reference and
4924 * schedule a vdd off, so we don't hold on to the reference
4925 * indefinitely.
4926 */
4927 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
Ville Syrjälä25f78f52015-11-16 15:01:04 +01004928 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
Ville Syrjälä49e6bc52014-10-28 16:15:52 +02004929 intel_display_power_get(dev_priv, power_domain);
4930
4931 edp_panel_vdd_schedule_off(intel_dp);
4932}
4933
Imre Deak6d93c0c2014-07-31 14:03:36 +03004934static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4935{
Ville Syrjälä49e6bc52014-10-28 16:15:52 +02004936 struct intel_dp *intel_dp;
4937
4938 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4939 return;
4940
4941 intel_dp = enc_to_intel_dp(encoder);
4942
4943 pps_lock(intel_dp);
4944
4945 /*
4946 * Read out the current power sequencer assignment,
4947 * in case the BIOS did something with it.
4948 */
Wayne Boyer666a4532015-12-09 12:29:35 -08004949 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
Ville Syrjälä49e6bc52014-10-28 16:15:52 +02004950 vlv_initial_power_sequencer_setup(intel_dp);
4951
4952 intel_edp_panel_vdd_sanitize(intel_dp);
4953
4954 pps_unlock(intel_dp);
Imre Deak6d93c0c2014-07-31 14:03:36 +03004955}
4956
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004957static const struct drm_connector_funcs intel_dp_connector_funcs = {
Maarten Lankhorst4d688a22015-08-05 12:37:06 +02004958 .dpms = drm_atomic_helper_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004959 .detect = intel_dp_detect,
Chris Wilsonbeb60602014-09-02 20:04:00 +01004960 .force = intel_dp_force,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004961 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01004962 .set_property = intel_dp_set_property,
Matt Roper2545e4a2015-01-22 16:51:27 -08004963 .atomic_get_property = intel_connector_atomic_get_property,
Paulo Zanoni73845ad2013-06-12 17:27:30 -03004964 .destroy = intel_dp_connector_destroy,
Matt Roperc6f95f22015-01-22 16:50:32 -08004965 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Ander Conselvan de Oliveira98969722015-03-20 16:18:06 +02004966 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004967};
4968
4969static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4970 .get_modes = intel_dp_get_modes,
4971 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01004972 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004973};
4974
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004975static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Imre Deak6d93c0c2014-07-31 14:03:36 +03004976 .reset = intel_dp_encoder_reset,
Daniel Vetter24d05922010-08-20 18:08:28 +02004977 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004978};
4979
Daniel Vetterb2c5c182015-01-23 06:00:31 +01004980enum irqreturn
Dave Airlie13cf5502014-06-18 11:29:35 +10004981intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4982{
4983 struct intel_dp *intel_dp = &intel_dig_port->dp;
Imre Deak1c767b32014-08-18 14:42:42 +03004984 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Dave Airlie0e32b392014-05-02 14:02:48 +10004985 struct drm_device *dev = intel_dig_port->base.base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak1c767b32014-08-18 14:42:42 +03004987 enum intel_display_power_domain power_domain;
Daniel Vetterb2c5c182015-01-23 06:00:31 +01004988 enum irqreturn ret = IRQ_NONE;
Imre Deak1c767b32014-08-18 14:42:42 +03004989
Takashi Iwai25400582015-11-19 12:09:56 +01004990 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4991 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
Dave Airlie0e32b392014-05-02 14:02:48 +10004992 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
Dave Airlie13cf5502014-06-18 11:29:35 +10004993
Ville Syrjälä7a7f84c2014-10-16 20:46:10 +03004994 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4995 /*
4996 * vdd off can generate a long pulse on eDP which
4997 * would require vdd on to handle it, and thus we
4998 * would end up in an endless cycle of
4999 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5000 */
5001 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5002 port_name(intel_dig_port->port));
Ville Syrjäläa8b3d522015-02-10 14:11:46 +02005003 return IRQ_HANDLED;
Ville Syrjälä7a7f84c2014-10-16 20:46:10 +03005004 }
5005
Ville Syrjälä26fbb772014-08-11 18:37:37 +03005006 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5007 port_name(intel_dig_port->port),
Dave Airlie0e32b392014-05-02 14:02:48 +10005008 long_hpd ? "long" : "short");
Dave Airlie13cf5502014-06-18 11:29:35 +10005009
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005010 power_domain = intel_display_port_aux_power_domain(intel_encoder);
Imre Deak1c767b32014-08-18 14:42:42 +03005011 intel_display_power_get(dev_priv, power_domain);
5012
Dave Airlie0e32b392014-05-02 14:02:48 +10005013 if (long_hpd) {
Mika Kahola5fa836a2015-04-29 09:17:40 +03005014 /* indicate that we need to restart link training */
5015 intel_dp->train_set_valid = false;
Dave Airlie2a592be2014-09-01 16:58:12 +10005016
Jani Nikula7e66bcf2015-08-20 10:47:39 +03005017 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5018 goto mst_fail;
Dave Airlie0e32b392014-05-02 14:02:48 +10005019
5020 if (!intel_dp_get_dpcd(intel_dp)) {
5021 goto mst_fail;
5022 }
5023
5024 intel_dp_probe_oui(intel_dp);
5025
Ville Syrjäläd14e7b62015-08-20 19:37:29 +03005026 if (!intel_dp_probe_mst(intel_dp)) {
5027 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5028 intel_dp_check_link_status(intel_dp);
5029 drm_modeset_unlock(&dev->mode_config.connection_mutex);
Dave Airlie0e32b392014-05-02 14:02:48 +10005030 goto mst_fail;
Ville Syrjäläd14e7b62015-08-20 19:37:29 +03005031 }
Dave Airlie0e32b392014-05-02 14:02:48 +10005032 } else {
5033 if (intel_dp->is_mst) {
Imre Deak1c767b32014-08-18 14:42:42 +03005034 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
Dave Airlie0e32b392014-05-02 14:02:48 +10005035 goto mst_fail;
5036 }
5037
5038 if (!intel_dp->is_mst) {
Dave Airlie5b215bc2014-08-05 10:40:20 +10005039 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
Dave Airlie0e32b392014-05-02 14:02:48 +10005040 intel_dp_check_link_status(intel_dp);
Dave Airlie5b215bc2014-08-05 10:40:20 +10005041 drm_modeset_unlock(&dev->mode_config.connection_mutex);
Dave Airlie0e32b392014-05-02 14:02:48 +10005042 }
5043 }
Daniel Vetterb2c5c182015-01-23 06:00:31 +01005044
5045 ret = IRQ_HANDLED;
5046
Imre Deak1c767b32014-08-18 14:42:42 +03005047 goto put_power;
Dave Airlie0e32b392014-05-02 14:02:48 +10005048mst_fail:
5049 /* if we were in MST mode, and device is not there get out of MST mode */
5050 if (intel_dp->is_mst) {
5051 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5052 intel_dp->is_mst = false;
5053 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5054 }
Imre Deak1c767b32014-08-18 14:42:42 +03005055put_power:
5056 intel_display_power_put(dev_priv, power_domain);
5057
5058 return ret;
Dave Airlie13cf5502014-06-18 11:29:35 +10005059}
5060
Rodrigo Vivi477ec322015-08-06 15:51:39 +08005061/* check the VBT to see whether the eDP is on another port */
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02005062bool intel_dp_is_edp(struct drm_device *dev, enum port port)
Zhao Yakui36e83a12010-06-12 14:32:21 +08005063{
5064 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03005065 union child_device_config *p_child;
Zhao Yakui36e83a12010-06-12 14:32:21 +08005066 int i;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02005067 static const short port_mapping[] = {
Rodrigo Vivi477ec322015-08-06 15:51:39 +08005068 [PORT_B] = DVO_PORT_DPB,
5069 [PORT_C] = DVO_PORT_DPC,
5070 [PORT_D] = DVO_PORT_DPD,
5071 [PORT_E] = DVO_PORT_DPE,
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02005072 };
Zhao Yakui36e83a12010-06-12 14:32:21 +08005073
Ville Syrjälä53ce81a2015-09-11 21:04:38 +03005074 /*
5075 * eDP not supported on g4x. so bail out early just
5076 * for a bit extra safety in case the VBT is bonkers.
5077 */
5078 if (INTEL_INFO(dev)->gen < 5)
5079 return false;
5080
Ville Syrjälä3b32a352013-11-01 18:22:41 +02005081 if (port == PORT_A)
5082 return true;
5083
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005084 if (!dev_priv->vbt.child_dev_num)
Zhao Yakui36e83a12010-06-12 14:32:21 +08005085 return false;
5086
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005087 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5088 p_child = dev_priv->vbt.child_dev + i;
Zhao Yakui36e83a12010-06-12 14:32:21 +08005089
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02005090 if (p_child->common.dvo_port == port_mapping[port] &&
Ville Syrjäläf02586d2013-11-01 20:32:08 +02005091 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5092 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
Zhao Yakui36e83a12010-06-12 14:32:21 +08005093 return true;
5094 }
5095 return false;
5096}
5097
Dave Airlie0e32b392014-05-02 14:02:48 +10005098void
Chris Wilsonf6849602010-09-19 09:29:33 +01005099intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5100{
Yuly Novikov53b41832012-10-26 12:04:00 +03005101 struct intel_connector *intel_connector = to_intel_connector(connector);
5102
Chris Wilson3f43c482011-05-12 22:17:24 +01005103 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00005104 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02005105 intel_dp->color_range_auto = true;
Yuly Novikov53b41832012-10-26 12:04:00 +03005106
5107 if (is_edp(intel_dp)) {
5108 drm_mode_create_scaling_mode_property(connector->dev);
Rob Clark6de6d842012-10-11 20:36:04 -05005109 drm_object_attach_property(
5110 &connector->base,
Yuly Novikov53b41832012-10-26 12:04:00 +03005111 connector->dev->mode_config.scaling_mode_property,
Yuly Novikov8e740cd2012-10-26 12:04:01 +03005112 DRM_MODE_SCALE_ASPECT);
5113 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
Yuly Novikov53b41832012-10-26 12:04:00 +03005114 }
Chris Wilsonf6849602010-09-19 09:29:33 +01005115}
5116
Imre Deakdada1a92014-01-29 13:25:41 +02005117static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5118{
5119 intel_dp->last_power_cycle = jiffies;
5120 intel_dp->last_power_on = jiffies;
5121 intel_dp->last_backlight_off = jiffies;
5122}
5123
Daniel Vetter67a54562012-10-20 20:57:45 +02005124static void
5125intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005126 struct intel_dp *intel_dp)
Daniel Vetter67a54562012-10-20 20:57:45 +02005127{
5128 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005129 struct edp_power_seq cur, vbt, spec,
5130 *final = &intel_dp->pps_delays;
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305131 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005132 i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07005133
Ville Syrjäläe39b9992014-09-04 14:53:14 +03005134 lockdep_assert_held(&dev_priv->pps_mutex);
5135
Ville Syrjälä81ddbc62014-10-16 21:27:31 +03005136 /* already initialized? */
5137 if (final->t11_t12 != 0)
5138 return;
5139
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305140 if (IS_BROXTON(dev)) {
5141 /*
5142 * TODO: BXT has 2 sets of PPS registers.
5143 * Correct Register for Broxton need to be identified
5144 * using VBT. hardcoding for now
5145 */
5146 pp_ctrl_reg = BXT_PP_CONTROL(0);
5147 pp_on_reg = BXT_PP_ON_DELAYS(0);
5148 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5149 } else if (HAS_PCH_SPLIT(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03005150 pp_ctrl_reg = PCH_PP_CONTROL;
Jesse Barnes453c5422013-03-28 09:55:41 -07005151 pp_on_reg = PCH_PP_ON_DELAYS;
5152 pp_off_reg = PCH_PP_OFF_DELAYS;
5153 pp_div_reg = PCH_PP_DIVISOR;
5154 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03005155 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5156
5157 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5158 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5159 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5160 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07005161 }
Daniel Vetter67a54562012-10-20 20:57:45 +02005162
5163 /* Workaround: Need to write PP_CONTROL with the unlock key as
5164 * the very first thing. */
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305165 pp_ctl = ironlake_get_pp_control(intel_dp);
Daniel Vetter67a54562012-10-20 20:57:45 +02005166
Jesse Barnes453c5422013-03-28 09:55:41 -07005167 pp_on = I915_READ(pp_on_reg);
5168 pp_off = I915_READ(pp_off_reg);
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305169 if (!IS_BROXTON(dev)) {
5170 I915_WRITE(pp_ctrl_reg, pp_ctl);
5171 pp_div = I915_READ(pp_div_reg);
5172 }
Daniel Vetter67a54562012-10-20 20:57:45 +02005173
5174 /* Pull timing values out of registers */
5175 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5176 PANEL_POWER_UP_DELAY_SHIFT;
5177
5178 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5179 PANEL_LIGHT_ON_DELAY_SHIFT;
5180
5181 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5182 PANEL_LIGHT_OFF_DELAY_SHIFT;
5183
5184 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5185 PANEL_POWER_DOWN_DELAY_SHIFT;
5186
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305187 if (IS_BROXTON(dev)) {
5188 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5189 BXT_POWER_CYCLE_DELAY_SHIFT;
5190 if (tmp > 0)
5191 cur.t11_t12 = (tmp - 1) * 1000;
5192 else
5193 cur.t11_t12 = 0;
5194 } else {
5195 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
Daniel Vetter67a54562012-10-20 20:57:45 +02005196 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305197 }
Daniel Vetter67a54562012-10-20 20:57:45 +02005198
5199 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5200 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5201
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005202 vbt = dev_priv->vbt.edp_pps;
Daniel Vetter67a54562012-10-20 20:57:45 +02005203
5204 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5205 * our hw here, which are all in 100usec. */
5206 spec.t1_t3 = 210 * 10;
5207 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5208 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5209 spec.t10 = 500 * 10;
5210 /* This one is special and actually in units of 100ms, but zero
5211 * based in the hw (so we need to add 100 ms). But the sw vbt
5212 * table multiplies it with 1000 to make it in units of 100usec,
5213 * too. */
5214 spec.t11_t12 = (510 + 100) * 10;
5215
5216 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5217 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5218
5219 /* Use the max of the register settings and vbt. If both are
5220 * unset, fall back to the spec limits. */
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005221#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
Daniel Vetter67a54562012-10-20 20:57:45 +02005222 spec.field : \
5223 max(cur.field, vbt.field))
5224 assign_final(t1_t3);
5225 assign_final(t8);
5226 assign_final(t9);
5227 assign_final(t10);
5228 assign_final(t11_t12);
5229#undef assign_final
5230
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005231#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
Daniel Vetter67a54562012-10-20 20:57:45 +02005232 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5233 intel_dp->backlight_on_delay = get_delay(t8);
5234 intel_dp->backlight_off_delay = get_delay(t9);
5235 intel_dp->panel_power_down_delay = get_delay(t10);
5236 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5237#undef get_delay
5238
Jani Nikulaf30d26e2013-01-16 10:53:40 +02005239 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5240 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5241 intel_dp->panel_power_cycle_delay);
5242
5243 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5244 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
Jani Nikulaf30d26e2013-01-16 10:53:40 +02005245}
5246
5247static void
5248intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005249 struct intel_dp *intel_dp)
Jani Nikulaf30d26e2013-01-16 10:53:40 +02005250{
5251 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07005252 u32 pp_on, pp_off, pp_div, port_sel = 0;
5253 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005254 i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
Ville Syrjäläad933b52014-08-18 22:15:56 +03005255 enum port port = dp_to_dig_port(intel_dp)->port;
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005256 const struct edp_power_seq *seq = &intel_dp->pps_delays;
Jesse Barnes453c5422013-03-28 09:55:41 -07005257
Ville Syrjäläe39b9992014-09-04 14:53:14 +03005258 lockdep_assert_held(&dev_priv->pps_mutex);
Jesse Barnes453c5422013-03-28 09:55:41 -07005259
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305260 if (IS_BROXTON(dev)) {
5261 /*
5262 * TODO: BXT has 2 sets of PPS registers.
5263 * Correct Register for Broxton need to be identified
5264 * using VBT. hardcoding for now
5265 */
5266 pp_ctrl_reg = BXT_PP_CONTROL(0);
5267 pp_on_reg = BXT_PP_ON_DELAYS(0);
5268 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5269
5270 } else if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes453c5422013-03-28 09:55:41 -07005271 pp_on_reg = PCH_PP_ON_DELAYS;
5272 pp_off_reg = PCH_PP_OFF_DELAYS;
5273 pp_div_reg = PCH_PP_DIVISOR;
5274 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03005275 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5276
5277 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5278 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5279 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07005280 }
5281
Paulo Zanonib2f19d12013-12-19 14:29:44 -02005282 /*
5283 * And finally store the new values in the power sequencer. The
5284 * backlight delays are set to 1 because we do manual waits on them. For
5285 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5286 * we'll end up waiting for the backlight off delay twice: once when we
5287 * do the manual sleep, and once when we disable the panel and wait for
5288 * the PP_STATUS bit to become zero.
5289 */
Jani Nikulaf30d26e2013-01-16 10:53:40 +02005290 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
Paulo Zanonib2f19d12013-12-19 14:29:44 -02005291 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5292 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
Jani Nikulaf30d26e2013-01-16 10:53:40 +02005293 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
Daniel Vetter67a54562012-10-20 20:57:45 +02005294 /* Compute the divisor for the pp clock, simply match the Bspec
5295 * formula. */
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305296 if (IS_BROXTON(dev)) {
5297 pp_div = I915_READ(pp_ctrl_reg);
5298 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5299 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5300 << BXT_POWER_CYCLE_DELAY_SHIFT);
5301 } else {
5302 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5303 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5304 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5305 }
Daniel Vetter67a54562012-10-20 20:57:45 +02005306
5307 /* Haswell doesn't have any port selection bits for the panel
5308 * power sequencer any more. */
Wayne Boyer666a4532015-12-09 12:29:35 -08005309 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjäläad933b52014-08-18 22:15:56 +03005310 port_sel = PANEL_PORT_SELECT_VLV(port);
Imre Deakbc7d38a2013-05-16 14:40:36 +03005311 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
Ville Syrjäläad933b52014-08-18 22:15:56 +03005312 if (port == PORT_A)
Jani Nikulaa24c1442013-09-05 16:44:46 +03005313 port_sel = PANEL_PORT_SELECT_DPA;
Daniel Vetter67a54562012-10-20 20:57:45 +02005314 else
Jani Nikulaa24c1442013-09-05 16:44:46 +03005315 port_sel = PANEL_PORT_SELECT_DPD;
Daniel Vetter67a54562012-10-20 20:57:45 +02005316 }
5317
Jesse Barnes453c5422013-03-28 09:55:41 -07005318 pp_on |= port_sel;
5319
5320 I915_WRITE(pp_on_reg, pp_on);
5321 I915_WRITE(pp_off_reg, pp_off);
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305322 if (IS_BROXTON(dev))
5323 I915_WRITE(pp_ctrl_reg, pp_div);
5324 else
5325 I915_WRITE(pp_div_reg, pp_div);
Daniel Vetter67a54562012-10-20 20:57:45 +02005326
Daniel Vetter67a54562012-10-20 20:57:45 +02005327 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07005328 I915_READ(pp_on_reg),
5329 I915_READ(pp_off_reg),
Vandana Kannanb0a08be2015-06-18 11:00:55 +05305330 IS_BROXTON(dev) ?
5331 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
Jesse Barnes453c5422013-03-28 09:55:41 -07005332 I915_READ(pp_div_reg));
Zhenyu Wange3421a12010-04-08 09:43:27 +08005333}
5334
Vandana Kannanb33a2812015-02-13 15:33:03 +05305335/**
5336 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5337 * @dev: DRM device
5338 * @refresh_rate: RR to be programmed
5339 *
5340 * This function gets called when refresh rate (RR) has to be changed from
5341 * one frequency to another. Switches can be between high and low RR
5342 * supported by the panel or to any other RR based on media playback (in
5343 * this case, RR value needs to be passed from user space).
5344 *
5345 * The caller of this function needs to take a lock on dev_priv->drrs.
5346 */
Vandana Kannan96178ee2015-01-10 02:25:56 +05305347static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305348{
5349 struct drm_i915_private *dev_priv = dev->dev_private;
5350 struct intel_encoder *encoder;
Vandana Kannan96178ee2015-01-10 02:25:56 +05305351 struct intel_digital_port *dig_port = NULL;
5352 struct intel_dp *intel_dp = dev_priv->drrs.dp;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02005353 struct intel_crtc_state *config = NULL;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305354 struct intel_crtc *intel_crtc = NULL;
Vandana Kannan96178ee2015-01-10 02:25:56 +05305355 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305356
5357 if (refresh_rate <= 0) {
5358 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5359 return;
5360 }
5361
Vandana Kannan96178ee2015-01-10 02:25:56 +05305362 if (intel_dp == NULL) {
5363 DRM_DEBUG_KMS("DRRS not supported.\n");
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305364 return;
5365 }
5366
Daniel Vetter1fcc9d12014-07-11 10:30:10 -07005367 /*
Rodrigo Vivie4d59f62014-11-20 02:22:08 -08005368 * FIXME: This needs proper synchronization with psr state for some
5369 * platforms that cannot have PSR and DRRS enabled at the same time.
Daniel Vetter1fcc9d12014-07-11 10:30:10 -07005370 */
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305371
Vandana Kannan96178ee2015-01-10 02:25:56 +05305372 dig_port = dp_to_dig_port(intel_dp);
5373 encoder = &dig_port->base;
Ander Conselvan de Oliveira723f9aa2015-03-20 16:18:18 +02005374 intel_crtc = to_intel_crtc(encoder->base.crtc);
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305375
5376 if (!intel_crtc) {
5377 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5378 return;
5379 }
5380
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005381 config = intel_crtc->config;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305382
Vandana Kannan96178ee2015-01-10 02:25:56 +05305383 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305384 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5385 return;
5386 }
5387
Vandana Kannan96178ee2015-01-10 02:25:56 +05305388 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5389 refresh_rate)
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305390 index = DRRS_LOW_RR;
5391
Vandana Kannan96178ee2015-01-10 02:25:56 +05305392 if (index == dev_priv->drrs.refresh_rate_type) {
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305393 DRM_DEBUG_KMS(
5394 "DRRS requested for previously set RR...ignoring\n");
5395 return;
5396 }
5397
5398 if (!intel_crtc->active) {
5399 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5400 return;
5401 }
5402
Durgadoss R44395bf2015-02-13 15:33:02 +05305403 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
Vandana Kannana4c30b12015-02-13 15:33:00 +05305404 switch (index) {
5405 case DRRS_HIGH_RR:
5406 intel_dp_set_m_n(intel_crtc, M1_N1);
5407 break;
5408 case DRRS_LOW_RR:
5409 intel_dp_set_m_n(intel_crtc, M2_N2);
5410 break;
5411 case DRRS_MAX_RR:
5412 default:
5413 DRM_ERROR("Unsupported refreshrate type\n");
5414 }
5415 } else if (INTEL_INFO(dev)->gen > 6) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005416 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
Ville Syrjälä649636e2015-09-22 19:50:01 +03005417 u32 val;
Vandana Kannana4c30b12015-02-13 15:33:00 +05305418
Ville Syrjälä649636e2015-09-22 19:50:01 +03005419 val = I915_READ(reg);
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305420 if (index > DRRS_HIGH_RR) {
Wayne Boyer666a4532015-12-09 12:29:35 -08005421 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05305422 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5423 else
5424 val |= PIPECONF_EDP_RR_MODE_SWITCH;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305425 } else {
Wayne Boyer666a4532015-12-09 12:29:35 -08005426 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Vandana Kannan6fa7aec2015-02-13 15:33:01 +05305427 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5428 else
5429 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305430 }
5431 I915_WRITE(reg, val);
5432 }
5433
Vandana Kannan4e9ac942015-01-22 15:14:45 +05305434 dev_priv->drrs.refresh_rate_type = index;
5435
5436 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5437}
5438
Vandana Kannanb33a2812015-02-13 15:33:03 +05305439/**
5440 * intel_edp_drrs_enable - init drrs struct if supported
5441 * @intel_dp: DP struct
5442 *
5443 * Initializes frontbuffer_bits and drrs.dp
5444 */
Vandana Kannanc3955782015-01-22 15:17:40 +05305445void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5446{
5447 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5450 struct drm_crtc *crtc = dig_port->base.base.crtc;
5451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5452
5453 if (!intel_crtc->config->has_drrs) {
5454 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5455 return;
5456 }
5457
5458 mutex_lock(&dev_priv->drrs.mutex);
5459 if (WARN_ON(dev_priv->drrs.dp)) {
5460 DRM_ERROR("DRRS already enabled\n");
5461 goto unlock;
5462 }
5463
5464 dev_priv->drrs.busy_frontbuffer_bits = 0;
5465
5466 dev_priv->drrs.dp = intel_dp;
5467
5468unlock:
5469 mutex_unlock(&dev_priv->drrs.mutex);
5470}
5471
Vandana Kannanb33a2812015-02-13 15:33:03 +05305472/**
5473 * intel_edp_drrs_disable - Disable DRRS
5474 * @intel_dp: DP struct
5475 *
5476 */
Vandana Kannanc3955782015-01-22 15:17:40 +05305477void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5478{
5479 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5480 struct drm_i915_private *dev_priv = dev->dev_private;
5481 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5482 struct drm_crtc *crtc = dig_port->base.base.crtc;
5483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5484
5485 if (!intel_crtc->config->has_drrs)
5486 return;
5487
5488 mutex_lock(&dev_priv->drrs.mutex);
5489 if (!dev_priv->drrs.dp) {
5490 mutex_unlock(&dev_priv->drrs.mutex);
5491 return;
5492 }
5493
5494 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5495 intel_dp_set_drrs_state(dev_priv->dev,
5496 intel_dp->attached_connector->panel.
5497 fixed_mode->vrefresh);
5498
5499 dev_priv->drrs.dp = NULL;
5500 mutex_unlock(&dev_priv->drrs.mutex);
5501
5502 cancel_delayed_work_sync(&dev_priv->drrs.work);
5503}
5504
Vandana Kannan4e9ac942015-01-22 15:14:45 +05305505static void intel_edp_drrs_downclock_work(struct work_struct *work)
5506{
5507 struct drm_i915_private *dev_priv =
5508 container_of(work, typeof(*dev_priv), drrs.work.work);
5509 struct intel_dp *intel_dp;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305510
Vandana Kannan96178ee2015-01-10 02:25:56 +05305511 mutex_lock(&dev_priv->drrs.mutex);
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305512
Vandana Kannan4e9ac942015-01-22 15:14:45 +05305513 intel_dp = dev_priv->drrs.dp;
5514
5515 if (!intel_dp)
5516 goto unlock;
5517
5518 /*
5519 * The delayed work can race with an invalidate hence we need to
5520 * recheck.
5521 */
5522
5523 if (dev_priv->drrs.busy_frontbuffer_bits)
5524 goto unlock;
5525
5526 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5527 intel_dp_set_drrs_state(dev_priv->dev,
5528 intel_dp->attached_connector->panel.
5529 downclock_mode->vrefresh);
5530
5531unlock:
Vandana Kannan96178ee2015-01-10 02:25:56 +05305532 mutex_unlock(&dev_priv->drrs.mutex);
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305533}
5534
Vandana Kannanb33a2812015-02-13 15:33:03 +05305535/**
Ramalingam C0ddfd202015-06-15 20:50:05 +05305536 * intel_edp_drrs_invalidate - Disable Idleness DRRS
Vandana Kannanb33a2812015-02-13 15:33:03 +05305537 * @dev: DRM device
5538 * @frontbuffer_bits: frontbuffer plane tracking bits
5539 *
Ramalingam C0ddfd202015-06-15 20:50:05 +05305540 * This function gets called everytime rendering on the given planes start.
5541 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
Vandana Kannanb33a2812015-02-13 15:33:03 +05305542 *
5543 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5544 */
Vandana Kannana93fad02015-01-10 02:25:59 +05305545void intel_edp_drrs_invalidate(struct drm_device *dev,
5546 unsigned frontbuffer_bits)
5547{
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 struct drm_crtc *crtc;
5550 enum pipe pipe;
5551
Daniel Vetter9da7d692015-04-09 16:44:15 +02005552 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
Vandana Kannana93fad02015-01-10 02:25:59 +05305553 return;
5554
Daniel Vetter88f933a2015-04-09 16:44:16 +02005555 cancel_delayed_work(&dev_priv->drrs.work);
Ramalingam C3954e732015-03-03 12:11:46 +05305556
Vandana Kannana93fad02015-01-10 02:25:59 +05305557 mutex_lock(&dev_priv->drrs.mutex);
Daniel Vetter9da7d692015-04-09 16:44:15 +02005558 if (!dev_priv->drrs.dp) {
5559 mutex_unlock(&dev_priv->drrs.mutex);
5560 return;
5561 }
5562
Vandana Kannana93fad02015-01-10 02:25:59 +05305563 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5564 pipe = to_intel_crtc(crtc)->pipe;
5565
Daniel Vetterc1d038c2015-06-18 10:30:25 +02005566 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5567 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5568
Ramalingam C0ddfd202015-06-15 20:50:05 +05305569 /* invalidate means busy screen hence upclock */
Daniel Vetterc1d038c2015-06-18 10:30:25 +02005570 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
Vandana Kannana93fad02015-01-10 02:25:59 +05305571 intel_dp_set_drrs_state(dev_priv->dev,
5572 dev_priv->drrs.dp->attached_connector->panel.
5573 fixed_mode->vrefresh);
Vandana Kannana93fad02015-01-10 02:25:59 +05305574
Vandana Kannana93fad02015-01-10 02:25:59 +05305575 mutex_unlock(&dev_priv->drrs.mutex);
5576}
5577
Vandana Kannanb33a2812015-02-13 15:33:03 +05305578/**
Ramalingam C0ddfd202015-06-15 20:50:05 +05305579 * intel_edp_drrs_flush - Restart Idleness DRRS
Vandana Kannanb33a2812015-02-13 15:33:03 +05305580 * @dev: DRM device
5581 * @frontbuffer_bits: frontbuffer plane tracking bits
5582 *
Ramalingam C0ddfd202015-06-15 20:50:05 +05305583 * This function gets called every time rendering on the given planes has
5584 * completed or flip on a crtc is completed. So DRRS should be upclocked
5585 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5586 * if no other planes are dirty.
Vandana Kannanb33a2812015-02-13 15:33:03 +05305587 *
5588 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5589 */
Vandana Kannana93fad02015-01-10 02:25:59 +05305590void intel_edp_drrs_flush(struct drm_device *dev,
5591 unsigned frontbuffer_bits)
5592{
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 struct drm_crtc *crtc;
5595 enum pipe pipe;
5596
Daniel Vetter9da7d692015-04-09 16:44:15 +02005597 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
Vandana Kannana93fad02015-01-10 02:25:59 +05305598 return;
5599
Daniel Vetter88f933a2015-04-09 16:44:16 +02005600 cancel_delayed_work(&dev_priv->drrs.work);
Ramalingam C3954e732015-03-03 12:11:46 +05305601
Vandana Kannana93fad02015-01-10 02:25:59 +05305602 mutex_lock(&dev_priv->drrs.mutex);
Daniel Vetter9da7d692015-04-09 16:44:15 +02005603 if (!dev_priv->drrs.dp) {
5604 mutex_unlock(&dev_priv->drrs.mutex);
5605 return;
5606 }
5607
Vandana Kannana93fad02015-01-10 02:25:59 +05305608 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5609 pipe = to_intel_crtc(crtc)->pipe;
Daniel Vetterc1d038c2015-06-18 10:30:25 +02005610
5611 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
Vandana Kannana93fad02015-01-10 02:25:59 +05305612 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5613
Ramalingam C0ddfd202015-06-15 20:50:05 +05305614 /* flush means busy screen hence upclock */
Daniel Vetterc1d038c2015-06-18 10:30:25 +02005615 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
Ramalingam C0ddfd202015-06-15 20:50:05 +05305616 intel_dp_set_drrs_state(dev_priv->dev,
5617 dev_priv->drrs.dp->attached_connector->panel.
5618 fixed_mode->vrefresh);
5619
5620 /*
5621 * flush also means no more activity hence schedule downclock, if all
5622 * other fbs are quiescent too
5623 */
5624 if (!dev_priv->drrs.busy_frontbuffer_bits)
Vandana Kannana93fad02015-01-10 02:25:59 +05305625 schedule_delayed_work(&dev_priv->drrs.work,
5626 msecs_to_jiffies(1000));
5627 mutex_unlock(&dev_priv->drrs.mutex);
5628}
5629
Vandana Kannanb33a2812015-02-13 15:33:03 +05305630/**
5631 * DOC: Display Refresh Rate Switching (DRRS)
5632 *
5633 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5634 * which enables swtching between low and high refresh rates,
5635 * dynamically, based on the usage scenario. This feature is applicable
5636 * for internal panels.
5637 *
5638 * Indication that the panel supports DRRS is given by the panel EDID, which
5639 * would list multiple refresh rates for one resolution.
5640 *
5641 * DRRS is of 2 types - static and seamless.
5642 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5643 * (may appear as a blink on screen) and is used in dock-undock scenario.
5644 * Seamless DRRS involves changing RR without any visual effect to the user
5645 * and can be used during normal system usage. This is done by programming
5646 * certain registers.
5647 *
5648 * Support for static/seamless DRRS may be indicated in the VBT based on
5649 * inputs from the panel spec.
5650 *
5651 * DRRS saves power by switching to low RR based on usage scenarios.
5652 *
5653 * eDP DRRS:-
5654 * The implementation is based on frontbuffer tracking implementation.
5655 * When there is a disturbance on the screen triggered by user activity or a
5656 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5657 * When there is no movement on screen, after a timeout of 1 second, a switch
5658 * to low RR is made.
5659 * For integration with frontbuffer tracking code,
5660 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5661 *
5662 * DRRS can be further extended to support other internal panels and also
5663 * the scenario of video playback wherein RR is set based on the rate
5664 * requested by userspace.
5665 */
5666
5667/**
5668 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5669 * @intel_connector: eDP connector
5670 * @fixed_mode: preferred mode of panel
5671 *
5672 * This function is called only once at driver load to initialize basic
5673 * DRRS stuff.
5674 *
5675 * Returns:
5676 * Downclock mode if panel supports it, else return NULL.
5677 * DRRS support is determined by the presence of downclock mode (apart
5678 * from VBT setting).
5679 */
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305680static struct drm_display_mode *
Vandana Kannan96178ee2015-01-10 02:25:56 +05305681intel_dp_drrs_init(struct intel_connector *intel_connector,
5682 struct drm_display_mode *fixed_mode)
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305683{
5684 struct drm_connector *connector = &intel_connector->base;
Vandana Kannan96178ee2015-01-10 02:25:56 +05305685 struct drm_device *dev = connector->dev;
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 struct drm_display_mode *downclock_mode = NULL;
5688
Daniel Vetter9da7d692015-04-09 16:44:15 +02005689 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5690 mutex_init(&dev_priv->drrs.mutex);
5691
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305692 if (INTEL_INFO(dev)->gen <= 6) {
5693 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5694 return NULL;
5695 }
5696
5697 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
Damien Lespiau4079b8d2014-08-05 10:39:42 +01005698 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305699 return NULL;
5700 }
5701
5702 downclock_mode = intel_find_panel_downclock
5703 (dev, fixed_mode, connector);
5704
5705 if (!downclock_mode) {
Ramalingam Ca1d26342015-02-23 17:38:33 +05305706 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305707 return NULL;
5708 }
5709
Vandana Kannan96178ee2015-01-10 02:25:56 +05305710 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05305711
Vandana Kannan96178ee2015-01-10 02:25:56 +05305712 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
Damien Lespiau4079b8d2014-08-05 10:39:42 +01005713 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305714 return downclock_mode;
5715}
5716
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005717static bool intel_edp_init_connector(struct intel_dp *intel_dp,
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005718 struct intel_connector *intel_connector)
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005719{
5720 struct drm_connector *connector = &intel_connector->base;
5721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Paulo Zanoni63635212014-04-22 19:55:42 -03005722 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5723 struct drm_device *dev = intel_encoder->base.dev;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005724 struct drm_i915_private *dev_priv = dev->dev_private;
5725 struct drm_display_mode *fixed_mode = NULL;
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305726 struct drm_display_mode *downclock_mode = NULL;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005727 bool has_dpcd;
5728 struct drm_display_mode *scan;
5729 struct edid *edid;
Ville Syrjälä6517d272014-11-07 11:16:02 +02005730 enum pipe pipe = INVALID_PIPE;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005731
5732 if (!is_edp(intel_dp))
5733 return true;
5734
Ville Syrjälä49e6bc52014-10-28 16:15:52 +02005735 pps_lock(intel_dp);
5736 intel_edp_panel_vdd_sanitize(intel_dp);
5737 pps_unlock(intel_dp);
Paulo Zanoni63635212014-04-22 19:55:42 -03005738
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005739 /* Cache DPCD and EDID for edp. */
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005740 has_dpcd = intel_dp_get_dpcd(intel_dp);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005741
5742 if (has_dpcd) {
5743 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5744 dev_priv->no_aux_handshake =
5745 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5746 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5747 } else {
5748 /* if this fails, presume the device is a ghost */
5749 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005750 return false;
5751 }
5752
5753 /* We now know it's not a ghost, init power sequence regs. */
Ville Syrjälä773538e82014-09-04 14:54:56 +03005754 pps_lock(intel_dp);
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005755 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03005756 pps_unlock(intel_dp);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005757
Daniel Vetter060c8772014-03-21 23:22:35 +01005758 mutex_lock(&dev->mode_config.mutex);
Jani Nikula0b998362014-03-14 16:51:17 +02005759 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005760 if (edid) {
5761 if (drm_add_edid_modes(connector, edid)) {
5762 drm_mode_connector_update_edid_property(connector,
5763 edid);
5764 drm_edid_to_eld(connector, edid);
5765 } else {
5766 kfree(edid);
5767 edid = ERR_PTR(-EINVAL);
5768 }
5769 } else {
5770 edid = ERR_PTR(-ENOENT);
5771 }
5772 intel_connector->edid = edid;
5773
5774 /* prefer fixed mode from EDID if available */
5775 list_for_each_entry(scan, &connector->probed_modes, head) {
5776 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5777 fixed_mode = drm_mode_duplicate(dev, scan);
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305778 downclock_mode = intel_dp_drrs_init(
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305779 intel_connector, fixed_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005780 break;
5781 }
5782 }
5783
5784 /* fallback to VBT if available for eDP */
5785 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5786 fixed_mode = drm_mode_duplicate(dev,
5787 dev_priv->vbt.lfp_lvds_vbt_mode);
5788 if (fixed_mode)
5789 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5790 }
Daniel Vetter060c8772014-03-21 23:22:35 +01005791 mutex_unlock(&dev->mode_config.mutex);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005792
Wayne Boyer666a4532015-12-09 12:29:35 -08005793 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Clint Taylor01527b32014-07-07 13:01:46 -07005794 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5795 register_reboot_notifier(&intel_dp->edp_notifier);
Ville Syrjälä6517d272014-11-07 11:16:02 +02005796
5797 /*
5798 * Figure out the current pipe for the initial backlight setup.
5799 * If the current pipe isn't valid, try the PPS pipe, and if that
5800 * fails just assume pipe A.
5801 */
5802 if (IS_CHERRYVIEW(dev))
5803 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5804 else
5805 pipe = PORT_TO_PIPE(intel_dp->DP);
5806
5807 if (pipe != PIPE_A && pipe != PIPE_B)
5808 pipe = intel_dp->pps_pipe;
5809
5810 if (pipe != PIPE_A && pipe != PIPE_B)
5811 pipe = PIPE_A;
5812
5813 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5814 pipe_name(pipe));
Clint Taylor01527b32014-07-07 13:01:46 -07005815 }
5816
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05305817 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
Jani Nikula5507fae2015-09-14 14:03:48 +03005818 intel_connector->panel.backlight.power = intel_edp_backlight_power;
Ville Syrjälä6517d272014-11-07 11:16:02 +02005819 intel_panel_setup_backlight(connector, pipe);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03005820
5821 return true;
5822}
5823
Paulo Zanoni16c25532013-06-12 17:27:25 -03005824bool
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005825intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5826 struct intel_connector *intel_connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005827{
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005828 struct drm_connector *connector = &intel_connector->base;
5829 struct intel_dp *intel_dp = &intel_dig_port->dp;
5830 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5831 struct drm_device *dev = intel_encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005832 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02005833 enum port port = intel_dig_port->port;
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02005834 int type, ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005835
Ville Syrjäläccb1a832015-12-08 19:59:38 +02005836 if (WARN(intel_dig_port->max_lanes < 1,
5837 "Not enough lanes (%d) for DP on port %c\n",
5838 intel_dig_port->max_lanes, port_name(port)))
5839 return false;
5840
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03005841 intel_dp->pps_pipe = INVALID_PIPE;
5842
Damien Lespiauec5b01d2014-01-21 13:35:39 +00005843 /* intel_dp vfuncs */
Damien Lespiaub6b5e382014-01-20 16:00:59 +00005844 if (INTEL_INFO(dev)->gen >= 9)
5845 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
Wayne Boyer666a4532015-12-09 12:29:35 -08005846 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Damien Lespiauec5b01d2014-01-21 13:35:39 +00005847 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5848 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5849 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5850 else if (HAS_PCH_SPLIT(dev))
5851 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5852 else
5853 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5854
Damien Lespiaub9ca5fa2014-01-20 16:01:00 +00005855 if (INTEL_INFO(dev)->gen >= 9)
5856 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5857 else
5858 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
Damien Lespiau153b1102014-01-21 13:37:15 +00005859
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03005860 if (HAS_DDI(dev))
5861 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5862
Daniel Vetter07679352012-09-06 22:15:42 +02005863 /* Preserve the current hw state. */
5864 intel_dp->DP = I915_READ(intel_dp->output_reg);
Jani Nikuladd06f902012-10-19 14:51:50 +03005865 intel_dp->attached_connector = intel_connector;
Chris Wilson3d3dc142011-02-12 10:33:12 +00005866
Ville Syrjälä3b32a352013-11-01 18:22:41 +02005867 if (intel_dp_is_edp(dev, port))
Gajanan Bhat19c03922012-09-27 19:13:07 +05305868 type = DRM_MODE_CONNECTOR_eDP;
Ville Syrjälä3b32a352013-11-01 18:22:41 +02005869 else
5870 type = DRM_MODE_CONNECTOR_DisplayPort;
Adam Jacksonb3295302010-07-16 14:46:28 -04005871
Imre Deakf7d24902013-05-08 13:14:05 +03005872 /*
5873 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5874 * for DP the encoder type can be set by the caller to
5875 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5876 */
5877 if (type == DRM_MODE_CONNECTOR_eDP)
5878 intel_encoder->type = INTEL_OUTPUT_EDP;
5879
Ville Syrjäläc17ed5b2014-10-16 21:27:27 +03005880 /* eDP only on port B and/or C on vlv/chv */
Wayne Boyer666a4532015-12-09 12:29:35 -08005881 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5882 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
Ville Syrjäläc17ed5b2014-10-16 21:27:27 +03005883 return false;
5884
Imre Deake7281ea2013-05-08 13:14:08 +03005885 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5886 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5887 port_name(port));
5888
Adam Jacksonb3295302010-07-16 14:46:28 -04005889 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005890 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5891
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005892 connector->interlace_allowed = true;
5893 connector->doublescan_allowed = 0;
Ma Lingf8aed702009-08-24 13:50:24 +08005894
Daniel Vetter66a92782012-07-12 20:08:18 +02005895 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
Daniel Vetter4be73782014-01-17 14:39:48 +01005896 edp_panel_vdd_work);
Zhenyu Wang6251ec02010-01-12 05:38:32 +08005897
Chris Wilsondf0e9242010-09-09 16:20:55 +01005898 intel_connector_attach_encoder(intel_connector, intel_encoder);
Thomas Wood34ea3d32014-05-29 16:57:41 +01005899 drm_connector_register(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005900
Paulo Zanoniaffa9352012-11-23 15:30:39 -02005901 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02005902 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5903 else
5904 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak80f65de2014-02-11 17:12:49 +02005905 intel_connector->unregister = intel_dp_connector_unregister;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02005906
Jani Nikula0b998362014-03-14 16:51:17 +02005907 /* Set up the hotplug pin. */
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005908 switch (port) {
5909 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05005910 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005911 break;
5912 case PORT_B:
Egbert Eich1d843f92013-02-25 12:06:49 -05005913 intel_encoder->hpd_pin = HPD_PORT_B;
Jani Nikulae87a0052015-10-20 15:22:02 +03005914 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
Sonika Jindalcf1d5882015-08-10 10:35:36 +05305915 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005916 break;
5917 case PORT_C:
Egbert Eich1d843f92013-02-25 12:06:49 -05005918 intel_encoder->hpd_pin = HPD_PORT_C;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005919 break;
5920 case PORT_D:
Egbert Eich1d843f92013-02-25 12:06:49 -05005921 intel_encoder->hpd_pin = HPD_PORT_D;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005922 break;
Xiong Zhang26951ca2015-08-17 15:55:50 +08005923 case PORT_E:
5924 intel_encoder->hpd_pin = HPD_PORT_E;
5925 break;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03005926 default:
Damien Lespiauad1c0b12013-03-07 15:30:28 +00005927 BUG();
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005928 }
5929
Imre Deakdada1a92014-01-29 13:25:41 +02005930 if (is_edp(intel_dp)) {
Ville Syrjälä773538e82014-09-04 14:54:56 +03005931 pps_lock(intel_dp);
Ville Syrjälä1e74a322014-10-28 16:15:51 +02005932 intel_dp_init_panel_power_timestamps(intel_dp);
Wayne Boyer666a4532015-12-09 12:29:35 -08005933 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +03005934 vlv_initial_power_sequencer_setup(intel_dp);
Ville Syrjälä1e74a322014-10-28 16:15:51 +02005935 else
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005936 intel_dp_init_panel_power_sequencer(dev, intel_dp);
Ville Syrjälä773538e82014-09-04 14:54:56 +03005937 pps_unlock(intel_dp);
Imre Deakdada1a92014-01-29 13:25:41 +02005938 }
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02005939
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02005940 ret = intel_dp_aux_init(intel_dp, intel_connector);
5941 if (ret)
5942 goto fail;
Dave Airliec1f05262012-08-30 11:06:18 +10005943
Dave Airlie0e32b392014-05-02 14:02:48 +10005944 /* init MST on ports that can support it */
Jani Nikula0c9b3712015-05-18 17:10:01 +03005945 if (HAS_DP_MST(dev) &&
5946 (port == PORT_B || port == PORT_C || port == PORT_D))
5947 intel_dp_mst_encoder_init(intel_dig_port,
5948 intel_connector->base.base.id);
Dave Airlie0e32b392014-05-02 14:02:48 +10005949
Ville Syrjälä36b5f422014-10-16 21:27:30 +03005950 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02005951 intel_dp_aux_fini(intel_dp);
5952 intel_dp_mst_encoder_cleanup(intel_dig_port);
5953 goto fail;
Paulo Zanonib2f246a2013-06-12 17:27:26 -03005954 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005955
Chris Wilsonf6849602010-09-19 09:29:33 +01005956 intel_dp_add_properties(intel_dp, connector);
5957
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005958 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5959 * 0xd. Failure to do so will result in spurious interrupts being
5960 * generated on the port when a cable is not attached.
5961 */
5962 if (IS_G4X(dev) && !IS_GM45(dev)) {
5963 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5964 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5965 }
Paulo Zanoni16c25532013-06-12 17:27:25 -03005966
Jani Nikulaaa7471d2015-04-01 11:15:21 +03005967 i915_debugfs_connector_add(connector);
5968
Paulo Zanoni16c25532013-06-12 17:27:25 -03005969 return true;
Ville Syrjäläa121f4e2015-11-11 20:34:11 +02005970
5971fail:
5972 if (is_edp(intel_dp)) {
5973 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5974 /*
5975 * vdd might still be enabled do to the delayed vdd off.
5976 * Make sure vdd is actually turned off here.
5977 */
5978 pps_lock(intel_dp);
5979 edp_panel_vdd_off_sync(intel_dp);
5980 pps_unlock(intel_dp);
5981 }
5982 drm_connector_unregister(connector);
5983 drm_connector_cleanup(connector);
5984
5985 return false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005986}
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005987
5988void
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005989intel_dp_init(struct drm_device *dev,
5990 i915_reg_t output_reg, enum port port)
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005991{
Dave Airlie13cf5502014-06-18 11:29:35 +10005992 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005993 struct intel_digital_port *intel_dig_port;
5994 struct intel_encoder *intel_encoder;
5995 struct drm_encoder *encoder;
5996 struct intel_connector *intel_connector;
5997
Daniel Vetterb14c5672013-09-19 12:18:32 +02005998 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02005999 if (!intel_dig_port)
6000 return;
6001
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006002 intel_connector = intel_connector_alloc();
Sudip Mukherjee11aee0f2015-10-08 19:27:59 +05306003 if (!intel_connector)
6004 goto err_connector_alloc;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006005
6006 intel_encoder = &intel_dig_port->base;
6007 encoder = &intel_encoder->base;
6008
Sudip Mukherjee893da0c2015-10-08 19:28:00 +05306009 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
Dave Airlieade1ba72015-12-23 14:22:09 +10006010 DRM_MODE_ENCODER_TMDS, NULL))
Sudip Mukherjee893da0c2015-10-08 19:28:00 +05306011 goto err_encoder_init;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006012
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01006013 intel_encoder->compute_config = intel_dp_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02006014 intel_encoder->disable = intel_disable_dp;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02006015 intel_encoder->get_hw_state = intel_dp_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07006016 intel_encoder->get_config = intel_dp_get_config;
Imre Deak07f9cd02014-08-18 14:42:45 +03006017 intel_encoder->suspend = intel_dp_encoder_suspend;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03006018 if (IS_CHERRYVIEW(dev)) {
Ville Syrjälä9197c882014-04-09 13:29:05 +03006019 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03006020 intel_encoder->pre_enable = chv_pre_enable_dp;
6021 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä580d3812014-04-09 13:29:00 +03006022 intel_encoder->post_disable = chv_post_disable_dp;
Ville Syrjäläd6db9952015-07-08 23:45:49 +03006023 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03006024 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaecff4f32013-09-06 07:38:29 +03006025 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03006026 intel_encoder->pre_enable = vlv_pre_enable_dp;
6027 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03006028 intel_encoder->post_disable = vlv_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03006029 } else {
Jani Nikulaecff4f32013-09-06 07:38:29 +03006030 intel_encoder->pre_enable = g4x_pre_enable_dp;
6031 intel_encoder->enable = g4x_enable_dp;
Ville Syrjälä08aff3f2014-08-18 22:16:09 +03006032 if (INTEL_INFO(dev)->gen >= 5)
6033 intel_encoder->post_disable = ilk_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03006034 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006035
Paulo Zanoni174edf12012-10-26 19:05:50 -02006036 intel_dig_port->port = port;
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01006037 dev_priv->dig_port_map[port] = intel_encoder;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006038 intel_dig_port->dp.output_reg = output_reg;
Ville Syrjäläccb1a832015-12-08 19:59:38 +02006039 intel_dig_port->max_lanes = 4;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006040
Paulo Zanoni00c09d72012-10-26 19:05:52 -02006041 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Ville Syrjälä882ec382014-04-28 14:07:43 +03006042 if (IS_CHERRYVIEW(dev)) {
6043 if (port == PORT_D)
6044 intel_encoder->crtc_mask = 1 << 2;
6045 else
6046 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6047 } else {
6048 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6049 }
Ville Syrjäläbc079e82014-03-03 16:15:28 +02006050 intel_encoder->cloneable = 0;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006051
Dave Airlie13cf5502014-06-18 11:29:35 +10006052 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
Jani Nikula5fcece82015-05-27 15:03:42 +03006053 dev_priv->hotplug.irq_port[port] = intel_dig_port;
Dave Airlie13cf5502014-06-18 11:29:35 +10006054
Sudip Mukherjee11aee0f2015-10-08 19:27:59 +05306055 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6056 goto err_init_connector;
6057
6058 return;
6059
6060err_init_connector:
6061 drm_encoder_cleanup(encoder);
Sudip Mukherjee893da0c2015-10-08 19:28:00 +05306062err_encoder_init:
Sudip Mukherjee11aee0f2015-10-08 19:27:59 +05306063 kfree(intel_connector);
6064err_connector_alloc:
6065 kfree(intel_dig_port);
6066
6067 return;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02006068}
Dave Airlie0e32b392014-05-02 14:02:48 +10006069
6070void intel_dp_mst_suspend(struct drm_device *dev)
6071{
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6073 int i;
6074
6075 /* disable MST */
6076 for (i = 0; i < I915_MAX_PORTS; i++) {
Jani Nikula5fcece82015-05-27 15:03:42 +03006077 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
Dave Airlie0e32b392014-05-02 14:02:48 +10006078 if (!intel_dig_port)
6079 continue;
6080
6081 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6082 if (!intel_dig_port->dp.can_mst)
6083 continue;
6084 if (intel_dig_port->dp.is_mst)
6085 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6086 }
6087 }
6088}
6089
6090void intel_dp_mst_resume(struct drm_device *dev)
6091{
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 int i;
6094
6095 for (i = 0; i < I915_MAX_PORTS; i++) {
Jani Nikula5fcece82015-05-27 15:03:42 +03006096 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
Dave Airlie0e32b392014-05-02 14:02:48 +10006097 if (!intel_dig_port)
6098 continue;
6099 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6100 int ret;
6101
6102 if (!intel_dig_port->dp.can_mst)
6103 continue;
6104
6105 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6106 if (ret != 0) {
6107 intel_dp_check_mst_status(&intel_dig_port->dp);
6108 }
6109 }
6110 }
6111}