blob: 6b0013cc962f3157bef4a4f8fd470bfaea156b69 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Akshay Joshi0206e352011-08-16 15:34:10 -040044bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020045static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010046static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080047
Jesse Barnesf1f644d2013-06-27 00:39:25 +030048static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
Jesse Barnes79e53942008-11-07 14:24:08 -080053typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040054 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080055} intel_range_t;
56
57typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040058 int dot_limit;
59 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080060} intel_p2_t;
61
62#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080063typedef struct intel_limit intel_limit_t;
64struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040065 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080067};
Jesse Barnes79e53942008-11-07 14:24:08 -080068
Jesse Barnes2377b742010-07-07 14:06:43 -070069/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
Daniel Vetterd2acd212012-10-20 20:57:43 +020072int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
Chris Wilson021357a2010-09-07 20:54:59 +010082static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
Chris Wilson8b99e682010-10-13 09:59:17 +010085 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +010090}
91
Keith Packarde4b36692009-06-05 19:22:17 -070092static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -040093 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700103};
104
105static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700116};
Eric Anholt273e27c2011-03-30 13:01:10 -0700117
Keith Packarde4b36692009-06-05 19:22:17 -0700118static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700129};
130
131static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700142};
143
Eric Anholt273e27c2011-03-30 13:01:10 -0700144
Keith Packarde4b36692009-06-05 19:22:17 -0700145static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800157 },
Keith Packarde4b36692009-06-05 19:22:17 -0700158};
159
160static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700171};
172
173static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800184 },
Keith Packarde4b36692009-06-05 19:22:17 -0700185};
186
187static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800198 },
Keith Packarde4b36692009-06-05 19:22:17 -0700199};
200
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500201static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700204 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700207 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700214};
215
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500216static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700227};
228
Eric Anholt273e27c2011-03-30 13:01:10 -0700229/* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800234static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700245};
246
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800247static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800258};
259
260static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800271};
272
Eric Anholt273e27c2011-03-30 13:01:10 -0700273/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800274static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400282 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400295 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800298};
299
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700300static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200308 .p1 = { .min = 1, .max = 3 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700311};
312
313static const intel_limit_t intel_limits_vlv_hdmi = {
Daniel Vetter75e53982013-04-18 21:10:43 +0200314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700324};
325
326static const intel_limit_t intel_limits_vlv_dp = {
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700329 .n = { .min = 1, .max = 7 },
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530330 .m = { .min = 22, .max = 450 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200334 .p1 = { .min = 1, .max = 3 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700337};
338
Chris Wilson1b894b52010-12-14 20:04:54 +0000339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800341{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800342 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800343 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100346 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000347 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000352 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200357 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800358 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800359
360 return limit;
361}
362
Ma Ling044c7c42009-03-18 20:13:23 +0800363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100369 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700370 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800371 else
Keith Packarde4b36692009-06-05 19:22:17 -0700372 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700375 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700377 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800378 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700379 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800380
381 return limit;
382}
383
Chris Wilson1b894b52010-12-14 20:04:54 +0000384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
Eric Anholtbad720f2009-10-22 16:11:14 -0700389 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000390 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800391 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800392 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500393 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500395 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800396 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500397 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700412 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800413 else
Keith Packarde4b36692009-06-05 19:22:17 -0700414 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800415 }
416 return limit;
417}
418
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800421{
Shaohua Li21778322009-02-23 15:19:16 +0800422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200433static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800434{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200435 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
Jesse Barnes79e53942008-11-07 14:24:08 -0800441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800445{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100446 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100447 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800448
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100451 return true;
452
453 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800454}
455
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
Chris Wilson1b894b52010-12-14 20:04:54 +0000462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800465{
Jesse Barnes79e53942008-11-07 14:24:08 -0800466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400467 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800468 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400469 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400471 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400473 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400475 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800476 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400477 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800478 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400479 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400481 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400486 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800487
488 return true;
489}
490
Ma Lingd4906092009-03-18 20:13:27 +0800491static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800495{
496 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800497 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800498 int err = target;
499
Daniel Vettera210b022012-11-26 17:22:08 +0100500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800505 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100506 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
Akshay Joshi0206e352011-08-16 15:34:10 -0400517 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800518
Zhao Yakui42158662009-11-20 11:24:18 +0800519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200523 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800529 int this_err;
530
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200531 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800534 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
Ma Lingd4906092009-03-18 20:13:27 +0800552static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200556{
557 struct drm_device *dev = crtc->dev;
558 intel_clock_t clock;
559 int err = target;
560
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
562 /*
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
566 */
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
578 memset(best_clock, 0, sizeof(*best_clock));
579
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
588 int this_err;
589
590 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
593 continue;
594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
Ma Lingd4906092009-03-18 20:13:27 +0800611static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800615{
616 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800617 intel_clock_t clock;
618 int max_n;
619 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100625 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200638 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200640 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200649 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800652 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000653
654 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800665 return found;
666}
Ma Lingd4906092009-03-18 20:13:27 +0800667
Zhenyu Wang2c072452009-06-05 15:38:42 +0800668static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
Alan Coxaf447bd2012-07-25 13:49:18 +0100679 flag = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700736
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200737enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739{
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
Daniel Vetter3b117c82013-04-17 20:15:07 +0200743 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200744}
745
Paulo Zanonia928d532012-05-04 17:18:15 -0300746static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755}
756
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700757/**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800766{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700767 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800768 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700769
Paulo Zanonia928d532012-05-04 17:18:15 -0300770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
Chris Wilson300387c2010-09-05 20:25:43 +0100775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700791 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
Keith Packardab7ad7f2010-10-03 00:33:06 -0700798/*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100813 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700814 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100815void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700820
Keith Packardab7ad7f2010-10-03 00:33:06 -0700821 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200822 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700823
Keith Packardab7ad7f2010-10-03 00:33:06 -0700824 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200827 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700828 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300829 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100830 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
Paulo Zanoni837ba002012-05-04 17:18:14 -0300833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
Keith Packardab7ad7f2010-10-03 00:33:06 -0700838 /* Wait for the display line to settle */
839 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -0300840 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700841 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -0300842 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
Daniel Vetter284637d2012-07-09 09:51:57 +0200845 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700846 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800847}
848
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000849/*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858{
859 u32 bit;
860
Damien Lespiauc36346e2012-12-13 16:09:03 +0000861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000889 }
890
891 return I915_READ(SDEISR) & bit;
892}
893
Jesse Barnesb24e7172011-01-04 15:09:30 -0800894static const char *state_string(bool enabled)
895{
896 return enabled ? "on" : "off";
897}
898
899/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +0200900void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800902{
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913}
Jesse Barnesb24e7172011-01-04 15:09:30 -0800914
Daniel Vetter55607e82013-06-16 21:42:39 +0200915struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +0200916intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -0800917{
Daniel Vettere2b78262013-06-07 23:10:03 +0200918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
Daniel Vettera43f6e02013-06-07 23:10:32 +0200920 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +0200921 return NULL;
922
Daniel Vettera43f6e02013-06-07 23:10:32 +0200923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +0200924}
925
Jesse Barnesb24e7172011-01-04 15:09:30 -0800926/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +0200927void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -0800930{
Jesse Barnes040484a2011-01-03 12:14:26 -0800931 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +0200932 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -0800933
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -0300934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
Chris Wilson92b27b02012-05-20 18:10:50 +0100939 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +0200940 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100941 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100942
Daniel Vetter53589012013-06-05 13:34:16 +0200943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +0100944 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +0200945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -0800947}
Jesse Barnes040484a2011-01-03 12:14:26 -0800948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -0200955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -0800957
Paulo Zanoniaffa9352012-11-23 15:30:39 -0200958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -0200960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300961 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -0200962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
Jesse Barnes040484a2011-01-03 12:14:26 -0800968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
Paulo Zanonid63fa0d2012-11-20 13:27:35 -0200982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -0800985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001003 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001004 return;
1005
Jesse Barnes040484a2011-01-03 12:14:26 -08001006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
Daniel Vetter55607e82013-06-16 21:42:39 +02001011void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001013{
1014 int reg;
1015 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001016 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001024}
1025
Jesse Barnesea0760c2011-01-04 15:09:32 -08001026static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001032 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001052 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001053}
1054
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001055void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001057{
1058 int reg;
1059 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001060 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001063
Daniel Vetter8e636782012-01-22 01:36:48 +01001064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
Paulo Zanonib97186f2013-05-03 12:15:36 -03001068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001079 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001080}
1081
Chris Wilson931872f2012-01-16 23:01:13 +00001082static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001084{
1085 int reg;
1086 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001087 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001095}
1096
Chris Wilson931872f2012-01-16 23:01:13 +00001097#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
Jesse Barnesb24e7172011-01-04 15:09:30 -08001100static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001103 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
Ville Syrjälä653e1022013-06-04 13:49:05 +03001108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001115 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001116 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001117
Jesse Barnesb24e7172011-01-04 15:09:30 -08001118 /* Need to check both planes against the pipe */
Ville Syrjälä653e1022013-06-04 13:49:05 +03001119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001127 }
1128}
1129
Jesse Barnes19332d72013-03-28 09:55:38 -07001130static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001133 struct drm_device *dev = dev_priv->dev;
Jesse Barnes19332d72013-03-28 09:55:38 -07001134 int reg, i;
1135 u32 val;
1136
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001147 val = I915_READ(reg);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001148 WARN((val & SPRITE_ENABLE),
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
1153 val = I915_READ(reg);
1154 WARN((val & DVS_ENABLE),
1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1156 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001157 }
1158}
1159
Jesse Barnes92f25842011-01-04 15:09:34 -08001160static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161{
1162 u32 val;
1163 bool enabled;
1164
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
Jesse Barnes92f25842011-01-04 15:09:34 -08001170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174}
1175
Daniel Vetterab9412b2013-05-03 11:49:46 +02001176static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001178{
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
Daniel Vetterab9412b2013-05-03 11:49:46 +02001183 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001189}
1190
Keith Packard4e634382011-08-06 10:39:45 -07001191static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001193{
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207}
1208
Keith Packard1519b992011-08-06 10:35:34 -07001209static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001212 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001217 return false;
1218 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001220 return false;
1221 }
1222 return true;
1223}
1224
1225static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
Jesse Barnes291906f2011-02-02 12:28:03 -08001256static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001257 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001258{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001259 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001262 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001263
Daniel Vetter75c5da22012-09-10 21:58:29 +02001264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001266 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001267}
1268
1269static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001272 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001275 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001276
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001278 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001279 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001280}
1281
1282static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001287
Keith Packardf0575e92011-07-25 22:12:43 -07001288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001295 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001296 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001302 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001303
Paulo Zanonie2debe92013-02-18 19:00:27 -03001304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001307}
1308
Daniel Vetter87442f72013-06-06 00:52:17 +02001309static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001310{
1311 int reg;
1312 u32 val;
1313
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001314 assert_pipe_disabled(dev_priv, pipe);
1315
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001316 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337}
1338
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001339static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001340{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001345
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001346 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001347
1348 /* No really, not for ILK+ */
1349 BUG_ON(dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001350
1351 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001354
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001372
1373 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001374 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001377 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001380 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
Jesse Barnes89b667f2013-04-18 14:51:36 -07001413void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414{
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425}
1426
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001427/**
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001428 * ironlake_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
Daniel Vettere2b78262013-06-07 23:10:03 +02001435static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001436{
Daniel Vettere2b78262013-06-07 23:10:03 +02001437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001439
Chris Wilson48da64a2012-05-13 20:16:12 +01001440 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001441 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001442 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001447
Daniel Vetter46edb022013-06-05 13:34:12 +02001448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001450 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001451
Daniel Vettercdbd2312013-06-05 13:34:03 +02001452 if (pll->active++) {
1453 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001454 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001455 return;
1456 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001457 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001458
Daniel Vetter46edb022013-06-05 13:34:12 +02001459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001460 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001461 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001462}
1463
Daniel Vettere2b78262013-06-07 23:10:03 +02001464static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001465{
Daniel Vettere2b78262013-06-07 23:10:03 +02001466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001468
Jesse Barnes92f25842011-01-04 15:09:34 -08001469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001471 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001472 return;
1473
Chris Wilson48da64a2012-05-13 20:16:12 +01001474 if (WARN_ON(pll->refcount == 0))
1475 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001476
Daniel Vetter46edb022013-06-05 13:34:12 +02001477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001479 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001480
Chris Wilson48da64a2012-05-13 20:16:12 +01001481 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001482 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001483 return;
1484 }
1485
Daniel Vettere9d69442013-06-05 13:34:15 +02001486 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001487 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001488 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001489 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001490
Daniel Vetter46edb022013-06-05 13:34:12 +02001491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001492 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001493 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001494}
1495
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001496static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001498{
Daniel Vetter23670b322012-11-01 09:15:30 +01001499 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001502 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001508 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001509 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
Daniel Vetter23670b322012-11-01 09:15:30 +01001515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001522 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001523
Daniel Vetterab9412b2013-05-03 11:49:46 +02001524 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001525 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001526 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001535 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001544 else
1545 val |= TRANS_PROGRESSIVE;
1546
Jesse Barnes040484a2011-01-03 12:14:26 -08001547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001550}
1551
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001552static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001553 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001554{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001555 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001560 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001563
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001569 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001571
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001574 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001575 else
1576 val |= TRANS_PROGRESSIVE;
1577
Daniel Vetterab9412b2013-05-03 11:49:46 +02001578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001580 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001581}
1582
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001583static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001585{
Daniel Vetter23670b322012-11-01 09:15:30 +01001586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
Jesse Barnes291906f2011-02-02 12:28:03 -08001593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
Daniel Vetterab9412b2013-05-03 11:49:46 +02001596 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001611}
1612
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001613static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001614{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001615 u32 val;
1616
Daniel Vetterab9412b2013-05-03 11:49:46 +02001617 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001618 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001619 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001620 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001622 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001627 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001628}
1629
1630/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001631 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001644static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001646{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001649 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001650 int reg;
1651 u32 val;
1652
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
Paulo Zanoni681e5812012-12-06 11:12:38 -02001656 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
Jesse Barnesb24e7172011-01-04 15:09:30 -08001661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001677
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001678 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001679 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685}
1686
1687/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001688 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001712 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001718 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001719 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725}
1726
Keith Packardd74362c2011-07-28 14:47:14 -07001727/*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001731void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001732 enum plane plane)
1733{
Damien Lespiau14f86142012-10-29 15:24:49 +00001734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
Keith Packardd74362c2011-07-28 14:47:14 -07001738}
1739
Jesse Barnesb24e7172011-01-04 15:09:30 -08001740/**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750{
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001763 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765}
1766
Jesse Barnesb24e7172011-01-04 15:09:30 -08001767/**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789}
1790
Chris Wilson693db182013-03-05 14:52:39 +00001791static bool need_vtd_wa(struct drm_device *dev)
1792{
1793#ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796#endif
1797 return false;
1798}
1799
Chris Wilson127bd2a2010-07-23 23:32:05 +01001800int
Chris Wilson48b956c2010-09-14 12:50:34 +01001801intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001802 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001803 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001804{
Chris Wilsonce453d82011-02-21 14:43:56 +00001805 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001806 u32 alignment;
1807 int ret;
1808
Chris Wilson05394f32010-11-08 19:18:58 +00001809 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001810 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001813 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
Daniel Vetter8bb6e952013-04-06 23:54:56 +02001823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
Chris Wilson693db182013-03-05 14:52:39 +00001832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
Chris Wilsonce453d82011-02-21 14:43:56 +00001840 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001842 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001843 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
Chris Wilson06d98132012-04-17 15:31:24 +01001850 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001851 if (ret)
1852 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001853
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001854 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001855
Chris Wilsonce453d82011-02-21 14:43:56 +00001856 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001857 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001858
1859err_unpin:
1860 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001861err_interruptible:
1862 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001863 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001864}
1865
Chris Wilson1690e1e2011-12-14 13:57:08 +01001866void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867{
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870}
1871
Daniel Vetterc2c75132012-07-05 12:17:30 +02001872/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00001874unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02001878{
Chris Wilsonbc752862013-02-21 20:04:31 +00001879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001881
Chris Wilsonbc752862013-02-21 20:04:31 +00001882 tile_rows = *y / 8;
1883 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001884
Chris Wilsonbc752862013-02-21 20:04:31 +00001885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02001897}
1898
Jesse Barnes17638cd2011-06-24 12:19:23 -07001899static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001901{
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001906 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001907 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02001908 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07001909 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01001910 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07001911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03001917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes81255562010-08-02 12:07:50 -07001918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001923
Chris Wilson5eddb702010-09-11 13:48:45 +01001924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07001930 dspcntr |= DISPPLANE_8BPP;
1931 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07001935 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02001936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07001954 break;
1955 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01001956 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07001957 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02001958
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001959 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00001960 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07001961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
Ville Syrjäläde1aa622013-06-07 10:47:01 +03001966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
Chris Wilson5eddb702010-09-11 13:48:45 +01001969 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07001970
Daniel Vettere506a0c2012-07-05 12:17:29 +02001971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07001972
Daniel Vetterc2c75132012-07-05 12:17:30 +02001973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00001975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02001978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02001980 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001981 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02001982
1983 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02001985 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001986 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02001987 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001989 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02001990 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001991 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02001992 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01001993 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001994
Jesse Barnes17638cd2011-06-24 12:19:23 -07001995 return 0;
1996}
1997
1998static int ironlake_update_plane(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb, int x, int y)
2000{
2001 struct drm_device *dev = crtc->dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004 struct intel_framebuffer *intel_fb;
2005 struct drm_i915_gem_object *obj;
2006 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002007 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002008 u32 dspcntr;
2009 u32 reg;
2010
2011 switch (plane) {
2012 case 0:
2013 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002014 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002015 break;
2016 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002017 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes17638cd2011-06-24 12:19:23 -07002018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2023
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002028 switch (fb->pixel_format) {
2029 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002030 dspcntr |= DISPPLANE_8BPP;
2031 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002034 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2038 break;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2042 break;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2046 break;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002050 break;
2051 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002052 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002053 }
2054
2055 if (obj->tiling_mode != I915_TILING_NONE)
2056 dspcntr |= DISPPLANE_TILED;
2057 else
2058 dspcntr &= ~DISPPLANE_TILED;
2059
2060 /* must disable */
2061 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2062
2063 I915_WRITE(reg, dspcntr);
2064
Daniel Vettere506a0c2012-07-05 12:17:29 +02002065 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002066 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2069 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002070 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002071
Daniel Vettere506a0c2012-07-05 12:17:29 +02002072 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002074 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002075 I915_MODIFY_DISPBASE(DSPSURF(plane),
2076 obj->gtt_offset + intel_crtc->dspaddr_offset);
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002077 if (IS_HASWELL(dev)) {
2078 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2079 } else {
2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
2082 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002083 POSTING_READ(reg);
2084
2085 return 0;
2086}
2087
2088/* Assume fb object is pinned & idle & fenced and just update base pointers */
2089static int
2090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 int x, int y, enum mode_set_atomic state)
2092{
2093 struct drm_device *dev = crtc->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002095
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002096 if (dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002098 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002099
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002100 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002101}
2102
Ville Syrjälä96a02912013-02-18 19:08:49 +02002103void intel_display_handle_reset(struct drm_device *dev)
2104{
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct drm_crtc *crtc;
2107
2108 /*
2109 * Flips in the rings have been nuked by the reset,
2110 * so complete all pending flips so that user space
2111 * will get its events and not get stuck.
2112 *
2113 * Also update the base address of all primary
2114 * planes to the the last fb to make sure we're
2115 * showing the correct fb after a reset.
2116 *
2117 * Need to make two loops over the crtcs so that we
2118 * don't try to grab a crtc mutex before the
2119 * pending_flip_queue really got woken up.
2120 */
2121
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 enum plane plane = intel_crtc->plane;
2125
2126 intel_prepare_page_flip(dev, plane);
2127 intel_finish_page_flip_plane(dev, plane);
2128 }
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 mutex_lock(&crtc->mutex);
2134 if (intel_crtc->active)
2135 dev_priv->display.update_plane(crtc, crtc->fb,
2136 crtc->x, crtc->y);
2137 mutex_unlock(&crtc->mutex);
2138 }
2139}
2140
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002141static int
Chris Wilson14667a42012-04-03 17:58:35 +01002142intel_finish_fb(struct drm_framebuffer *old_fb)
2143{
2144 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 bool was_interruptible = dev_priv->mm.interruptible;
2147 int ret;
2148
Chris Wilson14667a42012-04-03 17:58:35 +01002149 /* Big Hammer, we also need to ensure that any pending
2150 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151 * current scanout is retired before unpinning the old
2152 * framebuffer.
2153 *
2154 * This should only fail upon a hung GPU, in which case we
2155 * can safely continue.
2156 */
2157 dev_priv->mm.interruptible = false;
2158 ret = i915_gem_object_finish_gpu(obj);
2159 dev_priv->mm.interruptible = was_interruptible;
2160
2161 return ret;
2162}
2163
Ville Syrjälä198598d2012-10-31 17:50:24 +02002164static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2165{
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_master_private *master_priv;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (!dev->primary->master)
2171 return;
2172
2173 master_priv = dev->primary->master->driver_priv;
2174 if (!master_priv->sarea_priv)
2175 return;
2176
2177 switch (intel_crtc->pipe) {
2178 case 0:
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
2181 break;
2182 case 1:
2183 master_priv->sarea_priv->pipeB_x = x;
2184 master_priv->sarea_priv->pipeB_y = y;
2185 break;
2186 default:
2187 break;
2188 }
2189}
2190
Chris Wilson14667a42012-04-03 17:58:35 +01002191static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002192intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002193 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002194{
2195 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002196 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002198 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002199 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002200
2201 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002202 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002203 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002204 return 0;
2205 }
2206
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002207 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002208 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209 plane_name(intel_crtc->plane),
2210 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002211 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002212 }
2213
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002214 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002215 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002216 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002217 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002218 if (ret != 0) {
2219 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002220 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002221 return ret;
2222 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002223
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002224 /* Update pipe size and adjust fitter if needed */
2225 if (i915_fastboot) {
2226 I915_WRITE(PIPESRC(intel_crtc->pipe),
2227 ((crtc->mode.hdisplay - 1) << 16) |
2228 (crtc->mode.vdisplay - 1));
2229 if (!intel_crtc->config.pch_pfit.size &&
2230 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2231 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2232 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2233 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2234 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2235 }
2236 }
2237
Daniel Vetter94352cf2012-07-05 22:51:56 +02002238 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002239 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002240 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002241 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002242 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002243 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002244 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002245
Daniel Vetter94352cf2012-07-05 22:51:56 +02002246 old_fb = crtc->fb;
2247 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002248 crtc->x = x;
2249 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002250
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002251 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002252 if (intel_crtc->active && old_fb != fb)
2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002254 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002255 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002256
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002257 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002258 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002259
Ville Syrjälä198598d2012-10-31 17:50:24 +02002260 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002261
2262 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002263}
2264
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002265static void intel_fdi_normal_train(struct drm_crtc *crtc)
2266{
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 int pipe = intel_crtc->pipe;
2271 u32 reg, temp;
2272
2273 /* enable normal train */
2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002276 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002277 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2278 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002282 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002283 I915_WRITE(reg, temp);
2284
2285 reg = FDI_RX_CTL(pipe);
2286 temp = I915_READ(reg);
2287 if (HAS_PCH_CPT(dev)) {
2288 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2289 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2290 } else {
2291 temp &= ~FDI_LINK_TRAIN_NONE;
2292 temp |= FDI_LINK_TRAIN_NONE;
2293 }
2294 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2295
2296 /* wait one idle pattern time */
2297 POSTING_READ(reg);
2298 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002299
2300 /* IVB wants error correction enabled */
2301 if (IS_IVYBRIDGE(dev))
2302 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2303 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002304}
2305
Daniel Vetter1e833f42013-02-19 22:31:57 +01002306static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2307{
2308 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2309}
2310
Daniel Vetter01a415f2012-10-27 15:58:40 +02002311static void ivb_modeset_global_resources(struct drm_device *dev)
2312{
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *pipe_B_crtc =
2315 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2316 struct intel_crtc *pipe_C_crtc =
2317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2318 uint32_t temp;
2319
Daniel Vetter1e833f42013-02-19 22:31:57 +01002320 /*
2321 * When everything is off disable fdi C so that we could enable fdi B
2322 * with all lanes. Note that we don't care about enabled pipes without
2323 * an enabled pch encoder.
2324 */
2325 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2326 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002327 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2328 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2329
2330 temp = I915_READ(SOUTH_CHICKEN1);
2331 temp &= ~FDI_BC_BIFURCATION_SELECT;
2332 DRM_DEBUG_KMS("disabling fdi C rx\n");
2333 I915_WRITE(SOUTH_CHICKEN1, temp);
2334 }
2335}
2336
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002337/* The FDI link training functions for ILK/Ibexpeak. */
2338static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2339{
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002344 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002345 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002346
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002347 /* FDI needs bits from pipe & plane first */
2348 assert_pipe_enabled(dev_priv, pipe);
2349 assert_plane_enabled(dev_priv, plane);
2350
Adam Jacksone1a44742010-06-25 15:32:14 -04002351 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2352 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002353 reg = FDI_RX_IMR(pipe);
2354 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002355 temp &= ~FDI_RX_SYMBOL_LOCK;
2356 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002357 I915_WRITE(reg, temp);
2358 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002359 udelay(150);
2360
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002361 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002364 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2365 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002368 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002369
Chris Wilson5eddb702010-09-11 13:48:45 +01002370 reg = FDI_RX_CTL(pipe);
2371 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002372 temp &= ~FDI_LINK_TRAIN_NONE;
2373 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002374 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2375
2376 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002377 udelay(150);
2378
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002379 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002380 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2381 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2382 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002383
Chris Wilson5eddb702010-09-11 13:48:45 +01002384 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002385 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002386 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002387 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2388
2389 if ((temp & FDI_RX_BIT_LOCK)) {
2390 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002391 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002392 break;
2393 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002394 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002395 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002396 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002397
2398 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002403 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002404
Chris Wilson5eddb702010-09-11 13:48:45 +01002405 reg = FDI_RX_CTL(pipe);
2406 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002409 I915_WRITE(reg, temp);
2410
2411 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002412 udelay(150);
2413
Chris Wilson5eddb702010-09-11 13:48:45 +01002414 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002415 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002416 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002417 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2418
2419 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002420 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002421 DRM_DEBUG_KMS("FDI train 2 done.\n");
2422 break;
2423 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002424 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002425 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002426 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002427
2428 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002429
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002430}
2431
Akshay Joshi0206e352011-08-16 15:34:10 -04002432static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002433 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2434 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2435 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2436 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2437};
2438
2439/* The FDI link training functions for SNB/Cougarpoint. */
2440static void gen6_fdi_link_train(struct drm_crtc *crtc)
2441{
2442 struct drm_device *dev = crtc->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002446 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002447
Adam Jacksone1a44742010-06-25 15:32:14 -04002448 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2449 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002450 reg = FDI_RX_IMR(pipe);
2451 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002452 temp &= ~FDI_RX_SYMBOL_LOCK;
2453 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002454 I915_WRITE(reg, temp);
2455
2456 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002457 udelay(150);
2458
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002459 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002462 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2463 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
2466 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2467 /* SNB-B */
2468 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002470
Daniel Vetterd74cf322012-10-26 10:58:13 +02002471 I915_WRITE(FDI_RX_MISC(pipe),
2472 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2473
Chris Wilson5eddb702010-09-11 13:48:45 +01002474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002476 if (HAS_PCH_CPT(dev)) {
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479 } else {
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002483 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002486 udelay(150);
2487
Akshay Joshi0206e352011-08-16 15:34:10 -04002488 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002489 reg = FDI_TX_CTL(pipe);
2490 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002493 I915_WRITE(reg, temp);
2494
2495 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002496 udelay(500);
2497
Sean Paulfa37d392012-03-02 12:53:39 -05002498 for (retry = 0; retry < 5; retry++) {
2499 reg = FDI_RX_IIR(pipe);
2500 temp = I915_READ(reg);
2501 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2502 if (temp & FDI_RX_BIT_LOCK) {
2503 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2504 DRM_DEBUG_KMS("FDI train 1 done.\n");
2505 break;
2506 }
2507 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002508 }
Sean Paulfa37d392012-03-02 12:53:39 -05002509 if (retry < 5)
2510 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002511 }
2512 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002513 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002514
2515 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 if (IS_GEN6(dev)) {
2521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2522 /* SNB-B */
2523 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2524 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002525 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526
Chris Wilson5eddb702010-09-11 13:48:45 +01002527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002529 if (HAS_PCH_CPT(dev)) {
2530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2532 } else {
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_2;
2535 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002536 I915_WRITE(reg, temp);
2537
2538 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002539 udelay(150);
2540
Akshay Joshi0206e352011-08-16 15:34:10 -04002541 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002546 I915_WRITE(reg, temp);
2547
2548 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002549 udelay(500);
2550
Sean Paulfa37d392012-03-02 12:53:39 -05002551 for (retry = 0; retry < 5; retry++) {
2552 reg = FDI_RX_IIR(pipe);
2553 temp = I915_READ(reg);
2554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
2560 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002561 }
Sean Paulfa37d392012-03-02 12:53:39 -05002562 if (retry < 5)
2563 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002564 }
2565 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002566 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002567
2568 DRM_DEBUG_KMS("FDI train done.\n");
2569}
2570
Jesse Barnes357555c2011-04-28 15:09:55 -07002571/* Manual link training for Ivy Bridge A0 parts */
2572static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2573{
2574 struct drm_device *dev = crtc->dev;
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577 int pipe = intel_crtc->pipe;
2578 u32 reg, temp, i;
2579
2580 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2581 for train result */
2582 reg = FDI_RX_IMR(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_RX_SYMBOL_LOCK;
2585 temp &= ~FDI_RX_BIT_LOCK;
2586 I915_WRITE(reg, temp);
2587
2588 POSTING_READ(reg);
2589 udelay(150);
2590
Daniel Vetter01a415f2012-10-27 15:58:40 +02002591 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2592 I915_READ(FDI_RX_IIR(pipe)));
2593
Jesse Barnes357555c2011-04-28 15:09:55 -07002594 /* enable CPU FDI TX and PCH FDI RX */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002597 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2598 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Jesse Barnes357555c2011-04-28 15:09:55 -07002599 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002603 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
Daniel Vetterd74cf322012-10-26 10:58:13 +02002606 I915_WRITE(FDI_RX_MISC(pipe),
2607 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2608
Jesse Barnes357555c2011-04-28 15:09:55 -07002609 reg = FDI_RX_CTL(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_LINK_TRAIN_AUTO;
2612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2613 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002614 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002615 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2616
2617 POSTING_READ(reg);
2618 udelay(150);
2619
Akshay Joshi0206e352011-08-16 15:34:10 -04002620 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(500);
2629
2630 reg = FDI_RX_IIR(pipe);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634 if (temp & FDI_RX_BIT_LOCK ||
2635 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002637 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002638 break;
2639 }
2640 }
2641 if (i == 4)
2642 DRM_ERROR("FDI train 1 fail!\n");
2643
2644 /* Train 2 */
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 I915_WRITE(reg, temp);
2652
2653 reg = FDI_RX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(150);
2661
Akshay Joshi0206e352011-08-16 15:34:10 -04002662 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= snb_b_fdi_train_param[i];
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(500);
2671
2672 reg = FDI_RX_IIR(pipe);
2673 temp = I915_READ(reg);
2674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676 if (temp & FDI_RX_SYMBOL_LOCK) {
2677 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002678 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002679 break;
2680 }
2681 }
2682 if (i == 4)
2683 DRM_ERROR("FDI train 2 fail!\n");
2684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686}
2687
Daniel Vetter88cefb62012-08-12 19:27:14 +02002688static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002689{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002690 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002691 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002692 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002693 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002694
Jesse Barnesc64e3112010-09-10 11:27:03 -07002695
Jesse Barnes0e23b992010-09-10 11:10:00 -07002696 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002697 reg = FDI_RX_CTL(pipe);
2698 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002699 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2700 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002701 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01002702 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2703
2704 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002705 udelay(200);
2706
2707 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002708 temp = I915_READ(reg);
2709 I915_WRITE(reg, temp | FDI_PCDCLK);
2710
2711 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002712 udelay(200);
2713
Paulo Zanoni20749732012-11-23 15:30:38 -02002714 /* Enable CPU FDI TX PLL, always on for Ironlake */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2718 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002719
Paulo Zanoni20749732012-11-23 15:30:38 -02002720 POSTING_READ(reg);
2721 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002722 }
2723}
2724
Daniel Vetter88cefb62012-08-12 19:27:14 +02002725static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2726{
2727 struct drm_device *dev = intel_crtc->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 int pipe = intel_crtc->pipe;
2730 u32 reg, temp;
2731
2732 /* Switch from PCDclk to Rawclk */
2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2736
2737 /* Disable CPU FDI TX PLL */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2741
2742 POSTING_READ(reg);
2743 udelay(100);
2744
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2748
2749 /* Wait for the clocks to turn off. */
2750 POSTING_READ(reg);
2751 udelay(100);
2752}
2753
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002754static void ironlake_fdi_disable(struct drm_crtc *crtc)
2755{
2756 struct drm_device *dev = crtc->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759 int pipe = intel_crtc->pipe;
2760 u32 reg, temp;
2761
2762 /* disable CPU FDI tx and PCH FDI rx */
2763 reg = FDI_TX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2766 POSTING_READ(reg);
2767
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002771 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002772 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2773
2774 POSTING_READ(reg);
2775 udelay(100);
2776
2777 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002778 if (HAS_PCH_IBX(dev)) {
2779 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002780 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002781
2782 /* still set train pattern 1 */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2794 } else {
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1;
2797 }
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805}
2806
Chris Wilson5bb61642012-09-27 21:25:58 +01002807static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2808{
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä10d83732013-01-29 18:13:34 +02002811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5bb61642012-09-27 21:25:58 +01002812 unsigned long flags;
2813 bool pending;
2814
Ville Syrjälä10d83732013-01-29 18:13:34 +02002815 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2816 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
Chris Wilson5bb61642012-09-27 21:25:58 +01002817 return false;
2818
2819 spin_lock_irqsave(&dev->event_lock, flags);
2820 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821 spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823 return pending;
2824}
2825
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002826static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827{
Chris Wilson0f911282012-04-17 10:05:38 +01002828 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002829 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002830
2831 if (crtc->fb == NULL)
2832 return;
2833
Daniel Vetter2c10d572012-12-20 21:24:07 +01002834 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2835
Chris Wilson5bb61642012-09-27 21:25:58 +01002836 wait_event(dev_priv->pending_flip_queue,
2837 !intel_crtc_has_pending_flip(crtc));
2838
Chris Wilson0f911282012-04-17 10:05:38 +01002839 mutex_lock(&dev->struct_mutex);
2840 intel_finish_fb(crtc->fb);
2841 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002842}
2843
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002844/* Program iCLKIP clock to the desired frequency */
2845static void lpt_program_iclkip(struct drm_crtc *crtc)
2846{
2847 struct drm_device *dev = crtc->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2850 u32 temp;
2851
Daniel Vetter09153002012-12-12 14:06:44 +01002852 mutex_lock(&dev_priv->dpio_lock);
2853
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002854 /* It is necessary to ungate the pixclk gate prior to programming
2855 * the divisors, and gate it back when it is done.
2856 */
2857 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2858
2859 /* Disable SSCCTL */
2860 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002861 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2862 SBI_SSCCTL_DISABLE,
2863 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002864
2865 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2866 if (crtc->mode.clock == 20000) {
2867 auxdiv = 1;
2868 divsel = 0x41;
2869 phaseinc = 0x20;
2870 } else {
2871 /* The iCLK virtual clock root frequency is in MHz,
2872 * but the crtc->mode.clock in in KHz. To get the divisors,
2873 * it is necessary to divide one by another, so we
2874 * convert the virtual clock precision to KHz here for higher
2875 * precision.
2876 */
2877 u32 iclk_virtual_root_freq = 172800 * 1000;
2878 u32 iclk_pi_range = 64;
2879 u32 desired_divisor, msb_divisor_value, pi_value;
2880
2881 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2882 msb_divisor_value = desired_divisor / iclk_pi_range;
2883 pi_value = desired_divisor % iclk_pi_range;
2884
2885 auxdiv = 0;
2886 divsel = msb_divisor_value - 2;
2887 phaseinc = pi_value;
2888 }
2889
2890 /* This should not happen with any sane values */
2891 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2892 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2893 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2894 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2895
2896 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2897 crtc->mode.clock,
2898 auxdiv,
2899 divsel,
2900 phasedir,
2901 phaseinc);
2902
2903 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002904 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002905 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2906 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2907 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2908 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2909 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2910 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002911 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002912
2913 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002914 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002915 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2916 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002917 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002918
2919 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002920 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002921 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002922 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002923
2924 /* Wait for initialization time */
2925 udelay(24);
2926
2927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01002928
2929 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002930}
2931
Daniel Vetter275f01b22013-05-03 11:49:47 +02002932static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2933 enum pipe pch_transcoder)
2934{
2935 struct drm_device *dev = crtc->base.dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2938
2939 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2940 I915_READ(HTOTAL(cpu_transcoder)));
2941 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2942 I915_READ(HBLANK(cpu_transcoder)));
2943 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2944 I915_READ(HSYNC(cpu_transcoder)));
2945
2946 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2947 I915_READ(VTOTAL(cpu_transcoder)));
2948 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2949 I915_READ(VBLANK(cpu_transcoder)));
2950 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2951 I915_READ(VSYNC(cpu_transcoder)));
2952 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2953 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2954}
2955
Jesse Barnesf67a5592011-01-05 10:31:48 -08002956/*
2957 * Enable PCH resources required for PCH ports:
2958 * - PCH PLLs
2959 * - FDI training & RX/TX
2960 * - update transcoder timings
2961 * - DP transcoding bits
2962 * - transcoder
2963 */
2964static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002965{
2966 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002970 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002971
Daniel Vetterab9412b2013-05-03 11:49:46 +02002972 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01002973
Daniel Vettercd986ab2012-10-26 10:58:12 +02002974 /* Write the TU size bits before fdi link training, so that error
2975 * detection works. */
2976 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2977 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2978
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002979 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002980 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002981
Daniel Vetter572deb32012-10-27 18:46:14 +02002982 /* XXX: pch pll's can be enabled any time before we enable the PCH
2983 * transcoder, and we actually should do this to not upset any PCH
2984 * transcoder that already use the clock when we share it.
2985 *
Daniel Vettere72f9fb2013-06-05 13:34:06 +02002986 * Note that enable_shared_dpll tries to do the right thing, but
2987 * get_shared_dpll unconditionally resets the pll - we need that to have
2988 * the right LVDS enable sequence. */
2989 ironlake_enable_shared_dpll(intel_crtc);
Chris Wilson6f13b7b2012-05-13 09:54:09 +01002990
Paulo Zanoni303b81e2012-10-31 18:12:23 -02002991 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002992 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07002993
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002994 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02002995 temp |= TRANS_DPLL_ENABLE(pipe);
2996 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02002997 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002998 temp |= sel;
2999 else
3000 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003001 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003002 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003003
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003004 /* set transcoder timing, panel must allow it */
3005 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003006 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003007
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003008 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003009
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003010 /* For PCH DP, enable TRANS_DP_CTL */
3011 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003012 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3013 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003014 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003015 reg = TRANS_DP_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003018 TRANS_DP_SYNC_MASK |
3019 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003020 temp |= (TRANS_DP_OUTPUT_ENABLE |
3021 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003022 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003023
3024 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003025 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003026 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003027 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003028
3029 switch (intel_trans_dp_port_sel(crtc)) {
3030 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003031 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003032 break;
3033 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003034 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003035 break;
3036 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003037 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003038 break;
3039 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003040 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003041 }
3042
Chris Wilson5eddb702010-09-11 13:48:45 +01003043 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003044 }
3045
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003046 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003047}
3048
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003049static void lpt_pch_enable(struct drm_crtc *crtc)
3050{
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003054 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003055
Daniel Vetterab9412b2013-05-03 11:49:46 +02003056 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003057
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003058 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003059
Paulo Zanoni0540e482012-10-31 18:12:40 -02003060 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003061 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003062
Paulo Zanoni937bb612012-10-31 18:12:47 -02003063 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003064}
3065
Daniel Vettere2b78262013-06-07 23:10:03 +02003066static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003067{
Daniel Vettere2b78262013-06-07 23:10:03 +02003068 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003069
3070 if (pll == NULL)
3071 return;
3072
3073 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003074 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003075 return;
3076 }
3077
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003078 if (--pll->refcount == 0) {
3079 WARN_ON(pll->on);
3080 WARN_ON(pll->active);
3081 }
3082
Daniel Vettera43f6e02013-06-07 23:10:32 +02003083 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003084}
3085
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003086static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003087{
Daniel Vettere2b78262013-06-07 23:10:03 +02003088 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3089 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003091
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003092 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003093 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3094 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003095 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003096 }
3097
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003098 if (HAS_PCH_IBX(dev_priv->dev)) {
3099 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vettere2b78262013-06-07 23:10:03 +02003100 i = crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003101 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003102
Daniel Vetter46edb022013-06-05 13:34:12 +02003103 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3104 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003105
3106 goto found;
3107 }
3108
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003109 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3110 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003111
3112 /* Only want to check enabled timings first */
3113 if (pll->refcount == 0)
3114 continue;
3115
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003116 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3117 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003118 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003119 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003120 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003121
3122 goto found;
3123 }
3124 }
3125
3126 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3128 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003129 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003130 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3131 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003132 goto found;
3133 }
3134 }
3135
3136 return NULL;
3137
3138found:
Daniel Vettera43f6e02013-06-07 23:10:32 +02003139 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003140 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3141 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003142
Daniel Vettercdbd2312013-06-05 13:34:03 +02003143 if (pll->active == 0) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02003144 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3145 sizeof(pll->hw_state));
3146
Daniel Vetter46edb022013-06-05 13:34:12 +02003147 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003148 WARN_ON(pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02003149 assert_shared_dpll_disabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003150
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02003151 pll->mode_set(dev_priv, pll);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003152 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003153 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003154
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003155 return pll;
3156}
3157
Daniel Vettera1520312013-05-03 11:49:50 +02003158static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003159{
3160 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003161 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003162 u32 temp;
3163
3164 temp = I915_READ(dslreg);
3165 udelay(500);
3166 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003167 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003168 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003169 }
3170}
3171
Jesse Barnesb074cec2013-04-25 12:55:02 -07003172static void ironlake_pfit_enable(struct intel_crtc *crtc)
3173{
3174 struct drm_device *dev = crtc->base.dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 int pipe = crtc->pipe;
3177
Jesse Barnes0ef37f32013-05-03 13:26:37 -07003178 if (crtc->config.pch_pfit.size) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003179 /* Force use of hard-coded filter coefficients
3180 * as some pre-programmed values are broken,
3181 * e.g. x201.
3182 */
3183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3185 PF_PIPE_SEL_IVB(pipe));
3186 else
3187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3188 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003190 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003191}
3192
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003193static void intel_enable_planes(struct drm_crtc *crtc)
3194{
3195 struct drm_device *dev = crtc->dev;
3196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197 struct intel_plane *intel_plane;
3198
3199 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200 if (intel_plane->pipe == pipe)
3201 intel_plane_restore(&intel_plane->base);
3202}
3203
3204static void intel_disable_planes(struct drm_crtc *crtc)
3205{
3206 struct drm_device *dev = crtc->dev;
3207 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3208 struct intel_plane *intel_plane;
3209
3210 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3211 if (intel_plane->pipe == pipe)
3212 intel_plane_disable(&intel_plane->base);
3213}
3214
Jesse Barnesf67a5592011-01-05 10:31:48 -08003215static void ironlake_crtc_enable(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003220 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003221 int pipe = intel_crtc->pipe;
3222 int plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003223
Daniel Vetter08a48462012-07-02 11:43:47 +02003224 WARN_ON(!crtc->enabled);
3225
Jesse Barnesf67a5592011-01-05 10:31:48 -08003226 if (intel_crtc->active)
3227 return;
3228
3229 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003230
3231 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3232 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3233
Jesse Barnesf67a5592011-01-05 10:31:48 -08003234 intel_update_watermarks(dev);
3235
Daniel Vetterf6736a12013-06-05 13:34:30 +02003236 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003237 if (encoder->pre_enable)
3238 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003239
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003240 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003241 /* Note: FDI PLL enabling _must_ be done before we enable the
3242 * cpu pipes, hence this is separate from all the other fdi/pch
3243 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003244 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003245 } else {
3246 assert_fdi_tx_disabled(dev_priv, pipe);
3247 assert_fdi_rx_disabled(dev_priv, pipe);
3248 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003249
Jesse Barnesb074cec2013-04-25 12:55:02 -07003250 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003251
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003252 /*
3253 * On ILK+ LUT must be loaded before the pipe is running but with
3254 * clocks enabled
3255 */
3256 intel_crtc_load_lut(crtc);
3257
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003258 intel_enable_pipe(dev_priv, pipe,
3259 intel_crtc->config.has_pch_encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003260 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003261 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003262 intel_crtc_update_cursor(crtc, true);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003263
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003264 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003265 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003266
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003267 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003268 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003269 mutex_unlock(&dev->struct_mutex);
3270
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003271 for_each_encoder_on_crtc(dev, crtc, encoder)
3272 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003273
3274 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003275 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003276
3277 /*
3278 * There seems to be a race in PCH platform hw (at least on some
3279 * outputs) where an enabled pipe still completes any pageflip right
3280 * away (as if the pipe is off) instead of waiting for vblank. As soon
3281 * as the first vblank happend, everything works as expected. Hence just
3282 * wait for one vblank before returning to avoid strange things
3283 * happening.
3284 */
3285 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003286}
3287
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003288/* IPS only exists on ULT machines and is tied to pipe A. */
3289static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3290{
Damien Lespiauf5adf942013-06-24 18:29:34 +01003291 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003292}
3293
3294static void hsw_enable_ips(struct intel_crtc *crtc)
3295{
3296 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3297
3298 if (!crtc->config.ips_enabled)
3299 return;
3300
3301 /* We can only enable IPS after we enable a plane and wait for a vblank.
3302 * We guarantee that the plane is enabled by calling intel_enable_ips
3303 * only after intel_enable_plane. And intel_enable_plane already waits
3304 * for a vblank, so all we need to do here is to enable the IPS bit. */
3305 assert_plane_enabled(dev_priv, crtc->plane);
3306 I915_WRITE(IPS_CTL, IPS_ENABLE);
3307}
3308
3309static void hsw_disable_ips(struct intel_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->base.dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313
3314 if (!crtc->config.ips_enabled)
3315 return;
3316
3317 assert_plane_enabled(dev_priv, crtc->plane);
3318 I915_WRITE(IPS_CTL, 0);
3319
3320 /* We need to wait for a vblank before we can disable the plane. */
3321 intel_wait_for_vblank(dev, crtc->pipe);
3322}
3323
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003324static void haswell_crtc_enable(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 struct intel_encoder *encoder;
3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003332
3333 WARN_ON(!crtc->enabled);
3334
3335 if (intel_crtc->active)
3336 return;
3337
3338 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003339
3340 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3341 if (intel_crtc->config.has_pch_encoder)
3342 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3343
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003344 intel_update_watermarks(dev);
3345
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003346 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02003347 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003348
3349 for_each_encoder_on_crtc(dev, crtc, encoder)
3350 if (encoder->pre_enable)
3351 encoder->pre_enable(encoder);
3352
Paulo Zanoni1f544382012-10-24 11:32:00 -02003353 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003354
Jesse Barnesb074cec2013-04-25 12:55:02 -07003355 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003356
3357 /*
3358 * On ILK+ LUT must be loaded before the pipe is running but with
3359 * clocks enabled
3360 */
3361 intel_crtc_load_lut(crtc);
3362
Paulo Zanoni1f544382012-10-24 11:32:00 -02003363 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00003364 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003365
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003366 intel_enable_pipe(dev_priv, pipe,
3367 intel_crtc->config.has_pch_encoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003368 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003369 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003370 intel_crtc_update_cursor(crtc, true);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003371
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003372 hsw_enable_ips(intel_crtc);
3373
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003374 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003375 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003376
3377 mutex_lock(&dev->struct_mutex);
3378 intel_update_fbc(dev);
3379 mutex_unlock(&dev->struct_mutex);
3380
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 encoder->enable(encoder);
3383
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003384 /*
3385 * There seems to be a race in PCH platform hw (at least on some
3386 * outputs) where an enabled pipe still completes any pageflip right
3387 * away (as if the pipe is off) instead of waiting for vblank. As soon
3388 * as the first vblank happend, everything works as expected. Hence just
3389 * wait for one vblank before returning to avoid strange things
3390 * happening.
3391 */
3392 intel_wait_for_vblank(dev, intel_crtc->pipe);
3393}
3394
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003395static void ironlake_pfit_disable(struct intel_crtc *crtc)
3396{
3397 struct drm_device *dev = crtc->base.dev;
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 int pipe = crtc->pipe;
3400
3401 /* To avoid upsetting the power well on haswell only disable the pfit if
3402 * it's in use. The hw state code will make sure we get this right. */
3403 if (crtc->config.pch_pfit.size) {
3404 I915_WRITE(PF_CTL(pipe), 0);
3405 I915_WRITE(PF_WIN_POS(pipe), 0);
3406 I915_WRITE(PF_WIN_SZ(pipe), 0);
3407 }
3408}
3409
Jesse Barnes6be4a602010-09-10 10:26:01 -07003410static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003415 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003418 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003419
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003420
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003421 if (!intel_crtc->active)
3422 return;
3423
Daniel Vetterea9d7582012-07-10 10:42:52 +02003424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3426
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003427 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003428 drm_vblank_off(dev, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003429
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07003430 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01003431 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003432
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003433 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003434 intel_disable_planes(crtc);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003435 intel_disable_plane(dev_priv, plane, pipe);
3436
Daniel Vetterd925c592013-06-05 13:34:04 +02003437 if (intel_crtc->config.has_pch_encoder)
3438 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3439
Jesse Barnesb24e7172011-01-04 15:09:30 -08003440 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003441
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003442 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003443
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003444 for_each_encoder_on_crtc(dev, crtc, encoder)
3445 if (encoder->post_disable)
3446 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003447
Daniel Vetterd925c592013-06-05 13:34:04 +02003448 if (intel_crtc->config.has_pch_encoder) {
3449 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003450
Daniel Vetterd925c592013-06-05 13:34:04 +02003451 ironlake_disable_pch_transcoder(dev_priv, pipe);
3452 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003453
Daniel Vetterd925c592013-06-05 13:34:04 +02003454 if (HAS_PCH_CPT(dev)) {
3455 /* disable TRANS_DP_CTL */
3456 reg = TRANS_DP_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3459 TRANS_DP_PORT_SEL_MASK);
3460 temp |= TRANS_DP_PORT_SEL_NONE;
3461 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003462
Daniel Vetterd925c592013-06-05 13:34:04 +02003463 /* disable DPLL_SEL */
3464 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003465 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02003466 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003467 }
Daniel Vetterd925c592013-06-05 13:34:04 +02003468
3469 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003470 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02003471
3472 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003473 }
3474
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003475 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003476 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003477
3478 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003479 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003480 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003481}
3482
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003483static void haswell_crtc_disable(struct drm_crtc *crtc)
3484{
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 struct intel_encoder *encoder;
3489 int pipe = intel_crtc->pipe;
3490 int plane = intel_crtc->plane;
Daniel Vetter3b117c82013-04-17 20:15:07 +02003491 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003492
3493 if (!intel_crtc->active)
3494 return;
3495
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 encoder->disable(encoder);
3498
3499 intel_crtc_wait_for_pending_flips(crtc);
3500 drm_vblank_off(dev, pipe);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003501
Rodrigo Vivi891348b2013-05-06 19:37:36 -03003502 /* FBC must be disabled before disabling the plane on HSW. */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07003503 if (dev_priv->fbc.plane == plane)
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003504 intel_disable_fbc(dev);
3505
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003506 hsw_disable_ips(intel_crtc);
3507
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003508 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003509 intel_disable_planes(crtc);
Rodrigo Vivi891348b2013-05-06 19:37:36 -03003510 intel_disable_plane(dev_priv, plane, pipe);
3511
Paulo Zanoni86642812013-04-12 17:57:57 -03003512 if (intel_crtc->config.has_pch_encoder)
3513 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003514 intel_disable_pipe(dev_priv, pipe);
3515
Paulo Zanoniad80a812012-10-24 16:06:19 -02003516 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003517
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003518 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003519
Paulo Zanoni1f544382012-10-24 11:32:00 -02003520 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003521
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 if (encoder->post_disable)
3524 encoder->post_disable(encoder);
3525
Daniel Vetter88adfff2013-03-28 10:42:01 +01003526 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003527 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03003528 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003529 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003530 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003531
3532 intel_crtc->active = false;
3533 intel_update_watermarks(dev);
3534
3535 mutex_lock(&dev->struct_mutex);
3536 intel_update_fbc(dev);
3537 mutex_unlock(&dev->struct_mutex);
3538}
3539
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003540static void ironlake_crtc_off(struct drm_crtc *crtc)
3541{
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003543 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003544}
3545
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003546static void haswell_crtc_off(struct drm_crtc *crtc)
3547{
3548 intel_ddi_put_crtc_pll(crtc);
3549}
3550
Daniel Vetter02e792f2009-09-15 22:57:34 +02003551static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3552{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003553 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003554 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003555 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003556
Chris Wilson23f09ce2010-08-12 13:53:37 +01003557 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003558 dev_priv->mm.interruptible = false;
3559 (void) intel_overlay_switch_off(intel_crtc->overlay);
3560 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003561 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003562 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003563
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003564 /* Let userspace switch the overlay on again. In most cases userspace
3565 * has to recompute where to put it anyway.
3566 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003567}
3568
Egbert Eich61bc95c2013-03-04 09:24:38 -05003569/**
3570 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3571 * cursor plane briefly if not already running after enabling the display
3572 * plane.
3573 * This workaround avoids occasional blank screens when self refresh is
3574 * enabled.
3575 */
3576static void
3577g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3578{
3579 u32 cntl = I915_READ(CURCNTR(pipe));
3580
3581 if ((cntl & CURSOR_MODE) == 0) {
3582 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3583
3584 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3585 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3586 intel_wait_for_vblank(dev_priv->dev, pipe);
3587 I915_WRITE(CURCNTR(pipe), cntl);
3588 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3589 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3590 }
3591}
3592
Jesse Barnes2dd24552013-04-25 12:55:01 -07003593static void i9xx_pfit_enable(struct intel_crtc *crtc)
3594{
3595 struct drm_device *dev = crtc->base.dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc_config *pipe_config = &crtc->config;
3598
Daniel Vetter328d8e82013-05-08 10:36:31 +02003599 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07003600 return;
3601
Daniel Vetterc0b03412013-05-28 12:05:54 +02003602 /*
3603 * The panel fitter should only be adjusted whilst the pipe is disabled,
3604 * according to register description and PRM.
3605 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07003606 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3607 assert_pipe_disabled(dev_priv, crtc->pipe);
3608
Jesse Barnesb074cec2013-04-25 12:55:02 -07003609 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3610 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02003611
3612 /* Border color in case we don't scale up to the full screen. Black by
3613 * default, change to something else for debugging. */
3614 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07003615}
3616
Jesse Barnes89b667f2013-04-18 14:51:36 -07003617static void valleyview_crtc_enable(struct drm_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 struct intel_encoder *encoder;
3623 int pipe = intel_crtc->pipe;
3624 int plane = intel_crtc->plane;
3625
3626 WARN_ON(!crtc->enabled);
3627
3628 if (intel_crtc->active)
3629 return;
3630
3631 intel_crtc->active = true;
3632 intel_update_watermarks(dev);
3633
3634 mutex_lock(&dev_priv->dpio_lock);
3635
3636 for_each_encoder_on_crtc(dev, crtc, encoder)
3637 if (encoder->pre_pll_enable)
3638 encoder->pre_pll_enable(encoder);
3639
Daniel Vetter87442f72013-06-06 00:52:17 +02003640 vlv_enable_pll(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07003641
3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->pre_enable)
3644 encoder->pre_enable(encoder);
3645
3646 /* VLV wants encoder enabling _before_ the pipe is up. */
3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 encoder->enable(encoder);
3649
Jesse Barnes2dd24552013-04-25 12:55:01 -07003650 i9xx_pfit_enable(intel_crtc);
3651
Ville Syrjälä63cbb072013-06-04 13:48:59 +03003652 intel_crtc_load_lut(crtc);
3653
Jesse Barnes89b667f2013-04-18 14:51:36 -07003654 intel_enable_pipe(dev_priv, pipe, false);
3655 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003656 intel_enable_planes(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07003657 intel_crtc_update_cursor(crtc, true);
3658
Ville Syrjäläf440eb12013-06-04 13:49:01 +03003659 intel_update_fbc(dev);
3660
Jesse Barnes89b667f2013-04-18 14:51:36 -07003661 mutex_unlock(&dev_priv->dpio_lock);
3662}
3663
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003664static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003665{
3666 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003669 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003670 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003671 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003672
Daniel Vetter08a48462012-07-02 11:43:47 +02003673 WARN_ON(!crtc->enabled);
3674
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003675 if (intel_crtc->active)
3676 return;
3677
3678 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003679 intel_update_watermarks(dev);
3680
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02003681 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02003682 if (encoder->pre_enable)
3683 encoder->pre_enable(encoder);
3684
Daniel Vetterf6736a12013-06-05 13:34:30 +02003685 i9xx_enable_pll(intel_crtc);
3686
Jesse Barnes2dd24552013-04-25 12:55:01 -07003687 i9xx_pfit_enable(intel_crtc);
3688
Ville Syrjälä63cbb072013-06-04 13:48:59 +03003689 intel_crtc_load_lut(crtc);
3690
Jesse Barnes040484a2011-01-03 12:14:26 -08003691 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003692 intel_enable_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003693 intel_enable_planes(crtc);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03003694 /* The fixup needs to happen before cursor is enabled */
Egbert Eich61bc95c2013-03-04 09:24:38 -05003695 if (IS_G4X(dev))
3696 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03003697 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003698
3699 /* Give the overlay scaler a chance to enable if it's on this pipe */
3700 intel_crtc_dpms_overlay(intel_crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003701
Ville Syrjäläf440eb12013-06-04 13:49:01 +03003702 intel_update_fbc(dev);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003703
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003704 for_each_encoder_on_crtc(dev, crtc, encoder)
3705 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003706}
3707
Daniel Vetter87476d62013-04-11 16:29:06 +02003708static void i9xx_pfit_disable(struct intel_crtc *crtc)
3709{
3710 struct drm_device *dev = crtc->base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02003712
3713 if (!crtc->config.gmch_pfit.control)
3714 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02003715
3716 assert_pipe_disabled(dev_priv, crtc->pipe);
3717
Daniel Vetter328d8e82013-05-08 10:36:31 +02003718 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3719 I915_READ(PFIT_CONTROL));
3720 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02003721}
3722
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003723static void i9xx_crtc_disable(struct drm_crtc *crtc)
3724{
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003728 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003729 int pipe = intel_crtc->pipe;
3730 int plane = intel_crtc->plane;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003731
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003732 if (!intel_crtc->active)
3733 return;
3734
Daniel Vetterea9d7582012-07-10 10:42:52 +02003735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3737
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003738 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003741
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07003742 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01003743 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003744
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003745 intel_crtc_dpms_overlay(intel_crtc, false);
3746 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003747 intel_disable_planes(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003748 intel_disable_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003749
Jesse Barnesb24e7172011-01-04 15:09:30 -08003750 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003751
Daniel Vetter87476d62013-04-11 16:29:06 +02003752 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02003753
Jesse Barnes89b667f2013-04-18 14:51:36 -07003754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 if (encoder->post_disable)
3756 encoder->post_disable(encoder);
3757
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003758 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003759
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003760 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003761 intel_update_fbc(dev);
3762 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003763}
3764
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003765static void i9xx_crtc_off(struct drm_crtc *crtc)
3766{
3767}
3768
Daniel Vetter976f8a22012-07-08 22:34:21 +02003769static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3770 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003771{
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_master_private *master_priv;
3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003776
3777 if (!dev->primary->master)
3778 return;
3779
3780 master_priv = dev->primary->master->driver_priv;
3781 if (!master_priv->sarea_priv)
3782 return;
3783
Jesse Barnes79e53942008-11-07 14:24:08 -08003784 switch (pipe) {
3785 case 0:
3786 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3787 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3788 break;
3789 case 1:
3790 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3791 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3792 break;
3793 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003794 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003795 break;
3796 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003797}
3798
Daniel Vetter976f8a22012-07-08 22:34:21 +02003799/**
3800 * Sets the power management mode of the pipe and plane.
3801 */
3802void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01003803{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003804 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003805 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003806 struct intel_encoder *intel_encoder;
3807 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003808
Daniel Vetter976f8a22012-07-08 22:34:21 +02003809 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3810 enable |= intel_encoder->connectors_active;
3811
3812 if (enable)
3813 dev_priv->display.crtc_enable(crtc);
3814 else
3815 dev_priv->display.crtc_disable(crtc);
3816
3817 intel_crtc_update_sarea(crtc, enable);
3818}
3819
Daniel Vetter976f8a22012-07-08 22:34:21 +02003820static void intel_crtc_disable(struct drm_crtc *crtc)
3821{
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_connector *connector;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08003825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003826
3827 /* crtc should still be enabled when we disable it. */
3828 WARN_ON(!crtc->enabled);
3829
3830 dev_priv->display.crtc_disable(crtc);
Paulo Zanonic77bf562013-05-03 12:15:40 -03003831 intel_crtc->eld_vld = false;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003832 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003833 dev_priv->display.off(crtc);
3834
Chris Wilson931872f2012-01-16 23:01:13 +00003835 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3836 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003837
3838 if (crtc->fb) {
3839 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003840 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003841 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003842 crtc->fb = NULL;
3843 }
3844
3845 /* Update computed state. */
3846 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3847 if (!connector->encoder || !connector->encoder->crtc)
3848 continue;
3849
3850 if (connector->encoder->crtc != crtc)
3851 continue;
3852
3853 connector->dpms = DRM_MODE_DPMS_OFF;
3854 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003855 }
3856}
3857
Daniel Vettera261b242012-07-26 19:21:47 +02003858void intel_modeset_disable(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003859{
Daniel Vettera261b242012-07-26 19:21:47 +02003860 struct drm_crtc *crtc;
3861
3862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3863 if (crtc->enabled)
3864 intel_crtc_disable(crtc);
3865 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003866}
3867
Chris Wilsonea5b2132010-08-04 13:50:23 +01003868void intel_encoder_destroy(struct drm_encoder *encoder)
3869{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003870 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003871
Chris Wilsonea5b2132010-08-04 13:50:23 +01003872 drm_encoder_cleanup(encoder);
3873 kfree(intel_encoder);
3874}
3875
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003876/* Simple dpms helper for encodres with just one connector, no cloning and only
3877 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3878 * state of the entire output pipe. */
3879void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3880{
3881 if (mode == DRM_MODE_DPMS_ON) {
3882 encoder->connectors_active = true;
3883
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003884 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003885 } else {
3886 encoder->connectors_active = false;
3887
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003888 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003889 }
3890}
3891
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003892/* Cross check the actual hw state with our own modeset state tracking (and it's
3893 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02003894static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003895{
3896 if (connector->get_hw_state(connector)) {
3897 struct intel_encoder *encoder = connector->encoder;
3898 struct drm_crtc *crtc;
3899 bool encoder_enabled;
3900 enum pipe pipe;
3901
3902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3903 connector->base.base.id,
3904 drm_get_connector_name(&connector->base));
3905
3906 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3907 "wrong connector dpms state\n");
3908 WARN(connector->base.encoder != &encoder->base,
3909 "active connector not linked to encoder\n");
3910 WARN(!encoder->connectors_active,
3911 "encoder->connectors_active not set\n");
3912
3913 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3914 WARN(!encoder_enabled, "encoder not enabled\n");
3915 if (WARN_ON(!encoder->base.crtc))
3916 return;
3917
3918 crtc = encoder->base.crtc;
3919
3920 WARN(!crtc->enabled, "crtc not enabled\n");
3921 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3922 WARN(pipe != to_intel_crtc(crtc)->pipe,
3923 "encoder active on the wrong pipe\n");
3924 }
3925}
3926
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003927/* Even simpler default implementation, if there's really no special case to
3928 * consider. */
3929void intel_connector_dpms(struct drm_connector *connector, int mode)
3930{
3931 struct intel_encoder *encoder = intel_attached_encoder(connector);
3932
3933 /* All the simple cases only support two dpms states. */
3934 if (mode != DRM_MODE_DPMS_ON)
3935 mode = DRM_MODE_DPMS_OFF;
3936
3937 if (mode == connector->dpms)
3938 return;
3939
3940 connector->dpms = mode;
3941
3942 /* Only need to change hw state when actually enabled */
3943 if (encoder->base.crtc)
3944 intel_encoder_dpms(encoder, mode);
3945 else
Daniel Vetter8af6cf82012-07-10 09:50:11 +02003946 WARN_ON(encoder->connectors_active != false);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003947
Daniel Vetterb9805142012-08-31 17:37:33 +02003948 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003949}
3950
Daniel Vetterf0947c32012-07-02 13:10:34 +02003951/* Simple connector->get_hw_state implementation for encoders that support only
3952 * one connector and no cloning and hence the encoder state determines the state
3953 * of the connector. */
3954bool intel_connector_get_hw_state(struct intel_connector *connector)
3955{
Daniel Vetter24929352012-07-02 20:28:59 +02003956 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02003957 struct intel_encoder *encoder = connector->encoder;
3958
3959 return encoder->get_hw_state(encoder, &pipe);
3960}
3961
Daniel Vetter1857e1d2013-04-29 19:34:16 +02003962static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3963 struct intel_crtc_config *pipe_config)
3964{
3965 struct drm_i915_private *dev_priv = dev->dev_private;
3966 struct intel_crtc *pipe_B_crtc =
3967 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3968
3969 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 if (pipe_config->fdi_lanes > 4) {
3972 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976
3977 if (IS_HASWELL(dev)) {
3978 if (pipe_config->fdi_lanes > 2) {
3979 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3980 pipe_config->fdi_lanes);
3981 return false;
3982 } else {
3983 return true;
3984 }
3985 }
3986
3987 if (INTEL_INFO(dev)->num_pipes == 2)
3988 return true;
3989
3990 /* Ivybridge 3 pipe is really complicated */
3991 switch (pipe) {
3992 case PIPE_A:
3993 return true;
3994 case PIPE_B:
3995 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3996 pipe_config->fdi_lanes > 2) {
3997 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3998 pipe_name(pipe), pipe_config->fdi_lanes);
3999 return false;
4000 }
4001 return true;
4002 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01004003 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004004 pipe_B_crtc->config.fdi_lanes <= 2) {
4005 if (pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 return false;
4009 }
4010 } else {
4011 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4012 return false;
4013 }
4014 return true;
4015 default:
4016 BUG();
4017 }
4018}
4019
Daniel Vettere29c22c2013-02-21 00:00:16 +01004020#define RETRY 1
4021static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4022 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02004023{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004024 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004025 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02004026 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01004027 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004028
Daniel Vettere29c22c2013-02-21 00:00:16 +01004029retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02004030 /* FDI is a binary signal running at ~2.7GHz, encoding
4031 * each output octet as 10 bits. The actual frequency
4032 * is stored as a divider into a 100MHz clock, and the
4033 * mode pixel clock is stored in units of 1KHz.
4034 * Hence the bw of each lane in terms of the mode signal
4035 * is:
4036 */
4037 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4038
Daniel Vetterff9a6752013-06-01 17:16:21 +02004039 fdi_dotclock = adjusted_mode->clock;
Daniel Vetteref1b4602013-06-01 17:17:04 +02004040 fdi_dotclock /= pipe_config->pixel_multiplier;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004041
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004042 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004043 pipe_config->pipe_bpp);
4044
4045 pipe_config->fdi_lanes = lane;
4046
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004047 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004048 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004049
Daniel Vettere29c22c2013-02-21 00:00:16 +01004050 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4051 intel_crtc->pipe, pipe_config);
4052 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4053 pipe_config->pipe_bpp -= 2*3;
4054 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4055 pipe_config->pipe_bpp);
4056 needs_recompute = true;
4057 pipe_config->bw_constrained = true;
4058
4059 goto retry;
4060 }
4061
4062 if (needs_recompute)
4063 return RETRY;
4064
4065 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004066}
4067
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004068static void hsw_compute_ips_config(struct intel_crtc *crtc,
4069 struct intel_crtc_config *pipe_config)
4070{
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03004071 pipe_config->ips_enabled = i915_enable_ips &&
4072 hsw_crtc_supports_ips(crtc) &&
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004073 pipe_config->pipe_bpp == 24;
4074}
4075
Daniel Vettera43f6e02013-06-07 23:10:32 +02004076static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01004077 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08004078{
Daniel Vettera43f6e02013-06-07 23:10:32 +02004079 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004080 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01004081
Eric Anholtbad720f2009-10-22 16:11:14 -07004082 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004083 /* FDI link clock is fixed at 2.7G */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004084 if (pipe_config->requested_mode.clock * 3
4085 > IRONLAKE_FDI_FREQ * 4)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004086 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004087 }
Chris Wilson89749352010-09-12 18:25:19 +01004088
Daniel Vetterf9bef082012-04-15 19:53:19 +02004089 /* All interlaced capable intel hw wants timings in frames. Note though
4090 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4091 * timings, so we need to be careful not to clobber these.*/
Daniel Vetter7ae89232013-03-27 00:44:52 +01004092 if (!pipe_config->timings_set)
Daniel Vetterf9bef082012-04-15 19:53:19 +02004093 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01004094
Damien Lespiau8693a822013-05-03 18:48:11 +01004095 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4096 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03004097 */
4098 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4099 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004100 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03004101
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004102 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004103 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004104 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004105 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4106 * for lvds. */
4107 pipe_config->pipe_bpp = 8*3;
4108 }
4109
Damien Lespiauf5adf942013-06-24 18:29:34 +01004110 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02004111 hsw_compute_ips_config(crtc, pipe_config);
4112
4113 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4114 * clock survives for now. */
4115 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4116 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004117
Daniel Vetter877d48d2013-04-19 11:24:43 +02004118 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02004119 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02004120
Daniel Vettere29c22c2013-02-21 00:00:16 +01004121 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004122}
4123
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07004124static int valleyview_get_display_clock_speed(struct drm_device *dev)
4125{
4126 return 400000; /* FIXME */
4127}
4128
Jesse Barnese70236a2009-09-21 10:42:27 -07004129static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08004130{
Jesse Barnese70236a2009-09-21 10:42:27 -07004131 return 400000;
4132}
Jesse Barnes79e53942008-11-07 14:24:08 -08004133
Jesse Barnese70236a2009-09-21 10:42:27 -07004134static int i915_get_display_clock_speed(struct drm_device *dev)
4135{
4136 return 333000;
4137}
Jesse Barnes79e53942008-11-07 14:24:08 -08004138
Jesse Barnese70236a2009-09-21 10:42:27 -07004139static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4140{
4141 return 200000;
4142}
Jesse Barnes79e53942008-11-07 14:24:08 -08004143
Jesse Barnese70236a2009-09-21 10:42:27 -07004144static int i915gm_get_display_clock_speed(struct drm_device *dev)
4145{
4146 u16 gcfgc = 0;
4147
4148 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4149
4150 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08004151 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07004152 else {
4153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154 case GC_DISPLAY_CLOCK_333_MHZ:
4155 return 333000;
4156 default:
4157 case GC_DISPLAY_CLOCK_190_200_MHZ:
4158 return 190000;
4159 }
4160 }
4161}
Jesse Barnes79e53942008-11-07 14:24:08 -08004162
Jesse Barnese70236a2009-09-21 10:42:27 -07004163static int i865_get_display_clock_speed(struct drm_device *dev)
4164{
4165 return 266000;
4166}
4167
4168static int i855_get_display_clock_speed(struct drm_device *dev)
4169{
4170 u16 hpllcc = 0;
4171 /* Assume that the hardware is in the high speed state. This
4172 * should be the default.
4173 */
4174 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4175 case GC_CLOCK_133_200:
4176 case GC_CLOCK_100_200:
4177 return 200000;
4178 case GC_CLOCK_166_250:
4179 return 250000;
4180 case GC_CLOCK_100_133:
4181 return 133000;
4182 }
4183
4184 /* Shouldn't happen */
4185 return 0;
4186}
4187
4188static int i830_get_display_clock_speed(struct drm_device *dev)
4189{
4190 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004191}
4192
Zhenyu Wang2c072452009-06-05 15:38:42 +08004193static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004194intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004195{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004196 while (*num > DATA_LINK_M_N_MASK ||
4197 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004198 *num >>= 1;
4199 *den >>= 1;
4200 }
4201}
4202
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004203static void compute_m_n(unsigned int m, unsigned int n,
4204 uint32_t *ret_m, uint32_t *ret_n)
4205{
4206 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4207 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4208 intel_reduce_m_n_ratio(ret_m, ret_n);
4209}
4210
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004211void
4212intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4213 int pixel_clock, int link_clock,
4214 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004215{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004216 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004217
4218 compute_m_n(bits_per_pixel * pixel_clock,
4219 link_clock * nlanes * 8,
4220 &m_n->gmch_m, &m_n->gmch_n);
4221
4222 compute_m_n(pixel_clock, link_clock,
4223 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004224}
4225
Chris Wilsona7615032011-01-12 17:04:08 +00004226static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4227{
Keith Packard72bbe582011-09-26 16:09:45 -07004228 if (i915_panel_use_ssc >= 0)
4229 return i915_panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004230 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004231 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004232}
4233
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004234static int vlv_get_refclk(struct drm_crtc *crtc)
4235{
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 int refclk = 27000; /* for DP & HDMI */
4239
4240 return 100000; /* only one validated so far */
4241
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4243 refclk = 96000;
4244 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4245 if (intel_panel_use_ssc(dev_priv))
4246 refclk = 100000;
4247 else
4248 refclk = 96000;
4249 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4250 refclk = 100000;
4251 }
4252
4253 return refclk;
4254}
4255
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004256static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4257{
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 int refclk;
4261
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004262 if (IS_VALLEYVIEW(dev)) {
4263 refclk = vlv_get_refclk(crtc);
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004265 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004266 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004267 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4268 refclk / 1000);
4269 } else if (!IS_GEN2(dev)) {
4270 refclk = 96000;
4271 } else {
4272 refclk = 48000;
4273 }
4274
4275 return refclk;
4276}
4277
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004278static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004279{
Daniel Vetter7df00d72013-05-21 21:54:55 +02004280 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004281}
Daniel Vetterf47709a2013-03-28 10:42:02 +01004282
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004283static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4284{
4285 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004286}
4287
Daniel Vetterf47709a2013-03-28 10:42:02 +01004288static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08004289 intel_clock_t *reduced_clock)
4290{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004291 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004292 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004293 int pipe = crtc->pipe;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004294 u32 fp, fp2 = 0;
4295
4296 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004297 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004298 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004299 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004300 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004301 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004302 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004303 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004304 }
4305
4306 I915_WRITE(FP0(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004307 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004308
Daniel Vetterf47709a2013-03-28 10:42:02 +01004309 crtc->lowfreq_avail = false;
4310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jesse Barnesa7516a02011-12-15 12:30:37 -08004311 reduced_clock && i915_powersave) {
4312 I915_WRITE(FP1(pipe), fp2);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004313 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004314 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004315 } else {
4316 I915_WRITE(FP1(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004317 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004318 }
4319}
4320
Jesse Barnes89b667f2013-04-18 14:51:36 -07004321static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4322{
4323 u32 reg_val;
4324
4325 /*
4326 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4327 * and set it to a reasonable value instead.
4328 */
Jani Nikulaae992582013-05-22 15:36:19 +03004329 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004330 reg_val &= 0xffffff00;
4331 reg_val |= 0x00000030;
Jani Nikulaae992582013-05-22 15:36:19 +03004332 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004333
Jani Nikulaae992582013-05-22 15:36:19 +03004334 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004335 reg_val &= 0x8cffffff;
4336 reg_val = 0x8c000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004337 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004338
Jani Nikulaae992582013-05-22 15:36:19 +03004339 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004340 reg_val &= 0xffffff00;
Jani Nikulaae992582013-05-22 15:36:19 +03004341 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004342
Jani Nikulaae992582013-05-22 15:36:19 +03004343 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004344 reg_val &= 0x00ffffff;
4345 reg_val |= 0xb0000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004346 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004347}
4348
Daniel Vetterb5518422013-05-03 11:49:48 +02004349static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4350 struct intel_link_m_n *m_n)
4351{
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 int pipe = crtc->pipe;
4355
Daniel Vettere3b95f12013-05-03 11:49:49 +02004356 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4357 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4358 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4359 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004360}
4361
4362static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4363 struct intel_link_m_n *m_n)
4364{
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
4368 enum transcoder transcoder = crtc->config.cpu_transcoder;
4369
4370 if (INTEL_INFO(dev)->gen >= 5) {
4371 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4372 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4373 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4374 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4375 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02004376 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4378 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4379 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004380 }
4381}
4382
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004383static void intel_dp_set_m_n(struct intel_crtc *crtc)
4384{
4385 if (crtc->config.has_pch_encoder)
4386 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4387 else
4388 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389}
4390
Daniel Vetterf47709a2013-03-28 10:42:02 +01004391static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004392{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004393 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004394 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004395 struct intel_encoder *encoder;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004396 int pipe = crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004397 u32 dpll, mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004398 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004399 bool is_hdmi;
Daniel Vetter198a037f2013-04-19 11:14:37 +02004400 u32 coreclk, reg_val, dpll_md;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004401
Daniel Vetter09153002012-12-12 14:06:44 +01004402 mutex_lock(&dev_priv->dpio_lock);
4403
Jesse Barnes89b667f2013-04-18 14:51:36 -07004404 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004405
Daniel Vetterf47709a2013-03-28 10:42:02 +01004406 bestn = crtc->config.dpll.n;
4407 bestm1 = crtc->config.dpll.m1;
4408 bestm2 = crtc->config.dpll.m2;
4409 bestp1 = crtc->config.dpll.p1;
4410 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004411
Jesse Barnes89b667f2013-04-18 14:51:36 -07004412 /* See eDP HDMI DPIO driver vbios notes doc */
4413
4414 /* PLL B needs special handling */
4415 if (pipe)
4416 vlv_pllb_recal_opamp(dev_priv);
4417
4418 /* Set up Tx target for periodic Rcomp update */
Jani Nikulaae992582013-05-22 15:36:19 +03004419 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004420
4421 /* Disable target IRef on PLL */
Jani Nikulaae992582013-05-22 15:36:19 +03004422 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004423 reg_val &= 0x00ffffff;
Jani Nikulaae992582013-05-22 15:36:19 +03004424 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004425
4426 /* Disable fast lock */
Jani Nikulaae992582013-05-22 15:36:19 +03004427 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004428
4429 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004430 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4431 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4432 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004433 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07004434
4435 /*
4436 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4437 * but we don't support that).
4438 * Note: don't use the DAC post divider as it seems unstable.
4439 */
4440 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Jani Nikulaae992582013-05-22 15:36:19 +03004441 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004442
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004443 mdiv |= DPIO_ENABLE_CALIBRATION;
Jani Nikulaae992582013-05-22 15:36:19 +03004444 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004445
Jesse Barnes89b667f2013-04-18 14:51:36 -07004446 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02004447 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03004448 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07004449 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Ville Syrjälä4abb2c32013-06-14 14:02:53 +03004450 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004451 0x005f0021);
4452 else
Ville Syrjälä4abb2c32013-06-14 14:02:53 +03004453 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004454 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004455
Jesse Barnes89b667f2013-04-18 14:51:36 -07004456 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458 /* Use SSC source */
4459 if (!pipe)
Jani Nikulaae992582013-05-22 15:36:19 +03004460 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004461 0x0df40000);
4462 else
Jani Nikulaae992582013-05-22 15:36:19 +03004463 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004464 0x0df70000);
4465 } else { /* HDMI or VGA */
4466 /* Use bend source */
4467 if (!pipe)
Jani Nikulaae992582013-05-22 15:36:19 +03004468 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004469 0x0df70000);
4470 else
Jani Nikulaae992582013-05-22 15:36:19 +03004471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004472 0x0df40000);
4473 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004474
Jani Nikulaae992582013-05-22 15:36:19 +03004475 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004476 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479 coreclk |= 0x01000000;
Jani Nikulaae992582013-05-22 15:36:19 +03004480 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004481
Jani Nikulaae992582013-05-22 15:36:19 +03004482 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004483
4484 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485 if (encoder->pre_pll_enable)
4486 encoder->pre_pll_enable(encoder);
4487
4488 /* Enable DPIO clock input */
4489 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491 if (pipe)
4492 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004493
4494 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004495 crtc->config.dpll_hw_state.dpll = dpll;
4496
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004497 I915_WRITE(DPLL(pipe), dpll);
4498 POSTING_READ(DPLL(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004499 udelay(150);
4500
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004501 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4502 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4503
Daniel Vetteref1b4602013-06-01 17:17:04 +02004504 dpll_md = (crtc->config.pixel_multiplier - 1)
4505 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004506 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4507
Daniel Vetter198a037f2013-04-19 11:14:37 +02004508 I915_WRITE(DPLL_MD(pipe), dpll_md);
4509 POSTING_READ(DPLL_MD(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004510
Daniel Vetterf47709a2013-03-28 10:42:02 +01004511 if (crtc->config.has_dp_encoder)
4512 intel_dp_set_m_n(crtc);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304513
Daniel Vetter09153002012-12-12 14:06:44 +01004514 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004515}
4516
Daniel Vetterf47709a2013-03-28 10:42:02 +01004517static void i9xx_update_pll(struct intel_crtc *crtc,
4518 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004519 int num_connectors)
4520{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004521 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004522 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004523 u32 dpll;
4524 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004525 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004526
Daniel Vetterf47709a2013-03-28 10:42:02 +01004527 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304528
Daniel Vetterf47709a2013-03-28 10:42:02 +01004529 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4530 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004531
4532 dpll = DPLL_VGA_MODE_DIS;
4533
Daniel Vetterf47709a2013-03-28 10:42:02 +01004534 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004535 dpll |= DPLLB_MODE_LVDS;
4536 else
4537 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004538
Daniel Vetteref1b4602013-06-01 17:17:04 +02004539 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02004540 dpll |= (crtc->config.pixel_multiplier - 1)
4541 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004542 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02004543
4544 if (is_sdvo)
4545 dpll |= DPLL_DVO_HIGH_SPEED;
4546
Daniel Vetterf47709a2013-03-28 10:42:02 +01004547 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004548 dpll |= DPLL_DVO_HIGH_SPEED;
4549
4550 /* compute bitmask from p1 value */
4551 if (IS_PINEVIEW(dev))
4552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4553 else {
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4555 if (IS_G4X(dev) && reduced_clock)
4556 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4557 }
4558 switch (clock->p2) {
4559 case 5:
4560 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4561 break;
4562 case 7:
4563 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4564 break;
4565 case 10:
4566 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4567 break;
4568 case 14:
4569 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4570 break;
4571 }
4572 if (INTEL_INFO(dev)->gen >= 4)
4573 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4574
Daniel Vetter09ede542013-04-30 14:01:45 +02004575 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004576 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004577 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004578 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4580 else
4581 dpll |= PLL_REF_INPUT_DREFCLK;
4582
4583 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004584 crtc->config.dpll_hw_state.dpll = dpll;
4585
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004586 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02004587 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004589 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004590 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004591
4592 if (crtc->config.has_dp_encoder)
4593 intel_dp_set_m_n(crtc);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004594}
4595
Daniel Vetterf47709a2013-03-28 10:42:02 +01004596static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01004597 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004598 int num_connectors)
4599{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004600 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004601 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004602 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004603 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004604
Daniel Vetterf47709a2013-03-28 10:42:02 +01004605 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304606
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004607 dpll = DPLL_VGA_MODE_DIS;
4608
Daniel Vetterf47709a2013-03-28 10:42:02 +01004609 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4611 } else {
4612 if (clock->p1 == 2)
4613 dpll |= PLL_P1_DIVIDE_BY_TWO;
4614 else
4615 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4616 if (clock->p2 == 4)
4617 dpll |= PLL_P2_DIVIDE_BY_4;
4618 }
4619
Daniel Vetterf47709a2013-03-28 10:42:02 +01004620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004621 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4623 else
4624 dpll |= PLL_REF_INPUT_DREFCLK;
4625
4626 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004627 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004628}
4629
Daniel Vetter8a654f32013-06-01 17:16:22 +02004630static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004631{
4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02004635 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02004636 struct drm_display_mode *adjusted_mode =
4637 &intel_crtc->config.adjusted_mode;
4638 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004639 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641 /* We need to be careful not to changed the adjusted mode, for otherwise
4642 * the hw state checker will get angry at the mismatch. */
4643 crtc_vtotal = adjusted_mode->crtc_vtotal;
4644 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004645
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004648 crtc_vtotal -= 1;
4649 crtc_vblank_end -= 1;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4652 } else {
4653 vsyncshift = 0;
4654 }
4655
4656 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004658
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004659 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004662 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004665 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004669 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004670 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004671 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004672 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004673 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02004674 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004675 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
Paulo Zanonib5e508d2012-10-24 11:34:43 -02004679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682 * bits. */
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4689 */
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692}
4693
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004694static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695 struct intel_crtc_config *pipe_config)
4696{
4697 struct drm_device *dev = crtc->base.dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700 uint32_t tmp;
4701
4702 tmp = I915_READ(HTOTAL(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HBLANK(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708 tmp = I915_READ(HSYNC(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712 tmp = I915_READ(VTOTAL(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VBLANK(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(VSYNC(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726 }
4727
4728 tmp = I915_READ(PIPESRC(crtc->pipe));
4729 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731}
4732
Jesse Barnesbabea612013-06-26 18:57:38 +03004733static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4734 struct intel_crtc_config *pipe_config)
4735{
4736 struct drm_crtc *crtc = &intel_crtc->base;
4737
4738 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4739 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4740 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4741 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4742
4743 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4744 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4745 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4746 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4747
4748 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4749
4750 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4751 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4752}
4753
Daniel Vetter84b046f2013-02-19 18:48:54 +01004754static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4755{
4756 struct drm_device *dev = intel_crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 uint32_t pipeconf;
4759
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02004760 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004761
4762 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4763 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4764 * core speed.
4765 *
4766 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4767 * pipe == 0 check?
4768 */
4769 if (intel_crtc->config.requested_mode.clock >
4770 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4771 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004772 }
4773
Daniel Vetterff9ce462013-04-24 14:57:17 +02004774 /* only g4x and later have fancy bpc/dither controls */
4775 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02004776 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4777 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4778 pipeconf |= PIPECONF_DITHER_EN |
4779 PIPECONF_DITHER_TYPE_SP;
4780
4781 switch (intel_crtc->config.pipe_bpp) {
4782 case 18:
4783 pipeconf |= PIPECONF_6BPC;
4784 break;
4785 case 24:
4786 pipeconf |= PIPECONF_8BPC;
4787 break;
4788 case 30:
4789 pipeconf |= PIPECONF_10BPC;
4790 break;
4791 default:
4792 /* Case prevented by intel_choose_pipe_bpp_dither. */
4793 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01004794 }
4795 }
4796
4797 if (HAS_PIPE_CXSR(dev)) {
4798 if (intel_crtc->lowfreq_avail) {
4799 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4800 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4801 } else {
4802 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01004803 }
4804 }
4805
Daniel Vetter84b046f2013-02-19 18:48:54 +01004806 if (!IS_GEN2(dev) &&
4807 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4809 else
4810 pipeconf |= PIPECONF_PROGRESSIVE;
4811
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02004812 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4813 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03004814
Daniel Vetter84b046f2013-02-19 18:48:54 +01004815 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4816 POSTING_READ(PIPECONF(intel_crtc->pipe));
4817}
4818
Eric Anholtf564048e2011-03-30 13:01:02 -07004819static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07004820 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004821 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004822{
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004826 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08004827 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004828 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004829 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004830 intel_clock_t clock, reduced_clock;
Daniel Vetter84b046f2013-02-19 18:48:54 +01004831 u32 dspcntr;
Daniel Vettera16af7212013-04-30 14:01:44 +02004832 bool ok, has_reduced_clock = false;
4833 bool is_lvds = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004834 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004835 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004836 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004837
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004838 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004839 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004840 case INTEL_OUTPUT_LVDS:
4841 is_lvds = true;
4842 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004843 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004844
Eric Anholtc751ce42010-03-25 11:48:48 -07004845 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004846 }
4847
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004848 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004849
Ma Lingd4906092009-03-18 20:13:27 +08004850 /*
4851 * Returns a set of divisors for the desired target clock with the given
4852 * refclk, or FALSE. The returned values represent the clock equation:
4853 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4854 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004855 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02004856 ok = dev_priv->display.find_dpll(limit, crtc,
4857 intel_crtc->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02004858 refclk, NULL, &clock);
4859 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004861 return -EINVAL;
4862 }
4863
4864 /* Ensure that the cursor is valid for the new mode before changing... */
4865 intel_crtc_update_cursor(crtc, true);
4866
4867 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004868 /*
4869 * Ensure we match the reduced clock's P to the target clock.
4870 * If the clocks don't match, we can't switch the display clock
4871 * by using the FP0/FP1. In such case we will disable the LVDS
4872 * downclock feature.
4873 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02004874 has_reduced_clock =
4875 dev_priv->display.find_dpll(limit, crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07004876 dev_priv->lvds_downclock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02004877 refclk, &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004878 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004879 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01004880 /* Compat-code for transition, will disappear. */
4881 if (!intel_crtc->config.clock_set) {
4882 intel_crtc->config.dpll.n = clock.n;
4883 intel_crtc->config.dpll.m1 = clock.m1;
4884 intel_crtc->config.dpll.m2 = clock.m2;
4885 intel_crtc->config.dpll.p1 = clock.p1;
4886 intel_crtc->config.dpll.p2 = clock.p2;
4887 }
Eric Anholtf564048e2011-03-30 13:01:02 -07004888
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004889 if (IS_GEN2(dev))
Daniel Vetter8a654f32013-06-01 17:16:22 +02004890 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304891 has_reduced_clock ? &reduced_clock : NULL,
4892 num_connectors);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004893 else if (IS_VALLEYVIEW(dev))
Daniel Vetterf47709a2013-03-28 10:42:02 +01004894 vlv_update_pll(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07004895 else
Daniel Vetterf47709a2013-03-28 10:42:02 +01004896 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004897 has_reduced_clock ? &reduced_clock : NULL,
Jesse Barnes89b667f2013-04-18 14:51:36 -07004898 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004899
Eric Anholtf564048e2011-03-30 13:01:02 -07004900 /* Set up the display plane register */
4901 dspcntr = DISPPLANE_GAMMA_ENABLE;
4902
Jesse Barnesda6ecc52013-03-08 10:46:00 -08004903 if (!IS_VALLEYVIEW(dev)) {
4904 if (pipe == 0)
4905 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4906 else
4907 dspcntr |= DISPPLANE_SEL_PIPE_B;
4908 }
Eric Anholtf564048e2011-03-30 13:01:02 -07004909
Daniel Vetter8a654f32013-06-01 17:16:22 +02004910 intel_set_pipe_timings(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07004911
4912 /* pipesrc and dspsize control the size that is scaled from,
4913 * which should always be the user's requested size.
4914 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004915 I915_WRITE(DSPSIZE(plane),
4916 ((mode->vdisplay - 1) << 16) |
4917 (mode->hdisplay - 1));
4918 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004919
Daniel Vetter84b046f2013-02-19 18:48:54 +01004920 i9xx_set_pipeconf(intel_crtc);
4921
Eric Anholtf564048e2011-03-30 13:01:02 -07004922 I915_WRITE(DSPCNTR(plane), dspcntr);
4923 POSTING_READ(DSPCNTR(plane));
4924
Daniel Vetter94352cf2012-07-05 22:51:56 +02004925 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07004926
4927 intel_update_watermarks(dev);
4928
Eric Anholtf564048e2011-03-30 13:01:02 -07004929 return ret;
4930}
4931
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02004932static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4933 struct intel_crtc_config *pipe_config)
4934{
4935 struct drm_device *dev = crtc->base.dev;
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937 uint32_t tmp;
4938
4939 tmp = I915_READ(PFIT_CONTROL);
4940
4941 if (INTEL_INFO(dev)->gen < 4) {
4942 if (crtc->pipe != PIPE_B)
4943 return;
4944
4945 /* gen2/3 store dither state in pfit control, needs to match */
4946 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4947 } else {
4948 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4949 return;
4950 }
4951
4952 if (!(tmp & PFIT_ENABLE))
4953 return;
4954
4955 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4956 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4957 if (INTEL_INFO(dev)->gen < 5)
4958 pipe_config->gmch_pfit.lvds_border_bits =
4959 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4960}
4961
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01004962static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963 struct intel_crtc_config *pipe_config)
4964{
4965 struct drm_device *dev = crtc->base.dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 uint32_t tmp;
4968
Daniel Vettereccb1402013-05-22 00:50:22 +02004969 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02004970 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02004971
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01004972 tmp = I915_READ(PIPECONF(crtc->pipe));
4973 if (!(tmp & PIPECONF_ENABLE))
4974 return false;
4975
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02004976 intel_get_pipe_timings(crtc, pipe_config);
4977
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02004978 i9xx_get_pfit_config(crtc, pipe_config);
4979
Daniel Vetter6c49f242013-06-06 12:45:25 +02004980 if (INTEL_INFO(dev)->gen >= 4) {
4981 tmp = I915_READ(DPLL_MD(crtc->pipe));
4982 pipe_config->pixel_multiplier =
4983 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4984 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004985 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02004986 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4987 tmp = I915_READ(DPLL(crtc->pipe));
4988 pipe_config->pixel_multiplier =
4989 ((tmp & SDVO_MULTIPLIER_MASK)
4990 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4991 } else {
4992 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4993 * port and will be fixed up in the encoder->get_config
4994 * function. */
4995 pipe_config->pixel_multiplier = 1;
4996 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004997 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4998 if (!IS_VALLEYVIEW(dev)) {
4999 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5000 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03005001 } else {
5002 /* Mask out read-only status bits. */
5003 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5004 DPLL_PORTC_READY_MASK |
5005 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005006 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02005007
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005008 return true;
5009}
5010
Paulo Zanonidde86e22012-12-01 12:04:25 -02005011static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07005012{
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005015 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005016 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005017 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005018 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005019 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07005020 bool has_ck505 = false;
5021 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005022
5023 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07005024 list_for_each_entry(encoder, &mode_config->encoder_list,
5025 base.head) {
5026 switch (encoder->type) {
5027 case INTEL_OUTPUT_LVDS:
5028 has_panel = true;
5029 has_lvds = true;
5030 break;
5031 case INTEL_OUTPUT_EDP:
5032 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03005033 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07005034 has_cpu_edp = true;
5035 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005036 }
5037 }
5038
Keith Packard99eb6a02011-09-26 14:29:12 -07005039 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005040 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07005041 can_ssc = has_ck505;
5042 } else {
5043 has_ck505 = false;
5044 can_ssc = true;
5045 }
5046
Imre Deak2de69052013-05-08 13:14:04 +03005047 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5048 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005049
5050 /* Ironlake: try to setup display ref clock before DPLL
5051 * enabling. This is only under driver's control after
5052 * PCH B stepping, previous chipset stepping should be
5053 * ignoring this setting.
5054 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005055 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005056
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005057 /* As we must carefully and slowly disable/enable each source in turn,
5058 * compute the final state we want first and check if we need to
5059 * make any changes at all.
5060 */
5061 final = val;
5062 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07005063 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005064 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07005065 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005066 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5067
5068 final &= ~DREF_SSC_SOURCE_MASK;
5069 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5070 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005071
Keith Packard199e5d72011-09-22 12:01:57 -07005072 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005073 final |= DREF_SSC_SOURCE_ENABLE;
5074
5075 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5076 final |= DREF_SSC1_ENABLE;
5077
5078 if (has_cpu_edp) {
5079 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5080 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5081 else
5082 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5083 } else
5084 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5085 } else {
5086 final |= DREF_SSC_SOURCE_DISABLE;
5087 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5088 }
5089
5090 if (final == val)
5091 return;
5092
5093 /* Always enable nonspread source */
5094 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5095
5096 if (has_ck505)
5097 val |= DREF_NONSPREAD_CK505_ENABLE;
5098 else
5099 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5100
5101 if (has_panel) {
5102 val &= ~DREF_SSC_SOURCE_MASK;
5103 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005104
Keith Packard199e5d72011-09-22 12:01:57 -07005105 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005106 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005107 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005108 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02005109 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005110 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005111
5112 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005113 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005114 POSTING_READ(PCH_DREF_CONTROL);
5115 udelay(200);
5116
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005117 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005118
5119 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005120 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005121 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005122 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005123 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005124 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005125 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005126 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005127 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005128 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005129
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005130 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005131 POSTING_READ(PCH_DREF_CONTROL);
5132 udelay(200);
5133 } else {
5134 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5135
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005136 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07005137
5138 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005139 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005140
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005141 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
5144
5145 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005146 val &= ~DREF_SSC_SOURCE_MASK;
5147 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005148
5149 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005150 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005151
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005152 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005153 POSTING_READ(PCH_DREF_CONTROL);
5154 udelay(200);
5155 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005156
5157 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005158}
5159
Paulo Zanonidde86e22012-12-01 12:04:25 -02005160/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5161static void lpt_init_pch_refclk(struct drm_device *dev)
5162{
5163 struct drm_i915_private *dev_priv = dev->dev_private;
5164 struct drm_mode_config *mode_config = &dev->mode_config;
5165 struct intel_encoder *encoder;
5166 bool has_vga = false;
5167 bool is_sdv = false;
5168 u32 tmp;
5169
5170 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5171 switch (encoder->type) {
5172 case INTEL_OUTPUT_ANALOG:
5173 has_vga = true;
5174 break;
5175 }
5176 }
5177
5178 if (!has_vga)
5179 return;
5180
Daniel Vetterc00db242013-01-22 15:33:27 +01005181 mutex_lock(&dev_priv->dpio_lock);
5182
Paulo Zanonidde86e22012-12-01 12:04:25 -02005183 /* XXX: Rip out SDV support once Haswell ships for real. */
5184 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5185 is_sdv = true;
5186
5187 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5188 tmp &= ~SBI_SSCCTL_DISABLE;
5189 tmp |= SBI_SSCCTL_PATHALT;
5190 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5191
5192 udelay(24);
5193
5194 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5195 tmp &= ~SBI_SSCCTL_PATHALT;
5196 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5197
5198 if (!is_sdv) {
5199 tmp = I915_READ(SOUTH_CHICKEN2);
5200 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5201 I915_WRITE(SOUTH_CHICKEN2, tmp);
5202
5203 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5204 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5205 DRM_ERROR("FDI mPHY reset assert timeout\n");
5206
5207 tmp = I915_READ(SOUTH_CHICKEN2);
5208 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5209 I915_WRITE(SOUTH_CHICKEN2, tmp);
5210
5211 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5212 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5213 100))
5214 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5215 }
5216
5217 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218 tmp &= ~(0xFF << 24);
5219 tmp |= (0x12 << 24);
5220 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5221
Paulo Zanonidde86e22012-12-01 12:04:25 -02005222 if (is_sdv) {
5223 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5224 tmp |= 0x7FFF;
5225 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5226 }
5227
5228 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5229 tmp |= (1 << 11);
5230 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5233 tmp |= (1 << 11);
5234 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5235
5236 if (is_sdv) {
5237 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5238 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5239 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5240
5241 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5242 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5243 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5244
5245 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5246 tmp |= (0x3F << 8);
5247 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5250 tmp |= (0x3F << 8);
5251 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5252 }
5253
5254 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5255 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5259 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5260 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5261
5262 if (!is_sdv) {
5263 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5264 tmp &= ~(7 << 13);
5265 tmp |= (5 << 13);
5266 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5269 tmp &= ~(7 << 13);
5270 tmp |= (5 << 13);
5271 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5272 }
5273
5274 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5275 tmp &= ~0xFF;
5276 tmp |= 0x1C;
5277 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5280 tmp &= ~0xFF;
5281 tmp |= 0x1C;
5282 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5285 tmp &= ~(0xFF << 16);
5286 tmp |= (0x1C << 16);
5287 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5290 tmp &= ~(0xFF << 16);
5291 tmp |= (0x1C << 16);
5292 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5293
5294 if (!is_sdv) {
5295 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5296 tmp |= (1 << 27);
5297 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5298
5299 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5300 tmp |= (1 << 27);
5301 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5302
5303 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5304 tmp &= ~(0xF << 28);
5305 tmp |= (4 << 28);
5306 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5307
5308 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5309 tmp &= ~(0xF << 28);
5310 tmp |= (4 << 28);
5311 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5312 }
5313
5314 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5315 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5316 tmp |= SBI_DBUFF0_ENABLE;
5317 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01005318
5319 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005320}
5321
5322/*
5323 * Initialize reference clocks when the driver loads
5324 */
5325void intel_init_pch_refclk(struct drm_device *dev)
5326{
5327 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5328 ironlake_init_pch_refclk(dev);
5329 else if (HAS_PCH_LPT(dev))
5330 lpt_init_pch_refclk(dev);
5331}
5332
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005333static int ironlake_get_refclk(struct drm_crtc *crtc)
5334{
5335 struct drm_device *dev = crtc->dev;
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005338 int num_connectors = 0;
5339 bool is_lvds = false;
5340
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005341 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005342 switch (encoder->type) {
5343 case INTEL_OUTPUT_LVDS:
5344 is_lvds = true;
5345 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005346 }
5347 num_connectors++;
5348 }
5349
5350 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5351 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005352 dev_priv->vbt.lvds_ssc_freq);
5353 return dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005354 }
5355
5356 return 120000;
5357}
5358
Daniel Vetter6ff93602013-04-19 11:24:36 +02005359static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03005360{
5361 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363 int pipe = intel_crtc->pipe;
5364 uint32_t val;
5365
Daniel Vetter78114072013-06-13 00:54:57 +02005366 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03005367
Daniel Vetter965e0c42013-03-27 00:44:57 +01005368 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03005369 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005370 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005371 break;
5372 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005373 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005374 break;
5375 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005376 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005377 break;
5378 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005379 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005380 break;
5381 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005382 /* Case prevented by intel_choose_pipe_bpp_dither. */
5383 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005384 }
5385
Daniel Vetterd8b32242013-04-25 17:54:44 +02005386 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03005387 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5388
Daniel Vetter6ff93602013-04-19 11:24:36 +02005389 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03005390 val |= PIPECONF_INTERLACED_ILK;
5391 else
5392 val |= PIPECONF_PROGRESSIVE;
5393
Daniel Vetter50f3b012013-03-27 00:44:56 +01005394 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005395 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005396
Paulo Zanonic8203562012-09-12 10:06:29 -03005397 I915_WRITE(PIPECONF(pipe), val);
5398 POSTING_READ(PIPECONF(pipe));
5399}
5400
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005401/*
5402 * Set up the pipe CSC unit.
5403 *
5404 * Currently only full range RGB to limited range RGB conversion
5405 * is supported, but eventually this should handle various
5406 * RGB<->YCbCr scenarios as well.
5407 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01005408static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005409{
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 int pipe = intel_crtc->pipe;
5414 uint16_t coeff = 0x7800; /* 1.0 */
5415
5416 /*
5417 * TODO: Check what kind of values actually come out of the pipe
5418 * with these coeff/postoff values and adjust to get the best
5419 * accuracy. Perhaps we even need to take the bpc value into
5420 * consideration.
5421 */
5422
Daniel Vetter50f3b012013-03-27 00:44:56 +01005423 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005424 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5425
5426 /*
5427 * GY/GU and RY/RU should be the other way around according
5428 * to BSpec, but reality doesn't agree. Just set them up in
5429 * a way that results in the correct picture.
5430 */
5431 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5432 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5433
5434 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5435 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5436
5437 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5438 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5439
5440 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5441 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5442 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5443
5444 if (INTEL_INFO(dev)->gen > 6) {
5445 uint16_t postoff = 0;
5446
Daniel Vetter50f3b012013-03-27 00:44:56 +01005447 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005448 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5449
5450 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5451 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5452 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5453
5454 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5455 } else {
5456 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5457
Daniel Vetter50f3b012013-03-27 00:44:56 +01005458 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005459 mode |= CSC_BLACK_SCREEN_OFFSET;
5460
5461 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5462 }
5463}
5464
Daniel Vetter6ff93602013-04-19 11:24:36 +02005465static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005466{
5467 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02005469 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005470 uint32_t val;
5471
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005472 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005473
Daniel Vetterd8b32242013-04-25 17:54:44 +02005474 if (intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005475 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5476
Daniel Vetter6ff93602013-04-19 11:24:36 +02005477 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005478 val |= PIPECONF_INTERLACED_ILK;
5479 else
5480 val |= PIPECONF_PROGRESSIVE;
5481
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005482 I915_WRITE(PIPECONF(cpu_transcoder), val);
5483 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005484
5485 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5486 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005487}
5488
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005489static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005490 intel_clock_t *clock,
5491 bool *has_reduced_clock,
5492 intel_clock_t *reduced_clock)
5493{
5494 struct drm_device *dev = crtc->dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 struct intel_encoder *intel_encoder;
5497 int refclk;
5498 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02005499 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005500
5501 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5502 switch (intel_encoder->type) {
5503 case INTEL_OUTPUT_LVDS:
5504 is_lvds = true;
5505 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005506 }
5507 }
5508
5509 refclk = ironlake_get_refclk(crtc);
5510
5511 /*
5512 * Returns a set of divisors for the desired target clock with the given
5513 * refclk, or FALSE. The returned values represent the clock equation:
5514 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5515 */
5516 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02005517 ret = dev_priv->display.find_dpll(limit, crtc,
5518 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02005519 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005520 if (!ret)
5521 return false;
5522
5523 if (is_lvds && dev_priv->lvds_downclock_avail) {
5524 /*
5525 * Ensure we match the reduced clock's P to the target clock.
5526 * If the clocks don't match, we can't switch the display clock
5527 * by using the FP0/FP1. In such case we will disable the LVDS
5528 * downclock feature.
5529 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02005530 *has_reduced_clock =
5531 dev_priv->display.find_dpll(limit, crtc,
5532 dev_priv->lvds_downclock,
5533 refclk, clock,
5534 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005535 }
5536
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005537 return true;
5538}
5539
Daniel Vetter01a415f2012-10-27 15:58:40 +02005540static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5541{
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543 uint32_t temp;
5544
5545 temp = I915_READ(SOUTH_CHICKEN1);
5546 if (temp & FDI_BC_BIFURCATION_SELECT)
5547 return;
5548
5549 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5550 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5551
5552 temp |= FDI_BC_BIFURCATION_SELECT;
5553 DRM_DEBUG_KMS("enabling fdi C rx\n");
5554 I915_WRITE(SOUTH_CHICKEN1, temp);
5555 POSTING_READ(SOUTH_CHICKEN1);
5556}
5557
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005558static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
Daniel Vetter01a415f2012-10-27 15:58:40 +02005559{
5560 struct drm_device *dev = intel_crtc->base.dev;
5561 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005562
5563 switch (intel_crtc->pipe) {
5564 case PIPE_A:
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005565 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005566 case PIPE_B:
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005567 if (intel_crtc->config.fdi_lanes > 2)
Daniel Vetter01a415f2012-10-27 15:58:40 +02005568 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5569 else
5570 cpt_enable_fdi_bc_bifurcation(dev);
5571
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005572 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005573 case PIPE_C:
Daniel Vetter01a415f2012-10-27 15:58:40 +02005574 cpt_enable_fdi_bc_bifurcation(dev);
5575
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005576 break;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005577 default:
5578 BUG();
5579 }
5580}
5581
Paulo Zanonid4b19312012-11-29 11:29:32 -02005582int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5583{
5584 /*
5585 * Account for spread spectrum to avoid
5586 * oversubscribing the link. Max center spread
5587 * is 2.5%; use 5% for safety's sake.
5588 */
5589 u32 bps = target_clock * bpp * 21 / 20;
5590 return bps / (link_bw * 8) + 1;
5591}
5592
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005593static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02005594{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005595 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005596}
5597
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005598static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005599 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02005600 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005601{
5602 struct drm_crtc *crtc = &intel_crtc->base;
5603 struct drm_device *dev = crtc->dev;
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 struct intel_encoder *intel_encoder;
5606 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005607 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02005608 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005609
5610 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5611 switch (intel_encoder->type) {
5612 case INTEL_OUTPUT_LVDS:
5613 is_lvds = true;
5614 break;
5615 case INTEL_OUTPUT_SDVO:
5616 case INTEL_OUTPUT_HDMI:
5617 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005618 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005619 }
5620
5621 num_connectors++;
5622 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005623
Chris Wilsonc1858122010-12-03 21:35:48 +00005624 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005625 factor = 21;
5626 if (is_lvds) {
5627 if ((intel_panel_use_ssc(dev_priv) &&
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005628 dev_priv->vbt.lvds_ssc_freq == 100) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02005629 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07005630 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02005631 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07005632 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005633
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005634 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02005635 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005636
Daniel Vetter9a7c7892013-04-04 22:20:34 +02005637 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5638 *fp2 |= FP_CB_TUNE;
5639
Chris Wilson5eddb702010-09-11 13:48:45 +01005640 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005641
Eric Anholta07d6782011-03-30 13:01:08 -07005642 if (is_lvds)
5643 dpll |= DPLLB_MODE_LVDS;
5644 else
5645 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005646
Daniel Vetteref1b4602013-06-01 17:17:04 +02005647 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5648 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005649
5650 if (is_sdvo)
5651 dpll |= DPLL_DVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02005652 if (intel_crtc->config.has_dp_encoder)
Eric Anholta07d6782011-03-30 13:01:08 -07005653 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005654
Eric Anholta07d6782011-03-30 13:01:08 -07005655 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005656 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005657 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005658 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005659
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005660 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07005661 case 5:
5662 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5663 break;
5664 case 7:
5665 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5666 break;
5667 case 10:
5668 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5669 break;
5670 case 14:
5671 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5672 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005673 }
5674
Daniel Vetterb4c09f32013-04-30 14:01:42 +02005675 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005676 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08005677 else
5678 dpll |= PLL_REF_INPUT_DREFCLK;
5679
Daniel Vetter959e16d2013-06-05 13:34:21 +02005680 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005681}
5682
Jesse Barnes79e53942008-11-07 14:24:08 -08005683static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08005684 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005685 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005686{
5687 struct drm_device *dev = crtc->dev;
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5690 int pipe = intel_crtc->pipe;
5691 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005692 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005693 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005694 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005695 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01005696 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005697 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02005698 struct intel_shared_dpll *pll;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005699 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005700
5701 for_each_encoder_on_crtc(dev, crtc, encoder) {
5702 switch (encoder->type) {
5703 case INTEL_OUTPUT_LVDS:
5704 is_lvds = true;
5705 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005706 }
5707
5708 num_connectors++;
5709 }
5710
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005711 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5712 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5713
Daniel Vetterff9a6752013-06-01 17:16:21 +02005714 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005715 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02005716 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005717 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5718 return -EINVAL;
5719 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01005720 /* Compat-code for transition, will disappear. */
5721 if (!intel_crtc->config.clock_set) {
5722 intel_crtc->config.dpll.n = clock.n;
5723 intel_crtc->config.dpll.m1 = clock.m1;
5724 intel_crtc->config.dpll.m2 = clock.m2;
5725 intel_crtc->config.dpll.p1 = clock.p1;
5726 intel_crtc->config.dpll.p2 = clock.p2;
5727 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005728
5729 /* Ensure that the cursor is valid for the new mode before changing... */
5730 intel_crtc_update_cursor(crtc, true);
5731
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005732 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01005733 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005734 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005735 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005736 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005737
Daniel Vetter7429e9d2013-04-20 17:19:46 +02005738 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02005739 &fp, &reduced_clock,
5740 has_reduced_clock ? &fp2 : NULL);
5741
Daniel Vetter959e16d2013-06-05 13:34:21 +02005742 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02005743 intel_crtc->config.dpll_hw_state.fp0 = fp;
5744 if (has_reduced_clock)
5745 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5746 else
5747 intel_crtc->config.dpll_hw_state.fp1 = fp;
5748
Daniel Vetterb89a1d32013-06-05 13:34:24 +02005749 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005750 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03005751 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5752 pipe_name(pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07005753 return -EINVAL;
5754 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005755 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02005756 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005757
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005758 if (intel_crtc->config.has_dp_encoder)
5759 intel_dp_set_m_n(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005760
Daniel Vetterbcd644e2013-06-05 13:34:22 +02005761 if (is_lvds && has_reduced_clock && i915_powersave)
5762 intel_crtc->lowfreq_avail = true;
5763 else
5764 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02005765
5766 if (intel_crtc->config.has_pch_encoder) {
5767 pll = intel_crtc_to_shared_dpll(intel_crtc);
5768
Jesse Barnes79e53942008-11-07 14:24:08 -08005769 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005770
Daniel Vetter8a654f32013-06-01 17:16:22 +02005771 intel_set_pipe_timings(intel_crtc);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005772
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005773 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005774 intel_cpu_transcoder_set_m_n(intel_crtc,
5775 &intel_crtc->config.fdi_m_n);
5776 }
Chris Wilson5eddb702010-09-11 13:48:45 +01005777
Daniel Vetterebfd86f2013-04-19 11:24:44 +02005778 if (IS_IVYBRIDGE(dev))
5779 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005780
Daniel Vetter6ff93602013-04-19 11:24:36 +02005781 ironlake_set_pipeconf(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005782
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005783 /* Set up the display plane register */
5784 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005785 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005786
Daniel Vetter94352cf2012-07-05 22:51:56 +02005787 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005788
5789 intel_update_watermarks(dev);
5790
Daniel Vetter1857e1d2013-04-29 19:34:16 +02005791 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005792}
5793
Daniel Vetter72419202013-04-04 13:28:53 +02005794static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5795 struct intel_crtc_config *pipe_config)
5796{
5797 struct drm_device *dev = crtc->base.dev;
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 enum transcoder transcoder = pipe_config->cpu_transcoder;
5800
5801 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5802 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5803 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5804 & ~TU_SIZE_MASK;
5805 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5806 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5807 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5808}
5809
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005810static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5811 struct intel_crtc_config *pipe_config)
5812{
5813 struct drm_device *dev = crtc->base.dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 uint32_t tmp;
5816
5817 tmp = I915_READ(PF_CTL(crtc->pipe));
5818
5819 if (tmp & PF_ENABLE) {
5820 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5821 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02005822
5823 /* We currently do not free assignements of panel fitters on
5824 * ivb/hsw (since we don't use the higher upscaling modes which
5825 * differentiates them) so just WARN about this case for now. */
5826 if (IS_GEN7(dev)) {
5827 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5828 PF_PIPE_SEL_IVB(crtc->pipe));
5829 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005830 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005831}
5832
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005833static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5834 struct intel_crtc_config *pipe_config)
5835{
5836 struct drm_device *dev = crtc->base.dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 uint32_t tmp;
5839
Daniel Vettereccb1402013-05-22 00:50:22 +02005840 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005841 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02005842
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005843 tmp = I915_READ(PIPECONF(crtc->pipe));
5844 if (!(tmp & PIPECONF_ENABLE))
5845 return false;
5846
Daniel Vetterab9412b2013-05-03 11:49:46 +02005847 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02005848 struct intel_shared_dpll *pll;
5849
Daniel Vetter88adfff2013-03-28 10:42:01 +01005850 pipe_config->has_pch_encoder = true;
5851
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005852 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5853 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5854 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02005855
5856 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02005857
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005858 if (HAS_PCH_IBX(dev_priv->dev)) {
5859 pipe_config->shared_dpll = crtc->pipe;
5860 } else {
5861 tmp = I915_READ(PCH_DPLL_SEL);
5862 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5863 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5864 else
5865 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5866 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02005867
5868 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5869
5870 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5871 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02005872
5873 tmp = pipe_config->dpll_hw_state.dpll;
5874 pipe_config->pixel_multiplier =
5875 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5876 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter6c49f242013-06-06 12:45:25 +02005877 } else {
5878 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005879 }
5880
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005881 intel_get_pipe_timings(crtc, pipe_config);
5882
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005883 ironlake_get_pfit_config(crtc, pipe_config);
5884
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005885 return true;
5886}
5887
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005888static void haswell_modeset_global_resources(struct drm_device *dev)
5889{
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005890 bool enable = false;
5891 struct intel_crtc *crtc;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005892
5893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Daniel Vettere7a639c2013-05-31 17:49:17 +02005894 if (!crtc->base.enabled)
5895 continue;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005896
Daniel Vettere7a639c2013-05-31 17:49:17 +02005897 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5898 crtc->config.cpu_transcoder != TRANSCODER_EDP)
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005899 enable = true;
5900 }
5901
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02005902 intel_set_power_well(dev, enable);
5903}
5904
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005905static int haswell_crtc_mode_set(struct drm_crtc *crtc,
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005906 int x, int y,
5907 struct drm_framebuffer *fb)
5908{
5909 struct drm_device *dev = crtc->dev;
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005912 int plane = intel_crtc->plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005913 int ret;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005914
Daniel Vetterff9a6752013-06-01 17:16:21 +02005915 if (!intel_ddi_pll_mode_set(crtc))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005916 return -EINVAL;
5917
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005918 /* Ensure that the cursor is valid for the new mode before changing... */
5919 intel_crtc_update_cursor(crtc, true);
5920
Daniel Vetter03afc4a2013-04-02 23:42:31 +02005921 if (intel_crtc->config.has_dp_encoder)
5922 intel_dp_set_m_n(intel_crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005923
5924 intel_crtc->lowfreq_avail = false;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005925
Daniel Vetter8a654f32013-06-01 17:16:22 +02005926 intel_set_pipe_timings(intel_crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005927
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005928 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01005929 intel_cpu_transcoder_set_m_n(intel_crtc,
5930 &intel_crtc->config.fdi_m_n);
5931 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005932
Daniel Vetter6ff93602013-04-19 11:24:36 +02005933 haswell_set_pipeconf(crtc);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005934
Daniel Vetter50f3b012013-03-27 00:44:56 +01005935 intel_set_pipe_csc(crtc);
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005936
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005937 /* Set up the display plane register */
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005938 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005939 POSTING_READ(DSPCNTR(plane));
5940
5941 ret = intel_pipe_set_base(crtc, x, y, fb);
5942
5943 intel_update_watermarks(dev);
5944
Jesse Barnes79e53942008-11-07 14:24:08 -08005945 return ret;
5946}
5947
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005948static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5949 struct intel_crtc_config *pipe_config)
5950{
5951 struct drm_device *dev = crtc->base.dev;
5952 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005953 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005954 uint32_t tmp;
5955
Daniel Vettereccb1402013-05-22 00:50:22 +02005956 pipe_config->cpu_transcoder = crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005957 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5958
Daniel Vettereccb1402013-05-22 00:50:22 +02005959 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5960 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5961 enum pipe trans_edp_pipe;
5962 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5963 default:
5964 WARN(1, "unknown pipe linked to edp transcoder\n");
5965 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5966 case TRANS_DDI_EDP_INPUT_A_ON:
5967 trans_edp_pipe = PIPE_A;
5968 break;
5969 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5970 trans_edp_pipe = PIPE_B;
5971 break;
5972 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5973 trans_edp_pipe = PIPE_C;
5974 break;
5975 }
5976
5977 if (trans_edp_pipe == crtc->pipe)
5978 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5979 }
5980
Paulo Zanonib97186f2013-05-03 12:15:36 -03005981 if (!intel_display_power_enabled(dev,
Daniel Vettereccb1402013-05-22 00:50:22 +02005982 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -03005983 return false;
5984
Daniel Vettereccb1402013-05-22 00:50:22 +02005985 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005986 if (!(tmp & PIPECONF_ENABLE))
5987 return false;
5988
Daniel Vetter88adfff2013-03-28 10:42:01 +01005989 /*
Paulo Zanonif196e6b2013-04-18 16:35:41 -03005990 * Haswell has only FDI/PCH transcoder A. It is which is connected to
Daniel Vetter88adfff2013-03-28 10:42:01 +01005991 * DDI E. So just check whether this pipe is wired to DDI E and whether
5992 * the PCH transcoder is on.
5993 */
Daniel Vettereccb1402013-05-22 00:50:22 +02005994 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
Daniel Vetter88adfff2013-03-28 10:42:01 +01005995 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
Daniel Vetterab9412b2013-05-03 11:49:46 +02005996 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01005997 pipe_config->has_pch_encoder = true;
5998
Daniel Vetter627eb5a2013-04-29 19:33:42 +02005999 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6000 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6001 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02006002
6003 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006004 }
6005
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006006 intel_get_pipe_timings(crtc, pipe_config);
6007
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006008 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6009 if (intel_display_power_enabled(dev, pfit_domain))
6010 ironlake_get_pfit_config(crtc, pipe_config);
Daniel Vetter88adfff2013-03-28 10:42:01 +01006011
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006012 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6013 (I915_READ(IPS_CTL) & IPS_ENABLE);
6014
Daniel Vetter6c49f242013-06-06 12:45:25 +02006015 pipe_config->pixel_multiplier = 1;
6016
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006017 return true;
6018}
6019
Eric Anholtf564048e2011-03-30 13:01:02 -07006020static int intel_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07006021 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006022 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07006023{
6024 struct drm_device *dev = crtc->dev;
6025 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9256aa12012-10-31 19:26:13 +01006026 struct drm_encoder_helper_funcs *encoder_funcs;
6027 struct intel_encoder *encoder;
Eric Anholt0b701d22011-03-30 13:01:03 -07006028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01006029 struct drm_display_mode *adjusted_mode =
6030 &intel_crtc->config.adjusted_mode;
6031 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Eric Anholt0b701d22011-03-30 13:01:03 -07006032 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07006033 int ret;
6034
Eric Anholt0b701d22011-03-30 13:01:03 -07006035 drm_vblank_pre_modeset(dev, pipe);
6036
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01006037 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6038
Jesse Barnes79e53942008-11-07 14:24:08 -08006039 drm_vblank_post_modeset(dev, pipe);
6040
Daniel Vetter9256aa12012-10-31 19:26:13 +01006041 if (ret != 0)
6042 return ret;
6043
6044 for_each_encoder_on_crtc(dev, crtc, encoder) {
6045 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6046 encoder->base.base.id,
6047 drm_get_encoder_name(&encoder->base),
6048 mode->base.id, mode->name);
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006049 if (encoder->mode_set) {
6050 encoder->mode_set(encoder);
6051 } else {
6052 encoder_funcs = encoder->base.helper_private;
6053 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6054 }
Daniel Vetter9256aa12012-10-31 19:26:13 +01006055 }
6056
6057 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006058}
6059
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006060static bool intel_eld_uptodate(struct drm_connector *connector,
6061 int reg_eldv, uint32_t bits_eldv,
6062 int reg_elda, uint32_t bits_elda,
6063 int reg_edid)
6064{
6065 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6066 uint8_t *eld = connector->eld;
6067 uint32_t i;
6068
6069 i = I915_READ(reg_eldv);
6070 i &= bits_eldv;
6071
6072 if (!eld[0])
6073 return !i;
6074
6075 if (!i)
6076 return false;
6077
6078 i = I915_READ(reg_elda);
6079 i &= ~bits_elda;
6080 I915_WRITE(reg_elda, i);
6081
6082 for (i = 0; i < eld[2]; i++)
6083 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6084 return false;
6085
6086 return true;
6087}
6088
Wu Fengguange0dac652011-09-05 14:25:34 +08006089static void g4x_write_eld(struct drm_connector *connector,
6090 struct drm_crtc *crtc)
6091{
6092 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6093 uint8_t *eld = connector->eld;
6094 uint32_t eldv;
6095 uint32_t len;
6096 uint32_t i;
6097
6098 i = I915_READ(G4X_AUD_VID_DID);
6099
6100 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6101 eldv = G4X_ELDV_DEVCL_DEVBLC;
6102 else
6103 eldv = G4X_ELDV_DEVCTG;
6104
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006105 if (intel_eld_uptodate(connector,
6106 G4X_AUD_CNTL_ST, eldv,
6107 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6108 G4X_HDMIW_HDMIEDID))
6109 return;
6110
Wu Fengguange0dac652011-09-05 14:25:34 +08006111 i = I915_READ(G4X_AUD_CNTL_ST);
6112 i &= ~(eldv | G4X_ELD_ADDR);
6113 len = (i >> 9) & 0x1f; /* ELD buffer size */
6114 I915_WRITE(G4X_AUD_CNTL_ST, i);
6115
6116 if (!eld[0])
6117 return;
6118
6119 len = min_t(uint8_t, eld[2], len);
6120 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6121 for (i = 0; i < len; i++)
6122 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6123
6124 i = I915_READ(G4X_AUD_CNTL_ST);
6125 i |= eldv;
6126 I915_WRITE(G4X_AUD_CNTL_ST, i);
6127}
6128
Wang Xingchao83358c852012-08-16 22:43:37 +08006129static void haswell_write_eld(struct drm_connector *connector,
6130 struct drm_crtc *crtc)
6131{
6132 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6133 uint8_t *eld = connector->eld;
6134 struct drm_device *dev = crtc->dev;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08006135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Wang Xingchao83358c852012-08-16 22:43:37 +08006136 uint32_t eldv;
6137 uint32_t i;
6138 int len;
6139 int pipe = to_intel_crtc(crtc)->pipe;
6140 int tmp;
6141
6142 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6143 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6144 int aud_config = HSW_AUD_CFG(pipe);
6145 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6146
6147
6148 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6149
6150 /* Audio output enable */
6151 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6152 tmp = I915_READ(aud_cntrl_st2);
6153 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6154 I915_WRITE(aud_cntrl_st2, tmp);
6155
6156 /* Wait for 1 vertical blank */
6157 intel_wait_for_vblank(dev, pipe);
6158
6159 /* Set ELD valid state */
6160 tmp = I915_READ(aud_cntrl_st2);
6161 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6162 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6163 I915_WRITE(aud_cntrl_st2, tmp);
6164 tmp = I915_READ(aud_cntrl_st2);
6165 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6166
6167 /* Enable HDMI mode */
6168 tmp = I915_READ(aud_config);
6169 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6170 /* clear N_programing_enable and N_value_index */
6171 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6172 I915_WRITE(aud_config, tmp);
6173
6174 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6175
6176 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08006177 intel_crtc->eld_vld = true;
Wang Xingchao83358c852012-08-16 22:43:37 +08006178
6179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6180 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6181 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6182 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6183 } else
6184 I915_WRITE(aud_config, 0);
6185
6186 if (intel_eld_uptodate(connector,
6187 aud_cntrl_st2, eldv,
6188 aud_cntl_st, IBX_ELD_ADDRESS,
6189 hdmiw_hdmiedid))
6190 return;
6191
6192 i = I915_READ(aud_cntrl_st2);
6193 i &= ~eldv;
6194 I915_WRITE(aud_cntrl_st2, i);
6195
6196 if (!eld[0])
6197 return;
6198
6199 i = I915_READ(aud_cntl_st);
6200 i &= ~IBX_ELD_ADDRESS;
6201 I915_WRITE(aud_cntl_st, i);
6202 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6203 DRM_DEBUG_DRIVER("port num:%d\n", i);
6204
6205 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6206 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6207 for (i = 0; i < len; i++)
6208 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6209
6210 i = I915_READ(aud_cntrl_st2);
6211 i |= eldv;
6212 I915_WRITE(aud_cntrl_st2, i);
6213
6214}
6215
Wu Fengguange0dac652011-09-05 14:25:34 +08006216static void ironlake_write_eld(struct drm_connector *connector,
6217 struct drm_crtc *crtc)
6218{
6219 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6220 uint8_t *eld = connector->eld;
6221 uint32_t eldv;
6222 uint32_t i;
6223 int len;
6224 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006225 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08006226 int aud_cntl_st;
6227 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08006228 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08006229
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08006230 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006231 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6232 aud_config = IBX_AUD_CFG(pipe);
6233 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006234 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006235 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006236 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6237 aud_config = CPT_AUD_CFG(pipe);
6238 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006239 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006240 }
6241
Wang Xingchao9b138a82012-08-09 16:52:18 +08006242 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08006243
6244 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08006245 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08006246 if (!i) {
6247 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6248 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006249 eldv = IBX_ELD_VALIDB;
6250 eldv |= IBX_ELD_VALIDB << 4;
6251 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08006252 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03006253 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006254 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08006255 }
6256
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006257 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6258 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6259 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06006260 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6261 } else
6262 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006263
6264 if (intel_eld_uptodate(connector,
6265 aud_cntrl_st2, eldv,
6266 aud_cntl_st, IBX_ELD_ADDRESS,
6267 hdmiw_hdmiedid))
6268 return;
6269
Wu Fengguange0dac652011-09-05 14:25:34 +08006270 i = I915_READ(aud_cntrl_st2);
6271 i &= ~eldv;
6272 I915_WRITE(aud_cntrl_st2, i);
6273
6274 if (!eld[0])
6275 return;
6276
Wu Fengguange0dac652011-09-05 14:25:34 +08006277 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006278 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08006279 I915_WRITE(aud_cntl_st, i);
6280
6281 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6282 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6283 for (i = 0; i < len; i++)
6284 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6285
6286 i = I915_READ(aud_cntrl_st2);
6287 i |= eldv;
6288 I915_WRITE(aud_cntrl_st2, i);
6289}
6290
6291void intel_write_eld(struct drm_encoder *encoder,
6292 struct drm_display_mode *mode)
6293{
6294 struct drm_crtc *crtc = encoder->crtc;
6295 struct drm_connector *connector;
6296 struct drm_device *dev = encoder->dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299 connector = drm_select_eld(encoder, mode);
6300 if (!connector)
6301 return;
6302
6303 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6304 connector->base.id,
6305 drm_get_connector_name(connector),
6306 connector->encoder->base.id,
6307 drm_get_encoder_name(connector->encoder));
6308
6309 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6310
6311 if (dev_priv->display.write_eld)
6312 dev_priv->display.write_eld(connector, crtc);
6313}
6314
Jesse Barnes79e53942008-11-07 14:24:08 -08006315/** Loads the palette/gamma unit for the CRTC with the prepared values */
6316void intel_crtc_load_lut(struct drm_crtc *crtc)
6317{
6318 struct drm_device *dev = crtc->dev;
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006321 enum pipe pipe = intel_crtc->pipe;
6322 int palreg = PALETTE(pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006323 int i;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006324 bool reenable_ips = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006325
6326 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00006327 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08006328 return;
6329
Ville Syrjälä14420bd2013-06-04 13:49:07 +03006330 if (!HAS_PCH_SPLIT(dev_priv->dev))
6331 assert_pll_enabled(dev_priv, pipe);
6332
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006333 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07006334 if (HAS_PCH_SPLIT(dev))
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006335 palreg = LGC_PALETTE(pipe);
6336
6337 /* Workaround : Do not read or write the pipe palette/gamma data while
6338 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6339 */
6340 if (intel_crtc->config.ips_enabled &&
6341 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6342 GAMMA_MODE_MODE_SPLIT)) {
6343 hsw_disable_ips(intel_crtc);
6344 reenable_ips = true;
6345 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08006346
Jesse Barnes79e53942008-11-07 14:24:08 -08006347 for (i = 0; i < 256; i++) {
6348 I915_WRITE(palreg + 4 * i,
6349 (intel_crtc->lut_r[i] << 16) |
6350 (intel_crtc->lut_g[i] << 8) |
6351 intel_crtc->lut_b[i]);
6352 }
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006353
6354 if (reenable_ips)
6355 hsw_enable_ips(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006356}
6357
Chris Wilson560b85b2010-08-07 11:01:38 +01006358static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6359{
6360 struct drm_device *dev = crtc->dev;
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363 bool visible = base != 0;
6364 u32 cntl;
6365
6366 if (intel_crtc->cursor_visible == visible)
6367 return;
6368
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006369 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01006370 if (visible) {
6371 /* On these chipsets we can only modify the base whilst
6372 * the cursor is disabled.
6373 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006374 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006375
6376 cntl &= ~(CURSOR_FORMAT_MASK);
6377 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6378 cntl |= CURSOR_ENABLE |
6379 CURSOR_GAMMA_ENABLE |
6380 CURSOR_FORMAT_ARGB;
6381 } else
6382 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006383 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006384
6385 intel_crtc->cursor_visible = visible;
6386}
6387
6388static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6389{
6390 struct drm_device *dev = crtc->dev;
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6393 int pipe = intel_crtc->pipe;
6394 bool visible = base != 0;
6395
6396 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08006397 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01006398 if (base) {
6399 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6400 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6401 cntl |= pipe << 28; /* Connect to correct pipe */
6402 } else {
6403 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6404 cntl |= CURSOR_MODE_DISABLE;
6405 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006406 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006407
6408 intel_crtc->cursor_visible = visible;
6409 }
6410 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006411 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006412}
6413
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006414static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6415{
6416 struct drm_device *dev = crtc->dev;
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 int pipe = intel_crtc->pipe;
6420 bool visible = base != 0;
6421
6422 if (intel_crtc->cursor_visible != visible) {
6423 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6424 if (base) {
6425 cntl &= ~CURSOR_MODE;
6426 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6427 } else {
6428 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6429 cntl |= CURSOR_MODE_DISABLE;
6430 }
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006431 if (IS_HASWELL(dev))
6432 cntl |= CURSOR_PIPE_CSC_ENABLE;
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006433 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6434
6435 intel_crtc->cursor_visible = visible;
6436 }
6437 /* and commit changes on next vblank */
6438 I915_WRITE(CURBASE_IVB(pipe), base);
6439}
6440
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006441/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01006442static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6443 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006444{
6445 struct drm_device *dev = crtc->dev;
6446 struct drm_i915_private *dev_priv = dev->dev_private;
6447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6448 int pipe = intel_crtc->pipe;
6449 int x = intel_crtc->cursor_x;
6450 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01006451 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006452 bool visible;
6453
6454 pos = 0;
6455
Chris Wilson6b383a72010-09-13 13:54:26 +01006456 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006457 base = intel_crtc->cursor_addr;
6458 if (x > (int) crtc->fb->width)
6459 base = 0;
6460
6461 if (y > (int) crtc->fb->height)
6462 base = 0;
6463 } else
6464 base = 0;
6465
6466 if (x < 0) {
6467 if (x + intel_crtc->cursor_width < 0)
6468 base = 0;
6469
6470 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6471 x = -x;
6472 }
6473 pos |= x << CURSOR_X_SHIFT;
6474
6475 if (y < 0) {
6476 if (y + intel_crtc->cursor_height < 0)
6477 base = 0;
6478
6479 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6480 y = -y;
6481 }
6482 pos |= y << CURSOR_Y_SHIFT;
6483
6484 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006485 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006486 return;
6487
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03006488 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006489 I915_WRITE(CURPOS_IVB(pipe), pos);
6490 ivb_update_cursor(crtc, base);
6491 } else {
6492 I915_WRITE(CURPOS(pipe), pos);
6493 if (IS_845G(dev) || IS_I865G(dev))
6494 i845_update_cursor(crtc, base);
6495 else
6496 i9xx_update_cursor(crtc, base);
6497 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006498}
6499
Jesse Barnes79e53942008-11-07 14:24:08 -08006500static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006501 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006502 uint32_t handle,
6503 uint32_t width, uint32_t height)
6504{
6505 struct drm_device *dev = crtc->dev;
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006508 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006509 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006510 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006511
Jesse Barnes79e53942008-11-07 14:24:08 -08006512 /* if we want to turn off the cursor ignore width and height */
6513 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006514 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006515 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006516 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006517 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006518 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006519 }
6520
6521 /* Currently we only support 64x64 cursors */
6522 if (width != 64 || height != 64) {
6523 DRM_ERROR("we currently only support 64x64 cursors\n");
6524 return -EINVAL;
6525 }
6526
Chris Wilson05394f32010-11-08 19:18:58 +00006527 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006528 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006529 return -ENOENT;
6530
Chris Wilson05394f32010-11-08 19:18:58 +00006531 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006532 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006533 ret = -ENOMEM;
6534 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006535 }
6536
Dave Airlie71acb5e2008-12-30 20:31:46 +10006537 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006538 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006539 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00006540 unsigned alignment;
6541
Chris Wilsond9e86c02010-11-10 16:40:20 +00006542 if (obj->tiling_mode) {
6543 DRM_ERROR("cursor cannot be tiled\n");
6544 ret = -EINVAL;
6545 goto fail_locked;
6546 }
6547
Chris Wilson693db182013-03-05 14:52:39 +00006548 /* Note that the w/a also requires 2 PTE of padding following
6549 * the bo. We currently fill all unused PTE with the shadow
6550 * page and so we should always have valid PTE following the
6551 * cursor preventing the VT-d warning.
6552 */
6553 alignment = 0;
6554 if (need_vtd_wa(dev))
6555 alignment = 64*1024;
6556
6557 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006558 if (ret) {
6559 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006560 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006561 }
6562
Chris Wilsond9e86c02010-11-10 16:40:20 +00006563 ret = i915_gem_object_put_fence(obj);
6564 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006565 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006566 goto fail_unpin;
6567 }
6568
Chris Wilson05394f32010-11-08 19:18:58 +00006569 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006570 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006571 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006572 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006573 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6574 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006575 if (ret) {
6576 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006577 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006578 }
Chris Wilson05394f32010-11-08 19:18:58 +00006579 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006580 }
6581
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006582 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006583 I915_WRITE(CURSIZE, (height << 12) | width);
6584
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006585 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006586 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006587 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006588 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006589 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6590 } else
6591 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006592 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006593 }
Jesse Barnes80824002009-09-10 15:28:06 -07006594
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006595 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006596
6597 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006598 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006599 intel_crtc->cursor_width = width;
6600 intel_crtc->cursor_height = height;
6601
Mika Kuoppala40ccc722013-04-23 17:27:08 +03006602 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006603
Jesse Barnes79e53942008-11-07 14:24:08 -08006604 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006605fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006606 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006607fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006608 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006609fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006610 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006611 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006612}
6613
6614static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6615{
Jesse Barnes79e53942008-11-07 14:24:08 -08006616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006617
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006618 intel_crtc->cursor_x = x;
6619 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006620
Mika Kuoppala40ccc722013-04-23 17:27:08 +03006621 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08006622
6623 return 0;
6624}
6625
6626/** Sets the color ramps on behalf of RandR */
6627void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6628 u16 blue, int regno)
6629{
6630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6631
6632 intel_crtc->lut_r[regno] = red >> 8;
6633 intel_crtc->lut_g[regno] = green >> 8;
6634 intel_crtc->lut_b[regno] = blue >> 8;
6635}
6636
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006637void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6638 u16 *blue, int regno)
6639{
6640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6641
6642 *red = intel_crtc->lut_r[regno] << 8;
6643 *green = intel_crtc->lut_g[regno] << 8;
6644 *blue = intel_crtc->lut_b[regno] << 8;
6645}
6646
Jesse Barnes79e53942008-11-07 14:24:08 -08006647static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006648 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006649{
James Simmons72034252010-08-03 01:33:19 +01006650 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006652
James Simmons72034252010-08-03 01:33:19 +01006653 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006654 intel_crtc->lut_r[i] = red[i] >> 8;
6655 intel_crtc->lut_g[i] = green[i] >> 8;
6656 intel_crtc->lut_b[i] = blue[i] >> 8;
6657 }
6658
6659 intel_crtc_load_lut(crtc);
6660}
6661
Jesse Barnes79e53942008-11-07 14:24:08 -08006662/* VESA 640x480x72Hz mode to set on the pipe */
6663static struct drm_display_mode load_detect_mode = {
6664 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6665 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6666};
6667
Chris Wilsond2dff872011-04-19 08:36:26 +01006668static struct drm_framebuffer *
6669intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006670 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01006671 struct drm_i915_gem_object *obj)
6672{
6673 struct intel_framebuffer *intel_fb;
6674 int ret;
6675
6676 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6677 if (!intel_fb) {
6678 drm_gem_object_unreference_unlocked(&obj->base);
6679 return ERR_PTR(-ENOMEM);
6680 }
6681
6682 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6683 if (ret) {
6684 drm_gem_object_unreference_unlocked(&obj->base);
6685 kfree(intel_fb);
6686 return ERR_PTR(ret);
6687 }
6688
6689 return &intel_fb->base;
6690}
6691
6692static u32
6693intel_framebuffer_pitch_for_width(int width, int bpp)
6694{
6695 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6696 return ALIGN(pitch, 64);
6697}
6698
6699static u32
6700intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6701{
6702 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6703 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6704}
6705
6706static struct drm_framebuffer *
6707intel_framebuffer_create_for_mode(struct drm_device *dev,
6708 struct drm_display_mode *mode,
6709 int depth, int bpp)
6710{
6711 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00006712 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01006713
6714 obj = i915_gem_alloc_object(dev,
6715 intel_framebuffer_size_for_mode(mode, bpp));
6716 if (obj == NULL)
6717 return ERR_PTR(-ENOMEM);
6718
6719 mode_cmd.width = mode->hdisplay;
6720 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006721 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6722 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00006723 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01006724
6725 return intel_framebuffer_create(dev, &mode_cmd, obj);
6726}
6727
6728static struct drm_framebuffer *
6729mode_fits_in_fbdev(struct drm_device *dev,
6730 struct drm_display_mode *mode)
6731{
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6733 struct drm_i915_gem_object *obj;
6734 struct drm_framebuffer *fb;
6735
6736 if (dev_priv->fbdev == NULL)
6737 return NULL;
6738
6739 obj = dev_priv->fbdev->ifb.obj;
6740 if (obj == NULL)
6741 return NULL;
6742
6743 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006744 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6745 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006746 return NULL;
6747
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006748 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006749 return NULL;
6750
6751 return fb;
6752}
6753
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006754bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01006755 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006756 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006757{
6758 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006759 struct intel_encoder *intel_encoder =
6760 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08006761 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006762 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006763 struct drm_crtc *crtc = NULL;
6764 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02006765 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006766 int i = -1;
6767
Chris Wilsond2dff872011-04-19 08:36:26 +01006768 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6769 connector->base.id, drm_get_connector_name(connector),
6770 encoder->base.id, drm_get_encoder_name(encoder));
6771
Jesse Barnes79e53942008-11-07 14:24:08 -08006772 /*
6773 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006774 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006775 * - if the connector already has an assigned crtc, use it (but make
6776 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006777 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006778 * - try to find the first unused crtc that can drive this connector,
6779 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006780 */
6781
6782 /* See if we already have a CRTC for this connector */
6783 if (encoder->crtc) {
6784 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006785
Daniel Vetter7b240562012-12-12 00:35:33 +01006786 mutex_lock(&crtc->mutex);
6787
Daniel Vetter24218aa2012-08-12 19:27:11 +02006788 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006789 old->load_detect_temp = false;
6790
6791 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006792 if (connector->dpms != DRM_MODE_DPMS_ON)
6793 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01006794
Chris Wilson71731882011-04-19 23:10:58 +01006795 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006796 }
6797
6798 /* Find an unused one (if possible) */
6799 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6800 i++;
6801 if (!(encoder->possible_crtcs & (1 << i)))
6802 continue;
6803 if (!possible_crtc->enabled) {
6804 crtc = possible_crtc;
6805 break;
6806 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006807 }
6808
6809 /*
6810 * If we didn't find an unused CRTC, don't use any.
6811 */
6812 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006813 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6814 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006815 }
6816
Daniel Vetter7b240562012-12-12 00:35:33 +01006817 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02006818 intel_encoder->new_crtc = to_intel_crtc(crtc);
6819 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006820
6821 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006822 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006823 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006824 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006825
Chris Wilson64927112011-04-20 07:25:26 +01006826 if (!mode)
6827 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006828
Chris Wilsond2dff872011-04-19 08:36:26 +01006829 /* We need a framebuffer large enough to accommodate all accesses
6830 * that the plane may generate whilst we perform load detection.
6831 * We can not rely on the fbcon either being present (we get called
6832 * during its initialisation to detect all boot displays, or it may
6833 * not even exist) or that it is large enough to satisfy the
6834 * requested mode.
6835 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02006836 fb = mode_fits_in_fbdev(dev, mode);
6837 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006838 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006839 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6840 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01006841 } else
6842 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006843 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006844 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter7b240562012-12-12 00:35:33 +01006845 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006846 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006847 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006848
Chris Wilsonc0c36b942012-12-19 16:08:43 +00006849 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006850 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006851 if (old->release_fb)
6852 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter7b240562012-12-12 00:35:33 +01006853 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006854 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006855 }
Chris Wilson71731882011-04-19 23:10:58 +01006856
Jesse Barnes79e53942008-11-07 14:24:08 -08006857 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006858 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01006859 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006860}
6861
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006862void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01006863 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006864{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006865 struct intel_encoder *intel_encoder =
6866 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01006867 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01006868 struct drm_crtc *crtc = encoder->crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -08006869
Chris Wilsond2dff872011-04-19 08:36:26 +01006870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6871 connector->base.id, drm_get_connector_name(connector),
6872 encoder->base.id, drm_get_encoder_name(encoder));
6873
Chris Wilson8261b192011-04-19 23:18:09 +01006874 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02006875 to_intel_connector(connector)->new_encoder = NULL;
6876 intel_encoder->new_crtc = NULL;
6877 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01006878
Daniel Vetter36206362012-12-10 20:42:17 +01006879 if (old->release_fb) {
6880 drm_framebuffer_unregister_private(old->release_fb);
6881 drm_framebuffer_unreference(old->release_fb);
6882 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006883
Daniel Vetter67c96402013-01-23 16:25:09 +00006884 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01006885 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006886 }
6887
Eric Anholtc751ce42010-03-25 11:48:48 -07006888 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006889 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6890 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01006891
6892 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08006893}
6894
6895/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03006896static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6897 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08006898{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03006899 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08006900 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03006901 int pipe = pipe_config->cpu_transcoder;
Jesse Barnes548f2452011-02-17 10:40:53 -08006902 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006903 u32 fp;
6904 intel_clock_t clock;
6905
6906 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006907 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006908 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006909 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006910
6911 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006912 if (IS_PINEVIEW(dev)) {
6913 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6914 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006915 } else {
6916 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6917 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6918 }
6919
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006920 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006921 if (IS_PINEVIEW(dev))
6922 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6923 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006924 else
6925 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006926 DPLL_FPA01_P1_POST_DIV_SHIFT);
6927
6928 switch (dpll & DPLL_MODE_MASK) {
6929 case DPLLB_MODE_DAC_SERIAL:
6930 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6931 5 : 10;
6932 break;
6933 case DPLLB_MODE_LVDS:
6934 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6935 7 : 14;
6936 break;
6937 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006938 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006939 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03006940 pipe_config->adjusted_mode.clock = 0;
6941 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006942 }
6943
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006944 if (IS_PINEVIEW(dev))
6945 pineview_clock(96000, &clock);
6946 else
6947 i9xx_clock(96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006948 } else {
6949 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6950
6951 if (is_lvds) {
6952 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6953 DPLL_FPA01_P1_POST_DIV_SHIFT);
6954 clock.p2 = 14;
6955
6956 if ((dpll & PLL_REF_INPUT_MASK) ==
6957 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6958 /* XXX: might not be 66MHz */
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006959 i9xx_clock(66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006960 } else
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006961 i9xx_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006962 } else {
6963 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6964 clock.p1 = 2;
6965 else {
6966 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6967 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6968 }
6969 if (dpll & PLL_P2_DIVIDE_BY_4)
6970 clock.p2 = 4;
6971 else
6972 clock.p2 = 2;
6973
Daniel Vetterac58c3f2013-06-01 17:16:17 +02006974 i9xx_clock(48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006975 }
6976 }
6977
Jesse Barnesf1f644d2013-06-27 00:39:25 +03006978 pipe_config->adjusted_mode.clock = clock.dot *
6979 pipe_config->pixel_multiplier;
6980}
6981
6982static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6983 struct intel_crtc_config *pipe_config)
6984{
6985 struct drm_device *dev = crtc->base.dev;
6986 struct drm_i915_private *dev_priv = dev->dev_private;
6987 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6988 int link_freq, repeat;
6989 u64 clock;
6990 u32 link_m, link_n;
6991
6992 repeat = pipe_config->pixel_multiplier;
6993
6994 /*
6995 * The calculation for the data clock is:
6996 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6997 * But we want to avoid losing precison if possible, so:
6998 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
6999 *
7000 * and the link clock is simpler:
7001 * link_clock = (m * link_clock * repeat) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08007002 */
7003
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007004 /*
7005 * We need to get the FDI or DP link clock here to derive
7006 * the M/N dividers.
7007 *
7008 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7009 * For DP, it's either 1.62GHz or 2.7GHz.
7010 * We do our calculations in 10*MHz since we don't need much precison.
7011 */
7012 if (pipe_config->has_pch_encoder)
7013 link_freq = intel_fdi_link_freq(dev) * 10000;
7014 else
7015 link_freq = pipe_config->port_clock;
7016
7017 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7018 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7019
7020 if (!link_m || !link_n)
7021 return;
7022
7023 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7024 do_div(clock, link_n);
7025
7026 pipe_config->adjusted_mode.clock = clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08007027}
7028
7029/** Returns the currently programmed mode of the given pipe. */
7030struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7031 struct drm_crtc *crtc)
7032{
Jesse Barnes548f2452011-02-17 10:40:53 -08007033 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02007035 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007036 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007037 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007038 int htot = I915_READ(HTOTAL(cpu_transcoder));
7039 int hsync = I915_READ(HSYNC(cpu_transcoder));
7040 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7041 int vsync = I915_READ(VSYNC(cpu_transcoder));
Jesse Barnes79e53942008-11-07 14:24:08 -08007042
7043 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7044 if (!mode)
7045 return NULL;
7046
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007047 /*
7048 * Construct a pipe_config sufficient for getting the clock info
7049 * back out of crtc_clock_get.
7050 *
7051 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7052 * to use a real value here instead.
7053 */
7054 pipe_config.cpu_transcoder = intel_crtc->pipe;
7055 pipe_config.pixel_multiplier = 1;
7056 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7057
7058 mode->clock = pipe_config.adjusted_mode.clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08007059 mode->hdisplay = (htot & 0xffff) + 1;
7060 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7061 mode->hsync_start = (hsync & 0xffff) + 1;
7062 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7063 mode->vdisplay = (vtot & 0xffff) + 1;
7064 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7065 mode->vsync_start = (vsync & 0xffff) + 1;
7066 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7067
7068 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08007069
7070 return mode;
7071}
7072
Daniel Vetter3dec0092010-08-20 21:40:52 +02007073static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07007074{
7075 struct drm_device *dev = crtc->dev;
7076 drm_i915_private_t *dev_priv = dev->dev_private;
7077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7078 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007079 int dpll_reg = DPLL(pipe);
7080 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07007081
Eric Anholtbad720f2009-10-22 16:11:14 -07007082 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007083 return;
7084
7085 if (!dev_priv->lvds_downclock_avail)
7086 return;
7087
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007088 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07007089 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08007090 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007091
Sean Paul8ac5a6d2012-02-13 13:14:51 -05007092 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007093
7094 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007096 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007097
Jesse Barnes652c3932009-08-17 13:31:43 -07007098 dpll = I915_READ(dpll_reg);
7099 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08007100 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007101 }
Jesse Barnes652c3932009-08-17 13:31:43 -07007102}
7103
7104static void intel_decrease_pllclock(struct drm_crtc *crtc)
7105{
7106 struct drm_device *dev = crtc->dev;
7107 drm_i915_private_t *dev_priv = dev->dev_private;
7108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007109
Eric Anholtbad720f2009-10-22 16:11:14 -07007110 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007111 return;
7112
7113 if (!dev_priv->lvds_downclock_avail)
7114 return;
7115
7116 /*
7117 * Since this is called by a timer, we should never get here in
7118 * the manual case.
7119 */
7120 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01007121 int pipe = intel_crtc->pipe;
7122 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02007123 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01007124
Zhao Yakui44d98a62009-10-09 11:39:40 +08007125 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007126
Sean Paul8ac5a6d2012-02-13 13:14:51 -05007127 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007128
Chris Wilson074b5e12012-05-02 12:07:06 +01007129 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07007130 dpll |= DISPLAY_RATE_SELECT_FPA1;
7131 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007132 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007133 dpll = I915_READ(dpll_reg);
7134 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08007135 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007136 }
7137
7138}
7139
Chris Wilsonf047e392012-07-21 12:31:41 +01007140void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07007141{
Chris Wilsonf047e392012-07-21 12:31:41 +01007142 i915_update_gfx_val(dev->dev_private);
7143}
7144
7145void intel_mark_idle(struct drm_device *dev)
7146{
Chris Wilson725a5b52013-01-08 11:02:57 +00007147 struct drm_crtc *crtc;
7148
7149 if (!i915_powersave)
7150 return;
7151
7152 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7153 if (!crtc->fb)
7154 continue;
7155
7156 intel_decrease_pllclock(crtc);
7157 }
Chris Wilsonf047e392012-07-21 12:31:41 +01007158}
7159
Chris Wilsonc65355b2013-06-06 16:53:41 -03007160void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7161 struct intel_ring_buffer *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01007162{
7163 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07007164 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07007165
7166 if (!i915_powersave)
7167 return;
7168
Jesse Barnes652c3932009-08-17 13:31:43 -07007169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007170 if (!crtc->fb)
7171 continue;
7172
Chris Wilsonc65355b2013-06-06 16:53:41 -03007173 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7174 continue;
7175
7176 intel_increase_pllclock(crtc);
7177 if (ring && intel_fbc_enabled(dev))
7178 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07007179 }
Jesse Barnes652c3932009-08-17 13:31:43 -07007180}
7181
Jesse Barnes79e53942008-11-07 14:24:08 -08007182static void intel_crtc_destroy(struct drm_crtc *crtc)
7183{
7184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007185 struct drm_device *dev = crtc->dev;
7186 struct intel_unpin_work *work;
7187 unsigned long flags;
7188
7189 spin_lock_irqsave(&dev->event_lock, flags);
7190 work = intel_crtc->unpin_work;
7191 intel_crtc->unpin_work = NULL;
7192 spin_unlock_irqrestore(&dev->event_lock, flags);
7193
7194 if (work) {
7195 cancel_work_sync(&work->work);
7196 kfree(work);
7197 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007198
Mika Kuoppala40ccc722013-04-23 17:27:08 +03007199 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7200
Jesse Barnes79e53942008-11-07 14:24:08 -08007201 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007202
Jesse Barnes79e53942008-11-07 14:24:08 -08007203 kfree(intel_crtc);
7204}
7205
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007206static void intel_unpin_work_fn(struct work_struct *__work)
7207{
7208 struct intel_unpin_work *work =
7209 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007210 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007211
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007212 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01007213 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00007214 drm_gem_object_unreference(&work->pending_flip_obj->base);
7215 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00007216
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007217 intel_update_fbc(dev);
7218 mutex_unlock(&dev->struct_mutex);
7219
7220 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7221 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7222
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007223 kfree(work);
7224}
7225
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007226static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01007227 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007228{
7229 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007232 unsigned long flags;
7233
7234 /* Ignore early vblank irqs */
7235 if (intel_crtc == NULL)
7236 return;
7237
7238 spin_lock_irqsave(&dev->event_lock, flags);
7239 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00007240
7241 /* Ensure we don't miss a work->pending update ... */
7242 smp_rmb();
7243
7244 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007245 spin_unlock_irqrestore(&dev->event_lock, flags);
7246 return;
7247 }
7248
Chris Wilsone7d841c2012-12-03 11:36:30 +00007249 /* and that the unpin work is consistent wrt ->pending. */
7250 smp_rmb();
7251
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007252 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007253
Rob Clark45a066e2012-10-08 14:50:40 -05007254 if (work->event)
7255 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007256
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007257 drm_vblank_put(dev, intel_crtc->pipe);
7258
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007259 spin_unlock_irqrestore(&dev->event_lock, flags);
7260
Daniel Vetter2c10d572012-12-20 21:24:07 +01007261 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007262
7263 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07007264
7265 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007266}
7267
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007268void intel_finish_page_flip(struct drm_device *dev, int pipe)
7269{
7270 drm_i915_private_t *dev_priv = dev->dev_private;
7271 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7272
Mario Kleiner49b14a52010-12-09 07:00:07 +01007273 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007274}
7275
7276void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7277{
7278 drm_i915_private_t *dev_priv = dev->dev_private;
7279 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7280
Mario Kleiner49b14a52010-12-09 07:00:07 +01007281 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007282}
7283
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007284void intel_prepare_page_flip(struct drm_device *dev, int plane)
7285{
7286 drm_i915_private_t *dev_priv = dev->dev_private;
7287 struct intel_crtc *intel_crtc =
7288 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7289 unsigned long flags;
7290
Chris Wilsone7d841c2012-12-03 11:36:30 +00007291 /* NB: An MMIO update of the plane base pointer will also
7292 * generate a page-flip completion irq, i.e. every modeset
7293 * is also accompanied by a spurious intel_prepare_page_flip().
7294 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007295 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007296 if (intel_crtc->unpin_work)
7297 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007298 spin_unlock_irqrestore(&dev->event_lock, flags);
7299}
7300
Chris Wilsone7d841c2012-12-03 11:36:30 +00007301inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7302{
7303 /* Ensure that the work item is consistent when activating it ... */
7304 smp_wmb();
7305 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7306 /* and that it is marked active as soon as the irq could fire. */
7307 smp_wmb();
7308}
7309
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007310static int intel_gen2_queue_flip(struct drm_device *dev,
7311 struct drm_crtc *crtc,
7312 struct drm_framebuffer *fb,
7313 struct drm_i915_gem_object *obj)
7314{
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007317 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007318 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007319 int ret;
7320
Daniel Vetter6d90c952012-04-26 23:28:05 +02007321 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007322 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007323 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007324
Daniel Vetter6d90c952012-04-26 23:28:05 +02007325 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007326 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007327 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007328
7329 /* Can't queue multiple flips, so wait for the previous
7330 * one to finish before executing the next.
7331 */
7332 if (intel_crtc->plane)
7333 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7334 else
7335 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007336 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7337 intel_ring_emit(ring, MI_NOOP);
7338 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7339 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7340 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007341 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007342 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00007343
7344 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007345 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007346 return 0;
7347
7348err_unpin:
7349 intel_unpin_fb_obj(obj);
7350err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007351 return ret;
7352}
7353
7354static int intel_gen3_queue_flip(struct drm_device *dev,
7355 struct drm_crtc *crtc,
7356 struct drm_framebuffer *fb,
7357 struct drm_i915_gem_object *obj)
7358{
7359 struct drm_i915_private *dev_priv = dev->dev_private;
7360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007361 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007362 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007363 int ret;
7364
Daniel Vetter6d90c952012-04-26 23:28:05 +02007365 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007366 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007367 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007368
Daniel Vetter6d90c952012-04-26 23:28:05 +02007369 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007370 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007371 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007372
7373 if (intel_crtc->plane)
7374 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7375 else
7376 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007377 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7378 intel_ring_emit(ring, MI_NOOP);
7379 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7380 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7381 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007382 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007383 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007384
Chris Wilsone7d841c2012-12-03 11:36:30 +00007385 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007386 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007387 return 0;
7388
7389err_unpin:
7390 intel_unpin_fb_obj(obj);
7391err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007392 return ret;
7393}
7394
7395static int intel_gen4_queue_flip(struct drm_device *dev,
7396 struct drm_crtc *crtc,
7397 struct drm_framebuffer *fb,
7398 struct drm_i915_gem_object *obj)
7399{
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007403 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007404 int ret;
7405
Daniel Vetter6d90c952012-04-26 23:28:05 +02007406 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007407 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007408 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007409
Daniel Vetter6d90c952012-04-26 23:28:05 +02007410 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007411 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007412 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007413
7414 /* i965+ uses the linear or tiled offsets from the
7415 * Display Registers (which do not change across a page-flip)
7416 * so we need only reprogram the base address.
7417 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02007418 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7419 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7420 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007421 intel_ring_emit(ring,
7422 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7423 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007424
7425 /* XXX Enabling the panel-fitter across page-flip is so far
7426 * untested on non-native modes, so ignore it for now.
7427 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7428 */
7429 pf = 0;
7430 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007431 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007432
7433 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007434 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007435 return 0;
7436
7437err_unpin:
7438 intel_unpin_fb_obj(obj);
7439err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007440 return ret;
7441}
7442
7443static int intel_gen6_queue_flip(struct drm_device *dev,
7444 struct drm_crtc *crtc,
7445 struct drm_framebuffer *fb,
7446 struct drm_i915_gem_object *obj)
7447{
7448 struct drm_i915_private *dev_priv = dev->dev_private;
7449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007450 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007451 uint32_t pf, pipesrc;
7452 int ret;
7453
Daniel Vetter6d90c952012-04-26 23:28:05 +02007454 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007455 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007456 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007457
Daniel Vetter6d90c952012-04-26 23:28:05 +02007458 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007459 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007460 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007461
Daniel Vetter6d90c952012-04-26 23:28:05 +02007462 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7463 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7464 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007465 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007466
Chris Wilson99d9acd2012-04-17 20:37:00 +01007467 /* Contrary to the suggestions in the documentation,
7468 * "Enable Panel Fitter" does not seem to be required when page
7469 * flipping with a non-native mode, and worse causes a normal
7470 * modeset to fail.
7471 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7472 */
7473 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007474 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007475 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007476
7477 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007478 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007479 return 0;
7480
7481err_unpin:
7482 intel_unpin_fb_obj(obj);
7483err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007484 return ret;
7485}
7486
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007487/*
7488 * On gen7 we currently use the blit ring because (in early silicon at least)
7489 * the render ring doesn't give us interrpts for page flip completion, which
7490 * means clients will hang after the first flip is queued. Fortunately the
7491 * blit ring generates interrupts properly, so use it instead.
7492 */
7493static int intel_gen7_queue_flip(struct drm_device *dev,
7494 struct drm_crtc *crtc,
7495 struct drm_framebuffer *fb,
7496 struct drm_i915_gem_object *obj)
7497{
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7500 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007501 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007502 int ret;
7503
7504 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7505 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007506 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007507
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007508 switch(intel_crtc->plane) {
7509 case PLANE_A:
7510 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7511 break;
7512 case PLANE_B:
7513 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7514 break;
7515 case PLANE_C:
7516 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7517 break;
7518 default:
7519 WARN_ONCE(1, "unknown plane in flip command\n");
7520 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03007521 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007522 }
7523
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007524 ret = intel_ring_begin(ring, 4);
7525 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007526 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007527
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007528 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007529 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02007530 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007531 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00007532
7533 intel_mark_page_flip_active(intel_crtc);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007534 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007535 return 0;
7536
7537err_unpin:
7538 intel_unpin_fb_obj(obj);
7539err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007540 return ret;
7541}
7542
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007543static int intel_default_queue_flip(struct drm_device *dev,
7544 struct drm_crtc *crtc,
7545 struct drm_framebuffer *fb,
7546 struct drm_i915_gem_object *obj)
7547{
7548 return -ENODEV;
7549}
7550
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007551static int intel_crtc_page_flip(struct drm_crtc *crtc,
7552 struct drm_framebuffer *fb,
7553 struct drm_pending_vblank_event *event)
7554{
7555 struct drm_device *dev = crtc->dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007557 struct drm_framebuffer *old_fb = crtc->fb;
7558 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7560 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007561 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007562 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007563
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03007564 /* Can't change pixel format via MI display flips. */
7565 if (fb->pixel_format != crtc->fb->pixel_format)
7566 return -EINVAL;
7567
7568 /*
7569 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7570 * Note that pitch changes could also affect these register.
7571 */
7572 if (INTEL_INFO(dev)->gen > 3 &&
7573 (fb->offsets[0] != crtc->fb->offsets[0] ||
7574 fb->pitches[0] != crtc->fb->pitches[0]))
7575 return -EINVAL;
7576
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007577 work = kzalloc(sizeof *work, GFP_KERNEL);
7578 if (work == NULL)
7579 return -ENOMEM;
7580
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007581 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007582 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007583 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007584 INIT_WORK(&work->work, intel_unpin_work_fn);
7585
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007586 ret = drm_vblank_get(dev, intel_crtc->pipe);
7587 if (ret)
7588 goto free_work;
7589
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007590 /* We borrow the event spin lock for protecting unpin_work */
7591 spin_lock_irqsave(&dev->event_lock, flags);
7592 if (intel_crtc->unpin_work) {
7593 spin_unlock_irqrestore(&dev->event_lock, flags);
7594 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007595 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01007596
7597 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007598 return -EBUSY;
7599 }
7600 intel_crtc->unpin_work = work;
7601 spin_unlock_irqrestore(&dev->event_lock, flags);
7602
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007603 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7604 flush_workqueue(dev_priv->wq);
7605
Chris Wilson79158102012-05-23 11:13:58 +01007606 ret = i915_mutex_lock_interruptible(dev);
7607 if (ret)
7608 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007609
Jesse Barnes75dfca82010-02-10 15:09:44 -08007610 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007611 drm_gem_object_reference(&work->old_fb_obj->base);
7612 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007613
7614 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007615
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007616 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007617
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007618 work->enable_stall_check = true;
7619
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007620 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02007621 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007622
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007623 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7624 if (ret)
7625 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007626
Chris Wilson7782de32011-07-08 12:22:41 +01007627 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03007628 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007629 mutex_unlock(&dev->struct_mutex);
7630
Jesse Barnese5510fa2010-07-01 16:48:37 -07007631 trace_i915_flip_request(intel_crtc->plane, obj);
7632
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007633 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007634
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007635cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007636 atomic_dec(&intel_crtc->unpin_work_count);
Ville Syrjälä4a35f832013-02-22 16:53:38 +02007637 crtc->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007638 drm_gem_object_unreference(&work->old_fb_obj->base);
7639 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007640 mutex_unlock(&dev->struct_mutex);
7641
Chris Wilson79158102012-05-23 11:13:58 +01007642cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01007643 spin_lock_irqsave(&dev->event_lock, flags);
7644 intel_crtc->unpin_work = NULL;
7645 spin_unlock_irqrestore(&dev->event_lock, flags);
7646
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007647 drm_vblank_put(dev, intel_crtc->pipe);
7648free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01007649 kfree(work);
7650
7651 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007652}
7653
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007654static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007655 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7656 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007657};
7658
Daniel Vetter50f56112012-07-02 09:35:43 +02007659static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7660 struct drm_crtc *crtc)
7661{
7662 struct drm_device *dev;
7663 struct drm_crtc *tmp;
7664 int crtc_mask = 1;
7665
7666 WARN(!crtc, "checking null crtc?\n");
7667
7668 dev = crtc->dev;
7669
7670 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7671 if (tmp == crtc)
7672 break;
7673 crtc_mask <<= 1;
7674 }
7675
7676 if (encoder->possible_crtcs & crtc_mask)
7677 return true;
7678 return false;
7679}
7680
Daniel Vetter9a935852012-07-05 22:34:27 +02007681/**
7682 * intel_modeset_update_staged_output_state
7683 *
7684 * Updates the staged output configuration state, e.g. after we've read out the
7685 * current hw state.
7686 */
7687static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7688{
7689 struct intel_encoder *encoder;
7690 struct intel_connector *connector;
7691
7692 list_for_each_entry(connector, &dev->mode_config.connector_list,
7693 base.head) {
7694 connector->new_encoder =
7695 to_intel_encoder(connector->base.encoder);
7696 }
7697
7698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7699 base.head) {
7700 encoder->new_crtc =
7701 to_intel_crtc(encoder->base.crtc);
7702 }
7703}
7704
7705/**
7706 * intel_modeset_commit_output_state
7707 *
7708 * This function copies the stage display pipe configuration to the real one.
7709 */
7710static void intel_modeset_commit_output_state(struct drm_device *dev)
7711{
7712 struct intel_encoder *encoder;
7713 struct intel_connector *connector;
7714
7715 list_for_each_entry(connector, &dev->mode_config.connector_list,
7716 base.head) {
7717 connector->base.encoder = &connector->new_encoder->base;
7718 }
7719
7720 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7721 base.head) {
7722 encoder->base.crtc = &encoder->new_crtc->base;
7723 }
7724}
7725
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007726static void
7727connected_sink_compute_bpp(struct intel_connector * connector,
7728 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007729{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007730 int bpp = pipe_config->pipe_bpp;
7731
7732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7733 connector->base.base.id,
7734 drm_get_connector_name(&connector->base));
7735
7736 /* Don't use an invalid EDID bpc value */
7737 if (connector->base.display_info.bpc &&
7738 connector->base.display_info.bpc * 3 < bpp) {
7739 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7740 bpp, connector->base.display_info.bpc*3);
7741 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7742 }
7743
7744 /* Clamp bpp to 8 on screens without EDID 1.4 */
7745 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7746 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7747 bpp);
7748 pipe_config->pipe_bpp = 24;
7749 }
7750}
7751
7752static int
7753compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7754 struct drm_framebuffer *fb,
7755 struct intel_crtc_config *pipe_config)
7756{
7757 struct drm_device *dev = crtc->base.dev;
7758 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007759 int bpp;
7760
Daniel Vetterd42264b2013-03-28 16:38:08 +01007761 switch (fb->pixel_format) {
7762 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007763 bpp = 8*3; /* since we go through a colormap */
7764 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007765 case DRM_FORMAT_XRGB1555:
7766 case DRM_FORMAT_ARGB1555:
7767 /* checked in intel_framebuffer_init already */
7768 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7769 return -EINVAL;
7770 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007771 bpp = 6*3; /* min is 18bpp */
7772 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007773 case DRM_FORMAT_XBGR8888:
7774 case DRM_FORMAT_ABGR8888:
7775 /* checked in intel_framebuffer_init already */
7776 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7777 return -EINVAL;
7778 case DRM_FORMAT_XRGB8888:
7779 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007780 bpp = 8*3;
7781 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01007782 case DRM_FORMAT_XRGB2101010:
7783 case DRM_FORMAT_ARGB2101010:
7784 case DRM_FORMAT_XBGR2101010:
7785 case DRM_FORMAT_ABGR2101010:
7786 /* checked in intel_framebuffer_init already */
7787 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01007788 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007789 bpp = 10*3;
7790 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01007791 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007792 default:
7793 DRM_DEBUG_KMS("unsupported depth\n");
7794 return -EINVAL;
7795 }
7796
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007797 pipe_config->pipe_bpp = bpp;
7798
7799 /* Clamp display bpp to EDID value */
7800 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007801 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02007802 if (!connector->new_encoder ||
7803 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007804 continue;
7805
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007806 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007807 }
7808
7809 return bpp;
7810}
7811
Daniel Vetterc0b03412013-05-28 12:05:54 +02007812static void intel_dump_pipe_config(struct intel_crtc *crtc,
7813 struct intel_crtc_config *pipe_config,
7814 const char *context)
7815{
7816 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7817 context, pipe_name(crtc->pipe));
7818
7819 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7820 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7821 pipe_config->pipe_bpp, pipe_config->dither);
7822 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7823 pipe_config->has_pch_encoder,
7824 pipe_config->fdi_lanes,
7825 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7826 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7827 pipe_config->fdi_m_n.tu);
7828 DRM_DEBUG_KMS("requested mode:\n");
7829 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7830 DRM_DEBUG_KMS("adjusted mode:\n");
7831 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7832 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7833 pipe_config->gmch_pfit.control,
7834 pipe_config->gmch_pfit.pgm_ratios,
7835 pipe_config->gmch_pfit.lvds_border_bits);
7836 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7837 pipe_config->pch_pfit.pos,
7838 pipe_config->pch_pfit.size);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03007839 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Daniel Vetterc0b03412013-05-28 12:05:54 +02007840}
7841
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02007842static bool check_encoder_cloning(struct drm_crtc *crtc)
7843{
7844 int num_encoders = 0;
7845 bool uncloneable_encoders = false;
7846 struct intel_encoder *encoder;
7847
7848 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7849 base.head) {
7850 if (&encoder->new_crtc->base != crtc)
7851 continue;
7852
7853 num_encoders++;
7854 if (!encoder->cloneable)
7855 uncloneable_encoders = true;
7856 }
7857
7858 return !(num_encoders > 1 && uncloneable_encoders);
7859}
7860
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007861static struct intel_crtc_config *
7862intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007863 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007864 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02007865{
7866 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02007867 struct drm_encoder_helper_funcs *encoder_funcs;
7868 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007869 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01007870 int plane_bpp, ret = -EINVAL;
7871 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02007872
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02007873 if (!check_encoder_cloning(crtc)) {
7874 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7875 return ERR_PTR(-EINVAL);
7876 }
7877
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007878 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7879 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02007880 return ERR_PTR(-ENOMEM);
7881
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007882 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7883 drm_mode_copy(&pipe_config->requested_mode, mode);
Daniel Vettereccb1402013-05-22 00:50:22 +02007884 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02007885 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007886
Daniel Vetter050f7ae2013-06-02 13:26:23 +02007887 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7888 * plane pixel format and any sink constraints into account. Returns the
7889 * source plane bpp so that dithering can be selected on mismatches
7890 * after encoders and crtc also have had their say. */
7891 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7892 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007893 if (plane_bpp < 0)
7894 goto fail;
7895
Daniel Vettere29c22c2013-02-21 00:00:16 +01007896encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02007897 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02007898 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02007899 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02007900
Daniel Vetter7758a112012-07-08 19:40:39 +02007901 /* Pass our mode to the connectors and the CRTC to give them a chance to
7902 * adjust it according to limitations or connector properties, and also
7903 * a chance to reject the mode entirely.
7904 */
7905 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7906 base.head) {
7907
7908 if (&encoder->new_crtc->base != crtc)
7909 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01007910
7911 if (encoder->compute_config) {
7912 if (!(encoder->compute_config(encoder, pipe_config))) {
7913 DRM_DEBUG_KMS("Encoder config failure\n");
7914 goto fail;
7915 }
7916
7917 continue;
7918 }
7919
Daniel Vetter7758a112012-07-08 19:40:39 +02007920 encoder_funcs = encoder->base.helper_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007921 if (!(encoder_funcs->mode_fixup(&encoder->base,
7922 &pipe_config->requested_mode,
7923 &pipe_config->adjusted_mode))) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007924 DRM_DEBUG_KMS("Encoder fixup failed\n");
7925 goto fail;
7926 }
7927 }
7928
Daniel Vetterff9a6752013-06-01 17:16:21 +02007929 /* Set default port clock if not overwritten by the encoder. Needs to be
7930 * done afterwards in case the encoder adjusts the mode. */
7931 if (!pipe_config->port_clock)
7932 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7933
Daniel Vettera43f6e02013-06-07 23:10:32 +02007934 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01007935 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02007936 DRM_DEBUG_KMS("CRTC fixup failed\n");
7937 goto fail;
7938 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01007939
7940 if (ret == RETRY) {
7941 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7942 ret = -EINVAL;
7943 goto fail;
7944 }
7945
7946 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7947 retry = false;
7948 goto encoder_retry;
7949 }
7950
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01007951 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7952 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7953 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7954
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007955 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02007956fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007957 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01007958 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02007959}
7960
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007961/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7962 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7963static void
7964intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7965 unsigned *prepare_pipes, unsigned *disable_pipes)
7966{
7967 struct intel_crtc *intel_crtc;
7968 struct drm_device *dev = crtc->dev;
7969 struct intel_encoder *encoder;
7970 struct intel_connector *connector;
7971 struct drm_crtc *tmp_crtc;
7972
7973 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7974
7975 /* Check which crtcs have changed outputs connected to them, these need
7976 * to be part of the prepare_pipes mask. We don't (yet) support global
7977 * modeset across multiple crtcs, so modeset_pipes will only have one
7978 * bit set at most. */
7979 list_for_each_entry(connector, &dev->mode_config.connector_list,
7980 base.head) {
7981 if (connector->base.encoder == &connector->new_encoder->base)
7982 continue;
7983
7984 if (connector->base.encoder) {
7985 tmp_crtc = connector->base.encoder->crtc;
7986
7987 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7988 }
7989
7990 if (connector->new_encoder)
7991 *prepare_pipes |=
7992 1 << connector->new_encoder->new_crtc->pipe;
7993 }
7994
7995 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7996 base.head) {
7997 if (encoder->base.crtc == &encoder->new_crtc->base)
7998 continue;
7999
8000 if (encoder->base.crtc) {
8001 tmp_crtc = encoder->base.crtc;
8002
8003 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8004 }
8005
8006 if (encoder->new_crtc)
8007 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8008 }
8009
8010 /* Check for any pipes that will be fully disabled ... */
8011 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8012 base.head) {
8013 bool used = false;
8014
8015 /* Don't try to disable disabled crtcs. */
8016 if (!intel_crtc->base.enabled)
8017 continue;
8018
8019 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8020 base.head) {
8021 if (encoder->new_crtc == intel_crtc)
8022 used = true;
8023 }
8024
8025 if (!used)
8026 *disable_pipes |= 1 << intel_crtc->pipe;
8027 }
8028
8029
8030 /* set_mode is also used to update properties on life display pipes. */
8031 intel_crtc = to_intel_crtc(crtc);
8032 if (crtc->enabled)
8033 *prepare_pipes |= 1 << intel_crtc->pipe;
8034
Daniel Vetterb6c51642013-04-12 18:48:43 +02008035 /*
8036 * For simplicity do a full modeset on any pipe where the output routing
8037 * changed. We could be more clever, but that would require us to be
8038 * more careful with calling the relevant encoder->mode_set functions.
8039 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02008040 if (*prepare_pipes)
8041 *modeset_pipes = *prepare_pipes;
8042
8043 /* ... and mask these out. */
8044 *modeset_pipes &= ~(*disable_pipes);
8045 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02008046
8047 /*
8048 * HACK: We don't (yet) fully support global modesets. intel_set_config
8049 * obies this rule, but the modeset restore mode of
8050 * intel_modeset_setup_hw_state does not.
8051 */
8052 *modeset_pipes &= 1 << intel_crtc->pipe;
8053 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02008054
8055 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8056 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02008057}
8058
Daniel Vetterea9d7582012-07-10 10:42:52 +02008059static bool intel_crtc_in_use(struct drm_crtc *crtc)
8060{
8061 struct drm_encoder *encoder;
8062 struct drm_device *dev = crtc->dev;
8063
8064 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8065 if (encoder->crtc == crtc)
8066 return true;
8067
8068 return false;
8069}
8070
8071static void
8072intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8073{
8074 struct intel_encoder *intel_encoder;
8075 struct intel_crtc *intel_crtc;
8076 struct drm_connector *connector;
8077
8078 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8079 base.head) {
8080 if (!intel_encoder->base.crtc)
8081 continue;
8082
8083 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8084
8085 if (prepare_pipes & (1 << intel_crtc->pipe))
8086 intel_encoder->connectors_active = false;
8087 }
8088
8089 intel_modeset_commit_output_state(dev);
8090
8091 /* Update computed state. */
8092 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8093 base.head) {
8094 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8095 }
8096
8097 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8098 if (!connector->encoder || !connector->encoder->crtc)
8099 continue;
8100
8101 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8102
8103 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02008104 struct drm_property *dpms_property =
8105 dev->mode_config.dpms_property;
8106
Daniel Vetterea9d7582012-07-10 10:42:52 +02008107 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05008108 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02008109 dpms_property,
8110 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02008111
8112 intel_encoder = to_intel_encoder(connector->encoder);
8113 intel_encoder->connectors_active = true;
8114 }
8115 }
8116
8117}
8118
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008119static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8120 struct intel_crtc_config *new)
8121{
8122 int clock1, clock2, diff;
8123
8124 clock1 = cur->adjusted_mode.clock;
8125 clock2 = new->adjusted_mode.clock;
8126
8127 if (clock1 == clock2)
8128 return true;
8129
8130 if (!clock1 || !clock2)
8131 return false;
8132
8133 diff = abs(clock1 - clock2);
8134
8135 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8136 return true;
8137
8138 return false;
8139}
8140
Daniel Vetter25c5b262012-07-08 22:08:04 +02008141#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8142 list_for_each_entry((intel_crtc), \
8143 &(dev)->mode_config.crtc_list, \
8144 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02008145 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02008146
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008147static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008148intel_pipe_config_compare(struct drm_device *dev,
8149 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008150 struct intel_crtc_config *pipe_config)
8151{
Daniel Vetter66e985c2013-06-05 13:34:20 +02008152#define PIPE_CONF_CHECK_X(name) \
8153 if (current_config->name != pipe_config->name) { \
8154 DRM_ERROR("mismatch in " #name " " \
8155 "(expected 0x%08x, found 0x%08x)\n", \
8156 current_config->name, \
8157 pipe_config->name); \
8158 return false; \
8159 }
8160
Daniel Vetter08a24032013-04-19 11:25:34 +02008161#define PIPE_CONF_CHECK_I(name) \
8162 if (current_config->name != pipe_config->name) { \
8163 DRM_ERROR("mismatch in " #name " " \
8164 "(expected %i, found %i)\n", \
8165 current_config->name, \
8166 pipe_config->name); \
8167 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01008168 }
8169
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008170#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8171 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07008172 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008173 "(expected %i, found %i)\n", \
8174 current_config->name & (mask), \
8175 pipe_config->name & (mask)); \
8176 return false; \
8177 }
8178
Daniel Vetterbb760062013-06-06 14:55:52 +02008179#define PIPE_CONF_QUIRK(quirk) \
8180 ((current_config->quirks | pipe_config->quirks) & (quirk))
8181
Daniel Vettereccb1402013-05-22 00:50:22 +02008182 PIPE_CONF_CHECK_I(cpu_transcoder);
8183
Daniel Vetter08a24032013-04-19 11:25:34 +02008184 PIPE_CONF_CHECK_I(has_pch_encoder);
8185 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02008186 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8187 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8188 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8189 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8190 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02008191
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008192 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8193 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8194 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8195 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8196 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8197 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8198
8199 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8200 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8201 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8202 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8203 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8204 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8205
Daniel Vetterc93f54c2013-06-27 19:47:19 +02008206 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6c49f242013-06-06 12:45:25 +02008207
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008208 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8209 DRM_MODE_FLAG_INTERLACE);
8210
Daniel Vetterbb760062013-06-06 14:55:52 +02008211 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8212 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8213 DRM_MODE_FLAG_PHSYNC);
8214 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8215 DRM_MODE_FLAG_NHSYNC);
8216 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8217 DRM_MODE_FLAG_PVSYNC);
8218 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8219 DRM_MODE_FLAG_NVSYNC);
8220 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07008221
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008222 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8223 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8224
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008225 PIPE_CONF_CHECK_I(gmch_pfit.control);
8226 /* pfit ratios are autocomputed by the hw on gen4+ */
8227 if (INTEL_INFO(dev)->gen < 4)
8228 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8229 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8230 PIPE_CONF_CHECK_I(pch_pfit.pos);
8231 PIPE_CONF_CHECK_I(pch_pfit.size);
8232
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008233 PIPE_CONF_CHECK_I(ips_enabled);
8234
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008235 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008236 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008237 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008238 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8239 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008240
Daniel Vetter66e985c2013-06-05 13:34:20 +02008241#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +02008242#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008243#undef PIPE_CONF_CHECK_FLAGS
Daniel Vetterbb760062013-06-06 14:55:52 +02008244#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +02008245
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008246 if (!IS_HASWELL(dev)) {
8247 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
Jesse Barnes6f024882013-07-01 10:19:09 -07008248 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008249 current_config->adjusted_mode.clock,
8250 pipe_config->adjusted_mode.clock);
8251 return false;
8252 }
8253 }
8254
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008255 return true;
8256}
8257
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008258static void
8259check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008260{
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008261 struct intel_connector *connector;
8262
8263 list_for_each_entry(connector, &dev->mode_config.connector_list,
8264 base.head) {
8265 /* This also checks the encoder/connector hw state with the
8266 * ->get_hw_state callbacks. */
8267 intel_connector_check_state(connector);
8268
8269 WARN(&connector->new_encoder->base != connector->base.encoder,
8270 "connector's staged encoder doesn't match current encoder\n");
8271 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008272}
8273
8274static void
8275check_encoder_state(struct drm_device *dev)
8276{
8277 struct intel_encoder *encoder;
8278 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008279
8280 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8281 base.head) {
8282 bool enabled = false;
8283 bool active = false;
8284 enum pipe pipe, tracked_pipe;
8285
8286 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8287 encoder->base.base.id,
8288 drm_get_encoder_name(&encoder->base));
8289
8290 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8291 "encoder's stage crtc doesn't match current crtc\n");
8292 WARN(encoder->connectors_active && !encoder->base.crtc,
8293 "encoder's active_connectors set, but no crtc\n");
8294
8295 list_for_each_entry(connector, &dev->mode_config.connector_list,
8296 base.head) {
8297 if (connector->base.encoder != &encoder->base)
8298 continue;
8299 enabled = true;
8300 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8301 active = true;
8302 }
8303 WARN(!!encoder->base.crtc != enabled,
8304 "encoder's enabled state mismatch "
8305 "(expected %i, found %i)\n",
8306 !!encoder->base.crtc, enabled);
8307 WARN(active && !encoder->base.crtc,
8308 "active encoder with no crtc\n");
8309
8310 WARN(encoder->connectors_active != active,
8311 "encoder's computed active state doesn't match tracked active state "
8312 "(expected %i, found %i)\n", active, encoder->connectors_active);
8313
8314 active = encoder->get_hw_state(encoder, &pipe);
8315 WARN(active != encoder->connectors_active,
8316 "encoder's hw state doesn't match sw tracking "
8317 "(expected %i, found %i)\n",
8318 encoder->connectors_active, active);
8319
8320 if (!encoder->base.crtc)
8321 continue;
8322
8323 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8324 WARN(active && pipe != tracked_pipe,
8325 "active encoder's pipe doesn't match"
8326 "(expected %i, found %i)\n",
8327 tracked_pipe, pipe);
8328
8329 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008330}
8331
8332static void
8333check_crtc_state(struct drm_device *dev)
8334{
8335 drm_i915_private_t *dev_priv = dev->dev_private;
8336 struct intel_crtc *crtc;
8337 struct intel_encoder *encoder;
8338 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008339
8340 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8341 base.head) {
8342 bool enabled = false;
8343 bool active = false;
8344
Jesse Barnes045ac3b2013-05-14 17:08:26 -07008345 memset(&pipe_config, 0, sizeof(pipe_config));
8346
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008347 DRM_DEBUG_KMS("[CRTC:%d]\n",
8348 crtc->base.base.id);
8349
8350 WARN(crtc->active && !crtc->base.enabled,
8351 "active crtc, but not enabled in sw tracking\n");
8352
8353 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8354 base.head) {
8355 if (encoder->base.crtc != &crtc->base)
8356 continue;
8357 enabled = true;
8358 if (encoder->connectors_active)
8359 active = true;
8360 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008361
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008362 WARN(active != crtc->active,
8363 "crtc's computed active state doesn't match tracked active state "
8364 "(expected %i, found %i)\n", active, crtc->active);
8365 WARN(enabled != crtc->base.enabled,
8366 "crtc's computed enabled state doesn't match tracked enabled state "
8367 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8368
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008369 active = dev_priv->display.get_pipe_config(crtc,
8370 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +02008371
8372 /* hw state is inconsistent with the pipe A quirk */
8373 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8374 active = crtc->active;
8375
Daniel Vetter6c49f242013-06-06 12:45:25 +02008376 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8377 base.head) {
8378 if (encoder->base.crtc != &crtc->base)
8379 continue;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008380 if (encoder->get_config &&
8381 dev_priv->display.get_clock) {
Daniel Vetter6c49f242013-06-06 12:45:25 +02008382 encoder->get_config(encoder, &pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008383 dev_priv->display.get_clock(crtc,
8384 &pipe_config);
8385 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008386 }
8387
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008388 WARN(crtc->active != active,
8389 "crtc active state doesn't match with hw state "
8390 "(expected %i, found %i)\n", crtc->active, active);
8391
Daniel Vetterc0b03412013-05-28 12:05:54 +02008392 if (active &&
8393 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8394 WARN(1, "pipe state doesn't match!\n");
8395 intel_dump_pipe_config(crtc, &pipe_config,
8396 "[hw state]");
8397 intel_dump_pipe_config(crtc, &crtc->config,
8398 "[sw state]");
8399 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008400 }
8401}
8402
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008403static void
8404check_shared_dpll_state(struct drm_device *dev)
8405{
8406 drm_i915_private_t *dev_priv = dev->dev_private;
8407 struct intel_crtc *crtc;
8408 struct intel_dpll_hw_state dpll_hw_state;
8409 int i;
Daniel Vetter53589012013-06-05 13:34:16 +02008410
8411 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8412 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8413 int enabled_crtcs = 0, active_crtcs = 0;
8414 bool active;
8415
8416 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8417
8418 DRM_DEBUG_KMS("%s\n", pll->name);
8419
8420 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8421
8422 WARN(pll->active > pll->refcount,
8423 "more active pll users than references: %i vs %i\n",
8424 pll->active, pll->refcount);
8425 WARN(pll->active && !pll->on,
8426 "pll in active use but not on in sw tracking\n");
8427 WARN(pll->on != active,
8428 "pll on state mismatch (expected %i, found %i)\n",
8429 pll->on, active);
8430
8431 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8432 base.head) {
8433 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8434 enabled_crtcs++;
8435 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8436 active_crtcs++;
8437 }
8438 WARN(pll->active != active_crtcs,
8439 "pll active crtcs mismatch (expected %i, found %i)\n",
8440 pll->active, active_crtcs);
8441 WARN(pll->refcount != enabled_crtcs,
8442 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8443 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +02008444
8445 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8446 sizeof(dpll_hw_state)),
8447 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +02008448 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008449}
8450
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02008451void
8452intel_modeset_check_state(struct drm_device *dev)
8453{
8454 check_connector_state(dev);
8455 check_encoder_state(dev);
8456 check_crtc_state(dev);
8457 check_shared_dpll_state(dev);
8458}
8459
Daniel Vetterf30da182013-04-11 20:22:50 +02008460static int __intel_set_mode(struct drm_crtc *crtc,
8461 struct drm_display_mode *mode,
8462 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02008463{
8464 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02008465 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008466 struct drm_display_mode *saved_mode, *saved_hwmode;
8467 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +02008468 struct intel_crtc *intel_crtc;
8469 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008470 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +02008471
Tim Gardner3ac18232012-12-07 07:54:26 -07008472 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008473 if (!saved_mode)
8474 return -ENOMEM;
Tim Gardner3ac18232012-12-07 07:54:26 -07008475 saved_hwmode = saved_mode + 1;
Daniel Vettera6778b32012-07-02 09:56:42 +02008476
Daniel Vettere2e1ed42012-07-08 21:14:38 +02008477 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02008478 &prepare_pipes, &disable_pipes);
8479
Tim Gardner3ac18232012-12-07 07:54:26 -07008480 *saved_hwmode = crtc->hwmode;
8481 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008482
Daniel Vetter25c5b262012-07-08 22:08:04 +02008483 /* Hack: Because we don't (yet) support global modeset on multiple
8484 * crtcs, we don't keep track of the new mode for more than one crtc.
8485 * Hence simply check whether any bit is set in modeset_pipes in all the
8486 * pieces of code that are not yet converted to deal with mutliple crtcs
8487 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008488 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008489 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008490 if (IS_ERR(pipe_config)) {
8491 ret = PTR_ERR(pipe_config);
8492 pipe_config = NULL;
8493
Tim Gardner3ac18232012-12-07 07:54:26 -07008494 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +02008495 }
Daniel Vetterc0b03412013-05-28 12:05:54 +02008496 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8497 "[modeset]");
Daniel Vettera6778b32012-07-02 09:56:42 +02008498 }
8499
Daniel Vetter460da9162013-03-27 00:44:51 +01008500 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8501 intel_crtc_disable(&intel_crtc->base);
8502
Daniel Vetterea9d7582012-07-10 10:42:52 +02008503 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8504 if (intel_crtc->base.enabled)
8505 dev_priv->display.crtc_disable(&intel_crtc->base);
8506 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008507
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02008508 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8509 * to set it here already despite that we pass it down the callchain.
8510 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008511 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +02008512 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008513 /* mode_set/enable/disable functions rely on a correct pipe
8514 * config. */
8515 to_intel_crtc(crtc)->config = *pipe_config;
8516 }
Daniel Vetter7758a112012-07-08 19:40:39 +02008517
Daniel Vetterea9d7582012-07-10 10:42:52 +02008518 /* Only after disabling all output pipelines that will be changed can we
8519 * update the the output configuration. */
8520 intel_modeset_update_state(dev, prepare_pipes);
8521
Daniel Vetter47fab732012-10-26 10:58:18 +02008522 if (dev_priv->display.modeset_global_resources)
8523 dev_priv->display.modeset_global_resources(dev);
8524
Daniel Vettera6778b32012-07-02 09:56:42 +02008525 /* Set up the DPLL and any encoders state that needs to adjust or depend
8526 * on the DPLL.
8527 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008528 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008529 ret = intel_crtc_mode_set(&intel_crtc->base,
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008530 x, y, fb);
8531 if (ret)
8532 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02008533 }
8534
8535 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02008536 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8537 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02008538
Daniel Vetter25c5b262012-07-08 22:08:04 +02008539 if (modeset_pipes) {
8540 /* Store real post-adjustment hardware mode. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008541 crtc->hwmode = pipe_config->adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008542
Daniel Vetter25c5b262012-07-08 22:08:04 +02008543 /* Calculate and store various constants which
8544 * are later needed by vblank and swap-completion
8545 * timestamping. They are derived from true hwmode.
8546 */
8547 drm_calc_timestamping_constants(crtc);
8548 }
Daniel Vettera6778b32012-07-02 09:56:42 +02008549
8550 /* FIXME: add subpixel order */
8551done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008552 if (ret && crtc->enabled) {
Tim Gardner3ac18232012-12-07 07:54:26 -07008553 crtc->hwmode = *saved_hwmode;
8554 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02008555 }
8556
Tim Gardner3ac18232012-12-07 07:54:26 -07008557out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008558 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -07008559 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +02008560 return ret;
8561}
8562
Daniel Vetterf30da182013-04-11 20:22:50 +02008563int intel_set_mode(struct drm_crtc *crtc,
8564 struct drm_display_mode *mode,
8565 int x, int y, struct drm_framebuffer *fb)
8566{
8567 int ret;
8568
8569 ret = __intel_set_mode(crtc, mode, x, y, fb);
8570
8571 if (ret == 0)
8572 intel_modeset_check_state(crtc->dev);
8573
8574 return ret;
8575}
8576
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008577void intel_crtc_restore_mode(struct drm_crtc *crtc)
8578{
8579 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8580}
8581
Daniel Vetter25c5b262012-07-08 22:08:04 +02008582#undef for_each_intel_crtc_masked
8583
Daniel Vetterd9e55602012-07-04 22:16:09 +02008584static void intel_set_config_free(struct intel_set_config *config)
8585{
8586 if (!config)
8587 return;
8588
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008589 kfree(config->save_connector_encoders);
8590 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02008591 kfree(config);
8592}
8593
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008594static int intel_set_config_save_state(struct drm_device *dev,
8595 struct intel_set_config *config)
8596{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008597 struct drm_encoder *encoder;
8598 struct drm_connector *connector;
8599 int count;
8600
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008601 config->save_encoder_crtcs =
8602 kcalloc(dev->mode_config.num_encoder,
8603 sizeof(struct drm_crtc *), GFP_KERNEL);
8604 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008605 return -ENOMEM;
8606
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008607 config->save_connector_encoders =
8608 kcalloc(dev->mode_config.num_connector,
8609 sizeof(struct drm_encoder *), GFP_KERNEL);
8610 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008611 return -ENOMEM;
8612
8613 /* Copy data. Note that driver private data is not affected.
8614 * Should anything bad happen only the expected state is
8615 * restored, not the drivers personal bookkeeping.
8616 */
8617 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008618 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008619 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008620 }
8621
8622 count = 0;
8623 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008624 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008625 }
8626
8627 return 0;
8628}
8629
8630static void intel_set_config_restore_state(struct drm_device *dev,
8631 struct intel_set_config *config)
8632{
Daniel Vetter9a935852012-07-05 22:34:27 +02008633 struct intel_encoder *encoder;
8634 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008635 int count;
8636
8637 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008638 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8639 encoder->new_crtc =
8640 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008641 }
8642
8643 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008644 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8645 connector->new_encoder =
8646 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008647 }
8648}
8649
Imre Deake3de42b2013-05-03 19:44:07 +02008650static bool
8651is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8652 int num_connectors)
8653{
8654 int i;
8655
8656 for (i = 0; i < num_connectors; i++)
8657 if (connectors[i].encoder &&
8658 connectors[i].encoder->crtc == crtc &&
8659 connectors[i].dpms != DRM_MODE_DPMS_ON)
8660 return true;
8661
8662 return false;
8663}
8664
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008665static void
8666intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8667 struct intel_set_config *config)
8668{
8669
8670 /* We should be able to check here if the fb has the same properties
8671 * and then just flip_or_move it */
Imre Deake3de42b2013-05-03 19:44:07 +02008672 if (set->connectors != NULL &&
8673 is_crtc_connector_off(set->crtc, *set->connectors,
8674 set->num_connectors)) {
8675 config->mode_changed = true;
8676 } else if (set->crtc->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008677 /* If we have no fb then treat it as a full mode set */
8678 if (set->crtc->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +03008679 struct intel_crtc *intel_crtc =
8680 to_intel_crtc(set->crtc);
8681
8682 if (intel_crtc->active && i915_fastboot) {
8683 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8684 config->fb_changed = true;
8685 } else {
8686 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8687 config->mode_changed = true;
8688 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008689 } else if (set->fb == NULL) {
8690 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +01008691 } else if (set->fb->pixel_format !=
8692 set->crtc->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008693 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02008694 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008695 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02008696 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008697 }
8698
Daniel Vetter835c5872012-07-10 18:11:08 +02008699 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008700 config->fb_changed = true;
8701
8702 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8703 DRM_DEBUG_KMS("modes are different, full mode set\n");
8704 drm_mode_debug_printmodeline(&set->crtc->mode);
8705 drm_mode_debug_printmodeline(set->mode);
8706 config->mode_changed = true;
8707 }
8708}
8709
Daniel Vetter2e431052012-07-04 22:42:15 +02008710static int
Daniel Vetter9a935852012-07-05 22:34:27 +02008711intel_modeset_stage_output_state(struct drm_device *dev,
8712 struct drm_mode_set *set,
8713 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02008714{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008715 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02008716 struct intel_connector *connector;
8717 struct intel_encoder *encoder;
Daniel Vetter2e431052012-07-04 22:42:15 +02008718 int count, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02008719
Damien Lespiau9abdda72013-02-13 13:29:23 +00008720 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +02008721 * of connectors. For paranoia, double-check this. */
8722 WARN_ON(!set->fb && (set->num_connectors != 0));
8723 WARN_ON(set->fb && (set->num_connectors == 0));
8724
Daniel Vetter50f56112012-07-02 09:35:43 +02008725 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008726 list_for_each_entry(connector, &dev->mode_config.connector_list,
8727 base.head) {
8728 /* Otherwise traverse passed in connector list and get encoders
8729 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008730 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008731 if (set->connectors[ro] == &connector->base) {
8732 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02008733 break;
8734 }
8735 }
8736
Daniel Vetter9a935852012-07-05 22:34:27 +02008737 /* If we disable the crtc, disable all its connectors. Also, if
8738 * the connector is on the changing crtc but not on the new
8739 * connector list, disable it. */
8740 if ((!set->fb || ro == set->num_connectors) &&
8741 connector->base.encoder &&
8742 connector->base.encoder->crtc == set->crtc) {
8743 connector->new_encoder = NULL;
8744
8745 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8746 connector->base.base.id,
8747 drm_get_connector_name(&connector->base));
8748 }
8749
8750
8751 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008752 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008753 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008754 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008755 }
8756 /* connector->new_encoder is now updated for all connectors. */
8757
8758 /* Update crtc of enabled connectors. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008759 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008760 list_for_each_entry(connector, &dev->mode_config.connector_list,
8761 base.head) {
8762 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02008763 continue;
8764
Daniel Vetter9a935852012-07-05 22:34:27 +02008765 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02008766
8767 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008768 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02008769 new_crtc = set->crtc;
8770 }
8771
8772 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02008773 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8774 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008775 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02008776 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008777 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8778
8779 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8780 connector->base.base.id,
8781 drm_get_connector_name(&connector->base),
8782 new_crtc->base.id);
8783 }
8784
8785 /* Check for any encoders that needs to be disabled. */
8786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8787 base.head) {
8788 list_for_each_entry(connector,
8789 &dev->mode_config.connector_list,
8790 base.head) {
8791 if (connector->new_encoder == encoder) {
8792 WARN_ON(!connector->new_encoder->new_crtc);
8793
8794 goto next_encoder;
8795 }
8796 }
8797 encoder->new_crtc = NULL;
8798next_encoder:
8799 /* Only now check for crtc changes so we don't miss encoders
8800 * that will be disabled. */
8801 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008802 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008803 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008804 }
8805 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008806 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008807
Daniel Vetter2e431052012-07-04 22:42:15 +02008808 return 0;
8809}
8810
8811static int intel_crtc_set_config(struct drm_mode_set *set)
8812{
8813 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02008814 struct drm_mode_set save_set;
8815 struct intel_set_config *config;
8816 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02008817
Daniel Vetter8d3e3752012-07-05 16:09:09 +02008818 BUG_ON(!set);
8819 BUG_ON(!set->crtc);
8820 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02008821
Daniel Vetter7e53f3a2013-01-21 10:52:17 +01008822 /* Enforce sane interface api - has been abused by the fb helper. */
8823 BUG_ON(!set->mode && set->fb);
8824 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +02008825
Daniel Vetter2e431052012-07-04 22:42:15 +02008826 if (set->fb) {
8827 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8828 set->crtc->base.id, set->fb->base.id,
8829 (int)set->num_connectors, set->x, set->y);
8830 } else {
8831 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02008832 }
8833
8834 dev = set->crtc->dev;
8835
8836 ret = -ENOMEM;
8837 config = kzalloc(sizeof(*config), GFP_KERNEL);
8838 if (!config)
8839 goto out_config;
8840
8841 ret = intel_set_config_save_state(dev, config);
8842 if (ret)
8843 goto out_config;
8844
8845 save_set.crtc = set->crtc;
8846 save_set.mode = &set->crtc->mode;
8847 save_set.x = set->crtc->x;
8848 save_set.y = set->crtc->y;
8849 save_set.fb = set->crtc->fb;
8850
8851 /* Compute whether we need a full modeset, only an fb base update or no
8852 * change at all. In the future we might also check whether only the
8853 * mode changed, e.g. for LVDS where we only change the panel fitter in
8854 * such cases. */
8855 intel_set_config_compute_mode_changes(set, config);
8856
Daniel Vetter9a935852012-07-05 22:34:27 +02008857 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02008858 if (ret)
8859 goto fail;
8860
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008861 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00008862 ret = intel_set_mode(set->crtc, set->mode,
8863 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008864 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +02008865 intel_crtc_wait_for_pending_flips(set->crtc);
8866
Daniel Vetter4f660f42012-07-02 09:47:37 +02008867 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02008868 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02008869 }
8870
Chris Wilson2d05eae2013-05-03 17:36:25 +01008871 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +02008872 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8873 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +02008874fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +01008875 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008876
Chris Wilson2d05eae2013-05-03 17:36:25 +01008877 /* Try to restore the config */
8878 if (config->mode_changed &&
8879 intel_set_mode(save_set.crtc, save_set.mode,
8880 save_set.x, save_set.y, save_set.fb))
8881 DRM_ERROR("failed to restore config after modeset failure\n");
8882 }
Daniel Vetter50f56112012-07-02 09:35:43 +02008883
Daniel Vetterd9e55602012-07-04 22:16:09 +02008884out_config:
8885 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008886 return ret;
8887}
8888
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008889static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008890 .cursor_set = intel_crtc_cursor_set,
8891 .cursor_move = intel_crtc_cursor_move,
8892 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02008893 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008894 .destroy = intel_crtc_destroy,
8895 .page_flip = intel_crtc_page_flip,
8896};
8897
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008898static void intel_cpu_pll_init(struct drm_device *dev)
8899{
Paulo Zanoniaffa9352012-11-23 15:30:39 -02008900 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008901 intel_ddi_pll_init(dev);
8902}
8903
Daniel Vetter53589012013-06-05 13:34:16 +02008904static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8905 struct intel_shared_dpll *pll,
8906 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008907{
Daniel Vetter53589012013-06-05 13:34:16 +02008908 uint32_t val;
8909
8910 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +02008911 hw_state->dpll = val;
8912 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8913 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +02008914
8915 return val & DPLL_VCO_ENABLE;
8916}
8917
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008918static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8919 struct intel_shared_dpll *pll)
8920{
8921 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8922 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8923}
8924
Daniel Vettere7b903d2013-06-05 13:34:14 +02008925static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8926 struct intel_shared_dpll *pll)
8927{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008928 /* PCH refclock must be enabled first */
8929 assert_pch_refclk_enabled(dev_priv);
8930
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008931 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8932
8933 /* Wait for the clocks to stabilize. */
8934 POSTING_READ(PCH_DPLL(pll->id));
8935 udelay(150);
8936
8937 /* The pixel multiplier can only be updated once the
8938 * DPLL is enabled and the clocks are stable.
8939 *
8940 * So write it again.
8941 */
8942 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8943 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02008944 udelay(200);
8945}
8946
8947static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8948 struct intel_shared_dpll *pll)
8949{
8950 struct drm_device *dev = dev_priv->dev;
8951 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +02008952
8953 /* Make sure no transcoder isn't still depending on us. */
8954 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8955 if (intel_crtc_to_shared_dpll(crtc) == pll)
8956 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8957 }
8958
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008959 I915_WRITE(PCH_DPLL(pll->id), 0);
8960 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02008961 udelay(200);
8962}
8963
Daniel Vetter46edb022013-06-05 13:34:12 +02008964static char *ibx_pch_dpll_names[] = {
8965 "PCH DPLL A",
8966 "PCH DPLL B",
8967};
8968
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008969static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008970{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008971 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008972 int i;
8973
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008974 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008975
Daniel Vettere72f9fb2013-06-05 13:34:06 +02008976 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +02008977 dev_priv->shared_dplls[i].id = i;
8978 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02008979 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +02008980 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8981 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +02008982 dev_priv->shared_dplls[i].get_hw_state =
8983 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008984 }
8985}
8986
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008987static void intel_shared_dpll_init(struct drm_device *dev)
8988{
Daniel Vettere7b903d2013-06-05 13:34:14 +02008989 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +02008990
8991 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8992 ibx_pch_dpll_init(dev);
8993 else
8994 dev_priv->num_shared_dpll = 0;
8995
8996 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8997 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8998 dev_priv->num_shared_dpll);
8999}
9000
Hannes Ederb358d0a2008-12-18 21:18:47 +01009001static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08009002{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08009003 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08009004 struct intel_crtc *intel_crtc;
9005 int i;
9006
9007 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9008 if (intel_crtc == NULL)
9009 return;
9010
9011 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9012
9013 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08009014 for (i = 0; i < 256; i++) {
9015 intel_crtc->lut_r[i] = i;
9016 intel_crtc->lut_g[i] = i;
9017 intel_crtc->lut_b[i] = i;
9018 }
9019
Jesse Barnes80824002009-09-10 15:28:06 -07009020 /* Swap pipes & planes for FBC on pre-965 */
9021 intel_crtc->pipe = pipe;
9022 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01009023 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08009024 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01009025 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07009026 }
9027
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08009028 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9029 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9030 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9031 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9032
Jesse Barnes79e53942008-11-07 14:24:08 -08009033 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08009034}
9035
Carl Worth08d7b3d2009-04-29 14:43:54 -07009036int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00009037 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07009038{
Carl Worth08d7b3d2009-04-29 14:43:54 -07009039 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02009040 struct drm_mode_object *drmmode_obj;
9041 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07009042
Daniel Vetter1cff8f62012-04-24 09:55:08 +02009043 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9044 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07009045
Daniel Vetterc05422d2009-08-11 16:05:30 +02009046 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9047 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07009048
Daniel Vetterc05422d2009-08-11 16:05:30 +02009049 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07009050 DRM_ERROR("no such CRTC id\n");
9051 return -EINVAL;
9052 }
9053
Daniel Vetterc05422d2009-08-11 16:05:30 +02009054 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9055 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07009056
Daniel Vetterc05422d2009-08-11 16:05:30 +02009057 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07009058}
9059
Daniel Vetter66a92782012-07-12 20:08:18 +02009060static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08009061{
Daniel Vetter66a92782012-07-12 20:08:18 +02009062 struct drm_device *dev = encoder->base.dev;
9063 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08009064 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009065 int entry = 0;
9066
Daniel Vetter66a92782012-07-12 20:08:18 +02009067 list_for_each_entry(source_encoder,
9068 &dev->mode_config.encoder_list, base.head) {
9069
9070 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08009071 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02009072
9073 /* Intel hw has only one MUX where enocoders could be cloned. */
9074 if (encoder->cloneable && source_encoder->cloneable)
9075 index_mask |= (1 << entry);
9076
Jesse Barnes79e53942008-11-07 14:24:08 -08009077 entry++;
9078 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01009079
Jesse Barnes79e53942008-11-07 14:24:08 -08009080 return index_mask;
9081}
9082
Chris Wilson4d302442010-12-14 19:21:29 +00009083static bool has_edp_a(struct drm_device *dev)
9084{
9085 struct drm_i915_private *dev_priv = dev->dev_private;
9086
9087 if (!IS_MOBILE(dev))
9088 return false;
9089
9090 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9091 return false;
9092
9093 if (IS_GEN5(dev) &&
9094 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9095 return false;
9096
9097 return true;
9098}
9099
Jesse Barnes79e53942008-11-07 14:24:08 -08009100static void intel_setup_outputs(struct drm_device *dev)
9101{
Eric Anholt725e30a2009-01-22 13:01:02 -08009102 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01009103 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04009104 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08009105
Daniel Vetterc9093352013-06-06 22:22:47 +02009106 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009107
Paulo Zanonic40c0f52013-04-12 18:16:53 -03009108 if (!IS_ULT(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -02009109 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04009110
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009111 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03009112 int found;
9113
9114 /* Haswell uses DDI functions to detect digital outputs */
9115 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9116 /* DDI A only supports eDP */
9117 if (found)
9118 intel_ddi_init(dev, PORT_A);
9119
9120 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9121 * register */
9122 found = I915_READ(SFUSE_STRAP);
9123
9124 if (found & SFUSE_STRAP_DDIB_DETECTED)
9125 intel_ddi_init(dev, PORT_B);
9126 if (found & SFUSE_STRAP_DDIC_DETECTED)
9127 intel_ddi_init(dev, PORT_C);
9128 if (found & SFUSE_STRAP_DDID_DETECTED)
9129 intel_ddi_init(dev, PORT_D);
9130 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04009131 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +02009132 dpd_is_edp = intel_dpd_is_edp(dev);
9133
9134 if (has_edp_a(dev))
9135 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04009136
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009137 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08009138 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01009139 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009140 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -03009141 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009142 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009143 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009144 }
9145
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009146 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03009147 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009148
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009149 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -03009150 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08009151
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009152 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009153 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08009154
Daniel Vetter270b3042012-10-27 15:52:05 +02009155 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009156 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07009157 } else if (IS_VALLEYVIEW(dev)) {
Gajanan Bhat19c03922012-09-27 19:13:07 +05309158 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
Ville Syrjälä67cfc202013-01-25 21:44:44 +02009159 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9160 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +05309161
Paulo Zanonidc0fa712013-02-19 16:21:46 -03009162 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
Paulo Zanonie2debe92013-02-18 19:00:27 -03009163 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9164 PORT_B);
Ville Syrjälä67cfc202013-01-25 21:44:44 +02009165 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9166 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07009167 }
Zhenyu Wang103a1962009-11-27 11:44:36 +08009168 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08009169 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08009170
Paulo Zanonie2debe92013-02-18 19:00:27 -03009171 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009172 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009173 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009174 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9175 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009176 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009177 }
Ma Ling27185ae2009-08-24 13:50:23 +08009178
Imre Deake7281ea2013-05-08 13:14:08 +03009179 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009180 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -08009181 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04009182
9183 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04009184
Paulo Zanonie2debe92013-02-18 19:00:27 -03009185 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009186 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009187 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009188 }
Ma Ling27185ae2009-08-24 13:50:23 +08009189
Paulo Zanonie2debe92013-02-18 19:00:27 -03009190 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +08009191
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009192 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9193 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -03009194 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009195 }
Imre Deake7281ea2013-05-08 13:14:08 +03009196 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009197 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -08009198 }
Ma Ling27185ae2009-08-24 13:50:23 +08009199
Jesse Barnesb01f2c32009-12-11 11:07:17 -08009200 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +03009201 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03009202 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -07009203 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08009204 intel_dvo_init(dev);
9205
Zhenyu Wang103a1962009-11-27 11:44:36 +08009206 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08009207 intel_tv_init(dev);
9208
Chris Wilson4ef69c72010-09-09 15:14:28 +01009209 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9210 encoder->base.possible_crtcs = encoder->crtc_mask;
9211 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02009212 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08009213 }
Chris Wilson47356eb2011-01-11 17:06:04 +00009214
Paulo Zanonidde86e22012-12-01 12:04:25 -02009215 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +02009216
9217 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009218}
9219
9220static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9221{
9222 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08009223
9224 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00009225 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009226
9227 kfree(intel_fb);
9228}
9229
9230static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00009231 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08009232 unsigned int *handle)
9233{
9234 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00009235 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08009236
Chris Wilson05394f32010-11-08 19:18:58 +00009237 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08009238}
9239
9240static const struct drm_framebuffer_funcs intel_fb_funcs = {
9241 .destroy = intel_user_framebuffer_destroy,
9242 .create_handle = intel_user_framebuffer_create_handle,
9243};
9244
Dave Airlie38651672010-03-30 05:34:13 +00009245int intel_framebuffer_init(struct drm_device *dev,
9246 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009247 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00009248 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08009249{
Chris Wilsona35cdaa2013-06-25 17:26:45 +01009250 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -08009251 int ret;
9252
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009253 if (obj->tiling_mode == I915_TILING_Y) {
9254 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +01009255 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009256 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009257
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009258 if (mode_cmd->pitches[0] & 63) {
9259 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9260 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +01009261 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009262 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009263
Chris Wilsona35cdaa2013-06-25 17:26:45 +01009264 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9265 pitch_limit = 32*1024;
9266 } else if (INTEL_INFO(dev)->gen >= 4) {
9267 if (obj->tiling_mode)
9268 pitch_limit = 16*1024;
9269 else
9270 pitch_limit = 32*1024;
9271 } else if (INTEL_INFO(dev)->gen >= 3) {
9272 if (obj->tiling_mode)
9273 pitch_limit = 8*1024;
9274 else
9275 pitch_limit = 16*1024;
9276 } else
9277 /* XXX DSPC is limited to 4k tiled */
9278 pitch_limit = 8*1024;
9279
9280 if (mode_cmd->pitches[0] > pitch_limit) {
9281 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9282 obj->tiling_mode ? "tiled" : "linear",
9283 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009284 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009285 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009286
9287 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009288 mode_cmd->pitches[0] != obj->stride) {
9289 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9290 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009291 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009292 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02009293
Ville Syrjälä57779d02012-10-31 17:50:14 +02009294 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009295 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +02009296 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +02009297 case DRM_FORMAT_RGB565:
9298 case DRM_FORMAT_XRGB8888:
9299 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02009300 break;
9301 case DRM_FORMAT_XRGB1555:
9302 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009303 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009304 DRM_DEBUG("unsupported pixel format: %s\n",
9305 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009306 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009307 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02009308 break;
9309 case DRM_FORMAT_XBGR8888:
9310 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02009311 case DRM_FORMAT_XRGB2101010:
9312 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02009313 case DRM_FORMAT_XBGR2101010:
9314 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009315 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009316 DRM_DEBUG("unsupported pixel format: %s\n",
9317 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009318 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009319 }
Jesse Barnesb5626742011-06-24 12:19:27 -07009320 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02009321 case DRM_FORMAT_YUYV:
9322 case DRM_FORMAT_UYVY:
9323 case DRM_FORMAT_YVYU:
9324 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009325 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009326 DRM_DEBUG("unsupported pixel format: %s\n",
9327 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +02009328 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00009329 }
Chris Wilson57cd6502010-08-08 12:34:44 +01009330 break;
9331 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +00009332 DRM_DEBUG("unsupported pixel format: %s\n",
9333 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +01009334 return -EINVAL;
9335 }
9336
Ville Syrjälä90f9a332012-10-31 17:50:19 +02009337 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9338 if (mode_cmd->offsets[0] != 0)
9339 return -EINVAL;
9340
Daniel Vetterc7d73f62012-12-13 23:38:38 +01009341 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9342 intel_fb->obj = obj;
9343
Jesse Barnes79e53942008-11-07 14:24:08 -08009344 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9345 if (ret) {
9346 DRM_ERROR("framebuffer init failed %d\n", ret);
9347 return ret;
9348 }
9349
Jesse Barnes79e53942008-11-07 14:24:08 -08009350 return 0;
9351}
9352
Jesse Barnes79e53942008-11-07 14:24:08 -08009353static struct drm_framebuffer *
9354intel_user_framebuffer_create(struct drm_device *dev,
9355 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009356 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08009357{
Chris Wilson05394f32010-11-08 19:18:58 +00009358 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08009359
Jesse Barnes308e5bc2011-11-14 14:51:28 -08009360 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9361 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00009362 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01009363 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08009364
Chris Wilsond2dff872011-04-19 08:36:26 +01009365 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08009366}
9367
Jesse Barnes79e53942008-11-07 14:24:08 -08009368static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08009369 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00009370 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08009371};
9372
Jesse Barnese70236a2009-09-21 10:42:27 -07009373/* Set up chip specific display functions */
9374static void intel_init_display(struct drm_device *dev)
9375{
9376 struct drm_i915_private *dev_priv = dev->dev_private;
9377
Daniel Vetteree9300b2013-06-03 22:40:22 +02009378 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9379 dev_priv->display.find_dpll = g4x_find_best_dpll;
9380 else if (IS_VALLEYVIEW(dev))
9381 dev_priv->display.find_dpll = vlv_find_best_dpll;
9382 else if (IS_PINEVIEW(dev))
9383 dev_priv->display.find_dpll = pnv_find_best_dpll;
9384 else
9385 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9386
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009387 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009388 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009389 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02009390 dev_priv->display.crtc_enable = haswell_crtc_enable;
9391 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009392 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009393 dev_priv->display.update_plane = ironlake_update_plane;
9394 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009395 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009396 dev_priv->display.get_clock = ironlake_crtc_clock_get;
Eric Anholtf564048e2011-03-30 13:01:02 -07009397 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02009398 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9399 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009400 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07009401 dev_priv->display.update_plane = ironlake_update_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -07009402 } else if (IS_VALLEYVIEW(dev)) {
9403 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009404 dev_priv->display.get_clock = i9xx_crtc_clock_get;
Jesse Barnes89b667f2013-04-18 14:51:36 -07009405 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9406 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9407 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9408 dev_priv->display.off = i9xx_crtc_off;
9409 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07009410 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009411 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009412 dev_priv->display.get_clock = i9xx_crtc_clock_get;
Eric Anholtf564048e2011-03-30 13:01:02 -07009413 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02009414 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9415 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009416 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07009417 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07009418 }
Jesse Barnese70236a2009-09-21 10:42:27 -07009419
Jesse Barnese70236a2009-09-21 10:42:27 -07009420 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07009421 if (IS_VALLEYVIEW(dev))
9422 dev_priv->display.get_display_clock_speed =
9423 valleyview_get_display_clock_speed;
9424 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07009425 dev_priv->display.get_display_clock_speed =
9426 i945_get_display_clock_speed;
9427 else if (IS_I915G(dev))
9428 dev_priv->display.get_display_clock_speed =
9429 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05009430 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07009431 dev_priv->display.get_display_clock_speed =
9432 i9xx_misc_get_display_clock_speed;
9433 else if (IS_I915GM(dev))
9434 dev_priv->display.get_display_clock_speed =
9435 i915gm_get_display_clock_speed;
9436 else if (IS_I865G(dev))
9437 dev_priv->display.get_display_clock_speed =
9438 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02009439 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07009440 dev_priv->display.get_display_clock_speed =
9441 i855_get_display_clock_speed;
9442 else /* 852, 830 */
9443 dev_priv->display.get_display_clock_speed =
9444 i830_get_display_clock_speed;
9445
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08009446 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01009447 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07009448 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009449 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08009450 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07009451 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009452 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07009453 } else if (IS_IVYBRIDGE(dev)) {
9454 /* FIXME: detect B0+ stepping and use auto training */
9455 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08009456 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +02009457 dev_priv->display.modeset_global_resources =
9458 ivb_modeset_global_resources;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03009459 } else if (IS_HASWELL(dev)) {
9460 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08009461 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -02009462 dev_priv->display.modeset_global_resources =
9463 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -02009464 }
Jesse Barnes6067aae2011-04-28 15:04:31 -07009465 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08009466 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07009467 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009468
9469 /* Default just returns -ENODEV to indicate unsupported */
9470 dev_priv->display.queue_flip = intel_default_queue_flip;
9471
9472 switch (INTEL_INFO(dev)->gen) {
9473 case 2:
9474 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9475 break;
9476
9477 case 3:
9478 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9479 break;
9480
9481 case 4:
9482 case 5:
9483 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9484 break;
9485
9486 case 6:
9487 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9488 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07009489 case 7:
9490 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9491 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07009492 }
Jesse Barnese70236a2009-09-21 10:42:27 -07009493}
9494
Jesse Barnesb690e962010-07-19 13:53:12 -07009495/*
9496 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9497 * resume, or other times. This quirk makes sure that's the case for
9498 * affected systems.
9499 */
Akshay Joshi0206e352011-08-16 15:34:10 -04009500static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07009501{
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503
9504 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009505 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07009506}
9507
Keith Packard435793d2011-07-12 14:56:22 -07009508/*
9509 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9510 */
9511static void quirk_ssc_force_disable(struct drm_device *dev)
9512{
9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009515 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07009516}
9517
Carsten Emde4dca20e2012-03-15 15:56:26 +01009518/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01009519 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9520 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01009521 */
9522static void quirk_invert_brightness(struct drm_device *dev)
9523{
9524 struct drm_i915_private *dev_priv = dev->dev_private;
9525 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02009526 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07009527}
9528
9529struct intel_quirk {
9530 int device;
9531 int subsystem_vendor;
9532 int subsystem_device;
9533 void (*hook)(struct drm_device *dev);
9534};
9535
Egbert Eich5f85f1762012-10-14 15:46:38 +02009536/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9537struct intel_dmi_quirk {
9538 void (*hook)(struct drm_device *dev);
9539 const struct dmi_system_id (*dmi_id_list)[];
9540};
9541
9542static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9543{
9544 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9545 return 1;
9546}
9547
9548static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9549 {
9550 .dmi_id_list = &(const struct dmi_system_id[]) {
9551 {
9552 .callback = intel_dmi_reverse_brightness,
9553 .ident = "NCR Corporation",
9554 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9555 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9556 },
9557 },
9558 { } /* terminating entry */
9559 },
9560 .hook = quirk_invert_brightness,
9561 },
9562};
9563
Ben Widawskyc43b5632012-04-16 14:07:40 -07009564static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07009565 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04009566 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07009567
Jesse Barnesb690e962010-07-19 13:53:12 -07009568 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9569 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9570
Jesse Barnesb690e962010-07-19 13:53:12 -07009571 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9572 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9573
Daniel Vetterccd0d362012-10-10 23:13:59 +02009574 /* 830/845 need to leave pipe A & dpll A up */
Jesse Barnesb690e962010-07-19 13:53:12 -07009575 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02009576 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07009577
9578 /* Lenovo U160 cannot use SSC on LVDS */
9579 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02009580
9581 /* Sony Vaio Y cannot use SSC on LVDS */
9582 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01009583
9584 /* Acer Aspire 5734Z must invert backlight brightness */
9585 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jani Nikula1ffff602013-01-22 12:50:34 +02009586
9587 /* Acer/eMachines G725 */
9588 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
Jani Nikula01e3a8f2013-01-22 12:50:35 +02009589
9590 /* Acer/eMachines e725 */
9591 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
Jani Nikula5559eca2013-01-22 12:50:36 +02009592
9593 /* Acer/Packard Bell NCL20 */
9594 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
Daniel Vetterac4199e2013-02-15 18:35:30 +01009595
9596 /* Acer Aspire 4736Z */
9597 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07009598};
9599
9600static void intel_init_quirks(struct drm_device *dev)
9601{
9602 struct pci_dev *d = dev->pdev;
9603 int i;
9604
9605 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9606 struct intel_quirk *q = &intel_quirks[i];
9607
9608 if (d->device == q->device &&
9609 (d->subsystem_vendor == q->subsystem_vendor ||
9610 q->subsystem_vendor == PCI_ANY_ID) &&
9611 (d->subsystem_device == q->subsystem_device ||
9612 q->subsystem_device == PCI_ANY_ID))
9613 q->hook(dev);
9614 }
Egbert Eich5f85f1762012-10-14 15:46:38 +02009615 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9616 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9617 intel_dmi_quirks[i].hook(dev);
9618 }
Jesse Barnesb690e962010-07-19 13:53:12 -07009619}
9620
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009621/* Disable the VGA plane that we never use */
9622static void i915_disable_vga(struct drm_device *dev)
9623{
9624 struct drm_i915_private *dev_priv = dev->dev_private;
9625 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02009626 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009627
9628 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07009629 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009630 sr1 = inb(VGA_SR_DATA);
9631 outb(sr1 | 1<<5, VGA_SR_DATA);
9632 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9633 udelay(300);
9634
9635 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9636 POSTING_READ(vga_reg);
9637}
9638
Daniel Vetterf8175862012-04-10 15:50:11 +02009639void intel_modeset_init_hw(struct drm_device *dev)
9640{
Paulo Zanonifa42e232013-01-25 16:59:11 -02009641 intel_init_power_well(dev);
Eugeni Dodonov0232e922012-07-06 15:42:36 -03009642
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03009643 intel_prepare_ddi(dev);
9644
Daniel Vetterf8175862012-04-10 15:50:11 +02009645 intel_init_clock_gating(dev);
9646
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02009647 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02009648 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02009649 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02009650}
9651
Imre Deak7d708ee2013-04-17 14:04:50 +03009652void intel_modeset_suspend_hw(struct drm_device *dev)
9653{
9654 intel_suspend_hw(dev);
9655}
9656
Jesse Barnes79e53942008-11-07 14:24:08 -08009657void intel_modeset_init(struct drm_device *dev)
9658{
Jesse Barnes652c3932009-08-17 13:31:43 -07009659 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009660 int i, j, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08009661
9662 drm_mode_config_init(dev);
9663
9664 dev->mode_config.min_width = 0;
9665 dev->mode_config.min_height = 0;
9666
Dave Airlie019d96c2011-09-29 16:20:42 +01009667 dev->mode_config.preferred_depth = 24;
9668 dev->mode_config.prefer_shadow = 1;
9669
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02009670 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08009671
Jesse Barnesb690e962010-07-19 13:53:12 -07009672 intel_init_quirks(dev);
9673
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03009674 intel_init_pm(dev);
9675
Ben Widawskye3c74752013-04-05 13:12:39 -07009676 if (INTEL_INFO(dev)->num_pipes == 0)
9677 return;
9678
Jesse Barnese70236a2009-09-21 10:42:27 -07009679 intel_init_display(dev);
9680
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009681 if (IS_GEN2(dev)) {
9682 dev->mode_config.max_width = 2048;
9683 dev->mode_config.max_height = 2048;
9684 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07009685 dev->mode_config.max_width = 4096;
9686 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08009687 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009688 dev->mode_config.max_width = 8192;
9689 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08009690 }
Ben Widawsky5d4545a2013-01-17 12:45:15 -08009691 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -08009692
Zhao Yakui28c97732009-10-09 11:39:41 +08009693 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009694 INTEL_INFO(dev)->num_pipes,
9695 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08009696
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009697 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009698 intel_crtc_init(dev, i);
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009699 for (j = 0; j < dev_priv->num_plane; j++) {
9700 ret = intel_plane_init(dev, i, j);
9701 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +03009702 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9703 pipe_name(i), sprite_name(i, j), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -07009704 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009705 }
9706
Paulo Zanoni79f689a2012-10-05 12:05:52 -03009707 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02009708 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009709
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009710 /* Just disable it once at startup */
9711 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009712 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00009713
9714 /* Just in case the BIOS is doing something questionable. */
9715 intel_disable_fbc(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009716}
Jesse Barnesd5bb0812011-01-05 12:01:26 -08009717
Daniel Vetter24929352012-07-02 20:28:59 +02009718static void
9719intel_connector_break_all_links(struct intel_connector *connector)
9720{
9721 connector->base.dpms = DRM_MODE_DPMS_OFF;
9722 connector->base.encoder = NULL;
9723 connector->encoder->connectors_active = false;
9724 connector->encoder->base.crtc = NULL;
9725}
9726
Daniel Vetter7fad7982012-07-04 17:51:47 +02009727static void intel_enable_pipe_a(struct drm_device *dev)
9728{
9729 struct intel_connector *connector;
9730 struct drm_connector *crt = NULL;
9731 struct intel_load_detect_pipe load_detect_temp;
9732
9733 /* We can't just switch on the pipe A, we need to set things up with a
9734 * proper mode and output configuration. As a gross hack, enable pipe A
9735 * by enabling the load detect pipe once. */
9736 list_for_each_entry(connector,
9737 &dev->mode_config.connector_list,
9738 base.head) {
9739 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9740 crt = &connector->base;
9741 break;
9742 }
9743 }
9744
9745 if (!crt)
9746 return;
9747
9748 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9749 intel_release_load_detect_pipe(crt, &load_detect_temp);
9750
9751
9752}
9753
Daniel Vetterfa555832012-10-10 23:14:00 +02009754static bool
9755intel_check_plane_mapping(struct intel_crtc *crtc)
9756{
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009757 struct drm_device *dev = crtc->base.dev;
9758 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009759 u32 reg, val;
9760
Ben Widawsky7eb552a2013-03-13 14:05:41 -07009761 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +02009762 return true;
9763
9764 reg = DSPCNTR(!crtc->plane);
9765 val = I915_READ(reg);
9766
9767 if ((val & DISPLAY_PLANE_ENABLE) &&
9768 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9769 return false;
9770
9771 return true;
9772}
9773
Daniel Vetter24929352012-07-02 20:28:59 +02009774static void intel_sanitize_crtc(struct intel_crtc *crtc)
9775{
9776 struct drm_device *dev = crtc->base.dev;
9777 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009778 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +02009779
Daniel Vetter24929352012-07-02 20:28:59 +02009780 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +02009781 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +02009782 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9783
9784 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +02009785 * disable the crtc (and hence change the state) if it is wrong. Note
9786 * that gen4+ has a fixed plane -> pipe mapping. */
9787 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +02009788 struct intel_connector *connector;
9789 bool plane;
9790
Daniel Vetter24929352012-07-02 20:28:59 +02009791 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9792 crtc->base.base.id);
9793
9794 /* Pipe has the wrong plane attached and the plane is active.
9795 * Temporarily change the plane mapping and disable everything
9796 * ... */
9797 plane = crtc->plane;
9798 crtc->plane = !plane;
9799 dev_priv->display.crtc_disable(&crtc->base);
9800 crtc->plane = plane;
9801
9802 /* ... and break all links. */
9803 list_for_each_entry(connector, &dev->mode_config.connector_list,
9804 base.head) {
9805 if (connector->encoder->base.crtc != &crtc->base)
9806 continue;
9807
9808 intel_connector_break_all_links(connector);
9809 }
9810
9811 WARN_ON(crtc->active);
9812 crtc->base.enabled = false;
9813 }
Daniel Vetter24929352012-07-02 20:28:59 +02009814
Daniel Vetter7fad7982012-07-04 17:51:47 +02009815 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9816 crtc->pipe == PIPE_A && !crtc->active) {
9817 /* BIOS forgot to enable pipe A, this mostly happens after
9818 * resume. Force-enable the pipe to fix this, the update_dpms
9819 * call below we restore the pipe to the right state, but leave
9820 * the required bits on. */
9821 intel_enable_pipe_a(dev);
9822 }
9823
Daniel Vetter24929352012-07-02 20:28:59 +02009824 /* Adjust the state of the output pipe according to whether we
9825 * have active connectors/encoders. */
9826 intel_crtc_update_dpms(&crtc->base);
9827
9828 if (crtc->active != crtc->base.enabled) {
9829 struct intel_encoder *encoder;
9830
9831 /* This can happen either due to bugs in the get_hw_state
9832 * functions or because the pipe is force-enabled due to the
9833 * pipe A quirk. */
9834 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9835 crtc->base.base.id,
9836 crtc->base.enabled ? "enabled" : "disabled",
9837 crtc->active ? "enabled" : "disabled");
9838
9839 crtc->base.enabled = crtc->active;
9840
9841 /* Because we only establish the connector -> encoder ->
9842 * crtc links if something is active, this means the
9843 * crtc is now deactivated. Break the links. connector
9844 * -> encoder links are only establish when things are
9845 * actually up, hence no need to break them. */
9846 WARN_ON(crtc->active);
9847
9848 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9849 WARN_ON(encoder->connectors_active);
9850 encoder->base.crtc = NULL;
9851 }
9852 }
9853}
9854
9855static void intel_sanitize_encoder(struct intel_encoder *encoder)
9856{
9857 struct intel_connector *connector;
9858 struct drm_device *dev = encoder->base.dev;
9859
9860 /* We need to check both for a crtc link (meaning that the
9861 * encoder is active and trying to read from a pipe) and the
9862 * pipe itself being active. */
9863 bool has_active_crtc = encoder->base.crtc &&
9864 to_intel_crtc(encoder->base.crtc)->active;
9865
9866 if (encoder->connectors_active && !has_active_crtc) {
9867 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9868 encoder->base.base.id,
9869 drm_get_encoder_name(&encoder->base));
9870
9871 /* Connector is active, but has no active pipe. This is
9872 * fallout from our resume register restoring. Disable
9873 * the encoder manually again. */
9874 if (encoder->base.crtc) {
9875 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9876 encoder->base.base.id,
9877 drm_get_encoder_name(&encoder->base));
9878 encoder->disable(encoder);
9879 }
9880
9881 /* Inconsistent output/port/pipe state happens presumably due to
9882 * a bug in one of the get_hw_state functions. Or someplace else
9883 * in our code, like the register restore mess on resume. Clamp
9884 * things to off as a safer default. */
9885 list_for_each_entry(connector,
9886 &dev->mode_config.connector_list,
9887 base.head) {
9888 if (connector->encoder != encoder)
9889 continue;
9890
9891 intel_connector_break_all_links(connector);
9892 }
9893 }
9894 /* Enabled encoders without active connectors will be fixed in
9895 * the crtc fixup. */
9896}
9897
Daniel Vetter44cec742013-01-25 17:53:21 +01009898void i915_redisable_vga(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009899{
9900 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02009901 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009902
9903 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9904 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
Ville Syrjälä209d5212013-01-25 21:44:48 +02009905 i915_disable_vga(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009906 }
9907}
9908
Daniel Vetter30e984d2013-06-05 13:34:17 +02009909static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +02009910{
9911 struct drm_i915_private *dev_priv = dev->dev_private;
9912 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +02009913 struct intel_crtc *crtc;
9914 struct intel_encoder *encoder;
9915 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +02009916 int i;
Daniel Vetter24929352012-07-02 20:28:59 +02009917
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009918 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9919 base.head) {
Daniel Vetter88adfff2013-03-28 10:42:01 +01009920 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +02009921
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009922 crtc->active = dev_priv->display.get_pipe_config(crtc,
9923 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +02009924
9925 crtc->base.enabled = crtc->active;
9926
9927 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9928 crtc->base.base.id,
9929 crtc->active ? "enabled" : "disabled");
9930 }
9931
Daniel Vetter53589012013-06-05 13:34:16 +02009932 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009933 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009934 intel_ddi_setup_hw_pll_state(dev);
9935
Daniel Vetter53589012013-06-05 13:34:16 +02009936 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9937 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9938
9939 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9940 pll->active = 0;
9941 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9942 base.head) {
9943 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9944 pll->active++;
9945 }
9946 pll->refcount = pll->active;
9947
9948 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9949 pll->name, pll->refcount);
9950 }
9951
Daniel Vetter24929352012-07-02 20:28:59 +02009952 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9953 base.head) {
9954 pipe = 0;
9955
9956 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009957 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9958 encoder->base.crtc = &crtc->base;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009959 if (encoder->get_config &&
9960 dev_priv->display.get_clock) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009961 encoder->get_config(encoder, &crtc->config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009962 dev_priv->display.get_clock(crtc,
9963 &crtc->config);
9964 }
Daniel Vetter24929352012-07-02 20:28:59 +02009965 } else {
9966 encoder->base.crtc = NULL;
9967 }
9968
9969 encoder->connectors_active = false;
9970 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9971 encoder->base.base.id,
9972 drm_get_encoder_name(&encoder->base),
9973 encoder->base.crtc ? "enabled" : "disabled",
9974 pipe);
9975 }
9976
9977 list_for_each_entry(connector, &dev->mode_config.connector_list,
9978 base.head) {
9979 if (connector->get_hw_state(connector)) {
9980 connector->base.dpms = DRM_MODE_DPMS_ON;
9981 connector->encoder->connectors_active = true;
9982 connector->base.encoder = &connector->encoder->base;
9983 } else {
9984 connector->base.dpms = DRM_MODE_DPMS_OFF;
9985 connector->base.encoder = NULL;
9986 }
9987 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9988 connector->base.base.id,
9989 drm_get_connector_name(&connector->base),
9990 connector->base.encoder ? "enabled" : "disabled");
9991 }
Daniel Vetter30e984d2013-06-05 13:34:17 +02009992}
9993
9994/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9995 * and i915 state tracking structures. */
9996void intel_modeset_setup_hw_state(struct drm_device *dev,
9997 bool force_restore)
9998{
9999 struct drm_i915_private *dev_priv = dev->dev_private;
10000 enum pipe pipe;
10001 struct drm_plane *plane;
10002 struct intel_crtc *crtc;
10003 struct intel_encoder *encoder;
10004
10005 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020010006
Jesse Barnesbabea612013-06-26 18:57:38 +030010007 /*
10008 * Now that we have the config, copy it to each CRTC struct
10009 * Note that this could go away if we move to using crtc_config
10010 * checking everywhere.
10011 */
10012 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10013 base.head) {
10014 if (crtc->active && i915_fastboot) {
10015 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10016
10017 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10018 crtc->base.base.id);
10019 drm_mode_debug_printmodeline(&crtc->base.mode);
10020 }
10021 }
10022
Daniel Vetter24929352012-07-02 20:28:59 +020010023 /* HW state is read out, now we need to sanitize this mess. */
10024 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10025 base.head) {
10026 intel_sanitize_encoder(encoder);
10027 }
10028
10029 for_each_pipe(pipe) {
10030 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10031 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020010032 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020010033 }
Daniel Vetter9a935852012-07-05 22:34:27 +020010034
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010010035 if (force_restore) {
Daniel Vetterf30da182013-04-11 20:22:50 +020010036 /*
10037 * We need to use raw interfaces for restoring state to avoid
10038 * checking (bogus) intermediate states.
10039 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010010040 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070010041 struct drm_crtc *crtc =
10042 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020010043
10044 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10045 crtc->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010010046 }
Jesse Barnesb5644d02013-03-26 13:25:27 -070010047 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10048 intel_plane_restore(plane);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010010049
10050 i915_redisable_vga(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010010051 } else {
10052 intel_modeset_update_staged_output_state(dev);
10053 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020010054
10055 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +020010056
10057 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010010058}
10059
10060void intel_modeset_gem_init(struct drm_device *dev)
10061{
Chris Wilson1833b132012-05-09 11:56:28 +010010062 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020010063
10064 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020010065
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010010066 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -080010067}
10068
10069void intel_modeset_cleanup(struct drm_device *dev)
10070{
Jesse Barnes652c3932009-08-17 13:31:43 -070010071 struct drm_i915_private *dev_priv = dev->dev_private;
10072 struct drm_crtc *crtc;
10073 struct intel_crtc *intel_crtc;
10074
Daniel Vetterfd0c0642013-04-24 11:13:35 +020010075 /*
10076 * Interrupts and polling as the first thing to avoid creating havoc.
10077 * Too much stuff here (turning of rps, connectors, ...) would
10078 * experience fancy races otherwise.
10079 */
10080 drm_irq_uninstall(dev);
10081 cancel_work_sync(&dev_priv->hotplug_work);
10082 /*
10083 * Due to the hpd irq storm handling the hotplug work can re-arm the
10084 * poll handlers. Hence disable polling after hpd handling is shut down.
10085 */
Keith Packardf87ea762010-10-03 19:36:26 -070010086 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020010087
Jesse Barnes652c3932009-08-17 13:31:43 -070010088 mutex_lock(&dev->struct_mutex);
10089
Jesse Barnes723bfd72010-10-07 16:01:13 -070010090 intel_unregister_dsm_handler();
10091
Jesse Barnes652c3932009-08-17 13:31:43 -070010092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10093 /* Skip inactive CRTCs */
10094 if (!crtc->fb)
10095 continue;
10096
10097 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +020010098 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070010099 }
10100
Chris Wilson973d04f2011-07-08 12:22:37 +010010101 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070010102
Daniel Vetter8090c6b2012-06-24 16:42:32 +020010103 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000010104
Daniel Vetter930ebb42012-06-29 23:32:16 +020010105 ironlake_teardown_rc6(dev);
10106
Kristian Høgsberg69341a52009-11-11 12:19:17 -050010107 mutex_unlock(&dev->struct_mutex);
10108
Chris Wilson1630fe72011-07-08 12:22:42 +010010109 /* flush any delayed tasks or pending work */
10110 flush_scheduled_work();
10111
Jani Nikuladc652f92013-04-12 15:18:38 +030010112 /* destroy backlight, if any, before the connectors */
10113 intel_panel_destroy_backlight(dev);
10114
Jesse Barnes79e53942008-11-07 14:24:08 -080010115 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010010116
10117 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010118}
10119
Dave Airlie28d52042009-09-21 14:33:58 +100010120/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080010121 * Return which encoder is currently attached for connector.
10122 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010010123struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080010124{
Chris Wilsondf0e9242010-09-09 16:20:55 +010010125 return &intel_attached_encoder(connector)->base;
10126}
Jesse Barnes79e53942008-11-07 14:24:08 -080010127
Chris Wilsondf0e9242010-09-09 16:20:55 +010010128void intel_connector_attach_encoder(struct intel_connector *connector,
10129 struct intel_encoder *encoder)
10130{
10131 connector->encoder = encoder;
10132 drm_mode_connector_attach_encoder(&connector->base,
10133 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080010134}
Dave Airlie28d52042009-09-21 14:33:58 +100010135
10136/*
10137 * set vga decode state - true == enable VGA decode
10138 */
10139int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10140{
10141 struct drm_i915_private *dev_priv = dev->dev_private;
10142 u16 gmch_ctrl;
10143
10144 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10145 if (state)
10146 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10147 else
10148 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10149 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10150 return 0;
10151}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010152
10153#ifdef CONFIG_DEBUG_FS
10154#include <linux/seq_file.h>
10155
10156struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010157
10158 u32 power_well_driver;
10159
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010160 struct intel_cursor_error_state {
10161 u32 control;
10162 u32 position;
10163 u32 base;
10164 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010010165 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010166
10167 struct intel_pipe_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010168 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010169 u32 conf;
10170 u32 source;
10171
10172 u32 htotal;
10173 u32 hblank;
10174 u32 hsync;
10175 u32 vtotal;
10176 u32 vblank;
10177 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +010010178 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010179
10180 struct intel_plane_error_state {
10181 u32 control;
10182 u32 stride;
10183 u32 size;
10184 u32 pos;
10185 u32 addr;
10186 u32 surface;
10187 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010010188 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010189};
10190
10191struct intel_display_error_state *
10192intel_display_capture_error_state(struct drm_device *dev)
10193{
Akshay Joshi0206e352011-08-16 15:34:10 -040010194 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010195 struct intel_display_error_state *error;
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010196 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010197 int i;
10198
10199 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10200 if (error == NULL)
10201 return NULL;
10202
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010203 if (HAS_POWER_WELL(dev))
10204 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10205
Damien Lespiau52331302012-08-15 19:23:25 +010010206 for_each_pipe(i) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010207 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010208 error->pipe[i].cpu_transcoder = cpu_transcoder;
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010209
Paulo Zanonia18c4c32013-03-06 20:03:12 -030010210 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10211 error->cursor[i].control = I915_READ(CURCNTR(i));
10212 error->cursor[i].position = I915_READ(CURPOS(i));
10213 error->cursor[i].base = I915_READ(CURBASE(i));
10214 } else {
10215 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10216 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10217 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10218 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010219
10220 error->plane[i].control = I915_READ(DSPCNTR(i));
10221 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010222 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030010223 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010224 error->plane[i].pos = I915_READ(DSPPOS(i));
10225 }
Paulo Zanonica291362013-03-06 20:03:14 -030010226 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10227 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010228 if (INTEL_INFO(dev)->gen >= 4) {
10229 error->plane[i].surface = I915_READ(DSPSURF(i));
10230 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10231 }
10232
Paulo Zanoni702e7a52012-10-23 18:29:59 -020010233 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010234 error->pipe[i].source = I915_READ(PIPESRC(i));
Paulo Zanonife2b8f92012-10-23 18:30:02 -020010235 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10236 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10237 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10238 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10239 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10240 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010241 }
10242
Paulo Zanoni12d217c2013-05-03 12:15:38 -030010243 /* In the code above we read the registers without checking if the power
10244 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10245 * prevent the next I915_WRITE from detecting it and printing an error
10246 * message. */
10247 if (HAS_POWER_WELL(dev))
10248 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10249
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010250 return error;
10251}
10252
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010253#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10254
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010255void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010256intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010257 struct drm_device *dev,
10258 struct intel_display_error_state *error)
10259{
10260 int i;
10261
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010262 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010263 if (HAS_POWER_WELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010264 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010265 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010010266 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010267 err_printf(m, "Pipe [%d]:\n", i);
10268 err_printf(m, " CPU transcoder: %c\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030010269 transcoder_name(error->pipe[i].cpu_transcoder));
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010270 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10271 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10272 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10273 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10274 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10275 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10276 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10277 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010278
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010279 err_printf(m, "Plane [%d]:\n", i);
10280 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10281 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010282 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010283 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10284 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030010285 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030010286 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010287 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010288 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010289 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10290 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010291 }
10292
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030010293 err_printf(m, "Cursor [%d]:\n", i);
10294 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10295 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10296 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000010297 }
10298}
10299#endif