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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
34
Jesse Barnes585fb112008-07-29 11:54:06 -070035#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080037#include "intel_ringbuffer.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070038#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070039#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010040#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020041#include <drm/intel-gtt.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020042#include <linux/backlight.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070043#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020044#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010045#include <linux/pm_qos.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070046
Linus Torvalds1da177e2005-04-16 15:20:36 -070047/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070054#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Jesse Barnes317c35d2008-08-25 15:11:06 -070056enum pipe {
Jesse Barnes752aa882013-10-31 18:55:49 +020057 INVALID_PIPE = -1,
Jesse Barnes317c35d2008-08-25 15:11:06 -070058 PIPE_A = 0,
59 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080060 PIPE_C,
61 I915_MAX_PIPES
Jesse Barnes317c35d2008-08-25 15:11:06 -070062};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080063#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070064
Paulo Zanonia5c961d2012-10-24 15:59:34 -020065enum transcoder {
66 TRANSCODER_A = 0,
67 TRANSCODER_B,
68 TRANSCODER_C,
69 TRANSCODER_EDP = 0xF,
70};
71#define transcoder_name(t) ((t) + 'A')
72
Jesse Barnes80824002009-09-10 15:28:06 -070073enum plane {
74 PLANE_A = 0,
75 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080076 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070077};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080078#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080079
Ville Syrjälä06da8da2013-04-17 17:48:51 +030080#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
81
Eugeni Dodonov2b139522012-03-29 12:32:22 -030082enum port {
83 PORT_A = 0,
84 PORT_B,
85 PORT_C,
86 PORT_D,
87 PORT_E,
88 I915_MAX_PORTS
89};
90#define port_name(p) ((p) + 'A')
91
Paulo Zanonib97186f2013-05-03 12:15:36 -030092enum intel_display_power_domain {
93 POWER_DOMAIN_PIPE_A,
94 POWER_DOMAIN_PIPE_B,
95 POWER_DOMAIN_PIPE_C,
96 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
98 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
99 POWER_DOMAIN_TRANSCODER_A,
100 POWER_DOMAIN_TRANSCODER_B,
101 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300102 POWER_DOMAIN_TRANSCODER_EDP,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300103 POWER_DOMAIN_VGA,
Imre Deakbaa70702013-10-25 17:36:48 +0300104 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300105
106 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300107};
108
Imre Deakbddc7642013-10-16 17:25:49 +0300109#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
110
Paulo Zanonib97186f2013-05-03 12:15:36 -0300111#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
112#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
113 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300114#define POWER_DOMAIN_TRANSCODER(tran) \
115 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
116 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300117
Imre Deakbddc7642013-10-16 17:25:49 +0300118#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
119 BIT(POWER_DOMAIN_PIPE_A) | \
120 BIT(POWER_DOMAIN_TRANSCODER_EDP))
Paulo Zanoni6745a2c2013-11-02 21:07:34 -0700121#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
122 BIT(POWER_DOMAIN_PIPE_A) | \
123 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
124 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
Imre Deakbddc7642013-10-16 17:25:49 +0300125
Egbert Eich1d843f92013-02-25 12:06:49 -0500126enum hpd_pin {
127 HPD_NONE = 0,
128 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
129 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
130 HPD_CRT,
131 HPD_SDVO_B,
132 HPD_SDVO_C,
133 HPD_PORT_B,
134 HPD_PORT_C,
135 HPD_PORT_D,
136 HPD_NUM_PINS
137};
138
Chris Wilson2a2d5482012-12-03 11:49:06 +0000139#define I915_GEM_GPU_DOMAINS \
140 (I915_GEM_DOMAIN_RENDER | \
141 I915_GEM_DOMAIN_SAMPLER | \
142 I915_GEM_DOMAIN_COMMAND | \
143 I915_GEM_DOMAIN_INSTRUCTION | \
144 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700145
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700146#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800147
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200148#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
149 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
150 if ((intel_encoder)->base.crtc == (__crtc))
151
Daniel Vettere7b903d2013-06-05 13:34:14 +0200152struct drm_i915_private;
153
Daniel Vettere2b78262013-06-07 23:10:03 +0200154enum intel_dpll_id {
155 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
156 /* real shared dpll ids must be >= 0 */
157 DPLL_ID_PCH_PLL_A,
158 DPLL_ID_PCH_PLL_B,
159};
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100160#define I915_NUM_PLLS 2
161
Daniel Vetter53589012013-06-05 13:34:16 +0200162struct intel_dpll_hw_state {
Daniel Vetter66e985c2013-06-05 13:34:20 +0200163 uint32_t dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +0200164 uint32_t dpll_md;
Daniel Vetter66e985c2013-06-05 13:34:20 +0200165 uint32_t fp0;
166 uint32_t fp1;
Daniel Vetter53589012013-06-05 13:34:16 +0200167};
168
Daniel Vetter46edb022013-06-05 13:34:12 +0200169struct intel_shared_dpll {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 int refcount; /* count of number of CRTCs sharing this PLL */
171 int active; /* count of number of active CRTCs (i.e. DPMS on) */
172 bool on; /* is the PLL actually active? Disabled during modeset */
Daniel Vetter46edb022013-06-05 13:34:12 +0200173 const char *name;
174 /* should match the index in the dev_priv->shared_dplls array */
175 enum intel_dpll_id id;
Daniel Vetter53589012013-06-05 13:34:16 +0200176 struct intel_dpll_hw_state hw_state;
Daniel Vetter15bdd4c2013-06-05 13:34:23 +0200177 void (*mode_set)(struct drm_i915_private *dev_priv,
178 struct intel_shared_dpll *pll);
Daniel Vettere7b903d2013-06-05 13:34:14 +0200179 void (*enable)(struct drm_i915_private *dev_priv,
180 struct intel_shared_dpll *pll);
181 void (*disable)(struct drm_i915_private *dev_priv,
182 struct intel_shared_dpll *pll);
Daniel Vetter53589012013-06-05 13:34:16 +0200183 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
184 struct intel_shared_dpll *pll,
185 struct intel_dpll_hw_state *hw_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100188/* Used by dp and fdi links */
189struct intel_link_m_n {
190 uint32_t tu;
191 uint32_t gmch_m;
192 uint32_t gmch_n;
193 uint32_t link_m;
194 uint32_t link_n;
195};
196
197void intel_link_compute_m_n(int bpp, int nlanes,
198 int pixel_clock, int link_clock,
199 struct intel_link_m_n *m_n);
200
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300201struct intel_ddi_plls {
202 int spll_refcount;
203 int wrpll1_refcount;
204 int wrpll2_refcount;
205};
206
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207/* Interface history:
208 *
209 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100210 * 1.2: Add Power Management
211 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100212 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000213 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000214 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
215 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 */
217#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000218#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219#define DRIVER_PATCHLEVEL 0
220
Chris Wilson23bc5982010-09-29 16:10:57 +0100221#define WATCH_LISTS 0
Chris Wilson42d6ab42012-07-26 11:49:32 +0100222#define WATCH_GTT 0
Eric Anholt673a3942008-07-30 12:06:12 -0700223
Dave Airlie71acb5e2008-12-30 20:31:46 +1000224#define I915_GEM_PHYS_CURSOR_0 1
225#define I915_GEM_PHYS_CURSOR_1 2
226#define I915_GEM_PHYS_OVERLAY_REGS 3
227#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
228
229struct drm_i915_gem_phys_object {
230 int id;
231 struct page **page_list;
232 drm_dma_handle_t *handle;
Chris Wilson05394f32010-11-08 19:18:58 +0000233 struct drm_i915_gem_object *cur_obj;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000234};
235
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700236struct opregion_header;
237struct opregion_acpi;
238struct opregion_swsci;
239struct opregion_asle;
240
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100241struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700242 struct opregion_header __iomem *header;
243 struct opregion_acpi __iomem *acpi;
244 struct opregion_swsci __iomem *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300245 u32 swsci_gbda_sub_functions;
246 u32 swsci_sbcb_sub_functions;
Ben Widawsky5bc44182012-04-16 14:07:42 -0700247 struct opregion_asle __iomem *asle;
248 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000249 u32 __iomem *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200250 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100251};
Chris Wilson44834a62010-08-19 16:09:23 +0100252#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100253
Chris Wilson6ef3d422010-08-04 20:26:07 +0100254struct intel_overlay;
255struct intel_overlay_error_state;
256
Dave Airlie7c1c2872008-11-28 14:22:24 +1000257struct drm_i915_master_private {
258 drm_local_map_t *sarea;
259 struct _drm_i915_sarea *sarea_priv;
260};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800261#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300262#define I915_MAX_NUM_FENCES 32
263/* 32 fences + sign bit for FENCE_REG_NONE */
264#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800265
266struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200267 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000268 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100269 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800270};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000271
yakui_zhao9b9d1722009-05-31 17:17:17 +0800272struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100273 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800274 u8 dvo_port;
275 u8 slave_addr;
276 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100277 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400278 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800279};
280
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000281struct intel_display_error_state;
282
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700283struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200284 struct kref ref;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700285 u32 eir;
286 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700287 u32 ier;
Ben Widawskyb9a39062012-06-04 14:42:52 -0700288 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000289 u32 derrmr;
290 u32 forcewake;
Ben Widawsky9574b3f2012-04-26 16:03:01 -0700291 bool waiting[I915_NUM_RINGS];
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800292 u32 pipestat[I915_MAX_PIPES];
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100293 u32 tail[I915_NUM_RINGS];
294 u32 head[I915_NUM_RINGS];
Chris Wilson0f3b6842013-01-15 12:05:55 +0000295 u32 ctl[I915_NUM_RINGS];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100296 u32 ipeir[I915_NUM_RINGS];
297 u32 ipehr[I915_NUM_RINGS];
298 u32 instdone[I915_NUM_RINGS];
299 u32 acthd[I915_NUM_RINGS];
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100300 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilsondf2b23d2012-11-27 17:06:54 +0000301 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilson12f55812012-07-05 17:14:01 +0100302 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100303 /* our own tracking of ring head and tail */
304 u32 cpu_ring_head[I915_NUM_RINGS];
305 u32 cpu_ring_tail[I915_NUM_RINGS];
Chris Wilson1d8f38f2010-10-29 19:00:51 +0100306 u32 error; /* gen6+ */
Ben Widawsky71e172e2012-08-20 16:15:13 -0700307 u32 err_int; /* gen7 */
Chris Wilson94e39e22013-10-30 09:28:22 +0000308 u32 bbstate[I915_NUM_RINGS];
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100309 u32 instpm[I915_NUM_RINGS];
310 u32 instps[I915_NUM_RINGS];
Ben Widawsky050ee912012-08-22 11:32:15 -0700311 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100312 u32 seqno[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000313 u64 bbaddr;
Daniel Vetter33f3f512011-12-14 13:57:39 +0100314 u32 fault_reg[I915_NUM_RINGS];
315 u32 done_reg;
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100316 u32 faddr[I915_NUM_RINGS];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200317 u64 fence[I915_MAX_NUM_FENCES];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700318 struct timeval time;
Chris Wilson52d39a22012-02-15 11:25:37 +0000319 struct drm_i915_error_ring {
320 struct drm_i915_error_object {
321 int page_count;
322 u32 gtt_offset;
323 u32 *pages[0];
Ben Widawsky8c123e52013-03-04 17:00:29 -0800324 } *ringbuffer, *batchbuffer, *ctx;
Chris Wilson52d39a22012-02-15 11:25:37 +0000325 struct drm_i915_error_request {
326 long jiffies;
327 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000328 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000329 } *requests;
330 int num_requests;
331 } ring[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000332 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000333 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000334 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100335 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000336 u32 gtt_offset;
337 u32 read_domains;
338 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200339 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000340 s32 pinned:2;
341 u32 tiling:2;
342 u32 dirty:1;
343 u32 purgeable:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100344 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100345 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700346 } **active_bo, **pinned_bo;
347 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson6ef3d422010-08-04 20:26:07 +0100348 struct intel_overlay_error_state *overlay;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000349 struct intel_display_error_state *display;
Mika Kuoppalada661462013-09-06 16:03:28 +0300350 int hangcheck_score[I915_NUM_RINGS];
351 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700352};
353
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100354struct intel_crtc_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100355struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200356struct intel_limit;
357struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100358
Jesse Barnese70236a2009-09-21 10:42:27 -0700359struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400360 bool (*fbc_enabled)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700361 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
362 void (*disable_fbc)(struct drm_device *dev);
363 int (*get_display_clock_speed)(struct drm_device *dev);
364 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200365 /**
366 * find_dpll() - Find the best values for the PLL
367 * @limit: limits for the PLL
368 * @crtc: current CRTC
369 * @target: target frequency in kHz
370 * @refclk: reference clock frequency in kHz
371 * @match_clock: if provided, @best_clock P divider must
372 * match the P divider from @match_clock
373 * used for LVDS downclocking
374 * @best_clock: best PLL values found
375 *
376 * Returns true on success, false on failure.
377 */
378 bool (*find_dpll)(const struct intel_limit *limit,
379 struct drm_crtc *crtc,
380 int target, int refclk,
381 struct dpll *match_clock,
382 struct dpll *best_clock);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300383 void (*update_wm)(struct drm_crtc *crtc);
Ville Syrjäläadf3d352013-08-06 22:24:11 +0300384 void (*update_sprite_wm)(struct drm_plane *plane,
385 struct drm_crtc *crtc,
Paulo Zanoni4c4ff432013-05-24 11:59:17 -0300386 uint32_t sprite_width, int pixel_size,
Ville Syrjäläbdd57d02013-07-05 11:57:13 +0300387 bool enable, bool scaled);
Daniel Vetter47fab732012-10-26 10:58:18 +0200388 void (*modeset_global_resources)(struct drm_device *dev);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100389 /* Returns the active state of the crtc, and if the crtc is active,
390 * fills out the pipe-config with the hw state. */
391 bool (*get_pipe_config)(struct intel_crtc *,
392 struct intel_crtc_config *);
Eric Anholtf564048e2011-03-30 13:01:02 -0700393 int (*crtc_mode_set)(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -0700394 int x, int y,
395 struct drm_framebuffer *old_fb);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200396 void (*crtc_enable)(struct drm_crtc *crtc);
397 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100398 void (*off)(struct drm_crtc *crtc);
Wu Fengguange0dac652011-09-05 14:25:34 +0800399 void (*write_eld)(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +0300400 struct drm_crtc *crtc,
401 struct drm_display_mode *mode);
Jesse Barnes674cf962011-04-28 14:27:04 -0700402 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700403 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700404 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
405 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700406 struct drm_i915_gem_object *obj,
407 uint32_t flags);
Jesse Barnes17638cd2011-06-24 12:19:23 -0700408 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
409 int x, int y);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100410 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700411 /* clock updates for mode set */
412 /* cursor updates */
413 /* render clock increase/decrease */
414 /* display clock increase/decrease */
415 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700416};
417
Chris Wilson907b28c2013-07-19 20:36:52 +0100418struct intel_uncore_funcs {
Chris Wilson990bbda2012-07-02 11:51:02 -0300419 void (*force_wake_get)(struct drm_i915_private *dev_priv);
420 void (*force_wake_put)(struct drm_i915_private *dev_priv);
Ben Widawsky0b274482013-10-04 21:22:51 -0700421
422 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
423 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
424 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
425 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
426
427 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
428 uint8_t val, bool trace);
429 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
430 uint16_t val, bool trace);
431 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
432 uint32_t val, bool trace);
433 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
434 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300435};
436
Chris Wilson907b28c2013-07-19 20:36:52 +0100437struct intel_uncore {
438 spinlock_t lock; /** lock is also taken in irq contexts. */
439
440 struct intel_uncore_funcs funcs;
441
442 unsigned fifo_count;
443 unsigned forcewake_count;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100444
445 struct delayed_work force_wake_work;
Chris Wilson907b28c2013-07-19 20:36:52 +0100446};
447
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100448#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
449 func(is_mobile) sep \
450 func(is_i85x) sep \
451 func(is_i915g) sep \
452 func(is_i945gm) sep \
453 func(is_g33) sep \
454 func(need_gfx_hws) sep \
455 func(is_g4x) sep \
456 func(is_pineview) sep \
457 func(is_broadwater) sep \
458 func(is_crestline) sep \
459 func(is_ivybridge) sep \
460 func(is_valleyview) sep \
461 func(is_haswell) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700462 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100463 func(has_fbc) sep \
464 func(has_pipe_cxsr) sep \
465 func(has_hotplug) sep \
466 func(cursor_needs_physical) sep \
467 func(has_overlay) sep \
468 func(overlay_needs_physical) sep \
469 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100470 func(has_llc) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100471 func(has_ddi) sep \
472 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200473
Damien Lespiaua587f772013-04-22 18:40:38 +0100474#define DEFINE_FLAG(name) u8 name:1
475#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200476
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500477struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200478 u32 display_mmio_offset;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700479 u8 num_pipes:3;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000480 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700481 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100482 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500483};
484
Damien Lespiaua587f772013-04-22 18:40:38 +0100485#undef DEFINE_FLAG
486#undef SEP_SEMICOLON
487
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800488enum i915_cache_level {
489 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100490 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
491 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
492 caches, eg sampler/render caches, and the
493 large Last-Level-Cache. LLC is coherent with
494 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100495 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800496};
497
Kenneth Graunke2d04bef2013-04-22 00:53:49 -0700498typedef uint32_t gen6_gtt_pte_t;
499
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700500struct i915_address_space {
Ben Widawsky93bd8642013-07-16 16:50:06 -0700501 struct drm_mm mm;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700502 struct drm_device *dev;
Ben Widawskya7bbbd62013-07-16 16:50:07 -0700503 struct list_head global_link;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700504 unsigned long start; /* Start offset always 0 for dri2 */
505 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
506
507 struct {
508 dma_addr_t addr;
509 struct page *page;
510 } scratch;
511
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700512 /**
513 * List of objects currently involved in rendering.
514 *
515 * Includes buffers having the contents of their GPU caches
516 * flushed, not necessarily primitives. last_rendering_seqno
517 * represents when the rendering involved will be completed.
518 *
519 * A reference is held on the buffer while on this list.
520 */
521 struct list_head active_list;
522
523 /**
524 * LRU list of objects which are not in the ringbuffer and
525 * are ready to unbind, but are still in the GTT.
526 *
527 * last_rendering_seqno is 0 while an object is in this list.
528 *
529 * A reference is not held on the buffer while on this list,
530 * as merely being GTT-bound shouldn't prevent its being
531 * freed, and we'll pull it off the list in the free path.
532 */
533 struct list_head inactive_list;
534
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700535 /* FIXME: Need a more generic return type */
536 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
Ben Widawskyb35b3802013-10-16 09:18:21 -0700537 enum i915_cache_level level,
538 bool valid); /* Create a valid PTE */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700539 void (*clear_range)(struct i915_address_space *vm,
540 unsigned int first_entry,
Ben Widawsky828c7902013-10-16 09:21:30 -0700541 unsigned int num_entries,
542 bool use_scratch);
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700543 void (*insert_entries)(struct i915_address_space *vm,
544 struct sg_table *st,
545 unsigned int first_entry,
546 enum i915_cache_level cache_level);
547 void (*cleanup)(struct i915_address_space *vm);
548};
549
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800550/* The Graphics Translation Table is the way in which GEN hardware translates a
551 * Graphics Virtual Address into a Physical Address. In addition to the normal
552 * collateral associated with any va->pa translations GEN hardware also has a
553 * portion of the GTT which can be mapped by the CPU and remain both coherent
554 * and correct (in cases like swizzling). That region is referred to as GMADR in
555 * the spec.
556 */
557struct i915_gtt {
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700558 struct i915_address_space base;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800559 size_t stolen_size; /* Total size of stolen memory */
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800560
561 unsigned long mappable_end; /* End offset that we can CPU map */
562 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
563 phys_addr_t mappable_base; /* PA of our GMADR */
564
565 /** "Graphics Stolen Memory" holds the global PTEs */
566 void __iomem *gsm;
Ben Widawskya81cc002013-01-18 12:30:31 -0800567
568 bool do_idle_maps;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800569
Ben Widawsky911bdf02013-06-27 16:30:23 -0700570 int mtrr;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800571
572 /* global gtt ops */
Ben Widawskybaa09f52013-01-24 13:49:57 -0800573 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -0800574 size_t *stolen, phys_addr_t *mappable_base,
575 unsigned long *mappable_end);
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800576};
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700577#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
Ben Widawsky5d4545a2013-01-17 12:45:15 -0800578
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100579struct i915_hw_ppgtt {
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700580 struct i915_address_space base;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100581 unsigned num_pd_entries;
Ben Widawsky37aca442013-11-04 20:47:32 -0800582 union {
583 struct page **pt_pages;
584 struct page *gen8_pt_pages;
585 };
586 struct page *pd_pages;
587 int num_pd_pages;
588 int num_pt_pages;
589 union {
590 uint32_t pd_offset;
591 dma_addr_t pd_dma_addr[4];
592 };
593 union {
594 dma_addr_t *pt_dma_addr;
595 dma_addr_t *gen8_pt_dma_addr[4];
596 };
Ben Widawskyb7c36d22013-04-08 18:43:56 -0700597 int (*enable)(struct drm_device *dev);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100598};
599
Ben Widawsky0b02e792013-07-31 17:00:08 -0700600/**
601 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
602 * VMA's presence cannot be guaranteed before binding, or after unbinding the
603 * object into/from the address space.
604 *
605 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
Ben Widawsky2f633152013-07-17 12:19:03 -0700606 * will always be <= an objects lifetime. So object refcounting should cover us.
607 */
608struct i915_vma {
609 struct drm_mm_node node;
610 struct drm_i915_gem_object *obj;
611 struct i915_address_space *vm;
612
Ben Widawskyca191b12013-07-31 17:00:14 -0700613 /** This object's place on the active/inactive lists */
614 struct list_head mm_list;
615
Ben Widawsky2f633152013-07-17 12:19:03 -0700616 struct list_head vma_link; /* Link in the object's VMA list */
Ben Widawsky82a55ad2013-08-14 11:38:34 +0200617
618 /** This vma's place in the batchbuffer or on the eviction list */
619 struct list_head exec_list;
620
Ben Widawsky27173f12013-08-14 11:38:36 +0200621 /**
622 * Used for performing relocations during execbuffer insertion.
623 */
624 struct hlist_node exec_node;
625 unsigned long exec_handle;
626 struct drm_i915_gem_exec_object2 *exec_entry;
627
Daniel Vetter02e792f2009-09-15 22:57:34 +0200628};
629
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300630struct i915_ctx_hang_stats {
631 /* This context had batch pending when hang was declared */
632 unsigned batch_pending;
633
634 /* This context had batch active when hang was declared */
635 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300636
637 /* Time when this context was last blamed for a GPU reset */
638 unsigned long guilty_ts;
639
640 /* This context is banned to submit more work */
641 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300642};
Ben Widawsky40521052012-06-04 14:42:43 -0700643
644/* This must match up with the value previously used for execbuf2.rsvd1. */
645#define DEFAULT_CONTEXT_ID 0
646struct i915_hw_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300647 struct kref ref;
Ben Widawsky40521052012-06-04 14:42:43 -0700648 int id;
Ben Widawskye0556842012-06-04 14:42:46 -0700649 bool is_initialized;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700650 uint8_t remap_slice;
Ben Widawsky40521052012-06-04 14:42:43 -0700651 struct drm_i915_file_private *file_priv;
652 struct intel_ring_buffer *ring;
653 struct drm_i915_gem_object *obj;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300654 struct i915_ctx_hang_stats hang_stats;
Ben Widawskya33afea2013-09-17 21:12:45 -0700655
656 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700657};
658
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700659struct i915_fbc {
660 unsigned long size;
661 unsigned int fb_id;
662 enum plane plane;
663 int y;
664
665 struct drm_mm_node *compressed_fb;
666 struct drm_mm_node *compressed_llb;
667
668 struct intel_fbc_work {
669 struct delayed_work work;
670 struct drm_crtc *crtc;
671 struct drm_framebuffer *fb;
672 int interval;
673 } *fbc_work;
674
Chris Wilson29ebf902013-07-27 17:23:55 +0100675 enum no_fbc_reason {
676 FBC_OK, /* FBC is enabled */
677 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700678 FBC_NO_OUTPUT, /* no outputs enabled to compress */
679 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
680 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
681 FBC_MODE_TOO_LARGE, /* mode too large for compression */
682 FBC_BAD_PLANE, /* fbc not supported on plane */
683 FBC_NOT_TILED, /* buffer not tiled */
684 FBC_MULTIPLE_PIPES, /* more than one pipe active */
685 FBC_MODULE_PARAM,
686 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
687 } no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800688};
689
Rodrigo Vivia031d702013-10-03 16:15:06 -0300690struct i915_psr {
691 bool sink_support;
692 bool source_ok;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300693};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700694
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800695enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300696 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800697 PCH_IBX, /* Ibexpeak PCH */
698 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300699 PCH_LPT, /* Lynxpoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700700 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800701};
702
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200703enum intel_sbi_destination {
704 SBI_ICLK,
705 SBI_MPHY,
706};
707
Jesse Barnesb690e962010-07-19 13:53:12 -0700708#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700709#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100710#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Kamal Mostafae85843b2013-07-19 15:02:01 -0700711#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
Jesse Barnesb690e962010-07-19 13:53:12 -0700712
Dave Airlie8be48d92010-03-30 05:34:14 +0000713struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100714struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000715
Daniel Vetterc2b91522012-02-14 22:37:19 +0100716struct intel_gmbus {
717 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000718 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100719 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100720 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100721 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100722 struct drm_i915_private *dev_priv;
723};
724
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100725struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000726 u8 saveLBB;
727 u32 saveDSPACNTR;
728 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000729 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000730 u32 savePIPEACONF;
731 u32 savePIPEBCONF;
732 u32 savePIPEASRC;
733 u32 savePIPEBSRC;
734 u32 saveFPA0;
735 u32 saveFPA1;
736 u32 saveDPLL_A;
737 u32 saveDPLL_A_MD;
738 u32 saveHTOTAL_A;
739 u32 saveHBLANK_A;
740 u32 saveHSYNC_A;
741 u32 saveVTOTAL_A;
742 u32 saveVBLANK_A;
743 u32 saveVSYNC_A;
744 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000745 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800746 u32 saveTRANS_HTOTAL_A;
747 u32 saveTRANS_HBLANK_A;
748 u32 saveTRANS_HSYNC_A;
749 u32 saveTRANS_VTOTAL_A;
750 u32 saveTRANS_VBLANK_A;
751 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000752 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000753 u32 saveDSPASTRIDE;
754 u32 saveDSPASIZE;
755 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700756 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000757 u32 saveDSPASURF;
758 u32 saveDSPATILEOFF;
759 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700760 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000761 u32 saveBLC_PWM_CTL;
762 u32 saveBLC_PWM_CTL2;
Jesse Barnes07bf1392013-10-31 18:55:50 +0200763 u32 saveBLC_HIST_CTL_B;
764 u32 saveBLC_PWM_CTL_B;
765 u32 saveBLC_PWM_CTL2_B;
Zhenyu Wang42048782009-10-21 15:27:01 +0800766 u32 saveBLC_CPU_PWM_CTL;
767 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000768 u32 saveFPB0;
769 u32 saveFPB1;
770 u32 saveDPLL_B;
771 u32 saveDPLL_B_MD;
772 u32 saveHTOTAL_B;
773 u32 saveHBLANK_B;
774 u32 saveHSYNC_B;
775 u32 saveVTOTAL_B;
776 u32 saveVBLANK_B;
777 u32 saveVSYNC_B;
778 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000779 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800780 u32 saveTRANS_HTOTAL_B;
781 u32 saveTRANS_HBLANK_B;
782 u32 saveTRANS_HSYNC_B;
783 u32 saveTRANS_VTOTAL_B;
784 u32 saveTRANS_VBLANK_B;
785 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000786 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000787 u32 saveDSPBSTRIDE;
788 u32 saveDSPBSIZE;
789 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700790 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000791 u32 saveDSPBSURF;
792 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700793 u32 saveVGA0;
794 u32 saveVGA1;
795 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000796 u32 saveVGACNTRL;
797 u32 saveADPA;
798 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700799 u32 savePP_ON_DELAYS;
800 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000801 u32 saveDVOA;
802 u32 saveDVOB;
803 u32 saveDVOC;
804 u32 savePP_ON;
805 u32 savePP_OFF;
806 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700807 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000808 u32 savePFIT_CONTROL;
809 u32 save_palette_a[256];
810 u32 save_palette_b[256];
Jesse Barnes06027f92009-10-05 13:47:26 -0700811 u32 saveDPFC_CB_BASE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000812 u32 saveFBC_CFB_BASE;
813 u32 saveFBC_LL_BASE;
814 u32 saveFBC_CONTROL;
815 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000816 u32 saveIER;
817 u32 saveIIR;
818 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800819 u32 saveDEIER;
820 u32 saveDEIMR;
821 u32 saveGTIER;
822 u32 saveGTIMR;
823 u32 saveFDI_RXA_IMR;
824 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800825 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800826 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000827 u32 saveSWF0[16];
828 u32 saveSWF1[16];
829 u32 saveSWF2[3];
830 u8 saveMSR;
831 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800832 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000833 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000834 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000835 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000836 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200837 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000838 u32 saveCURACNTR;
839 u32 saveCURAPOS;
840 u32 saveCURABASE;
841 u32 saveCURBCNTR;
842 u32 saveCURBPOS;
843 u32 saveCURBBASE;
844 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700845 u32 saveDP_B;
846 u32 saveDP_C;
847 u32 saveDP_D;
848 u32 savePIPEA_GMCH_DATA_M;
849 u32 savePIPEB_GMCH_DATA_M;
850 u32 savePIPEA_GMCH_DATA_N;
851 u32 savePIPEB_GMCH_DATA_N;
852 u32 savePIPEA_DP_LINK_M;
853 u32 savePIPEB_DP_LINK_M;
854 u32 savePIPEA_DP_LINK_N;
855 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800856 u32 saveFDI_RXA_CTL;
857 u32 saveFDI_TXA_CTL;
858 u32 saveFDI_RXB_CTL;
859 u32 saveFDI_TXB_CTL;
860 u32 savePFA_CTL_1;
861 u32 savePFB_CTL_1;
862 u32 savePFA_WIN_SZ;
863 u32 savePFB_WIN_SZ;
864 u32 savePFA_WIN_POS;
865 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000866 u32 savePCH_DREF_CONTROL;
867 u32 saveDISP_ARB_CTL;
868 u32 savePIPEA_DATA_M1;
869 u32 savePIPEA_DATA_N1;
870 u32 savePIPEA_LINK_M1;
871 u32 savePIPEA_LINK_N1;
872 u32 savePIPEB_DATA_M1;
873 u32 savePIPEB_DATA_N1;
874 u32 savePIPEB_LINK_M1;
875 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000876 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400877 u32 savePCH_PORT_HOTPLUG;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100878};
Daniel Vetterc85aa882012-11-02 19:55:03 +0100879
880struct intel_gen6_power_mgmt {
Daniel Vetter59cdb632013-07-04 23:35:28 +0200881 /* work and pm_iir are protected by dev_priv->irq_lock */
Daniel Vetterc85aa882012-11-02 19:55:03 +0100882 struct work_struct work;
883 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +0200884
Daniel Vetterc85aa882012-11-02 19:55:03 +0100885 /* The below variables an all the rps hw state are protected by
886 * dev->struct mutext. */
887 u8 cur_delay;
888 u8 min_delay;
889 u8 max_delay;
Jesse Barnes52ceb902013-04-23 10:09:26 -0700890 u8 rpe_delay;
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100891 u8 rp1_delay;
892 u8 rp0_delay;
Ben Widawsky31c77382013-04-05 14:29:22 -0700893 u8 hw_max;
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700894
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100895 int last_adj;
896 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
897
Chris Wilsonc0951f02013-10-10 21:58:50 +0100898 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -0700899 struct delayed_work delayed_resume_work;
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700900
901 /*
902 * Protects RPS/RC6 register access and PCU communication.
903 * Must be taken after struct_mutex if nested.
904 */
905 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100906};
907
Daniel Vetter1a240d42012-11-29 22:18:51 +0100908/* defined intel_pm.c */
909extern spinlock_t mchdev_lock;
910
Daniel Vetterc85aa882012-11-02 19:55:03 +0100911struct intel_ilk_power_mgmt {
912 u8 cur_delay;
913 u8 min_delay;
914 u8 max_delay;
915 u8 fmax;
916 u8 fstart;
917
918 u64 last_count1;
919 unsigned long last_time1;
920 unsigned long chipset_power;
921 u64 last_count2;
922 struct timespec last_time2;
923 unsigned long gfx_power;
924 u8 corr;
925
926 int c_m;
927 int r_t;
Daniel Vetter3e373942012-11-02 19:55:04 +0100928
929 struct drm_i915_gem_object *pwrctx;
930 struct drm_i915_gem_object *renderctx;
Daniel Vetterc85aa882012-11-02 19:55:03 +0100931};
932
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800933/* Power well structure for haswell */
934struct i915_power_well {
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800935 /* power well enable/disable usage count */
936 int count;
Wang Xingchaoa38911a2013-05-30 22:07:11 +0800937};
938
Imre Deak83c00f552013-10-25 17:36:47 +0300939#define I915_MAX_POWER_WELLS 1
940
941struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +0300942 /*
943 * Power wells needed for initialization at driver init and suspend
944 * time are on. They are kept on until after the first modeset.
945 */
946 bool init_power_on;
947
Imre Deak83c00f552013-10-25 17:36:47 +0300948 struct mutex lock;
949 struct i915_power_well power_wells[I915_MAX_POWER_WELLS];
950};
951
Daniel Vetter231f42a2012-11-02 19:55:05 +0100952struct i915_dri1_state {
953 unsigned allow_batchbuffer : 1;
954 u32 __iomem *gfx_hws_cpu_addr;
955
956 unsigned int cpp;
957 int back_offset;
958 int front_offset;
959 int current_page;
960 int page_flipping;
961
962 uint32_t counter;
963};
964
Daniel Vetterdb1b76c2013-07-09 16:51:37 +0200965struct i915_ums_state {
966 /**
967 * Flag if the X Server, and thus DRM, is not currently in
968 * control of the device.
969 *
970 * This is set between LeaveVT and EnterVT. It needs to be
971 * replaced with a semaphore. It also needs to be
972 * transitioned away from for kernel modesetting.
973 */
974 int mm_suspended;
975};
976
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700977#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100978struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700979 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100980 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700981 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100982};
983
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100984struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100985 /** Memory allocator for GTT stolen memory */
986 struct drm_mm stolen;
Daniel Vetter4b5aed62012-11-14 17:14:03 +0100987 /** List of all objects in gtt_space. Used to restore gtt
988 * mappings on resume */
989 struct list_head bound_list;
990 /**
991 * List of objects which are not bound to the GTT (thus
992 * are idle and not used by the GPU) but still have
993 * (presumably uncached) pages still attached.
994 */
995 struct list_head unbound_list;
996
997 /** Usable portion of the GTT for GEM */
998 unsigned long stolen_base; /* limited to low memory (32-bit) */
999
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001000 /** PPGTT used for aliasing the PPGTT with the GTT */
1001 struct i915_hw_ppgtt *aliasing_ppgtt;
1002
1003 struct shrinker inactive_shrinker;
1004 bool shrinker_no_lock_stealing;
1005
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001006 /** LRU list of objects with fence regs on them. */
1007 struct list_head fence_list;
1008
1009 /**
1010 * We leave the user IRQ off as much as possible,
1011 * but this means that requests will finish and never
1012 * be retired once the system goes idle. Set a timer to
1013 * fire periodically while the ring is running. When it
1014 * fires, go retire requests.
1015 */
1016 struct delayed_work retire_work;
1017
1018 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001019 * When we detect an idle GPU, we want to turn on
1020 * powersaving features. So once we see that there
1021 * are no more requests outstanding and no more
1022 * arrive within a small period of time, we fire
1023 * off the idle_work.
1024 */
1025 struct delayed_work idle_work;
1026
1027 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001028 * Are we in a non-interruptible section of code like
1029 * modesetting?
1030 */
1031 bool interruptible;
1032
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001033 /** Bit 6 swizzling required for X tiling */
1034 uint32_t bit_6_swizzle_x;
1035 /** Bit 6 swizzling required for Y tiling */
1036 uint32_t bit_6_swizzle_y;
1037
1038 /* storage for physical objects */
1039 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1040
1041 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001042 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001043 size_t object_memory;
1044 u32 object_count;
1045};
1046
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001047struct drm_i915_error_state_buf {
1048 unsigned bytes;
1049 unsigned size;
1050 int err;
1051 u8 *buf;
1052 loff_t start;
1053 loff_t pos;
1054};
1055
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001056struct i915_error_state_file_priv {
1057 struct drm_device *dev;
1058 struct drm_i915_error_state *error;
1059};
1060
Daniel Vetter99584db2012-11-14 17:14:04 +01001061struct i915_gpu_error {
1062 /* For hangcheck timer */
1063#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1064#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001065 /* Hang gpu twice in this window and your context gets banned */
1066#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1067
Daniel Vetter99584db2012-11-14 17:14:04 +01001068 struct timer_list hangcheck_timer;
Daniel Vetter99584db2012-11-14 17:14:04 +01001069
1070 /* For reset and error_state handling. */
1071 spinlock_t lock;
1072 /* Protected by the above dev->gpu_error.lock. */
1073 struct drm_i915_error_state *first_error;
1074 struct work_struct work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001075
Chris Wilson094f9a52013-09-25 17:34:55 +01001076
1077 unsigned long missed_irq_rings;
1078
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001079 /**
Daniel Vetterf69061b2012-12-06 09:01:42 +01001080 * State variable and reset counter controlling the reset flow
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001081 *
Daniel Vetterf69061b2012-12-06 09:01:42 +01001082 * Upper bits are for the reset counter. This counter is used by the
1083 * wait_seqno code to race-free noticed that a reset event happened and
1084 * that it needs to restart the entire ioctl (since most likely the
1085 * seqno it waited for won't ever signal anytime soon).
1086 *
1087 * This is important for lock-free wait paths, where no contended lock
1088 * naturally enforces the correct ordering between the bail-out of the
1089 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001090 *
1091 * Lowest bit controls the reset state machine: Set means a reset is in
1092 * progress. This state will (presuming we don't have any bugs) decay
1093 * into either unset (successful reset) or the special WEDGED value (hw
1094 * terminally sour). All waiters on the reset_queue will be woken when
1095 * that happens.
1096 */
1097 atomic_t reset_counter;
1098
1099 /**
1100 * Special values/flags for reset_counter
1101 *
1102 * Note that the code relies on
1103 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1104 * being true.
1105 */
1106#define I915_RESET_IN_PROGRESS_FLAG 1
1107#define I915_WEDGED 0xffffffff
1108
1109 /**
1110 * Waitqueue to signal when the reset has completed. Used by clients
1111 * that wait for dev_priv->mm.wedged to settle.
1112 */
1113 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001114
Daniel Vetter99584db2012-11-14 17:14:04 +01001115 /* For gpu hang simulation. */
1116 unsigned int stop_rings;
Chris Wilson094f9a52013-09-25 17:34:55 +01001117
1118 /* For missed irq/seqno simulation. */
1119 unsigned int test_irq_rings;
Daniel Vetter99584db2012-11-14 17:14:04 +01001120};
1121
Zhang Ruib8efb172013-02-05 15:41:53 +08001122enum modeset_restore {
1123 MODESET_ON_LID_OPEN,
1124 MODESET_DONE,
1125 MODESET_SUSPENDED,
1126};
1127
Paulo Zanoni6acab152013-09-12 17:06:24 -03001128struct ddi_vbt_port_info {
1129 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001130
1131 uint8_t supports_dvi:1;
1132 uint8_t supports_hdmi:1;
1133 uint8_t supports_dp:1;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001134};
1135
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001136struct intel_vbt_data {
1137 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1138 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1139
1140 /* Feature bits */
1141 unsigned int int_tv_support:1;
1142 unsigned int lvds_dither:1;
1143 unsigned int lvds_vbt:1;
1144 unsigned int int_crt_support:1;
1145 unsigned int lvds_use_ssc:1;
1146 unsigned int display_clock_mode:1;
1147 unsigned int fdi_rx_polarity_inverted:1;
1148 int lvds_ssc_freq;
1149 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1150
1151 /* eDP */
1152 int edp_rate;
1153 int edp_lanes;
1154 int edp_preemphasis;
1155 int edp_vswing;
1156 bool edp_initialized;
1157 bool edp_support;
1158 int edp_bpp;
1159 struct edp_power_seq edp_pps;
1160
Shobhit Kumard17c5442013-08-27 15:12:25 +03001161 /* MIPI DSI */
1162 struct {
1163 u16 panel_id;
1164 } dsi;
1165
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001166 int crt_ddc_pin;
1167
1168 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001169 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001170
1171 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001172};
1173
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001174enum intel_ddb_partitioning {
1175 INTEL_DDB_PART_1_2,
1176 INTEL_DDB_PART_5_6, /* IVB+ */
1177};
1178
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001179struct intel_wm_level {
1180 bool enable;
1181 uint32_t pri_val;
1182 uint32_t spr_val;
1183 uint32_t cur_val;
1184 uint32_t fbc_val;
1185};
1186
Ville Syrjälä609cede2013-10-09 19:18:03 +03001187struct hsw_wm_values {
1188 uint32_t wm_pipe[3];
1189 uint32_t wm_lp[3];
1190 uint32_t wm_lp_spr[3];
1191 uint32_t wm_linetime[3];
1192 bool enable_fbc_wm;
1193 enum intel_ddb_partitioning partitioning;
1194};
1195
Paulo Zanonic67a4702013-08-19 13:18:09 -03001196/*
1197 * This struct tracks the state needed for the Package C8+ feature.
1198 *
1199 * Package states C8 and deeper are really deep PC states that can only be
1200 * reached when all the devices on the system allow it, so even if the graphics
1201 * device allows PC8+, it doesn't mean the system will actually get to these
1202 * states.
1203 *
1204 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1205 * is disabled and the GPU is idle. When these conditions are met, we manually
1206 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1207 * refclk to Fclk.
1208 *
1209 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1210 * the state of some registers, so when we come back from PC8+ we need to
1211 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1212 * need to take care of the registers kept by RC6.
1213 *
1214 * The interrupt disabling is part of the requirements. We can only leave the
1215 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1216 * can lock the machine.
1217 *
1218 * Ideally every piece of our code that needs PC8+ disabled would call
1219 * hsw_disable_package_c8, which would increment disable_count and prevent the
1220 * system from reaching PC8+. But we don't have a symmetric way to do this for
1221 * everything, so we have the requirements_met and gpu_idle variables. When we
1222 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1223 * increase it in the opposite case. The requirements_met variable is true when
1224 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1225 * variable is true when the GPU is idle.
1226 *
1227 * In addition to everything, we only actually enable PC8+ if disable_count
1228 * stays at zero for at least some seconds. This is implemented with the
1229 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1230 * consecutive times when all screens are disabled and some background app
1231 * queries the state of our connectors, or we have some application constantly
1232 * waking up to use the GPU. Only after the enable_work function actually
1233 * enables PC8+ the "enable" variable will become true, which means that it can
1234 * be false even if disable_count is 0.
1235 *
1236 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1237 * goes back to false exactly before we reenable the IRQs. We use this variable
1238 * to check if someone is trying to enable/disable IRQs while they're supposed
1239 * to be disabled. This shouldn't happen and we'll print some error messages in
1240 * case it happens, but if it actually happens we'll also update the variables
1241 * inside struct regsave so when we restore the IRQs they will contain the
1242 * latest expected values.
1243 *
1244 * For more, read "Display Sequences for Package C8" on our documentation.
1245 */
1246struct i915_package_c8 {
1247 bool requirements_met;
1248 bool gpu_idle;
1249 bool irqs_disabled;
1250 /* Only true after the delayed work task actually enables it. */
1251 bool enabled;
1252 int disable_count;
1253 struct mutex lock;
1254 struct delayed_work enable_work;
1255
1256 struct {
1257 uint32_t deimr;
1258 uint32_t sdeimr;
1259 uint32_t gtimr;
1260 uint32_t gtier;
1261 uint32_t gen6_pmimr;
1262 } regsave;
1263};
1264
Daniel Vetter926321d2013-10-16 13:30:34 +02001265enum intel_pipe_crc_source {
1266 INTEL_PIPE_CRC_SOURCE_NONE,
1267 INTEL_PIPE_CRC_SOURCE_PLANE1,
1268 INTEL_PIPE_CRC_SOURCE_PLANE2,
1269 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001270 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001271 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1272 INTEL_PIPE_CRC_SOURCE_TV,
1273 INTEL_PIPE_CRC_SOURCE_DP_B,
1274 INTEL_PIPE_CRC_SOURCE_DP_C,
1275 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001276 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001277 INTEL_PIPE_CRC_SOURCE_MAX,
1278};
1279
Shuang He8bf1e9f2013-10-15 18:55:27 +01001280struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001281 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001282 uint32_t crc[5];
1283};
1284
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001285#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001286struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001287 spinlock_t lock;
1288 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001289 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001290 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001291 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001292 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001293};
1294
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001295typedef struct drm_i915_private {
1296 struct drm_device *dev;
Chris Wilson42dcedd2012-11-15 11:32:30 +00001297 struct kmem_cache *slab;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001298
1299 const struct intel_device_info *info;
1300
1301 int relative_constants_mode;
1302
1303 void __iomem *regs;
1304
Chris Wilson907b28c2013-07-19 20:36:52 +01001305 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001306
1307 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1308
Daniel Vetter28c70f12012-12-01 13:53:45 +01001309
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001310 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1311 * controller on different i2c buses. */
1312 struct mutex gmbus_mutex;
1313
1314 /**
1315 * Base address of the gmbus and gpio block.
1316 */
1317 uint32_t gpio_mmio_base;
1318
Daniel Vetter28c70f12012-12-01 13:53:45 +01001319 wait_queue_head_t gmbus_wait_queue;
1320
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001321 struct pci_dev *bridge_dev;
1322 struct intel_ring_buffer ring[I915_NUM_RINGS];
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001323 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001324
1325 drm_dma_handle_t *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001326 struct resource mch_res;
1327
1328 atomic_t irq_received;
1329
1330 /* protects the irq masks */
1331 spinlock_t irq_lock;
1332
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001333 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1334 struct pm_qos_request pm_qos;
1335
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001336 /* DPIO indirect register protection */
Daniel Vetter09153002012-12-12 14:06:44 +01001337 struct mutex dpio_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001338
1339 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001340 union {
1341 u32 irq_mask;
1342 u32 de_irq_mask[I915_MAX_PIPES];
1343 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001344 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001345 u32 pm_irq_mask;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001346
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001347 struct work_struct hotplug_work;
Daniel Vetter52d7ece2012-12-01 21:03:22 +01001348 bool enable_hotplug_processing;
Egbert Eichb543fb02013-04-16 13:36:54 +02001349 struct {
1350 unsigned long hpd_last_jiffies;
1351 int hpd_cnt;
1352 enum {
1353 HPD_ENABLED = 0,
1354 HPD_DISABLED = 1,
1355 HPD_MARK_DISABLED = 2
1356 } hpd_mark;
1357 } hpd_stats[HPD_NUM_PINS];
Egbert Eich142e2392013-04-11 15:57:57 +02001358 u32 hpd_event_bits;
Egbert Eichac4c16c2013-04-16 13:36:58 +02001359 struct timer_list hotplug_reenable_timer;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001360
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001361 int num_plane;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001362
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001363 struct i915_fbc fbc;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001364 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001365 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001366
1367 /* overlay */
1368 struct intel_overlay *overlay;
Ville Syrjälä2c6602d2013-02-08 23:13:35 +02001369 unsigned int sprite_scaling_enabled;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001370
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001371 /* backlight */
1372 struct {
1373 int level;
1374 bool enabled;
Jani Nikula8ba2d182013-04-12 15:18:37 +03001375 spinlock_t lock; /* bl registers and the above bl fields */
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001376 struct backlight_device *device;
1377 } backlight;
1378
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001379 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001380 bool no_aux_handshake;
1381
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001382 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1383 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1384 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1385
1386 unsigned int fsb_freq, mem_freq, is_ddr3;
1387
Daniel Vetter645416f2013-09-02 16:22:25 +02001388 /**
1389 * wq - Driver workqueue for GEM.
1390 *
1391 * NOTE: Work items scheduled here are not allowed to grab any modeset
1392 * locks, for otherwise the flushing done in the pageflip code will
1393 * result in deadlocks.
1394 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001395 struct workqueue_struct *wq;
1396
1397 /* Display functions */
1398 struct drm_i915_display_funcs display;
1399
1400 /* PCH chipset type */
1401 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001402 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001403
1404 unsigned long quirks;
1405
Zhang Ruib8efb172013-02-05 15:41:53 +08001406 enum modeset_restore modeset_restore;
1407 struct mutex modeset_restore_lock;
Eric Anholt673a3942008-07-30 12:06:12 -07001408
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001409 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001410 struct i915_gtt gtt; /* VMA representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001411
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001412 struct i915_gem_mm mm;
Daniel Vetter87813422012-05-02 11:49:32 +02001413
Daniel Vetter87813422012-05-02 11:49:32 +02001414 /* Kernel Modesetting */
1415
yakui_zhao9b9d1722009-05-31 17:17:17 +08001416 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001417
Jesse Barnes27f82272011-09-02 12:54:37 -07001418 struct drm_crtc *plane_to_crtc_mapping[3];
1419 struct drm_crtc *pipe_to_crtc_mapping[3];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001420 wait_queue_head_t pending_flip_queue;
1421
Daniel Vetterc4597872013-10-21 21:04:07 +02001422#ifdef CONFIG_DEBUG_FS
1423 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1424#endif
1425
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001426 int num_shared_dpll;
1427 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Paulo Zanoni6441ab52012-10-05 12:05:58 -03001428 struct intel_ddi_plls ddi_plls;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001429
Jesse Barnes652c3932009-08-17 13:31:43 -07001430 /* Reclocking support */
1431 bool render_reclock_avail;
1432 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +00001433 /* indicates the reduced downclock for LVDS*/
1434 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -07001435 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001436
Zhenyu Wangc48044112009-12-17 14:48:43 +08001437 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001438
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001439 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001440
Ben Widawsky59124502013-07-04 11:02:05 -07001441 /* Cannot be determined by PCIID. You must always read a register. */
1442 size_t ellc_size;
1443
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001444 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001445 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001446
Daniel Vetter20e4d402012-08-08 23:35:39 +02001447 /* ilk-only ips/rps state. Everything in here is protected by the global
1448 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001449 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001450
Imre Deak83c00f552013-10-25 17:36:47 +03001451 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001452
Rodrigo Vivia031d702013-10-03 16:15:06 -03001453 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001454
Daniel Vetter99584db2012-11-14 17:14:04 +01001455 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001456
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001457 struct drm_i915_gem_object *vlv_pctx;
1458
Daniel Vetter4520f532013-10-09 09:18:51 +02001459#ifdef CONFIG_DRM_I915_FBDEV
Dave Airlie8be48d92010-03-30 05:34:14 +00001460 /* list of fbdev register on this device */
1461 struct intel_fbdev *fbdev;
Daniel Vetter4520f532013-10-09 09:18:51 +02001462#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001463
Jesse Barnes073f34d2012-11-02 11:13:59 -07001464 /*
1465 * The console may be contended at resume, but we don't
1466 * want it to block on it.
1467 */
1468 struct work_struct console_resume_work;
1469
Chris Wilsone953fd72011-02-21 22:23:52 +00001470 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001471 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001472
Ben Widawsky254f9652012-06-04 14:42:42 -07001473 bool hw_contexts_disabled;
1474 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001475 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001476
Damien Lespiau3e683202012-12-11 18:48:29 +00001477 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001478
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001479 struct i915_suspend_saved_registers regfile;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001480
Ville Syrjälä53615a52013-08-01 16:18:50 +03001481 struct {
1482 /*
1483 * Raw watermark latency values:
1484 * in 0.1us units for WM0,
1485 * in 0.5us units for WM1+.
1486 */
1487 /* primary */
1488 uint16_t pri_latency[5];
1489 /* sprite */
1490 uint16_t spr_latency[5];
1491 /* cursor */
1492 uint16_t cur_latency[5];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001493
1494 /* current hardware state */
1495 struct hsw_wm_values hw;
Ville Syrjälä53615a52013-08-01 16:18:50 +03001496 } wm;
1497
Paulo Zanonic67a4702013-08-19 13:18:09 -03001498 struct i915_package_c8 pc8;
1499
Daniel Vetter231f42a2012-11-02 19:55:05 +01001500 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1501 * here! */
1502 struct i915_dri1_state dri1;
Daniel Vetterdb1b76c2013-07-09 16:51:37 +02001503 /* Old ums support infrastructure, same warning applies. */
1504 struct i915_ums_state ums;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505} drm_i915_private_t;
1506
Chris Wilson2c1792a2013-08-01 18:39:55 +01001507static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1508{
1509 return dev->dev_private;
1510}
1511
Chris Wilsonb4519512012-05-11 14:29:30 +01001512/* Iterate over initialised rings */
1513#define for_each_ring(ring__, dev_priv__, i__) \
1514 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1515 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1516
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001517enum hdmi_force_audio {
1518 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1519 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1520 HDMI_AUDIO_AUTO, /* trust EDID */
1521 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1522};
1523
Daniel Vetter190d6cd2013-07-04 13:06:28 +02001524#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00001525
Chris Wilson37e680a2012-06-07 15:38:42 +01001526struct drm_i915_gem_object_ops {
1527 /* Interface between the GEM object and its backing storage.
1528 * get_pages() is called once prior to the use of the associated set
1529 * of pages before to binding them into the GTT, and put_pages() is
1530 * called after we no longer need them. As we expect there to be
1531 * associated cost with migrating pages between the backing storage
1532 * and making them available for the GPU (e.g. clflush), we may hold
1533 * onto the pages after they are no longer referenced by the GPU
1534 * in case they may be used again shortly (for example migrating the
1535 * pages to a different memory domain within the GTT). put_pages()
1536 * will therefore most likely be called when the object itself is
1537 * being released or under memory pressure (where we attempt to
1538 * reap pages for the shrinker).
1539 */
1540 int (*get_pages)(struct drm_i915_gem_object *);
1541 void (*put_pages)(struct drm_i915_gem_object *);
1542};
1543
Eric Anholt673a3942008-07-30 12:06:12 -07001544struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00001545 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07001546
Chris Wilson37e680a2012-06-07 15:38:42 +01001547 const struct drm_i915_gem_object_ops *ops;
1548
Ben Widawsky2f633152013-07-17 12:19:03 -07001549 /** List of VMAs backed by this object */
1550 struct list_head vma_list;
1551
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00001552 /** Stolen memory for this object, instead of being backed by shmem. */
1553 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07001554 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001555
Chris Wilson69dc4982010-10-19 10:36:51 +01001556 struct list_head ring_list;
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02001557 /** Used in execbuf to temporarily hold a ref */
1558 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07001559
1560 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01001561 * This is set if the object is on the active lists (has pending
1562 * rendering and so a non-zero seqno), and is not set if it i s on
1563 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07001564 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001565 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -07001566
1567 /**
1568 * This is set if the object has been written to since last bound
1569 * to the GTT
1570 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001571 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001572
1573 /**
1574 * Fence register bits (if any) for this object. Will be set
1575 * as needed when mapped into the GTT.
1576 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02001577 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02001578 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02001579
1580 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001581 * Advice: are the backing pages purgeable?
1582 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001583 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02001584
1585 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02001586 * Current tiling mode for the object.
1587 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001588 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01001589 /**
1590 * Whether the tiling parameters for the currently associated fence
1591 * register have changed. Note that for the purposes of tracking
1592 * tiling changes we also treat the unfenced register, the register
1593 * slot that the object occupies whilst it executes a fenced
1594 * command (such as BLT on gen2/3), as a "fence".
1595 */
1596 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02001597
1598 /** How many users have pinned this object in GTT space. The following
1599 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1600 * (via user_pin_count), execbuffer (objects are not allowed multiple
1601 * times for the same batchbuffer), and the framebuffer code. When
1602 * switching/pageflipping, the framebuffer code has at most two buffers
1603 * pinned per crtc.
1604 *
1605 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1606 * bits with absolutely no headroom. So use 4 bits. */
Akshay Joshi0206e352011-08-16 15:34:10 -04001607 unsigned int pin_count:4;
Daniel Vetter778c3542010-05-13 11:49:44 +02001608#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
Eric Anholt673a3942008-07-30 12:06:12 -07001609
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001610 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01001611 * Is the object at the current location in the gtt mappable and
1612 * fenceable? Used to avoid costly recalculations.
1613 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001614 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01001615
1616 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001617 * Whether the current gtt mapping needs to be mappable (and isn't just
1618 * mappable by accident). Track pin and fault separate for a more
1619 * accurate mappable working set.
1620 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001621 unsigned int fault_mappable:1;
1622 unsigned int pin_mappable:1;
Chris Wilsoncc98b412013-08-09 12:25:09 +01001623 unsigned int pin_display:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001624
Chris Wilsoncaea7472010-11-12 13:53:37 +00001625 /*
1626 * Is the GPU currently using a fence to access this buffer,
1627 */
1628 unsigned int pending_fenced_gpu_access:1;
1629 unsigned int fenced_gpu_access:1;
1630
Chris Wilson651d7942013-08-08 14:41:10 +01001631 unsigned int cache_level:3;
Chris Wilson93dfb402011-03-29 16:59:50 -07001632
Daniel Vetter7bddb012012-02-09 17:15:47 +01001633 unsigned int has_aliasing_ppgtt_mapping:1;
Daniel Vetter74898d72012-02-15 23:50:22 +01001634 unsigned int has_global_gtt_mapping:1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001635 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001636
Chris Wilson9da3da62012-06-01 15:20:22 +01001637 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001638 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001639
Daniel Vetter1286ff72012-05-10 15:25:09 +02001640 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001641 void *dma_buf_vmapping;
1642 int vmapping_count;
1643
Chris Wilsoncaea7472010-11-12 13:53:37 +00001644 struct intel_ring_buffer *ring;
1645
Chris Wilson1c293ea2012-04-17 15:31:27 +01001646 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001647 uint32_t last_read_seqno;
1648 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001649 /** Breadcrumb of last fenced GPU access to the buffer. */
1650 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001651
Daniel Vetter778c3542010-05-13 11:49:44 +02001652 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001653 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001654
Daniel Vetter80075d42013-10-09 21:23:52 +02001655 /** References from framebuffers, locks out tiling changes. */
1656 unsigned long framebuffer_references;
1657
Eric Anholt280b7132009-03-12 16:56:27 -07001658 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001659 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001660
Jesse Barnes79e53942008-11-07 14:24:08 -08001661 /** User space pin count and filp owning the pin */
Daniel Vetteraa5f8022013-10-10 14:46:37 +02001662 unsigned long user_pin_count;
Jesse Barnes79e53942008-11-07 14:24:08 -08001663 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001664
1665 /** for phy allocated objects */
1666 struct drm_i915_gem_phys_object *phys_obj;
Eric Anholt673a3942008-07-30 12:06:12 -07001667};
Daniel Vetterb45305f2012-12-17 16:21:27 +01001668#define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
Eric Anholt673a3942008-07-30 12:06:12 -07001669
Daniel Vetter62b8b212010-04-09 19:05:08 +00001670#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001671
Eric Anholt673a3942008-07-30 12:06:12 -07001672/**
1673 * Request queue structure.
1674 *
1675 * The request queue allows us to note sequence numbers that have been emitted
1676 * and may be associated with active buffers to be retired.
1677 *
1678 * By keeping this list, we can avoid having to do questionable
1679 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1680 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1681 */
1682struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001683 /** On Which ring this request was generated */
1684 struct intel_ring_buffer *ring;
1685
Eric Anholt673a3942008-07-30 12:06:12 -07001686 /** GEM sequence number associated with this request. */
1687 uint32_t seqno;
1688
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001689 /** Position in the ringbuffer of the start of the request */
1690 u32 head;
1691
1692 /** Position in the ringbuffer of the end of the request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00001693 u32 tail;
1694
Mika Kuoppala0e50e962013-05-02 16:48:08 +03001695 /** Context related to this request */
1696 struct i915_hw_context *ctx;
1697
Mika Kuoppala7d736f42013-06-12 15:01:39 +03001698 /** Batch buffer related to this request if any */
1699 struct drm_i915_gem_object *batch_obj;
1700
Eric Anholt673a3942008-07-30 12:06:12 -07001701 /** Time at which this request was emitted, in jiffies. */
1702 unsigned long emitted_jiffies;
1703
Eric Anholtb9624422009-06-03 07:27:35 +00001704 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07001705 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00001706
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001707 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00001708 /** file_priv list entry for this request */
1709 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001710};
1711
1712struct drm_i915_file_private {
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001713 struct drm_i915_private *dev_priv;
1714
Eric Anholt673a3942008-07-30 12:06:12 -07001715 struct {
Luis R. Rodriguez99057c82012-11-29 12:45:06 -08001716 spinlock_t lock;
Eric Anholtb9624422009-06-03 07:27:35 +00001717 struct list_head request_list;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001718 struct delayed_work idle_work;
Eric Anholt673a3942008-07-30 12:06:12 -07001719 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07001720 struct idr context_idr;
Mika Kuoppalae59ec132013-06-12 12:35:28 +03001721
1722 struct i915_ctx_hang_stats hang_stats;
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001723 atomic_t rps_wait_boost;
Eric Anholt673a3942008-07-30 12:06:12 -07001724};
1725
Chris Wilson2c1792a2013-08-01 18:39:55 +01001726#define INTEL_INFO(dev) (to_i915(dev)->info)
Zou Nan haicae58522010-11-09 17:17:32 +08001727
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001728#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1729#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08001730#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001731#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08001732#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001733#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1734#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08001735#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1736#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1737#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001738#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08001739#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001740#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1741#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08001742#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1743#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001744#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07001745#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001746#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1747 (dev)->pdev->device == 0x0152 || \
1748 (dev)->pdev->device == 0x015a)
1749#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1750 (dev)->pdev->device == 0x0106 || \
1751 (dev)->pdev->device == 0x010A)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07001752#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03001753#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Paulo Zanoni4e8058a2013-11-02 21:07:31 -07001754#define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
Zou Nan haicae58522010-11-09 17:17:32 +08001755#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03001756#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001757 ((dev)->pdev->device & 0xFF00) == 0x0C00)
Paulo Zanonid567b072012-11-20 13:27:43 -02001758#define IS_ULT(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001759 ((dev)->pdev->device & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03001760#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Ville Syrjäläffbab09b2013-10-04 14:53:40 +03001761 ((dev)->pdev->device & 0x00F0) == 0x0020)
Ben Widawskyb833d682013-08-23 16:00:07 -07001762#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08001763
Jesse Barnes85436692011-04-06 12:11:14 -07001764/*
1765 * The genX designation typically refers to the render engine, so render
1766 * capability related checks should use IS_GEN, while display and other checks
1767 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1768 * chips, etc.).
1769 */
Zou Nan haicae58522010-11-09 17:17:32 +08001770#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1771#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1772#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1773#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1774#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07001775#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07001776#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Zou Nan haicae58522010-11-09 17:17:32 +08001777
Ben Widawsky73ae4782013-10-15 10:02:57 -07001778#define RENDER_RING (1<<RCS)
1779#define BSD_RING (1<<VCS)
1780#define BLT_RING (1<<BCS)
1781#define VEBOX_RING (1<<VECS)
1782#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1783#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1784#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02001785#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Chris Wilson651d7942013-08-08 14:41:10 +01001786#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08001787#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1788
Ben Widawsky254f9652012-06-04 14:42:42 -07001789#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Jesse Barnes93553602012-06-15 11:55:23 -07001790#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001791
Chris Wilson05394f32010-11-08 19:18:58 +00001792#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08001793#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1794
Daniel Vetterb45305f2012-12-17 16:21:27 +01001795/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1796#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1797
Zou Nan haicae58522010-11-09 17:17:32 +08001798/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1799 * rows, which changed the alignment requirements and fence programming.
1800 */
1801#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1802 IS_I915GM(dev)))
1803#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1804#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1805#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
Zou Nan haicae58522010-11-09 17:17:32 +08001806#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1807#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08001808
1809#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1810#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1811#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08001812
Ben Widawsky2a114cc2013-11-02 21:07:47 -07001813#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01001814
Damien Lespiaudd93be52013-04-22 18:40:39 +01001815#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Paulo Zanoni6745a2c2013-11-02 21:07:34 -07001816#define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
Damien Lespiau30568c42013-04-22 18:40:41 +01001817#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Ben Widawskyed8546a2013-11-04 22:45:05 -08001818#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
Chris Wilson7c6c2652013-11-18 18:32:37 -08001819#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001820
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001821#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1822#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1823#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1824#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1825#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1826#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1827
Chris Wilson2c1792a2013-08-01 18:39:55 +01001828#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001829#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08001830#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1831#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07001832#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03001833#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08001834
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001835/* DPF == dynamic parity feature */
1836#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1837#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07001838
Ben Widawskyc8735b02012-09-07 19:43:39 -07001839#define GT_FREQUENCY_MULTIPLIER 50
1840
Chris Wilson05394f32010-11-08 19:18:58 +00001841#include "i915_trace.h"
1842
Rob Clarkbaa70942013-08-02 13:27:49 -04001843extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10001844extern int i915_max_ioctl;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001845extern unsigned int i915_fbpercrtc __always_unused;
1846extern int i915_panel_ignore_lid __read_mostly;
1847extern unsigned int i915_powersave __read_mostly;
Eugeni Dodonovf45b5552011-12-09 17:16:37 -08001848extern int i915_semaphores __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001849extern unsigned int i915_lvds_downclock __read_mostly;
Takashi Iwai121d5272012-03-20 13:07:06 +01001850extern int i915_lvds_channel_mode __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001851extern int i915_panel_use_ssc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001852extern int i915_vbt_sdvo_panel_type __read_mostly;
Keith Packardc0f372b32011-11-16 22:24:52 -08001853extern int i915_enable_rc6 __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001854extern int i915_enable_fbc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001855extern bool i915_enable_hangcheck __read_mostly;
Daniel Vetter650dc072012-04-02 10:08:35 +02001856extern int i915_enable_ppgtt __read_mostly;
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001857extern int i915_enable_psr __read_mostly;
Rodrigo Vivi0a3af262012-10-15 17:16:23 -03001858extern unsigned int i915_preliminary_hw_support __read_mostly;
Paulo Zanoni2124b722013-03-22 14:07:23 -03001859extern int i915_disable_power_well __read_mostly;
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03001860extern int i915_enable_ips __read_mostly;
Jesse Barnes2385bdf2013-06-26 01:38:15 +03001861extern bool i915_fastboot __read_mostly;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001862extern int i915_enable_pc8 __read_mostly;
Paulo Zanoni90058742013-08-19 13:18:11 -03001863extern int i915_pc8_timeout __read_mostly;
Xiong Zhang0b74b502013-07-19 13:51:24 +08001864extern bool i915_prefault_disable __read_mostly;
Dave Airlieb3a83632005-09-30 18:37:36 +10001865
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001866extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1867extern int i915_resume(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001868extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1869extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1870
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871 /* i915_dma.c */
Daniel Vetterd05c6172012-04-26 23:28:09 +02001872void i915_update_dri1_breadcrumb(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001873extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +11001874extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001875extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -07001876extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001877extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10001878extern void i915_driver_preclose(struct drm_device *dev,
1879 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001880extern void i915_driver_postclose(struct drm_device *dev,
1881 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001882extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001883#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11001884extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1885 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001886#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001887extern int i915_emit_box(struct drm_device *dev,
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001888 struct drm_clip_rect *box,
1889 int DR1, int DR4);
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07001890extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02001891extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001892extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1893extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1894extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1895extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1896
Jesse Barnes073f34d2012-11-02 11:13:59 -07001897extern void intel_console_resume(struct work_struct *work);
Dave Airlieaf6061a2008-05-07 12:15:39 +10001898
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03001900void i915_queue_hangcheck(struct drm_device *dev);
Chris Wilson527f9e92010-11-11 01:16:58 +00001901void i915_handle_error(struct drm_device *dev, bool wedged);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001902
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001903extern void intel_irq_init(struct drm_device *dev);
Ben Widawskye1b4d302013-07-30 16:27:57 -07001904extern void intel_pm_init(struct drm_device *dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01001905extern void intel_hpd_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01001906extern void intel_pm_init(struct drm_device *dev);
1907
1908extern void intel_uncore_sanitize(struct drm_device *dev);
1909extern void intel_uncore_early_sanitize(struct drm_device *dev);
1910extern void intel_uncore_init(struct drm_device *dev);
Chris Wilson907b28c2013-07-19 20:36:52 +01001911extern void intel_uncore_clear_errors(struct drm_device *dev);
1912extern void intel_uncore_check_errors(struct drm_device *dev);
Chris Wilsonaec347a2013-08-26 13:46:09 +01001913extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001914
Keith Packard7c463582008-11-04 02:03:27 -08001915void
Daniel Vetter3b6c42e2013-10-21 18:04:35 +02001916i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
Keith Packard7c463582008-11-04 02:03:27 -08001917
1918void
Daniel Vetter3b6c42e2013-10-21 18:04:35 +02001919i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
Keith Packard7c463582008-11-04 02:03:27 -08001920
Eric Anholt673a3942008-07-30 12:06:12 -07001921/* i915_gem.c */
1922int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1923 struct drm_file *file_priv);
1924int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1925 struct drm_file *file_priv);
1926int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1927 struct drm_file *file_priv);
1928int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1929 struct drm_file *file_priv);
1930int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1931 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001932int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1933 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001934int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1935 struct drm_file *file_priv);
1936int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1937 struct drm_file *file_priv);
1938int i915_gem_execbuffer(struct drm_device *dev, void *data,
1939 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05001940int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1941 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001942int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *file_priv);
1944int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1945 struct drm_file *file_priv);
1946int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1947 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07001948int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1949 struct drm_file *file);
1950int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1951 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001952int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1953 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001954int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1955 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001956int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1957 struct drm_file *file_priv);
1958int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *file_priv);
1960int i915_gem_set_tiling(struct drm_device *dev, void *data,
1961 struct drm_file *file_priv);
1962int i915_gem_get_tiling(struct drm_device *dev, void *data,
1963 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -07001964int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07001966int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1967 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001968void i915_gem_load(struct drm_device *dev);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001969void *i915_gem_object_alloc(struct drm_device *dev);
1970void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01001971void i915_gem_object_init(struct drm_i915_gem_object *obj,
1972 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00001973struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1974 size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07001975void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07001976void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00001977
Chris Wilson20217462010-11-23 15:26:33 +00001978int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
Ben Widawskyc37e2202013-07-31 16:59:58 -07001979 struct i915_address_space *vm,
Chris Wilson20217462010-11-23 15:26:33 +00001980 uint32_t alignment,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001981 bool map_and_fenceable,
1982 bool nonblocking);
Chris Wilson05394f32010-11-08 19:18:58 +00001983void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07001984int __must_check i915_vma_unbind(struct i915_vma *vma);
1985int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
Chris Wilsondd624af2013-01-15 12:39:35 +00001986int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001987void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001988void i915_gem_lastclose(struct drm_device *dev);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001989
Chris Wilson37e680a2012-06-07 15:38:42 +01001990int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01001991static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1992{
Imre Deak67d5a502013-02-18 19:28:02 +02001993 struct sg_page_iter sg_iter;
Chris Wilson1cf83782012-10-10 12:11:52 +01001994
Imre Deak67d5a502013-02-18 19:28:02 +02001995 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
Imre Deak2db76d72013-03-26 15:14:18 +02001996 return sg_page_iter_page(&sg_iter);
Imre Deak67d5a502013-02-18 19:28:02 +02001997
1998 return NULL;
Chris Wilson9da3da62012-06-01 15:20:22 +01001999}
Chris Wilsona5570172012-09-04 21:02:54 +01002000static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2001{
2002 BUG_ON(obj->pages == NULL);
2003 obj->pages_pin_count++;
2004}
2005static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2006{
2007 BUG_ON(obj->pages_pin_count == 0);
2008 obj->pages_pin_count--;
2009}
2010
Chris Wilson54cf91d2010-11-25 18:00:26 +00002011int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002012int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2013 struct intel_ring_buffer *to);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002014void i915_vma_move_to_active(struct i915_vma *vma,
2015 struct intel_ring_buffer *ring);
Dave Airlieff72145b2011-02-07 12:16:14 +10002016int i915_gem_dumb_create(struct drm_file *file_priv,
2017 struct drm_device *dev,
2018 struct drm_mode_create_dumb *args);
2019int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2020 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002021/**
2022 * Returns true if seq1 is later than seq2.
2023 */
2024static inline bool
2025i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2026{
2027 return (int32_t)(seq1 - seq2) >= 0;
2028}
2029
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002030int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2031int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson06d98132012-04-17 15:31:24 +01002032int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00002033int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00002034
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002035static inline bool
Chris Wilson1690e1e2011-12-14 13:57:08 +01002036i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2037{
2038 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2039 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2040 dev_priv->fence_regs[obj->fence_reg].pin_count++;
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002041 return true;
2042 } else
2043 return false;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002044}
2045
2046static inline void
2047i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2048{
2049 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2050 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsonb8c3af72013-06-12 11:29:47 +01002051 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002052 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2053 }
2054}
2055
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002056bool i915_gem_retire_requests(struct drm_device *dev);
Chris Wilsona71d8d92012-02-15 11:25:36 +00002057void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
Daniel Vetter33196de2012-11-14 17:14:05 +01002058int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02002059 bool interruptible);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002060static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2061{
2062 return unlikely(atomic_read(&error->reset_counter)
2063 & I915_RESET_IN_PROGRESS_FLAG);
2064}
2065
2066static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2067{
2068 return atomic_read(&error->reset_counter) == I915_WEDGED;
2069}
Chris Wilsona71d8d92012-02-15 11:25:36 +00002070
Chris Wilson069efc12010-09-30 16:53:18 +01002071void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01002072bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilsona8198ee2011-04-13 22:04:09 +01002073int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01002074int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002075int __must_check i915_gem_init_hw(struct drm_device *dev);
Ben Widawskyc3787e22013-09-17 21:12:44 -07002076int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01002077void i915_gem_init_swizzling(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002078void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07002079int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01002080int __must_check i915_gem_suspend(struct drm_device *dev);
Mika Kuoppala0025c072013-06-12 12:35:30 +03002081int __i915_add_request(struct intel_ring_buffer *ring,
2082 struct drm_file *file,
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002083 struct drm_i915_gem_object *batch_obj,
Mika Kuoppala0025c072013-06-12 12:35:30 +03002084 u32 *seqno);
2085#define i915_add_request(ring, seqno) \
Dan Carpenter854c94a2013-06-18 10:29:58 +03002086 __i915_add_request(ring, NULL, NULL, seqno)
Ben Widawsky199b2bc2012-05-24 15:03:11 -07002087int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2088 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002089int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00002090int __must_check
2091i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2092 bool write);
2093int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02002094i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2095int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002096i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2097 u32 alignment,
Chris Wilson20217462010-11-23 15:26:33 +00002098 struct intel_ring_buffer *pipelined);
Chris Wilsoncc98b412013-08-09 12:25:09 +01002099void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002100int i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002101 struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01002102 int id,
2103 int align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002104void i915_gem_detach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002105 struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10002106void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002107int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00002108void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002109
Chris Wilson467cffb2011-03-07 10:42:03 +00002110uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02002111i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2112uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02002113i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2114 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00002115
Chris Wilsone4ffd172011-04-04 09:44:39 +01002116int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2117 enum i915_cache_level cache_level);
2118
Daniel Vetter1286ff72012-05-10 15:25:09 +02002119struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2120 struct dma_buf *dma_buf);
2121
2122struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2123 struct drm_gem_object *gem_obj, int flags);
2124
Chris Wilson19b2dbd2013-06-12 10:15:12 +01002125void i915_gem_restore_fences(struct drm_device *dev);
2126
Ben Widawskya70a3142013-07-31 16:59:56 -07002127unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2128 struct i915_address_space *vm);
2129bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2130bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2131 struct i915_address_space *vm);
2132unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2133 struct i915_address_space *vm);
2134struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2135 struct i915_address_space *vm);
Ben Widawskyaccfef22013-08-14 11:38:35 +02002136struct i915_vma *
2137i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2138 struct i915_address_space *vm);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07002139
2140struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2141
Ben Widawskya70a3142013-07-31 16:59:56 -07002142/* Some GGTT VM helpers */
2143#define obj_to_ggtt(obj) \
2144 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2145static inline bool i915_is_ggtt(struct i915_address_space *vm)
2146{
2147 struct i915_address_space *ggtt =
2148 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2149 return vm == ggtt;
2150}
2151
2152static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2153{
2154 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2155}
2156
2157static inline unsigned long
2158i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2159{
2160 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2161}
2162
2163static inline unsigned long
2164i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2165{
2166 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2167}
Ben Widawskyc37e2202013-07-31 16:59:58 -07002168
2169static inline int __must_check
2170i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2171 uint32_t alignment,
2172 bool map_and_fenceable,
2173 bool nonblocking)
2174{
2175 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2176 map_and_fenceable, nonblocking);
2177}
Ben Widawskya70a3142013-07-31 16:59:56 -07002178
Ben Widawsky254f9652012-06-04 14:42:42 -07002179/* i915_gem_context.c */
2180void i915_gem_context_init(struct drm_device *dev);
2181void i915_gem_context_fini(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07002182void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Ben Widawskye0556842012-06-04 14:42:46 -07002183int i915_switch_context(struct intel_ring_buffer *ring,
2184 struct drm_file *file, int to_id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03002185void i915_gem_context_free(struct kref *ctx_ref);
2186static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2187{
2188 kref_get(&ctx->ref);
2189}
2190
2191static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2192{
2193 kref_put(&ctx->ref, i915_gem_context_free);
2194}
2195
Mika Kuoppalac0bb6172013-06-12 12:35:29 +03002196struct i915_ctx_hang_stats * __must_check
Chris Wilson11fa3382013-07-03 17:22:06 +03002197i915_gem_context_get_hang_stats(struct drm_device *dev,
Mika Kuoppalac0bb6172013-06-12 12:35:29 +03002198 struct drm_file *file,
2199 u32 id);
Ben Widawsky84624812012-06-04 14:42:54 -07002200int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2201 struct drm_file *file);
2202int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2203 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02002204
Daniel Vetter76aaf222010-11-05 22:23:30 +01002205/* i915_gem_gtt.c */
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002206void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
Daniel Vetter7bddb012012-02-09 17:15:47 +01002207void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2208 struct drm_i915_gem_object *obj,
2209 enum i915_cache_level cache_level);
2210void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2211 struct drm_i915_gem_object *obj);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002212
Ben Widawsky828c7902013-10-16 09:21:30 -07002213void i915_check_and_clear_faults(struct drm_device *dev);
2214void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
Daniel Vetter76aaf222010-11-05 22:23:30 +01002215void i915_gem_restore_gtt_mappings(struct drm_device *dev);
Daniel Vetter74163902012-02-15 23:50:21 +01002216int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2217void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
Chris Wilsone4ffd172011-04-04 09:44:39 +01002218 enum i915_cache_level cache_level);
Chris Wilson05394f32010-11-08 19:18:58 +00002219void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
Daniel Vetter74163902012-02-15 23:50:21 +01002220void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
Ben Widawskyd7e50082012-12-18 10:31:25 -08002221void i915_gem_init_global_gtt(struct drm_device *dev);
2222void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2223 unsigned long mappable_end, unsigned long end);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002224int i915_gem_gtt_init(struct drm_device *dev);
Ben Widawskyd09105c2012-11-15 12:06:09 -08002225static inline void i915_gem_chipset_flush(struct drm_device *dev)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002226{
2227 if (INTEL_INFO(dev)->gen < 6)
2228 intel_gtt_chipset_flush();
2229}
2230
Daniel Vetter76aaf222010-11-05 22:23:30 +01002231
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002232/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07002233int __must_check i915_gem_evict_something(struct drm_device *dev,
2234 struct i915_address_space *vm,
2235 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01002236 unsigned alignment,
2237 unsigned cache_level,
Chris Wilson86a1ee22012-08-11 15:41:04 +01002238 bool mappable,
2239 bool nonblock);
Ben Widawsky68c8c172013-09-11 14:57:50 -07002240int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilson6c085a72012-08-20 11:40:46 +02002241int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01002242
Chris Wilson9797fbf2012-04-24 15:47:39 +01002243/* i915_gem_stolen.c */
2244int i915_gem_init_stolen(struct drm_device *dev);
Chris Wilson11be49e2012-11-15 11:32:20 +00002245int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2246void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002247void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002248struct drm_i915_gem_object *
2249i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08002250struct drm_i915_gem_object *
2251i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2252 u32 stolen_offset,
2253 u32 gtt_offset,
2254 u32 size);
Chris Wilson0104fdb2012-11-15 11:32:26 +00002255void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
Chris Wilson9797fbf2012-04-24 15:47:39 +01002256
Eric Anholt673a3942008-07-30 12:06:12 -07002257/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01002258static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00002259{
2260 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2261
2262 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2263 obj->tiling_mode != I915_TILING_NONE;
2264}
2265
Eric Anholt673a3942008-07-30 12:06:12 -07002266void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00002267void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2268void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002269
2270/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01002271#if WATCH_LISTS
2272int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07002273#else
Chris Wilson23bc5982010-09-29 16:10:57 +01002274#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07002275#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002276
Ben Gamari20172632009-02-17 20:08:50 -05002277/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04002278int i915_debugfs_init(struct drm_minor *minor);
2279void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002280#ifdef CONFIG_DEBUG_FS
Damien Lespiau07144422013-10-15 18:55:40 +01002281void intel_display_crc_init(struct drm_device *dev);
2282#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02002283static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01002284#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03002285
2286/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002287__printf(2, 3)
2288void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03002289int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2290 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03002291int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2292 size_t count, loff_t pos);
2293static inline void i915_error_state_buf_release(
2294 struct drm_i915_error_state_buf *eb)
2295{
2296 kfree(eb->buf);
2297}
Mika Kuoppala84734a02013-07-12 16:50:57 +03002298void i915_capture_error_state(struct drm_device *dev);
2299void i915_error_state_get(struct drm_device *dev,
2300 struct i915_error_state_file_priv *error_priv);
2301void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2302void i915_destroy_error_state(struct drm_device *dev);
2303
2304void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2305const char *i915_cache_level_str(int type);
Ben Gamari20172632009-02-17 20:08:50 -05002306
Jesse Barnes317c35d2008-08-25 15:11:06 -07002307/* i915_suspend.c */
2308extern int i915_save_state(struct drm_device *dev);
2309extern int i915_restore_state(struct drm_device *dev);
2310
Daniel Vetterd8157a32013-01-25 17:53:20 +01002311/* i915_ums.c */
2312void i915_save_display_reg(struct drm_device *dev);
2313void i915_restore_display_reg(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002314
Ben Widawsky0136db582012-04-10 21:17:01 -07002315/* i915_sysfs.c */
2316void i915_setup_sysfs(struct drm_device *dev_priv);
2317void i915_teardown_sysfs(struct drm_device *dev_priv);
2318
Chris Wilsonf899fc62010-07-20 15:44:45 -07002319/* intel_i2c.c */
2320extern int intel_setup_gmbus(struct drm_device *dev);
2321extern void intel_teardown_gmbus(struct drm_device *dev);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002322static inline bool intel_gmbus_is_port_valid(unsigned port)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002323{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08002324 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08002325}
2326
2327extern struct i2c_adapter *intel_gmbus_get_adapter(
2328 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01002329extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2330extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02002331static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01002332{
2333 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2334}
Chris Wilsonf899fc62010-07-20 15:44:45 -07002335extern void intel_i2c_reset(struct drm_device *dev);
2336
Chris Wilson3b617962010-08-24 09:02:58 +01002337/* intel_opregion.c */
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002338struct intel_encoder;
Chris Wilson44834a62010-08-19 16:09:23 +01002339extern int intel_opregion_setup(struct drm_device *dev);
2340#ifdef CONFIG_ACPI
2341extern void intel_opregion_init(struct drm_device *dev);
2342extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01002343extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002344extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2345 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002346extern int intel_opregion_notify_adapter(struct drm_device *dev,
2347 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04002348#else
Chris Wilson44834a62010-08-19 16:09:23 +01002349static inline void intel_opregion_init(struct drm_device *dev) { return; }
2350static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01002351static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03002352static inline int
2353intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2354{
2355 return 0;
2356}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03002357static inline int
2358intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2359{
2360 return 0;
2361}
Len Brown65e082c2008-10-24 17:18:10 -04002362#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01002363
Jesse Barnes723bfd72010-10-07 16:01:13 -07002364/* intel_acpi.c */
2365#ifdef CONFIG_ACPI
2366extern void intel_register_dsm_handler(void);
2367extern void intel_unregister_dsm_handler(void);
2368#else
2369static inline void intel_register_dsm_handler(void) { return; }
2370static inline void intel_unregister_dsm_handler(void) { return; }
2371#endif /* CONFIG_ACPI */
2372
Jesse Barnes79e53942008-11-07 14:24:08 -08002373/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02002374extern void intel_modeset_init_hw(struct drm_device *dev);
Imre Deak7d708ee2013-04-17 14:04:50 +03002375extern void intel_modeset_suspend_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002376extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01002377extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002378extern void intel_modeset_cleanup(struct drm_device *dev);
Dave Airlie28d52042009-09-21 14:33:58 +10002379extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01002380extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2381 bool force_restore);
Daniel Vetter44cec742013-01-25 17:53:21 +01002382extern void i915_redisable_vga(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04002383extern bool intel_fbc_enabled(struct drm_device *dev);
Chris Wilson43a95392011-07-08 12:22:36 +01002384extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002385extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02002386extern void intel_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08002387extern void gen6_set_rps(struct drm_device *dev, u8 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002388extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2389extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2390extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
Akshay Joshi0206e352011-08-16 15:34:10 -04002391extern void intel_detect_pch(struct drm_device *dev);
2392extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07002393extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08002394
Ben Widawsky2911a352012-04-05 14:47:36 -07002395extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07002396int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2397 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07002398
Chris Wilson6ef3d422010-08-04 20:26:07 +01002399/* overlay */
2400extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002401extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2402 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002403
2404extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03002405extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002406 struct drm_device *dev,
2407 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01002408
Ben Widawskyb7287d82011-04-25 11:22:22 -07002409/* On SNB platform, before reading ring registers forcewake bit
2410 * must be set to prevent GT core from power down and stale values being
2411 * returned.
2412 */
Ben Widawskyfcca7922011-04-25 11:23:07 -07002413void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2414void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07002415
Ben Widawsky42c05262012-09-26 10:34:00 -07002416int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2417int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002418
2419/* intel_sideband.c */
Jani Nikula64936252013-05-22 15:36:20 +03002420u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2421void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2422u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Jani Nikulae9f882a2013-08-27 15:12:14 +03002423u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2424void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2425u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2426void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2427u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2428void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2429u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2430void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002431u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2432void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03002433u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2434 enum intel_sbi_destination destination);
2435void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2436 enum intel_sbi_destination destination);
Jesse Barnes0a073b82013-04-17 15:54:58 -07002437
Jesse Barnes855ba3b2013-04-17 15:54:57 -07002438int vlv_gpu_freq(int ddr_freq, int val);
2439int vlv_freq_opcode(int ddr_freq, int val);
Ben Widawsky42c05262012-09-26 10:34:00 -07002440
Ben Widawsky0b274482013-10-04 21:22:51 -07002441#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2442#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00002443
Ben Widawsky0b274482013-10-04 21:22:51 -07002444#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2445#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2446#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2447#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002448
Ben Widawsky0b274482013-10-04 21:22:51 -07002449#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2450#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2451#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2452#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00002453
Ben Widawsky0b274482013-10-04 21:22:51 -07002454#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2455#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08002456
2457#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2458#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2459
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02002460/* "Broadcast RGB" property */
2461#define INTEL_BROADCAST_RGB_AUTO 0
2462#define INTEL_BROADCAST_RGB_FULL 1
2463#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08002464
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02002465static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2466{
2467 if (HAS_PCH_SPLIT(dev))
2468 return CPU_VGACNTRL;
2469 else if (IS_VALLEYVIEW(dev))
2470 return VLV_VGACNTRL;
2471 else
2472 return VGACNTRL;
2473}
2474
Ville Syrjälä2bb46292013-02-22 16:12:51 +02002475static inline void __user *to_user_ptr(u64 address)
2476{
2477 return (void __user *)(uintptr_t)address;
2478}
2479
Imre Deakdf977292013-05-21 20:03:17 +03002480static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2481{
2482 unsigned long j = msecs_to_jiffies(m);
2483
2484 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2485}
2486
2487static inline unsigned long
2488timespec_to_jiffies_timeout(const struct timespec *value)
2489{
2490 unsigned long j = timespec_to_jiffies(value);
2491
2492 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2493}
2494
Linus Torvalds1da177e2005-04-16 15:20:36 -07002495#endif