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Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drmP.h>
34#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010036#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Egbert Eiche5868a32013-02-28 04:17:12 -050039static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010049 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050050 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
Egbert Eichcd569ae2013-04-16 13:36:57 +020091static void ibx_hpd_irq_setup(struct drm_device *dev);
92static void i915_hpd_irq_setup(struct drm_device *dev);
Egbert Eiche5868a32013-02-28 04:17:12 -050093
Zhenyu Wang036a4a72009-06-08 14:40:19 +080094/* For display hotplug interrupt */
Chris Wilson995b6762010-08-20 13:23:26 +010095static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050096ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080097{
Chris Wilson1ec14ad2010-12-04 11:30:53 +000098 if ((dev_priv->irq_mask & mask) != 0) {
99 dev_priv->irq_mask &= ~mask;
100 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000101 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800102 }
103}
104
Paulo Zanoni0ff98002013-02-22 17:05:31 -0300105static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500106ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800107{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000108 if ((dev_priv->irq_mask & mask) != mask) {
109 dev_priv->irq_mask |= mask;
110 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000111 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800112 }
113}
114
Paulo Zanoni86642812013-04-12 17:57:57 -0300115static bool ivb_can_enable_err_int(struct drm_device *dev)
116{
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct intel_crtc *crtc;
119 enum pipe pipe;
120
121 for_each_pipe(pipe) {
122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
123
124 if (crtc->cpu_fifo_underrun_disabled)
125 return false;
126 }
127
128 return true;
129}
130
131static bool cpt_can_enable_serr_int(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 enum pipe pipe;
135 struct intel_crtc *crtc;
136
137 for_each_pipe(pipe) {
138 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
139
140 if (crtc->pch_fifo_underrun_disabled)
141 return false;
142 }
143
144 return true;
145}
146
147static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
148 enum pipe pipe, bool enable)
149{
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
152 DE_PIPEB_FIFO_UNDERRUN;
153
154 if (enable)
155 ironlake_enable_display_irq(dev_priv, bit);
156 else
157 ironlake_disable_display_irq(dev_priv, bit);
158}
159
160static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
161 bool enable)
162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 if (enable) {
166 if (!ivb_can_enable_err_int(dev))
167 return;
168
169 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
170 ERR_INT_FIFO_UNDERRUN_B |
171 ERR_INT_FIFO_UNDERRUN_C);
172
173 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
174 } else {
175 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
176 }
177}
178
179static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
180 bool enable)
181{
182 struct drm_device *dev = crtc->base.dev;
183 struct drm_i915_private *dev_priv = dev->dev_private;
184 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
185 SDE_TRANSB_FIFO_UNDER;
186
187 if (enable)
188 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
189 else
190 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
191
192 POSTING_READ(SDEIMR);
193}
194
195static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
196 enum transcoder pch_transcoder,
197 bool enable)
198{
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
201 if (enable) {
202 if (!cpt_can_enable_serr_int(dev))
203 return;
204
205 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
206 SERR_INT_TRANS_B_FIFO_UNDERRUN |
207 SERR_INT_TRANS_C_FIFO_UNDERRUN);
208
209 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
210 } else {
211 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
212 }
213
214 POSTING_READ(SDEIMR);
215}
216
217/**
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
219 * @dev: drm device
220 * @pipe: pipe
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
222 *
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
228 *
229 * Returns the previous state of underrun reporting.
230 */
231bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
232 enum pipe pipe, bool enable)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
237 unsigned long flags;
238 bool ret;
239
240 spin_lock_irqsave(&dev_priv->irq_lock, flags);
241
242 ret = !intel_crtc->cpu_fifo_underrun_disabled;
243
244 if (enable == ret)
245 goto done;
246
247 intel_crtc->cpu_fifo_underrun_disabled = !enable;
248
249 if (IS_GEN5(dev) || IS_GEN6(dev))
250 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
251 else if (IS_GEN7(dev))
252 ivybridge_set_fifo_underrun_reporting(dev, enable);
253
254done:
255 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
256 return ret;
257}
258
259/**
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
261 * @dev: drm device
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
264 *
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
270 *
271 * Returns the previous state of underrun reporting.
272 */
273bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
275 bool enable)
276{
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 enum pipe p;
279 struct drm_crtc *crtc;
280 struct intel_crtc *intel_crtc;
281 unsigned long flags;
282 bool ret;
283
284 if (HAS_PCH_LPT(dev)) {
285 crtc = NULL;
286 for_each_pipe(p) {
287 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
288 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
289 crtc = c;
290 break;
291 }
292 }
293 if (!crtc) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
295 return false;
296 }
297 } else {
298 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
299 }
300 intel_crtc = to_intel_crtc(crtc);
301
302 spin_lock_irqsave(&dev_priv->irq_lock, flags);
303
304 ret = !intel_crtc->pch_fifo_underrun_disabled;
305
306 if (enable == ret)
307 goto done;
308
309 intel_crtc->pch_fifo_underrun_disabled = !enable;
310
311 if (HAS_PCH_IBX(dev))
312 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
313 else
314 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
315
316done:
317 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318 return ret;
319}
320
321
Keith Packard7c463582008-11-04 02:03:27 -0800322void
323i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
324{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200325 u32 reg = PIPESTAT(pipe);
326 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800327
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200328 if ((pipestat & mask) == mask)
329 return;
330
331 /* Enable the interrupt, clear any pending status */
332 pipestat |= mask | (mask >> 16);
333 I915_WRITE(reg, pipestat);
334 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800335}
336
337void
338i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
339{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200340 u32 reg = PIPESTAT(pipe);
341 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800342
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200343 if ((pipestat & mask) == 0)
344 return;
345
346 pipestat &= ~mask;
347 I915_WRITE(reg, pipestat);
348 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800349}
350
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000351/**
Zhao Yakui01c66882009-10-28 05:10:00 +0000352 * intel_enable_asle - enable ASLE interrupt for OpRegion
353 */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000354void intel_enable_asle(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000355{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000356 drm_i915_private_t *dev_priv = dev->dev_private;
357 unsigned long irqflags;
358
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700359 /* FIXME: opregion/asle for VLV */
360 if (IS_VALLEYVIEW(dev))
361 return;
362
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000363 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000364
Eric Anholtc619eed2010-01-28 16:45:52 -0800365 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500366 ironlake_enable_display_irq(dev_priv, DE_GSE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800367 else {
Zhao Yakui01c66882009-10-28 05:10:00 +0000368 i915_enable_pipestat(dev_priv, 1,
Jesse Barnesd874bcf2010-06-30 13:16:00 -0700369 PIPE_LEGACY_BLC_EVENT_ENABLE);
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100370 if (INTEL_INFO(dev)->gen >= 4)
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800371 i915_enable_pipestat(dev_priv, 0,
Jesse Barnesd874bcf2010-06-30 13:16:00 -0700372 PIPE_LEGACY_BLC_EVENT_ENABLE);
Zhao Yakuiedcb49c2010-04-07 17:11:21 +0800373 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000374
375 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000376}
377
378/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700379 * i915_pipe_enabled - check if a pipe is enabled
380 * @dev: DRM device
381 * @pipe: pipe to check
382 *
383 * Reading certain registers when the pipe is disabled can hang the chip.
384 * Use this routine to make sure the PLL is running and the pipe is active
385 * before reading such registers if unsure.
386 */
387static int
388i915_pipe_enabled(struct drm_device *dev, int pipe)
389{
390 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200391 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
392 pipe);
393
394 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700395}
396
Keith Packard42f52ef2008-10-18 19:39:29 -0700397/* Called from drm generic code, passed a 'crtc', which
398 * we use as a pipe index
399 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700400static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700401{
402 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
403 unsigned long high_frame;
404 unsigned long low_frame;
Chris Wilson5eddb702010-09-11 13:48:45 +0100405 u32 high1, high2, low;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700406
407 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800408 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800409 "pipe %c\n", pipe_name(pipe));
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700410 return 0;
411 }
412
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800413 high_frame = PIPEFRAME(pipe);
414 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100415
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700416 /*
417 * High & low register fields aren't synchronized, so make sure
418 * we get a low value that's stable across two reads of the high
419 * register.
420 */
421 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100422 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
423 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
424 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700425 } while (high1 != high2);
426
Chris Wilson5eddb702010-09-11 13:48:45 +0100427 high1 >>= PIPE_FRAME_HIGH_SHIFT;
428 low >>= PIPE_FRAME_LOW_SHIFT;
429 return (high1 << 8) | low;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700430}
431
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700432static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800433{
434 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800435 int reg = PIPE_FRMCOUNT_GM45(pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800436
437 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800438 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800439 "pipe %c\n", pipe_name(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800440 return 0;
441 }
442
443 return I915_READ(reg);
444}
445
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700446static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100447 int *vpos, int *hpos)
448{
449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
450 u32 vbl = 0, position = 0;
451 int vbl_start, vbl_end, htotal, vtotal;
452 bool in_vbl = true;
453 int ret = 0;
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200454 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
455 pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100456
457 if (!i915_pipe_enabled(dev, pipe)) {
458 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800459 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100460 return 0;
461 }
462
463 /* Get vtotal. */
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200464 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100465
466 if (INTEL_INFO(dev)->gen >= 4) {
467 /* No obvious pixelcount register. Only query vertical
468 * scanout position from Display scan line register.
469 */
470 position = I915_READ(PIPEDSL(pipe));
471
472 /* Decode into vertical scanout position. Don't have
473 * horizontal scanout position.
474 */
475 *vpos = position & 0x1fff;
476 *hpos = 0;
477 } else {
478 /* Have access to pixelcount since start of frame.
479 * We can split this into vertical and horizontal
480 * scanout position.
481 */
482 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
483
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200484 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100485 *vpos = position / htotal;
486 *hpos = position - (*vpos * htotal);
487 }
488
489 /* Query vblank area. */
Paulo Zanonife2b8f92012-10-23 18:30:02 -0200490 vbl = I915_READ(VBLANK(cpu_transcoder));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100491
492 /* Test position against vblank region. */
493 vbl_start = vbl & 0x1fff;
494 vbl_end = (vbl >> 16) & 0x1fff;
495
496 if ((*vpos < vbl_start) || (*vpos > vbl_end))
497 in_vbl = false;
498
499 /* Inside "upper part" of vblank area? Apply corrective offset: */
500 if (in_vbl && (*vpos >= vbl_start))
501 *vpos = *vpos - vtotal;
502
503 /* Readouts valid? */
504 if (vbl > 0)
505 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
506
507 /* In vblank? */
508 if (in_vbl)
509 ret |= DRM_SCANOUTPOS_INVBL;
510
511 return ret;
512}
513
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700514static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100515 int *max_error,
516 struct timeval *vblank_time,
517 unsigned flags)
518{
Chris Wilson4041b852011-01-22 10:07:56 +0000519 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100520
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700521 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000522 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100523 return -EINVAL;
524 }
525
526 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000527 crtc = intel_get_crtc_for_pipe(dev, pipe);
528 if (crtc == NULL) {
529 DRM_ERROR("Invalid crtc %d\n", pipe);
530 return -EINVAL;
531 }
532
533 if (!crtc->enabled) {
534 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
535 return -EBUSY;
536 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100537
538 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000539 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
540 vblank_time, flags,
541 crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100542}
543
Jesse Barnes5ca58282009-03-31 14:11:15 -0700544/*
545 * Handle hotplug events outside the interrupt handler proper.
546 */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200547#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
548
Jesse Barnes5ca58282009-03-31 14:11:15 -0700549static void i915_hotplug_work_func(struct work_struct *work)
550{
551 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
552 hotplug_work);
553 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700554 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200555 struct intel_connector *intel_connector;
556 struct intel_encoder *intel_encoder;
557 struct drm_connector *connector;
558 unsigned long irqflags;
559 bool hpd_disabled = false;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700560
Daniel Vetter52d7ece2012-12-01 21:03:22 +0100561 /* HPD irq before everything is fully set up. */
562 if (!dev_priv->enable_hotplug_processing)
563 return;
564
Keith Packarda65e34c2011-07-25 10:04:56 -0700565 mutex_lock(&mode_config->mutex);
Jesse Barnese67189ab2011-02-11 14:44:51 -0800566 DRM_DEBUG_KMS("running encoder hotplug functions\n");
567
Egbert Eichcd569ae2013-04-16 13:36:57 +0200568 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
569 list_for_each_entry(connector, &mode_config->connector_list, head) {
570 intel_connector = to_intel_connector(connector);
571 intel_encoder = intel_connector->encoder;
572 if (intel_encoder->hpd_pin > HPD_NONE &&
573 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
574 connector->polled == DRM_CONNECTOR_POLL_HPD) {
575 DRM_INFO("HPD interrupt storm detected on connector %s: "
576 "switching from hotplug detection to polling\n",
577 drm_get_connector_name(connector));
578 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
579 connector->polled = DRM_CONNECTOR_POLL_CONNECT
580 | DRM_CONNECTOR_POLL_DISCONNECT;
581 hpd_disabled = true;
582 }
583 }
584 /* if there were no outputs to poll, poll was disabled,
585 * therefore make sure it's enabled when disabling HPD on
586 * some connectors */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200587 if (hpd_disabled) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200588 drm_kms_helper_poll_enable(dev);
Egbert Eichac4c16c2013-04-16 13:36:58 +0200589 mod_timer(&dev_priv->hotplug_reenable_timer,
590 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
591 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200592
593 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
594
595 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
596 if (intel_encoder->hot_plug)
597 intel_encoder->hot_plug(intel_encoder);
Chris Wilson4ef69c72010-09-09 15:14:28 +0100598
Keith Packard40ee3382011-07-28 15:31:19 -0700599 mutex_unlock(&mode_config->mutex);
600
Jesse Barnes5ca58282009-03-31 14:11:15 -0700601 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000602 drm_helper_hpd_irq_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700603}
604
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200605static void ironlake_handle_rps_change(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800606{
607 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000608 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200609 u8 new_delay;
610 unsigned long flags;
611
612 spin_lock_irqsave(&mchdev_lock, flags);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800613
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200614 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
615
Daniel Vetter20e4d402012-08-08 23:35:39 +0200616 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200617
Jesse Barnes7648fa92010-05-20 14:28:11 -0700618 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000619 busy_up = I915_READ(RCPREVBSYTUPAVG);
620 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800621 max_avg = I915_READ(RCBMAXAVG);
622 min_avg = I915_READ(RCBMINAVG);
623
624 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000625 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200626 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
627 new_delay = dev_priv->ips.cur_delay - 1;
628 if (new_delay < dev_priv->ips.max_delay)
629 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000630 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200631 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
632 new_delay = dev_priv->ips.cur_delay + 1;
633 if (new_delay > dev_priv->ips.min_delay)
634 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800635 }
636
Jesse Barnes7648fa92010-05-20 14:28:11 -0700637 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200638 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800639
Daniel Vetter92703882012-08-09 16:46:01 +0200640 spin_unlock_irqrestore(&mchdev_lock, flags);
641
Jesse Barnesf97108d2010-01-29 11:27:07 -0800642 return;
643}
644
Chris Wilson549f7362010-10-19 11:19:32 +0100645static void notify_ring(struct drm_device *dev,
646 struct intel_ring_buffer *ring)
647{
648 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9862e602011-01-04 22:22:17 +0000649
Chris Wilson475553d2011-01-20 09:52:56 +0000650 if (ring->obj == NULL)
651 return;
652
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100653 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
Chris Wilson9862e602011-01-04 22:22:17 +0000654
Chris Wilson549f7362010-10-19 11:19:32 +0100655 wake_up_all(&ring->irq_queue);
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700656 if (i915_enable_hangcheck) {
Daniel Vetter99584db2012-11-14 17:14:04 +0100657 dev_priv->gpu_error.hangcheck_count = 0;
658 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
Chris Wilsoncecc21f2012-10-05 17:02:56 +0100659 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -0700660 }
Chris Wilson549f7362010-10-19 11:19:32 +0100661}
662
Ben Widawsky4912d042011-04-25 11:25:20 -0700663static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800664{
Ben Widawsky4912d042011-04-25 11:25:20 -0700665 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200666 rps.work);
Ben Widawsky4912d042011-04-25 11:25:20 -0700667 u32 pm_iir, pm_imr;
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100668 u8 new_delay;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800669
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200670 spin_lock_irq(&dev_priv->rps.lock);
671 pm_iir = dev_priv->rps.pm_iir;
672 dev_priv->rps.pm_iir = 0;
Ben Widawsky4912d042011-04-25 11:25:20 -0700673 pm_imr = I915_READ(GEN6_PMIMR);
Daniel Vettera9e26412011-09-08 14:00:21 +0200674 I915_WRITE(GEN6_PMIMR, 0);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200675 spin_unlock_irq(&dev_priv->rps.lock);
Ben Widawsky4912d042011-04-25 11:25:20 -0700676
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100677 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800678 return;
679
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700680 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100681
682 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200683 new_delay = dev_priv->rps.cur_delay + 1;
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100684 else
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200685 new_delay = dev_priv->rps.cur_delay - 1;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800686
Ben Widawsky79249632012-09-07 19:43:42 -0700687 /* sysfs frequency interfaces may have snuck in while servicing the
688 * interrupt
689 */
690 if (!(new_delay > dev_priv->rps.max_delay ||
691 new_delay < dev_priv->rps.min_delay)) {
Jesse Barnes0a073b82013-04-17 15:54:58 -0700692 if (IS_VALLEYVIEW(dev_priv->dev))
693 valleyview_set_rps(dev_priv->dev, new_delay);
694 else
695 gen6_set_rps(dev_priv->dev, new_delay);
Ben Widawsky79249632012-09-07 19:43:42 -0700696 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800697
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700698 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800699}
700
Ben Widawskye3689192012-05-25 16:56:22 -0700701
702/**
703 * ivybridge_parity_work - Workqueue called when a parity error interrupt
704 * occurred.
705 * @work: workqueue struct
706 *
707 * Doesn't actually do anything except notify userspace. As a consequence of
708 * this event, userspace should try to remap the bad rows since statistically
709 * it is likely the same row is more likely to go bad again.
710 */
711static void ivybridge_parity_work(struct work_struct *work)
712{
713 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100714 l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -0700715 u32 error_status, row, bank, subbank;
716 char *parity_event[5];
717 uint32_t misccpctl;
718 unsigned long flags;
719
720 /* We must turn off DOP level clock gating to access the L3 registers.
721 * In order to prevent a get/put style interface, acquire struct mutex
722 * any time we access those registers.
723 */
724 mutex_lock(&dev_priv->dev->struct_mutex);
725
726 misccpctl = I915_READ(GEN7_MISCCPCTL);
727 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
728 POSTING_READ(GEN7_MISCCPCTL);
729
730 error_status = I915_READ(GEN7_L3CDERRST1);
731 row = GEN7_PARITY_ERROR_ROW(error_status);
732 bank = GEN7_PARITY_ERROR_BANK(error_status);
733 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
734
735 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
736 GEN7_L3CDERRST1_ENABLE);
737 POSTING_READ(GEN7_L3CDERRST1);
738
739 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
740
741 spin_lock_irqsave(&dev_priv->irq_lock, flags);
742 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
743 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
744 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
745
746 mutex_unlock(&dev_priv->dev->struct_mutex);
747
748 parity_event[0] = "L3_PARITY_ERROR=1";
749 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
750 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
751 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
752 parity_event[4] = NULL;
753
754 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
755 KOBJ_CHANGE, parity_event);
756
757 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
758 row, bank, subbank);
759
760 kfree(parity_event[3]);
761 kfree(parity_event[2]);
762 kfree(parity_event[1]);
763}
764
Daniel Vetterd2ba8472012-05-31 14:57:41 +0200765static void ivybridge_handle_parity_error(struct drm_device *dev)
Ben Widawskye3689192012-05-25 16:56:22 -0700766{
767 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
768 unsigned long flags;
769
Ben Widawskye1ef7cc2012-07-24 20:47:31 -0700770 if (!HAS_L3_GPU_CACHE(dev))
Ben Widawskye3689192012-05-25 16:56:22 -0700771 return;
772
773 spin_lock_irqsave(&dev_priv->irq_lock, flags);
774 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
775 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
776 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
777
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100778 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -0700779}
780
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200781static void snb_gt_irq_handler(struct drm_device *dev,
782 struct drm_i915_private *dev_priv,
783 u32 gt_iir)
784{
785
786 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
787 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
788 notify_ring(dev, &dev_priv->ring[RCS]);
789 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
790 notify_ring(dev, &dev_priv->ring[VCS]);
791 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
792 notify_ring(dev, &dev_priv->ring[BCS]);
793
794 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
795 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
796 GT_RENDER_CS_ERROR_INTERRUPT)) {
797 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
798 i915_handle_error(dev, false);
799 }
Ben Widawskye3689192012-05-25 16:56:22 -0700800
801 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
802 ivybridge_handle_parity_error(dev);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200803}
804
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100805static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
806 u32 pm_iir)
807{
808 unsigned long flags;
809
810 /*
811 * IIR bits should never already be set because IMR should
812 * prevent an interrupt from being shown in IIR. The warning
813 * displays a case where we've unsafely cleared
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200814 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100815 * type is not a problem, it displays a problem in the logic.
816 *
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200817 * The mask bit in IMR is cleared by dev_priv->rps.work.
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100818 */
819
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200820 spin_lock_irqsave(&dev_priv->rps.lock, flags);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200821 dev_priv->rps.pm_iir |= pm_iir;
822 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100823 POSTING_READ(GEN6_PMIMR);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200824 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100825
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200826 queue_work(dev_priv->wq, &dev_priv->rps.work);
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100827}
828
Egbert Eichb543fb02013-04-16 13:36:54 +0200829#define HPD_STORM_DETECT_PERIOD 1000
830#define HPD_STORM_THRESHOLD 5
831
Egbert Eichcd569ae2013-04-16 13:36:57 +0200832static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
Egbert Eichb543fb02013-04-16 13:36:54 +0200833 u32 hotplug_trigger,
834 const u32 *hpd)
835{
836 drm_i915_private_t *dev_priv = dev->dev_private;
837 unsigned long irqflags;
838 int i;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200839 bool ret = false;
Egbert Eichb543fb02013-04-16 13:36:54 +0200840
841 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
842
843 for (i = 1; i < HPD_NUM_PINS; i++) {
Egbert Eich821450c2013-04-16 13:36:55 +0200844
Egbert Eichb543fb02013-04-16 13:36:54 +0200845 if (!(hpd[i] & hotplug_trigger) ||
846 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
847 continue;
848
849 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
850 dev_priv->hpd_stats[i].hpd_last_jiffies
851 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
852 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
853 dev_priv->hpd_stats[i].hpd_cnt = 0;
854 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
855 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
856 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200857 ret = true;
Egbert Eichb543fb02013-04-16 13:36:54 +0200858 } else {
859 dev_priv->hpd_stats[i].hpd_cnt++;
860 }
861 }
862
863 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200864
865 return ret;
Egbert Eichb543fb02013-04-16 13:36:54 +0200866}
867
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100868static void gmbus_irq_handler(struct drm_device *dev)
869{
Daniel Vetter28c70f12012-12-01 13:53:45 +0100870 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
871
Daniel Vetter28c70f12012-12-01 13:53:45 +0100872 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100873}
874
Daniel Vetterce99c252012-12-01 13:53:47 +0100875static void dp_aux_irq_handler(struct drm_device *dev)
876{
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100877 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
878
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100879 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +0100880}
881
Daniel Vetterff1f5252012-10-02 15:10:55 +0200882static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700883{
884 struct drm_device *dev = (struct drm_device *) arg;
885 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
886 u32 iir, gt_iir, pm_iir;
887 irqreturn_t ret = IRQ_NONE;
888 unsigned long irqflags;
889 int pipe;
890 u32 pipe_stats[I915_MAX_PIPES];
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700891
892 atomic_inc(&dev_priv->irq_received);
893
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700894 while (true) {
895 iir = I915_READ(VLV_IIR);
896 gt_iir = I915_READ(GTIIR);
897 pm_iir = I915_READ(GEN6_PMIIR);
898
899 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
900 goto out;
901
902 ret = IRQ_HANDLED;
903
Daniel Vettere7b4c6b2012-03-30 20:24:35 +0200904 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700905
906 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
907 for_each_pipe(pipe) {
908 int reg = PIPESTAT(pipe);
909 pipe_stats[pipe] = I915_READ(reg);
910
911 /*
912 * Clear the PIPE*STAT regs before the IIR
913 */
914 if (pipe_stats[pipe] & 0x8000ffff) {
915 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
916 DRM_DEBUG_DRIVER("pipe %c underrun\n",
917 pipe_name(pipe));
918 I915_WRITE(reg, pipe_stats[pipe]);
919 }
920 }
921 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
922
Jesse Barnes31acc7f2012-06-20 10:53:11 -0700923 for_each_pipe(pipe) {
924 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
925 drm_handle_vblank(dev, pipe);
926
927 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
928 intel_prepare_page_flip(dev, pipe);
929 intel_finish_page_flip(dev, pipe);
930 }
931 }
932
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700933 /* Consume port. Then clear IIR or we'll miss events */
934 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
935 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +0200936 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700937
938 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
939 hotplug_status);
Egbert Eichb543fb02013-04-16 13:36:54 +0200940 if (hotplug_trigger) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200941 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
942 i915_hpd_irq_setup(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700943 queue_work(dev_priv->wq,
944 &dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +0200945 }
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700946 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
947 I915_READ(PORT_HOTPLUG_STAT);
948 }
949
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100950 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
951 gmbus_irq_handler(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700952
Chris Wilsonfc6826d2012-04-15 11:56:03 +0100953 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
954 gen6_queue_rps_work(dev_priv, pm_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700955
956 I915_WRITE(GTIIR, gt_iir);
957 I915_WRITE(GEN6_PMIIR, pm_iir);
958 I915_WRITE(VLV_IIR, iir);
959 }
960
961out:
962 return ret;
963}
964
Adam Jackson23e81d62012-06-06 15:45:44 -0400965static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -0800966{
967 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800968 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +0200969 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Jesse Barnes776ad802011-01-04 15:09:39 -0800970
Egbert Eichb543fb02013-04-16 13:36:54 +0200971 if (hotplug_trigger) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200972 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
973 ibx_hpd_irq_setup(dev);
Daniel Vetter76e43832012-10-12 20:14:05 +0200974 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +0200975 }
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +0300976 if (pch_iir & SDE_AUDIO_POWER_MASK) {
977 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
978 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -0800979 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +0300980 port_name(port));
981 }
Jesse Barnes776ad802011-01-04 15:09:39 -0800982
Daniel Vetterce99c252012-12-01 13:53:47 +0100983 if (pch_iir & SDE_AUX_MASK)
984 dp_aux_irq_handler(dev);
985
Jesse Barnes776ad802011-01-04 15:09:39 -0800986 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +0100987 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -0800988
989 if (pch_iir & SDE_AUDIO_HDCP_MASK)
990 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
991
992 if (pch_iir & SDE_AUDIO_TRANS_MASK)
993 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
994
995 if (pch_iir & SDE_POISON)
996 DRM_ERROR("PCH poison interrupt\n");
997
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800998 if (pch_iir & SDE_FDI_MASK)
999 for_each_pipe(pipe)
1000 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1001 pipe_name(pipe),
1002 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08001003
1004 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1005 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1006
1007 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1008 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1009
Jesse Barnes776ad802011-01-04 15:09:39 -08001010 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Paulo Zanoni86642812013-04-12 17:57:57 -03001011 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1012 false))
1013 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1014
1015 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1016 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1017 false))
1018 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1019}
1020
1021static void ivb_err_int_handler(struct drm_device *dev)
1022{
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 err_int = I915_READ(GEN7_ERR_INT);
1025
1026 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1027 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1028 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1029
1030 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1031 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1032 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1033
1034 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1035 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1036 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1037
1038 I915_WRITE(GEN7_ERR_INT, err_int);
1039}
1040
1041static void cpt_serr_int_handler(struct drm_device *dev)
1042{
1043 struct drm_i915_private *dev_priv = dev->dev_private;
1044 u32 serr_int = I915_READ(SERR_INT);
1045
1046 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1047 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1048 false))
1049 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1050
1051 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1052 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1053 false))
1054 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1055
1056 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1057 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1058 false))
1059 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1060
1061 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08001062}
1063
Adam Jackson23e81d62012-06-06 15:45:44 -04001064static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1065{
1066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1067 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001068 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Adam Jackson23e81d62012-06-06 15:45:44 -04001069
Egbert Eichb543fb02013-04-16 13:36:54 +02001070 if (hotplug_trigger) {
Egbert Eichcd569ae2013-04-16 13:36:57 +02001071 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1072 ibx_hpd_irq_setup(dev);
Daniel Vetter76e43832012-10-12 20:14:05 +02001073 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02001074 }
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001075 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1076 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1077 SDE_AUDIO_POWER_SHIFT_CPT);
1078 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1079 port_name(port));
1080 }
Adam Jackson23e81d62012-06-06 15:45:44 -04001081
1082 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +01001083 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001084
1085 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001086 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001087
1088 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1089 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1090
1091 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1092 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1093
1094 if (pch_iir & SDE_FDI_MASK_CPT)
1095 for_each_pipe(pipe)
1096 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1097 pipe_name(pipe),
1098 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03001099
1100 if (pch_iir & SDE_ERROR_CPT)
1101 cpt_serr_int_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001102}
1103
Daniel Vetterff1f5252012-10-02 15:10:55 +02001104static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001105{
1106 struct drm_device *dev = (struct drm_device *) arg;
1107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Ben Widawskyab5c6082013-04-05 13:12:41 -07001108 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01001109 irqreturn_t ret = IRQ_NONE;
1110 int i;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001111
1112 atomic_inc(&dev_priv->irq_received);
1113
Paulo Zanoni86642812013-04-12 17:57:57 -03001114 /* We get interrupts on unclaimed registers, so check for this before we
1115 * do any I915_{READ,WRITE}. */
1116 if (IS_HASWELL(dev) &&
1117 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1118 DRM_ERROR("Unclaimed register before interrupt\n");
1119 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1120 }
1121
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001122 /* disable master interrupt before clearing iir */
1123 de_ier = I915_READ(DEIER);
1124 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Chris Wilson0e434062012-05-09 21:45:44 +01001125
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001126 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1127 * interrupts will will be stored on its back queue, and then we'll be
1128 * able to process them after we restore SDEIER (as soon as we restore
1129 * it, we'll get an interrupt if SDEIIR still has something to process
1130 * due to its back queue). */
Ben Widawskyab5c6082013-04-05 13:12:41 -07001131 if (!HAS_PCH_NOP(dev)) {
1132 sde_ier = I915_READ(SDEIER);
1133 I915_WRITE(SDEIER, 0);
1134 POSTING_READ(SDEIER);
1135 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001136
Paulo Zanoni86642812013-04-12 17:57:57 -03001137 /* On Haswell, also mask ERR_INT because we don't want to risk
1138 * generating "unclaimed register" interrupts from inside the interrupt
1139 * handler. */
1140 if (IS_HASWELL(dev))
1141 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1142
Chris Wilson0e434062012-05-09 21:45:44 +01001143 gt_iir = I915_READ(GTIIR);
1144 if (gt_iir) {
1145 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1146 I915_WRITE(GTIIR, gt_iir);
1147 ret = IRQ_HANDLED;
1148 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001149
1150 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01001151 if (de_iir) {
Paulo Zanoni86642812013-04-12 17:57:57 -03001152 if (de_iir & DE_ERR_INT_IVB)
1153 ivb_err_int_handler(dev);
1154
Daniel Vetterce99c252012-12-01 13:53:47 +01001155 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1156 dp_aux_irq_handler(dev);
1157
Chris Wilson0e434062012-05-09 21:45:44 +01001158 if (de_iir & DE_GSE_IVB)
1159 intel_opregion_gse_intr(dev);
1160
1161 for (i = 0; i < 3; i++) {
Daniel Vetter74d44442012-10-02 17:54:35 +02001162 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1163 drm_handle_vblank(dev, i);
Chris Wilson0e434062012-05-09 21:45:44 +01001164 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1165 intel_prepare_page_flip(dev, i);
1166 intel_finish_page_flip_plane(dev, i);
1167 }
Chris Wilson0e434062012-05-09 21:45:44 +01001168 }
1169
1170 /* check event from PCH */
Ben Widawskyab5c6082013-04-05 13:12:41 -07001171 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
Chris Wilson0e434062012-05-09 21:45:44 +01001172 u32 pch_iir = I915_READ(SDEIIR);
1173
Adam Jackson23e81d62012-06-06 15:45:44 -04001174 cpt_irq_handler(dev, pch_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01001175
1176 /* clear PCH hotplug event before clear CPU irq */
1177 I915_WRITE(SDEIIR, pch_iir);
1178 }
1179
1180 I915_WRITE(DEIIR, de_iir);
1181 ret = IRQ_HANDLED;
1182 }
1183
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001184 pm_iir = I915_READ(GEN6_PMIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01001185 if (pm_iir) {
1186 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
1187 gen6_queue_rps_work(dev_priv, pm_iir);
1188 I915_WRITE(GEN6_PMIIR, pm_iir);
1189 ret = IRQ_HANDLED;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001190 }
1191
Paulo Zanoni86642812013-04-12 17:57:57 -03001192 if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1193 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1194
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001195 I915_WRITE(DEIER, de_ier);
1196 POSTING_READ(DEIER);
Ben Widawskyab5c6082013-04-05 13:12:41 -07001197 if (!HAS_PCH_NOP(dev)) {
1198 I915_WRITE(SDEIER, sde_ier);
1199 POSTING_READ(SDEIER);
1200 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001201
1202 return ret;
1203}
1204
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001205static void ilk_gt_irq_handler(struct drm_device *dev,
1206 struct drm_i915_private *dev_priv,
1207 u32 gt_iir)
1208{
1209 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
1210 notify_ring(dev, &dev_priv->ring[RCS]);
1211 if (gt_iir & GT_BSD_USER_INTERRUPT)
1212 notify_ring(dev, &dev_priv->ring[VCS]);
1213}
1214
Daniel Vetterff1f5252012-10-02 15:10:55 +02001215static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001216{
Jesse Barnes46979952011-04-07 13:53:55 -07001217 struct drm_device *dev = (struct drm_device *) arg;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1219 int ret = IRQ_NONE;
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001220 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
Xiang, Haihao881f47b2010-09-19 14:40:43 +01001221
Jesse Barnes46979952011-04-07 13:53:55 -07001222 atomic_inc(&dev_priv->irq_received);
1223
Zou, Nanhai2d109a82009-11-06 02:13:01 +00001224 /* disable master interrupt before clearing iir */
1225 de_ier = I915_READ(DEIER);
1226 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001227 POSTING_READ(DEIER);
Zou, Nanhai2d109a82009-11-06 02:13:01 +00001228
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001229 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1230 * interrupts will will be stored on its back queue, and then we'll be
1231 * able to process them after we restore SDEIER (as soon as we restore
1232 * it, we'll get an interrupt if SDEIIR still has something to process
1233 * due to its back queue). */
1234 sde_ier = I915_READ(SDEIER);
1235 I915_WRITE(SDEIER, 0);
1236 POSTING_READ(SDEIER);
1237
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001238 de_iir = I915_READ(DEIIR);
1239 gt_iir = I915_READ(GTIIR);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001240 pm_iir = I915_READ(GEN6_PMIIR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001241
Daniel Vetteracd15b62012-11-30 11:24:50 +01001242 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
Zou Nan haic7c85102010-01-15 10:29:06 +08001243 goto done;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001244
Zou Nan haic7c85102010-01-15 10:29:06 +08001245 ret = IRQ_HANDLED;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001246
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001247 if (IS_GEN5(dev))
1248 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1249 else
1250 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Zou Nan haic7c85102010-01-15 10:29:06 +08001251
Daniel Vetterce99c252012-12-01 13:53:47 +01001252 if (de_iir & DE_AUX_CHANNEL_A)
1253 dp_aux_irq_handler(dev);
1254
Zou Nan haic7c85102010-01-15 10:29:06 +08001255 if (de_iir & DE_GSE)
Chris Wilson3b617962010-08-24 09:02:58 +01001256 intel_opregion_gse_intr(dev);
Zou Nan haic7c85102010-01-15 10:29:06 +08001257
Daniel Vetter74d44442012-10-02 17:54:35 +02001258 if (de_iir & DE_PIPEA_VBLANK)
1259 drm_handle_vblank(dev, 0);
1260
1261 if (de_iir & DE_PIPEB_VBLANK)
1262 drm_handle_vblank(dev, 1);
1263
Paulo Zanoni86642812013-04-12 17:57:57 -03001264 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1265 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1266 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1267
1268 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1269 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1270 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1271
Zhenyu Wangf072d2e2010-02-09 09:46:19 +08001272 if (de_iir & DE_PLANEA_FLIP_DONE) {
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001273 intel_prepare_page_flip(dev, 0);
Chris Wilson2bbda382010-09-02 17:59:39 +01001274 intel_finish_page_flip_plane(dev, 0);
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001275 }
1276
Zhenyu Wangf072d2e2010-02-09 09:46:19 +08001277 if (de_iir & DE_PLANEB_FLIP_DONE) {
1278 intel_prepare_page_flip(dev, 1);
Chris Wilson2bbda382010-09-02 17:59:39 +01001279 intel_finish_page_flip_plane(dev, 1);
Jesse Barnes013d5aa2010-01-29 11:18:31 -08001280 }
Li Pengc062df62010-01-23 00:12:58 +08001281
Zou Nan haic7c85102010-01-15 10:29:06 +08001282 /* check event from PCH */
Jesse Barnes776ad802011-01-04 15:09:39 -08001283 if (de_iir & DE_PCH_EVENT) {
Daniel Vetteracd15b62012-11-30 11:24:50 +01001284 u32 pch_iir = I915_READ(SDEIIR);
1285
Adam Jackson23e81d62012-06-06 15:45:44 -04001286 if (HAS_PCH_CPT(dev))
1287 cpt_irq_handler(dev, pch_iir);
1288 else
1289 ibx_irq_handler(dev, pch_iir);
Daniel Vetteracd15b62012-11-30 11:24:50 +01001290
1291 /* should clear PCH hotplug event before clear CPU irq */
1292 I915_WRITE(SDEIIR, pch_iir);
Jesse Barnes776ad802011-01-04 15:09:39 -08001293 }
Zou Nan haic7c85102010-01-15 10:29:06 +08001294
Daniel Vetter73edd18f2012-08-08 23:35:37 +02001295 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1296 ironlake_handle_rps_change(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001297
Chris Wilsonfc6826d2012-04-15 11:56:03 +01001298 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
1299 gen6_queue_rps_work(dev_priv, pm_iir);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001300
Zou Nan haic7c85102010-01-15 10:29:06 +08001301 I915_WRITE(GTIIR, gt_iir);
1302 I915_WRITE(DEIIR, de_iir);
Ben Widawsky4912d042011-04-25 11:25:20 -07001303 I915_WRITE(GEN6_PMIIR, pm_iir);
Zou Nan haic7c85102010-01-15 10:29:06 +08001304
1305done:
Zou, Nanhai2d109a82009-11-06 02:13:01 +00001306 I915_WRITE(DEIER, de_ier);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001307 POSTING_READ(DEIER);
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001308 I915_WRITE(SDEIER, sde_ier);
1309 POSTING_READ(SDEIER);
Zou, Nanhai2d109a82009-11-06 02:13:01 +00001310
Zhenyu Wang036a4a72009-06-08 14:40:19 +08001311 return ret;
1312}
1313
Jesse Barnes8a905232009-07-11 16:48:03 -04001314/**
1315 * i915_error_work_func - do process context error handling work
1316 * @work: work struct
1317 *
1318 * Fire an error uevent so userspace can see that a hang or error
1319 * was detected.
1320 */
1321static void i915_error_work_func(struct work_struct *work)
1322{
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001323 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1324 work);
1325 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1326 gpu_error);
Jesse Barnes8a905232009-07-11 16:48:03 -04001327 struct drm_device *dev = dev_priv->dev;
Daniel Vetterf69061b2012-12-06 09:01:42 +01001328 struct intel_ring_buffer *ring;
Ben Gamarif316a422009-09-14 17:48:46 -04001329 char *error_event[] = { "ERROR=1", NULL };
1330 char *reset_event[] = { "RESET=1", NULL };
1331 char *reset_done_event[] = { "ERROR=0", NULL };
Daniel Vetterf69061b2012-12-06 09:01:42 +01001332 int i, ret;
Jesse Barnes8a905232009-07-11 16:48:03 -04001333
Ben Gamarif316a422009-09-14 17:48:46 -04001334 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04001335
Daniel Vetter7db0ba22012-12-06 16:23:37 +01001336 /*
1337 * Note that there's only one work item which does gpu resets, so we
1338 * need not worry about concurrent gpu resets potentially incrementing
1339 * error->reset_counter twice. We only need to take care of another
1340 * racing irq/hangcheck declaring the gpu dead for a second time. A
1341 * quick check for that is good enough: schedule_work ensures the
1342 * correct ordering between hang detection and this work item, and since
1343 * the reset in-progress bit is only ever set by code outside of this
1344 * work we don't need to worry about any other races.
1345 */
1346 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +01001347 DRM_DEBUG_DRIVER("resetting chip\n");
Daniel Vetter7db0ba22012-12-06 16:23:37 +01001348 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1349 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001350
Daniel Vetterf69061b2012-12-06 09:01:42 +01001351 ret = i915_reset(dev);
1352
1353 if (ret == 0) {
1354 /*
1355 * After all the gem state is reset, increment the reset
1356 * counter and wake up everyone waiting for the reset to
1357 * complete.
1358 *
1359 * Since unlock operations are a one-sided barrier only,
1360 * we need to insert a barrier here to order any seqno
1361 * updates before
1362 * the counter increment.
1363 */
1364 smp_mb__before_atomic_inc();
1365 atomic_inc(&dev_priv->gpu_error.reset_counter);
1366
1367 kobject_uevent_env(&dev->primary->kdev.kobj,
1368 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001369 } else {
1370 atomic_set(&error->reset_counter, I915_WEDGED);
Ben Gamarif316a422009-09-14 17:48:46 -04001371 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001372
Daniel Vetterf69061b2012-12-06 09:01:42 +01001373 for_each_ring(ring, dev_priv, i)
1374 wake_up_all(&ring->irq_queue);
1375
Ville Syrjälä96a02912013-02-18 19:08:49 +02001376 intel_display_handle_reset(dev);
1377
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001378 wake_up_all(&dev_priv->gpu_error.reset_queue);
Ben Gamarif316a422009-09-14 17:48:46 -04001379 }
Jesse Barnes8a905232009-07-11 16:48:03 -04001380}
1381
Daniel Vetter85f9e502012-08-31 21:42:26 +02001382/* NB: please notice the memset */
1383static void i915_get_extra_instdone(struct drm_device *dev,
1384 uint32_t *instdone)
1385{
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1388
1389 switch(INTEL_INFO(dev)->gen) {
1390 case 2:
1391 case 3:
1392 instdone[0] = I915_READ(INSTDONE);
1393 break;
1394 case 4:
1395 case 5:
1396 case 6:
1397 instdone[0] = I915_READ(INSTDONE_I965);
1398 instdone[1] = I915_READ(INSTDONE1);
1399 break;
1400 default:
1401 WARN_ONCE(1, "Unsupported platform\n");
1402 case 7:
1403 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1404 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1405 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1406 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1407 break;
1408 }
1409}
1410
Chris Wilson3bd3c932010-08-19 08:19:30 +01001411#ifdef CONFIG_DEBUG_FS
Chris Wilson9df30792010-02-18 10:24:56 +00001412static struct drm_i915_error_object *
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001413i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1414 struct drm_i915_gem_object *src,
1415 const int num_pages)
Chris Wilson9df30792010-02-18 10:24:56 +00001416{
1417 struct drm_i915_error_object *dst;
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001418 int i;
Chris Wilsone56660d2010-08-07 11:01:26 +01001419 u32 reloc_offset;
Chris Wilson9df30792010-02-18 10:24:56 +00001420
Chris Wilson05394f32010-11-08 19:18:58 +00001421 if (src == NULL || src->pages == NULL)
Chris Wilson9df30792010-02-18 10:24:56 +00001422 return NULL;
1423
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001424 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
Chris Wilson9df30792010-02-18 10:24:56 +00001425 if (dst == NULL)
1426 return NULL;
1427
Chris Wilson05394f32010-11-08 19:18:58 +00001428 reloc_offset = src->gtt_offset;
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001429 for (i = 0; i < num_pages; i++) {
Andrew Morton788885a2010-05-11 14:07:05 -07001430 unsigned long flags;
Chris Wilsone56660d2010-08-07 11:01:26 +01001431 void *d;
Andrew Morton788885a2010-05-11 14:07:05 -07001432
Chris Wilsone56660d2010-08-07 11:01:26 +01001433 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
Chris Wilson9df30792010-02-18 10:24:56 +00001434 if (d == NULL)
1435 goto unwind;
Chris Wilsone56660d2010-08-07 11:01:26 +01001436
Andrew Morton788885a2010-05-11 14:07:05 -07001437 local_irq_save(flags);
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001438 if (reloc_offset < dev_priv->gtt.mappable_end &&
Daniel Vetter74898d72012-02-15 23:50:22 +01001439 src->has_global_gtt_mapping) {
Chris Wilson172975aa2011-12-14 13:57:25 +01001440 void __iomem *s;
1441
1442 /* Simply ignore tiling or any overlapping fence.
1443 * It's part of the error state, and this hopefully
1444 * captures what the GPU read.
1445 */
1446
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001447 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
Chris Wilson172975aa2011-12-14 13:57:25 +01001448 reloc_offset);
1449 memcpy_fromio(d, s, PAGE_SIZE);
1450 io_mapping_unmap_atomic(s);
Chris Wilson960e3562012-11-15 11:32:23 +00001451 } else if (src->stolen) {
1452 unsigned long offset;
1453
1454 offset = dev_priv->mm.stolen_base;
1455 offset += src->stolen->start;
1456 offset += i << PAGE_SHIFT;
1457
Daniel Vetter1a240d42012-11-29 22:18:51 +01001458 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
Chris Wilson172975aa2011-12-14 13:57:25 +01001459 } else {
Chris Wilson9da3da62012-06-01 15:20:22 +01001460 struct page *page;
Chris Wilson172975aa2011-12-14 13:57:25 +01001461 void *s;
1462
Chris Wilson9da3da62012-06-01 15:20:22 +01001463 page = i915_gem_object_get_page(src, i);
Chris Wilson172975aa2011-12-14 13:57:25 +01001464
Chris Wilson9da3da62012-06-01 15:20:22 +01001465 drm_clflush_pages(&page, 1);
1466
1467 s = kmap_atomic(page);
Chris Wilson172975aa2011-12-14 13:57:25 +01001468 memcpy(d, s, PAGE_SIZE);
1469 kunmap_atomic(s);
1470
Chris Wilson9da3da62012-06-01 15:20:22 +01001471 drm_clflush_pages(&page, 1);
Chris Wilson172975aa2011-12-14 13:57:25 +01001472 }
Andrew Morton788885a2010-05-11 14:07:05 -07001473 local_irq_restore(flags);
Chris Wilsone56660d2010-08-07 11:01:26 +01001474
Chris Wilson9da3da62012-06-01 15:20:22 +01001475 dst->pages[i] = d;
Chris Wilsone56660d2010-08-07 11:01:26 +01001476
1477 reloc_offset += PAGE_SIZE;
Chris Wilson9df30792010-02-18 10:24:56 +00001478 }
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001479 dst->page_count = num_pages;
Chris Wilson05394f32010-11-08 19:18:58 +00001480 dst->gtt_offset = src->gtt_offset;
Chris Wilson9df30792010-02-18 10:24:56 +00001481
1482 return dst;
1483
1484unwind:
Chris Wilson9da3da62012-06-01 15:20:22 +01001485 while (i--)
1486 kfree(dst->pages[i]);
Chris Wilson9df30792010-02-18 10:24:56 +00001487 kfree(dst);
1488 return NULL;
1489}
Ben Widawskyd0d045e2013-02-24 18:10:00 -08001490#define i915_error_object_create(dev_priv, src) \
1491 i915_error_object_create_sized((dev_priv), (src), \
1492 (src)->base.size>>PAGE_SHIFT)
Chris Wilson9df30792010-02-18 10:24:56 +00001493
1494static void
1495i915_error_object_free(struct drm_i915_error_object *obj)
1496{
1497 int page;
1498
1499 if (obj == NULL)
1500 return;
1501
1502 for (page = 0; page < obj->page_count; page++)
1503 kfree(obj->pages[page]);
1504
1505 kfree(obj);
1506}
1507
Daniel Vetter742cbee2012-04-27 15:17:39 +02001508void
1509i915_error_state_free(struct kref *error_ref)
Chris Wilson9df30792010-02-18 10:24:56 +00001510{
Daniel Vetter742cbee2012-04-27 15:17:39 +02001511 struct drm_i915_error_state *error = container_of(error_ref,
1512 typeof(*error), ref);
Chris Wilsone2f973d2011-01-27 19:15:11 +00001513 int i;
1514
Chris Wilson52d39a22012-02-15 11:25:37 +00001515 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1516 i915_error_object_free(error->ring[i].batchbuffer);
1517 i915_error_object_free(error->ring[i].ringbuffer);
1518 kfree(error->ring[i].requests);
1519 }
Chris Wilsone2f973d2011-01-27 19:15:11 +00001520
Chris Wilson9df30792010-02-18 10:24:56 +00001521 kfree(error->active_bo);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001522 kfree(error->overlay);
Chris Wilson9df30792010-02-18 10:24:56 +00001523 kfree(error);
1524}
Chris Wilson1b502472012-04-24 15:47:30 +01001525static void capture_bo(struct drm_i915_error_buffer *err,
1526 struct drm_i915_gem_object *obj)
1527{
1528 err->size = obj->base.size;
1529 err->name = obj->base.name;
Chris Wilson0201f1e2012-07-20 12:41:01 +01001530 err->rseqno = obj->last_read_seqno;
1531 err->wseqno = obj->last_write_seqno;
Chris Wilson1b502472012-04-24 15:47:30 +01001532 err->gtt_offset = obj->gtt_offset;
1533 err->read_domains = obj->base.read_domains;
1534 err->write_domain = obj->base.write_domain;
1535 err->fence_reg = obj->fence_reg;
1536 err->pinned = 0;
1537 if (obj->pin_count > 0)
1538 err->pinned = 1;
1539 if (obj->user_pin_count > 0)
1540 err->pinned = -1;
1541 err->tiling = obj->tiling_mode;
1542 err->dirty = obj->dirty;
1543 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1544 err->ring = obj->ring ? obj->ring->id : -1;
1545 err->cache_level = obj->cache_level;
1546}
Chris Wilson9df30792010-02-18 10:24:56 +00001547
Chris Wilson1b502472012-04-24 15:47:30 +01001548static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1549 int count, struct list_head *head)
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001550{
1551 struct drm_i915_gem_object *obj;
1552 int i = 0;
1553
1554 list_for_each_entry(obj, head, mm_list) {
Chris Wilson1b502472012-04-24 15:47:30 +01001555 capture_bo(err++, obj);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001556 if (++i == count)
1557 break;
Chris Wilson1b502472012-04-24 15:47:30 +01001558 }
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001559
Chris Wilson1b502472012-04-24 15:47:30 +01001560 return i;
1561}
1562
1563static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1564 int count, struct list_head *head)
1565{
1566 struct drm_i915_gem_object *obj;
1567 int i = 0;
1568
1569 list_for_each_entry(obj, head, gtt_list) {
1570 if (obj->pin_count == 0)
1571 continue;
1572
1573 capture_bo(err++, obj);
1574 if (++i == count)
1575 break;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001576 }
1577
1578 return i;
1579}
1580
Chris Wilson748ebc62010-10-24 10:28:47 +01001581static void i915_gem_record_fences(struct drm_device *dev,
1582 struct drm_i915_error_state *error)
1583{
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 int i;
1586
1587 /* Fences */
1588 switch (INTEL_INFO(dev)->gen) {
Daniel Vetter775d17b2011-10-09 21:52:01 +02001589 case 7:
Chris Wilson748ebc62010-10-24 10:28:47 +01001590 case 6:
Ville Syrjälä42b5aea2013-04-09 13:02:47 +03001591 for (i = 0; i < dev_priv->num_fence_regs; i++)
Chris Wilson748ebc62010-10-24 10:28:47 +01001592 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1593 break;
1594 case 5:
1595 case 4:
1596 for (i = 0; i < 16; i++)
1597 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1598 break;
1599 case 3:
1600 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1601 for (i = 0; i < 8; i++)
1602 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1603 case 2:
1604 for (i = 0; i < 8; i++)
1605 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1606 break;
1607
Ben Widawsky7dbf9d62012-12-18 10:31:22 -08001608 default:
1609 BUG();
Chris Wilson748ebc62010-10-24 10:28:47 +01001610 }
1611}
1612
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001613static struct drm_i915_error_object *
1614i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1615 struct intel_ring_buffer *ring)
1616{
1617 struct drm_i915_gem_object *obj;
1618 u32 seqno;
1619
1620 if (!ring->get_seqno)
1621 return NULL;
1622
Daniel Vetterb45305f2012-12-17 16:21:27 +01001623 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1624 u32 acthd = I915_READ(ACTHD);
1625
1626 if (WARN_ON(ring->id != RCS))
1627 return NULL;
1628
1629 obj = ring->private;
1630 if (acthd >= obj->gtt_offset &&
1631 acthd < obj->gtt_offset + obj->base.size)
1632 return i915_error_object_create(dev_priv, obj);
1633 }
1634
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01001635 seqno = ring->get_seqno(ring, false);
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001636 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1637 if (obj->ring != ring)
1638 continue;
1639
Chris Wilson0201f1e2012-07-20 12:41:01 +01001640 if (i915_seqno_passed(seqno, obj->last_read_seqno))
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001641 continue;
1642
1643 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1644 continue;
1645
1646 /* We need to copy these to an anonymous buffer as the simplest
1647 * method to avoid being overwritten by userspace.
1648 */
1649 return i915_error_object_create(dev_priv, obj);
1650 }
1651
1652 return NULL;
1653}
1654
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001655static void i915_record_ring_state(struct drm_device *dev,
1656 struct drm_i915_error_state *error,
1657 struct intel_ring_buffer *ring)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
Daniel Vetter33f3f512011-12-14 13:57:39 +01001661 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilson12f55812012-07-05 17:14:01 +01001662 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
Daniel Vetter33f3f512011-12-14 13:57:39 +01001663 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
Daniel Vetter7e3b8732012-02-01 22:26:45 +01001664 error->semaphore_mboxes[ring->id][0]
1665 = I915_READ(RING_SYNC_0(ring->mmio_base));
1666 error->semaphore_mboxes[ring->id][1]
1667 = I915_READ(RING_SYNC_1(ring->mmio_base));
Chris Wilsondf2b23d2012-11-27 17:06:54 +00001668 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1669 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
Daniel Vetter33f3f512011-12-14 13:57:39 +01001670 }
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001671
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001672 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001673 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001674 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1675 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1676 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001677 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
Ben Widawsky050ee912012-08-22 11:32:15 -07001678 if (ring->id == RCS)
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001679 error->bbaddr = I915_READ64(BB_ADDR);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001680 } else {
Daniel Vetter9d2f41f2012-04-02 21:41:45 +02001681 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001682 error->ipeir[ring->id] = I915_READ(IPEIR);
1683 error->ipehr[ring->id] = I915_READ(IPEHR);
1684 error->instdone[ring->id] = I915_READ(INSTDONE);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001685 }
1686
Ben Widawsky9574b3f2012-04-26 16:03:01 -07001687 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001688 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01001689 error->seqno[ring->id] = ring->get_seqno(ring, false);
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001690 error->acthd[ring->id] = intel_ring_get_active_head(ring);
Daniel Vetterc1cd90e2011-12-14 13:57:02 +01001691 error->head[ring->id] = I915_READ_HEAD(ring);
1692 error->tail[ring->id] = I915_READ_TAIL(ring);
Chris Wilson0f3b6842013-01-15 12:05:55 +00001693 error->ctl[ring->id] = I915_READ_CTL(ring);
Daniel Vetter7e3b8732012-02-01 22:26:45 +01001694
1695 error->cpu_ring_head[ring->id] = ring->head;
1696 error->cpu_ring_tail[ring->id] = ring->tail;
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001697}
1698
Ben Widawsky8c123e52013-03-04 17:00:29 -08001699
1700static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1701 struct drm_i915_error_state *error,
1702 struct drm_i915_error_ring *ering)
1703{
1704 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1705 struct drm_i915_gem_object *obj;
1706
1707 /* Currently render ring is the only HW context user */
1708 if (ring->id != RCS || !error->ccid)
1709 return;
1710
1711 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1712 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1713 ering->ctx = i915_error_object_create_sized(dev_priv,
1714 obj, 1);
1715 }
1716 }
1717}
1718
Chris Wilson52d39a22012-02-15 11:25:37 +00001719static void i915_gem_record_rings(struct drm_device *dev,
1720 struct drm_i915_error_state *error)
1721{
1722 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb4519512012-05-11 14:29:30 +01001723 struct intel_ring_buffer *ring;
Chris Wilson52d39a22012-02-15 11:25:37 +00001724 struct drm_i915_gem_request *request;
1725 int i, count;
1726
Chris Wilsonb4519512012-05-11 14:29:30 +01001727 for_each_ring(ring, dev_priv, i) {
Chris Wilson52d39a22012-02-15 11:25:37 +00001728 i915_record_ring_state(dev, error, ring);
1729
1730 error->ring[i].batchbuffer =
1731 i915_error_first_batchbuffer(dev_priv, ring);
1732
1733 error->ring[i].ringbuffer =
1734 i915_error_object_create(dev_priv, ring->obj);
1735
Ben Widawsky8c123e52013-03-04 17:00:29 -08001736
1737 i915_gem_record_active_context(ring, error, &error->ring[i]);
1738
Chris Wilson52d39a22012-02-15 11:25:37 +00001739 count = 0;
1740 list_for_each_entry(request, &ring->request_list, list)
1741 count++;
1742
1743 error->ring[i].num_requests = count;
1744 error->ring[i].requests =
1745 kmalloc(count*sizeof(struct drm_i915_error_request),
1746 GFP_ATOMIC);
1747 if (error->ring[i].requests == NULL) {
1748 error->ring[i].num_requests = 0;
1749 continue;
1750 }
1751
1752 count = 0;
1753 list_for_each_entry(request, &ring->request_list, list) {
1754 struct drm_i915_error_request *erq;
1755
1756 erq = &error->ring[i].requests[count++];
1757 erq->seqno = request->seqno;
1758 erq->jiffies = request->emitted_jiffies;
Chris Wilsonee4f42b2012-02-15 11:25:38 +00001759 erq->tail = request->tail;
Chris Wilson52d39a22012-02-15 11:25:37 +00001760 }
1761 }
1762}
1763
Jesse Barnes8a905232009-07-11 16:48:03 -04001764/**
1765 * i915_capture_error_state - capture an error record for later analysis
1766 * @dev: drm device
1767 *
1768 * Should be called when an error is detected (either a hang or an error
1769 * interrupt) to capture error state from the time of the error. Fills
1770 * out a structure which becomes available in debugfs for user level tools
1771 * to pick up.
1772 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001773static void i915_capture_error_state(struct drm_device *dev)
1774{
1775 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00001776 struct drm_i915_gem_object *obj;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001777 struct drm_i915_error_state *error;
1778 unsigned long flags;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001779 int i, pipe;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001780
Daniel Vetter99584db2012-11-14 17:14:04 +01001781 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1782 error = dev_priv->gpu_error.first_error;
1783 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001784 if (error)
1785 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001786
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001787 /* Account for pipe specific data like PIPE*STAT */
Daniel Vetter33f3f512011-12-14 13:57:39 +01001788 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001789 if (!error) {
Chris Wilson9df30792010-02-18 10:24:56 +00001790 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1791 return;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001792 }
1793
Paulo Zanoni5d83d292013-03-06 20:03:22 -03001794 DRM_INFO("capturing error event; look for more information in "
Ben Widawsky2f86f192013-01-28 15:32:15 -08001795 "/sys/kernel/debug/dri/%d/i915_error_state\n",
Chris Wilsonb6f78332011-02-01 14:15:55 +00001796 dev->primary->index);
Chris Wilson2fa772f2010-10-01 13:23:27 +01001797
Daniel Vetter742cbee2012-04-27 15:17:39 +02001798 kref_init(&error->ref);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001799 error->eir = I915_READ(EIR);
1800 error->pgtbl_er = I915_READ(PGTBL_ER);
Ben Widawsky211816e2013-02-24 18:10:01 -08001801 if (HAS_HW_CONTEXTS(dev))
1802 error->ccid = I915_READ(CCID);
Ben Widawskybe998e22012-04-26 16:03:00 -07001803
1804 if (HAS_PCH_SPLIT(dev))
1805 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1806 else if (IS_VALLEYVIEW(dev))
1807 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1808 else if (IS_GEN2(dev))
1809 error->ier = I915_READ16(IER);
1810 else
1811 error->ier = I915_READ(IER);
1812
Chris Wilson0f3b6842013-01-15 12:05:55 +00001813 if (INTEL_INFO(dev)->gen >= 6)
1814 error->derrmr = I915_READ(DERRMR);
1815
1816 if (IS_VALLEYVIEW(dev))
1817 error->forcewake = I915_READ(FORCEWAKE_VLV);
1818 else if (INTEL_INFO(dev)->gen >= 7)
1819 error->forcewake = I915_READ(FORCEWAKE_MT);
1820 else if (INTEL_INFO(dev)->gen == 6)
1821 error->forcewake = I915_READ(FORCEWAKE);
1822
Paulo Zanoni4f3308b2013-03-22 14:24:16 -03001823 if (!HAS_PCH_SPLIT(dev))
1824 for_each_pipe(pipe)
1825 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
Daniel Vetterd27b1e02011-12-14 13:57:01 +01001826
Daniel Vetter33f3f512011-12-14 13:57:39 +01001827 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilsonf4068392010-10-27 20:36:41 +01001828 error->error = I915_READ(ERROR_GEN6);
Daniel Vetter33f3f512011-12-14 13:57:39 +01001829 error->done_reg = I915_READ(DONE_REG);
1830 }
Chris Wilsonadd354d2010-10-29 19:00:51 +01001831
Ben Widawsky71e172e2012-08-20 16:15:13 -07001832 if (INTEL_INFO(dev)->gen == 7)
1833 error->err_int = I915_READ(GEN7_ERR_INT);
1834
Ben Widawsky050ee912012-08-22 11:32:15 -07001835 i915_get_extra_instdone(dev, error->extra_instdone);
1836
Chris Wilson748ebc62010-10-24 10:28:47 +01001837 i915_gem_record_fences(dev, error);
Chris Wilson52d39a22012-02-15 11:25:37 +00001838 i915_gem_record_rings(dev, error);
Chris Wilson9df30792010-02-18 10:24:56 +00001839
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001840 /* Record buffers on the active and pinned lists. */
Chris Wilson9df30792010-02-18 10:24:56 +00001841 error->active_bo = NULL;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001842 error->pinned_bo = NULL;
Chris Wilson9df30792010-02-18 10:24:56 +00001843
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001844 i = 0;
1845 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1846 i++;
1847 error->active_bo_count = i;
Chris Wilson6c085a72012-08-20 11:40:46 +02001848 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
Chris Wilson1b502472012-04-24 15:47:30 +01001849 if (obj->pin_count)
1850 i++;
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001851 error->pinned_bo_count = i - error->active_bo_count;
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001852
Chris Wilson8e934db2011-01-24 12:34:00 +00001853 error->active_bo = NULL;
1854 error->pinned_bo = NULL;
Chris Wilsonbcfb2e22011-01-07 21:06:07 +00001855 if (i) {
1856 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
Chris Wilson9df30792010-02-18 10:24:56 +00001857 GFP_ATOMIC);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001858 if (error->active_bo)
1859 error->pinned_bo =
1860 error->active_bo + error->active_bo_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001861 }
1862
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001863 if (error->active_bo)
1864 error->active_bo_count =
Chris Wilson1b502472012-04-24 15:47:30 +01001865 capture_active_bo(error->active_bo,
1866 error->active_bo_count,
1867 &dev_priv->mm.active_list);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001868
1869 if (error->pinned_bo)
1870 error->pinned_bo_count =
Chris Wilson1b502472012-04-24 15:47:30 +01001871 capture_pinned_bo(error->pinned_bo,
1872 error->pinned_bo_count,
Chris Wilson6c085a72012-08-20 11:40:46 +02001873 &dev_priv->mm.bound_list);
Chris Wilsonc724e8a2010-11-22 08:07:02 +00001874
Jesse Barnes8a905232009-07-11 16:48:03 -04001875 do_gettimeofday(&error->time);
1876
Chris Wilson6ef3d422010-08-04 20:26:07 +01001877 error->overlay = intel_overlay_capture_error_state(dev);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00001878 error->display = intel_display_capture_error_state(dev);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001879
Daniel Vetter99584db2012-11-14 17:14:04 +01001880 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1881 if (dev_priv->gpu_error.first_error == NULL) {
1882 dev_priv->gpu_error.first_error = error;
Chris Wilson9df30792010-02-18 10:24:56 +00001883 error = NULL;
1884 }
Daniel Vetter99584db2012-11-14 17:14:04 +01001885 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001886
1887 if (error)
Daniel Vetter742cbee2012-04-27 15:17:39 +02001888 i915_error_state_free(&error->ref);
Chris Wilson9df30792010-02-18 10:24:56 +00001889}
1890
1891void i915_destroy_error_state(struct drm_device *dev)
1892{
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 struct drm_i915_error_state *error;
Ben Widawsky6dc0e812012-01-23 15:30:02 -08001895 unsigned long flags;
Chris Wilson9df30792010-02-18 10:24:56 +00001896
Daniel Vetter99584db2012-11-14 17:14:04 +01001897 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1898 error = dev_priv->gpu_error.first_error;
1899 dev_priv->gpu_error.first_error = NULL;
1900 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
Chris Wilson9df30792010-02-18 10:24:56 +00001901
1902 if (error)
Daniel Vetter742cbee2012-04-27 15:17:39 +02001903 kref_put(&error->ref, i915_error_state_free);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001904}
Chris Wilson3bd3c932010-08-19 08:19:30 +01001905#else
1906#define i915_capture_error_state(x)
1907#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -07001908
Chris Wilson35aed2e2010-05-27 13:18:12 +01001909static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04001910{
1911 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07001912 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04001913 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07001914 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04001915
Chris Wilson35aed2e2010-05-27 13:18:12 +01001916 if (!eir)
1917 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04001918
Joe Perchesa70491c2012-03-18 13:00:11 -07001919 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04001920
Ben Widawskybd9854f2012-08-23 15:18:09 -07001921 i915_get_extra_instdone(dev, instdone);
1922
Jesse Barnes8a905232009-07-11 16:48:03 -04001923 if (IS_G4X(dev)) {
1924 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1925 u32 ipeir = I915_READ(IPEIR_I965);
1926
Joe Perchesa70491c2012-03-18 13:00:11 -07001927 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1928 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07001929 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1930 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07001931 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001932 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001933 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001934 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001935 }
1936 if (eir & GM45_ERROR_PAGE_TABLE) {
1937 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001938 pr_err("page table error\n");
1939 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001940 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001941 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001942 }
1943 }
1944
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001945 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001946 if (eir & I915_ERROR_PAGE_TABLE) {
1947 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001948 pr_err("page table error\n");
1949 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001950 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001951 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001952 }
1953 }
1954
1955 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001956 pr_err("memory refresh error:\n");
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001957 for_each_pipe(pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07001958 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001959 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04001960 /* pipestat has already been acked */
1961 }
1962 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001963 pr_err("instruction error\n");
1964 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07001965 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1966 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001967 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001968 u32 ipeir = I915_READ(IPEIR);
1969
Joe Perchesa70491c2012-03-18 13:00:11 -07001970 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1971 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07001972 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04001973 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001974 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001975 } else {
1976 u32 ipeir = I915_READ(IPEIR_I965);
1977
Joe Perchesa70491c2012-03-18 13:00:11 -07001978 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1979 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07001980 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001981 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001982 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001983 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001984 }
1985 }
1986
1987 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001988 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001989 eir = I915_READ(EIR);
1990 if (eir) {
1991 /*
1992 * some errors might have become stuck,
1993 * mask them.
1994 */
1995 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1996 I915_WRITE(EMR, I915_READ(EMR) | eir);
1997 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1998 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01001999}
2000
2001/**
2002 * i915_handle_error - handle an error interrupt
2003 * @dev: drm device
2004 *
2005 * Do some basic checking of regsiter state at error interrupt time and
2006 * dump it to the syslog. Also call i915_capture_error_state() to make
2007 * sure we get a record and make it available in debugfs. Fire a uevent
2008 * so userspace knows something bad happened (should trigger collection
2009 * of a ring dump etc.).
2010 */
Chris Wilson527f9e92010-11-11 01:16:58 +00002011void i915_handle_error(struct drm_device *dev, bool wedged)
Chris Wilson35aed2e2010-05-27 13:18:12 +01002012{
2013 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb4519512012-05-11 14:29:30 +01002014 struct intel_ring_buffer *ring;
2015 int i;
Chris Wilson35aed2e2010-05-27 13:18:12 +01002016
2017 i915_capture_error_state(dev);
2018 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002019
Ben Gamariba1234d2009-09-14 17:48:47 -04002020 if (wedged) {
Daniel Vetterf69061b2012-12-06 09:01:42 +01002021 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2022 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04002023
Ben Gamari11ed50e2009-09-14 17:48:45 -04002024 /*
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002025 * Wakeup waiting processes so that the reset work item
2026 * doesn't deadlock trying to grab various locks.
Ben Gamari11ed50e2009-09-14 17:48:45 -04002027 */
Chris Wilsonb4519512012-05-11 14:29:30 +01002028 for_each_ring(ring, dev_priv, i)
2029 wake_up_all(&ring->irq_queue);
Ben Gamari11ed50e2009-09-14 17:48:45 -04002030 }
2031
Daniel Vetter99584db2012-11-14 17:14:04 +01002032 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
Jesse Barnes8a905232009-07-11 16:48:03 -04002033}
2034
Ville Syrjälä21ad8332013-02-19 15:16:39 +02002035static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002036{
2037 drm_i915_private_t *dev_priv = dev->dev_private;
2038 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00002040 struct drm_i915_gem_object *obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002041 struct intel_unpin_work *work;
2042 unsigned long flags;
2043 bool stall_detected;
2044
2045 /* Ignore early vblank irqs */
2046 if (intel_crtc == NULL)
2047 return;
2048
2049 spin_lock_irqsave(&dev->event_lock, flags);
2050 work = intel_crtc->unpin_work;
2051
Chris Wilsone7d841c2012-12-03 11:36:30 +00002052 if (work == NULL ||
2053 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2054 !work->enable_stall_check) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002055 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2056 spin_unlock_irqrestore(&dev->event_lock, flags);
2057 return;
2058 }
2059
2060 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
Chris Wilson05394f32010-11-08 19:18:58 +00002061 obj = work->pending_flip_obj;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002062 if (INTEL_INFO(dev)->gen >= 4) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002063 int dspsurf = DSPSURF(intel_crtc->plane);
Armin Reese446f2542012-03-30 16:20:16 -07002064 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2065 obj->gtt_offset;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002066 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002067 int dspaddr = DSPADDR(intel_crtc->plane);
Chris Wilson05394f32010-11-08 19:18:58 +00002068 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002069 crtc->y * crtc->fb->pitches[0] +
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01002070 crtc->x * crtc->fb->bits_per_pixel/8);
2071 }
2072
2073 spin_unlock_irqrestore(&dev->event_lock, flags);
2074
2075 if (stall_detected) {
2076 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2077 intel_prepare_page_flip(dev, intel_crtc->plane);
2078 }
2079}
2080
Keith Packard42f52ef2008-10-18 19:39:29 -07002081/* Called from drm generic code, passed 'crtc' which
2082 * we use as a pipe index
2083 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002084static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002085{
2086 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002087 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002088
Chris Wilson5eddb702010-09-11 13:48:45 +01002089 if (!i915_pipe_enabled(dev, pipe))
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002090 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002091
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002092 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002093 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08002094 i915_enable_pipestat(dev_priv, pipe,
2095 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07002096 else
Keith Packard7c463582008-11-04 02:03:27 -08002097 i915_enable_pipestat(dev_priv, pipe,
2098 PIPE_VBLANK_INTERRUPT_ENABLE);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002099
2100 /* maintain vblank delivery even in deep C-states */
2101 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02002102 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002103 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002104
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002105 return 0;
2106}
2107
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002108static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002109{
2110 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2111 unsigned long irqflags;
2112
2113 if (!i915_pipe_enabled(dev, pipe))
2114 return -EINVAL;
2115
2116 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2117 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
Akshay Joshi0206e352011-08-16 15:34:10 -04002118 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002119 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2120
2121 return 0;
2122}
2123
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002124static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002125{
2126 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2127 unsigned long irqflags;
2128
2129 if (!i915_pipe_enabled(dev, pipe))
2130 return -EINVAL;
2131
2132 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilsonb615b572012-05-02 09:52:12 +01002133 ironlake_enable_display_irq(dev_priv,
2134 DE_PIPEA_VBLANK_IVB << (5 * pipe));
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002135 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2136
2137 return 0;
2138}
2139
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002140static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2141{
2142 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2143 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002144 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002145
2146 if (!i915_pipe_enabled(dev, pipe))
2147 return -EINVAL;
2148
2149 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002150 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002151 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002152 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002153 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002154 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002155 I915_WRITE(VLV_IMR, imr);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002156 i915_enable_pipestat(dev_priv, pipe,
2157 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002158 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2159
2160 return 0;
2161}
2162
Keith Packard42f52ef2008-10-18 19:39:29 -07002163/* Called from drm generic code, passed 'crtc' which
2164 * we use as a pipe index
2165 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002166static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002167{
2168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002169 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002170
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002171 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002172 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02002173 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson8692d00e2011-02-05 10:08:21 +00002174
Jesse Barnesf796cf82011-04-07 13:58:17 -07002175 i915_disable_pipestat(dev_priv, pipe,
2176 PIPE_VBLANK_INTERRUPT_ENABLE |
2177 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2178 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2179}
2180
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002181static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002182{
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2184 unsigned long irqflags;
2185
2186 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2187 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
Akshay Joshi0206e352011-08-16 15:34:10 -04002188 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002189 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002190}
2191
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002192static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002193{
2194 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2195 unsigned long irqflags;
2196
2197 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilsonb615b572012-05-02 09:52:12 +01002198 ironlake_disable_display_irq(dev_priv,
2199 DE_PIPEA_VBLANK_IVB << (pipe * 5));
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002200 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2201}
2202
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002203static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2204{
2205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2206 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002207 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002208
2209 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002210 i915_disable_pipestat(dev_priv, pipe,
2211 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002212 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002213 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002214 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002215 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002216 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002217 I915_WRITE(VLV_IMR, imr);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002218 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2219}
2220
Chris Wilson893eead2010-10-27 14:44:35 +01002221static u32
2222ring_last_seqno(struct intel_ring_buffer *ring)
Zou Nan hai852835f2010-05-21 09:08:56 +08002223{
Chris Wilson893eead2010-10-27 14:44:35 +01002224 return list_entry(ring->request_list.prev,
2225 struct drm_i915_gem_request, list)->seqno;
2226}
2227
2228static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
2229{
2230 if (list_empty(&ring->request_list) ||
Chris Wilsonb2eadbc2012-08-09 10:58:30 +01002231 i915_seqno_passed(ring->get_seqno(ring, false),
2232 ring_last_seqno(ring))) {
Chris Wilson893eead2010-10-27 14:44:35 +01002233 /* Issue a wake-up to catch stuck h/w. */
Ben Widawsky9574b3f2012-04-26 16:03:01 -07002234 if (waitqueue_active(&ring->irq_queue)) {
2235 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2236 ring->name);
Chris Wilson893eead2010-10-27 14:44:35 +01002237 wake_up_all(&ring->irq_queue);
2238 *err = true;
2239 }
2240 return true;
2241 }
2242 return false;
Ben Gamarif65d9422009-09-14 17:48:44 -04002243}
2244
Chris Wilsona24a11e2013-03-14 17:52:05 +02002245static bool semaphore_passed(struct intel_ring_buffer *ring)
2246{
2247 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2248 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2249 struct intel_ring_buffer *signaller;
2250 u32 cmd, ipehr, acthd_min;
2251
2252 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2253 if ((ipehr & ~(0x3 << 16)) !=
2254 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2255 return false;
2256
2257 /* ACTHD is likely pointing to the dword after the actual command,
2258 * so scan backwards until we find the MBOX.
2259 */
2260 acthd_min = max((int)acthd - 3 * 4, 0);
2261 do {
2262 cmd = ioread32(ring->virtual_start + acthd);
2263 if (cmd == ipehr)
2264 break;
2265
2266 acthd -= 4;
2267 if (acthd < acthd_min)
2268 return false;
2269 } while (1);
2270
2271 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2272 return i915_seqno_passed(signaller->get_seqno(signaller, false),
2273 ioread32(ring->virtual_start+acthd+4)+1);
2274}
2275
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002276static bool kick_ring(struct intel_ring_buffer *ring)
2277{
2278 struct drm_device *dev = ring->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 u32 tmp = I915_READ_CTL(ring);
2281 if (tmp & RING_WAIT) {
2282 DRM_ERROR("Kicking stuck wait on %s\n",
2283 ring->name);
2284 I915_WRITE_CTL(ring, tmp);
2285 return true;
2286 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002287
2288 if (INTEL_INFO(dev)->gen >= 6 &&
2289 tmp & RING_WAIT_SEMAPHORE &&
2290 semaphore_passed(ring)) {
2291 DRM_ERROR("Kicking stuck semaphore on %s\n",
2292 ring->name);
2293 I915_WRITE_CTL(ring, tmp);
2294 return true;
2295 }
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002296 return false;
2297}
2298
Chris Wilsond1e61e72012-04-10 17:00:41 +01002299static bool i915_hangcheck_hung(struct drm_device *dev)
2300{
2301 drm_i915_private_t *dev_priv = dev->dev_private;
2302
Daniel Vetter99584db2012-11-14 17:14:04 +01002303 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
Chris Wilsonb4519512012-05-11 14:29:30 +01002304 bool hung = true;
2305
Chris Wilsond1e61e72012-04-10 17:00:41 +01002306 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2307 i915_handle_error(dev, true);
2308
2309 if (!IS_GEN2(dev)) {
Chris Wilsonb4519512012-05-11 14:29:30 +01002310 struct intel_ring_buffer *ring;
2311 int i;
2312
Chris Wilsond1e61e72012-04-10 17:00:41 +01002313 /* Is the chip hanging on a WAIT_FOR_EVENT?
2314 * If so we can simply poke the RB_WAIT bit
2315 * and break the hang. This should work on
2316 * all but the second generation chipsets.
2317 */
Chris Wilsonb4519512012-05-11 14:29:30 +01002318 for_each_ring(ring, dev_priv, i)
2319 hung &= !kick_ring(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01002320 }
2321
Chris Wilsonb4519512012-05-11 14:29:30 +01002322 return hung;
Chris Wilsond1e61e72012-04-10 17:00:41 +01002323 }
2324
2325 return false;
2326}
2327
Ben Gamarif65d9422009-09-14 17:48:44 -04002328/**
2329 * This is called when the chip hasn't reported back with completed
2330 * batchbuffers in a long time. The first time this is called we simply record
2331 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2332 * again, we assume the chip is wedged and try to fix it.
2333 */
2334void i915_hangcheck_elapsed(unsigned long data)
2335{
2336 struct drm_device *dev = (struct drm_device *)data;
2337 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07002338 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
Chris Wilsonb4519512012-05-11 14:29:30 +01002339 struct intel_ring_buffer *ring;
2340 bool err = false, idle;
2341 int i;
Chris Wilson893eead2010-10-27 14:44:35 +01002342
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07002343 if (!i915_enable_hangcheck)
2344 return;
2345
Chris Wilsonb4519512012-05-11 14:29:30 +01002346 memset(acthd, 0, sizeof(acthd));
2347 idle = true;
2348 for_each_ring(ring, dev_priv, i) {
2349 idle &= i915_hangcheck_ring_idle(ring, &err);
2350 acthd[i] = intel_ring_get_active_head(ring);
2351 }
2352
Chris Wilson893eead2010-10-27 14:44:35 +01002353 /* If all work is done then ACTHD clearly hasn't advanced. */
Chris Wilsonb4519512012-05-11 14:29:30 +01002354 if (idle) {
Chris Wilsond1e61e72012-04-10 17:00:41 +01002355 if (err) {
2356 if (i915_hangcheck_hung(dev))
2357 return;
2358
Chris Wilson893eead2010-10-27 14:44:35 +01002359 goto repeat;
Chris Wilsond1e61e72012-04-10 17:00:41 +01002360 }
2361
Daniel Vetter99584db2012-11-14 17:14:04 +01002362 dev_priv->gpu_error.hangcheck_count = 0;
Chris Wilson893eead2010-10-27 14:44:35 +01002363 return;
2364 }
Eric Anholtb9201c12010-01-08 14:25:16 -08002365
Ben Widawskybd9854f2012-08-23 15:18:09 -07002366 i915_get_extra_instdone(dev, instdone);
Daniel Vetter99584db2012-11-14 17:14:04 +01002367 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
2368 sizeof(acthd)) == 0 &&
2369 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
2370 sizeof(instdone)) == 0) {
Chris Wilsond1e61e72012-04-10 17:00:41 +01002371 if (i915_hangcheck_hung(dev))
Chris Wilsoncbb465e2010-06-06 12:16:24 +01002372 return;
Chris Wilsoncbb465e2010-06-06 12:16:24 +01002373 } else {
Daniel Vetter99584db2012-11-14 17:14:04 +01002374 dev_priv->gpu_error.hangcheck_count = 0;
Chris Wilsoncbb465e2010-06-06 12:16:24 +01002375
Daniel Vetter99584db2012-11-14 17:14:04 +01002376 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2377 sizeof(acthd));
2378 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2379 sizeof(instdone));
Chris Wilsoncbb465e2010-06-06 12:16:24 +01002380 }
Ben Gamarif65d9422009-09-14 17:48:44 -04002381
Chris Wilson893eead2010-10-27 14:44:35 +01002382repeat:
Ben Gamarif65d9422009-09-14 17:48:44 -04002383 /* Reset timer case chip hangs without another request being added */
Daniel Vetter99584db2012-11-14 17:14:04 +01002384 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
Chris Wilsoncecc21f2012-10-05 17:02:56 +01002385 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04002386}
2387
Linus Torvalds1da177e2005-04-16 15:20:36 -07002388/* drm_dma.h hooks
2389*/
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002390static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002391{
2392 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2393
Jesse Barnes46979952011-04-07 13:53:55 -07002394 atomic_set(&dev_priv->irq_received, 0);
2395
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002396 I915_WRITE(HWSTAM, 0xeffe);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01002397
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002398 /* XXX hotplug from PCH */
2399
2400 I915_WRITE(DEIMR, 0xffffffff);
2401 I915_WRITE(DEIER, 0x0);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002402 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002403
2404 /* and GT */
2405 I915_WRITE(GTIMR, 0xffffffff);
2406 I915_WRITE(GTIER, 0x0);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002407 POSTING_READ(GTIER);
Zhenyu Wangc6501562009-11-03 18:57:21 +00002408
Ben Widawskyab5c6082013-04-05 13:12:41 -07002409 if (HAS_PCH_NOP(dev))
2410 return;
2411
Zhenyu Wangc6501562009-11-03 18:57:21 +00002412 /* south display irq */
2413 I915_WRITE(SDEIMR, 0xffffffff);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002414 /*
2415 * SDEIER is also touched by the interrupt handler to work around missed
2416 * PCH interrupts. Hence we can't update it after the interrupt handler
2417 * is enabled - instead we unconditionally enable all PCH interrupt
2418 * sources here, but then only unmask them as needed with SDEIMR.
2419 */
2420 I915_WRITE(SDEIER, 0xffffffff);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002421 POSTING_READ(SDEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002422}
2423
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002424static void valleyview_irq_preinstall(struct drm_device *dev)
2425{
2426 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2427 int pipe;
2428
2429 atomic_set(&dev_priv->irq_received, 0);
2430
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002431 /* VLV magic */
2432 I915_WRITE(VLV_IMR, 0);
2433 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2434 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2435 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2436
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002437 /* and GT */
2438 I915_WRITE(GTIIR, I915_READ(GTIIR));
2439 I915_WRITE(GTIIR, I915_READ(GTIIR));
2440 I915_WRITE(GTIMR, 0xffffffff);
2441 I915_WRITE(GTIER, 0x0);
2442 POSTING_READ(GTIER);
2443
2444 I915_WRITE(DPINVGTT, 0xff);
2445
2446 I915_WRITE(PORT_HOTPLUG_EN, 0);
2447 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2448 for_each_pipe(pipe)
2449 I915_WRITE(PIPESTAT(pipe), 0xffff);
2450 I915_WRITE(VLV_IIR, 0xffffffff);
2451 I915_WRITE(VLV_IMR, 0xffffffff);
2452 I915_WRITE(VLV_IER, 0x0);
2453 POSTING_READ(VLV_IER);
2454}
2455
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002456static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07002457{
2458 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002459 struct drm_mode_config *mode_config = &dev->mode_config;
2460 struct intel_encoder *intel_encoder;
2461 u32 mask = ~I915_READ(SDEIMR);
2462 u32 hotplug;
Keith Packard7fe0b972011-09-19 13:31:02 -07002463
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002464 if (HAS_PCH_IBX(dev)) {
Egbert Eich995e6b32013-04-16 13:36:56 +02002465 mask &= ~SDE_HOTPLUG_MASK;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002466 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
Egbert Eichcd569ae2013-04-16 13:36:57 +02002467 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2468 mask |= hpd_ibx[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002469 } else {
Egbert Eich995e6b32013-04-16 13:36:56 +02002470 mask &= ~SDE_HOTPLUG_MASK_CPT;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002471 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
Egbert Eichcd569ae2013-04-16 13:36:57 +02002472 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2473 mask |= hpd_cpt[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002474 }
2475
2476 I915_WRITE(SDEIMR, ~mask);
2477
2478 /*
2479 * Enable digital hotplug on the PCH, and configure the DP short pulse
2480 * duration to 2ms (which is the minimum in the Display Port spec)
2481 *
2482 * This register is the same on all known PCH chips.
2483 */
Keith Packard7fe0b972011-09-19 13:31:02 -07002484 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2485 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2486 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2487 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2488 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2489 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2490}
2491
Paulo Zanonid46da432013-02-08 17:35:15 -02002492static void ibx_irq_postinstall(struct drm_device *dev)
2493{
2494 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002495 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02002496
Paulo Zanoni86642812013-04-12 17:57:57 -03002497 if (HAS_PCH_IBX(dev)) {
2498 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2499 SDE_TRANSA_FIFO_UNDER;
2500 } else {
2501 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2502
2503 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2504 }
Ben Widawskyab5c6082013-04-05 13:12:41 -07002505
2506 if (HAS_PCH_NOP(dev))
2507 return;
2508
Paulo Zanonid46da432013-02-08 17:35:15 -02002509 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2510 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02002511}
2512
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002513static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002514{
2515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2516 /* enable kind of interrupts always enabled */
Jesse Barnes013d5aa2010-01-29 11:18:31 -08002517 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
Daniel Vetterce99c252012-12-01 13:53:47 +01002518 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Paulo Zanoni86642812013-04-12 17:57:57 -03002519 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2520 DE_PIPEA_FIFO_UNDERRUN;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002521 u32 render_irqs;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002522
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002523 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002524
2525 /* should always can generate irq */
2526 I915_WRITE(DEIIR, I915_READ(DEIIR));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002527 I915_WRITE(DEIMR, dev_priv->irq_mask);
2528 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002529 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002530
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002531 dev_priv->gt_irq_mask = ~0;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002532
2533 I915_WRITE(GTIIR, I915_READ(GTIIR));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002534 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
Xiang, Haihao881f47b2010-09-19 14:40:43 +01002535
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002536 if (IS_GEN6(dev))
2537 render_irqs =
2538 GT_USER_INTERRUPT |
Ben Widawskye2a1e2f2012-03-29 19:11:26 -07002539 GEN6_BSD_USER_INTERRUPT |
2540 GEN6_BLITTER_USER_INTERRUPT;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002541 else
2542 render_irqs =
Chris Wilson88f23b82010-12-05 15:08:31 +00002543 GT_USER_INTERRUPT |
Chris Wilsonc6df5412010-12-15 09:56:50 +00002544 GT_PIPE_NOTIFY |
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002545 GT_BSD_USER_INTERRUPT;
2546 I915_WRITE(GTIER, render_irqs);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002547 POSTING_READ(GTIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002548
Paulo Zanonid46da432013-02-08 17:35:15 -02002549 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07002550
Jesse Barnesf97108d2010-01-29 11:27:07 -08002551 if (IS_IRONLAKE_M(dev)) {
2552 /* Clear & enable PCU event interrupts */
2553 I915_WRITE(DEIIR, DE_PCU_EVENT);
2554 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2555 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2556 }
2557
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002558 return 0;
2559}
2560
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002561static int ivybridge_irq_postinstall(struct drm_device *dev)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002562{
2563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2564 /* enable kind of interrupts always enabled */
Chris Wilsonb615b572012-05-02 09:52:12 +01002565 u32 display_mask =
2566 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2567 DE_PLANEC_FLIP_DONE_IVB |
2568 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetterce99c252012-12-01 13:53:47 +01002569 DE_PLANEA_FLIP_DONE_IVB |
Paulo Zanoni86642812013-04-12 17:57:57 -03002570 DE_AUX_CHANNEL_A_IVB |
2571 DE_ERR_INT_IVB;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002572 u32 render_irqs;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002573
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002574 dev_priv->irq_mask = ~display_mask;
2575
2576 /* should always can generate irq */
Paulo Zanoni86642812013-04-12 17:57:57 -03002577 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002578 I915_WRITE(DEIIR, I915_READ(DEIIR));
2579 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilsonb615b572012-05-02 09:52:12 +01002580 I915_WRITE(DEIER,
2581 display_mask |
2582 DE_PIPEC_VBLANK_IVB |
2583 DE_PIPEB_VBLANK_IVB |
2584 DE_PIPEA_VBLANK_IVB);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002585 POSTING_READ(DEIER);
2586
Ben Widawsky15b9f802012-05-25 16:56:23 -07002587 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002588
2589 I915_WRITE(GTIIR, I915_READ(GTIIR));
2590 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2591
Ben Widawskye2a1e2f2012-03-29 19:11:26 -07002592 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
Ben Widawsky15b9f802012-05-25 16:56:23 -07002593 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002594 I915_WRITE(GTIER, render_irqs);
2595 POSTING_READ(GTIER);
2596
Paulo Zanonid46da432013-02-08 17:35:15 -02002597 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07002598
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002599 return 0;
2600}
2601
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002602static int valleyview_irq_postinstall(struct drm_device *dev)
2603{
2604 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002605 u32 enable_mask;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002606 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
Jesse Barnes3bcedbe2012-09-19 13:29:01 -07002607 u32 render_irqs;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002608 u16 msid;
2609
2610 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002611 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2612 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2613 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002614 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2615
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002616 /*
2617 *Leave vblank interrupts masked initially. enable/disable will
2618 * toggle them based on usage.
2619 */
2620 dev_priv->irq_mask = (~enable_mask) |
2621 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2622 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002623
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002624 /* Hack for broken MSIs on VLV */
2625 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2626 pci_read_config_word(dev->pdev, 0x98, &msid);
2627 msid &= 0xff; /* mask out delivery bits */
2628 msid |= (1<<14);
2629 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2630
Daniel Vetter20afbda2012-12-11 14:05:07 +01002631 I915_WRITE(PORT_HOTPLUG_EN, 0);
2632 POSTING_READ(PORT_HOTPLUG_EN);
2633
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002634 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2635 I915_WRITE(VLV_IER, enable_mask);
2636 I915_WRITE(VLV_IIR, 0xffffffff);
2637 I915_WRITE(PIPESTAT(0), 0xffff);
2638 I915_WRITE(PIPESTAT(1), 0xffff);
2639 POSTING_READ(VLV_IER);
2640
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002641 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002642 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002643 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2644
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002645 I915_WRITE(VLV_IIR, 0xffffffff);
2646 I915_WRITE(VLV_IIR, 0xffffffff);
2647
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002648 I915_WRITE(GTIIR, I915_READ(GTIIR));
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002649 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
Jesse Barnes3bcedbe2012-09-19 13:29:01 -07002650
2651 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2652 GEN6_BLITTER_USER_INTERRUPT;
2653 I915_WRITE(GTIER, render_irqs);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002654 POSTING_READ(GTIER);
2655
2656 /* ack & enable invalid PTE error interrupts */
2657#if 0 /* FIXME: add support to irq handler for checking these bits */
2658 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2659 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2660#endif
2661
2662 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01002663
2664 return 0;
2665}
2666
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002667static void valleyview_irq_uninstall(struct drm_device *dev)
2668{
2669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2670 int pipe;
2671
2672 if (!dev_priv)
2673 return;
2674
Egbert Eichac4c16c2013-04-16 13:36:58 +02002675 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2676
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002677 for_each_pipe(pipe)
2678 I915_WRITE(PIPESTAT(pipe), 0xffff);
2679
2680 I915_WRITE(HWSTAM, 0xffffffff);
2681 I915_WRITE(PORT_HOTPLUG_EN, 0);
2682 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2683 for_each_pipe(pipe)
2684 I915_WRITE(PIPESTAT(pipe), 0xffff);
2685 I915_WRITE(VLV_IIR, 0xffffffff);
2686 I915_WRITE(VLV_IMR, 0xffffffff);
2687 I915_WRITE(VLV_IER, 0x0);
2688 POSTING_READ(VLV_IER);
2689}
2690
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002691static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002692{
2693 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07002694
2695 if (!dev_priv)
2696 return;
2697
Egbert Eichac4c16c2013-04-16 13:36:58 +02002698 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2699
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002700 I915_WRITE(HWSTAM, 0xffffffff);
2701
2702 I915_WRITE(DEIMR, 0xffffffff);
2703 I915_WRITE(DEIER, 0x0);
2704 I915_WRITE(DEIIR, I915_READ(DEIIR));
Paulo Zanoni86642812013-04-12 17:57:57 -03002705 if (IS_GEN7(dev))
2706 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002707
2708 I915_WRITE(GTIMR, 0xffffffff);
2709 I915_WRITE(GTIER, 0x0);
2710 I915_WRITE(GTIIR, I915_READ(GTIIR));
Keith Packard192aac1f2011-09-20 10:12:44 -07002711
Ben Widawskyab5c6082013-04-05 13:12:41 -07002712 if (HAS_PCH_NOP(dev))
2713 return;
2714
Keith Packard192aac1f2011-09-20 10:12:44 -07002715 I915_WRITE(SDEIMR, 0xffffffff);
2716 I915_WRITE(SDEIER, 0x0);
2717 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
Paulo Zanoni86642812013-04-12 17:57:57 -03002718 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2719 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002720}
2721
Chris Wilsonc2798b12012-04-22 21:13:57 +01002722static void i8xx_irq_preinstall(struct drm_device * dev)
2723{
2724 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2725 int pipe;
2726
2727 atomic_set(&dev_priv->irq_received, 0);
2728
2729 for_each_pipe(pipe)
2730 I915_WRITE(PIPESTAT(pipe), 0);
2731 I915_WRITE16(IMR, 0xffff);
2732 I915_WRITE16(IER, 0x0);
2733 POSTING_READ16(IER);
2734}
2735
2736static int i8xx_irq_postinstall(struct drm_device *dev)
2737{
2738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2739
Chris Wilsonc2798b12012-04-22 21:13:57 +01002740 I915_WRITE16(EMR,
2741 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2742
2743 /* Unmask the interrupts that we always want on. */
2744 dev_priv->irq_mask =
2745 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2746 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2747 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2748 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2749 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2750 I915_WRITE16(IMR, dev_priv->irq_mask);
2751
2752 I915_WRITE16(IER,
2753 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2754 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2755 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2756 I915_USER_INTERRUPT);
2757 POSTING_READ16(IER);
2758
2759 return 0;
2760}
2761
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002762/*
2763 * Returns true when a page flip has completed.
2764 */
2765static bool i8xx_handle_vblank(struct drm_device *dev,
2766 int pipe, u16 iir)
2767{
2768 drm_i915_private_t *dev_priv = dev->dev_private;
2769 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2770
2771 if (!drm_handle_vblank(dev, pipe))
2772 return false;
2773
2774 if ((iir & flip_pending) == 0)
2775 return false;
2776
2777 intel_prepare_page_flip(dev, pipe);
2778
2779 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2780 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2781 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2782 * the flip is completed (no longer pending). Since this doesn't raise
2783 * an interrupt per se, we watch for the change at vblank.
2784 */
2785 if (I915_READ16(ISR) & flip_pending)
2786 return false;
2787
2788 intel_finish_page_flip(dev, pipe);
2789
2790 return true;
2791}
2792
Daniel Vetterff1f5252012-10-02 15:10:55 +02002793static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01002794{
2795 struct drm_device *dev = (struct drm_device *) arg;
2796 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002797 u16 iir, new_iir;
2798 u32 pipe_stats[2];
2799 unsigned long irqflags;
2800 int irq_received;
2801 int pipe;
2802 u16 flip_mask =
2803 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2804 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2805
2806 atomic_inc(&dev_priv->irq_received);
2807
2808 iir = I915_READ16(IIR);
2809 if (iir == 0)
2810 return IRQ_NONE;
2811
2812 while (iir & ~flip_mask) {
2813 /* Can't rely on pipestat interrupt bit in iir as it might
2814 * have been cleared after the pipestat interrupt was received.
2815 * It doesn't set the bit in iir again, but it still produces
2816 * interrupts (for non-MSI).
2817 */
2818 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2819 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2820 i915_handle_error(dev, false);
2821
2822 for_each_pipe(pipe) {
2823 int reg = PIPESTAT(pipe);
2824 pipe_stats[pipe] = I915_READ(reg);
2825
2826 /*
2827 * Clear the PIPE*STAT regs before the IIR
2828 */
2829 if (pipe_stats[pipe] & 0x8000ffff) {
2830 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2831 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2832 pipe_name(pipe));
2833 I915_WRITE(reg, pipe_stats[pipe]);
2834 irq_received = 1;
2835 }
2836 }
2837 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2838
2839 I915_WRITE16(IIR, iir & ~flip_mask);
2840 new_iir = I915_READ16(IIR); /* Flush posted writes */
2841
Daniel Vetterd05c6172012-04-26 23:28:09 +02002842 i915_update_dri1_breadcrumb(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002843
2844 if (iir & I915_USER_INTERRUPT)
2845 notify_ring(dev, &dev_priv->ring[RCS]);
2846
2847 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002848 i8xx_handle_vblank(dev, 0, iir))
2849 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002850
2851 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002852 i8xx_handle_vblank(dev, 1, iir))
2853 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002854
2855 iir = new_iir;
2856 }
2857
2858 return IRQ_HANDLED;
2859}
2860
2861static void i8xx_irq_uninstall(struct drm_device * dev)
2862{
2863 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2864 int pipe;
2865
Chris Wilsonc2798b12012-04-22 21:13:57 +01002866 for_each_pipe(pipe) {
2867 /* Clear enable bits; then clear status bits */
2868 I915_WRITE(PIPESTAT(pipe), 0);
2869 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2870 }
2871 I915_WRITE16(IMR, 0xffff);
2872 I915_WRITE16(IER, 0x0);
2873 I915_WRITE16(IIR, I915_READ16(IIR));
2874}
2875
Chris Wilsona266c7d2012-04-24 22:59:44 +01002876static void i915_irq_preinstall(struct drm_device * dev)
2877{
2878 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2879 int pipe;
2880
2881 atomic_set(&dev_priv->irq_received, 0);
2882
2883 if (I915_HAS_HOTPLUG(dev)) {
2884 I915_WRITE(PORT_HOTPLUG_EN, 0);
2885 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2886 }
2887
Chris Wilson00d98eb2012-04-24 22:59:48 +01002888 I915_WRITE16(HWSTAM, 0xeffe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002889 for_each_pipe(pipe)
2890 I915_WRITE(PIPESTAT(pipe), 0);
2891 I915_WRITE(IMR, 0xffffffff);
2892 I915_WRITE(IER, 0x0);
2893 POSTING_READ(IER);
2894}
2895
2896static int i915_irq_postinstall(struct drm_device *dev)
2897{
2898 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01002899 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002900
Chris Wilson38bde182012-04-24 22:59:50 +01002901 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2902
2903 /* Unmask the interrupts that we always want on. */
2904 dev_priv->irq_mask =
2905 ~(I915_ASLE_INTERRUPT |
2906 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2907 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2908 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2909 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2910 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2911
2912 enable_mask =
2913 I915_ASLE_INTERRUPT |
2914 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2915 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2916 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2917 I915_USER_INTERRUPT;
2918
Chris Wilsona266c7d2012-04-24 22:59:44 +01002919 if (I915_HAS_HOTPLUG(dev)) {
Daniel Vetter20afbda2012-12-11 14:05:07 +01002920 I915_WRITE(PORT_HOTPLUG_EN, 0);
2921 POSTING_READ(PORT_HOTPLUG_EN);
2922
Chris Wilsona266c7d2012-04-24 22:59:44 +01002923 /* Enable in IER... */
2924 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2925 /* and unmask in IMR */
2926 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2927 }
2928
Chris Wilsona266c7d2012-04-24 22:59:44 +01002929 I915_WRITE(IMR, dev_priv->irq_mask);
2930 I915_WRITE(IER, enable_mask);
2931 POSTING_READ(IER);
2932
Daniel Vetter20afbda2012-12-11 14:05:07 +01002933 intel_opregion_enable_asle(dev);
2934
2935 return 0;
2936}
2937
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002938/*
2939 * Returns true when a page flip has completed.
2940 */
2941static bool i915_handle_vblank(struct drm_device *dev,
2942 int plane, int pipe, u32 iir)
2943{
2944 drm_i915_private_t *dev_priv = dev->dev_private;
2945 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2946
2947 if (!drm_handle_vblank(dev, pipe))
2948 return false;
2949
2950 if ((iir & flip_pending) == 0)
2951 return false;
2952
2953 intel_prepare_page_flip(dev, plane);
2954
2955 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2956 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2957 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2958 * the flip is completed (no longer pending). Since this doesn't raise
2959 * an interrupt per se, we watch for the change at vblank.
2960 */
2961 if (I915_READ(ISR) & flip_pending)
2962 return false;
2963
2964 intel_finish_page_flip(dev, pipe);
2965
2966 return true;
2967}
2968
Daniel Vetterff1f5252012-10-02 15:10:55 +02002969static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01002970{
2971 struct drm_device *dev = (struct drm_device *) arg;
2972 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01002973 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01002974 unsigned long irqflags;
Chris Wilson38bde182012-04-24 22:59:50 +01002975 u32 flip_mask =
2976 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2977 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01002978 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002979
2980 atomic_inc(&dev_priv->irq_received);
2981
2982 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01002983 do {
2984 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01002985 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002986
2987 /* Can't rely on pipestat interrupt bit in iir as it might
2988 * have been cleared after the pipestat interrupt was received.
2989 * It doesn't set the bit in iir again, but it still produces
2990 * interrupts (for non-MSI).
2991 */
2992 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2993 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2994 i915_handle_error(dev, false);
2995
2996 for_each_pipe(pipe) {
2997 int reg = PIPESTAT(pipe);
2998 pipe_stats[pipe] = I915_READ(reg);
2999
Chris Wilson38bde182012-04-24 22:59:50 +01003000 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003001 if (pipe_stats[pipe] & 0x8000ffff) {
3002 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3003 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3004 pipe_name(pipe));
3005 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01003006 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003007 }
3008 }
3009 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3010
3011 if (!irq_received)
3012 break;
3013
Chris Wilsona266c7d2012-04-24 22:59:44 +01003014 /* Consume port. Then clear IIR or we'll miss events */
3015 if ((I915_HAS_HOTPLUG(dev)) &&
3016 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3017 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +02003018 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003019
3020 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3021 hotplug_status);
Egbert Eichb543fb02013-04-16 13:36:54 +02003022 if (hotplug_trigger) {
Egbert Eichcd569ae2013-04-16 13:36:57 +02003023 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3024 i915_hpd_irq_setup(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003025 queue_work(dev_priv->wq,
3026 &dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02003027 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003028 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
Chris Wilson38bde182012-04-24 22:59:50 +01003029 POSTING_READ(PORT_HOTPLUG_STAT);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003030 }
3031
Chris Wilson38bde182012-04-24 22:59:50 +01003032 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003033 new_iir = I915_READ(IIR); /* Flush posted writes */
3034
Chris Wilsona266c7d2012-04-24 22:59:44 +01003035 if (iir & I915_USER_INTERRUPT)
3036 notify_ring(dev, &dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003037
Chris Wilsona266c7d2012-04-24 22:59:44 +01003038 for_each_pipe(pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01003039 int plane = pipe;
3040 if (IS_MOBILE(dev))
3041 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02003042
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003043 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3044 i915_handle_vblank(dev, plane, pipe, iir))
3045 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003046
3047 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3048 blc_event = true;
3049 }
3050
Chris Wilsona266c7d2012-04-24 22:59:44 +01003051 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3052 intel_opregion_asle_intr(dev);
3053
3054 /* With MSI, interrupts are only generated when iir
3055 * transitions from zero to nonzero. If another bit got
3056 * set while we were handling the existing iir bits, then
3057 * we would never get another interrupt.
3058 *
3059 * This is fine on non-MSI as well, as if we hit this path
3060 * we avoid exiting the interrupt handler only to generate
3061 * another one.
3062 *
3063 * Note that for MSI this could cause a stray interrupt report
3064 * if an interrupt landed in the time between writing IIR and
3065 * the posting read. This should be rare enough to never
3066 * trigger the 99% of 100,000 interrupts test for disabling
3067 * stray interrupts.
3068 */
Chris Wilson38bde182012-04-24 22:59:50 +01003069 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003070 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01003071 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003072
Daniel Vetterd05c6172012-04-26 23:28:09 +02003073 i915_update_dri1_breadcrumb(dev);
Chris Wilson8291ee92012-04-24 22:59:47 +01003074
Chris Wilsona266c7d2012-04-24 22:59:44 +01003075 return ret;
3076}
3077
3078static void i915_irq_uninstall(struct drm_device * dev)
3079{
3080 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3081 int pipe;
3082
Egbert Eichac4c16c2013-04-16 13:36:58 +02003083 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3084
Chris Wilsona266c7d2012-04-24 22:59:44 +01003085 if (I915_HAS_HOTPLUG(dev)) {
3086 I915_WRITE(PORT_HOTPLUG_EN, 0);
3087 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3088 }
3089
Chris Wilson00d98eb2012-04-24 22:59:48 +01003090 I915_WRITE16(HWSTAM, 0xffff);
Chris Wilson55b39752012-04-24 22:59:49 +01003091 for_each_pipe(pipe) {
3092 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003093 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01003094 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3095 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003096 I915_WRITE(IMR, 0xffffffff);
3097 I915_WRITE(IER, 0x0);
3098
Chris Wilsona266c7d2012-04-24 22:59:44 +01003099 I915_WRITE(IIR, I915_READ(IIR));
3100}
3101
3102static void i965_irq_preinstall(struct drm_device * dev)
3103{
3104 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3105 int pipe;
3106
3107 atomic_set(&dev_priv->irq_received, 0);
3108
Chris Wilsonadca4732012-05-11 18:01:31 +01003109 I915_WRITE(PORT_HOTPLUG_EN, 0);
3110 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01003111
3112 I915_WRITE(HWSTAM, 0xeffe);
3113 for_each_pipe(pipe)
3114 I915_WRITE(PIPESTAT(pipe), 0);
3115 I915_WRITE(IMR, 0xffffffff);
3116 I915_WRITE(IER, 0x0);
3117 POSTING_READ(IER);
3118}
3119
3120static int i965_irq_postinstall(struct drm_device *dev)
3121{
3122 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003123 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003124 u32 error_mask;
3125
Chris Wilsona266c7d2012-04-24 22:59:44 +01003126 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003127 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01003128 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003129 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3130 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3131 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3132 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3133 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3134
3135 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003136 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3137 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003138 enable_mask |= I915_USER_INTERRUPT;
3139
3140 if (IS_G4X(dev))
3141 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003142
Daniel Vetter515ac2b2012-12-01 13:53:44 +01003143 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003144
Chris Wilsona266c7d2012-04-24 22:59:44 +01003145 /*
3146 * Enable some error detection, note the instruction error mask
3147 * bit is reserved, so we leave it masked.
3148 */
3149 if (IS_G4X(dev)) {
3150 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3151 GM45_ERROR_MEM_PRIV |
3152 GM45_ERROR_CP_PRIV |
3153 I915_ERROR_MEMORY_REFRESH);
3154 } else {
3155 error_mask = ~(I915_ERROR_PAGE_TABLE |
3156 I915_ERROR_MEMORY_REFRESH);
3157 }
3158 I915_WRITE(EMR, error_mask);
3159
3160 I915_WRITE(IMR, dev_priv->irq_mask);
3161 I915_WRITE(IER, enable_mask);
3162 POSTING_READ(IER);
3163
Daniel Vetter20afbda2012-12-11 14:05:07 +01003164 I915_WRITE(PORT_HOTPLUG_EN, 0);
3165 POSTING_READ(PORT_HOTPLUG_EN);
3166
3167 intel_opregion_enable_asle(dev);
3168
3169 return 0;
3170}
3171
Egbert Eichbac56d52013-02-25 12:06:51 -05003172static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01003173{
3174 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Egbert Eiche5868a32013-02-28 04:17:12 -05003175 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +02003176 struct intel_encoder *intel_encoder;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003177 u32 hotplug_en;
3178
Egbert Eichbac56d52013-02-25 12:06:51 -05003179 if (I915_HAS_HOTPLUG(dev)) {
3180 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3181 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3182 /* Note HDMI and DP share hotplug bits */
Egbert Eiche5868a32013-02-28 04:17:12 -05003183 /* enable bits are the same for all generations */
Egbert Eichcd569ae2013-04-16 13:36:57 +02003184 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3185 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3186 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
Egbert Eichbac56d52013-02-25 12:06:51 -05003187 /* Programming the CRT detection parameters tends
3188 to generate a spurious hotplug event about three
3189 seconds later. So just do it once.
3190 */
3191 if (IS_G4X(dev))
3192 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Daniel Vetter85fc95b2013-03-27 15:47:11 +01003193 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
Egbert Eichbac56d52013-02-25 12:06:51 -05003194 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003195
Egbert Eichbac56d52013-02-25 12:06:51 -05003196 /* Ignore TV since it's buggy */
3197 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3198 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003199}
3200
Daniel Vetterff1f5252012-10-02 15:10:55 +02003201static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003202{
3203 struct drm_device *dev = (struct drm_device *) arg;
3204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003205 u32 iir, new_iir;
3206 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01003207 unsigned long irqflags;
3208 int irq_received;
3209 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003210 u32 flip_mask =
3211 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3212 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003213
3214 atomic_inc(&dev_priv->irq_received);
3215
3216 iir = I915_READ(IIR);
3217
Chris Wilsona266c7d2012-04-24 22:59:44 +01003218 for (;;) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01003219 bool blc_event = false;
3220
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003221 irq_received = (iir & ~flip_mask) != 0;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003222
3223 /* Can't rely on pipestat interrupt bit in iir as it might
3224 * have been cleared after the pipestat interrupt was received.
3225 * It doesn't set the bit in iir again, but it still produces
3226 * interrupts (for non-MSI).
3227 */
3228 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3229 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3230 i915_handle_error(dev, false);
3231
3232 for_each_pipe(pipe) {
3233 int reg = PIPESTAT(pipe);
3234 pipe_stats[pipe] = I915_READ(reg);
3235
3236 /*
3237 * Clear the PIPE*STAT regs before the IIR
3238 */
3239 if (pipe_stats[pipe] & 0x8000ffff) {
3240 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3241 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3242 pipe_name(pipe));
3243 I915_WRITE(reg, pipe_stats[pipe]);
3244 irq_received = 1;
3245 }
3246 }
3247 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3248
3249 if (!irq_received)
3250 break;
3251
3252 ret = IRQ_HANDLED;
3253
3254 /* Consume port. Then clear IIR or we'll miss events */
Chris Wilsonadca4732012-05-11 18:01:31 +01003255 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003256 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +02003257 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3258 HOTPLUG_INT_STATUS_G4X :
3259 HOTPLUG_INT_STATUS_I965);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003260
3261 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3262 hotplug_status);
Egbert Eichb543fb02013-04-16 13:36:54 +02003263 if (hotplug_trigger) {
Egbert Eichcd569ae2013-04-16 13:36:57 +02003264 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3265 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3266 i915_hpd_irq_setup(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003267 queue_work(dev_priv->wq,
3268 &dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02003269 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003270 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3271 I915_READ(PORT_HOTPLUG_STAT);
3272 }
3273
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003274 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003275 new_iir = I915_READ(IIR); /* Flush posted writes */
3276
Chris Wilsona266c7d2012-04-24 22:59:44 +01003277 if (iir & I915_USER_INTERRUPT)
3278 notify_ring(dev, &dev_priv->ring[RCS]);
3279 if (iir & I915_BSD_USER_INTERRUPT)
3280 notify_ring(dev, &dev_priv->ring[VCS]);
3281
Chris Wilsona266c7d2012-04-24 22:59:44 +01003282 for_each_pipe(pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01003283 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003284 i915_handle_vblank(dev, pipe, pipe, iir))
3285 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003286
3287 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3288 blc_event = true;
3289 }
3290
3291
3292 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3293 intel_opregion_asle_intr(dev);
3294
Daniel Vetter515ac2b2012-12-01 13:53:44 +01003295 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3296 gmbus_irq_handler(dev);
3297
Chris Wilsona266c7d2012-04-24 22:59:44 +01003298 /* With MSI, interrupts are only generated when iir
3299 * transitions from zero to nonzero. If another bit got
3300 * set while we were handling the existing iir bits, then
3301 * we would never get another interrupt.
3302 *
3303 * This is fine on non-MSI as well, as if we hit this path
3304 * we avoid exiting the interrupt handler only to generate
3305 * another one.
3306 *
3307 * Note that for MSI this could cause a stray interrupt report
3308 * if an interrupt landed in the time between writing IIR and
3309 * the posting read. This should be rare enough to never
3310 * trigger the 99% of 100,000 interrupts test for disabling
3311 * stray interrupts.
3312 */
3313 iir = new_iir;
3314 }
3315
Daniel Vetterd05c6172012-04-26 23:28:09 +02003316 i915_update_dri1_breadcrumb(dev);
Chris Wilson2c8ba292012-04-24 22:59:46 +01003317
Chris Wilsona266c7d2012-04-24 22:59:44 +01003318 return ret;
3319}
3320
3321static void i965_irq_uninstall(struct drm_device * dev)
3322{
3323 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3324 int pipe;
3325
3326 if (!dev_priv)
3327 return;
3328
Egbert Eichac4c16c2013-04-16 13:36:58 +02003329 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3330
Chris Wilsonadca4732012-05-11 18:01:31 +01003331 I915_WRITE(PORT_HOTPLUG_EN, 0);
3332 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01003333
3334 I915_WRITE(HWSTAM, 0xffffffff);
3335 for_each_pipe(pipe)
3336 I915_WRITE(PIPESTAT(pipe), 0);
3337 I915_WRITE(IMR, 0xffffffff);
3338 I915_WRITE(IER, 0x0);
3339
3340 for_each_pipe(pipe)
3341 I915_WRITE(PIPESTAT(pipe),
3342 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3343 I915_WRITE(IIR, I915_READ(IIR));
3344}
3345
Egbert Eichac4c16c2013-04-16 13:36:58 +02003346static void i915_reenable_hotplug_timer_func(unsigned long data)
3347{
3348 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3349 struct drm_device *dev = dev_priv->dev;
3350 struct drm_mode_config *mode_config = &dev->mode_config;
3351 unsigned long irqflags;
3352 int i;
3353
3354 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3355 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3356 struct drm_connector *connector;
3357
3358 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3359 continue;
3360
3361 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3362
3363 list_for_each_entry(connector, &mode_config->connector_list, head) {
3364 struct intel_connector *intel_connector = to_intel_connector(connector);
3365
3366 if (intel_connector->encoder->hpd_pin == i) {
3367 if (connector->polled != intel_connector->polled)
3368 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3369 drm_get_connector_name(connector));
3370 connector->polled = intel_connector->polled;
3371 if (!connector->polled)
3372 connector->polled = DRM_CONNECTOR_POLL_HPD;
3373 }
3374 }
3375 }
3376 if (dev_priv->display.hpd_irq_setup)
3377 dev_priv->display.hpd_irq_setup(dev);
3378 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3379}
3380
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003381void intel_irq_init(struct drm_device *dev)
3382{
Chris Wilson8b2e3262012-04-24 22:59:41 +01003383 struct drm_i915_private *dev_priv = dev->dev_private;
3384
3385 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Daniel Vetter99584db2012-11-14 17:14:04 +01003386 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02003387 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01003388 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01003389
Daniel Vetter99584db2012-11-14 17:14:04 +01003390 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3391 i915_hangcheck_elapsed,
Daniel Vetter61bac782012-12-01 21:03:21 +01003392 (unsigned long) dev);
Egbert Eichac4c16c2013-04-16 13:36:58 +02003393 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3394 (unsigned long) dev_priv);
Daniel Vetter61bac782012-12-01 21:03:21 +01003395
Tomas Janousek97a19a22012-12-08 13:48:13 +01003396 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01003397
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003398 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3399 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Eugeni Dodonov7d4e1462012-05-09 15:37:09 -03003400 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003401 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3402 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3403 }
3404
Keith Packardc3613de2011-08-12 17:05:54 -07003405 if (drm_core_check_feature(dev, DRIVER_MODESET))
3406 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3407 else
3408 dev->driver->get_vblank_timestamp = NULL;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003409 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3410
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003411 if (IS_VALLEYVIEW(dev)) {
3412 dev->driver->irq_handler = valleyview_irq_handler;
3413 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3414 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3415 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3416 dev->driver->enable_vblank = valleyview_enable_vblank;
3417 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05003418 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetter4a06e202012-12-01 13:53:40 +01003419 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003420 /* Share pre & uninstall handlers with ILK/SNB */
3421 dev->driver->irq_handler = ivybridge_irq_handler;
3422 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3423 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3424 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3425 dev->driver->enable_vblank = ivybridge_enable_vblank;
3426 dev->driver->disable_vblank = ivybridge_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003427 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003428 } else if (HAS_PCH_SPLIT(dev)) {
3429 dev->driver->irq_handler = ironlake_irq_handler;
3430 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3431 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3432 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3433 dev->driver->enable_vblank = ironlake_enable_vblank;
3434 dev->driver->disable_vblank = ironlake_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003435 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003436 } else {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003437 if (INTEL_INFO(dev)->gen == 2) {
3438 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3439 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3440 dev->driver->irq_handler = i8xx_irq_handler;
3441 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003442 } else if (INTEL_INFO(dev)->gen == 3) {
3443 dev->driver->irq_preinstall = i915_irq_preinstall;
3444 dev->driver->irq_postinstall = i915_irq_postinstall;
3445 dev->driver->irq_uninstall = i915_irq_uninstall;
3446 dev->driver->irq_handler = i915_irq_handler;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003447 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003448 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003449 dev->driver->irq_preinstall = i965_irq_preinstall;
3450 dev->driver->irq_postinstall = i965_irq_postinstall;
3451 dev->driver->irq_uninstall = i965_irq_uninstall;
3452 dev->driver->irq_handler = i965_irq_handler;
Egbert Eichbac56d52013-02-25 12:06:51 -05003453 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003454 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003455 dev->driver->enable_vblank = i915_enable_vblank;
3456 dev->driver->disable_vblank = i915_disable_vblank;
3457 }
3458}
Daniel Vetter20afbda2012-12-11 14:05:07 +01003459
3460void intel_hpd_init(struct drm_device *dev)
3461{
3462 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eich821450c2013-04-16 13:36:55 +02003463 struct drm_mode_config *mode_config = &dev->mode_config;
3464 struct drm_connector *connector;
3465 int i;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003466
Egbert Eich821450c2013-04-16 13:36:55 +02003467 for (i = 1; i < HPD_NUM_PINS; i++) {
3468 dev_priv->hpd_stats[i].hpd_cnt = 0;
3469 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3470 }
3471 list_for_each_entry(connector, &mode_config->connector_list, head) {
3472 struct intel_connector *intel_connector = to_intel_connector(connector);
3473 connector->polled = intel_connector->polled;
3474 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3475 connector->polled = DRM_CONNECTOR_POLL_HPD;
3476 }
Daniel Vetter20afbda2012-12-11 14:05:07 +01003477 if (dev_priv->display.hpd_irq_setup)
3478 dev_priv->display.hpd_irq_setup(dev);
3479}