blob: 83320695a71675273464f100fcd460e46dcd031b [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Xi Ruoyao319c1d42015-03-12 20:16:32 +080040#include <drm/drm_atomic.h>
Matt Roperc196e1d2015-01-21 16:35:48 -080041#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010042#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
Matt Roper465c1202014-05-29 08:06:54 -070044#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080046#include <linux/dma_remapping.h>
Alex Goinsfd8e0582015-11-25 18:43:38 -080047#include <linux/reservation.h>
48#include <linux/dma-buf.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080049
Matt Roper465c1202014-05-29 08:06:54 -070050/* Primary plane formats for gen <= 3 */
Damien Lespiau568db4f2015-05-12 16:13:18 +010051static const uint32_t i8xx_primary_formats[] = {
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010052 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
Matt Roper465c1202014-05-29 08:06:54 -070054 DRM_FORMAT_XRGB1555,
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010055 DRM_FORMAT_XRGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070056};
57
58/* Primary plane formats for gen >= 4 */
Damien Lespiau568db4f2015-05-12 16:13:18 +010059static const uint32_t i965_primary_formats[] = {
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010060 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070063 DRM_FORMAT_XBGR8888,
Damien Lespiau6c0fd452015-05-19 12:29:16 +010064 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66};
67
68static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
Damien Lespiau67fe7dc2015-05-15 19:06:00 +010073 DRM_FORMAT_ARGB8888,
Matt Roper465c1202014-05-29 08:06:54 -070074 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
Matt Roper465c1202014-05-29 08:06:54 -070076 DRM_FORMAT_XBGR2101010,
Kumar, Maheshea916ea2015-09-03 16:17:09 +053077 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
Matt Roper465c1202014-05-29 08:06:54 -070081};
82
Matt Roper3d7d6512014-06-10 08:28:13 -070083/* Cursor formats */
84static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86};
87
Chris Wilson6b383a72010-09-13 13:54:26 +010088static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080089
Jesse Barnesf1f644d2013-06-27 00:39:25 +030090static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020091 struct intel_crtc_state *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030092static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020093 struct intel_crtc_state *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030094
Jesse Barneseb1bfe82014-02-12 12:26:25 -080095static int intel_framebuffer_init(struct drm_device *dev,
96 struct intel_framebuffer *ifb,
97 struct drm_mode_fb_cmd2 *mode_cmd,
98 struct drm_i915_gem_object *obj);
Daniel Vetter5b18e572014-04-24 23:55:06 +020099static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
100static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
Daniel Vetter29407aa2014-04-24 23:55:08 +0200101static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -0700102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
Daniel Vetter29407aa2014-04-24 23:55:08 +0200104static void ironlake_set_pipeconf(struct drm_crtc *crtc);
Daniel Vetter229fca92014-04-24 23:55:09 +0200105static void haswell_set_pipeconf(struct drm_crtc *crtc);
106static void intel_set_pipe_csc(struct drm_crtc *crtc);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200107static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200108 const struct intel_crtc_state *pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +0200109static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200110 const struct intel_crtc_state *pipe_config);
Maarten Lankhorst613d2b22015-07-21 13:28:58 +0200111static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
Chandra Konduru549e2bf2015-04-07 15:28:38 -0700113static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200115static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
116 int num_connectors);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +0200117static void skylake_pfit_enable(struct intel_crtc *crtc);
118static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
119static void ironlake_pfit_enable(struct intel_crtc *crtc);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +0200120static void intel_modeset_setup_hw_state(struct drm_device *dev);
Matt Roper200757f2015-12-03 11:37:36 -0800121static void intel_pre_disable_primary(struct drm_crtc *crtc);
Damien Lespiaue7457a92013-08-08 22:28:59 +0100122
Jesse Barnes79e53942008-11-07 14:24:08 -0800123typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400124 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -0800125} intel_range_t;
126
127typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -0400128 int dot_limit;
129 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800130} intel_p2_t;
131
Ma Lingd4906092009-03-18 20:13:27 +0800132typedef struct intel_limit intel_limit_t;
133struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -0400134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +0800136};
Jesse Barnes79e53942008-11-07 14:24:08 -0800137
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300138/* returns HPLL frequency in kHz */
139static int valleyview_get_vco(struct drm_i915_private *dev_priv)
140{
141 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
142
143 /* Obtain SKU information */
144 mutex_lock(&dev_priv->sb_lock);
145 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
146 CCK_FUSE_HPLL_FREQ_MASK;
147 mutex_unlock(&dev_priv->sb_lock);
148
149 return vco_freq[hpll_freq] * 1000;
150}
151
152static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
153 const char *name, u32 reg)
154{
155 u32 val;
156 int divider;
157
158 if (dev_priv->hpll_freq == 0)
159 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
160
161 mutex_lock(&dev_priv->sb_lock);
162 val = vlv_cck_read(dev_priv, reg);
163 mutex_unlock(&dev_priv->sb_lock);
164
165 divider = val & CCK_FREQUENCY_VALUES;
166
167 WARN((val & CCK_FREQUENCY_STATUS) !=
168 (divider << CCK_FREQUENCY_STATUS_SHIFT),
169 "%s change in progress\n", name);
170
171 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
172}
173
Daniel Vetterd2acd212012-10-20 20:57:43 +0200174int
175intel_pch_rawclk(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178
179 WARN_ON(!HAS_PCH_SPLIT(dev));
180
181 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
182}
183
Jani Nikula79e50a42015-08-26 10:58:20 +0300184/* hrawclock is 1/4 the FSB frequency */
185int intel_hrawclk(struct drm_device *dev)
186{
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 uint32_t clkcfg;
189
190 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
Wayne Boyer666a4532015-12-09 12:29:35 -0800191 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Jani Nikula79e50a42015-08-26 10:58:20 +0300192 return 200;
193
194 clkcfg = I915_READ(CLKCFG);
195 switch (clkcfg & CLKCFG_FSB_MASK) {
196 case CLKCFG_FSB_400:
197 return 100;
198 case CLKCFG_FSB_533:
199 return 133;
200 case CLKCFG_FSB_667:
201 return 166;
202 case CLKCFG_FSB_800:
203 return 200;
204 case CLKCFG_FSB_1067:
205 return 266;
206 case CLKCFG_FSB_1333:
207 return 333;
208 /* these two are just a guess; one of them might be right */
209 case CLKCFG_FSB_1600:
210 case CLKCFG_FSB_1600_ALT:
211 return 400;
212 default:
213 return 133;
214 }
215}
216
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300217static void intel_update_czclk(struct drm_i915_private *dev_priv)
218{
Wayne Boyer666a4532015-12-09 12:29:35 -0800219 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
Ville Syrjäläbfa7df02015-09-24 23:29:18 +0300220 return;
221
222 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
223 CCK_CZ_CLOCK_CONTROL);
224
225 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
226}
227
Chris Wilson021357a2010-09-07 20:54:59 +0100228static inline u32 /* units of 100MHz */
229intel_fdi_link_freq(struct drm_device *dev)
230{
Chris Wilson8b99e682010-10-13 09:59:17 +0100231 if (IS_GEN5(dev)) {
232 struct drm_i915_private *dev_priv = dev->dev_private;
233 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
234 } else
235 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100236}
237
Daniel Vetter5d536e22013-07-06 12:52:06 +0200238static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400239 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200240 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200241 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400242 .m = { .min = 96, .max = 140 },
243 .m1 = { .min = 18, .max = 26 },
244 .m2 = { .min = 6, .max = 16 },
245 .p = { .min = 4, .max = 128 },
246 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700247 .p2 = { .dot_limit = 165000,
248 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700249};
250
Daniel Vetter5d536e22013-07-06 12:52:06 +0200251static const intel_limit_t intel_limits_i8xx_dvo = {
252 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200253 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200254 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200255 .m = { .min = 96, .max = 140 },
256 .m1 = { .min = 18, .max = 26 },
257 .m2 = { .min = 6, .max = 16 },
258 .p = { .min = 4, .max = 128 },
259 .p1 = { .min = 2, .max = 33 },
260 .p2 = { .dot_limit = 165000,
261 .p2_slow = 4, .p2_fast = 4 },
262};
263
Keith Packarde4b36692009-06-05 19:22:17 -0700264static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400265 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200266 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200267 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 .m = { .min = 96, .max = 140 },
269 .m1 = { .min = 18, .max = 26 },
270 .m2 = { .min = 6, .max = 16 },
271 .p = { .min = 4, .max = 128 },
272 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 .p2 = { .dot_limit = 165000,
274 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700275};
Eric Anholt273e27c2011-03-30 13:01:10 -0700276
Keith Packarde4b36692009-06-05 19:22:17 -0700277static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400278 .dot = { .min = 20000, .max = 400000 },
279 .vco = { .min = 1400000, .max = 2800000 },
280 .n = { .min = 1, .max = 6 },
281 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100282 .m1 = { .min = 8, .max = 18 },
283 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700286 .p2 = { .dot_limit = 200000,
287 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700288};
289
290static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400291 .dot = { .min = 20000, .max = 400000 },
292 .vco = { .min = 1400000, .max = 2800000 },
293 .n = { .min = 1, .max = 6 },
294 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100295 .m1 = { .min = 8, .max = 18 },
296 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400297 .p = { .min = 7, .max = 98 },
298 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700299 .p2 = { .dot_limit = 112000,
300 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700301};
302
Eric Anholt273e27c2011-03-30 13:01:10 -0700303
Keith Packarde4b36692009-06-05 19:22:17 -0700304static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700305 .dot = { .min = 25000, .max = 270000 },
306 .vco = { .min = 1750000, .max = 3500000},
307 .n = { .min = 1, .max = 4 },
308 .m = { .min = 104, .max = 138 },
309 .m1 = { .min = 17, .max = 23 },
310 .m2 = { .min = 5, .max = 11 },
311 .p = { .min = 10, .max = 30 },
312 .p1 = { .min = 1, .max = 3},
313 .p2 = { .dot_limit = 270000,
314 .p2_slow = 10,
315 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800316 },
Keith Packarde4b36692009-06-05 19:22:17 -0700317};
318
319static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700320 .dot = { .min = 22000, .max = 400000 },
321 .vco = { .min = 1750000, .max = 3500000},
322 .n = { .min = 1, .max = 4 },
323 .m = { .min = 104, .max = 138 },
324 .m1 = { .min = 16, .max = 23 },
325 .m2 = { .min = 5, .max = 11 },
326 .p = { .min = 5, .max = 80 },
327 .p1 = { .min = 1, .max = 8},
328 .p2 = { .dot_limit = 165000,
329 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700330};
331
332static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700333 .dot = { .min = 20000, .max = 115000 },
334 .vco = { .min = 1750000, .max = 3500000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 104, .max = 138 },
337 .m1 = { .min = 17, .max = 23 },
338 .m2 = { .min = 5, .max = 11 },
339 .p = { .min = 28, .max = 112 },
340 .p1 = { .min = 2, .max = 8 },
341 .p2 = { .dot_limit = 0,
342 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800343 },
Keith Packarde4b36692009-06-05 19:22:17 -0700344};
345
346static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700347 .dot = { .min = 80000, .max = 224000 },
348 .vco = { .min = 1750000, .max = 3500000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 104, .max = 138 },
351 .m1 = { .min = 17, .max = 23 },
352 .m2 = { .min = 5, .max = 11 },
353 .p = { .min = 14, .max = 42 },
354 .p1 = { .min = 2, .max = 6 },
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800357 },
Keith Packarde4b36692009-06-05 19:22:17 -0700358};
359
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500360static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400361 .dot = { .min = 20000, .max = 400000},
362 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700363 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .n = { .min = 3, .max = 6 },
365 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700366 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400367 .m1 = { .min = 0, .max = 0 },
368 .m2 = { .min = 0, .max = 254 },
369 .p = { .min = 5, .max = 80 },
370 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700371 .p2 = { .dot_limit = 200000,
372 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700373};
374
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500375static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400376 .dot = { .min = 20000, .max = 400000 },
377 .vco = { .min = 1700000, .max = 3500000 },
378 .n = { .min = 3, .max = 6 },
379 .m = { .min = 2, .max = 256 },
380 .m1 = { .min = 0, .max = 0 },
381 .m2 = { .min = 0, .max = 254 },
382 .p = { .min = 7, .max = 112 },
383 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700384 .p2 = { .dot_limit = 112000,
385 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700386};
387
Eric Anholt273e27c2011-03-30 13:01:10 -0700388/* Ironlake / Sandybridge
389 *
390 * We calculate clock using (register_value + 2) for N/M1/M2, so here
391 * the range value for them is (actual_value - 2).
392 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800393static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700394 .dot = { .min = 25000, .max = 350000 },
395 .vco = { .min = 1760000, .max = 3510000 },
396 .n = { .min = 1, .max = 5 },
397 .m = { .min = 79, .max = 127 },
398 .m1 = { .min = 12, .max = 22 },
399 .m2 = { .min = 5, .max = 9 },
400 .p = { .min = 5, .max = 80 },
401 .p1 = { .min = 1, .max = 8 },
402 .p2 = { .dot_limit = 225000,
403 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700404};
405
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800406static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700407 .dot = { .min = 25000, .max = 350000 },
408 .vco = { .min = 1760000, .max = 3510000 },
409 .n = { .min = 1, .max = 3 },
410 .m = { .min = 79, .max = 118 },
411 .m1 = { .min = 12, .max = 22 },
412 .m2 = { .min = 5, .max = 9 },
413 .p = { .min = 28, .max = 112 },
414 .p1 = { .min = 2, .max = 8 },
415 .p2 = { .dot_limit = 225000,
416 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800417};
418
419static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700420 .dot = { .min = 25000, .max = 350000 },
421 .vco = { .min = 1760000, .max = 3510000 },
422 .n = { .min = 1, .max = 3 },
423 .m = { .min = 79, .max = 127 },
424 .m1 = { .min = 12, .max = 22 },
425 .m2 = { .min = 5, .max = 9 },
426 .p = { .min = 14, .max = 56 },
427 .p1 = { .min = 2, .max = 8 },
428 .p2 = { .dot_limit = 225000,
429 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800430};
431
Eric Anholt273e27c2011-03-30 13:01:10 -0700432/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800433static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700434 .dot = { .min = 25000, .max = 350000 },
435 .vco = { .min = 1760000, .max = 3510000 },
436 .n = { .min = 1, .max = 2 },
437 .m = { .min = 79, .max = 126 },
438 .m1 = { .min = 12, .max = 22 },
439 .m2 = { .min = 5, .max = 9 },
440 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400441 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700442 .p2 = { .dot_limit = 225000,
443 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800444};
445
446static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700447 .dot = { .min = 25000, .max = 350000 },
448 .vco = { .min = 1760000, .max = 3510000 },
449 .n = { .min = 1, .max = 3 },
450 .m = { .min = 79, .max = 126 },
451 .m1 = { .min = 12, .max = 22 },
452 .m2 = { .min = 5, .max = 9 },
453 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400454 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700455 .p2 = { .dot_limit = 225000,
456 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800457};
458
Ville Syrjälädc730512013-09-24 21:26:30 +0300459static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300460 /*
461 * These are the data rate limits (measured in fast clocks)
462 * since those are the strictest limits we have. The fast
463 * clock and actual rate limits are more relaxed, so checking
464 * them would make no difference.
465 */
466 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200467 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700468 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700469 .m1 = { .min = 2, .max = 3 },
470 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300471 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300472 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700473};
474
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300475static const intel_limit_t intel_limits_chv = {
476 /*
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
481 */
482 .dot = { .min = 25000 * 5, .max = 540000 * 5},
Ville Syrjälä17fe1022015-02-26 21:01:52 +0200483 .vco = { .min = 4800000, .max = 6480000 },
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300484 .n = { .min = 1, .max = 1 },
485 .m1 = { .min = 2, .max = 2 },
486 .m2 = { .min = 24 << 22, .max = 175 << 22 },
487 .p1 = { .min = 2, .max = 4 },
488 .p2 = { .p2_slow = 1, .p2_fast = 14 },
489};
490
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200491static const intel_limit_t intel_limits_bxt = {
492 /* FIXME: find real dot limits */
493 .dot = { .min = 0, .max = INT_MAX },
Vandana Kannane6292552015-07-01 17:02:57 +0530494 .vco = { .min = 4800000, .max = 6700000 },
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200495 .n = { .min = 1, .max = 1 },
496 .m1 = { .min = 2, .max = 2 },
497 /* FIXME: find real m2 limits */
498 .m2 = { .min = 2 << 22, .max = 255 << 22 },
499 .p1 = { .min = 2, .max = 4 },
500 .p2 = { .p2_slow = 1, .p2_fast = 20 },
501};
502
Ander Conselvan de Oliveiracdba9542015-06-01 12:49:51 +0200503static bool
504needs_modeset(struct drm_crtc_state *state)
505{
Maarten Lankhorstfc596662015-07-21 13:28:57 +0200506 return drm_atomic_crtc_needs_modeset(state);
Ander Conselvan de Oliveiracdba9542015-06-01 12:49:51 +0200507}
508
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300509/**
510 * Returns whether any output on the specified pipe is of the specified type
511 */
Damien Lespiau40935612014-10-29 11:16:59 +0000512bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300513{
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300514 struct drm_device *dev = crtc->base.dev;
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300515 struct intel_encoder *encoder;
516
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +0300517 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300518 if (encoder->type == type)
519 return true;
520
521 return false;
522}
523
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200524/**
525 * Returns whether any output on the specified pipe will have the specified
526 * type after a staged modeset is complete, i.e., the same as
527 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
528 * encoder->crtc.
529 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200530static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
531 int type)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200532{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200533 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +0300534 struct drm_connector *connector;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200535 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200536 struct intel_encoder *encoder;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200537 int i, num_connectors = 0;
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200538
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +0300539 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200540 if (connector_state->crtc != crtc_state->base.crtc)
541 continue;
542
543 num_connectors++;
544
545 encoder = to_intel_encoder(connector_state->best_encoder);
546 if (encoder->type == type)
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200547 return true;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200548 }
549
550 WARN_ON(num_connectors == 0);
Ander Conselvan de Oliveirad0737e12014-10-29 11:32:30 +0200551
552 return false;
553}
554
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200555static const intel_limit_t *
556intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800557{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200558 struct drm_device *dev = crtc_state->base.crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800559 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800560
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100562 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000563 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800564 limit = &intel_limits_ironlake_dual_lvds_100m;
565 else
566 limit = &intel_limits_ironlake_dual_lvds;
567 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000568 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800569 limit = &intel_limits_ironlake_single_lvds_100m;
570 else
571 limit = &intel_limits_ironlake_single_lvds;
572 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200573 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800574 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800575
576 return limit;
577}
578
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200579static const intel_limit_t *
580intel_g4x_limit(struct intel_crtc_state *crtc_state)
Ma Ling044c7c42009-03-18 20:13:23 +0800581{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200582 struct drm_device *dev = crtc_state->base.crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800583 const intel_limit_t *limit;
584
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200585 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100586 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700587 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800588 else
Keith Packarde4b36692009-06-05 19:22:17 -0700589 limit = &intel_limits_g4x_single_channel_lvds;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700592 limit = &intel_limits_g4x_hdmi;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200593 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700594 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800595 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700596 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800597
598 return limit;
599}
600
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200601static const intel_limit_t *
602intel_limit(struct intel_crtc_state *crtc_state, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800603{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200604 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800605 const intel_limit_t *limit;
606
Imre Deak5ab7b0b2015-03-06 03:29:25 +0200607 if (IS_BROXTON(dev))
608 limit = &intel_limits_bxt;
609 else if (HAS_PCH_SPLIT(dev))
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200610 limit = intel_ironlake_limit(crtc_state, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800611 else if (IS_G4X(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200612 limit = intel_g4x_limit(crtc_state);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500613 } else if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200614 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500615 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800616 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500617 limit = &intel_limits_pineview_sdvo;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300618 } else if (IS_CHERRYVIEW(dev)) {
619 limit = &intel_limits_chv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700620 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300621 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100622 } else if (!IS_GEN2(dev)) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200623 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100624 limit = &intel_limits_i9xx_lvds;
625 else
626 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800627 } else {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200628 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700629 limit = &intel_limits_i8xx_lvds;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200630 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700631 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200632 else
633 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800634 }
635 return limit;
636}
637
Imre Deakdccbea32015-06-22 23:35:51 +0300638/*
639 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
640 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
641 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
642 * The helpers' return value is the rate of the clock that is fed to the
643 * display engine's pipe which can be the above fast dot clock rate or a
644 * divided-down version of it.
645 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500646/* m1 is reserved as 0 in Pineview, n is a ring counter */
Imre Deakdccbea32015-06-22 23:35:51 +0300647static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800648{
Shaohua Li21778322009-02-23 15:19:16 +0800649 clock->m = clock->m2 + 2;
650 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200651 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300652 return 0;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300653 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
654 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300655
656 return clock->dot;
Shaohua Li21778322009-02-23 15:19:16 +0800657}
658
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200659static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
660{
661 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
662}
663
Imre Deakdccbea32015-06-22 23:35:51 +0300664static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800665{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200666 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800667 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200668 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300669 return 0;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300670 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
671 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300672
673 return clock->dot;
Jesse Barnes79e53942008-11-07 14:24:08 -0800674}
675
Imre Deakdccbea32015-06-22 23:35:51 +0300676static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
Imre Deak589eca62015-06-22 23:35:50 +0300677{
678 clock->m = clock->m1 * clock->m2;
679 clock->p = clock->p1 * clock->p2;
680 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300681 return 0;
Imre Deak589eca62015-06-22 23:35:50 +0300682 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
683 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300684
685 return clock->dot / 5;
Imre Deak589eca62015-06-22 23:35:50 +0300686}
687
Imre Deakdccbea32015-06-22 23:35:51 +0300688int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300689{
690 clock->m = clock->m1 * clock->m2;
691 clock->p = clock->p1 * clock->p2;
692 if (WARN_ON(clock->n == 0 || clock->p == 0))
Imre Deakdccbea32015-06-22 23:35:51 +0300693 return 0;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300694 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
695 clock->n << 22);
696 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Imre Deakdccbea32015-06-22 23:35:51 +0300697
698 return clock->dot / 5;
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300699}
700
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800701#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800702/**
703 * Returns whether the given set of divisors are valid for a given refclk with
704 * the given connectors.
705 */
706
Chris Wilson1b894b52010-12-14 20:04:54 +0000707static bool intel_PLL_is_valid(struct drm_device *dev,
708 const intel_limit_t *limit,
709 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800710{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300711 if (clock->n < limit->n.min || limit->n.max < clock->n)
712 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800713 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400714 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800715 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400716 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800717 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400718 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300719
Wayne Boyer666a4532015-12-09 12:29:35 -0800720 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
721 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300722 if (clock->m1 <= clock->m2)
723 INTELPllInvalid("m1 <= m2\n");
724
Wayne Boyer666a4532015-12-09 12:29:35 -0800725 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300726 if (clock->p < limit->p.min || limit->p.max < clock->p)
727 INTELPllInvalid("p out of range\n");
728 if (clock->m < limit->m.min || limit->m.max < clock->m)
729 INTELPllInvalid("m out of range\n");
730 }
731
Jesse Barnes79e53942008-11-07 14:24:08 -0800732 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400733 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800734 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
735 * connector, etc., rather than just a single range.
736 */
737 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400738 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800739
740 return true;
741}
742
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300743static int
744i9xx_select_p2_div(const intel_limit_t *limit,
745 const struct intel_crtc_state *crtc_state,
746 int target)
Jesse Barnes79e53942008-11-07 14:24:08 -0800747{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300748 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800749
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800751 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100752 * For LVDS just rely on its current settings for dual-channel.
753 * We haven't figured out how to reliably set up different
754 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800755 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100756 if (intel_is_dual_link_lvds(dev))
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300757 return limit->p2.p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800758 else
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300759 return limit->p2.p2_slow;
Jesse Barnes79e53942008-11-07 14:24:08 -0800760 } else {
761 if (target < limit->p2.dot_limit)
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300762 return limit->p2.p2_slow;
Jesse Barnes79e53942008-11-07 14:24:08 -0800763 else
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300764 return limit->p2.p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -0800765 }
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300766}
767
768static bool
769i9xx_find_best_dpll(const intel_limit_t *limit,
770 struct intel_crtc_state *crtc_state,
771 int target, int refclk, intel_clock_t *match_clock,
772 intel_clock_t *best_clock)
773{
774 struct drm_device *dev = crtc_state->base.crtc->dev;
775 intel_clock_t clock;
776 int err = target;
Jesse Barnes79e53942008-11-07 14:24:08 -0800777
Akshay Joshi0206e352011-08-16 15:34:10 -0400778 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800779
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300780 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
781
Zhao Yakui42158662009-11-20 11:24:18 +0800782 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
783 clock.m1++) {
784 for (clock.m2 = limit->m2.min;
785 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200786 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800787 break;
788 for (clock.n = limit->n.min;
789 clock.n <= limit->n.max; clock.n++) {
790 for (clock.p1 = limit->p1.min;
791 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800792 int this_err;
793
Imre Deakdccbea32015-06-22 23:35:51 +0300794 i9xx_calc_dpll_params(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800797 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800801
802 this_err = abs(clock.dot - target);
803 if (this_err < err) {
804 *best_clock = clock;
805 err = this_err;
806 }
807 }
808 }
809 }
810 }
811
812 return (err != target);
813}
814
Ma Lingd4906092009-03-18 20:13:27 +0800815static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200816pnv_find_best_dpll(const intel_limit_t *limit,
817 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200820{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300821 struct drm_device *dev = crtc_state->base.crtc->dev;
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200822 intel_clock_t clock;
823 int err = target;
824
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200825 memset(best_clock, 0, sizeof(*best_clock));
826
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300827 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
828
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200829 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
830 clock.m1++) {
831 for (clock.m2 = limit->m2.min;
832 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200833 for (clock.n = limit->n.min;
834 clock.n <= limit->n.max; clock.n++) {
835 for (clock.p1 = limit->p1.min;
836 clock.p1 <= limit->p1.max; clock.p1++) {
837 int this_err;
838
Imre Deakdccbea32015-06-22 23:35:51 +0300839 pnv_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800840 if (!intel_PLL_is_valid(dev, limit,
841 &clock))
842 continue;
843 if (match_clock &&
844 clock.p != match_clock->p)
845 continue;
846
847 this_err = abs(clock.dot - target);
848 if (this_err < err) {
849 *best_clock = clock;
850 err = this_err;
851 }
852 }
853 }
854 }
855 }
856
857 return (err != target);
858}
859
Ma Lingd4906092009-03-18 20:13:27 +0800860static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200861g4x_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800865{
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300866 struct drm_device *dev = crtc_state->base.crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800867 intel_clock_t clock;
868 int max_n;
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300869 bool found = false;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800872
873 memset(best_clock, 0, sizeof(*best_clock));
Ville Syrjälä3b1429d2015-06-18 13:47:22 +0300874
875 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
876
Ma Lingd4906092009-03-18 20:13:27 +0800877 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200878 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200880 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800881 for (clock.m1 = limit->m1.max;
882 clock.m1 >= limit->m1.min; clock.m1--) {
883 for (clock.m2 = limit->m2.max;
884 clock.m2 >= limit->m2.min; clock.m2--) {
885 for (clock.p1 = limit->p1.max;
886 clock.p1 >= limit->p1.min; clock.p1--) {
887 int this_err;
888
Imre Deakdccbea32015-06-22 23:35:51 +0300889 i9xx_calc_dpll_params(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800892 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000893
894 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800895 if (this_err < err_most) {
896 *best_clock = clock;
897 err_most = this_err;
898 max_n = clock.n;
899 found = true;
900 }
901 }
902 }
903 }
904 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800905 return found;
906}
Ma Lingd4906092009-03-18 20:13:27 +0800907
Imre Deakd5dd62b2015-03-17 11:40:03 +0200908/*
909 * Check if the calculated PLL configuration is more optimal compared to the
910 * best configuration and error found so far. Return the calculated error.
911 */
912static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
913 const intel_clock_t *calculated_clock,
914 const intel_clock_t *best_clock,
915 unsigned int best_error_ppm,
916 unsigned int *error_ppm)
917{
Imre Deak9ca3ba02015-03-17 11:40:05 +0200918 /*
919 * For CHV ignore the error and consider only the P value.
920 * Prefer a bigger P value based on HW requirements.
921 */
922 if (IS_CHERRYVIEW(dev)) {
923 *error_ppm = 0;
924
925 return calculated_clock->p > best_clock->p;
926 }
927
Imre Deak24be4e42015-03-17 11:40:04 +0200928 if (WARN_ON_ONCE(!target_freq))
929 return false;
930
Imre Deakd5dd62b2015-03-17 11:40:03 +0200931 *error_ppm = div_u64(1000000ULL *
932 abs(target_freq - calculated_clock->dot),
933 target_freq);
934 /*
935 * Prefer a better P value over a better (smaller) error if the error
936 * is small. Ensure this preference for future configurations too by
937 * setting the error to 0.
938 */
939 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
940 *error_ppm = 0;
941
942 return true;
943 }
944
945 return *error_ppm + 10 < best_error_ppm;
946}
947
Zhenyu Wang2c072452009-06-05 15:38:42 +0800948static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200949vlv_find_best_dpll(const intel_limit_t *limit,
950 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200951 int target, int refclk, intel_clock_t *match_clock,
952 intel_clock_t *best_clock)
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700953{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +0300955 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300956 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300957 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300958 /* min update 19.2 MHz */
959 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300960 bool found = false;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700961
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300962 target *= 5; /* fast clock */
963
964 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700965
966 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300967 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300968 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300969 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300970 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300971 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700972 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300973 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Imre Deakd5dd62b2015-03-17 11:40:03 +0200974 unsigned int ppm;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300975
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300976 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
977 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300978
Imre Deakdccbea32015-06-22 23:35:51 +0300979 vlv_calc_dpll_params(refclk, &clock);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300980
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300981 if (!intel_PLL_is_valid(dev, limit,
982 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300983 continue;
984
Imre Deakd5dd62b2015-03-17 11:40:03 +0200985 if (!vlv_PLL_is_optimal(dev, target,
986 &clock,
987 best_clock,
988 bestppm, &ppm))
989 continue;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300990
Imre Deakd5dd62b2015-03-17 11:40:03 +0200991 *best_clock = clock;
992 bestppm = ppm;
993 found = true;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700994 }
995 }
996 }
997 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700998
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300999 return found;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07001000}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001001
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001002static bool
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02001003chv_find_best_dpll(const intel_limit_t *limit,
1004 struct intel_crtc_state *crtc_state,
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001005 int target, int refclk, intel_clock_t *match_clock,
1006 intel_clock_t *best_clock)
1007{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02001008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Ander Conselvan de Oliveiraa919ff12014-10-20 13:46:43 +03001009 struct drm_device *dev = crtc->base.dev;
Imre Deak9ca3ba02015-03-17 11:40:05 +02001010 unsigned int best_error_ppm;
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001011 intel_clock_t clock;
1012 uint64_t m2;
1013 int found = false;
1014
1015 memset(best_clock, 0, sizeof(*best_clock));
Imre Deak9ca3ba02015-03-17 11:40:05 +02001016 best_error_ppm = 1000000;
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001017
1018 /*
1019 * Based on hardware doc, the n always set to 1, and m1 always
1020 * set to 2. If requires to support 200Mhz refclk, we need to
1021 * revisit this because n may not 1 anymore.
1022 */
1023 clock.n = 1, clock.m1 = 2;
1024 target *= 5; /* fast clock */
1025
1026 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1027 for (clock.p2 = limit->p2.p2_fast;
1028 clock.p2 >= limit->p2.p2_slow;
1029 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Imre Deak9ca3ba02015-03-17 11:40:05 +02001030 unsigned int error_ppm;
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001031
1032 clock.p = clock.p1 * clock.p2;
1033
1034 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1035 clock.n) << 22, refclk * clock.m1);
1036
1037 if (m2 > INT_MAX/clock.m1)
1038 continue;
1039
1040 clock.m2 = m2;
1041
Imre Deakdccbea32015-06-22 23:35:51 +03001042 chv_calc_dpll_params(refclk, &clock);
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001043
1044 if (!intel_PLL_is_valid(dev, limit, &clock))
1045 continue;
1046
Imre Deak9ca3ba02015-03-17 11:40:05 +02001047 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1048 best_error_ppm, &error_ppm))
1049 continue;
1050
1051 *best_clock = clock;
1052 best_error_ppm = error_ppm;
1053 found = true;
Chon Ming Leeef9348c2014-04-09 13:28:18 +03001054 }
1055 }
1056
1057 return found;
1058}
1059
Imre Deak5ab7b0b2015-03-06 03:29:25 +02001060bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1061 intel_clock_t *best_clock)
1062{
1063 int refclk = i9xx_get_refclk(crtc_state, 0);
1064
1065 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1066 target_clock, refclk, NULL, best_clock);
1067}
1068
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001069bool intel_crtc_active(struct drm_crtc *crtc)
1070{
1071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073 /* Be paranoid as we can arrive here with only partial
1074 * state retrieved from the hardware during setup.
1075 *
Damien Lespiau241bfc32013-09-25 16:45:37 +01001076 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001077 * as Haswell has gained clock readout/fastboot support.
1078 *
Dave Airlie66e514c2014-04-03 07:51:54 +10001079 * We can ditch the crtc->primary->fb check as soon as we can
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001080 * properly reconstruct framebuffers.
Matt Roperc3d1f432015-03-09 10:19:23 -07001081 *
1082 * FIXME: The intel_crtc->active here should be switched to
1083 * crtc->state->active once we have proper CRTC states wired up
1084 * for atomic.
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001085 */
Matt Roperc3d1f432015-03-09 10:19:23 -07001086 return intel_crtc->active && crtc->primary->state->fb &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001087 intel_crtc->config->base.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001088}
1089
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001090enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1091 enum pipe pipe)
1092{
1093 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1095
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001096 return intel_crtc->config->cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02001097}
1098
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001099static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1100{
1101 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001102 i915_reg_t reg = PIPEDSL(pipe);
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001103 u32 line1, line2;
1104 u32 line_mask;
1105
1106 if (IS_GEN2(dev))
1107 line_mask = DSL_LINEMASK_GEN2;
1108 else
1109 line_mask = DSL_LINEMASK_GEN3;
1110
1111 line1 = I915_READ(reg) & line_mask;
Daniel Vetter6adfb1e2015-07-07 09:10:40 +02001112 msleep(5);
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001113 line2 = I915_READ(reg) & line_mask;
1114
1115 return line1 == line2;
1116}
1117
Keith Packardab7ad7f2010-10-03 00:33:06 -07001118/*
1119 * intel_wait_for_pipe_off - wait for pipe to turn off
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001120 * @crtc: crtc whose pipe to wait for
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001121 *
1122 * After disabling a pipe, we can't wait for vblank in the usual way,
1123 * spinning on the vblank interrupt status bit, since we won't actually
1124 * see an interrupt when the pipe is disabled.
1125 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001126 * On Gen4 and above:
1127 * wait for the pipe register state bit to turn off
1128 *
1129 * Otherwise:
1130 * wait for the display line value to settle (it usually
1131 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001132 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001133 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001134static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001135{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001136 struct drm_device *dev = crtc->base.dev;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001137 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001138 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03001139 enum pipe pipe = crtc->pipe;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001140
Keith Packardab7ad7f2010-10-03 00:33:06 -07001141 if (INTEL_INFO(dev)->gen >= 4) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001142 i915_reg_t reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001143
Keith Packardab7ad7f2010-10-03 00:33:06 -07001144 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001145 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1146 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001147 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001148 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -07001149 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +03001150 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001151 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001152 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001153}
1154
Jesse Barnesb24e7172011-01-04 15:09:30 -08001155static const char *state_string(bool enabled)
1156{
1157 return enabled ? "on" : "off";
1158}
1159
1160/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +02001161void assert_pll(struct drm_i915_private *dev_priv,
1162 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001163{
Jesse Barnesb24e7172011-01-04 15:09:30 -08001164 u32 val;
1165 bool cur_state;
1166
Ville Syrjälä649636e2015-09-22 19:50:01 +03001167 val = I915_READ(DPLL(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001168 cur_state = !!(val & DPLL_VCO_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001169 I915_STATE_WARN(cur_state != state,
Jesse Barnesb24e7172011-01-04 15:09:30 -08001170 "PLL state assertion failure (expected %s, current %s)\n",
1171 state_string(state), state_string(cur_state));
1172}
Jesse Barnesb24e7172011-01-04 15:09:30 -08001173
Jani Nikula23538ef2013-08-27 15:12:22 +03001174/* XXX: the dsi pll is shared between MIPI DSI ports */
1175static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1176{
1177 u32 val;
1178 bool cur_state;
1179
Ville Syrjäläa5805162015-05-26 20:42:30 +03001180 mutex_lock(&dev_priv->sb_lock);
Jani Nikula23538ef2013-08-27 15:12:22 +03001181 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
Ville Syrjäläa5805162015-05-26 20:42:30 +03001182 mutex_unlock(&dev_priv->sb_lock);
Jani Nikula23538ef2013-08-27 15:12:22 +03001183
1184 cur_state = val & DSI_PLL_VCO_EN;
Rob Clarke2c719b2014-12-15 13:56:32 -05001185 I915_STATE_WARN(cur_state != state,
Jani Nikula23538ef2013-08-27 15:12:22 +03001186 "DSI PLL state assertion failure (expected %s, current %s)\n",
1187 state_string(state), state_string(cur_state));
1188}
1189#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1190#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1191
Daniel Vetter55607e82013-06-16 21:42:39 +02001192struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +02001193intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08001194{
Daniel Vettere2b78262013-06-07 23:10:03 +02001195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1196
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001197 if (crtc->config->shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +02001198 return NULL;
1199
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001200 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +02001201}
1202
Jesse Barnesb24e7172011-01-04 15:09:30 -08001203/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +02001204void assert_shared_dpll(struct drm_i915_private *dev_priv,
1205 struct intel_shared_dpll *pll,
1206 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001207{
Jesse Barnes040484a2011-01-03 12:14:26 -08001208 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +02001209 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001210
Chris Wilson92b27b02012-05-20 18:10:50 +01001211 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +02001212 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001213 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001214
Daniel Vetter53589012013-06-05 13:34:16 +02001215 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Rob Clarke2c719b2014-12-15 13:56:32 -05001216 I915_STATE_WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +02001217 "%s assertion failure (expected %s, current %s)\n",
1218 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001219}
Jesse Barnes040484a2011-01-03 12:14:26 -08001220
1221static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223{
Jesse Barnes040484a2011-01-03 12:14:26 -08001224 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001227
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
Ville Syrjälä649636e2015-09-22 19:50:01 +03001230 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
Paulo Zanoniad80a812012-10-24 16:06:19 -02001231 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001232 } else {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001233 u32 val = I915_READ(FDI_TX_CTL(pipe));
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001234 cur_state = !!(val & FDI_TX_ENABLE);
1235 }
Rob Clarke2c719b2014-12-15 13:56:32 -05001236 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001237 "FDI TX state assertion failure (expected %s, current %s)\n",
1238 state_string(state), state_string(cur_state));
1239}
1240#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1241#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1242
1243static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1244 enum pipe pipe, bool state)
1245{
Jesse Barnes040484a2011-01-03 12:14:26 -08001246 u32 val;
1247 bool cur_state;
1248
Ville Syrjälä649636e2015-09-22 19:50:01 +03001249 val = I915_READ(FDI_RX_CTL(pipe));
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001250 cur_state = !!(val & FDI_RX_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001251 I915_STATE_WARN(cur_state != state,
Jesse Barnes040484a2011-01-03 12:14:26 -08001252 "FDI RX state assertion failure (expected %s, current %s)\n",
1253 state_string(state), state_string(cur_state));
1254}
1255#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1256#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1257
1258static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe)
1260{
Jesse Barnes040484a2011-01-03 12:14:26 -08001261 u32 val;
1262
1263 /* ILK FDI PLL is always enabled */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001264 if (INTEL_INFO(dev_priv->dev)->gen == 5)
Jesse Barnes040484a2011-01-03 12:14:26 -08001265 return;
1266
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001267 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001268 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001269 return;
1270
Ville Syrjälä649636e2015-09-22 19:50:01 +03001271 val = I915_READ(FDI_TX_CTL(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001272 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
Jesse Barnes040484a2011-01-03 12:14:26 -08001273}
1274
Daniel Vetter55607e82013-06-16 21:42:39 +02001275void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1276 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001277{
Jesse Barnes040484a2011-01-03 12:14:26 -08001278 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001279 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001280
Ville Syrjälä649636e2015-09-22 19:50:01 +03001281 val = I915_READ(FDI_RX_CTL(pipe));
Daniel Vetter55607e82013-06-16 21:42:39 +02001282 cur_state = !!(val & FDI_RX_PLL_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001283 I915_STATE_WARN(cur_state != state,
Daniel Vetter55607e82013-06-16 21:42:39 +02001284 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1285 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001286}
1287
Daniel Vetterb680c372014-09-19 18:27:27 +02001288void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
Jesse Barnesea0760c2011-01-04 15:09:32 -08001290{
Jani Nikulabedd4db2014-08-22 15:04:13 +03001291 struct drm_device *dev = dev_priv->dev;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001292 i915_reg_t pp_reg;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001293 u32 val;
1294 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001295 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001296
Jani Nikulabedd4db2014-08-22 15:04:13 +03001297 if (WARN_ON(HAS_DDI(dev)))
1298 return;
1299
1300 if (HAS_PCH_SPLIT(dev)) {
1301 u32 port_sel;
1302
Jesse Barnesea0760c2011-01-04 15:09:32 -08001303 pp_reg = PCH_PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001304 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1305
1306 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1307 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1308 panel_pipe = PIPE_B;
1309 /* XXX: else fix for eDP */
Wayne Boyer666a4532015-12-09 12:29:35 -08001310 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Jani Nikulabedd4db2014-08-22 15:04:13 +03001311 /* presumably write lock depends on pipe, not port select */
1312 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1313 panel_pipe = pipe;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001314 } else {
1315 pp_reg = PP_CONTROL;
Jani Nikulabedd4db2014-08-22 15:04:13 +03001316 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1317 panel_pipe = PIPE_B;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001318 }
1319
1320 val = I915_READ(pp_reg);
1321 if (!(val & PANEL_POWER_ON) ||
Jani Nikulaec49ba22014-08-21 15:06:25 +03001322 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
Jesse Barnesea0760c2011-01-04 15:09:32 -08001323 locked = false;
1324
Rob Clarke2c719b2014-12-15 13:56:32 -05001325 I915_STATE_WARN(panel_pipe == pipe && locked,
Jesse Barnesea0760c2011-01-04 15:09:32 -08001326 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001327 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001328}
1329
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001330static void assert_cursor(struct drm_i915_private *dev_priv,
1331 enum pipe pipe, bool state)
1332{
1333 struct drm_device *dev = dev_priv->dev;
1334 bool cur_state;
1335
Paulo Zanonid9d82082014-02-27 16:30:56 -03001336 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä0b87c242015-09-22 19:47:51 +03001337 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
Paulo Zanonid9d82082014-02-27 16:30:56 -03001338 else
Ville Syrjälä5efb3e22014-04-09 13:28:53 +03001339 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001340
Rob Clarke2c719b2014-12-15 13:56:32 -05001341 I915_STATE_WARN(cur_state != state,
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001342 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1343 pipe_name(pipe), state_string(state), state_string(cur_state));
1344}
1345#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1346#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1347
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001348void assert_pipe(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001350{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001351 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001352 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1353 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001354
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001355 /* if we need the pipe quirk it must be always on */
1356 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1357 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Daniel Vetter8e636782012-01-22 01:36:48 +01001358 state = true;
1359
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001360 if (!intel_display_power_is_enabled(dev_priv,
Paulo Zanonib97186f2013-05-03 12:15:36 -03001361 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001362 cur_state = false;
1363 } else {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001364 u32 val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni69310162013-01-29 16:35:19 -02001365 cur_state = !!(val & PIPECONF_ENABLE);
1366 }
1367
Rob Clarke2c719b2014-12-15 13:56:32 -05001368 I915_STATE_WARN(cur_state != state,
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001369 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001370 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001371}
1372
Chris Wilson931872f2012-01-16 23:01:13 +00001373static void assert_plane(struct drm_i915_private *dev_priv,
1374 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001375{
Jesse Barnesb24e7172011-01-04 15:09:30 -08001376 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001377 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001378
Ville Syrjälä649636e2015-09-22 19:50:01 +03001379 val = I915_READ(DSPCNTR(plane));
Chris Wilson931872f2012-01-16 23:01:13 +00001380 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001381 I915_STATE_WARN(cur_state != state,
Chris Wilson931872f2012-01-16 23:01:13 +00001382 "plane %c assertion failure (expected %s, current %s)\n",
1383 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001384}
1385
Chris Wilson931872f2012-01-16 23:01:13 +00001386#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1387#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1388
Jesse Barnesb24e7172011-01-04 15:09:30 -08001389static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001392 struct drm_device *dev = dev_priv->dev;
Ville Syrjälä649636e2015-09-22 19:50:01 +03001393 int i;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001394
Ville Syrjälä653e1022013-06-04 13:49:05 +03001395 /* Primary planes are fixed to pipes on gen4+ */
1396 if (INTEL_INFO(dev)->gen >= 4) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001397 u32 val = I915_READ(DSPCNTR(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001398 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
Adam Jackson28c057942011-10-07 14:38:42 -04001399 "plane %c assertion failure, should be disabled but not\n",
1400 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001401 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001402 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001403
Jesse Barnesb24e7172011-01-04 15:09:30 -08001404 /* Need to check both planes against the pipe */
Damien Lespiau055e3932014-08-18 13:49:10 +01001405 for_each_pipe(dev_priv, i) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001406 u32 val = I915_READ(DSPCNTR(i));
1407 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
Jesse Barnesb24e7172011-01-04 15:09:30 -08001408 DISPPLANE_SEL_PIPE_SHIFT;
Rob Clarke2c719b2014-12-15 13:56:32 -05001409 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001410 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1411 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001412 }
1413}
1414
Jesse Barnes19332d72013-03-28 09:55:38 -07001415static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1416 enum pipe pipe)
1417{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001418 struct drm_device *dev = dev_priv->dev;
Ville Syrjälä649636e2015-09-22 19:50:01 +03001419 int sprite;
Jesse Barnes19332d72013-03-28 09:55:38 -07001420
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001421 if (INTEL_INFO(dev)->gen >= 9) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001422 for_each_sprite(dev_priv, pipe, sprite) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001423 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
Rob Clarke2c719b2014-12-15 13:56:32 -05001424 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
Damien Lespiau7feb8b82014-03-12 21:05:38 +00001425 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1426 sprite, pipe_name(pipe));
1427 }
Wayne Boyer666a4532015-12-09 12:29:35 -08001428 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Damien Lespiau3bdcfc02015-02-28 14:54:09 +00001429 for_each_sprite(dev_priv, pipe, sprite) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001430 u32 val = I915_READ(SPCNTR(pipe, sprite));
Rob Clarke2c719b2014-12-15 13:56:32 -05001431 I915_STATE_WARN(val & SP_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001432 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +00001433 sprite_name(pipe, sprite), pipe_name(pipe));
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001434 }
1435 } else if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001436 u32 val = I915_READ(SPRCTL(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001437 I915_STATE_WARN(val & SPRITE_ENABLE,
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001438 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001439 plane_name(pipe), pipe_name(pipe));
1440 } else if (INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä649636e2015-09-22 19:50:01 +03001441 u32 val = I915_READ(DVSCNTR(pipe));
Rob Clarke2c719b2014-12-15 13:56:32 -05001442 I915_STATE_WARN(val & DVS_ENABLE,
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001443 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1444 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001445 }
1446}
1447
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001448static void assert_vblank_disabled(struct drm_crtc *crtc)
1449{
Rob Clarke2c719b2014-12-15 13:56:32 -05001450 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
Ville Syrjälä08c71e52014-08-06 14:49:45 +03001451 drm_crtc_vblank_put(crtc);
1452}
1453
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001454static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001455{
1456 u32 val;
1457 bool enabled;
1458
Rob Clarke2c719b2014-12-15 13:56:32 -05001459 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001460
Jesse Barnes92f25842011-01-04 15:09:34 -08001461 val = I915_READ(PCH_DREF_CONTROL);
1462 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1463 DREF_SUPERSPREAD_SOURCE_MASK));
Rob Clarke2c719b2014-12-15 13:56:32 -05001464 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
Jesse Barnes92f25842011-01-04 15:09:34 -08001465}
1466
Daniel Vetterab9412b2013-05-03 11:49:46 +02001467static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001469{
Jesse Barnes92f25842011-01-04 15:09:34 -08001470 u32 val;
1471 bool enabled;
1472
Ville Syrjälä649636e2015-09-22 19:50:01 +03001473 val = I915_READ(PCH_TRANSCONF(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001474 enabled = !!(val & TRANS_ENABLE);
Rob Clarke2c719b2014-12-15 13:56:32 -05001475 I915_STATE_WARN(enabled,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001476 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1477 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001478}
1479
Keith Packard4e634382011-08-06 10:39:45 -07001480static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1481 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001482{
1483 if ((val & DP_PORT_EN) == 0)
1484 return false;
1485
1486 if (HAS_PCH_CPT(dev_priv->dev)) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001487 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
Keith Packardf0575e92011-07-25 22:12:43 -07001488 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1489 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001490 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1491 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1492 return false;
Keith Packardf0575e92011-07-25 22:12:43 -07001493 } else {
1494 if ((val & DP_PIPE_MASK) != (pipe << 30))
1495 return false;
1496 }
1497 return true;
1498}
1499
Keith Packard1519b992011-08-06 10:35:34 -07001500static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, u32 val)
1502{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001503 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001504 return false;
1505
1506 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001507 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001508 return false;
Chon Ming Lee44f37d12014-04-09 13:28:21 +03001509 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1510 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1511 return false;
Keith Packard1519b992011-08-06 10:35:34 -07001512 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001513 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001514 return false;
1515 }
1516 return true;
1517}
1518
1519static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1520 enum pipe pipe, u32 val)
1521{
1522 if ((val & LVDS_PORT_EN) == 0)
1523 return false;
1524
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
1535static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, u32 val)
1537{
1538 if ((val & ADPA_DAC_ENABLE) == 0)
1539 return false;
1540 if (HAS_PCH_CPT(dev_priv->dev)) {
1541 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1542 return false;
1543 } else {
1544 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1545 return false;
1546 }
1547 return true;
1548}
1549
Jesse Barnes291906f2011-02-02 12:28:03 -08001550static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001551 enum pipe pipe, i915_reg_t reg,
1552 u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001553{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001554 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001555 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001556 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001557 i915_mmio_reg_offset(reg), pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001558
Rob Clarke2c719b2014-12-15 13:56:32 -05001559 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001560 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001561 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001562}
1563
1564static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001565 enum pipe pipe, i915_reg_t reg)
Jesse Barnes291906f2011-02-02 12:28:03 -08001566{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001567 u32 val = I915_READ(reg);
Rob Clarke2c719b2014-12-15 13:56:32 -05001568 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001569 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001570 i915_mmio_reg_offset(reg), pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001571
Rob Clarke2c719b2014-12-15 13:56:32 -05001572 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001573 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001574 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001575}
1576
1577static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1578 enum pipe pipe)
1579{
Jesse Barnes291906f2011-02-02 12:28:03 -08001580 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001581
Keith Packardf0575e92011-07-25 22:12:43 -07001582 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1583 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1584 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001585
Ville Syrjälä649636e2015-09-22 19:50:01 +03001586 val = I915_READ(PCH_ADPA);
Rob Clarke2c719b2014-12-15 13:56:32 -05001587 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001588 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001589 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001590
Ville Syrjälä649636e2015-09-22 19:50:01 +03001591 val = I915_READ(PCH_LVDS);
Rob Clarke2c719b2014-12-15 13:56:32 -05001592 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001593 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001594 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001595
Paulo Zanonie2debe92013-02-18 19:00:27 -03001596 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1597 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1598 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001599}
1600
Ville Syrjäläd288f652014-10-28 13:20:22 +02001601static void vlv_enable_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001602 const struct intel_crtc_state *pipe_config)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001603{
Daniel Vetter426115c2013-07-11 22:13:42 +02001604 struct drm_device *dev = crtc->base.dev;
1605 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001606 i915_reg_t reg = DPLL(crtc->pipe);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001607 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001608
Daniel Vetter426115c2013-07-11 22:13:42 +02001609 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001610
Daniel Vetter87442f72013-06-06 00:52:17 +02001611 /* PLL is protected by panel, make sure we can write it */
Jani Nikula6a9e7362014-08-22 15:06:35 +03001612 if (IS_MOBILE(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001613 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001614
Daniel Vetter426115c2013-07-11 22:13:42 +02001615 I915_WRITE(reg, dpll);
1616 POSTING_READ(reg);
1617 udelay(150);
1618
1619 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1620 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1621
Ville Syrjäläd288f652014-10-28 13:20:22 +02001622 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
Daniel Vetter426115c2013-07-11 22:13:42 +02001623 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001624
1625 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001626 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001627 POSTING_READ(reg);
1628 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001629 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001630 POSTING_READ(reg);
1631 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001632 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001633 POSTING_READ(reg);
1634 udelay(150); /* wait for warmup */
1635}
1636
Ville Syrjäläd288f652014-10-28 13:20:22 +02001637static void chv_enable_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001638 const struct intel_crtc_state *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001639{
1640 struct drm_device *dev = crtc->base.dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 int pipe = crtc->pipe;
1643 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001644 u32 tmp;
1645
1646 assert_pipe_disabled(dev_priv, crtc->pipe);
1647
Ville Syrjäläa5805162015-05-26 20:42:30 +03001648 mutex_lock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001649
1650 /* Enable back the 10bit clock to display controller */
1651 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1652 tmp |= DPIO_DCLKP_EN;
1653 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1654
Ville Syrjälä54433e92015-05-26 20:42:31 +03001655 mutex_unlock(&dev_priv->sb_lock);
1656
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001657 /*
1658 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1659 */
1660 udelay(1);
1661
1662 /* Enable PLL */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001663 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001664
1665 /* Check PLL is locked */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001666 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001667 DRM_ERROR("PLL %d failed to lock\n", pipe);
1668
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001669 /* not sure when this should be written */
Ville Syrjäläd288f652014-10-28 13:20:22 +02001670 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001671 POSTING_READ(DPLL_MD(pipe));
Chon Ming Lee9d556c92014-05-02 14:27:47 +03001672}
1673
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001674static int intel_num_dvo_pipes(struct drm_device *dev)
1675{
1676 struct intel_crtc *crtc;
1677 int count = 0;
1678
1679 for_each_intel_crtc(dev, crtc)
Maarten Lankhorst3538b9d2015-06-01 12:50:10 +02001680 count += crtc->base.state->active &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001681 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001682
1683 return count;
1684}
1685
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001686static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001687{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001688 struct drm_device *dev = crtc->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001690 i915_reg_t reg = DPLL(crtc->pipe);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001691 u32 dpll = crtc->config->dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001692
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001693 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001694
1695 /* No really, not for ILK+ */
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001696 BUG_ON(INTEL_INFO(dev)->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001697
1698 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001699 if (IS_MOBILE(dev) && !IS_I830(dev))
1700 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001701
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001702 /* Enable DVO 2x clock on both PLLs if necessary */
1703 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1704 /*
1705 * It appears to be important that we don't enable this
1706 * for the current pipe before otherwise configuring the
1707 * PLL. No idea how this should be handled if multiple
1708 * DVO outputs are enabled simultaneosly.
1709 */
1710 dpll |= DPLL_DVO_2X_MODE;
1711 I915_WRITE(DPLL(!crtc->pipe),
1712 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1713 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001714
Ville Syrjäläc2b63372015-10-07 22:08:25 +03001715 /*
1716 * Apparently we need to have VGA mode enabled prior to changing
1717 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1718 * dividers, even though the register value does change.
1719 */
1720 I915_WRITE(reg, 0);
1721
Ville Syrjälä8e7a65a2015-10-07 22:08:24 +03001722 I915_WRITE(reg, dpll);
1723
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02001730 crtc->config->dpll_hw_state.dpll_md);
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001739
1740 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001741 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001744 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001747 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750}
1751
1752/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001753 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001761static void i9xx_disable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001762{
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03001769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
Maarten Lankhorst3538b9d2015-06-01 12:50:10 +02001770 !intel_num_dvo_pipes(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03001771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03001777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
Ville Syrjäläb8afb912015-06-29 15:25:48 +03001785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
Daniel Vetter50b44a42013-06-05 13:34:33 +02001786 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001787}
1788
Jesse Barnesf6071162013-10-01 10:41:38 -07001789static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790{
Ville Syrjäläb8afb912015-06-29 15:25:48 +03001791 u32 val;
Jesse Barnesf6071162013-10-01 10:41:38 -07001792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
Imre Deake5cbfbf2014-01-09 17:08:16 +02001796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
Ville Syrjäläb8afb912015-06-29 15:25:48 +03001800 val = DPLL_VGA_MODE_DIS;
Jesse Barnesf6071162013-10-01 10:41:38 -07001801 if (pipe == PIPE_B)
Ville Syrjälä60bfe442015-06-29 15:25:49 +03001802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001805
1806}
1807
1808static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809{
Ville Syrjäläd7520482014-04-09 13:28:59 +03001810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001811 u32 val;
1812
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03001815
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001816 /* Set PLL en = 0 */
Ville Syrjälä60bfe442015-06-29 15:25:49 +03001817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
Ville Syrjäläa11b0702014-04-09 13:28:57 +03001819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
Ville Syrjäläd7520482014-04-09 13:28:59 +03001823
Ville Syrjäläa5805162015-05-26 20:42:30 +03001824 mutex_lock(&dev_priv->sb_lock);
Ville Syrjäläd7520482014-04-09 13:28:59 +03001825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
Ville Syrjäläa5805162015-05-26 20:42:30 +03001831 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesf6071162013-10-01 10:41:38 -07001832}
1833
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001834void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001835 struct intel_digital_port *dport,
1836 unsigned int expected_mask)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001837{
1838 u32 port_mask;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001839 i915_reg_t dpll_reg;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001840
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001841 switch (dport->port) {
1842 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001843 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001844 dpll_reg = DPLL(0);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001845 break;
1846 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001847 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001848 dpll_reg = DPLL(0);
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001849 expected_mask <<= 4;
Chon Ming Lee00fc31b2014-04-09 13:28:15 +03001850 break;
1851 case PORT_D:
1852 port_mask = DPLL_PORTD_READY_MASK;
1853 dpll_reg = DPIO_PHY_STATUS;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001854 break;
1855 default:
1856 BUG();
1857 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001858
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001859 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1860 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1861 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001862}
1863
Daniel Vetterb14b1052014-04-24 23:55:13 +02001864static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1865{
1866 struct drm_device *dev = crtc->base.dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
1868 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1869
Chris Wilsonbe19f0f2014-05-28 16:16:42 +01001870 if (WARN_ON(pll == NULL))
1871 return;
1872
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001873 WARN_ON(!pll->config.crtc_mask);
Daniel Vetterb14b1052014-04-24 23:55:13 +02001874 if (pll->active == 0) {
1875 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1876 WARN_ON(pll->on);
1877 assert_shared_dpll_disabled(dev_priv, pll);
1878
1879 pll->mode_set(dev_priv, pll);
1880 }
1881}
1882
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001883/**
Daniel Vetter85b38942014-04-24 23:55:14 +02001884 * intel_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001885 * @dev_priv: i915 private structure
1886 * @pipe: pipe PLL to enable
1887 *
1888 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1889 * drives the transcoder clock.
1890 */
Daniel Vetter85b38942014-04-24 23:55:14 +02001891static void intel_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001892{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001893 struct drm_device *dev = crtc->base.dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001895 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001896
Daniel Vetter87a875b2013-06-05 13:34:19 +02001897 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001898 return;
1899
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +02001900 if (WARN_ON(pll->config.crtc_mask == 0))
Chris Wilson48da64a2012-05-13 20:16:12 +01001901 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001902
Damien Lespiau74dd6922014-07-29 18:06:17 +01001903 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
Daniel Vetter46edb022013-06-05 13:34:12 +02001904 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001905 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001906
Daniel Vettercdbd2312013-06-05 13:34:03 +02001907 if (pll->active++) {
1908 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001909 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001910 return;
1911 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001912 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001913
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001914 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1915
Daniel Vetter46edb022013-06-05 13:34:12 +02001916 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001917 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001918 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001919}
1920
Damien Lespiauf6daaec2014-08-09 23:00:56 +01001921static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001922{
Damien Lespiau3d13ef22014-02-07 19:12:47 +00001923 struct drm_device *dev = crtc->base.dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettere2b78262013-06-07 23:10:03 +02001925 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001926
Jesse Barnes92f25842011-01-04 15:09:34 -08001927 /* PCH only available on ILK+ */
Jesse Barnes80aa9312015-08-03 13:09:11 -07001928 if (INTEL_INFO(dev)->gen < 5)
1929 return;
1930
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +02001931 if (pll == NULL)
1932 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001933
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +02001934 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
Chris Wilson48da64a2012-05-13 20:16:12 +01001935 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001936
Daniel Vetter46edb022013-06-05 13:34:12 +02001937 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1938 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001939 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001940
Chris Wilson48da64a2012-05-13 20:16:12 +01001941 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001942 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001943 return;
1944 }
1945
Daniel Vettere9d69442013-06-05 13:34:15 +02001946 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001947 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001948 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001949 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001950
Daniel Vetter46edb022013-06-05 13:34:12 +02001951 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001952 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001953 pll->on = false;
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -03001954
1955 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
Jesse Barnes92f25842011-01-04 15:09:34 -08001956}
1957
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001958static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1959 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001960{
Daniel Vetter23670b322012-11-01 09:15:30 +01001961 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001962 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001964 i915_reg_t reg;
1965 uint32_t val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001966
1967 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03001968 BUG_ON(!HAS_PCH_SPLIT(dev));
Jesse Barnes040484a2011-01-03 12:14:26 -08001969
1970 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001971 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001972 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001973
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv, pipe);
1976 assert_fdi_rx_enabled(dev_priv, pipe);
1977
Daniel Vetter23670b322012-11-01 09:15:30 +01001978 if (HAS_PCH_CPT(dev)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg = TRANS_CHICKEN2(pipe);
1982 val = I915_READ(reg);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001985 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001986
Daniel Vetterab9412b2013-05-03 11:49:46 +02001987 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001988 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001989 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001990
1991 if (HAS_PCH_IBX(dev_priv->dev)) {
1992 /*
Ville Syrjäläc5de7c62015-05-05 17:06:22 +03001993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
Jesse Barnese9bcff52011-06-24 12:19:20 -07001996 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001997 val &= ~PIPECONF_BPC_MASK;
Ville Syrjäläc5de7c62015-05-05 17:06:22 +03001998 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999 val |= PIPECONF_8BPC;
2000 else
2001 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07002002 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02002003
2004 val &= ~TRANS_INTERLACE_MASK;
2005 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02002006 if (HAS_PCH_IBX(dev_priv->dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03002007 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02002008 val |= TRANS_LEGACY_INTERLACED_ILK;
2009 else
2010 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02002011 else
2012 val |= TRANS_PROGRESSIVE;
2013
Jesse Barnes040484a2011-01-03 12:14:26 -08002014 I915_WRITE(reg, val | TRANS_ENABLE);
2015 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03002016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08002017}
2018
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002019static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02002020 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08002021{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002022 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002023
2024 /* PCH only available on ILK+ */
Ville Syrjälä55522f32014-09-03 14:09:53 +03002025 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002026
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002027 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01002028 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02002029 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002030
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002031 /* Workaround: set timing override bit. */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03002032 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
Daniel Vetter23670b322012-11-01 09:15:30 +01002033 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03002034 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002035
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02002036 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02002037 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002038
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02002039 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02002041 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002042 else
2043 val |= TRANS_PROGRESSIVE;
2044
Daniel Vetterab9412b2013-05-03 11:49:46 +02002045 I915_WRITE(LPT_TRANSCONF, val);
2046 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02002047 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002048}
2049
Paulo Zanonib8a4f402012-10-31 18:12:42 -02002050static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08002052{
Daniel Vetter23670b322012-11-01 09:15:30 +01002053 struct drm_device *dev = dev_priv->dev;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002054 i915_reg_t reg;
2055 uint32_t val;
Jesse Barnes040484a2011-01-03 12:14:26 -08002056
2057 /* FDI relies on the transcoder */
2058 assert_fdi_tx_disabled(dev_priv, pipe);
2059 assert_fdi_rx_disabled(dev_priv, pipe);
2060
Jesse Barnes291906f2011-02-02 12:28:03 -08002061 /* Ports must be off as well */
2062 assert_pch_ports_disabled(dev_priv, pipe);
2063
Daniel Vetterab9412b2013-05-03 11:49:46 +02002064 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002065 val = I915_READ(reg);
2066 val &= ~TRANS_ENABLE;
2067 I915_WRITE(reg, val);
2068 /* wait for PCH transcoder off, transcoder state */
2069 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03002070 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01002071
Ville Syrjäläc4656132015-10-29 21:25:56 +02002072 if (HAS_PCH_CPT(dev)) {
Daniel Vetter23670b322012-11-01 09:15:30 +01002073 /* Workaround: Clear the timing override chicken bit again. */
2074 reg = TRANS_CHICKEN2(pipe);
2075 val = I915_READ(reg);
2076 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2077 I915_WRITE(reg, val);
2078 }
Jesse Barnes040484a2011-01-03 12:14:26 -08002079}
2080
Paulo Zanoniab4d9662012-10-31 18:12:55 -02002081static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002082{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002083 u32 val;
2084
Daniel Vetterab9412b2013-05-03 11:49:46 +02002085 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002086 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02002087 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02002088 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02002089 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02002090 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02002091
2092 /* Workaround: clear timing override bit. */
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03002093 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
Daniel Vetter23670b322012-11-01 09:15:30 +01002094 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Ville Syrjälä36c0d0c2015-09-18 20:03:31 +03002095 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
Jesse Barnes92f25842011-01-04 15:09:34 -08002096}
2097
2098/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002099 * intel_enable_pipe - enable a pipe, asserting requirements
Paulo Zanoni03722642014-01-17 13:51:09 -02002100 * @crtc: crtc responsible for the pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08002101 *
Paulo Zanoni03722642014-01-17 13:51:09 -02002102 * Enable @crtc's pipe, making sure that various hardware specific requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08002103 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002104 */
Paulo Zanonie1fdc472014-01-17 13:51:12 -02002105static void intel_enable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002106{
Paulo Zanoni03722642014-01-17 13:51:09 -02002107 struct drm_device *dev = crtc->base.dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 enum pipe pipe = crtc->pipe;
Ville Syrjälä1a70a7282015-10-29 21:25:50 +02002110 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter1a240d42012-11-29 22:18:51 +01002111 enum pipe pch_transcoder;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002112 i915_reg_t reg;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002113 u32 val;
2114
Ville Syrjälä9e2ee2d2015-06-24 21:59:35 +03002115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002117 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002118 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02002119 assert_sprites_disabled(dev_priv, pipe);
2120
Paulo Zanoni681e5812012-12-06 11:12:38 -02002121 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002122 pch_transcoder = TRANSCODER_A;
2123 else
2124 pch_transcoder = pipe;
2125
Jesse Barnesb24e7172011-01-04 15:09:30 -08002126 /*
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2129 * need the check.
2130 */
Imre Deak50360402015-01-16 00:55:16 -08002131 if (HAS_GMCH_DISPLAY(dev_priv->dev))
Jani Nikulaa65347b2015-11-27 12:21:46 +02002132 if (crtc->config->has_dsi_encoder)
Jani Nikula23538ef2013-08-27 15:12:22 +03002133 assert_dsi_pll_enabled(dev_priv);
2134 else
2135 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002136 else {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002137 if (crtc->config->has_pch_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002138 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02002139 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01002140 assert_fdi_tx_pll_enabled(dev_priv,
2141 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08002142 }
2143 /* FIXME: assert CPU port conditions for SNB+ */
2144 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08002145
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002146 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002147 val = I915_READ(reg);
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002148 if (val & PIPECONF_ENABLE) {
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002149 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
Chris Wilson00d70b12011-03-17 07:18:29 +00002151 return;
Paulo Zanoni7ad25d42014-01-17 13:51:13 -02002152 }
Chris Wilson00d70b12011-03-17 07:18:29 +00002153
2154 I915_WRITE(reg, val | PIPECONF_ENABLE);
Paulo Zanoni851855d2013-12-19 19:12:29 -02002155 POSTING_READ(reg);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002156}
2157
2158/**
Chris Wilson309cfea2011-01-28 13:54:53 +00002159 * intel_disable_pipe - disable a pipe, asserting requirements
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002160 * @crtc: crtc whose pipes is to be disabled
Jesse Barnesb24e7172011-01-04 15:09:30 -08002161 *
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
Jesse Barnesb24e7172011-01-04 15:09:30 -08002165 *
2166 * Will wait until the pipe has shut down before returning.
2167 */
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002168static void intel_disable_pipe(struct intel_crtc *crtc)
Jesse Barnesb24e7172011-01-04 15:09:30 -08002169{
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002171 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03002172 enum pipe pipe = crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002173 i915_reg_t reg;
Jesse Barnesb24e7172011-01-04 15:09:30 -08002174 u32 val;
2175
Ville Syrjälä9e2ee2d2015-06-24 21:59:35 +03002176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
Jesse Barnesb24e7172011-01-04 15:09:30 -08002178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03002183 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07002184 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002185
Paulo Zanoni702e7a52012-10-23 18:29:59 -02002186 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002187 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00002188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
Ville Syrjälä67adc642014-08-15 01:21:57 +03002191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002195 if (crtc->config->double_wide)
Ville Syrjälä67adc642014-08-15 01:21:57 +03002196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03002199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
Ville Syrjälä67adc642014-08-15 01:21:57 +03002201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002206}
2207
Chris Wilson693db182013-03-05 14:52:39 +00002208static bool need_vtd_wa(struct drm_device *dev)
2209{
2210#ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212 return true;
2213#endif
2214 return false;
2215}
2216
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002217unsigned int
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002218intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +01002219 uint64_t fb_format_modifier, unsigned int plane)
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002220{
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002221 unsigned int tile_height;
2222 uint32_t pixel_bytes;
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002223
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002224 switch (fb_format_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 tile_height = 1;
2227 break;
2228 case I915_FORMAT_MOD_X_TILED:
2229 tile_height = IS_GEN2(dev) ? 16 : 8;
2230 break;
2231 case I915_FORMAT_MOD_Y_TILED:
2232 tile_height = 32;
2233 break;
2234 case I915_FORMAT_MOD_Yf_TILED:
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +01002235 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002236 switch (pixel_bytes) {
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002237 default:
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002238 case 1:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002239 tile_height = 64;
2240 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002241 case 2:
2242 case 4:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002243 tile_height = 32;
2244 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002245 case 8:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002246 tile_height = 16;
2247 break;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002248 case 16:
Damien Lespiaub5d0e9b2015-02-27 11:15:19 +00002249 WARN_ONCE(1,
2250 "128-bit pixels are not supported for display!");
2251 tile_height = 16;
2252 break;
2253 }
2254 break;
2255 default:
2256 MISSING_CASE(fb_format_modifier);
2257 tile_height = 1;
2258 break;
2259 }
Daniel Vetter091df6c2015-02-10 17:16:10 +00002260
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00002261 return tile_height;
2262}
2263
2264unsigned int
2265intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266 uint32_t pixel_format, uint64_t fb_format_modifier)
2267{
2268 return ALIGN(height, intel_tile_height(dev, pixel_format,
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +01002269 fb_format_modifier, 0));
Jesse Barnesa57ce0b2014-02-07 12:10:35 -08002270}
2271
Daniel Vetter75c82a52015-10-14 16:51:04 +02002272static void
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002273intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274 const struct drm_plane_state *plane_state)
2275{
Daniel Vettera6d09182015-10-14 16:51:05 +02002276 struct intel_rotation_info *info = &view->params.rotation_info;
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002277 unsigned int tile_height, tile_pitch;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002278
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002279 *view = i915_ggtt_view_normal;
2280
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002281 if (!plane_state)
Daniel Vetter75c82a52015-10-14 16:51:04 +02002282 return;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002283
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002284 if (!intel_rotation_90_or_270(plane_state->rotation))
Daniel Vetter75c82a52015-10-14 16:51:04 +02002285 return;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002286
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02002287 *view = i915_ggtt_view_rotated;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002288
2289 info->height = fb->height;
2290 info->pixel_format = fb->pixel_format;
2291 info->pitch = fb->pitches[0];
Tvrtko Ursulin89e3e142015-09-21 10:45:34 +01002292 info->uv_offset = fb->offsets[1];
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002293 info->fb_modifier = fb->modifier[0];
2294
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002295 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +01002296 fb->modifier[0], 0);
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002297 tile_pitch = PAGE_SIZE / tile_height;
2298 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
Tvrtko Ursulin89e3e142015-09-21 10:45:34 +01002302 if (info->pixel_format == DRM_FORMAT_NV12) {
2303 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 fb->modifier[0], 1);
2305 tile_pitch = PAGE_SIZE / tile_height;
2306 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308 tile_height);
2309 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310 PAGE_SIZE;
2311 }
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002312}
2313
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002314static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315{
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
Ville Syrjälä985b8bb2015-06-11 16:31:15 +03002318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
Wayne Boyer666a4532015-12-09 12:29:35 -08002319 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
Ville Syrjälä44c59052015-06-11 16:31:16 +03002324 return 0;
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002325}
2326
Chris Wilson127bd2a2010-07-23 23:32:05 +01002327int
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002328intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
Maarten Lankhorst7580d772015-08-18 13:40:06 +02002330 const struct drm_plane_state *plane_state)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002331{
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002332 struct drm_device *dev = fb->dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002333 struct drm_i915_private *dev_priv = dev->dev_private;
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00002334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002335 struct i915_ggtt_view view;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002336 u32 alignment;
2337 int ret;
2338
Matt Roperebcdd392014-07-09 16:22:11 -07002339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2340
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002343 alignment = intel_linear_alignment(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002344 break;
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002345 case I915_FORMAT_MOD_X_TILED:
Damien Lespiau1fada4c2013-07-03 21:06:02 +01002346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else {
2349 /* pin() will align the object as required by fence */
2350 alignment = 0;
2351 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002352 break;
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002353 case I915_FORMAT_MOD_Y_TILED:
Damien Lespiau1327b9a2015-02-27 11:15:20 +00002354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2357 return -EINVAL;
2358 alignment = 1 * 1024 * 1024;
2359 break;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002360 default:
Tvrtko Ursulin7b911ad2015-02-10 17:16:15 +00002361 MISSING_CASE(fb->modifier[0]);
2362 return -EINVAL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002363 }
2364
Daniel Vetter75c82a52015-10-14 16:51:04 +02002365 intel_fill_fb_ggtt_view(&view, fb, plane_state);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002366
Chris Wilson693db182013-03-05 14:52:39 +00002367 /* Note that the w/a also requires 64 PTE of padding following the
2368 * bo. We currently fill all unused PTE with the shadow page and so
2369 * we should always have valid PTE following the scanout preventing
2370 * the VT-d warning.
2371 */
2372 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2373 alignment = 256 * 1024;
2374
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002375 /*
2376 * Global gtt pte registers are special registers which actually forward
2377 * writes to a chunk of system memory. Which means that there is no risk
2378 * that the register values disappear as soon as we call
2379 * intel_runtime_pm_put(), so it is correct to wrap only the
2380 * pin/unpin/fence and not more.
2381 */
2382 intel_runtime_pm_get(dev_priv);
2383
Maarten Lankhorst7580d772015-08-18 13:40:06 +02002384 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2385 &view);
Chris Wilson48b956c2010-09-14 12:50:34 +01002386 if (ret)
Maarten Lankhorstb26a6b32015-09-23 13:27:09 +02002387 goto err_pm;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002388
2389 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2390 * fence, whereas 965+ only requires a fence if using
2391 * framebuffer compression. For simplicity, we always install
2392 * a fence as the cost is not that onerous.
2393 */
Vivek Kasireddy98072162015-10-29 18:54:38 -07002394 if (view.type == I915_GGTT_VIEW_NORMAL) {
2395 ret = i915_gem_object_get_fence(obj);
2396 if (ret == -EDEADLK) {
2397 /*
2398 * -EDEADLK means there are no free fences
2399 * no pending flips.
2400 *
2401 * This is propagated to atomic, but it uses
2402 * -EDEADLK to force a locking recovery, so
2403 * change the returned error to -EBUSY.
2404 */
2405 ret = -EBUSY;
2406 goto err_unpin;
2407 } else if (ret)
2408 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01002409
Vivek Kasireddy98072162015-10-29 18:54:38 -07002410 i915_gem_object_pin_fence(obj);
2411 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002412
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002413 intel_runtime_pm_put(dev_priv);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002414 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002415
2416err_unpin:
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002417 i915_gem_object_unpin_from_display_plane(obj, &view);
Maarten Lankhorstb26a6b32015-09-23 13:27:09 +02002418err_pm:
Paulo Zanonid6dd6842014-08-15 15:59:32 -03002419 intel_runtime_pm_put(dev_priv);
Chris Wilson48b956c2010-09-14 12:50:34 +01002420 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002421}
2422
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002423static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
Chris Wilson1690e1e2011-12-14 13:57:08 +01002425{
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002427 struct i915_ggtt_view view;
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00002428
Matt Roperebcdd392014-07-09 16:22:11 -07002429 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2430
Daniel Vetter75c82a52015-10-14 16:51:04 +02002431 intel_fill_fb_ggtt_view(&view, fb, plane_state);
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002432
Vivek Kasireddy98072162015-10-29 18:54:38 -07002433 if (view.type == I915_GGTT_VIEW_NORMAL)
2434 i915_gem_object_unpin_fence(obj);
2435
Tvrtko Ursulinf64b98c2015-03-23 11:10:35 +00002436 i915_gem_object_unpin_from_display_plane(obj, &view);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002437}
2438
Daniel Vetterc2c75132012-07-05 12:17:30 +02002439/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002441unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442 int *x, int *y,
Chris Wilsonbc752862013-02-21 20:04:31 +00002443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002446{
Chris Wilsonbc752862013-02-21 20:04:31 +00002447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002449
Chris Wilsonbc752862013-02-21 20:04:31 +00002450 tile_rows = *y / 8;
2451 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002452
Chris Wilsonbc752862013-02-21 20:04:31 +00002453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
Chris Wilsonbc752862013-02-21 20:04:31 +00002459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
Chris Wilsonbc752862013-02-21 20:04:31 +00002465 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002466}
2467
Damien Lespiaub35d63f2015-01-20 12:51:50 +00002468static int i9xx_format_to_fourcc(int format)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002469{
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487}
2488
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00002489static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490{
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513}
2514
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002515static bool
Daniel Vetterf6936e22015-03-26 12:17:05 +01002516intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
Jesse Barnes46f297f2014-03-07 08:57:48 -08002518{
2519 struct drm_device *dev = crtc->base.dev;
Paulo Zanoni3badb492015-09-23 12:52:23 -03002520 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002521 struct drm_i915_gem_object *obj = NULL;
2522 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Damien Lespiau2d140302015-02-05 17:22:18 +00002523 struct drm_framebuffer *fb = &plane_config->fb->base;
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002524 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2525 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2526 PAGE_SIZE);
2527
2528 size_aligned -= base_aligned;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002529
Chris Wilsonff2652e2014-03-10 08:07:02 +00002530 if (plane_config->size == 0)
2531 return false;
2532
Paulo Zanoni3badb492015-09-23 12:52:23 -03002533 /* If the FB is too big, just don't use it since fbdev is not very
2534 * important and we should probably use that space with FBC or other
2535 * features. */
2536 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2537 return false;
2538
Daniel Vetterf37b5c22015-02-10 23:12:27 +01002539 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2540 base_aligned,
2541 base_aligned,
2542 size_aligned);
Jesse Barnes46f297f2014-03-07 08:57:48 -08002543 if (!obj)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002544 return false;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002545
Damien Lespiau49af4492015-01-20 12:51:44 +00002546 obj->tiling_mode = plane_config->tiling;
2547 if (obj->tiling_mode == I915_TILING_X)
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002548 obj->stride = fb->pitches[0];
Jesse Barnes46f297f2014-03-07 08:57:48 -08002549
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002550 mode_cmd.pixel_format = fb->pixel_format;
2551 mode_cmd.width = fb->width;
2552 mode_cmd.height = fb->height;
2553 mode_cmd.pitches[0] = fb->pitches[0];
Daniel Vetter18c52472015-02-10 17:16:09 +00002554 mode_cmd.modifier[0] = fb->modifier[0];
2555 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002556
2557 mutex_lock(&dev->struct_mutex);
Damien Lespiau6bf129d2015-02-05 17:22:16 +00002558 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
Jesse Barnes484b41d2014-03-07 08:57:55 -08002559 &mode_cmd, obj)) {
Jesse Barnes46f297f2014-03-07 08:57:48 -08002560 DRM_DEBUG_KMS("intel fb init failed\n");
2561 goto out_unref_obj;
2562 }
Jesse Barnes46f297f2014-03-07 08:57:48 -08002563 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002564
Daniel Vetterf6936e22015-03-26 12:17:05 +01002565 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002566 return true;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002567
2568out_unref_obj:
2569 drm_gem_object_unreference(&obj->base);
2570 mutex_unlock(&dev->struct_mutex);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002571 return false;
2572}
2573
Matt Roperafd65eb2015-02-03 13:10:04 -08002574/* Update plane->state->fb to match plane->fb after driver-internal updates */
2575static void
2576update_state_fb(struct drm_plane *plane)
2577{
2578 if (plane->fb == plane->state->fb)
2579 return;
2580
2581 if (plane->state->fb)
2582 drm_framebuffer_unreference(plane->state->fb);
2583 plane->state->fb = plane->fb;
2584 if (plane->state->fb)
2585 drm_framebuffer_reference(plane->state->fb);
2586}
2587
Damien Lespiau5724dbd2015-01-20 12:51:52 +00002588static void
Daniel Vetterf6936e22015-03-26 12:17:05 +01002589intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2590 struct intel_initial_plane_config *plane_config)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002591{
2592 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnesd9ceb812014-10-09 12:57:43 -07002593 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002594 struct drm_crtc *c;
2595 struct intel_crtc *i;
Matt Roper2ff8fde2014-07-08 07:50:07 -07002596 struct drm_i915_gem_object *obj;
Daniel Vetter88595ac2015-03-26 12:42:24 +01002597 struct drm_plane *primary = intel_crtc->base.primary;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002598 struct drm_plane_state *plane_state = primary->state;
Matt Roper200757f2015-12-03 11:37:36 -08002599 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2600 struct intel_plane *intel_plane = to_intel_plane(primary);
Daniel Vetter88595ac2015-03-26 12:42:24 +01002601 struct drm_framebuffer *fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002602
Damien Lespiau2d140302015-02-05 17:22:18 +00002603 if (!plane_config->fb)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002604 return;
2605
Daniel Vetterf6936e22015-03-26 12:17:05 +01002606 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002607 fb = &plane_config->fb->base;
2608 goto valid_fb;
Damien Lespiauf55548b2015-02-05 18:30:20 +00002609 }
Jesse Barnes484b41d2014-03-07 08:57:55 -08002610
Damien Lespiau2d140302015-02-05 17:22:18 +00002611 kfree(plane_config->fb);
Jesse Barnes484b41d2014-03-07 08:57:55 -08002612
2613 /*
2614 * Failed to alloc the obj, check to see if we should share
2615 * an fb with another CRTC instead
2616 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01002617 for_each_crtc(dev, c) {
Jesse Barnes484b41d2014-03-07 08:57:55 -08002618 i = to_intel_crtc(c);
2619
2620 if (c == &intel_crtc->base)
2621 continue;
2622
Matt Roper2ff8fde2014-07-08 07:50:07 -07002623 if (!i->active)
Jesse Barnes484b41d2014-03-07 08:57:55 -08002624 continue;
2625
Daniel Vetter88595ac2015-03-26 12:42:24 +01002626 fb = c->primary->fb;
2627 if (!fb)
Matt Roper2ff8fde2014-07-08 07:50:07 -07002628 continue;
2629
Daniel Vetter88595ac2015-03-26 12:42:24 +01002630 obj = intel_fb_obj(fb);
Matt Roper2ff8fde2014-07-08 07:50:07 -07002631 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
Daniel Vetter88595ac2015-03-26 12:42:24 +01002632 drm_framebuffer_reference(fb);
2633 goto valid_fb;
Jesse Barnes484b41d2014-03-07 08:57:55 -08002634 }
2635 }
Daniel Vetter88595ac2015-03-26 12:42:24 +01002636
Matt Roper200757f2015-12-03 11:37:36 -08002637 /*
2638 * We've failed to reconstruct the BIOS FB. Current display state
2639 * indicates that the primary plane is visible, but has a NULL FB,
2640 * which will lead to problems later if we don't fix it up. The
2641 * simplest solution is to just disable the primary plane now and
2642 * pretend the BIOS never had it enabled.
2643 */
2644 to_intel_plane_state(plane_state)->visible = false;
2645 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2646 intel_pre_disable_primary(&intel_crtc->base);
2647 intel_plane->disable_plane(primary, &intel_crtc->base);
2648
Daniel Vetter88595ac2015-03-26 12:42:24 +01002649 return;
2650
2651valid_fb:
Ville Syrjäläf44e2652015-11-13 19:16:13 +02002652 plane_state->src_x = 0;
2653 plane_state->src_y = 0;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002654 plane_state->src_w = fb->width << 16;
2655 plane_state->src_h = fb->height << 16;
2656
Ville Syrjäläf44e2652015-11-13 19:16:13 +02002657 plane_state->crtc_x = 0;
2658 plane_state->crtc_y = 0;
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002659 plane_state->crtc_w = fb->width;
2660 plane_state->crtc_h = fb->height;
2661
Daniel Vetter88595ac2015-03-26 12:42:24 +01002662 obj = intel_fb_obj(fb);
2663 if (obj->tiling_mode != I915_TILING_NONE)
2664 dev_priv->preserve_bios_swizzle = true;
2665
Maarten Lankhorstbe5651f2015-07-13 16:30:18 +02002666 drm_framebuffer_reference(fb);
2667 primary->fb = primary->state->fb = fb;
Maarten Lankhorst36750f22015-06-01 12:49:54 +02002668 primary->crtc = primary->state->crtc = &intel_crtc->base;
Maarten Lankhorst36750f22015-06-01 12:49:54 +02002669 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
Ville Syrjäläa9ff8712015-06-24 21:59:34 +03002670 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
Jesse Barnes46f297f2014-03-07 08:57:48 -08002671}
2672
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002673static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2674 struct drm_framebuffer *fb,
2675 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002676{
2677 struct drm_device *dev = crtc->dev;
2678 struct drm_i915_private *dev_priv = dev->dev_private;
2679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002680 struct drm_plane *primary = crtc->primary;
2681 bool visible = to_intel_plane_state(primary->state)->visible;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002682 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002683 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002684 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002685 u32 dspcntr;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002686 i915_reg_t reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302687 int pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002688
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002689 if (!visible || !fb) {
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002690 I915_WRITE(reg, 0);
2691 if (INTEL_INFO(dev)->gen >= 4)
2692 I915_WRITE(DSPSURF(plane), 0);
2693 else
2694 I915_WRITE(DSPADDR(plane), 0);
2695 POSTING_READ(reg);
2696 return;
2697 }
2698
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002699 obj = intel_fb_obj(fb);
2700 if (WARN_ON(obj == NULL))
2701 return;
2702
2703 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2704
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002705 dspcntr = DISPPLANE_GAMMA_ENABLE;
2706
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002707 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002708
2709 if (INTEL_INFO(dev)->gen < 4) {
2710 if (intel_crtc->pipe == PIPE_B)
2711 dspcntr |= DISPPLANE_SEL_PIPE_B;
2712
2713 /* pipesrc and dspsize control the size that is scaled from,
2714 * which should always be the user's requested size.
2715 */
2716 I915_WRITE(DSPSIZE(plane),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002717 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2718 (intel_crtc->config->pipe_src_w - 1));
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002719 I915_WRITE(DSPPOS(plane), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002720 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2721 I915_WRITE(PRIMSIZE(plane),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
Ville Syrjäläc14b0482014-10-16 20:52:34 +03002724 I915_WRITE(PRIMPOS(plane), 0);
2725 I915_WRITE(PRIMCNSTALPHA(plane), 0);
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002726 }
2727
Ville Syrjälä57779d02012-10-31 17:50:14 +02002728 switch (fb->pixel_format) {
2729 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002730 dspcntr |= DISPPLANE_8BPP;
2731 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002732 case DRM_FORMAT_XRGB1555:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002733 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002734 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002735 case DRM_FORMAT_RGB565:
2736 dspcntr |= DISPPLANE_BGRX565;
2737 break;
2738 case DRM_FORMAT_XRGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002739 dspcntr |= DISPPLANE_BGRX888;
2740 break;
2741 case DRM_FORMAT_XBGR8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002742 dspcntr |= DISPPLANE_RGBX888;
2743 break;
2744 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002745 dspcntr |= DISPPLANE_BGRX101010;
2746 break;
2747 case DRM_FORMAT_XBGR2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002748 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002749 break;
2750 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002751 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002752 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002753
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002754 if (INTEL_INFO(dev)->gen >= 4 &&
2755 obj->tiling_mode != I915_TILING_NONE)
2756 dspcntr |= DISPPLANE_TILED;
Jesse Barnes81255562010-08-02 12:07:50 -07002757
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002758 if (IS_G4X(dev))
2759 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2760
Ville Syrjäläb98971272014-08-27 16:51:22 +03002761 linear_offset = y * fb->pitches[0] + x * pixel_size;
Jesse Barnes81255562010-08-02 12:07:50 -07002762
Daniel Vetterc2c75132012-07-05 12:17:30 +02002763 if (INTEL_INFO(dev)->gen >= 4) {
2764 intel_crtc->dspaddr_offset =
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002765 intel_gen4_compute_page_offset(dev_priv,
2766 &x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002767 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002768 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002769 linear_offset -= intel_crtc->dspaddr_offset;
2770 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002771 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002772 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002773
Matt Roper8e7d6882015-01-21 16:35:41 -08002774 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Sonika Jindal48404c12014-08-22 14:06:04 +05302775 dspcntr |= DISPPLANE_ROTATE_180;
2776
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002777 x += (intel_crtc->config->pipe_src_w - 1);
2778 y += (intel_crtc->config->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05302779
2780 /* Finding the last pixel of the last line of the display
2781 data and adding to linear_offset*/
2782 linear_offset +=
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002783 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2784 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
Sonika Jindal48404c12014-08-22 14:06:04 +05302785 }
2786
Paulo Zanoni2db33662015-09-14 15:20:03 -03002787 intel_crtc->adjusted_x = x;
2788 intel_crtc->adjusted_y = y;
2789
Sonika Jindal48404c12014-08-22 14:06:04 +05302790 I915_WRITE(reg, dspcntr);
2791
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002792 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002793 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002794 I915_WRITE(DSPSURF(plane),
2795 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002796 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002797 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002798 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002799 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002800 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002801}
2802
Daniel Vetter29b9bde2014-04-24 23:55:01 +02002803static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2804 struct drm_framebuffer *fb,
2805 int x, int y)
Jesse Barnes17638cd2011-06-24 12:19:23 -07002806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002810 struct drm_plane *primary = crtc->primary;
2811 bool visible = to_intel_plane_state(primary->state)->visible;
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002812 struct drm_i915_gem_object *obj;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002813 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002814 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002815 u32 dspcntr;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02002816 i915_reg_t reg = DSPCNTR(plane);
Sonika Jindal48404c12014-08-22 14:06:04 +05302817 int pixel_size;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002818
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03002819 if (!visible || !fb) {
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002820 I915_WRITE(reg, 0);
2821 I915_WRITE(DSPSURF(plane), 0);
2822 POSTING_READ(reg);
2823 return;
2824 }
2825
Ville Syrjäläc9ba6fa2014-08-27 17:48:41 +03002826 obj = intel_fb_obj(fb);
2827 if (WARN_ON(obj == NULL))
2828 return;
2829
2830 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2831
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002832 dspcntr = DISPPLANE_GAMMA_ENABLE;
2833
Ville Syrjäläfdd508a2014-08-08 21:51:11 +03002834 dspcntr |= DISPLAY_PLANE_ENABLE;
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002835
2836 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2837 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2838
Ville Syrjälä57779d02012-10-31 17:50:14 +02002839 switch (fb->pixel_format) {
2840 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002841 dspcntr |= DISPPLANE_8BPP;
2842 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002843 case DRM_FORMAT_RGB565:
2844 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002845 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002846 case DRM_FORMAT_XRGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002847 dspcntr |= DISPPLANE_BGRX888;
2848 break;
2849 case DRM_FORMAT_XBGR8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002850 dspcntr |= DISPPLANE_RGBX888;
2851 break;
2852 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002853 dspcntr |= DISPPLANE_BGRX101010;
2854 break;
2855 case DRM_FORMAT_XBGR2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002856 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002857 break;
2858 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002859 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002860 }
2861
2862 if (obj->tiling_mode != I915_TILING_NONE)
2863 dspcntr |= DISPPLANE_TILED;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002864
Ville Syrjäläf45651b2014-08-08 21:51:10 +03002865 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002866 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002867
Ville Syrjäläb98971272014-08-27 16:51:22 +03002868 linear_offset = y * fb->pitches[0] + x * pixel_size;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002869 intel_crtc->dspaddr_offset =
Ville Syrjälä4e9a86b2015-06-11 16:31:14 +03002870 intel_gen4_compute_page_offset(dev_priv,
2871 &x, &y, obj->tiling_mode,
Ville Syrjäläb98971272014-08-27 16:51:22 +03002872 pixel_size,
Chris Wilsonbc752862013-02-21 20:04:31 +00002873 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002874 linear_offset -= intel_crtc->dspaddr_offset;
Matt Roper8e7d6882015-01-21 16:35:41 -08002875 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
Sonika Jindal48404c12014-08-22 14:06:04 +05302876 dspcntr |= DISPPLANE_ROTATE_180;
2877
2878 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002879 x += (intel_crtc->config->pipe_src_w - 1);
2880 y += (intel_crtc->config->pipe_src_h - 1);
Sonika Jindal48404c12014-08-22 14:06:04 +05302881
2882 /* Finding the last pixel of the last line of the display
2883 data and adding to linear_offset*/
2884 linear_offset +=
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02002885 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2886 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
Sonika Jindal48404c12014-08-22 14:06:04 +05302887 }
2888 }
2889
Paulo Zanoni2db33662015-09-14 15:20:03 -03002890 intel_crtc->adjusted_x = x;
2891 intel_crtc->adjusted_y = y;
2892
Sonika Jindal48404c12014-08-22 14:06:04 +05302893 I915_WRITE(reg, dspcntr);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002894
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002895 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetter85ba7b72014-01-24 10:31:44 +01002896 I915_WRITE(DSPSURF(plane),
2897 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002898 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002899 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2900 } else {
2901 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2902 I915_WRITE(DSPLINOFF(plane), linear_offset);
2903 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002904 POSTING_READ(reg);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002905}
2906
Damien Lespiaub3218032015-02-27 11:15:18 +00002907u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2908 uint32_t pixel_format)
2909{
2910 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2911
2912 /*
2913 * The stride is either expressed as a multiple of 64 bytes
2914 * chunks for linear buffers or in number of tiles for tiled
2915 * buffers.
2916 */
2917 switch (fb_modifier) {
2918 case DRM_FORMAT_MOD_NONE:
2919 return 64;
2920 case I915_FORMAT_MOD_X_TILED:
2921 if (INTEL_INFO(dev)->gen == 2)
2922 return 128;
2923 return 512;
2924 case I915_FORMAT_MOD_Y_TILED:
2925 /* No need to check for old gens and Y tiling since this is
2926 * about the display engine and those will be blocked before
2927 * we get here.
2928 */
2929 return 128;
2930 case I915_FORMAT_MOD_Yf_TILED:
2931 if (bits_per_pixel == 8)
2932 return 64;
2933 else
2934 return 128;
2935 default:
2936 MISSING_CASE(fb_modifier);
2937 return 64;
2938 }
2939}
2940
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +02002941u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2942 struct drm_i915_gem_object *obj,
2943 unsigned int plane)
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002944{
Daniel Vetterce7f1722015-10-14 16:51:06 +02002945 struct i915_ggtt_view view;
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01002946 struct i915_vma *vma;
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +02002947 u64 offset;
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002948
Daniel Vetterce7f1722015-10-14 16:51:06 +02002949 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2950 intel_plane->base.state);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002951
Daniel Vetterce7f1722015-10-14 16:51:06 +02002952 vma = i915_gem_obj_to_ggtt_view(obj, &view);
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01002953 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
Daniel Vetterce7f1722015-10-14 16:51:06 +02002954 view.type))
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01002955 return -1;
2956
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +02002957 offset = vma->node.start;
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01002958
2959 if (plane == 1) {
Daniel Vettera6d09182015-10-14 16:51:05 +02002960 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01002961 PAGE_SIZE;
2962 }
2963
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +02002964 WARN_ON(upper_32_bits(offset));
2965
2966 return lower_32_bits(offset);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00002967}
2968
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02002969static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2970{
2971 struct drm_device *dev = intel_crtc->base.dev;
2972 struct drm_i915_private *dev_priv = dev->dev_private;
2973
2974 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2975 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2976 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02002977}
2978
Chandra Kondurua1b22782015-04-07 15:28:45 -07002979/*
2980 * This function detaches (aka. unbinds) unused scalers in hardware
2981 */
Maarten Lankhorst05832362015-06-15 12:33:48 +02002982static void skl_detach_scalers(struct intel_crtc *intel_crtc)
Chandra Kondurua1b22782015-04-07 15:28:45 -07002983{
Chandra Kondurua1b22782015-04-07 15:28:45 -07002984 struct intel_crtc_scaler_state *scaler_state;
2985 int i;
2986
Chandra Kondurua1b22782015-04-07 15:28:45 -07002987 scaler_state = &intel_crtc->config->scaler_state;
2988
2989 /* loop through and disable scalers that aren't in use */
2990 for (i = 0; i < intel_crtc->num_scalers; i++) {
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02002991 if (!scaler_state->scalers[i].in_use)
2992 skl_detach_scaler(intel_crtc, i);
Chandra Kondurua1b22782015-04-07 15:28:45 -07002993 }
2994}
2995
Chandra Konduru6156a452015-04-27 13:48:39 -07002996u32 skl_plane_ctl_format(uint32_t pixel_format)
2997{
Chandra Konduru6156a452015-04-27 13:48:39 -07002998 switch (pixel_format) {
Damien Lespiaud161cf72015-05-12 16:13:17 +01002999 case DRM_FORMAT_C8:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003000 return PLANE_CTL_FORMAT_INDEXED;
Chandra Konduru6156a452015-04-27 13:48:39 -07003001 case DRM_FORMAT_RGB565:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003002 return PLANE_CTL_FORMAT_RGB_565;
Chandra Konduru6156a452015-04-27 13:48:39 -07003003 case DRM_FORMAT_XBGR8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003004 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
Chandra Konduru6156a452015-04-27 13:48:39 -07003005 case DRM_FORMAT_XRGB8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003006 return PLANE_CTL_FORMAT_XRGB_8888;
Chandra Konduru6156a452015-04-27 13:48:39 -07003007 /*
3008 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3009 * to be already pre-multiplied. We need to add a knob (or a different
3010 * DRM_FORMAT) for user-space to configure that.
3011 */
3012 case DRM_FORMAT_ABGR8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003013 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
Chandra Konduru6156a452015-04-27 13:48:39 -07003014 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003015 case DRM_FORMAT_ARGB8888:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003016 return PLANE_CTL_FORMAT_XRGB_8888 |
Chandra Konduru6156a452015-04-27 13:48:39 -07003017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003018 case DRM_FORMAT_XRGB2101010:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003019 return PLANE_CTL_FORMAT_XRGB_2101010;
Chandra Konduru6156a452015-04-27 13:48:39 -07003020 case DRM_FORMAT_XBGR2101010:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003021 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
Chandra Konduru6156a452015-04-27 13:48:39 -07003022 case DRM_FORMAT_YUYV:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003023 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
Chandra Konduru6156a452015-04-27 13:48:39 -07003024 case DRM_FORMAT_YVYU:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003025 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
Chandra Konduru6156a452015-04-27 13:48:39 -07003026 case DRM_FORMAT_UYVY:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003027 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003028 case DRM_FORMAT_VYUY:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003029 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
Chandra Konduru6156a452015-04-27 13:48:39 -07003030 default:
Damien Lespiau4249eee2015-05-12 16:13:16 +01003031 MISSING_CASE(pixel_format);
Chandra Konduru6156a452015-04-27 13:48:39 -07003032 }
Damien Lespiau8cfcba42015-05-12 16:13:14 +01003033
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003034 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003035}
3036
3037u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3038{
Chandra Konduru6156a452015-04-27 13:48:39 -07003039 switch (fb_modifier) {
3040 case DRM_FORMAT_MOD_NONE:
3041 break;
3042 case I915_FORMAT_MOD_X_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003043 return PLANE_CTL_TILED_X;
Chandra Konduru6156a452015-04-27 13:48:39 -07003044 case I915_FORMAT_MOD_Y_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003045 return PLANE_CTL_TILED_Y;
Chandra Konduru6156a452015-04-27 13:48:39 -07003046 case I915_FORMAT_MOD_Yf_TILED:
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003047 return PLANE_CTL_TILED_YF;
Chandra Konduru6156a452015-04-27 13:48:39 -07003048 default:
3049 MISSING_CASE(fb_modifier);
3050 }
Damien Lespiau8cfcba42015-05-12 16:13:14 +01003051
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003052 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003053}
3054
3055u32 skl_plane_ctl_rotation(unsigned int rotation)
3056{
Chandra Konduru6156a452015-04-27 13:48:39 -07003057 switch (rotation) {
3058 case BIT(DRM_ROTATE_0):
3059 break;
Sonika Jindal1e8df162015-05-20 13:40:48 +05303060 /*
3061 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3062 * while i915 HW rotation is clockwise, thats why this swapping.
3063 */
Chandra Konduru6156a452015-04-27 13:48:39 -07003064 case BIT(DRM_ROTATE_90):
Sonika Jindal1e8df162015-05-20 13:40:48 +05303065 return PLANE_CTL_ROTATE_270;
Chandra Konduru6156a452015-04-27 13:48:39 -07003066 case BIT(DRM_ROTATE_180):
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003067 return PLANE_CTL_ROTATE_180;
Chandra Konduru6156a452015-04-27 13:48:39 -07003068 case BIT(DRM_ROTATE_270):
Sonika Jindal1e8df162015-05-20 13:40:48 +05303069 return PLANE_CTL_ROTATE_90;
Chandra Konduru6156a452015-04-27 13:48:39 -07003070 default:
3071 MISSING_CASE(rotation);
3072 }
3073
Damien Lespiauc34ce3d2015-05-15 15:07:02 +01003074 return 0;
Chandra Konduru6156a452015-04-27 13:48:39 -07003075}
3076
Damien Lespiau70d21f02013-07-03 21:06:04 +01003077static void skylake_update_primary_plane(struct drm_crtc *crtc,
3078 struct drm_framebuffer *fb,
3079 int x, int y)
3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03003084 struct drm_plane *plane = crtc->primary;
3085 bool visible = to_intel_plane_state(plane->state)->visible;
Damien Lespiau70d21f02013-07-03 21:06:04 +01003086 struct drm_i915_gem_object *obj;
3087 int pipe = intel_crtc->pipe;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303088 u32 plane_ctl, stride_div, stride;
3089 u32 tile_height, plane_offset, plane_size;
3090 unsigned int rotation;
3091 int x_offset, y_offset;
Mika Kuoppala44eb0cb2015-10-30 13:26:15 +02003092 u32 surf_addr;
Chandra Konduru6156a452015-04-27 13:48:39 -07003093 struct intel_crtc_state *crtc_state = intel_crtc->config;
3094 struct intel_plane_state *plane_state;
3095 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3096 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3097 int scaler_id = -1;
3098
Chandra Konduru6156a452015-04-27 13:48:39 -07003099 plane_state = to_intel_plane_state(plane->state);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003100
Maarten Lankhorstb70709a2015-04-21 17:12:53 +03003101 if (!visible || !fb) {
Damien Lespiau70d21f02013-07-03 21:06:04 +01003102 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3103 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3104 POSTING_READ(PLANE_CTL(pipe, 0));
3105 return;
3106 }
3107
3108 plane_ctl = PLANE_CTL_ENABLE |
3109 PLANE_CTL_PIPE_GAMMA_ENABLE |
3110 PLANE_CTL_PIPE_CSC_ENABLE;
3111
Chandra Konduru6156a452015-04-27 13:48:39 -07003112 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3113 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003114 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303115
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303116 rotation = plane->state->rotation;
Chandra Konduru6156a452015-04-27 13:48:39 -07003117 plane_ctl |= skl_plane_ctl_rotation(rotation);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003118
Damien Lespiaub3218032015-02-27 11:15:18 +00003119 obj = intel_fb_obj(fb);
3120 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3121 fb->pixel_format);
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01003122 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303123
Paulo Zanonia42e5a22015-09-30 17:05:43 -03003124 WARN_ON(drm_rect_width(&plane_state->src) == 0);
Chandra Konduru6156a452015-04-27 13:48:39 -07003125
Paulo Zanonia42e5a22015-09-30 17:05:43 -03003126 scaler_id = plane_state->scaler_id;
3127 src_x = plane_state->src.x1 >> 16;
3128 src_y = plane_state->src.y1 >> 16;
3129 src_w = drm_rect_width(&plane_state->src) >> 16;
3130 src_h = drm_rect_height(&plane_state->src) >> 16;
3131 dst_x = plane_state->dst.x1;
3132 dst_y = plane_state->dst.y1;
3133 dst_w = drm_rect_width(&plane_state->dst);
3134 dst_h = drm_rect_height(&plane_state->dst);
3135
3136 WARN_ON(x != src_x || y != src_y);
Chandra Konduru6156a452015-04-27 13:48:39 -07003137
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303138 if (intel_rotation_90_or_270(rotation)) {
3139 /* stride = Surface height in tiles */
Chandra Konduru2614f172015-05-08 20:22:46 -07003140 tile_height = intel_tile_height(dev, fb->pixel_format,
Tvrtko Ursulinfe47ea02015-09-21 10:45:32 +01003141 fb->modifier[0], 0);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303142 stride = DIV_ROUND_UP(fb->height, tile_height);
Chandra Konduru6156a452015-04-27 13:48:39 -07003143 x_offset = stride * tile_height - y - src_h;
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303144 y_offset = x;
Chandra Konduru6156a452015-04-27 13:48:39 -07003145 plane_size = (src_w - 1) << 16 | (src_h - 1);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303146 } else {
3147 stride = fb->pitches[0] / stride_div;
3148 x_offset = x;
3149 y_offset = y;
Chandra Konduru6156a452015-04-27 13:48:39 -07003150 plane_size = (src_h - 1) << 16 | (src_w - 1);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303151 }
3152 plane_offset = y_offset << 16 | x_offset;
Damien Lespiaub3218032015-02-27 11:15:18 +00003153
Paulo Zanoni2db33662015-09-14 15:20:03 -03003154 intel_crtc->adjusted_x = x_offset;
3155 intel_crtc->adjusted_y = y_offset;
3156
Damien Lespiau70d21f02013-07-03 21:06:04 +01003157 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
Sonika Jindal3b7a5112015-04-10 14:37:29 +05303158 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3159 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3160 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
Chandra Konduru6156a452015-04-27 13:48:39 -07003161
3162 if (scaler_id >= 0) {
3163 uint32_t ps_ctrl = 0;
3164
3165 WARN_ON(!dst_w || !dst_h);
3166 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3167 crtc_state->scaler_state.scalers[scaler_id].mode;
3168 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3169 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3170 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3171 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3172 I915_WRITE(PLANE_POS(pipe, 0), 0);
3173 } else {
3174 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3175 }
3176
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00003177 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
Damien Lespiau70d21f02013-07-03 21:06:04 +01003178
3179 POSTING_READ(PLANE_SURF(pipe, 0));
3180}
3181
Jesse Barnes17638cd2011-06-24 12:19:23 -07003182/* Assume fb object is pinned & idle & fenced and just update base pointers */
3183static int
3184intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3185 int x, int y, enum mode_set_atomic state)
3186{
3187 struct drm_device *dev = crtc->dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07003189
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03003190 if (dev_priv->fbc.deactivate)
3191 dev_priv->fbc.deactivate(dev_priv);
Jesse Barnes81255562010-08-02 12:07:50 -07003192
Daniel Vetter29b9bde2014-04-24 23:55:01 +02003193 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3194
3195 return 0;
Jesse Barnes81255562010-08-02 12:07:50 -07003196}
3197
Ville Syrjälä75147472014-11-24 18:28:11 +02003198static void intel_complete_page_flips(struct drm_device *dev)
Ville Syrjälä96a02912013-02-18 19:08:49 +02003199{
Ville Syrjälä96a02912013-02-18 19:08:49 +02003200 struct drm_crtc *crtc;
3201
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003202 for_each_crtc(dev, crtc) {
Ville Syrjälä96a02912013-02-18 19:08:49 +02003203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3204 enum plane plane = intel_crtc->plane;
3205
3206 intel_prepare_page_flip(dev, plane);
3207 intel_finish_page_flip_plane(dev, plane);
3208 }
Ville Syrjälä75147472014-11-24 18:28:11 +02003209}
3210
3211static void intel_update_primary_planes(struct drm_device *dev)
3212{
Ville Syrjälä75147472014-11-24 18:28:11 +02003213 struct drm_crtc *crtc;
Ville Syrjälä96a02912013-02-18 19:08:49 +02003214
Damien Lespiau70e1e0e2014-05-13 23:32:24 +01003215 for_each_crtc(dev, crtc) {
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003216 struct intel_plane *plane = to_intel_plane(crtc->primary);
3217 struct intel_plane_state *plane_state;
Ville Syrjälä96a02912013-02-18 19:08:49 +02003218
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003219 drm_modeset_lock_crtc(crtc, &plane->base);
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003220 plane_state = to_intel_plane_state(plane->base.state);
3221
Maarten Lankhorstf029ee82015-09-23 16:29:37 +02003222 if (crtc->state->active && plane_state->base.fb)
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003223 plane->commit_plane(&plane->base, plane_state);
3224
3225 drm_modeset_unlock_crtc(crtc);
Ville Syrjälä96a02912013-02-18 19:08:49 +02003226 }
3227}
3228
Ville Syrjälä75147472014-11-24 18:28:11 +02003229void intel_prepare_reset(struct drm_device *dev)
3230{
3231 /* no reset support for gen2 */
3232 if (IS_GEN2(dev))
3233 return;
3234
3235 /* reset doesn't touch the display */
3236 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3237 return;
3238
3239 drm_modeset_lock_all(dev);
Ville Syrjäläf98ce922014-11-21 21:54:30 +02003240 /*
3241 * Disabling the crtcs gracefully seems nicer. Also the
3242 * g33 docs say we should at least disable all the planes.
3243 */
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02003244 intel_display_suspend(dev);
Ville Syrjälä75147472014-11-24 18:28:11 +02003245}
3246
3247void intel_finish_reset(struct drm_device *dev)
3248{
3249 struct drm_i915_private *dev_priv = to_i915(dev);
3250
3251 /*
3252 * Flips in the rings will be nuked by the reset,
3253 * so complete all pending flips so that user space
3254 * will get its events and not get stuck.
3255 */
3256 intel_complete_page_flips(dev);
3257
3258 /* no reset support for gen2 */
3259 if (IS_GEN2(dev))
3260 return;
3261
3262 /* reset doesn't touch the display */
3263 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3264 /*
3265 * Flips in the rings have been nuked by the reset,
3266 * so update the base address of all primary
3267 * planes to the the last fb to make sure we're
3268 * showing the correct fb after a reset.
Maarten Lankhorst11c22da2015-09-10 16:07:58 +02003269 *
3270 * FIXME: Atomic will make this obsolete since we won't schedule
3271 * CS-based flips (which might get lost in gpu resets) any more.
Ville Syrjälä75147472014-11-24 18:28:11 +02003272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +02003291 intel_display_resume(dev);
Ville Syrjälä75147472014-11-24 18:28:11 +02003292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296}
3297
Chris Wilson7d5e3792014-03-04 13:15:08 +00003298static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3299{
3300 struct drm_device *dev = crtc->dev;
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003303 bool pending;
3304
3305 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3306 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3307 return false;
3308
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003309 spin_lock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003310 pending = to_intel_crtc(crtc)->unpin_work != NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003311 spin_unlock_irq(&dev->event_lock);
Chris Wilson7d5e3792014-03-04 13:15:08 +00003312
3313 return pending;
3314}
3315
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003316static void intel_update_pipe_config(struct intel_crtc *crtc,
3317 struct intel_crtc_state *old_crtc_state)
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003318{
3319 struct drm_device *dev = crtc->base.dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003321 struct intel_crtc_state *pipe_config =
3322 to_intel_crtc_state(crtc->base.state);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003323
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003324 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3325 crtc->base.mode = crtc->base.state->mode;
3326
3327 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3328 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3329 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003330
Maarten Lankhorst44522d82015-08-27 15:44:02 +02003331 if (HAS_DDI(dev))
3332 intel_set_pipe_csc(&crtc->base);
3333
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003341 */
3342
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003343 I915_WRITE(PIPESRC(crtc->pipe),
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02003344 ((pipe_config->pipe_src_w - 1) << 16) |
3345 (pipe_config->pipe_src_h - 1));
3346
3347 /* on skylake this is done by detaching scalers */
3348 if (INTEL_INFO(dev)->gen >= 9) {
3349 skl_detach_scalers(crtc);
3350
3351 if (pipe_config->pch_pfit.enabled)
3352 skylake_pfit_enable(crtc);
3353 } else if (HAS_PCH_SPLIT(dev)) {
3354 if (pipe_config->pch_pfit.enabled)
3355 ironlake_pfit_enable(crtc);
3356 else if (old_crtc_state->pch_pfit.enabled)
3357 ironlake_pfit_disable(crtc, true);
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003358 }
Gustavo Padovane30e8f72014-09-10 12:04:17 -03003359}
3360
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003361static void intel_fdi_normal_train(struct drm_crtc *crtc)
3362{
3363 struct drm_device *dev = crtc->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003367 i915_reg_t reg;
3368 u32 temp;
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003369
3370 /* enable normal train */
3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07003373 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07003374 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3375 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07003376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07003379 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003380 I915_WRITE(reg, temp);
3381
3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 if (HAS_PCH_CPT(dev)) {
3385 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3386 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3387 } else {
3388 temp &= ~FDI_LINK_TRAIN_NONE;
3389 temp |= FDI_LINK_TRAIN_NONE;
3390 }
3391 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3392
3393 /* wait one idle pattern time */
3394 POSTING_READ(reg);
3395 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07003396
3397 /* IVB wants error correction enabled */
3398 if (IS_IVYBRIDGE(dev))
3399 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3400 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003401}
3402
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003403/* The FDI link training functions for ILK/Ibexpeak. */
3404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3405{
3406 struct drm_device *dev = crtc->dev;
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3409 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003410 i915_reg_t reg;
3411 u32 temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003412
Ville Syrjälä1c8562f2014-04-25 22:12:07 +03003413 /* FDI needs bits from pipe first */
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003414 assert_pipe_enabled(dev_priv, pipe);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003415
Adam Jacksone1a44742010-06-25 15:32:14 -04003416 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3417 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003418 reg = FDI_RX_IMR(pipe);
3419 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003420 temp &= ~FDI_RX_SYMBOL_LOCK;
3421 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003422 I915_WRITE(reg, temp);
3423 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003424 udelay(150);
3425
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003426 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003429 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003430 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003431 temp &= ~FDI_LINK_TRAIN_NONE;
3432 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003433 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003434
Chris Wilson5eddb702010-09-11 13:48:45 +01003435 reg = FDI_RX_CTL(pipe);
3436 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003437 temp &= ~FDI_LINK_TRAIN_NONE;
3438 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01003439 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3440
3441 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003442 udelay(150);
3443
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003444 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01003445 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3447 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07003448
Chris Wilson5eddb702010-09-11 13:48:45 +01003449 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003450 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003451 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3453
3454 if ((temp & FDI_RX_BIT_LOCK)) {
3455 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003456 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003457 break;
3458 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003459 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003460 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003461 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003462
3463 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003464 reg = FDI_TX_CTL(pipe);
3465 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003466 temp &= ~FDI_LINK_TRAIN_NONE;
3467 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003468 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003469
Chris Wilson5eddb702010-09-11 13:48:45 +01003470 reg = FDI_RX_CTL(pipe);
3471 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003472 temp &= ~FDI_LINK_TRAIN_NONE;
3473 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01003474 I915_WRITE(reg, temp);
3475
3476 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003477 udelay(150);
3478
Chris Wilson5eddb702010-09-11 13:48:45 +01003479 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04003480 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003481 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3483
3484 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003485 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003486 DRM_DEBUG_KMS("FDI train 2 done.\n");
3487 break;
3488 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003489 }
Adam Jacksone1a44742010-06-25 15:32:14 -04003490 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01003491 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003492
3493 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07003494
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003495}
3496
Akshay Joshi0206e352011-08-16 15:34:10 -04003497static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003498 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3499 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3500 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3501 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3502};
3503
3504/* The FDI link training functions for SNB/Cougarpoint. */
3505static void gen6_fdi_link_train(struct drm_crtc *crtc)
3506{
3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003511 i915_reg_t reg;
3512 u32 temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003513
Adam Jacksone1a44742010-06-25 15:32:14 -04003514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01003516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01003520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04003523 udelay(150);
3524
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003525 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01003526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01003535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003536
Daniel Vetterd74cf322012-10-26 10:58:13 +02003537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
Chris Wilson5eddb702010-09-11 13:48:45 +01003540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003552 udelay(150);
3553
Akshay Joshi0206e352011-08-16 15:34:10 -04003554 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003562 udelay(500);
3563
Sean Paulfa37d392012-03-02 12:53:39 -05003564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003574 }
Sean Paulfa37d392012-03-02 12:53:39 -05003575 if (retry < 5)
3576 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003577 }
3578 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003579 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003580
3581 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01003582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003591 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003592
Chris Wilson5eddb702010-09-11 13:48:45 +01003593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
Chris Wilson5eddb702010-09-11 13:48:45 +01003602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003605 udelay(150);
3606
Akshay Joshi0206e352011-08-16 15:34:10 -04003607 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01003608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01003612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003615 udelay(500);
3616
Sean Paulfa37d392012-03-02 12:53:39 -05003617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003627 }
Sean Paulfa37d392012-03-02 12:53:39 -05003628 if (retry < 5)
3629 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003630 }
3631 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01003632 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635}
3636
Jesse Barnes357555c2011-04-28 15:09:55 -07003637/* Manual link training for Ivy Bridge A0 parts */
3638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003644 i915_reg_t reg;
3645 u32 temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07003646
3647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3648 for train result */
3649 reg = FDI_RX_IMR(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_RX_SYMBOL_LOCK;
3652 temp &= ~FDI_RX_BIT_LOCK;
3653 I915_WRITE(reg, temp);
3654
3655 POSTING_READ(reg);
3656 udelay(150);
3657
Daniel Vetter01a415f2012-10-27 15:58:40 +02003658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3659 I915_READ(FDI_RX_IIR(pipe)));
3660
Jesse Barnes139ccd32013-08-19 11:04:55 -07003661 /* Try each vswing and preemphasis setting twice before moving on */
3662 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3663 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07003664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003666 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3667 temp &= ~FDI_TX_ENABLE;
3668 I915_WRITE(reg, temp);
3669
3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~FDI_LINK_TRAIN_AUTO;
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp &= ~FDI_RX_ENABLE;
3675 I915_WRITE(reg, temp);
3676
3677 /* enable CPU FDI TX and PCH FDI RX */
3678 reg = FDI_TX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp &= ~FDI_DP_PORT_WIDTH_MASK;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003682 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07003683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07003684 temp |= snb_b_fdi_train_param[j/2];
3685 temp |= FDI_COMPOSITE_SYNC;
3686 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3687
3688 I915_WRITE(FDI_RX_MISC(pipe),
3689 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3690
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3694 temp |= FDI_COMPOSITE_SYNC;
3695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3696
3697 POSTING_READ(reg);
3698 udelay(1); /* should be 0.5us */
3699
3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3704
3705 if (temp & FDI_RX_BIT_LOCK ||
3706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3709 i);
3710 break;
3711 }
3712 udelay(1); /* should be 0.5us */
3713 }
3714 if (i == 4) {
3715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3716 continue;
3717 }
3718
3719 /* Train 2 */
3720 reg = FDI_TX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3723 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3724 I915_WRITE(reg, temp);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3729 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07003730 I915_WRITE(reg, temp);
3731
3732 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07003733 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003734
Jesse Barnes139ccd32013-08-19 11:04:55 -07003735 for (i = 0; i < 4; i++) {
3736 reg = FDI_RX_IIR(pipe);
3737 temp = I915_READ(reg);
3738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07003739
Jesse Barnes139ccd32013-08-19 11:04:55 -07003740 if (temp & FDI_RX_SYMBOL_LOCK ||
3741 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3742 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3744 i);
3745 goto train_done;
3746 }
3747 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07003748 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07003749 if (i == 4)
3750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07003751 }
Jesse Barnes357555c2011-04-28 15:09:55 -07003752
Jesse Barnes139ccd32013-08-19 11:04:55 -07003753train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07003754 DRM_DEBUG_KMS("FDI train done.\n");
3755}
3756
Daniel Vetter88cefb62012-08-12 19:27:14 +02003757static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07003758{
Daniel Vetter88cefb62012-08-12 19:27:14 +02003759 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003760 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07003761 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003762 i915_reg_t reg;
3763 u32 temp;
Jesse Barnesc64e3112010-09-10 11:27:03 -07003764
Jesse Barnes0e23b992010-09-10 11:10:00 -07003765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01003766 reg = FDI_RX_CTL(pipe);
3767 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02003768 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003769 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003770 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01003771 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3772
3773 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003774 udelay(200);
3775
3776 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003777 temp = I915_READ(reg);
3778 I915_WRITE(reg, temp | FDI_PCDCLK);
3779
3780 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003781 udelay(200);
3782
Paulo Zanoni20749732012-11-23 15:30:38 -02003783 /* Enable CPU FDI TX PLL, always on for Ironlake */
3784 reg = FDI_TX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3787 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01003788
Paulo Zanoni20749732012-11-23 15:30:38 -02003789 POSTING_READ(reg);
3790 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07003791 }
3792}
3793
Daniel Vetter88cefb62012-08-12 19:27:14 +02003794static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3795{
3796 struct drm_device *dev = intel_crtc->base.dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003799 i915_reg_t reg;
3800 u32 temp;
Daniel Vetter88cefb62012-08-12 19:27:14 +02003801
3802 /* Switch from PCDclk to Rawclk */
3803 reg = FDI_RX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3806
3807 /* Disable CPU FDI TX PLL */
3808 reg = FDI_TX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3811
3812 POSTING_READ(reg);
3813 udelay(100);
3814
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3818
3819 /* Wait for the clocks to turn off. */
3820 POSTING_READ(reg);
3821 udelay(100);
3822}
3823
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003824static void ironlake_fdi_disable(struct drm_crtc *crtc)
3825{
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003830 i915_reg_t reg;
3831 u32 temp;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003832
3833 /* disable CPU FDI tx and PCH FDI rx */
3834 reg = FDI_TX_CTL(pipe);
3835 temp = I915_READ(reg);
3836 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3837 POSTING_READ(reg);
3838
3839 reg = FDI_RX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003842 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003843 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3844
3845 POSTING_READ(reg);
3846 udelay(100);
3847
3848 /* Ironlake workaround, disable clock pointer after downing FDI */
Robin Schroereba905b2014-05-18 02:24:50 +02003849 if (HAS_PCH_IBX(dev))
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003850 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003851
3852 /* still set train pattern 1 */
3853 reg = FDI_TX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~FDI_LINK_TRAIN_NONE;
3856 temp |= FDI_LINK_TRAIN_PATTERN_1;
3857 I915_WRITE(reg, temp);
3858
3859 reg = FDI_RX_CTL(pipe);
3860 temp = I915_READ(reg);
3861 if (HAS_PCH_CPT(dev)) {
3862 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3864 } else {
3865 temp &= ~FDI_LINK_TRAIN_NONE;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1;
3867 }
3868 /* BPC in FDI rx is consistent with that in PIPECONF */
3869 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003870 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003871 I915_WRITE(reg, temp);
3872
3873 POSTING_READ(reg);
3874 udelay(100);
3875}
3876
Chris Wilson5dce5b932014-01-20 10:17:36 +00003877bool intel_has_pending_fb_unpin(struct drm_device *dev)
3878{
3879 struct intel_crtc *crtc;
3880
3881 /* Note that we don't need to be called with mode_config.lock here
3882 * as our list of CRTC objects is static for the lifetime of the
3883 * device and so cannot disappear as we iterate. Similarly, we can
3884 * happily treat the predicates as racy, atomic checks as userspace
3885 * cannot claim and pin a new fb without at least acquring the
3886 * struct_mutex and so serialising with us.
3887 */
Damien Lespiaud3fcc802014-05-13 23:32:22 +01003888 for_each_intel_crtc(dev, crtc) {
Chris Wilson5dce5b932014-01-20 10:17:36 +00003889 if (atomic_read(&crtc->unpin_work_count) == 0)
3890 continue;
3891
3892 if (crtc->unpin_work)
3893 intel_wait_for_vblank(dev, crtc->pipe);
3894
3895 return true;
3896 }
3897
3898 return false;
3899}
3900
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003901static void page_flip_completed(struct intel_crtc *intel_crtc)
3902{
3903 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3904 struct intel_unpin_work *work = intel_crtc->unpin_work;
3905
3906 /* ensure that the unpin work is consistent wrt ->pending. */
3907 smp_rmb();
3908 intel_crtc->unpin_work = NULL;
3909
3910 if (work->event)
3911 drm_send_vblank_event(intel_crtc->base.dev,
3912 intel_crtc->pipe,
3913 work->event);
3914
3915 drm_crtc_vblank_put(&intel_crtc->base);
3916
3917 wake_up_all(&dev_priv->pending_flip_queue);
3918 queue_work(dev_priv->wq, &work->work);
3919
3920 trace_i915_flip_complete(intel_crtc->plane,
3921 work->pending_flip_obj);
3922}
3923
Maarten Lankhorst5008e872015-08-18 13:40:05 +02003924static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003925{
Chris Wilson0f911282012-04-17 10:05:38 +01003926 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01003927 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorst5008e872015-08-18 13:40:05 +02003928 long ret;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003929
Daniel Vetter2c10d572012-12-20 21:24:07 +01003930 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
Maarten Lankhorst5008e872015-08-18 13:40:05 +02003931
3932 ret = wait_event_interruptible_timeout(
3933 dev_priv->pending_flip_queue,
3934 !intel_crtc_has_pending_flip(crtc),
3935 60*HZ);
3936
3937 if (ret < 0)
3938 return ret;
3939
3940 if (ret == 0) {
Chris Wilson9c787942014-09-05 07:13:25 +01003941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter2c10d572012-12-20 21:24:07 +01003942
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003943 spin_lock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003944 if (intel_crtc->unpin_work) {
3945 WARN_ONCE(1, "Removing stuck page flip\n");
3946 page_flip_completed(intel_crtc);
3947 }
Daniel Vetter5e2d7af2014-09-15 14:55:22 +02003948 spin_unlock_irq(&dev->event_lock);
Chris Wilson9c787942014-09-05 07:13:25 +01003949 }
Chris Wilson5bb61642012-09-27 21:25:58 +01003950
Maarten Lankhorst5008e872015-08-18 13:40:05 +02003951 return 0;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003952}
3953
Ville Syrjälä060f02d2015-12-04 22:21:34 +02003954static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3955{
3956 u32 temp;
3957
3958 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3959
3960 mutex_lock(&dev_priv->sb_lock);
3961
3962 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3963 temp |= SBI_SSCCTL_DISABLE;
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3965
3966 mutex_unlock(&dev_priv->sb_lock);
3967}
3968
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003969/* Program iCLKIP clock to the desired frequency */
3970static void lpt_program_iclkip(struct drm_crtc *crtc)
3971{
3972 struct drm_device *dev = crtc->dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02003974 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003975 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3976 u32 temp;
3977
Ville Syrjälä060f02d2015-12-04 22:21:34 +02003978 lpt_disable_iclkip(dev_priv);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003979
3980 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003981 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003982 auxdiv = 1;
3983 divsel = 0x41;
3984 phaseinc = 0x20;
3985 } else {
3986 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003987 * but the adjusted_mode->crtc_clock in in KHz. To get the
3988 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003989 * convert the virtual clock precision to KHz here for higher
3990 * precision.
3991 */
3992 u32 iclk_virtual_root_freq = 172800 * 1000;
3993 u32 iclk_pi_range = 64;
3994 u32 desired_divisor, msb_divisor_value, pi_value;
3995
Ville Syrjäläa2572f52015-12-04 22:20:21 +02003996 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003997 msb_divisor_value = desired_divisor / iclk_pi_range;
3998 pi_value = desired_divisor % iclk_pi_range;
3999
4000 auxdiv = 0;
4001 divsel = msb_divisor_value - 2;
4002 phaseinc = pi_value;
4003 }
4004
4005 /* This should not happen with any sane values */
4006 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4007 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4009 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4010
4011 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03004012 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004013 auxdiv,
4014 divsel,
4015 phasedir,
4016 phaseinc);
4017
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004018 mutex_lock(&dev_priv->sb_lock);
4019
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004020 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004021 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004022 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004028 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004029
4030 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004031 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004032 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004034 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004035
4036 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004037 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004038 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02004039 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004040
Ville Syrjälä060f02d2015-12-04 22:21:34 +02004041 mutex_unlock(&dev_priv->sb_lock);
4042
Eugeni Dodonove615efe2012-05-09 15:37:26 -03004043 /* Wait for initialization time */
4044 udelay(24);
4045
4046 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4047}
4048
Daniel Vetter275f01b22013-05-03 11:49:47 +02004049static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050 enum pipe pch_transcoder)
4051{
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
Daniel Vetter275f01b22013-05-03 11:49:47 +02004055
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057 I915_READ(HTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059 I915_READ(HBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061 I915_READ(HSYNC(cpu_transcoder)));
4062
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064 I915_READ(VTOTAL(cpu_transcoder)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066 I915_READ(VBLANK(cpu_transcoder)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068 I915_READ(VSYNC(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4071}
4072
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004073static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 uint32_t temp;
4077
4078 temp = I915_READ(SOUTH_CHICKEN1);
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004079 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004080 return;
4081
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4084
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004085 temp &= ~FDI_BC_BIFURCATION_SELECT;
4086 if (enable)
4087 temp |= FDI_BC_BIFURCATION_SELECT;
4088
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004090 I915_WRITE(SOUTH_CHICKEN1, temp);
4091 POSTING_READ(SOUTH_CHICKEN1);
4092}
4093
4094static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095{
4096 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004097
4098 switch (intel_crtc->pipe) {
4099 case PIPE_A:
4100 break;
4101 case PIPE_B:
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004102 if (intel_crtc->config->fdi_lanes > 2)
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004103 cpt_set_fdi_bc_bifurcation(dev, false);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004104 else
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004105 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004106
4107 break;
4108 case PIPE_C:
Ander Conselvan de Oliveira003632d2015-03-11 13:35:43 +02004109 cpt_set_fdi_bc_bifurcation(dev, true);
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004110
4111 break;
4112 default:
4113 BUG();
4114 }
4115}
4116
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004117/* Return which DP Port should be selected for Transcoder DP control */
4118static enum port
4119intel_trans_dp_port_sel(struct drm_crtc *crtc)
4120{
4121 struct drm_device *dev = crtc->dev;
4122 struct intel_encoder *encoder;
4123
4124 for_each_encoder_on_crtc(dev, crtc, encoder) {
4125 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4126 encoder->type == INTEL_OUTPUT_EDP)
4127 return enc_to_dig_port(&encoder->base)->port;
4128 }
4129
4130 return -1;
4131}
4132
Jesse Barnesf67a5592011-01-05 10:31:48 -08004133/*
4134 * Enable PCH resources required for PCH ports:
4135 * - PCH PLLs
4136 * - FDI training & RX/TX
4137 * - update transcoder timings
4138 * - DP transcoding bits
4139 * - transcoder
4140 */
4141static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004142{
4143 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146 int pipe = intel_crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004147 u32 temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07004148
Daniel Vetterab9412b2013-05-03 11:49:46 +02004149 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01004150
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01004151 if (IS_IVYBRIDGE(dev))
4152 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4153
Daniel Vettercd986ab2012-10-26 10:58:12 +02004154 /* Write the TU size bits before fdi link training, so that error
4155 * detection works. */
4156 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4157 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4158
Ville Syrjälä3860b2e2015-11-20 22:09:18 +02004159 /*
4160 * Sometimes spurious CPU pipe underruns happen during FDI
4161 * training, at least with VGA+HDMI cloning. Suppress them.
4162 */
4163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4164
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004165 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07004166 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004167
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004170 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004171 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004172
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004173 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02004174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004177 temp |= sel;
4178 else
4179 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004180 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004181 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004182
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4186 *
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
Daniel Vetter85b38942014-04-24 23:55:14 +02004190 intel_enable_shared_dpll(intel_crtc);
Daniel Vetter3ad8a202013-06-05 13:34:32 +02004191
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08004192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02004194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004195
Paulo Zanoni303b81e2012-10-31 18:12:23 -02004196 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08004197
Ville Syrjälä3860b2e2015-11-20 22:09:18 +02004198 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4199
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004200 /* For PCH DP, enable TRANS_DP_CTL */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004201 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004202 const struct drm_display_mode *adjusted_mode =
4203 &intel_crtc->config->base.adjusted_mode;
Daniel Vetterdfd07d72012-12-17 11:21:38 +01004204 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004205 i915_reg_t reg = TRANS_DP_CTL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01004206 temp = I915_READ(reg);
4207 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08004208 TRANS_DP_SYNC_MASK |
4209 TRANS_DP_BPC_MASK);
Ville Syrjäläe3ef4472015-05-05 17:17:31 +03004210 temp |= TRANS_DP_OUTPUT_ENABLE;
Jesse Barnes9325c9f2011-06-24 12:19:21 -07004211 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004212
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004213 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004214 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Ville Syrjälä9c4edae2015-10-29 21:25:51 +02004215 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01004216 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004217
4218 switch (intel_trans_dp_port_sel(crtc)) {
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004219 case PORT_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01004220 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004221 break;
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004222 case PORT_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01004223 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004224 break;
Ville Syrjäläc48b5302015-11-04 23:19:56 +02004225 case PORT_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01004226 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004227 break;
4228 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02004229 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004230 }
4231
Chris Wilson5eddb702010-09-11 13:48:45 +01004232 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07004233 }
4234
Paulo Zanonib8a4f402012-10-31 18:12:42 -02004235 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004236}
4237
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004238static void lpt_pch_enable(struct drm_crtc *crtc)
4239{
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004243 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004244
Daniel Vetterab9412b2013-05-03 11:49:46 +02004245 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004246
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02004247 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004248
Paulo Zanoni0540e482012-10-31 18:12:40 -02004249 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02004250 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02004251
Paulo Zanoni937bb612012-10-31 18:12:47 -02004252 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004253}
4254
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004255struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4256 struct intel_crtc_state *crtc_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004257{
Daniel Vettere2b78262013-06-07 23:10:03 +02004258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004259 struct intel_shared_dpll *pll;
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004260 struct intel_shared_dpll_config *shared_dpll;
Daniel Vettere2b78262013-06-07 23:10:03 +02004261 enum intel_dpll_id i;
Maarten Lankhorst00490c22015-11-16 14:42:12 +01004262 int max = dev_priv->num_shared_dpll;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004263
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004264 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4265
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004266 if (HAS_PCH_IBX(dev_priv->dev)) {
4267 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02004268 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004269 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004270
Daniel Vetter46edb022013-06-05 13:34:12 +02004271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004273
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004274 WARN_ON(shared_dpll[i].crtc_mask);
Daniel Vetterf2a69f42014-05-20 15:19:19 +02004275
Daniel Vetter98b6bd92012-05-20 20:00:25 +02004276 goto found;
4277 }
4278
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +05304279 if (IS_BROXTON(dev_priv->dev)) {
4280 /* PLL is attached to port in bxt */
4281 struct intel_encoder *encoder;
4282 struct intel_digital_port *intel_dig_port;
4283
4284 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4285 if (WARN_ON(!encoder))
4286 return NULL;
4287
4288 intel_dig_port = enc_to_dig_port(&encoder->base);
4289 /* 1:1 mapping between ports and PLLs */
4290 i = (enum intel_dpll_id)intel_dig_port->port;
4291 pll = &dev_priv->shared_dplls[i];
4292 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4293 crtc->base.base.id, pll->name);
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004294 WARN_ON(shared_dpll[i].crtc_mask);
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +05304295
4296 goto found;
Maarten Lankhorst00490c22015-11-16 14:42:12 +01004297 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4298 /* Do not consider SPLL */
4299 max = 2;
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +05304300
Maarten Lankhorst00490c22015-11-16 14:42:12 +01004301 for (i = 0; i < max; i++) {
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004302 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004303
4304 /* Only want to check enabled timings first */
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004305 if (shared_dpll[i].crtc_mask == 0)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004306 continue;
4307
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004308 if (memcmp(&crtc_state->dpll_hw_state,
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004309 &shared_dpll[i].hw_state,
4310 sizeof(crtc_state->dpll_hw_state)) == 0) {
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004311 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +02004312 crtc->base.base.id, pll->name,
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004313 shared_dpll[i].crtc_mask,
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004314 pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004315 goto found;
4316 }
4317 }
4318
4319 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02004320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004322 if (shared_dpll[i].crtc_mask == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02004323 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4324 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004325 goto found;
4326 }
4327 }
4328
4329 return NULL;
4330
4331found:
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004332 if (shared_dpll[i].crtc_mask == 0)
4333 shared_dpll[i].hw_state =
4334 crtc_state->dpll_hw_state;
Daniel Vetterf2a69f42014-05-20 15:19:19 +02004335
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02004336 crtc_state->shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02004337 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4338 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02004339
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004340 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004341
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004342 return pll;
4343}
4344
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004345static void intel_shared_dpll_commit(struct drm_atomic_state *state)
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004346{
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004347 struct drm_i915_private *dev_priv = to_i915(state->dev);
4348 struct intel_shared_dpll_config *shared_dpll;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4351
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004352 if (!to_intel_atomic_state(state)->dpll_set)
4353 return;
4354
4355 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004356 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4357 pll = &dev_priv->shared_dplls[i];
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02004358 pll->config = shared_dpll[i];
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02004359 }
4360}
4361
Daniel Vettera1520312013-05-03 11:49:50 +02004362static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07004363{
4364 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004365 i915_reg_t dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07004366 u32 temp;
4367
4368 temp = I915_READ(dslreg);
4369 udelay(500);
4370 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07004371 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03004372 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07004373 }
4374}
4375
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004376static int
4377skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4378 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4379 int src_w, int src_h, int dst_w, int dst_h)
Chandra Kondurua1b22782015-04-07 15:28:45 -07004380{
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004381 struct intel_crtc_scaler_state *scaler_state =
4382 &crtc_state->scaler_state;
4383 struct intel_crtc *intel_crtc =
4384 to_intel_crtc(crtc_state->base.crtc);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004385 int need_scaling;
Chandra Konduru6156a452015-04-27 13:48:39 -07004386
4387 need_scaling = intel_rotation_90_or_270(rotation) ?
4388 (src_h != dst_w || src_w != dst_h):
4389 (src_w != dst_w || src_h != dst_h);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004390
4391 /*
4392 * if plane is being disabled or scaler is no more required or force detach
4393 * - free scaler binded to this plane/crtc
4394 * - in order to do this, update crtc->scaler_usage
4395 *
4396 * Here scaler state in crtc_state is set free so that
4397 * scaler can be assigned to other user. Actual register
4398 * update to free the scaler is done in plane/panel-fit programming.
4399 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4400 */
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004401 if (force_detach || !need_scaling) {
Chandra Kondurua1b22782015-04-07 15:28:45 -07004402 if (*scaler_id >= 0) {
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004403 scaler_state->scaler_users &= ~(1 << scaler_user);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004404 scaler_state->scalers[*scaler_id].in_use = 0;
4405
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004406 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4407 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4408 intel_crtc->pipe, scaler_user, *scaler_id,
Chandra Kondurua1b22782015-04-07 15:28:45 -07004409 scaler_state->scaler_users);
4410 *scaler_id = -1;
4411 }
4412 return 0;
4413 }
4414
4415 /* range checks */
4416 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4417 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4418
4419 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4420 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004421 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
Chandra Kondurua1b22782015-04-07 15:28:45 -07004422 "size is out of scaler range\n",
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004423 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004424 return -EINVAL;
4425 }
4426
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004427 /* mark this plane as a scaler user in crtc_state */
4428 scaler_state->scaler_users |= (1 << scaler_user);
4429 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4430 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4431 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4432 scaler_state->scaler_users);
4433
4434 return 0;
4435}
4436
4437/**
4438 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4439 *
4440 * @state: crtc's scaler state
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004441 *
4442 * Return
4443 * 0 - scaler_usage updated successfully
4444 * error - requested scaling cannot be supported or other error condition
4445 */
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004446int skl_update_scaler_crtc(struct intel_crtc_state *state)
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004447{
4448 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03004449 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004450
4451 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4452 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4453
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004454 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004455 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4456 state->pipe_src_w, state->pipe_src_h,
Ville Syrjäläaad941d2015-09-25 16:38:56 +03004457 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004458}
4459
4460/**
4461 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4462 *
4463 * @state: crtc's scaler state
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004464 * @plane_state: atomic plane state to update
4465 *
4466 * Return
4467 * 0 - scaler_usage updated successfully
4468 * error - requested scaling cannot be supported or other error condition
4469 */
Maarten Lankhorstda20eab2015-06-15 12:33:44 +02004470static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4471 struct intel_plane_state *plane_state)
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004472{
4473
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +02004475 struct intel_plane *intel_plane =
4476 to_intel_plane(plane_state->base.plane);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004477 struct drm_framebuffer *fb = plane_state->base.fb;
4478 int ret;
4479
4480 bool force_detach = !fb || !plane_state->visible;
4481
4482 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4483 intel_plane->base.base.id, intel_crtc->pipe,
4484 drm_plane_index(&intel_plane->base));
4485
4486 ret = skl_update_scaler(crtc_state, force_detach,
4487 drm_plane_index(&intel_plane->base),
4488 &plane_state->scaler_id,
4489 plane_state->base.rotation,
4490 drm_rect_width(&plane_state->src) >> 16,
4491 drm_rect_height(&plane_state->src) >> 16,
4492 drm_rect_width(&plane_state->dst),
4493 drm_rect_height(&plane_state->dst));
4494
4495 if (ret || plane_state->scaler_id < 0)
4496 return ret;
4497
Chandra Kondurua1b22782015-04-07 15:28:45 -07004498 /* check colorkey */
Maarten Lankhorst818ed962015-06-15 12:33:54 +02004499 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004500 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
Maarten Lankhorst818ed962015-06-15 12:33:54 +02004501 intel_plane->base.base.id);
Chandra Kondurua1b22782015-04-07 15:28:45 -07004502 return -EINVAL;
4503 }
4504
4505 /* Check src format */
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02004506 switch (fb->pixel_format) {
4507 case DRM_FORMAT_RGB565:
4508 case DRM_FORMAT_XBGR8888:
4509 case DRM_FORMAT_XRGB8888:
4510 case DRM_FORMAT_ABGR8888:
4511 case DRM_FORMAT_ARGB8888:
4512 case DRM_FORMAT_XRGB2101010:
4513 case DRM_FORMAT_XBGR2101010:
4514 case DRM_FORMAT_YUYV:
4515 case DRM_FORMAT_YVYU:
4516 case DRM_FORMAT_UYVY:
4517 case DRM_FORMAT_VYUY:
4518 break;
4519 default:
4520 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4521 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4522 return -EINVAL;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004523 }
4524
Chandra Kondurua1b22782015-04-07 15:28:45 -07004525 return 0;
4526}
4527
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02004528static void skylake_scaler_disable(struct intel_crtc *crtc)
4529{
4530 int i;
4531
4532 for (i = 0; i < crtc->num_scalers; i++)
4533 skl_detach_scaler(crtc, i);
4534}
4535
4536static void skylake_pfit_enable(struct intel_crtc *crtc)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004537{
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 int pipe = crtc->pipe;
Chandra Kondurua1b22782015-04-07 15:28:45 -07004541 struct intel_crtc_scaler_state *scaler_state =
4542 &crtc->config->scaler_state;
4543
4544 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4545
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004546 if (crtc->config->pch_pfit.enabled) {
Chandra Kondurua1b22782015-04-07 15:28:45 -07004547 int id;
4548
4549 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4550 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4551 return;
4552 }
4553
4554 id = scaler_state->scaler_id;
4555 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4556 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4557 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4558 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4559
4560 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00004561 }
4562}
4563
Jesse Barnesb074cec2013-04-25 12:55:02 -07004564static void ironlake_pfit_enable(struct intel_crtc *crtc)
4565{
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 int pipe = crtc->pipe;
4569
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004570 if (crtc->config->pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07004571 /* Force use of hard-coded filter coefficients
4572 * as some pre-programmed values are broken,
4573 * e.g. x201.
4574 */
4575 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4577 PF_PIPE_SEL_IVB(pipe));
4578 else
4579 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004580 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4581 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08004582 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004583}
4584
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004585void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004586{
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004587 struct drm_device *dev = crtc->base.dev;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004589
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004590 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004591 return;
4592
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004593 /* We can only enable IPS after we enable a plane and wait for a vblank */
4594 intel_wait_for_vblank(dev, crtc->pipe);
4595
Paulo Zanonid77e4532013-09-24 13:52:55 -03004596 assert_plane_enabled(dev_priv, crtc->plane);
Ville Syrjäläcea165c2014-04-15 21:41:35 +03004597 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004598 mutex_lock(&dev_priv->rps.hw_lock);
4599 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4600 mutex_unlock(&dev_priv->rps.hw_lock);
4601 /* Quoting Art Runyan: "its not safe to expect any particular
4602 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08004603 * mailbox." Moreover, the mailbox may return a bogus state,
4604 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004605 */
4606 } else {
4607 I915_WRITE(IPS_CTL, IPS_ENABLE);
4608 /* The bit only becomes 1 in the next vblank, so this wait here
4609 * is essentially intel_wait_for_vblank. If we don't have this
4610 * and don't wait for vblanks until the end of crtc_enable, then
4611 * the HW state readout code will complain that the expected
4612 * IPS_CTL value is not the one we read. */
4613 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4614 DRM_ERROR("Timed out waiting for IPS enable\n");
4615 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004616}
4617
Ville Syrjälä20bc86732013-10-01 18:02:17 +03004618void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004619{
4620 struct drm_device *dev = crtc->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004623 if (!crtc->config->ips_enabled)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004624 return;
4625
4626 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004627 if (IS_BROADWELL(dev)) {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004628 mutex_lock(&dev_priv->rps.hw_lock);
4629 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4630 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky23d0b132014-04-10 14:32:41 -07004631 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4632 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4633 DRM_ERROR("Timed out waiting for IPS disable\n");
Jesse Barnese59150d2014-01-07 13:30:45 -08004634 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07004635 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08004636 POSTING_READ(IPS_CTL);
4637 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03004638
4639 /* We need to wait for a vblank before we can disable the plane. */
4640 intel_wait_for_vblank(dev, crtc->pipe);
4641}
4642
4643/** Loads the palette/gamma unit for the CRTC with the prepared values */
4644static void intel_crtc_load_lut(struct drm_crtc *crtc)
4645{
4646 struct drm_device *dev = crtc->dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 enum pipe pipe = intel_crtc->pipe;
Paulo Zanonid77e4532013-09-24 13:52:55 -03004650 int i;
4651 bool reenable_ips = false;
4652
4653 /* The clocks have to be on to load the palette. */
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02004654 if (!crtc->state->active)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004655 return;
4656
Imre Deak50360402015-01-16 00:55:16 -08004657 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
Jani Nikulaa65347b2015-11-27 12:21:46 +02004658 if (intel_crtc->config->has_dsi_encoder)
Paulo Zanonid77e4532013-09-24 13:52:55 -03004659 assert_dsi_pll_enabled(dev_priv);
4660 else
4661 assert_pll_enabled(dev_priv, pipe);
4662 }
4663
Paulo Zanonid77e4532013-09-24 13:52:55 -03004664 /* Workaround : Do not read or write the pipe palette/gamma data while
4665 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4666 */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004667 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03004668 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4669 GAMMA_MODE_MODE_SPLIT)) {
4670 hsw_disable_ips(intel_crtc);
4671 reenable_ips = true;
4672 }
4673
4674 for (i = 0; i < 256; i++) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02004675 i915_reg_t palreg;
Ville Syrjäläf65a9c52015-09-18 20:03:28 +03004676
4677 if (HAS_GMCH_DISPLAY(dev))
4678 palreg = PALETTE(pipe, i);
4679 else
4680 palreg = LGC_PALETTE(pipe, i);
4681
4682 I915_WRITE(palreg,
Paulo Zanonid77e4532013-09-24 13:52:55 -03004683 (intel_crtc->lut_r[i] << 16) |
4684 (intel_crtc->lut_g[i] << 8) |
4685 intel_crtc->lut_b[i]);
4686 }
4687
4688 if (reenable_ips)
4689 hsw_enable_ips(intel_crtc);
4690}
4691
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004692static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004693{
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004694 if (intel_crtc->overlay) {
Ville Syrjäläd3eedb12014-05-08 19:23:13 +03004695 struct drm_device *dev = intel_crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697
4698 mutex_lock(&dev->struct_mutex);
4699 dev_priv->mm.interruptible = false;
4700 (void) intel_overlay_switch_off(intel_crtc->overlay);
4701 dev_priv->mm.interruptible = true;
4702 mutex_unlock(&dev->struct_mutex);
4703 }
4704
4705 /* Let userspace switch the overlay on again. In most cases userspace
4706 * has to recompute where to put it anyway.
4707 */
4708}
4709
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004710/**
4711 * intel_post_enable_primary - Perform operations after enabling primary plane
4712 * @crtc: the CRTC whose primary plane was just enabled
4713 *
4714 * Performs potentially sleeping operations that must be done after the primary
4715 * plane is enabled, such as updating FBC and IPS. Note that this may be
4716 * called due to an explicit primary plane update, or due to an implicit
4717 * re-enable that is caused when a sprite plane is updated to no longer
4718 * completely hide the primary plane.
4719 */
4720static void
4721intel_post_enable_primary(struct drm_crtc *crtc)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004722{
4723 struct drm_device *dev = crtc->dev;
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004724 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4726 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004727
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004728 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004729 * FIXME IPS should be fine as long as one plane is
4730 * enabled, but in practice it seems to have problems
4731 * when going from primary only to sprite only and vice
4732 * versa.
4733 */
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004734 hsw_enable_ips(intel_crtc);
4735
Daniel Vetterf99d7062014-06-19 16:01:59 +02004736 /*
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004737 * Gen2 reports pipe underruns whenever all planes are disabled.
4738 * So don't enable underrun reporting before at least some planes
4739 * are enabled.
4740 * FIXME: Need to fix the logic to work when we turn off all planes
4741 * but leave the pipe running.
Daniel Vetterf99d7062014-06-19 16:01:59 +02004742 */
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004743 if (IS_GEN2(dev))
4744 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4745
Ville Syrjäläaca7b682015-10-30 19:22:21 +02004746 /* Underruns don't always raise interrupts, so check manually. */
4747 intel_check_cpu_fifo_underruns(dev_priv);
4748 intel_check_pch_fifo_underruns(dev_priv);
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004749}
4750
4751/**
4752 * intel_pre_disable_primary - Perform operations before disabling primary plane
4753 * @crtc: the CRTC whose primary plane is to be disabled
4754 *
4755 * Performs potentially sleeping operations that must be done before the
4756 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4757 * be called due to an explicit primary plane update, or due to an implicit
4758 * disable that is caused when a sprite plane completely hides the primary
4759 * plane.
4760 */
4761static void
4762intel_pre_disable_primary(struct drm_crtc *crtc)
4763{
4764 struct drm_device *dev = crtc->dev;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 int pipe = intel_crtc->pipe;
4768
4769 /*
4770 * Gen2 reports pipe underruns whenever all planes are disabled.
4771 * So diasble underrun reporting before all the planes get disabled.
4772 * FIXME: Need to fix the logic to work when we turn off all planes
4773 * but leave the pipe running.
4774 */
4775 if (IS_GEN2(dev))
4776 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4777
4778 /*
4779 * Vblank time updates from the shadow to live plane control register
4780 * are blocked if the memory self-refresh mode is active at that
4781 * moment. So to make sure the plane gets truly disabled, disable
4782 * first the self-refresh mode. The self-refresh enable bit in turn
4783 * will be checked/applied by the HW only at the next frame start
4784 * event which is after the vblank start event, so we need to have a
4785 * wait-for-vblank between disabling the plane and the pipe.
4786 */
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03004787 if (HAS_GMCH_DISPLAY(dev)) {
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004788 intel_set_memory_cxsr(dev_priv, false);
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03004789 dev_priv->wm.vlv.cxsr = false;
4790 intel_wait_for_vblank(dev, pipe);
4791 }
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004792
Maarten Lankhorst87d43002015-04-21 17:12:54 +03004793 /*
4794 * FIXME IPS should be fine as long as one plane is
4795 * enabled, but in practice it seems to have problems
4796 * when going from primary only to sprite only and vice
4797 * versa.
4798 */
4799 hsw_disable_ips(intel_crtc);
4800}
4801
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004802static void intel_post_plane_update(struct intel_crtc *crtc)
4803{
4804 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
Maarten Lankhorst92826fc2015-12-03 13:49:13 +01004805 struct intel_crtc_state *pipe_config =
4806 to_intel_crtc_state(crtc->base.state);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004807 struct drm_device *dev = crtc->base.dev;
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004808
4809 if (atomic->wait_vblank)
4810 intel_wait_for_vblank(dev, crtc->pipe);
4811
4812 intel_frontbuffer_flip(dev, atomic->fb_bits);
4813
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +01004814 crtc->wm.cxsr_allowed = true;
Ville Syrjälä852eb002015-06-24 22:00:07 +03004815
Maarten Lankhorstb9001112015-11-19 16:07:16 +01004816 if (pipe_config->wm_changed && pipe_config->base.active)
Ville Syrjäläf015c552015-06-24 22:00:02 +03004817 intel_update_watermarks(&crtc->base);
4818
Paulo Zanonic80ac852015-07-02 19:25:13 -03004819 if (atomic->update_fbc)
Paulo Zanoni754d1132015-10-13 19:13:25 -03004820 intel_fbc_update(crtc);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004821
4822 if (atomic->post_enable_primary)
4823 intel_post_enable_primary(&crtc->base);
4824
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004825 memset(atomic, 0, sizeof(*atomic));
4826}
4827
4828static void intel_pre_plane_update(struct intel_crtc *crtc)
4829{
4830 struct drm_device *dev = crtc->base.dev;
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +02004831 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004832 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +01004833 struct intel_crtc_state *pipe_config =
4834 to_intel_crtc_state(crtc->base.state);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004835
Paulo Zanonic80ac852015-07-02 19:25:13 -03004836 if (atomic->disable_fbc)
Paulo Zanonid029bca2015-10-15 10:44:46 -03004837 intel_fbc_deactivate(crtc);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004838
Rodrigo Vivi066cf552015-06-26 13:55:54 -07004839 if (crtc->atomic.disable_ips)
4840 hsw_disable_ips(crtc);
4841
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004842 if (atomic->pre_disable_primary)
4843 intel_pre_disable_primary(&crtc->base);
Ville Syrjälä852eb002015-06-24 22:00:07 +03004844
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +01004845 if (pipe_config->disable_cxsr) {
Ville Syrjälä852eb002015-06-24 22:00:07 +03004846 crtc->wm.cxsr_allowed = false;
4847 intel_set_memory_cxsr(dev_priv, false);
4848 }
Maarten Lankhorst92826fc2015-12-03 13:49:13 +01004849
4850 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4851 intel_update_watermarks(&crtc->base);
Maarten Lankhorstac21b222015-06-15 12:33:49 +02004852}
4853
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02004854static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004855{
4856 struct drm_device *dev = crtc->dev;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02004858 struct drm_plane *p;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004859 int pipe = intel_crtc->pipe;
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004860
Maarten Lankhorst7cac9452015-04-21 17:12:55 +03004861 intel_crtc_dpms_overlay_disable(intel_crtc);
Maarten Lankhorst27321ae2015-04-21 17:12:52 +03004862
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +02004863 drm_for_each_plane_mask(p, dev, plane_mask)
4864 to_intel_plane(p)->disable_plane(p, crtc);
Ville Syrjäläf98551a2014-05-22 17:48:06 +03004865
Daniel Vetterf99d7062014-06-19 16:01:59 +02004866 /*
4867 * FIXME: Once we grow proper nuclear flip support out of this we need
4868 * to compute the mask of flip planes precisely. For the time being
4869 * consider this a flip to a NULL plane.
4870 */
4871 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
Ville Syrjäläa5c4d7b2014-03-07 18:32:13 +02004872}
4873
Jesse Barnesf67a5592011-01-05 10:31:48 -08004874static void ironlake_crtc_enable(struct drm_crtc *crtc)
4875{
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004879 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004880 int pipe = intel_crtc->pipe;
Jesse Barnesf67a5592011-01-05 10:31:48 -08004881
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02004882 if (WARN_ON(intel_crtc->active))
Jesse Barnesf67a5592011-01-05 10:31:48 -08004883 return;
4884
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004885 if (intel_crtc->config->has_pch_encoder)
Ville Syrjälä81b088c2015-10-30 19:21:31 +02004886 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4887
4888 if (intel_crtc->config->has_pch_encoder)
Daniel Vetterb14b1052014-04-24 23:55:13 +02004889 intel_prepare_shared_dpll(intel_crtc);
4890
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004891 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05304892 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004893
4894 intel_set_pipe_timings(intel_crtc);
4895
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004896 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter29407aa2014-04-24 23:55:08 +02004897 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004898 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter29407aa2014-04-24 23:55:08 +02004899 }
4900
4901 ironlake_set_pipeconf(crtc);
4902
Jesse Barnesf67a5592011-01-05 10:31:48 -08004903 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004904
Daniel Vettera72e4c92014-09-30 10:56:47 +02004905 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanoni86642812013-04-12 17:57:57 -03004906
Daniel Vetterf6736a12013-06-05 13:34:30 +02004907 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02004908 if (encoder->pre_enable)
4909 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004910
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004911 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02004912 /* Note: FDI PLL enabling _must_ be done before we enable the
4913 * cpu pipes, hence this is separate from all the other fdi/pch
4914 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02004915 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02004916 } else {
4917 assert_fdi_tx_disabled(dev_priv, pipe);
4918 assert_fdi_rx_disabled(dev_priv, pipe);
4919 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08004920
Jesse Barnesb074cec2013-04-25 12:55:02 -07004921 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004922
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02004923 /*
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4925 * clocks enabled
4926 */
4927 intel_crtc_load_lut(crtc);
4928
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004929 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02004930 intel_enable_pipe(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08004931
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004932 if (intel_crtc->config->has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08004933 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004934
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01004935 assert_vblank_disabled(crtc);
4936 drm_crtc_vblank_on(crtc);
4937
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02004940
4941 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02004942 cpt_verify_modeset(dev, intel_crtc->pipe);
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02004943
4944 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4945 if (intel_crtc->config->has_pch_encoder)
4946 intel_wait_for_vblank(dev, pipe);
4947 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanonid029bca2015-10-15 10:44:46 -03004948
4949 intel_fbc_enable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07004950}
4951
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004952/* IPS only exists on ULT machines and is tied to pipe A. */
4953static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954{
Damien Lespiauf5adf942013-06-24 18:29:34 +01004955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004956}
4957
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004958static void haswell_crtc_enable(struct drm_crtc *crtc)
4959{
4960 struct drm_device *dev = crtc->dev;
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963 struct intel_encoder *encoder;
Maarten Lankhorst99d736a2015-06-01 12:50:09 +02004964 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4965 struct intel_crtc_state *pipe_config =
4966 to_intel_crtc_state(crtc->state);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004967
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02004968 if (WARN_ON(intel_crtc->active))
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004969 return;
4970
Ville Syrjälä81b088c2015-10-30 19:21:31 +02004971 if (intel_crtc->config->has_pch_encoder)
4972 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4973 false);
4974
Daniel Vetterdf8ad702014-06-25 22:02:03 +03004975 if (intel_crtc_to_shared_dpll(intel_crtc))
4976 intel_enable_shared_dpll(intel_crtc);
4977
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004978 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05304979 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter229fca92014-04-24 23:55:09 +02004980
4981 intel_set_pipe_timings(intel_crtc);
4982
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004983 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4984 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4985 intel_crtc->config->pixel_multiplier - 1);
Clint Taylorebb69c92014-09-30 10:30:22 -07004986 }
4987
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004988 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetter229fca92014-04-24 23:55:09 +02004989 intel_cpu_transcoder_set_m_n(intel_crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02004990 &intel_crtc->config->fdi_m_n, NULL);
Daniel Vetter229fca92014-04-24 23:55:09 +02004991 }
4992
4993 haswell_set_pipeconf(crtc);
4994
4995 intel_set_pipe_csc(crtc);
4996
Paulo Zanoni4f771f12012-10-23 18:29:51 -02004997 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03004998
Daniel Vetter6b698512015-11-28 11:05:39 +01004999 if (intel_crtc->config->has_pch_encoder)
5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5001 else
5002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5003
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305004 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005005 if (encoder->pre_enable)
5006 encoder->pre_enable(encoder);
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305007 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005008
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005009 if (intel_crtc->config->has_pch_encoder)
Imre Deak4fe94672014-06-25 22:01:49 +03005010 dev_priv->display.fdi_link_train(crtc);
Imre Deak4fe94672014-06-25 22:01:49 +03005011
Jani Nikulaa65347b2015-11-27 12:21:46 +02005012 if (!intel_crtc->config->has_dsi_encoder)
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305013 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005014
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005015 if (INTEL_INFO(dev)->gen >= 9)
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02005016 skylake_pfit_enable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005017 else
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005018 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005019
5020 /*
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5022 * clocks enabled
5023 */
5024 intel_crtc_load_lut(crtc);
5025
Paulo Zanoni1f544382012-10-24 11:32:00 -02005026 intel_ddi_set_pipe_settings(crtc);
Jani Nikulaa65347b2015-11-27 12:21:46 +02005027 if (!intel_crtc->config->has_dsi_encoder)
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305028 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005029
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03005030 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02005031 intel_enable_pipe(intel_crtc);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03005032
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005033 if (intel_crtc->config->has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02005034 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005035
Jani Nikulaa65347b2015-11-27 12:21:46 +02005036 if (intel_crtc->config->dp_encoder_is_mst)
Dave Airlie0e32b392014-05-02 14:02:48 +10005037 intel_ddi_set_vc_payload_alloc(crtc, true);
5038
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005039 assert_vblank_disabled(crtc);
5040 drm_crtc_vblank_on(crtc);
5041
Jani Nikula8807e552013-08-30 19:40:32 +03005042 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005043 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03005044 intel_opregion_notify_encoder(encoder, true);
5045 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005046
Daniel Vetter6b698512015-11-28 11:05:39 +01005047 if (intel_crtc->config->has_pch_encoder) {
5048 intel_wait_for_vblank(dev, pipe);
5049 intel_wait_for_vblank(dev, pipe);
5050 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005051 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5052 true);
Daniel Vetter6b698512015-11-28 11:05:39 +01005053 }
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005054
Paulo Zanonie4916942013-09-20 16:21:19 -03005055 /* If we change the relative order between pipe/planes enabling, we need
5056 * to change the workaround. */
Maarten Lankhorst99d736a2015-06-01 12:50:09 +02005057 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5058 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5059 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5060 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5061 }
Paulo Zanonid029bca2015-10-15 10:44:46 -03005062
5063 intel_fbc_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005064}
5065
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005066static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005067{
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 int pipe = crtc->pipe;
5071
5072 /* To avoid upsetting the power well on haswell only disable the pfit if
5073 * it's in use. The hw state code will make sure we get this right. */
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005074 if (force || crtc->config->pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02005075 I915_WRITE(PF_CTL(pipe), 0);
5076 I915_WRITE(PF_WIN_POS(pipe), 0);
5077 I915_WRITE(PF_WIN_SZ(pipe), 0);
5078 }
5079}
5080
Jesse Barnes6be4a602010-09-10 10:26:01 -07005081static void ironlake_crtc_disable(struct drm_crtc *crtc)
5082{
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02005086 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005087 int pipe = intel_crtc->pipe;
Jesse Barnes6be4a602010-09-10 10:26:01 -07005088
Ville Syrjälä37ca8d42015-10-30 19:20:27 +02005089 if (intel_crtc->config->has_pch_encoder)
5090 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5091
Daniel Vetterea9d7582012-07-10 10:42:52 +02005092 for_each_encoder_on_crtc(dev, crtc, encoder)
5093 encoder->disable(encoder);
5094
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005095 drm_crtc_vblank_off(crtc);
5096 assert_vblank_disabled(crtc);
5097
Ville Syrjälä3860b2e2015-11-20 22:09:18 +02005098 /*
5099 * Sometimes spurious CPU pipe underruns happen when the
5100 * pipe is already disabled, but FDI RX/TX is still enabled.
5101 * Happens at least with VGA+HDMI cloning. Suppress them.
5102 */
5103 if (intel_crtc->config->has_pch_encoder)
5104 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5105
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005106 intel_disable_pipe(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005107
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005108 ironlake_pfit_disable(intel_crtc, false);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005109
Ville Syrjälä3860b2e2015-11-20 22:09:18 +02005110 if (intel_crtc->config->has_pch_encoder) {
Ville Syrjälä5a74f702015-05-05 17:17:38 +03005111 ironlake_fdi_disable(crtc);
Ville Syrjälä3860b2e2015-11-20 22:09:18 +02005112 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5113 }
Ville Syrjälä5a74f702015-05-05 17:17:38 +03005114
Daniel Vetterbf49ec82012-09-06 22:15:40 +02005115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005118
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005119 if (intel_crtc->config->has_pch_encoder) {
Daniel Vetterd925c592013-06-05 13:34:04 +02005120 ironlake_disable_pch_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005121
Daniel Vetterd925c592013-06-05 13:34:04 +02005122 if (HAS_PCH_CPT(dev)) {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02005123 i915_reg_t reg;
5124 u32 temp;
5125
Daniel Vetterd925c592013-06-05 13:34:04 +02005126 /* disable TRANS_DP_CTL */
5127 reg = TRANS_DP_CTL(pipe);
5128 temp = I915_READ(reg);
5129 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5130 TRANS_DP_PORT_SEL_MASK);
5131 temp |= TRANS_DP_PORT_SEL_NONE;
5132 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005133
Daniel Vetterd925c592013-06-05 13:34:04 +02005134 /* disable DPLL_SEL */
5135 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02005136 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02005137 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005138 }
Daniel Vetterd925c592013-06-05 13:34:04 +02005139
Daniel Vetterd925c592013-06-05 13:34:04 +02005140 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005141 }
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005142
5143 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
Paulo Zanonid029bca2015-10-15 10:44:46 -03005144
5145 intel_fbc_disable_crtc(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07005146}
5147
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005148static void haswell_crtc_disable(struct drm_crtc *crtc)
5149{
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153 struct intel_encoder *encoder;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005154 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005155
Ville Syrjäläd2d65402015-10-29 21:25:53 +02005156 if (intel_crtc->config->has_pch_encoder)
5157 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5158 false);
5159
Jani Nikula8807e552013-08-30 19:40:32 +03005160 for_each_encoder_on_crtc(dev, crtc, encoder) {
5161 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005162 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03005163 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005164
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01005165 drm_crtc_vblank_off(crtc);
5166 assert_vblank_disabled(crtc);
5167
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03005168 intel_disable_pipe(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005169
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005170 if (intel_crtc->config->dp_encoder_is_mst)
Ville Syrjäläa4bf2142014-08-18 21:27:34 +03005171 intel_ddi_set_vc_payload_alloc(crtc, false);
5172
Jani Nikulaa65347b2015-11-27 12:21:46 +02005173 if (!intel_crtc->config->has_dsi_encoder)
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305174 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005175
Rodrigo Vivi1c132b42015-09-02 15:19:26 -07005176 if (INTEL_INFO(dev)->gen >= 9)
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02005177 skylake_scaler_disable(intel_crtc);
Jesse Barnesff6d9f52015-01-21 17:19:54 -08005178 else
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +02005179 ironlake_pfit_disable(intel_crtc, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005180
Jani Nikulaa65347b2015-11-27 12:21:46 +02005181 if (!intel_crtc->config->has_dsi_encoder)
Shashank Sharma7d4aefd2015-10-01 22:23:49 +05305182 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005183
Imre Deak97b040a2014-06-25 22:01:50 +03005184 for_each_encoder_on_crtc(dev, crtc, encoder)
5185 if (encoder->post_disable)
5186 encoder->post_disable(encoder);
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005187
Ville Syrjälä92966a32015-12-08 16:05:48 +02005188 if (intel_crtc->config->has_pch_encoder) {
5189 lpt_disable_pch_transcoder(dev_priv);
Ville Syrjälä503a74e2015-12-04 22:22:14 +02005190 lpt_disable_iclkip(dev_priv);
Ville Syrjälä92966a32015-12-08 16:05:48 +02005191 intel_ddi_fdi_disable(crtc);
5192
Ville Syrjälä81b088c2015-10-30 19:21:31 +02005193 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5194 true);
Ville Syrjälä92966a32015-12-08 16:05:48 +02005195 }
Paulo Zanonid029bca2015-10-15 10:44:46 -03005196
5197 intel_fbc_disable_crtc(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02005198}
5199
Jesse Barnes2dd24552013-04-25 12:55:01 -07005200static void i9xx_pfit_enable(struct intel_crtc *crtc)
5201{
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005204 struct intel_crtc_state *pipe_config = crtc->config;
Jesse Barnes2dd24552013-04-25 12:55:01 -07005205
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02005206 if (!pipe_config->gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07005207 return;
5208
Daniel Vetterc0b03412013-05-28 12:05:54 +02005209 /*
5210 * The panel fitter should only be adjusted whilst the pipe is disabled,
5211 * according to register description and PRM.
5212 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07005213 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5214 assert_pipe_disabled(dev_priv, crtc->pipe);
5215
Jesse Barnesb074cec2013-04-25 12:55:02 -07005216 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5217 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02005218
5219 /* Border color in case we don't scale up to the full screen. Black by
5220 * default, change to something else for debugging. */
5221 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07005222}
5223
Dave Airlied05410f2014-06-05 13:22:59 +10005224static enum intel_display_power_domain port_to_power_domain(enum port port)
5225{
5226 switch (port) {
5227 case PORT_A:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005228 return POWER_DOMAIN_PORT_DDI_A_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005229 case PORT_B:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005230 return POWER_DOMAIN_PORT_DDI_B_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005231 case PORT_C:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005232 return POWER_DOMAIN_PORT_DDI_C_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005233 case PORT_D:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005234 return POWER_DOMAIN_PORT_DDI_D_LANES;
Xiong Zhangd8e19f92015-08-13 18:00:12 +08005235 case PORT_E:
Patrik Jakobsson6331a702015-11-09 16:48:21 +01005236 return POWER_DOMAIN_PORT_DDI_E_LANES;
Dave Airlied05410f2014-06-05 13:22:59 +10005237 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005238 MISSING_CASE(port);
Dave Airlied05410f2014-06-05 13:22:59 +10005239 return POWER_DOMAIN_PORT_OTHER;
5240 }
5241}
5242
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005243static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5244{
5245 switch (port) {
5246 case PORT_A:
5247 return POWER_DOMAIN_AUX_A;
5248 case PORT_B:
5249 return POWER_DOMAIN_AUX_B;
5250 case PORT_C:
5251 return POWER_DOMAIN_AUX_C;
5252 case PORT_D:
5253 return POWER_DOMAIN_AUX_D;
5254 case PORT_E:
5255 /* FIXME: Check VBT for actual wiring of PORT E */
5256 return POWER_DOMAIN_AUX_D;
5257 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005258 MISSING_CASE(port);
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005259 return POWER_DOMAIN_AUX_A;
5260 }
5261}
5262
Imre Deak319be8a2014-03-04 19:22:57 +02005263enum intel_display_power_domain
5264intel_display_port_power_domain(struct intel_encoder *intel_encoder)
Imre Deak77d22dc2014-03-05 16:20:52 +02005265{
Imre Deak319be8a2014-03-04 19:22:57 +02005266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5268
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Dave Airlied05410f2014-06-05 13:22:59 +10005277 return port_to_power_domain(intel_dig_port->port);
Dave Airlie0e32b392014-05-02 14:02:48 +10005278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
Imre Deak319be8a2014-03-04 19:22:57 +02005281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5285 default:
5286 return POWER_DOMAIN_PORT_OTHER;
5287 }
5288}
5289
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005290enum intel_display_power_domain
5291intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5292{
5293 struct drm_device *dev = intel_encoder->base.dev;
5294 struct intel_digital_port *intel_dig_port;
5295
5296 switch (intel_encoder->type) {
5297 case INTEL_OUTPUT_UNKNOWN:
Imre Deak651174a2015-11-18 15:57:24 +02005298 case INTEL_OUTPUT_HDMI:
5299 /*
5300 * Only DDI platforms should ever use these output types.
5301 * We can get here after the HDMI detect code has already set
5302 * the type of the shared encoder. Since we can't be sure
5303 * what's the status of the given connectors, play safe and
5304 * run the DP detection too.
5305 */
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005306 WARN_ON_ONCE(!HAS_DDI(dev));
5307 case INTEL_OUTPUT_DISPLAYPORT:
5308 case INTEL_OUTPUT_EDP:
5309 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5310 return port_to_aux_power_domain(intel_dig_port->port);
5311 case INTEL_OUTPUT_DP_MST:
5312 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5313 return port_to_aux_power_domain(intel_dig_port->port);
5314 default:
Imre Deakb9fec162015-11-18 15:57:25 +02005315 MISSING_CASE(intel_encoder->type);
Ville Syrjälä25f78f52015-11-16 15:01:04 +01005316 return POWER_DOMAIN_AUX_A;
5317 }
5318}
5319
Imre Deak319be8a2014-03-04 19:22:57 +02005320static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5321{
5322 struct drm_device *dev = crtc->dev;
5323 struct intel_encoder *intel_encoder;
5324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5325 enum pipe pipe = intel_crtc->pipe;
Imre Deak77d22dc2014-03-05 16:20:52 +02005326 unsigned long mask;
Ville Syrjälä1a70a7282015-10-29 21:25:50 +02005327 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
Imre Deak77d22dc2014-03-05 16:20:52 +02005328
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005329 if (!crtc->state->active)
5330 return 0;
5331
Imre Deak77d22dc2014-03-05 16:20:52 +02005332 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5333 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02005334 if (intel_crtc->config->pch_pfit.enabled ||
5335 intel_crtc->config->pch_pfit.force_thru)
Imre Deak77d22dc2014-03-05 16:20:52 +02005336 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5337
Imre Deak319be8a2014-03-04 19:22:57 +02005338 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5339 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5340
Imre Deak77d22dc2014-03-05 16:20:52 +02005341 return mask;
5342}
5343
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005344static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5345{
5346 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 enum intel_display_power_domain domain;
5349 unsigned long domains, new_domains, old_domains;
5350
5351 old_domains = intel_crtc->enabled_power_domains;
5352 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5353
5354 domains = new_domains & ~old_domains;
5355
5356 for_each_power_domain(domain, domains)
5357 intel_display_power_get(dev_priv, domain);
5358
5359 return old_domains & ~new_domains;
5360}
5361
5362static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5363 unsigned long domains)
5364{
5365 enum intel_display_power_domain domain;
5366
5367 for_each_power_domain(domain, domains)
5368 intel_display_power_put(dev_priv, domain);
5369}
5370
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +02005371static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
Imre Deak77d22dc2014-03-05 16:20:52 +02005372{
Ander Conselvan de Oliveira679dacd2015-03-20 16:18:15 +02005373 struct drm_device *dev = state->dev;
Imre Deak77d22dc2014-03-05 16:20:52 +02005374 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005375 unsigned long put_domains[I915_MAX_PIPES] = {};
5376 struct drm_crtc_state *crtc_state;
5377 struct drm_crtc *crtc;
5378 int i;
Imre Deak77d22dc2014-03-05 16:20:52 +02005379
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005380 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5381 if (needs_modeset(crtc->state))
5382 put_domains[to_intel_crtc(crtc)->pipe] =
5383 modeset_get_crtc_power_domains(crtc);
Imre Deak77d22dc2014-03-05 16:20:52 +02005384 }
5385
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02005386 if (dev_priv->display.modeset_commit_cdclk) {
5387 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5388
5389 if (cdclk != dev_priv->cdclk_freq &&
5390 !WARN_ON(!state->allow_modeset))
5391 dev_priv->display.modeset_commit_cdclk(state);
5392 }
Ville Syrjälä50f6e502014-11-06 14:49:12 +02005393
Maarten Lankhorst292b9902015-07-13 16:30:27 +02005394 for (i = 0; i < I915_MAX_PIPES; i++)
5395 if (put_domains[i])
5396 modeset_put_power_domains(dev_priv, put_domains[i]);
Imre Deak77d22dc2014-03-05 16:20:52 +02005397}
5398
Mika Kaholaadafdc62015-08-18 14:36:59 +03005399static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5400{
5401 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5402
5403 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5404 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5405 return max_cdclk_freq;
5406 else if (IS_CHERRYVIEW(dev_priv))
5407 return max_cdclk_freq*95/100;
5408 else if (INTEL_INFO(dev_priv)->gen < 4)
5409 return 2*max_cdclk_freq*90/100;
5410 else
5411 return max_cdclk_freq*90/100;
5412}
5413
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005414static void intel_update_max_cdclk(struct drm_device *dev)
5415{
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07005418 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005419 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5420
5421 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5422 dev_priv->max_cdclk_freq = 675000;
5423 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5424 dev_priv->max_cdclk_freq = 540000;
5425 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5426 dev_priv->max_cdclk_freq = 450000;
5427 else
5428 dev_priv->max_cdclk_freq = 337500;
5429 } else if (IS_BROADWELL(dev)) {
5430 /*
5431 * FIXME with extra cooling we can allow
5432 * 540 MHz for ULX and 675 Mhz for ULT.
5433 * How can we know if extra cooling is
5434 * available? PCI ID, VTB, something else?
5435 */
5436 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5437 dev_priv->max_cdclk_freq = 450000;
5438 else if (IS_BDW_ULX(dev))
5439 dev_priv->max_cdclk_freq = 450000;
5440 else if (IS_BDW_ULT(dev))
5441 dev_priv->max_cdclk_freq = 540000;
5442 else
5443 dev_priv->max_cdclk_freq = 675000;
Mika Kahola0904dea2015-06-12 10:11:32 +03005444 } else if (IS_CHERRYVIEW(dev)) {
5445 dev_priv->max_cdclk_freq = 320000;
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005446 } else if (IS_VALLEYVIEW(dev)) {
5447 dev_priv->max_cdclk_freq = 400000;
5448 } else {
5449 /* otherwise assume cdclk is fixed */
5450 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5451 }
5452
Mika Kaholaadafdc62015-08-18 14:36:59 +03005453 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5454
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005455 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5456 dev_priv->max_cdclk_freq);
Mika Kaholaadafdc62015-08-18 14:36:59 +03005457
5458 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5459 dev_priv->max_dotclk_freq);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005460}
5461
5462static void intel_update_cdclk(struct drm_device *dev)
5463{
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465
5466 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5467 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5468 dev_priv->cdclk_freq);
5469
5470 /*
5471 * Program the gmbus_freq based on the cdclk frequency.
5472 * BSpec erroneously claims we should aim for 4MHz, but
5473 * in fact 1MHz is the correct frequency.
5474 */
Wayne Boyer666a4532015-12-09 12:29:35 -08005475 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005476 /*
5477 * Program the gmbus_freq based on the cdclk frequency.
5478 * BSpec erroneously claims we should aim for 4MHz, but
5479 * in fact 1MHz is the correct frequency.
5480 */
5481 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5482 }
5483
5484 if (dev_priv->max_cdclk_freq == 0)
5485 intel_update_max_cdclk(dev);
5486}
5487
Damien Lespiau70d0c572015-06-04 18:21:29 +01005488static void broxton_set_cdclk(struct drm_device *dev, int frequency)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305489{
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 uint32_t divider;
5492 uint32_t ratio;
5493 uint32_t current_freq;
5494 int ret;
5495
5496 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5497 switch (frequency) {
5498 case 144000:
5499 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5500 ratio = BXT_DE_PLL_RATIO(60);
5501 break;
5502 case 288000:
5503 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5504 ratio = BXT_DE_PLL_RATIO(60);
5505 break;
5506 case 384000:
5507 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5508 ratio = BXT_DE_PLL_RATIO(60);
5509 break;
5510 case 576000:
5511 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5512 ratio = BXT_DE_PLL_RATIO(60);
5513 break;
5514 case 624000:
5515 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5516 ratio = BXT_DE_PLL_RATIO(65);
5517 break;
5518 case 19200:
5519 /*
5520 * Bypass frequency with DE PLL disabled. Init ratio, divider
5521 * to suppress GCC warning.
5522 */
5523 ratio = 0;
5524 divider = 0;
5525 break;
5526 default:
5527 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5528
5529 return;
5530 }
5531
5532 mutex_lock(&dev_priv->rps.hw_lock);
5533 /* Inform power controller of upcoming frequency change */
5534 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5535 0x80000000);
5536 mutex_unlock(&dev_priv->rps.hw_lock);
5537
5538 if (ret) {
5539 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5540 ret, frequency);
5541 return;
5542 }
5543
5544 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5545 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5546 current_freq = current_freq * 500 + 1000;
5547
5548 /*
5549 * DE PLL has to be disabled when
5550 * - setting to 19.2MHz (bypass, PLL isn't used)
5551 * - before setting to 624MHz (PLL needs toggling)
5552 * - before setting to any frequency from 624MHz (PLL needs toggling)
5553 */
5554 if (frequency == 19200 || frequency == 624000 ||
5555 current_freq == 624000) {
5556 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5557 /* Timeout 200us */
5558 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5559 1))
5560 DRM_ERROR("timout waiting for DE PLL unlock\n");
5561 }
5562
5563 if (frequency != 19200) {
5564 uint32_t val;
5565
5566 val = I915_READ(BXT_DE_PLL_CTL);
5567 val &= ~BXT_DE_PLL_RATIO_MASK;
5568 val |= ratio;
5569 I915_WRITE(BXT_DE_PLL_CTL, val);
5570
5571 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5572 /* Timeout 200us */
5573 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5574 DRM_ERROR("timeout waiting for DE PLL lock\n");
5575
5576 val = I915_READ(CDCLK_CTL);
5577 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5578 val |= divider;
5579 /*
5580 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5581 * enable otherwise.
5582 */
5583 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5584 if (frequency >= 500000)
5585 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5586
5587 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5588 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5589 val |= (frequency - 1000) / 500;
5590 I915_WRITE(CDCLK_CTL, val);
5591 }
5592
5593 mutex_lock(&dev_priv->rps.hw_lock);
5594 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5595 DIV_ROUND_UP(frequency, 25000));
5596 mutex_unlock(&dev_priv->rps.hw_lock);
5597
5598 if (ret) {
5599 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5600 ret, frequency);
5601 return;
5602 }
5603
Damien Lespiaua47871b2015-06-04 18:21:34 +01005604 intel_update_cdclk(dev);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305605}
5606
5607void broxton_init_cdclk(struct drm_device *dev)
5608{
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 uint32_t val;
5611
5612 /*
5613 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5614 * or else the reset will hang because there is no PCH to respond.
5615 * Move the handshake programming to initialization sequence.
5616 * Previously was left up to BIOS.
5617 */
5618 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5619 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5620 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5621
5622 /* Enable PG1 for cdclk */
5623 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5624
5625 /* check if cd clock is enabled */
5626 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5627 DRM_DEBUG_KMS("Display already initialized\n");
5628 return;
5629 }
5630
5631 /*
5632 * FIXME:
5633 * - The initial CDCLK needs to be read from VBT.
5634 * Need to make this change after VBT has changes for BXT.
5635 * - check if setting the max (or any) cdclk freq is really necessary
5636 * here, it belongs to modeset time
5637 */
5638 broxton_set_cdclk(dev, 624000);
5639
5640 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
Ville Syrjälä22e02c02015-05-06 14:28:57 +03005641 POSTING_READ(DBUF_CTL);
5642
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305643 udelay(10);
5644
5645 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5646 DRM_ERROR("DBuf power enable timeout!\n");
5647}
5648
5649void broxton_uninit_cdclk(struct drm_device *dev)
5650{
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652
5653 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
Ville Syrjälä22e02c02015-05-06 14:28:57 +03005654 POSTING_READ(DBUF_CTL);
5655
Vandana Kannanf8437dd12014-11-24 13:37:39 +05305656 udelay(10);
5657
5658 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5659 DRM_ERROR("DBuf power disable timeout!\n");
5660
5661 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5662 broxton_set_cdclk(dev, 19200);
5663
5664 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5665}
5666
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005667static const struct skl_cdclk_entry {
5668 unsigned int freq;
5669 unsigned int vco;
5670} skl_cdclk_frequencies[] = {
5671 { .freq = 308570, .vco = 8640 },
5672 { .freq = 337500, .vco = 8100 },
5673 { .freq = 432000, .vco = 8640 },
5674 { .freq = 450000, .vco = 8100 },
5675 { .freq = 540000, .vco = 8100 },
5676 { .freq = 617140, .vco = 8640 },
5677 { .freq = 675000, .vco = 8100 },
5678};
5679
5680static unsigned int skl_cdclk_decimal(unsigned int freq)
5681{
5682 return (freq - 1000) / 500;
5683}
5684
5685static unsigned int skl_cdclk_get_vco(unsigned int freq)
5686{
5687 unsigned int i;
5688
5689 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5690 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5691
5692 if (e->freq == freq)
5693 return e->vco;
5694 }
5695
5696 return 8100;
5697}
5698
5699static void
5700skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5701{
5702 unsigned int min_freq;
5703 u32 val;
5704
5705 /* select the minimum CDCLK before enabling DPLL 0 */
5706 val = I915_READ(CDCLK_CTL);
5707 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5708 val |= CDCLK_FREQ_337_308;
5709
5710 if (required_vco == 8640)
5711 min_freq = 308570;
5712 else
5713 min_freq = 337500;
5714
5715 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5716
5717 I915_WRITE(CDCLK_CTL, val);
5718 POSTING_READ(CDCLK_CTL);
5719
5720 /*
5721 * We always enable DPLL0 with the lowest link rate possible, but still
5722 * taking into account the VCO required to operate the eDP panel at the
5723 * desired frequency. The usual DP link rates operate with a VCO of
5724 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5725 * The modeset code is responsible for the selection of the exact link
5726 * rate later on, with the constraint of choosing a frequency that
5727 * works with required_vco.
5728 */
5729 val = I915_READ(DPLL_CTRL1);
5730
5731 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5732 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5733 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5734 if (required_vco == 8640)
5735 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5736 SKL_DPLL0);
5737 else
5738 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5739 SKL_DPLL0);
5740
5741 I915_WRITE(DPLL_CTRL1, val);
5742 POSTING_READ(DPLL_CTRL1);
5743
5744 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5745
5746 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5747 DRM_ERROR("DPLL0 not locked\n");
5748}
5749
5750static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5751{
5752 int ret;
5753 u32 val;
5754
5755 /* inform PCU we want to change CDCLK */
5756 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5757 mutex_lock(&dev_priv->rps.hw_lock);
5758 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5759 mutex_unlock(&dev_priv->rps.hw_lock);
5760
5761 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5762}
5763
5764static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5765{
5766 unsigned int i;
5767
5768 for (i = 0; i < 15; i++) {
5769 if (skl_cdclk_pcu_ready(dev_priv))
5770 return true;
5771 udelay(10);
5772 }
5773
5774 return false;
5775}
5776
5777static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5778{
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005779 struct drm_device *dev = dev_priv->dev;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005780 u32 freq_select, pcu_ack;
5781
5782 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5783
5784 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5785 DRM_ERROR("failed to inform PCU about cdclk change\n");
5786 return;
5787 }
5788
5789 /* set CDCLK_CTL */
5790 switch(freq) {
5791 case 450000:
5792 case 432000:
5793 freq_select = CDCLK_FREQ_450_432;
5794 pcu_ack = 1;
5795 break;
5796 case 540000:
5797 freq_select = CDCLK_FREQ_540;
5798 pcu_ack = 2;
5799 break;
5800 case 308570:
5801 case 337500:
5802 default:
5803 freq_select = CDCLK_FREQ_337_308;
5804 pcu_ack = 0;
5805 break;
5806 case 617140:
5807 case 675000:
5808 freq_select = CDCLK_FREQ_675_617;
5809 pcu_ack = 3;
5810 break;
5811 }
5812
5813 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5814 POSTING_READ(CDCLK_CTL);
5815
5816 /* inform PCU of the change */
5817 mutex_lock(&dev_priv->rps.hw_lock);
5818 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5819 mutex_unlock(&dev_priv->rps.hw_lock);
Damien Lespiau560a7ae2015-06-04 18:21:33 +01005820
5821 intel_update_cdclk(dev);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005822}
5823
5824void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5825{
5826 /* disable DBUF power */
5827 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5828 POSTING_READ(DBUF_CTL);
5829
5830 udelay(10);
5831
5832 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5833 DRM_ERROR("DBuf power disable timeout\n");
5834
Imre Deakab96c1ee2015-11-04 19:24:18 +02005835 /* disable DPLL0 */
5836 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5837 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5838 DRM_ERROR("Couldn't disable DPLL0\n");
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005839}
5840
5841void skl_init_cdclk(struct drm_i915_private *dev_priv)
5842{
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005843 unsigned int required_vco;
5844
Gary Wang39d9b852015-08-28 16:40:34 +08005845 /* DPLL0 not enabled (happens on early BIOS versions) */
5846 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5847 /* enable DPLL0 */
5848 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5849 skl_dpll0_enable(dev_priv, required_vco);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005850 }
5851
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01005852 /* set CDCLK to the frequency the BIOS chose */
5853 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5854
5855 /* enable DBUF power */
5856 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5857 POSTING_READ(DBUF_CTL);
5858
5859 udelay(10);
5860
5861 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5862 DRM_ERROR("DBuf power enable timeout\n");
5863}
5864
Shobhit Kumarc73666f2015-10-20 18:13:12 +05305865int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5866{
5867 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5868 uint32_t cdctl = I915_READ(CDCLK_CTL);
5869 int freq = dev_priv->skl_boot_cdclk;
5870
Shobhit Kumarf1b391a2015-11-05 18:05:32 +05305871 /*
5872 * check if the pre-os intialized the display
5873 * There is SWF18 scratchpad register defined which is set by the
5874 * pre-os which can be used by the OS drivers to check the status
5875 */
5876 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5877 goto sanitize;
5878
Shobhit Kumarc73666f2015-10-20 18:13:12 +05305879 /* Is PLL enabled and locked ? */
5880 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5881 goto sanitize;
5882
5883 /* DPLL okay; verify the cdclock
5884 *
5885 * Noticed in some instances that the freq selection is correct but
5886 * decimal part is programmed wrong from BIOS where pre-os does not
5887 * enable display. Verify the same as well.
5888 */
5889 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5890 /* All well; nothing to sanitize */
5891 return false;
5892sanitize:
5893 /*
5894 * As of now initialize with max cdclk till
5895 * we get dynamic cdclk support
5896 * */
5897 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5898 skl_init_cdclk(dev_priv);
5899
5900 /* we did have to sanitize */
5901 return true;
5902}
5903
Jesse Barnes30a970c2013-11-04 13:48:12 -08005904/* Adjust CDclk dividers to allow high res or save power if possible */
5905static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5906{
5907 struct drm_i915_private *dev_priv = dev->dev_private;
5908 u32 val, cmd;
5909
Vandana Kannan164dfd22014-11-24 13:37:41 +05305910 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5911 != dev_priv->cdclk_freq);
Imre Deakd60c4472014-03-27 17:45:10 +02005912
Ville Syrjälädfcab172014-06-13 13:37:47 +03005913 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
Jesse Barnes30a970c2013-11-04 13:48:12 -08005914 cmd = 2;
Ville Syrjälädfcab172014-06-13 13:37:47 +03005915 else if (cdclk == 266667)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005916 cmd = 1;
5917 else
5918 cmd = 0;
5919
5920 mutex_lock(&dev_priv->rps.hw_lock);
5921 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5922 val &= ~DSPFREQGUAR_MASK;
5923 val |= (cmd << DSPFREQGUAR_SHIFT);
5924 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5925 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5926 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5927 50)) {
5928 DRM_ERROR("timed out waiting for CDclk change\n");
5929 }
5930 mutex_unlock(&dev_priv->rps.hw_lock);
5931
Ville Syrjälä54433e92015-05-26 20:42:31 +03005932 mutex_lock(&dev_priv->sb_lock);
5933
Ville Syrjälädfcab172014-06-13 13:37:47 +03005934 if (cdclk == 400000) {
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005935 u32 divider;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005936
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03005937 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005938
Jesse Barnes30a970c2013-11-04 13:48:12 -08005939 /* adjust cdclk divider */
5940 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
Vandana Kannan87d5d252015-09-24 23:29:17 +03005941 val &= ~CCK_FREQUENCY_VALUES;
Jesse Barnes30a970c2013-11-04 13:48:12 -08005942 val |= divider;
5943 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
Ville Syrjäläa877e802014-06-13 13:37:52 +03005944
5945 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
Vandana Kannan87d5d252015-09-24 23:29:17 +03005946 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
Ville Syrjäläa877e802014-06-13 13:37:52 +03005947 50))
5948 DRM_ERROR("timed out waiting for CDclk change\n");
Jesse Barnes30a970c2013-11-04 13:48:12 -08005949 }
5950
Jesse Barnes30a970c2013-11-04 13:48:12 -08005951 /* adjust self-refresh exit latency value */
5952 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5953 val &= ~0x7f;
5954
5955 /*
5956 * For high bandwidth configs, we set a higher latency in the bunit
5957 * so that the core display fetch happens in time to avoid underruns.
5958 */
Ville Syrjälädfcab172014-06-13 13:37:47 +03005959 if (cdclk == 400000)
Jesse Barnes30a970c2013-11-04 13:48:12 -08005960 val |= 4500 / 250; /* 4.5 usec */
5961 else
5962 val |= 3000 / 250; /* 3.0 usec */
5963 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
Ville Syrjälä54433e92015-05-26 20:42:31 +03005964
Ville Syrjäläa5805162015-05-26 20:42:30 +03005965 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005966
Ville Syrjäläb6283052015-06-03 15:45:07 +03005967 intel_update_cdclk(dev);
Jesse Barnes30a970c2013-11-04 13:48:12 -08005968}
5969
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005970static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5971{
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 u32 val, cmd;
5974
Vandana Kannan164dfd22014-11-24 13:37:41 +05305975 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5976 != dev_priv->cdclk_freq);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005977
5978 switch (cdclk) {
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005979 case 333333:
5980 case 320000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005981 case 266667:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005982 case 200000:
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005983 break;
5984 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01005985 MISSING_CASE(cdclk);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005986 return;
5987 }
5988
Ville Syrjälä9d0d3fd2015-03-02 20:07:17 +02005989 /*
5990 * Specs are full of misinformation, but testing on actual
5991 * hardware has shown that we just need to write the desired
5992 * CCK divider into the Punit register.
5993 */
5994 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5995
Ville Syrjälä383c5a62014-06-28 02:03:57 +03005996 mutex_lock(&dev_priv->rps.hw_lock);
5997 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5998 val &= ~DSPFREQGUAR_MASK_CHV;
5999 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6000 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6001 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6002 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6003 50)) {
6004 DRM_ERROR("timed out waiting for CDclk change\n");
6005 }
6006 mutex_unlock(&dev_priv->rps.hw_lock);
6007
Ville Syrjäläb6283052015-06-03 15:45:07 +03006008 intel_update_cdclk(dev);
Ville Syrjälä383c5a62014-06-28 02:03:57 +03006009}
6010
Jesse Barnes30a970c2013-11-04 13:48:12 -08006011static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6012 int max_pixclk)
6013{
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03006014 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006015 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006016
Jesse Barnes30a970c2013-11-04 13:48:12 -08006017 /*
6018 * Really only a few cases to deal with, as only 4 CDclks are supported:
6019 * 200MHz
6020 * 267MHz
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006021 * 320/333MHz (depends on HPLL freq)
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006022 * 400MHz (VLV only)
6023 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6024 * of the lower bin and adjust if needed.
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006025 *
6026 * We seem to get an unstable or solid color picture at 200MHz.
6027 * Not sure what's wrong. For now use 200MHz only when all pipes
6028 * are off.
Jesse Barnes30a970c2013-11-04 13:48:12 -08006029 */
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006030 if (!IS_CHERRYVIEW(dev_priv) &&
6031 max_pixclk > freq_320*limit/100)
Ville Syrjälädfcab172014-06-13 13:37:47 +03006032 return 400000;
Ville Syrjälä6cca3192015-03-02 20:07:16 +02006033 else if (max_pixclk > 266667*limit/100)
Ville Syrjälä29dc7ef2014-06-13 13:37:50 +03006034 return freq_320;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006035 else if (max_pixclk > 0)
Ville Syrjälädfcab172014-06-13 13:37:47 +03006036 return 266667;
Ville Syrjäläe37c67a2014-06-13 13:37:51 +03006037 else
6038 return 200000;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006039}
6040
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306041static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6042 int max_pixclk)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006043{
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306044 /*
6045 * FIXME:
6046 * - remove the guardband, it's not needed on BXT
6047 * - set 19.2MHz bypass frequency if there are no active pipes
6048 */
6049 if (max_pixclk > 576000*9/10)
6050 return 624000;
6051 else if (max_pixclk > 384000*9/10)
6052 return 576000;
6053 else if (max_pixclk > 288000*9/10)
6054 return 384000;
6055 else if (max_pixclk > 144000*9/10)
6056 return 288000;
6057 else
6058 return 144000;
6059}
6060
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03006061/* Compute the max pixel clock for new configuration. Uses atomic state if
6062 * that's non-NULL, look at current state otherwise. */
6063static int intel_mode_max_pixclk(struct drm_device *dev,
6064 struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006065{
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006066 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6067 struct drm_i915_private *dev_priv = dev->dev_private;
6068 struct drm_crtc *crtc;
6069 struct drm_crtc_state *crtc_state;
6070 unsigned max_pixclk = 0, i;
6071 enum pipe pipe;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006072
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006073 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6074 sizeof(intel_state->min_pixclk));
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006075
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006076 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6077 int pixclk = 0;
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006078
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006079 if (crtc_state->enable)
6080 pixclk = crtc_state->adjusted_mode.crtc_clock;
6081
6082 intel_state->min_pixclk[i] = pixclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006083 }
6084
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006085 if (!intel_state->active_crtcs)
6086 return 0;
6087
6088 for_each_pipe(dev_priv, pipe)
6089 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6090
Jesse Barnes30a970c2013-11-04 13:48:12 -08006091 return max_pixclk;
6092}
6093
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006094static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006095{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006096 struct drm_device *dev = state->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 int max_pixclk = intel_mode_max_pixclk(dev, state);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006099
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006100 if (max_pixclk < 0)
6101 return max_pixclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006102
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006103 to_intel_atomic_state(state)->cdclk =
6104 valleyview_calc_cdclk(dev_priv, max_pixclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05306105
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006106 return 0;
6107}
Jesse Barnes30a970c2013-11-04 13:48:12 -08006108
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006109static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6110{
6111 struct drm_device *dev = state->dev;
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113 int max_pixclk = intel_mode_max_pixclk(dev, state);
Maarten Lankhorst85a96e72015-06-01 12:49:53 +02006114
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006115 if (max_pixclk < 0)
6116 return max_pixclk;
Maarten Lankhorst85a96e72015-06-01 12:49:53 +02006117
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006118 to_intel_atomic_state(state)->cdclk =
6119 broxton_calc_cdclk(dev_priv, max_pixclk);
Maarten Lankhorst85a96e72015-06-01 12:49:53 +02006120
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006121 return 0;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006122}
6123
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006124static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6125{
6126 unsigned int credits, default_credits;
6127
6128 if (IS_CHERRYVIEW(dev_priv))
6129 default_credits = PFI_CREDIT(12);
6130 else
6131 default_credits = PFI_CREDIT(8);
6132
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03006133 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006134 /* CHV suggested value is 31 or 63 */
6135 if (IS_CHERRYVIEW(dev_priv))
Ville Syrjäläfcc00082015-05-26 20:22:40 +03006136 credits = PFI_CREDIT_63;
Vidya Srinivas1e69cd72015-03-05 21:19:50 +02006137 else
6138 credits = PFI_CREDIT(15);
6139 } else {
6140 credits = default_credits;
6141 }
6142
6143 /*
6144 * WA - write default credits before re-programming
6145 * FIXME: should we also set the resend bit here?
6146 */
6147 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6148 default_credits);
6149
6150 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6151 credits | PFI_CREDIT_RESEND);
6152
6153 /*
6154 * FIXME is this guaranteed to clear
6155 * immediately or should we poll for it?
6156 */
6157 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6158}
6159
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006160static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Jesse Barnes30a970c2013-11-04 13:48:12 -08006161{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03006162 struct drm_device *dev = old_state->dev;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006163 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006164 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes30a970c2013-11-04 13:48:12 -08006165
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006166 /*
6167 * FIXME: We can end up here with all power domains off, yet
6168 * with a CDCLK frequency other than the minimum. To account
6169 * for this take the PIPE-A power domain, which covers the HW
6170 * blocks needed for the following programming. This can be
6171 * removed once it's guaranteed that we get here either with
6172 * the minimum CDCLK set, or the required power domains
6173 * enabled.
6174 */
6175 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
Ander Conselvan de Oliveira304603f2015-04-02 14:47:56 +03006176
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006177 if (IS_CHERRYVIEW(dev))
6178 cherryview_set_cdclk(dev, req_cdclk);
6179 else
6180 valleyview_set_cdclk(dev, req_cdclk);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006181
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006182 vlv_program_pfi_credits(dev_priv);
Imre Deak738c05c2014-11-19 16:25:37 +02006183
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02006184 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
Jesse Barnes30a970c2013-11-04 13:48:12 -08006185}
6186
Jesse Barnes89b667f2013-04-18 14:51:36 -07006187static void valleyview_crtc_enable(struct drm_crtc *crtc)
6188{
6189 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02006190 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6192 struct intel_encoder *encoder;
6193 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07006194
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02006195 if (WARN_ON(intel_crtc->active))
Jesse Barnes89b667f2013-04-18 14:51:36 -07006196 return;
6197
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006198 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05306199 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006200
6201 intel_set_pipe_timings(intel_crtc);
6202
Ville Syrjäläc14b0482014-10-16 20:52:34 +03006203 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6204 struct drm_i915_private *dev_priv = dev->dev_private;
6205
6206 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6207 I915_WRITE(CHV_CANVAS(pipe), 0);
6208 }
6209
Daniel Vetter5b18e572014-04-24 23:55:06 +02006210 i9xx_set_pipeconf(intel_crtc);
6211
Jesse Barnes89b667f2013-04-18 14:51:36 -07006212 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07006213
Daniel Vettera72e4c92014-09-30 10:56:47 +02006214 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006215
Jesse Barnes89b667f2013-04-18 14:51:36 -07006216 for_each_encoder_on_crtc(dev, crtc, encoder)
6217 if (encoder->pre_pll_enable)
6218 encoder->pre_pll_enable(encoder);
6219
Jani Nikulaa65347b2015-11-27 12:21:46 +02006220 if (!intel_crtc->config->has_dsi_encoder) {
Ville Syrjäläc0b4c662015-07-08 23:45:52 +03006221 if (IS_CHERRYVIEW(dev)) {
6222 chv_prepare_pll(intel_crtc, intel_crtc->config);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006223 chv_enable_pll(intel_crtc, intel_crtc->config);
Ville Syrjäläc0b4c662015-07-08 23:45:52 +03006224 } else {
6225 vlv_prepare_pll(intel_crtc, intel_crtc->config);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006226 vlv_enable_pll(intel_crtc, intel_crtc->config);
Ville Syrjäläc0b4c662015-07-08 23:45:52 +03006227 }
Chon Ming Lee9d556c92014-05-02 14:27:47 +03006228 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07006229
6230 for_each_encoder_on_crtc(dev, crtc, encoder)
6231 if (encoder->pre_enable)
6232 encoder->pre_enable(encoder);
6233
Jesse Barnes2dd24552013-04-25 12:55:01 -07006234 i9xx_pfit_enable(intel_crtc);
6235
Ville Syrjälä63cbb072013-06-04 13:48:59 +03006236 intel_crtc_load_lut(crtc);
6237
Paulo Zanonie1fdc472014-01-17 13:51:12 -02006238 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02006239
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006240 assert_vblank_disabled(crtc);
6241 drm_crtc_vblank_on(crtc);
6242
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01006243 for_each_encoder_on_crtc(dev, crtc, encoder)
6244 encoder->enable(encoder);
Jesse Barnes89b667f2013-04-18 14:51:36 -07006245}
6246
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006247static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6248{
6249 struct drm_device *dev = crtc->base.dev;
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006252 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6253 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006254}
6255
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006256static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08006257{
6258 struct drm_device *dev = crtc->dev;
Daniel Vettera72e4c92014-09-30 10:56:47 +02006259 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006261 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006262 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08006263
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +02006264 if (WARN_ON(intel_crtc->active))
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006265 return;
6266
Daniel Vetterf13c2ef2014-04-24 23:55:10 +02006267 i9xx_set_pll_dividers(intel_crtc);
6268
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006269 if (intel_crtc->config->has_dp_encoder)
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05306270 intel_dp_set_m_n(intel_crtc, M1_N1);
Daniel Vetter5b18e572014-04-24 23:55:06 +02006271
6272 intel_set_pipe_timings(intel_crtc);
6273
Daniel Vetter5b18e572014-04-24 23:55:06 +02006274 i9xx_set_pipeconf(intel_crtc);
6275
Chris Wilsonf7abfe82010-09-13 14:19:16 +01006276 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01006277
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006278 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02006279 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006280
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02006281 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02006282 if (encoder->pre_enable)
6283 encoder->pre_enable(encoder);
6284
Daniel Vetterf6736a12013-06-05 13:34:30 +02006285 i9xx_enable_pll(intel_crtc);
6286
Jesse Barnes2dd24552013-04-25 12:55:01 -07006287 i9xx_pfit_enable(intel_crtc);
6288
Ville Syrjälä63cbb072013-06-04 13:48:59 +03006289 intel_crtc_load_lut(crtc);
6290
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03006291 intel_update_watermarks(crtc);
Paulo Zanonie1fdc472014-01-17 13:51:12 -02006292 intel_enable_pipe(intel_crtc);
Daniel Vetterbe6a6f82014-04-15 18:41:22 +02006293
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006294 assert_vblank_disabled(crtc);
6295 drm_crtc_vblank_on(crtc);
6296
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01006297 for_each_encoder_on_crtc(dev, crtc, encoder)
6298 encoder->enable(encoder);
Paulo Zanonid029bca2015-10-15 10:44:46 -03006299
6300 intel_fbc_enable(intel_crtc);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006301}
6302
Daniel Vetter87476d62013-04-11 16:29:06 +02006303static void i9xx_pfit_disable(struct intel_crtc *crtc)
6304{
6305 struct drm_device *dev = crtc->base.dev;
6306 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02006307
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02006308 if (!crtc->config->gmch_pfit.control)
Daniel Vetter328d8e82013-05-08 10:36:31 +02006309 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02006310
6311 assert_pipe_disabled(dev_priv, crtc->pipe);
6312
Daniel Vetter328d8e82013-05-08 10:36:31 +02006313 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6314 I915_READ(PFIT_CONTROL));
6315 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02006316}
6317
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006318static void i9xx_crtc_disable(struct drm_crtc *crtc)
6319{
6320 struct drm_device *dev = crtc->dev;
6321 struct drm_i915_private *dev_priv = dev->dev_private;
6322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006323 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006324 int pipe = intel_crtc->pipe;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02006325
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006326 /*
6327 * On gen2 planes are double buffered but the pipe isn't, so we must
6328 * wait for planes to fully turn off before disabling the pipe.
Imre Deak564ed192014-06-13 14:54:21 +03006329 * We also need to wait on all gmch platforms because of the
6330 * self-refresh mode constraint explained above.
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006331 */
Imre Deak564ed192014-06-13 14:54:21 +03006332 intel_wait_for_vblank(dev, pipe);
Ville Syrjälä6304cd92014-04-25 13:30:12 +03006333
Ville Syrjälä4b3a9522014-08-14 22:04:37 +03006334 for_each_encoder_on_crtc(dev, crtc, encoder)
6335 encoder->disable(encoder);
6336
Daniel Vetterf9b61ff2015-01-07 13:54:39 +01006337 drm_crtc_vblank_off(crtc);
6338 assert_vblank_disabled(crtc);
6339
Ville Syrjälä575f7ab2014-08-15 01:21:56 +03006340 intel_disable_pipe(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006341
Daniel Vetter87476d62013-04-11 16:29:06 +02006342 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02006343
Jesse Barnes89b667f2013-04-18 14:51:36 -07006344 for_each_encoder_on_crtc(dev, crtc, encoder)
6345 if (encoder->post_disable)
6346 encoder->post_disable(encoder);
6347
Jani Nikulaa65347b2015-11-27 12:21:46 +02006348 if (!intel_crtc->config->has_dsi_encoder) {
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006349 if (IS_CHERRYVIEW(dev))
6350 chv_disable_pll(dev_priv, pipe);
6351 else if (IS_VALLEYVIEW(dev))
6352 vlv_disable_pll(dev_priv, pipe);
6353 else
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03006354 i9xx_disable_pll(intel_crtc);
Chon Ming Lee076ed3b2014-04-09 13:28:17 +03006355 }
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006356
Ville Syrjäläd6db9952015-07-08 23:45:49 +03006357 for_each_encoder_on_crtc(dev, crtc, encoder)
6358 if (encoder->post_pll_disable)
6359 encoder->post_pll_disable(encoder);
6360
Ville Syrjälä4a3436e2014-05-16 19:40:25 +03006361 if (!IS_GEN2(dev))
Daniel Vettera72e4c92014-09-30 10:56:47 +02006362 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
Paulo Zanonid029bca2015-10-15 10:44:46 -03006363
6364 intel_fbc_disable_crtc(intel_crtc);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07006365}
6366
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006367static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006368{
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006370 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006371 enum intel_display_power_domain domain;
6372 unsigned long domains;
Daniel Vetter976f8a22012-07-08 22:34:21 +02006373
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006374 if (!intel_crtc->active)
6375 return;
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006376
Maarten Lankhorsta5392052015-06-15 12:33:52 +02006377 if (to_intel_plane_state(crtc->primary->state)->visible) {
Maarten Lankhorstfc32b1f2015-10-19 17:09:23 +02006378 WARN_ON(intel_crtc->unpin_work);
6379
Maarten Lankhorsta5392052015-06-15 12:33:52 +02006380 intel_pre_disable_primary(crtc);
Maarten Lankhorst54a419612015-11-23 10:25:28 +01006381
6382 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6383 to_intel_plane_state(crtc->primary->state)->visible = false;
Maarten Lankhorsta5392052015-06-15 12:33:52 +02006384 }
6385
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006386 dev_priv->display.crtc_disable(crtc);
Matt Roper37d90782015-09-24 15:53:06 -07006387 intel_crtc->active = false;
6388 intel_update_watermarks(crtc);
Maarten Lankhorst1f7457b2015-07-13 11:55:05 +02006389 intel_disable_shared_dpll(intel_crtc);
Daniel Vetter0e572fe2014-04-24 23:55:42 +02006390
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006391 domains = intel_crtc->enabled_power_domains;
6392 for_each_power_domain(domain, domains)
6393 intel_display_power_put(dev_priv, domain);
6394 intel_crtc->enabled_power_domains = 0;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01006395
6396 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6397 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +02006398}
6399
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006400/*
6401 * turn all crtc's off, but do not adjust state
6402 * This has to be paired with a call to intel_modeset_setup_hw_state.
6403 */
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006404int intel_display_suspend(struct drm_device *dev)
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006405{
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006406 struct drm_mode_config *config = &dev->mode_config;
6407 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6408 struct drm_atomic_state *state;
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006409 struct drm_crtc *crtc;
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006410 unsigned crtc_mask = 0;
6411 int ret = 0;
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006412
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006413 if (WARN_ON(!ctx))
6414 return 0;
6415
6416 lockdep_assert_held(&ctx->ww_ctx);
6417 state = drm_atomic_state_alloc(dev);
6418 if (WARN_ON(!state))
6419 return -ENOMEM;
6420
6421 state->acquire_ctx = ctx;
6422 state->allow_modeset = true;
6423
6424 for_each_crtc(dev, crtc) {
6425 struct drm_crtc_state *crtc_state =
6426 drm_atomic_get_crtc_state(state, crtc);
6427
6428 ret = PTR_ERR_OR_ZERO(crtc_state);
6429 if (ret)
6430 goto free;
6431
6432 if (!crtc_state->active)
6433 continue;
6434
6435 crtc_state->active = false;
6436 crtc_mask |= 1 << drm_crtc_index(crtc);
6437 }
6438
6439 if (crtc_mask) {
Maarten Lankhorst74c090b2015-07-13 16:30:30 +02006440 ret = drm_atomic_commit(state);
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02006441
6442 if (!ret) {
6443 for_each_crtc(dev, crtc)
6444 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6445 crtc->state->active = true;
6446
6447 return ret;
6448 }
6449 }
6450
6451free:
6452 if (ret)
6453 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6454 drm_atomic_state_free(state);
6455 return ret;
Maarten Lankhorst6b72d482015-06-01 12:49:47 +02006456}
6457
Chris Wilsonea5b2132010-08-04 13:50:23 +01006458void intel_encoder_destroy(struct drm_encoder *encoder)
6459{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006460 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01006461
Chris Wilsonea5b2132010-08-04 13:50:23 +01006462 drm_encoder_cleanup(encoder);
6463 kfree(intel_encoder);
6464}
6465
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006466/* Cross check the actual hw state with our own modeset state tracking (and it's
6467 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02006468static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006469{
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006470 struct drm_crtc *crtc = connector->base.state->crtc;
6471
6472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6473 connector->base.base.id,
6474 connector->base.name);
6475
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006476 if (connector->get_hw_state(connector)) {
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006477 struct intel_encoder *encoder = connector->encoder;
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006478 struct drm_connector_state *conn_state = connector->base.state;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006479
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006480 I915_STATE_WARN(!crtc,
6481 "connector enabled without attached crtc\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006482
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006483 if (!crtc)
6484 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006485
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006486 I915_STATE_WARN(!crtc->state->active,
6487 "connector is active, but attached crtc isn't\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006488
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006489 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006490 return;
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006491
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006492 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006493 "atomic encoder doesn't match attached encoder\n");
Dave Airlie36cd7442014-05-02 13:44:18 +10006494
Maarten Lankhorste85376c2015-08-27 13:13:31 +02006495 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006496 "attached encoder crtc differs from connector crtc\n");
6497 } else {
Maarten Lankhorst4d688a22015-08-05 12:37:06 +02006498 I915_STATE_WARN(crtc && crtc->state->active,
6499 "attached crtc is active, but connector isn't\n");
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +02006500 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6501 "best encoder set without crtc!\n");
Daniel Vetter0a91ca22012-07-02 21:54:27 +02006502 }
6503}
6504
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03006505int intel_connector_init(struct intel_connector *connector)
6506{
6507 struct drm_connector_state *connector_state;
6508
6509 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6510 if (!connector_state)
6511 return -ENOMEM;
6512
6513 connector->base.state = connector_state;
6514 return 0;
6515}
6516
6517struct intel_connector *intel_connector_alloc(void)
6518{
6519 struct intel_connector *connector;
6520
6521 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6522 if (!connector)
6523 return NULL;
6524
6525 if (intel_connector_init(connector) < 0) {
6526 kfree(connector);
6527 return NULL;
6528 }
6529
6530 return connector;
6531}
6532
Daniel Vetterf0947c32012-07-02 13:10:34 +02006533/* Simple connector->get_hw_state implementation for encoders that support only
6534 * one connector and no cloning and hence the encoder state determines the state
6535 * of the connector. */
6536bool intel_connector_get_hw_state(struct intel_connector *connector)
6537{
Daniel Vetter24929352012-07-02 20:28:59 +02006538 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02006539 struct intel_encoder *encoder = connector->encoder;
6540
6541 return encoder->get_hw_state(encoder, &pipe);
6542}
6543
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006544static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02006545{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006546 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6547 return crtc_state->fdi_lanes;
Ville Syrjäläd272ddf2015-03-11 18:52:31 +02006548
6549 return 0;
6550}
6551
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006552static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006553 struct intel_crtc_state *pipe_config)
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006554{
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006555 struct drm_atomic_state *state = pipe_config->base.state;
6556 struct intel_crtc *other_crtc;
6557 struct intel_crtc_state *other_crtc_state;
6558
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006559 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6560 pipe_name(pipe), pipe_config->fdi_lanes);
6561 if (pipe_config->fdi_lanes > 4) {
6562 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6563 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006564 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006565 }
6566
Paulo Zanonibafb6552013-11-02 21:07:44 -07006567 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006568 if (pipe_config->fdi_lanes > 2) {
6569 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6570 pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006571 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006572 } else {
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006573 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006574 }
6575 }
6576
6577 if (INTEL_INFO(dev)->num_pipes == 2)
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006578 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006579
6580 /* Ivybridge 3 pipe is really complicated */
6581 switch (pipe) {
6582 case PIPE_A:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006583 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006584 case PIPE_B:
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006585 if (pipe_config->fdi_lanes <= 2)
6586 return 0;
6587
6588 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6589 other_crtc_state =
6590 intel_atomic_get_crtc_state(state, other_crtc);
6591 if (IS_ERR(other_crtc_state))
6592 return PTR_ERR(other_crtc_state);
6593
6594 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006595 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6596 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006597 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006598 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006599 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006600 case PIPE_C:
Ville Syrjälä251cc672015-03-11 18:52:30 +02006601 if (pipe_config->fdi_lanes > 2) {
6602 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6603 pipe_name(pipe), pipe_config->fdi_lanes);
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006604 return -EINVAL;
Ville Syrjälä251cc672015-03-11 18:52:30 +02006605 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006606
6607 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6608 other_crtc_state =
6609 intel_atomic_get_crtc_state(state, other_crtc);
6610 if (IS_ERR(other_crtc_state))
6611 return PTR_ERR(other_crtc_state);
6612
6613 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006614 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006615 return -EINVAL;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006616 }
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006617 return 0;
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006618 default:
6619 BUG();
6620 }
6621}
6622
Daniel Vettere29c22c2013-02-21 00:00:16 +01006623#define RETRY 1
6624static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006625 struct intel_crtc_state *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02006626{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006627 struct drm_device *dev = intel_crtc->base.dev;
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03006628 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006629 int lane, link_bw, fdi_dotclock, ret;
6630 bool needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006631
Daniel Vettere29c22c2013-02-21 00:00:16 +01006632retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02006633 /* FDI is a binary signal running at ~2.7GHz, encoding
6634 * each output octet as 10 bits. The actual frequency
6635 * is stored as a divider into a 100MHz clock, and the
6636 * mode pixel clock is stored in units of 1KHz.
6637 * Hence the bw of each lane in terms of the mode signal
6638 * is:
6639 */
6640 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6641
Damien Lespiau241bfc32013-09-25 16:45:37 +01006642 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006643
Daniel Vetter2bd89a02013-06-01 17:16:19 +02006644 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02006645 pipe_config->pipe_bpp);
6646
6647 pipe_config->fdi_lanes = lane;
6648
Daniel Vetter2bd89a02013-06-01 17:16:19 +02006649 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02006650 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006651
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006652 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6653 intel_crtc->pipe, pipe_config);
6654 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
Daniel Vettere29c22c2013-02-21 00:00:16 +01006655 pipe_config->pipe_bpp -= 2*3;
6656 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6657 pipe_config->pipe_bpp);
6658 needs_recompute = true;
6659 pipe_config->bw_constrained = true;
6660
6661 goto retry;
6662 }
6663
6664 if (needs_recompute)
6665 return RETRY;
6666
Ander Conselvan de Oliveira6d293982015-03-30 08:33:12 +03006667 return ret;
Daniel Vetter877d48d2013-04-19 11:24:43 +02006668}
6669
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03006670static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6671 struct intel_crtc_state *pipe_config)
6672{
6673 if (pipe_config->pipe_bpp > 24)
6674 return false;
6675
6676 /* HSW can handle pixel rate up to cdclk? */
6677 if (IS_HASWELL(dev_priv->dev))
6678 return true;
6679
6680 /*
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03006681 * We compare against max which means we must take
6682 * the increased cdclk requirement into account when
6683 * calculating the new cdclk.
6684 *
6685 * Should measure whether using a lower cdclk w/o IPS
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03006686 */
6687 return ilk_pipe_pixel_rate(pipe_config) <=
6688 dev_priv->max_cdclk_freq * 95 / 100;
6689}
6690
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006691static void hsw_compute_ips_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006692 struct intel_crtc_state *pipe_config)
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006693{
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03006694 struct drm_device *dev = crtc->base.dev;
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696
Jani Nikulad330a952014-01-21 11:24:25 +02006697 pipe_config->ips_enabled = i915.enable_ips &&
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03006698 hsw_crtc_supports_ips(crtc) &&
6699 pipe_config_supports_ips(dev_priv, pipe_config);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03006700}
6701
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006702static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6703{
6704 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6705
6706 /* GDG double wide on either pipe, otherwise pipe A only */
6707 return INTEL_INFO(dev_priv)->gen < 4 &&
6708 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6709}
6710
Daniel Vettera43f6e02013-06-07 23:10:32 +02006711static int intel_crtc_compute_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02006712 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08006713{
Daniel Vettera43f6e02013-06-07 23:10:32 +02006714 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira8bd31e62014-10-29 11:32:33 +02006715 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03006716 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01006717
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006718 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006719 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006720 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006721
6722 /*
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006723 * Enable double wide mode when the dot clock
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006724 * is > 90% of the (display) core speed.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006725 */
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006726 if (intel_crtc_supports_double_wide(crtc) &&
6727 adjusted_mode->crtc_clock > clock_limit) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006728 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03006729 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03006730 }
6731
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006732 if (adjusted_mode->crtc_clock > clock_limit) {
6733 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6734 adjusted_mode->crtc_clock, clock_limit,
6735 yesno(pipe_config->double_wide));
Daniel Vettere29c22c2013-02-21 00:00:16 +01006736 return -EINVAL;
Ville Syrjälä39acb4a2015-10-30 23:39:38 +02006737 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08006738 }
Chris Wilson89749352010-09-12 18:25:19 +01006739
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03006740 /*
6741 * Pipe horizontal size must be even in:
6742 * - DVO ganged mode
6743 * - LVDS dual channel mode
6744 * - Double wide pipe
6745 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02006746 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03006747 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6748 pipe_config->pipe_src_w &= ~1;
6749
Damien Lespiau8693a822013-05-03 18:48:11 +01006750 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6751 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03006752 */
6753 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
Ville Syrjäläaad941d2015-09-25 16:38:56 +03006754 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01006755 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03006756
Damien Lespiauf5adf942013-06-24 18:29:34 +01006757 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02006758 hsw_compute_ips_config(crtc, pipe_config);
6759
Daniel Vetter877d48d2013-04-19 11:24:43 +02006760 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02006761 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02006762
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +02006763 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006764}
6765
Ville Syrjälä1652d192015-03-31 14:12:01 +03006766static int skylake_get_display_clock_speed(struct drm_device *dev)
6767{
6768 struct drm_i915_private *dev_priv = to_i915(dev);
6769 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6770 uint32_t cdctl = I915_READ(CDCLK_CTL);
6771 uint32_t linkrate;
6772
Damien Lespiau414355a2015-06-04 18:21:31 +01006773 if (!(lcpll1 & LCPLL_PLL_ENABLE))
Ville Syrjälä1652d192015-03-31 14:12:01 +03006774 return 24000; /* 24MHz is the cd freq with NSSC ref */
Ville Syrjälä1652d192015-03-31 14:12:01 +03006775
6776 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6777 return 540000;
6778
6779 linkrate = (I915_READ(DPLL_CTRL1) &
Damien Lespiau71cd8422015-04-30 16:39:17 +01006780 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
Ville Syrjälä1652d192015-03-31 14:12:01 +03006781
Damien Lespiau71cd8422015-04-30 16:39:17 +01006782 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6783 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
Ville Syrjälä1652d192015-03-31 14:12:01 +03006784 /* vco 8640 */
6785 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6786 case CDCLK_FREQ_450_432:
6787 return 432000;
6788 case CDCLK_FREQ_337_308:
6789 return 308570;
6790 case CDCLK_FREQ_675_617:
6791 return 617140;
6792 default:
6793 WARN(1, "Unknown cd freq selection\n");
6794 }
6795 } else {
6796 /* vco 8100 */
6797 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6798 case CDCLK_FREQ_450_432:
6799 return 450000;
6800 case CDCLK_FREQ_337_308:
6801 return 337500;
6802 case CDCLK_FREQ_675_617:
6803 return 675000;
6804 default:
6805 WARN(1, "Unknown cd freq selection\n");
6806 }
6807 }
6808
6809 /* error case, do as if DPLL0 isn't enabled */
6810 return 24000;
6811}
6812
Bob Paauweacd3f3d2015-06-23 14:14:26 -07006813static int broxton_get_display_clock_speed(struct drm_device *dev)
6814{
6815 struct drm_i915_private *dev_priv = to_i915(dev);
6816 uint32_t cdctl = I915_READ(CDCLK_CTL);
6817 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6818 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6819 int cdclk;
6820
6821 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6822 return 19200;
6823
6824 cdclk = 19200 * pll_ratio / 2;
6825
6826 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6827 case BXT_CDCLK_CD2X_DIV_SEL_1:
6828 return cdclk; /* 576MHz or 624MHz */
6829 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6830 return cdclk * 2 / 3; /* 384MHz */
6831 case BXT_CDCLK_CD2X_DIV_SEL_2:
6832 return cdclk / 2; /* 288MHz */
6833 case BXT_CDCLK_CD2X_DIV_SEL_4:
6834 return cdclk / 4; /* 144MHz */
6835 }
6836
6837 /* error case, do as if DE PLL isn't enabled */
6838 return 19200;
6839}
6840
Ville Syrjälä1652d192015-03-31 14:12:01 +03006841static int broadwell_get_display_clock_speed(struct drm_device *dev)
6842{
6843 struct drm_i915_private *dev_priv = dev->dev_private;
6844 uint32_t lcpll = I915_READ(LCPLL_CTL);
6845 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6846
6847 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6848 return 800000;
6849 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6850 return 450000;
6851 else if (freq == LCPLL_CLK_FREQ_450)
6852 return 450000;
6853 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6854 return 540000;
6855 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6856 return 337500;
6857 else
6858 return 675000;
6859}
6860
6861static int haswell_get_display_clock_speed(struct drm_device *dev)
6862{
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864 uint32_t lcpll = I915_READ(LCPLL_CTL);
6865 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6866
6867 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6868 return 800000;
6869 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6870 return 450000;
6871 else if (freq == LCPLL_CLK_FREQ_450)
6872 return 450000;
6873 else if (IS_HSW_ULT(dev))
6874 return 337500;
6875 else
6876 return 540000;
Jesse Barnes79e53942008-11-07 14:24:08 -08006877}
6878
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07006879static int valleyview_get_display_clock_speed(struct drm_device *dev)
6880{
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03006881 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6882 CCK_DISPLAY_CLOCK_CONTROL);
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07006883}
6884
Ville Syrjäläb37a6432015-03-31 14:11:54 +03006885static int ilk_get_display_clock_speed(struct drm_device *dev)
6886{
6887 return 450000;
6888}
6889
Jesse Barnese70236a2009-09-21 10:42:27 -07006890static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08006891{
Jesse Barnese70236a2009-09-21 10:42:27 -07006892 return 400000;
6893}
Jesse Barnes79e53942008-11-07 14:24:08 -08006894
Jesse Barnese70236a2009-09-21 10:42:27 -07006895static int i915_get_display_clock_speed(struct drm_device *dev)
6896{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006897 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006898}
Jesse Barnes79e53942008-11-07 14:24:08 -08006899
Jesse Barnese70236a2009-09-21 10:42:27 -07006900static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6901{
6902 return 200000;
6903}
Jesse Barnes79e53942008-11-07 14:24:08 -08006904
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006905static int pnv_get_display_clock_speed(struct drm_device *dev)
6906{
6907 u16 gcfgc = 0;
6908
6909 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6910
6911 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6912 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006913 return 266667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006914 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006915 return 333333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006916 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006917 return 444444;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006918 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6919 return 200000;
6920 default:
6921 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6922 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006923 return 133333;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006924 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006925 return 166667;
Daniel Vetter257a7ff2013-07-26 08:35:42 +02006926 }
6927}
6928
Jesse Barnese70236a2009-09-21 10:42:27 -07006929static int i915gm_get_display_clock_speed(struct drm_device *dev)
6930{
6931 u16 gcfgc = 0;
6932
6933 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6934
6935 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Ville Syrjäläe907f172015-03-31 14:09:47 +03006936 return 133333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006937 else {
6938 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6939 case GC_DISPLAY_CLOCK_333_MHZ:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006940 return 333333;
Jesse Barnese70236a2009-09-21 10:42:27 -07006941 default:
6942 case GC_DISPLAY_CLOCK_190_200_MHZ:
6943 return 190000;
6944 }
6945 }
6946}
Jesse Barnes79e53942008-11-07 14:24:08 -08006947
Jesse Barnese70236a2009-09-21 10:42:27 -07006948static int i865_get_display_clock_speed(struct drm_device *dev)
6949{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006950 return 266667;
Jesse Barnese70236a2009-09-21 10:42:27 -07006951}
6952
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03006953static int i85x_get_display_clock_speed(struct drm_device *dev)
Jesse Barnese70236a2009-09-21 10:42:27 -07006954{
6955 u16 hpllcc = 0;
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03006956
Ville Syrjälä65cd2b32015-05-22 11:22:32 +03006957 /*
6958 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6959 * encoding is different :(
6960 * FIXME is this the right way to detect 852GM/852GMV?
6961 */
6962 if (dev->pdev->revision == 0x1)
6963 return 133333;
6964
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03006965 pci_bus_read_config_word(dev->pdev->bus,
6966 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6967
Jesse Barnese70236a2009-09-21 10:42:27 -07006968 /* Assume that the hardware is in the high speed state. This
6969 * should be the default.
6970 */
6971 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6972 case GC_CLOCK_133_200:
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03006973 case GC_CLOCK_133_200_2:
Jesse Barnese70236a2009-09-21 10:42:27 -07006974 case GC_CLOCK_100_200:
6975 return 200000;
6976 case GC_CLOCK_166_250:
6977 return 250000;
6978 case GC_CLOCK_100_133:
Ville Syrjäläe907f172015-03-31 14:09:47 +03006979 return 133333;
Ville Syrjälä1b1d2712015-05-22 11:22:31 +03006980 case GC_CLOCK_133_266:
6981 case GC_CLOCK_133_266_2:
6982 case GC_CLOCK_166_266:
6983 return 266667;
Jesse Barnese70236a2009-09-21 10:42:27 -07006984 }
6985
6986 /* Shouldn't happen */
6987 return 0;
6988}
6989
6990static int i830_get_display_clock_speed(struct drm_device *dev)
6991{
Ville Syrjäläe907f172015-03-31 14:09:47 +03006992 return 133333;
Jesse Barnes79e53942008-11-07 14:24:08 -08006993}
6994
Ville Syrjälä34edce22015-05-22 11:22:33 +03006995static unsigned int intel_hpll_vco(struct drm_device *dev)
6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
6998 static const unsigned int blb_vco[8] = {
6999 [0] = 3200000,
7000 [1] = 4000000,
7001 [2] = 5333333,
7002 [3] = 4800000,
7003 [4] = 6400000,
7004 };
7005 static const unsigned int pnv_vco[8] = {
7006 [0] = 3200000,
7007 [1] = 4000000,
7008 [2] = 5333333,
7009 [3] = 4800000,
7010 [4] = 2666667,
7011 };
7012 static const unsigned int cl_vco[8] = {
7013 [0] = 3200000,
7014 [1] = 4000000,
7015 [2] = 5333333,
7016 [3] = 6400000,
7017 [4] = 3333333,
7018 [5] = 3566667,
7019 [6] = 4266667,
7020 };
7021 static const unsigned int elk_vco[8] = {
7022 [0] = 3200000,
7023 [1] = 4000000,
7024 [2] = 5333333,
7025 [3] = 4800000,
7026 };
7027 static const unsigned int ctg_vco[8] = {
7028 [0] = 3200000,
7029 [1] = 4000000,
7030 [2] = 5333333,
7031 [3] = 6400000,
7032 [4] = 2666667,
7033 [5] = 4266667,
7034 };
7035 const unsigned int *vco_table;
7036 unsigned int vco;
7037 uint8_t tmp = 0;
7038
7039 /* FIXME other chipsets? */
7040 if (IS_GM45(dev))
7041 vco_table = ctg_vco;
7042 else if (IS_G4X(dev))
7043 vco_table = elk_vco;
7044 else if (IS_CRESTLINE(dev))
7045 vco_table = cl_vco;
7046 else if (IS_PINEVIEW(dev))
7047 vco_table = pnv_vco;
7048 else if (IS_G33(dev))
7049 vco_table = blb_vco;
7050 else
7051 return 0;
7052
7053 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7054
7055 vco = vco_table[tmp & 0x7];
7056 if (vco == 0)
7057 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7058 else
7059 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7060
7061 return vco;
7062}
7063
7064static int gm45_get_display_clock_speed(struct drm_device *dev)
7065{
7066 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7067 uint16_t tmp = 0;
7068
7069 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7070
7071 cdclk_sel = (tmp >> 12) & 0x1;
7072
7073 switch (vco) {
7074 case 2666667:
7075 case 4000000:
7076 case 5333333:
7077 return cdclk_sel ? 333333 : 222222;
7078 case 3200000:
7079 return cdclk_sel ? 320000 : 228571;
7080 default:
7081 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7082 return 222222;
7083 }
7084}
7085
7086static int i965gm_get_display_clock_speed(struct drm_device *dev)
7087{
7088 static const uint8_t div_3200[] = { 16, 10, 8 };
7089 static const uint8_t div_4000[] = { 20, 12, 10 };
7090 static const uint8_t div_5333[] = { 24, 16, 14 };
7091 const uint8_t *div_table;
7092 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7093 uint16_t tmp = 0;
7094
7095 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7096
7097 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7098
7099 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7100 goto fail;
7101
7102 switch (vco) {
7103 case 3200000:
7104 div_table = div_3200;
7105 break;
7106 case 4000000:
7107 div_table = div_4000;
7108 break;
7109 case 5333333:
7110 div_table = div_5333;
7111 break;
7112 default:
7113 goto fail;
7114 }
7115
7116 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7117
Damien Lespiaucaf4e252015-06-04 16:56:18 +01007118fail:
Ville Syrjälä34edce22015-05-22 11:22:33 +03007119 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7120 return 200000;
7121}
7122
7123static int g33_get_display_clock_speed(struct drm_device *dev)
7124{
7125 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7126 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7127 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7128 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7129 const uint8_t *div_table;
7130 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7131 uint16_t tmp = 0;
7132
7133 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7134
7135 cdclk_sel = (tmp >> 4) & 0x7;
7136
7137 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7138 goto fail;
7139
7140 switch (vco) {
7141 case 3200000:
7142 div_table = div_3200;
7143 break;
7144 case 4000000:
7145 div_table = div_4000;
7146 break;
7147 case 4800000:
7148 div_table = div_4800;
7149 break;
7150 case 5333333:
7151 div_table = div_5333;
7152 break;
7153 default:
7154 goto fail;
7155 }
7156
7157 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7158
Damien Lespiaucaf4e252015-06-04 16:56:18 +01007159fail:
Ville Syrjälä34edce22015-05-22 11:22:33 +03007160 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7161 return 190476;
7162}
7163
Zhenyu Wang2c072452009-06-05 15:38:42 +08007164static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007165intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08007166{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007167 while (*num > DATA_LINK_M_N_MASK ||
7168 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08007169 *num >>= 1;
7170 *den >>= 1;
7171 }
7172}
7173
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007174static void compute_m_n(unsigned int m, unsigned int n,
7175 uint32_t *ret_m, uint32_t *ret_n)
7176{
7177 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7178 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7179 intel_reduce_m_n_ratio(ret_m, ret_n);
7180}
7181
Daniel Vettere69d0bc2012-11-29 15:59:36 +01007182void
7183intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7184 int pixel_clock, int link_clock,
7185 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08007186{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01007187 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03007188
7189 compute_m_n(bits_per_pixel * pixel_clock,
7190 link_clock * nlanes * 8,
7191 &m_n->gmch_m, &m_n->gmch_n);
7192
7193 compute_m_n(pixel_clock, link_clock,
7194 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08007195}
7196
Chris Wilsona7615032011-01-12 17:04:08 +00007197static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7198{
Jani Nikulad330a952014-01-21 11:24:25 +02007199 if (i915.panel_use_ssc >= 0)
7200 return i915.panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03007201 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07007202 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00007203}
7204
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007205static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7206 int num_connectors)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007207{
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007208 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007209 struct drm_i915_private *dev_priv = dev->dev_private;
7210 int refclk;
7211
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007212 WARN_ON(!crtc_state->base.state);
7213
Wayne Boyer666a4532015-12-09 12:29:35 -08007214 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02007215 refclk = 100000;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007216 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007217 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007218 refclk = dev_priv->vbt.lvds_ssc_freq;
7219 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007220 } else if (!IS_GEN2(dev)) {
7221 refclk = 96000;
7222 } else {
7223 refclk = 48000;
7224 }
7225
7226 return refclk;
7227}
7228
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007229static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007230{
Daniel Vetter7df00d72013-05-21 21:54:55 +02007231 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007232}
Daniel Vetterf47709a2013-03-28 10:42:02 +01007233
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007234static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7235{
7236 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08007237}
7238
Daniel Vetterf47709a2013-03-28 10:42:02 +01007239static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007240 struct intel_crtc_state *crtc_state,
Jesse Barnesa7516a02011-12-15 12:30:37 -08007241 intel_clock_t *reduced_clock)
7242{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007243 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007244 u32 fp, fp2 = 0;
7245
7246 if (IS_PINEVIEW(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007247 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007248 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007249 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007250 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007251 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007252 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02007253 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08007254 }
7255
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007256 crtc_state->dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007257
Daniel Vetterf47709a2013-03-28 10:42:02 +01007258 crtc->lowfreq_avail = false;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007259 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Rodrigo Viviab585de2015-03-24 12:40:09 -07007260 reduced_clock) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007261 crtc_state->dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007262 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007263 } else {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007264 crtc_state->dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08007265 }
7266}
7267
Chon Ming Lee5e69f972013-09-05 20:41:49 +08007268static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7269 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07007270{
7271 u32 reg_val;
7272
7273 /*
7274 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7275 * and set it to a reasonable value instead.
7276 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007277 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007278 reg_val &= 0xffffff00;
7279 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007281
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007282 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007283 reg_val &= 0x8cffffff;
7284 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007285 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007286
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007287 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007288 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007290
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007291 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007292 reg_val &= 0x00ffffff;
7293 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007294 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007295}
7296
Daniel Vetterb5518422013-05-03 11:49:48 +02007297static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7298 struct intel_link_m_n *m_n)
7299{
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 int pipe = crtc->pipe;
7303
Daniel Vettere3b95f12013-05-03 11:49:49 +02007304 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7305 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7306 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7307 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02007308}
7309
7310static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
Vandana Kannanf769cd22014-08-05 07:51:22 -07007311 struct intel_link_m_n *m_n,
7312 struct intel_link_m_n *m2_n2)
Daniel Vetterb5518422013-05-03 11:49:48 +02007313{
7314 struct drm_device *dev = crtc->base.dev;
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316 int pipe = crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007317 enum transcoder transcoder = crtc->config->cpu_transcoder;
Daniel Vetterb5518422013-05-03 11:49:48 +02007318
7319 if (INTEL_INFO(dev)->gen >= 5) {
7320 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7321 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7322 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7323 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
Vandana Kannanf769cd22014-08-05 07:51:22 -07007324 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7325 * for gen < 8) and if DRRS is supported (to make sure the
7326 * registers are not unnecessarily accessed).
7327 */
Durgadoss R44395bf2015-02-13 15:33:02 +05307328 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007329 crtc->config->has_drrs) {
Vandana Kannanf769cd22014-08-05 07:51:22 -07007330 I915_WRITE(PIPE_DATA_M2(transcoder),
7331 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7332 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7333 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7334 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7335 }
Daniel Vetterb5518422013-05-03 11:49:48 +02007336 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02007337 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7338 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7339 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7340 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02007341 }
7342}
7343
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05307344void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007345{
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05307346 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7347
7348 if (m_n == M1_N1) {
7349 dp_m_n = &crtc->config->dp_m_n;
7350 dp_m2_n2 = &crtc->config->dp_m2_n2;
7351 } else if (m_n == M2_N2) {
7352
7353 /*
7354 * M2_N2 registers are not supported. Hence m2_n2 divider value
7355 * needs to be programmed into M1_N1.
7356 */
7357 dp_m_n = &crtc->config->dp_m2_n2;
7358 } else {
7359 DRM_ERROR("Unsupported divider value\n");
7360 return;
7361 }
7362
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007363 if (crtc->config->has_pch_encoder)
7364 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007365 else
Ramalingam Cfe3cd48d2015-02-13 15:32:59 +05307366 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
Daniel Vetter03afc4a2013-04-02 23:42:31 +02007367}
7368
Daniel Vetter251ac862015-06-18 10:30:24 +02007369static void vlv_compute_dpll(struct intel_crtc *crtc,
7370 struct intel_crtc_state *pipe_config)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007371{
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007372 u32 dpll, dpll_md;
7373
7374 /*
7375 * Enable DPIO clock input. We should never disable the reference
7376 * clock for pipe B, since VGA hotplug / manual detection depends
7377 * on it.
7378 */
Ville Syrjälä60bfe442015-06-29 15:25:49 +03007379 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7380 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007381 /* We should never disable this, set it here for state tracking */
7382 if (crtc->pipe == PIPE_B)
7383 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7384 dpll |= DPLL_VCO_ENABLE;
Ville Syrjäläd288f652014-10-28 13:20:22 +02007385 pipe_config->dpll_hw_state.dpll = dpll;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007386
Ville Syrjäläd288f652014-10-28 13:20:22 +02007387 dpll_md = (pipe_config->pixel_multiplier - 1)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007388 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjäläd288f652014-10-28 13:20:22 +02007389 pipe_config->dpll_hw_state.dpll_md = dpll_md;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007390}
7391
Ville Syrjäläd288f652014-10-28 13:20:22 +02007392static void vlv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007393 const struct intel_crtc_state *pipe_config)
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007394{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007395 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007396 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01007397 int pipe = crtc->pipe;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007398 u32 mdiv;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007399 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007400 u32 coreclk, reg_val;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007401
Ville Syrjäläa5805162015-05-26 20:42:30 +03007402 mutex_lock(&dev_priv->sb_lock);
Daniel Vetter09153002012-12-12 14:06:44 +01007403
Ville Syrjäläd288f652014-10-28 13:20:22 +02007404 bestn = pipe_config->dpll.n;
7405 bestm1 = pipe_config->dpll.m1;
7406 bestm2 = pipe_config->dpll.m2;
7407 bestp1 = pipe_config->dpll.p1;
7408 bestp2 = pipe_config->dpll.p2;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007409
Jesse Barnes89b667f2013-04-18 14:51:36 -07007410 /* See eDP HDMI DPIO driver vbios notes doc */
7411
7412 /* PLL B needs special handling */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007413 if (pipe == PIPE_B)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08007414 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007415
7416 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007417 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007418
7419 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007420 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007421 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007422 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007423
7424 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007425 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007426
7427 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007428 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7429 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7430 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007431 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07007432
7433 /*
7434 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7435 * but we don't support that).
7436 * Note: don't use the DAC post divider as it seems unstable.
7437 */
7438 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007439 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007440
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007441 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007442 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007443
Jesse Barnes89b667f2013-04-18 14:51:36 -07007444 /* Set HBR and RBR LPF coefficients */
Ville Syrjäläd288f652014-10-28 13:20:22 +02007445 if (pipe_config->port_clock == 162000 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007446 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7447 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007448 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03007449 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007450 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007451 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007452 0x00d0000f);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007453
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02007454 if (pipe_config->has_dp_encoder) {
Jesse Barnes89b667f2013-04-18 14:51:36 -07007455 /* Use SSC source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007456 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007458 0x0df40000);
7459 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007460 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007461 0x0df70000);
7462 } else { /* HDMI or VGA */
7463 /* Use bend source */
Daniel Vetterbdd4b6a2014-04-24 23:55:11 +02007464 if (pipe == PIPE_A)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007465 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007466 0x0df70000);
7467 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007468 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07007469 0x0df40000);
7470 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007471
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007472 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07007473 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007474 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7475 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Jesse Barnes89b667f2013-04-18 14:51:36 -07007476 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007477 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07007478
Chon Ming Leeab3c7592013-11-07 10:43:30 +08007479 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Ville Syrjäläa5805162015-05-26 20:42:30 +03007480 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07007481}
7482
Daniel Vetter251ac862015-06-18 10:30:24 +02007483static void chv_compute_dpll(struct intel_crtc *crtc,
7484 struct intel_crtc_state *pipe_config)
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007485{
Ville Syrjälä60bfe442015-06-29 15:25:49 +03007486 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7487 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007488 DPLL_VCO_ENABLE;
7489 if (crtc->pipe != PIPE_A)
Ville Syrjäläd288f652014-10-28 13:20:22 +02007490 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007491
Ville Syrjäläd288f652014-10-28 13:20:22 +02007492 pipe_config->dpll_hw_state.dpll_md =
7493 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007494}
7495
Ville Syrjäläd288f652014-10-28 13:20:22 +02007496static void chv_prepare_pll(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007497 const struct intel_crtc_state *pipe_config)
Ville Syrjälä1ae0d132014-06-28 02:04:00 +03007498{
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007499 struct drm_device *dev = crtc->base.dev;
7500 struct drm_i915_private *dev_priv = dev->dev_private;
7501 int pipe = crtc->pipe;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02007502 i915_reg_t dpll_reg = DPLL(crtc->pipe);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007503 enum dpio_channel port = vlv_pipe_to_channel(pipe);
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307504 u32 loopfilter, tribuf_calcntr;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007505 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307506 u32 dpio_val;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307507 int vco;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007508
Ville Syrjäläd288f652014-10-28 13:20:22 +02007509 bestn = pipe_config->dpll.n;
7510 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7511 bestm1 = pipe_config->dpll.m1;
7512 bestm2 = pipe_config->dpll.m2 >> 22;
7513 bestp1 = pipe_config->dpll.p1;
7514 bestp2 = pipe_config->dpll.p2;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307515 vco = pipe_config->dpll.vco;
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307516 dpio_val = 0;
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307517 loopfilter = 0;
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007518
7519 /*
7520 * Enable Refclk and SSC
7521 */
Ville Syrjäläa11b0702014-04-09 13:28:57 +03007522 I915_WRITE(dpll_reg,
Ville Syrjäläd288f652014-10-28 13:20:22 +02007523 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
Ville Syrjäläa11b0702014-04-09 13:28:57 +03007524
Ville Syrjäläa5805162015-05-26 20:42:30 +03007525 mutex_lock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007526
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007527 /* p1 and p2 divider */
7528 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7529 5 << DPIO_CHV_S1_DIV_SHIFT |
7530 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7531 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7532 1 << DPIO_CHV_K_DIV_SHIFT);
7533
7534 /* Feedback post-divider - m2 */
7535 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7536
7537 /* Feedback refclk divider - n and m1 */
7538 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7539 DPIO_CHV_M1_DIV_BY_2 |
7540 1 << DPIO_CHV_N_DIV_SHIFT);
7541
7542 /* M2 fraction division */
Ville Syrjälä25a25df2015-07-08 23:45:47 +03007543 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007544
7545 /* M2 fraction division enable */
Vijay Purushothamana945ce7e2015-03-05 19:30:57 +05307546 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7547 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7548 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7549 if (bestm2_frac)
7550 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7551 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007552
Vijay Purushothamande3a0fd2015-03-05 19:32:06 +05307553 /* Program digital lock detect threshold */
7554 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7555 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7556 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7557 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7558 if (!bestm2_frac)
7559 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7560 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7561
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007562 /* Loop filter */
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307563 if (vco == 5400000) {
7564 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7565 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7566 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7567 tribuf_calcntr = 0x9;
7568 } else if (vco <= 6200000) {
7569 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7570 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7571 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7572 tribuf_calcntr = 0x9;
7573 } else if (vco <= 6480000) {
7574 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7575 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7576 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7577 tribuf_calcntr = 0x8;
7578 } else {
7579 /* Not supported. Apply the same limits as in the max case */
7580 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7581 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7582 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7583 tribuf_calcntr = 0;
7584 }
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007585 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7586
Ville Syrjälä968040b2015-03-11 22:52:08 +02007587 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
Vijay Purushothaman9cbe40c2015-03-05 19:33:08 +05307588 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7589 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7590 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7591
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007592 /* AFC Recal */
7593 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7594 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7595 DPIO_AFC_RECAL);
7596
Ville Syrjäläa5805162015-05-26 20:42:30 +03007597 mutex_unlock(&dev_priv->sb_lock);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03007598}
7599
Ville Syrjäläd288f652014-10-28 13:20:22 +02007600/**
7601 * vlv_force_pll_on - forcibly enable just the PLL
7602 * @dev_priv: i915 private structure
7603 * @pipe: pipe PLL to enable
7604 * @dpll: PLL configuration
7605 *
7606 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7607 * in cases where we need the PLL enabled even when @pipe is not going to
7608 * be enabled.
7609 */
7610void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7611 const struct dpll *dpll)
7612{
7613 struct intel_crtc *crtc =
7614 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007615 struct intel_crtc_state pipe_config = {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007616 .base.crtc = &crtc->base,
Ville Syrjäläd288f652014-10-28 13:20:22 +02007617 .pixel_multiplier = 1,
7618 .dpll = *dpll,
7619 };
7620
7621 if (IS_CHERRYVIEW(dev)) {
Daniel Vetter251ac862015-06-18 10:30:24 +02007622 chv_compute_dpll(crtc, &pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +02007623 chv_prepare_pll(crtc, &pipe_config);
7624 chv_enable_pll(crtc, &pipe_config);
7625 } else {
Daniel Vetter251ac862015-06-18 10:30:24 +02007626 vlv_compute_dpll(crtc, &pipe_config);
Ville Syrjäläd288f652014-10-28 13:20:22 +02007627 vlv_prepare_pll(crtc, &pipe_config);
7628 vlv_enable_pll(crtc, &pipe_config);
7629 }
7630}
7631
7632/**
7633 * vlv_force_pll_off - forcibly disable just the PLL
7634 * @dev_priv: i915 private structure
7635 * @pipe: pipe PLL to disable
7636 *
7637 * Disable the PLL for @pipe. To be used in cases where we need
7638 * the PLL enabled even when @pipe is not going to be enabled.
7639 */
7640void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7641{
7642 if (IS_CHERRYVIEW(dev))
7643 chv_disable_pll(to_i915(dev), pipe);
7644 else
7645 vlv_disable_pll(to_i915(dev), pipe);
7646}
7647
Daniel Vetter251ac862015-06-18 10:30:24 +02007648static void i9xx_compute_dpll(struct intel_crtc *crtc,
7649 struct intel_crtc_state *crtc_state,
7650 intel_clock_t *reduced_clock,
7651 int num_connectors)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007652{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007653 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007654 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007655 u32 dpll;
7656 bool is_sdvo;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007657 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007658
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007659 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05307660
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007661 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7662 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007663
7664 dpll = DPLL_VGA_MODE_DIS;
7665
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007666 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007667 dpll |= DPLLB_MODE_LVDS;
7668 else
7669 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01007670
Daniel Vetteref1b4602013-06-01 17:17:04 +02007671 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007672 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetter198a037f2013-04-19 11:14:37 +02007673 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007674 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02007675
7676 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007677 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02007678
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007679 if (crtc_state->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02007680 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007681
7682 /* compute bitmask from p1 value */
7683 if (IS_PINEVIEW(dev))
7684 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7685 else {
7686 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7687 if (IS_G4X(dev) && reduced_clock)
7688 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7689 }
7690 switch (clock->p2) {
7691 case 5:
7692 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7693 break;
7694 case 7:
7695 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7696 break;
7697 case 10:
7698 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7699 break;
7700 case 14:
7701 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7702 break;
7703 }
7704 if (INTEL_INFO(dev)->gen >= 4)
7705 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7706
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007707 if (crtc_state->sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007708 dpll |= PLL_REF_INPUT_TVCLKINBC;
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007709 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007710 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7711 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7712 else
7713 dpll |= PLL_REF_INPUT_DREFCLK;
7714
7715 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007716 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02007717
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007718 if (INTEL_INFO(dev)->gen >= 4) {
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007719 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02007720 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007721 crtc_state->dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007722 }
7723}
7724
Daniel Vetter251ac862015-06-18 10:30:24 +02007725static void i8xx_compute_dpll(struct intel_crtc *crtc,
7726 struct intel_crtc_state *crtc_state,
7727 intel_clock_t *reduced_clock,
7728 int num_connectors)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007729{
Daniel Vetterf47709a2013-03-28 10:42:02 +01007730 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007731 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007732 u32 dpll;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007733 struct dpll *clock = &crtc_state->dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007734
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007735 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05307736
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007737 dpll = DPLL_VGA_MODE_DIS;
7738
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007739 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007740 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7741 } else {
7742 if (clock->p1 == 2)
7743 dpll |= PLL_P1_DIVIDE_BY_TWO;
7744 else
7745 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7746 if (clock->p2 == 4)
7747 dpll |= PLL_P2_DIVIDE_BY_4;
7748 }
7749
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007750 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
Daniel Vetter4a33e482013-07-06 12:52:05 +02007751 dpll |= DPLL_DVO_2X_MODE;
7752
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007753 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007754 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7755 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7756 else
7757 dpll |= PLL_REF_INPUT_DREFCLK;
7758
7759 dpll |= DPLL_VCO_ENABLE;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007760 crtc_state->dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02007761}
7762
Daniel Vetter8a654f32013-06-01 17:16:22 +02007763static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007764{
7765 struct drm_device *dev = intel_crtc->base.dev;
7766 struct drm_i915_private *dev_priv = dev->dev_private;
7767 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007768 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +03007769 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02007770 uint32_t crtc_vtotal, crtc_vblank_end;
7771 int vsyncshift = 0;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007772
7773 /* We need to be careful not to changed the adjusted mode, for otherwise
7774 * the hw state checker will get angry at the mismatch. */
7775 crtc_vtotal = adjusted_mode->crtc_vtotal;
7776 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007777
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007778 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007779 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007780 crtc_vtotal -= 1;
7781 crtc_vblank_end -= 1;
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007782
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007783 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjälä609aeac2014-03-28 23:29:30 +02007784 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7785 else
7786 vsyncshift = adjusted_mode->crtc_hsync_start -
7787 adjusted_mode->crtc_htotal / 2;
Ville Syrjälä1caea6e2014-03-28 23:29:32 +02007788 if (vsyncshift < 0)
7789 vsyncshift += adjusted_mode->crtc_htotal;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007790 }
7791
7792 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007793 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007794
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007795 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007796 (adjusted_mode->crtc_hdisplay - 1) |
7797 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007798 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007799 (adjusted_mode->crtc_hblank_start - 1) |
7800 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007801 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007802 (adjusted_mode->crtc_hsync_start - 1) |
7803 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7804
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007805 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007806 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007807 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007808 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007809 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02007810 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007811 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007812 (adjusted_mode->crtc_vsync_start - 1) |
7813 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7814
Paulo Zanonib5e508d2012-10-24 11:34:43 -02007815 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7816 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7817 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7818 * bits. */
7819 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7820 (pipe == PIPE_B || pipe == PIPE_C))
7821 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7822
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007823 /* pipesrc controls the size that is scaled from, which should
7824 * always be the user's requested size.
7825 */
7826 I915_WRITE(PIPESRC(pipe),
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007827 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7828 (intel_crtc->config->pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03007829}
7830
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007831static void intel_get_pipe_timings(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007832 struct intel_crtc_state *pipe_config)
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007833{
7834 struct drm_device *dev = crtc->base.dev;
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7837 uint32_t tmp;
7838
7839 tmp = I915_READ(HTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007840 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7841 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007842 tmp = I915_READ(HBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007843 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7844 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007845 tmp = I915_READ(HSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007846 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7847 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007848
7849 tmp = I915_READ(VTOTAL(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007850 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7851 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007852 tmp = I915_READ(VBLANK(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007853 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7854 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007855 tmp = I915_READ(VSYNC(cpu_transcoder));
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007856 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7857 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007858
7859 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007860 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7861 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7862 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007863 }
7864
7865 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03007866 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7867 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7868
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007869 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7870 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02007871}
7872
Daniel Vetterf6a83282014-02-11 15:28:57 -08007873void intel_mode_from_pipe_config(struct drm_display_mode *mode,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02007874 struct intel_crtc_state *pipe_config)
Jesse Barnesbabea612013-06-26 18:57:38 +03007875{
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007876 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7877 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7878 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7879 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03007880
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007881 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7882 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7883 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7884 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
Jesse Barnesbabea612013-06-26 18:57:38 +03007885
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007886 mode->flags = pipe_config->base.adjusted_mode.flags;
Maarten Lankhorstcd13f5a2015-07-14 14:12:02 +02007887 mode->type = DRM_MODE_TYPE_DRIVER;
Jesse Barnesbabea612013-06-26 18:57:38 +03007888
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +02007889 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7890 mode->flags |= pipe_config->base.adjusted_mode.flags;
Maarten Lankhorstcd13f5a2015-07-14 14:12:02 +02007891
7892 mode->hsync = drm_mode_hsync(mode);
7893 mode->vrefresh = drm_mode_vrefresh(mode);
7894 drm_mode_set_name(mode);
Jesse Barnesbabea612013-06-26 18:57:38 +03007895}
7896
Daniel Vetter84b046f2013-02-19 18:48:54 +01007897static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7898{
7899 struct drm_device *dev = intel_crtc->base.dev;
7900 struct drm_i915_private *dev_priv = dev->dev_private;
7901 uint32_t pipeconf;
7902
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02007903 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01007904
Ville Syrjäläb6b5d042014-08-15 01:22:07 +03007905 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7906 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7907 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
Daniel Vetter67c72a12013-09-24 11:46:14 +02007908
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007909 if (intel_crtc->config->double_wide)
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03007910 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01007911
Daniel Vetterff9ce462013-04-24 14:57:17 +02007912 /* only g4x and later have fancy bpc/dither controls */
Wayne Boyer666a4532015-12-09 12:29:35 -08007913 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02007914 /* Bspec claims that we can't use dithering for 30bpp pipes. */
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007915 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
Daniel Vetterff9ce462013-04-24 14:57:17 +02007916 pipeconf |= PIPECONF_DITHER_EN |
7917 PIPECONF_DITHER_TYPE_SP;
7918
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007919 switch (intel_crtc->config->pipe_bpp) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02007920 case 18:
7921 pipeconf |= PIPECONF_6BPC;
7922 break;
7923 case 24:
7924 pipeconf |= PIPECONF_8BPC;
7925 break;
7926 case 30:
7927 pipeconf |= PIPECONF_10BPC;
7928 break;
7929 default:
7930 /* Case prevented by intel_choose_pipe_bpp_dither. */
7931 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01007932 }
7933 }
7934
7935 if (HAS_PIPE_CXSR(dev)) {
7936 if (intel_crtc->lowfreq_avail) {
7937 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7938 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7939 } else {
7940 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01007941 }
7942 }
7943
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02007944 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02007945 if (INTEL_INFO(dev)->gen < 4 ||
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +03007946 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
Ville Syrjäläefc2cff2014-03-28 23:29:31 +02007947 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7948 else
7949 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7950 } else
Daniel Vetter84b046f2013-02-19 18:48:54 +01007951 pipeconf |= PIPECONF_PROGRESSIVE;
7952
Wayne Boyer666a4532015-12-09 12:29:35 -08007953 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7954 intel_crtc->config->limited_color_range)
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02007955 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03007956
Daniel Vetter84b046f2013-02-19 18:48:54 +01007957 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7958 POSTING_READ(PIPECONF(intel_crtc->pipe));
7959}
7960
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007961static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7962 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08007963{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03007964 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007965 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtc751ce42010-03-25 11:48:48 -07007966 int refclk, num_connectors = 0;
Daniel Vetterc329a4e2015-06-18 10:30:23 +02007967 intel_clock_t clock;
7968 bool ok;
Ma Lingd4906092009-03-18 20:13:27 +08007969 const intel_limit_t *limit;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02007970 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03007971 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02007972 struct drm_connector_state *connector_state;
7973 int i;
Jesse Barnes79e53942008-11-07 14:24:08 -08007974
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03007975 memset(&crtc_state->dpll_hw_state, 0,
7976 sizeof(crtc_state->dpll_hw_state));
7977
Jani Nikulaa65347b2015-11-27 12:21:46 +02007978 if (crtc_state->has_dsi_encoder)
Daniel Vetter5b18e572014-04-24 23:55:06 +02007979 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007980
Jani Nikulaa65347b2015-11-27 12:21:46 +02007981 for_each_connector_in_state(state, connector, connector_state, i) {
7982 if (connector_state->crtc == &crtc->base)
7983 num_connectors++;
7984 }
7985
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007986 if (!crtc_state->clock_set) {
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007987 refclk = i9xx_get_refclk(crtc_state, num_connectors);
Jani Nikulaf2335332013-09-13 11:03:09 +03007988
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007989 /*
7990 * Returns a set of divisors for the desired target clock with
7991 * the given refclk, or FALSE. The returned values represent
7992 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7993 * 2) / p1 / p2.
7994 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02007995 limit = intel_limit(crtc_state, refclk);
7996 ok = dev_priv->display.find_dpll(limit, crtc_state,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02007997 crtc_state->port_clock,
Jani Nikulae9fd1c02013-08-27 15:12:23 +03007998 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03007999 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008000 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8001 return -EINVAL;
8002 }
Eric Anholtf564048e2011-03-30 13:01:02 -07008003
Jani Nikulaf2335332013-09-13 11:03:09 +03008004 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008005 crtc_state->dpll.n = clock.n;
8006 crtc_state->dpll.m1 = clock.m1;
8007 crtc_state->dpll.m2 = clock.m2;
8008 crtc_state->dpll.p1 = clock.p1;
8009 crtc_state->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01008010 }
Eric Anholtf564048e2011-03-30 13:01:02 -07008011
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008012 if (IS_GEN2(dev)) {
Daniel Vetterc329a4e2015-06-18 10:30:23 +02008013 i8xx_compute_dpll(crtc, crtc_state, NULL,
Daniel Vetter251ac862015-06-18 10:30:24 +02008014 num_connectors);
Chon Ming Lee9d556c92014-05-02 14:27:47 +03008015 } else if (IS_CHERRYVIEW(dev)) {
Daniel Vetter251ac862015-06-18 10:30:24 +02008016 chv_compute_dpll(crtc, crtc_state);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008017 } else if (IS_VALLEYVIEW(dev)) {
Daniel Vetter251ac862015-06-18 10:30:24 +02008018 vlv_compute_dpll(crtc, crtc_state);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008019 } else {
Daniel Vetterc329a4e2015-06-18 10:30:23 +02008020 i9xx_compute_dpll(crtc, crtc_state, NULL,
Daniel Vetter251ac862015-06-18 10:30:24 +02008021 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03008022 }
Eric Anholtf564048e2011-03-30 13:01:02 -07008023
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02008024 return 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07008025}
8026
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008027static void i9xx_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008028 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008029{
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 uint32_t tmp;
8033
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02008034 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8035 return;
8036
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008037 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02008038 if (!(tmp & PFIT_ENABLE))
8039 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008040
Daniel Vetter06922822013-07-11 13:35:40 +02008041 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008042 if (INTEL_INFO(dev)->gen < 4) {
8043 if (crtc->pipe != PIPE_B)
8044 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008045 } else {
8046 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8047 return;
8048 }
8049
Daniel Vetter06922822013-07-11 13:35:40 +02008050 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008051 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8052 if (INTEL_INFO(dev)->gen < 5)
8053 pipe_config->gmch_pfit.lvds_border_bits =
8054 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8055}
8056
Jesse Barnesacbec812013-09-20 11:29:32 -07008057static void vlv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008058 struct intel_crtc_state *pipe_config)
Jesse Barnesacbec812013-09-20 11:29:32 -07008059{
8060 struct drm_device *dev = crtc->base.dev;
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062 int pipe = pipe_config->cpu_transcoder;
8063 intel_clock_t clock;
8064 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07008065 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07008066
Shobhit Kumarf573de52014-07-30 20:32:37 +05308067 /* In case of MIPI DPLL will not even be used */
8068 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8069 return;
8070
Ville Syrjäläa5805162015-05-26 20:42:30 +03008071 mutex_lock(&dev_priv->sb_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08008072 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Ville Syrjäläa5805162015-05-26 20:42:30 +03008073 mutex_unlock(&dev_priv->sb_lock);
Jesse Barnesacbec812013-09-20 11:29:32 -07008074
8075 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8076 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8077 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8078 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8079 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8080
Imre Deakdccbea32015-06-22 23:35:51 +03008081 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07008082}
8083
Damien Lespiau5724dbd2015-01-20 12:51:52 +00008084static void
8085i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8086 struct intel_initial_plane_config *plane_config)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008087{
8088 struct drm_device *dev = crtc->base.dev;
8089 struct drm_i915_private *dev_priv = dev->dev_private;
8090 u32 val, base, offset;
8091 int pipe = crtc->pipe, plane = crtc->plane;
8092 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00008093 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008094 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00008095 struct intel_framebuffer *intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008096
Damien Lespiau42a7b082015-02-05 19:35:13 +00008097 val = I915_READ(DSPCNTR(plane));
8098 if (!(val & DISPLAY_PLANE_ENABLE))
8099 return;
8100
Damien Lespiaud9806c92015-01-21 14:07:19 +00008101 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00008102 if (!intel_fb) {
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008103 DRM_DEBUG_KMS("failed to alloc fb\n");
8104 return;
8105 }
8106
Damien Lespiau1b842c82015-01-21 13:50:54 +00008107 fb = &intel_fb->base;
8108
Daniel Vetter18c52472015-02-10 17:16:09 +00008109 if (INTEL_INFO(dev)->gen >= 4) {
8110 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00008111 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00008112 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8113 }
8114 }
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008115
8116 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00008117 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008118 fb->pixel_format = fourcc;
8119 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008120
8121 if (INTEL_INFO(dev)->gen >= 4) {
Damien Lespiau49af4492015-01-20 12:51:44 +00008122 if (plane_config->tiling)
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008123 offset = I915_READ(DSPTILEOFF(plane));
8124 else
8125 offset = I915_READ(DSPLINOFF(plane));
8126 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8127 } else {
8128 base = I915_READ(DSPADDR(plane));
8129 }
8130 plane_config->base = base;
8131
8132 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008133 fb->width = ((val >> 16) & 0xfff) + 1;
8134 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008135
8136 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008137 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008138
Damien Lespiaub113d5e2015-01-20 12:51:46 +00008139 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00008140 fb->pixel_format,
8141 fb->modifier[0]);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008142
Daniel Vetterf37b5c22015-02-10 23:12:27 +01008143 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008144
Damien Lespiau2844a922015-01-20 12:51:48 +00008145 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8146 pipe_name(pipe), plane, fb->width, fb->height,
8147 fb->bits_per_pixel, base, fb->pitches[0],
8148 plane_config->size);
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008149
Damien Lespiau2d140302015-02-05 17:22:18 +00008150 plane_config->fb = intel_fb;
Jesse Barnes1ad292b2014-03-07 08:57:49 -08008151}
8152
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008153static void chv_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008154 struct intel_crtc_state *pipe_config)
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008155{
8156 struct drm_device *dev = crtc->base.dev;
8157 struct drm_i915_private *dev_priv = dev->dev_private;
8158 int pipe = pipe_config->cpu_transcoder;
8159 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8160 intel_clock_t clock;
Imre Deak0d7b6b12015-07-02 14:29:58 +03008161 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008162 int refclk = 100000;
8163
Ville Syrjäläa5805162015-05-26 20:42:30 +03008164 mutex_lock(&dev_priv->sb_lock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008165 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8166 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8167 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8168 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
Imre Deak0d7b6b12015-07-02 14:29:58 +03008169 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
Ville Syrjäläa5805162015-05-26 20:42:30 +03008170 mutex_unlock(&dev_priv->sb_lock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008171
8172 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
Imre Deak0d7b6b12015-07-02 14:29:58 +03008173 clock.m2 = (pll_dw0 & 0xff) << 22;
8174 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8175 clock.m2 |= pll_dw2 & 0x3fffff;
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008176 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8177 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8178 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8179
Imre Deakdccbea32015-06-22 23:35:51 +03008180 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008181}
8182
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008183static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02008184 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008185{
8186 struct drm_device *dev = crtc->base.dev;
8187 struct drm_i915_private *dev_priv = dev->dev_private;
8188 uint32_t tmp;
8189
Daniel Vetterf458ebb2014-09-30 10:56:39 +02008190 if (!intel_display_power_is_enabled(dev_priv,
8191 POWER_DOMAIN_PIPE(crtc->pipe)))
Imre Deakb5482bd2014-03-05 16:20:55 +02008192 return false;
8193
Daniel Vettere143a212013-07-04 12:01:15 +02008194 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008195 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02008196
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008197 tmp = I915_READ(PIPECONF(crtc->pipe));
8198 if (!(tmp & PIPECONF_ENABLE))
8199 return false;
8200
Wayne Boyer666a4532015-12-09 12:29:35 -08008201 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjälä42571ae2013-09-06 23:29:00 +03008202 switch (tmp & PIPECONF_BPC_MASK) {
8203 case PIPECONF_6BPC:
8204 pipe_config->pipe_bpp = 18;
8205 break;
8206 case PIPECONF_8BPC:
8207 pipe_config->pipe_bpp = 24;
8208 break;
8209 case PIPECONF_10BPC:
8210 pipe_config->pipe_bpp = 30;
8211 break;
8212 default:
8213 break;
8214 }
8215 }
8216
Wayne Boyer666a4532015-12-09 12:29:35 -08008217 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8218 (tmp & PIPECONF_COLOR_RANGE_SELECT))
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02008219 pipe_config->limited_color_range = true;
8220
Ville Syrjälä282740f2013-09-04 18:30:03 +03008221 if (INTEL_INFO(dev)->gen < 4)
8222 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8223
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02008224 intel_get_pipe_timings(crtc, pipe_config);
8225
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02008226 i9xx_get_pfit_config(crtc, pipe_config);
8227
Daniel Vetter6c49f242013-06-06 12:45:25 +02008228 if (INTEL_INFO(dev)->gen >= 4) {
8229 tmp = I915_READ(DPLL_MD(crtc->pipe));
8230 pipe_config->pixel_multiplier =
8231 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8232 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008233 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02008234 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8235 tmp = I915_READ(DPLL(crtc->pipe));
8236 pipe_config->pixel_multiplier =
8237 ((tmp & SDVO_MULTIPLIER_MASK)
8238 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8239 } else {
8240 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8241 * port and will be fixed up in the encoder->get_config
8242 * function. */
8243 pipe_config->pixel_multiplier = 1;
8244 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008245 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
Wayne Boyer666a4532015-12-09 12:29:35 -08008246 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Ville Syrjälä1c4e0272014-09-05 21:52:42 +03008247 /*
8248 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8249 * on 830. Filter it out here so that we don't
8250 * report errors due to that.
8251 */
8252 if (IS_I830(dev))
8253 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8254
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008255 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8256 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03008257 } else {
8258 /* Mask out read-only status bits. */
8259 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8260 DPLL_PORTC_READY_MASK |
8261 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02008262 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02008263
Ville Syrjälä70b23a92014-04-09 13:28:22 +03008264 if (IS_CHERRYVIEW(dev))
8265 chv_crtc_clock_get(crtc, pipe_config);
8266 else if (IS_VALLEYVIEW(dev))
Jesse Barnesacbec812013-09-20 11:29:32 -07008267 vlv_crtc_clock_get(crtc, pipe_config);
8268 else
8269 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03008270
Ville Syrjälä0f646142015-08-26 19:39:18 +03008271 /*
8272 * Normally the dotclock is filled in by the encoder .get_config()
8273 * but in case the pipe is enabled w/o any ports we need a sane
8274 * default.
8275 */
8276 pipe_config->base.adjusted_mode.crtc_clock =
8277 pipe_config->port_clock / pipe_config->pixel_multiplier;
8278
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01008279 return true;
8280}
8281
Paulo Zanonidde86e22012-12-01 12:04:25 -02008282static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07008283{
8284 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008285 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008286 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008287 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07008288 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07008289 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07008290 bool has_ck505 = false;
8291 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008292
8293 /* We need to take the global config into account */
Damien Lespiaub2784e12014-08-05 11:29:37 +01008294 for_each_intel_encoder(dev, encoder) {
Keith Packard199e5d72011-09-22 12:01:57 -07008295 switch (encoder->type) {
8296 case INTEL_OUTPUT_LVDS:
8297 has_panel = true;
8298 has_lvds = true;
8299 break;
8300 case INTEL_OUTPUT_EDP:
8301 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03008302 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07008303 has_cpu_edp = true;
8304 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008305 default:
8306 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008307 }
8308 }
8309
Keith Packard99eb6a02011-09-26 14:29:12 -07008310 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03008311 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07008312 can_ssc = has_ck505;
8313 } else {
8314 has_ck505 = false;
8315 can_ssc = true;
8316 }
8317
Imre Deak2de69052013-05-08 13:14:04 +03008318 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8319 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008320
8321 /* Ironlake: try to setup display ref clock before DPLL
8322 * enabling. This is only under driver's control after
8323 * PCH B stepping, previous chipset stepping should be
8324 * ignoring this setting.
8325 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008326 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008327
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008328 /* As we must carefully and slowly disable/enable each source in turn,
8329 * compute the final state we want first and check if we need to
8330 * make any changes at all.
8331 */
8332 final = val;
8333 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07008334 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008335 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07008336 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008337 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8338
8339 final &= ~DREF_SSC_SOURCE_MASK;
8340 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8341 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008342
Keith Packard199e5d72011-09-22 12:01:57 -07008343 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008344 final |= DREF_SSC_SOURCE_ENABLE;
8345
8346 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8347 final |= DREF_SSC1_ENABLE;
8348
8349 if (has_cpu_edp) {
8350 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8351 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8352 else
8353 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8354 } else
8355 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8356 } else {
8357 final |= DREF_SSC_SOURCE_DISABLE;
8358 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8359 }
8360
8361 if (final == val)
8362 return;
8363
8364 /* Always enable nonspread source */
8365 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8366
8367 if (has_ck505)
8368 val |= DREF_NONSPREAD_CK505_ENABLE;
8369 else
8370 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8371
8372 if (has_panel) {
8373 val &= ~DREF_SSC_SOURCE_MASK;
8374 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008375
Keith Packard199e5d72011-09-22 12:01:57 -07008376 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07008377 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07008378 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008379 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02008380 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008381 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07008382
8383 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008384 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07008385 POSTING_READ(PCH_DREF_CONTROL);
8386 udelay(200);
8387
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008388 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07008389
8390 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07008391 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07008392 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07008393 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008394 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Robin Schroereba905b2014-05-18 02:24:50 +02008395 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008396 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07008397 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008398 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07008399
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008400 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07008401 POSTING_READ(PCH_DREF_CONTROL);
8402 udelay(200);
8403 } else {
8404 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8405
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008406 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07008407
8408 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008409 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07008410
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008411 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07008412 POSTING_READ(PCH_DREF_CONTROL);
8413 udelay(200);
8414
8415 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008416 val &= ~DREF_SSC_SOURCE_MASK;
8417 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07008418
8419 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008420 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07008421
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008422 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008423 POSTING_READ(PCH_DREF_CONTROL);
8424 udelay(200);
8425 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07008426
8427 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07008428}
8429
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008430static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02008431{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008432 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02008433
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008434 tmp = I915_READ(SOUTH_CHICKEN2);
8435 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8436 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008437
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008438 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8439 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8440 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02008441
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008442 tmp = I915_READ(SOUTH_CHICKEN2);
8443 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8444 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008445
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008446 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8447 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8448 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008449}
8450
8451/* WaMPhyProgramming:hsw */
8452static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8453{
8454 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02008455
8456 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8457 tmp &= ~(0xFF << 24);
8458 tmp |= (0x12 << 24);
8459 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8460
Paulo Zanonidde86e22012-12-01 12:04:25 -02008461 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8462 tmp |= (1 << 11);
8463 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8466 tmp |= (1 << 11);
8467 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8468
Paulo Zanonidde86e22012-12-01 12:04:25 -02008469 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8470 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8471 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8474 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8475 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8476
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008477 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8478 tmp &= ~(7 << 13);
8479 tmp |= (5 << 13);
8480 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008481
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008482 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8483 tmp &= ~(7 << 13);
8484 tmp |= (5 << 13);
8485 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008486
8487 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8488 tmp &= ~0xFF;
8489 tmp |= 0x1C;
8490 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8491
8492 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8493 tmp &= ~0xFF;
8494 tmp |= 0x1C;
8495 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8496
8497 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8498 tmp &= ~(0xFF << 16);
8499 tmp |= (0x1C << 16);
8500 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8501
8502 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8503 tmp &= ~(0xFF << 16);
8504 tmp |= (0x1C << 16);
8505 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8506
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008507 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8508 tmp |= (1 << 27);
8509 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008510
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008511 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8512 tmp |= (1 << 27);
8513 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008514
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008515 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8516 tmp &= ~(0xF << 28);
8517 tmp |= (4 << 28);
8518 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008519
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03008520 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8521 tmp &= ~(0xF << 28);
8522 tmp |= (4 << 28);
8523 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008524}
8525
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008526/* Implements 3 different sequences from BSpec chapter "Display iCLK
8527 * Programming" based on the parameters passed:
8528 * - Sequence to enable CLKOUT_DP
8529 * - Sequence to enable CLKOUT_DP without spread
8530 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8531 */
8532static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8533 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008534{
8535 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008536 uint32_t reg, tmp;
8537
8538 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8539 with_spread = true;
Ville Syrjäläc2699522015-08-27 23:55:59 +03008540 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008541 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008542
Ville Syrjäläa5805162015-05-26 20:42:30 +03008543 mutex_lock(&dev_priv->sb_lock);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008544
8545 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8546 tmp &= ~SBI_SSCCTL_DISABLE;
8547 tmp |= SBI_SSCCTL_PATHALT;
8548 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8549
8550 udelay(24);
8551
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008552 if (with_spread) {
8553 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8554 tmp &= ~SBI_SSCCTL_PATHALT;
8555 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03008556
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008557 if (with_fdi) {
8558 lpt_reset_fdi_mphy(dev_priv);
8559 lpt_program_fdi_mphy(dev_priv);
8560 }
8561 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02008562
Ville Syrjäläc2699522015-08-27 23:55:59 +03008563 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03008564 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8565 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8566 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01008567
Ville Syrjäläa5805162015-05-26 20:42:30 +03008568 mutex_unlock(&dev_priv->sb_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02008569}
8570
Paulo Zanoni47701c32013-07-23 11:19:25 -03008571/* Sequence to disable CLKOUT_DP */
8572static void lpt_disable_clkout_dp(struct drm_device *dev)
8573{
8574 struct drm_i915_private *dev_priv = dev->dev_private;
8575 uint32_t reg, tmp;
8576
Ville Syrjäläa5805162015-05-26 20:42:30 +03008577 mutex_lock(&dev_priv->sb_lock);
Paulo Zanoni47701c32013-07-23 11:19:25 -03008578
Ville Syrjäläc2699522015-08-27 23:55:59 +03008579 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
Paulo Zanoni47701c32013-07-23 11:19:25 -03008580 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8581 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8582 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8583
8584 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8585 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8586 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8587 tmp |= SBI_SSCCTL_PATHALT;
8588 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8589 udelay(32);
8590 }
8591 tmp |= SBI_SSCCTL_DISABLE;
8592 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8593 }
8594
Ville Syrjäläa5805162015-05-26 20:42:30 +03008595 mutex_unlock(&dev_priv->sb_lock);
Paulo Zanoni47701c32013-07-23 11:19:25 -03008596}
8597
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008598#define BEND_IDX(steps) ((50 + (steps)) / 5)
8599
8600static const uint16_t sscdivintphase[] = {
8601 [BEND_IDX( 50)] = 0x3B23,
8602 [BEND_IDX( 45)] = 0x3B23,
8603 [BEND_IDX( 40)] = 0x3C23,
8604 [BEND_IDX( 35)] = 0x3C23,
8605 [BEND_IDX( 30)] = 0x3D23,
8606 [BEND_IDX( 25)] = 0x3D23,
8607 [BEND_IDX( 20)] = 0x3E23,
8608 [BEND_IDX( 15)] = 0x3E23,
8609 [BEND_IDX( 10)] = 0x3F23,
8610 [BEND_IDX( 5)] = 0x3F23,
8611 [BEND_IDX( 0)] = 0x0025,
8612 [BEND_IDX( -5)] = 0x0025,
8613 [BEND_IDX(-10)] = 0x0125,
8614 [BEND_IDX(-15)] = 0x0125,
8615 [BEND_IDX(-20)] = 0x0225,
8616 [BEND_IDX(-25)] = 0x0225,
8617 [BEND_IDX(-30)] = 0x0325,
8618 [BEND_IDX(-35)] = 0x0325,
8619 [BEND_IDX(-40)] = 0x0425,
8620 [BEND_IDX(-45)] = 0x0425,
8621 [BEND_IDX(-50)] = 0x0525,
8622};
8623
8624/*
8625 * Bend CLKOUT_DP
8626 * steps -50 to 50 inclusive, in steps of 5
8627 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8628 * change in clock period = -(steps / 10) * 5.787 ps
8629 */
8630static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8631{
8632 uint32_t tmp;
8633 int idx = BEND_IDX(steps);
8634
8635 if (WARN_ON(steps % 5 != 0))
8636 return;
8637
8638 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8639 return;
8640
8641 mutex_lock(&dev_priv->sb_lock);
8642
8643 if (steps % 10 != 0)
8644 tmp = 0xAAAAAAAB;
8645 else
8646 tmp = 0x00000000;
8647 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8648
8649 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8650 tmp &= 0xffff0000;
8651 tmp |= sscdivintphase[idx];
8652 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8653
8654 mutex_unlock(&dev_priv->sb_lock);
8655}
8656
8657#undef BEND_IDX
8658
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008659static void lpt_init_pch_refclk(struct drm_device *dev)
8660{
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008661 struct intel_encoder *encoder;
8662 bool has_vga = false;
8663
Damien Lespiaub2784e12014-08-05 11:29:37 +01008664 for_each_intel_encoder(dev, encoder) {
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008665 switch (encoder->type) {
8666 case INTEL_OUTPUT_ANALOG:
8667 has_vga = true;
8668 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008669 default:
8670 break;
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008671 }
8672 }
8673
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008674 if (has_vga) {
8675 lpt_bend_clkout_dp(to_i915(dev), 0);
Paulo Zanoni47701c32013-07-23 11:19:25 -03008676 lpt_enable_clkout_dp(dev, true, true);
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008677 } else {
Paulo Zanoni47701c32013-07-23 11:19:25 -03008678 lpt_disable_clkout_dp(dev);
Ville Syrjäläf7be2c22015-12-04 22:19:39 +02008679 }
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03008680}
8681
Paulo Zanonidde86e22012-12-01 12:04:25 -02008682/*
8683 * Initialize reference clocks when the driver loads
8684 */
8685void intel_init_pch_refclk(struct drm_device *dev)
8686{
8687 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8688 ironlake_init_pch_refclk(dev);
8689 else if (HAS_PCH_LPT(dev))
8690 lpt_init_pch_refclk(dev);
8691}
8692
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008693static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008694{
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008695 struct drm_device *dev = crtc_state->base.crtc->dev;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008696 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008697 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008698 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008699 struct drm_connector_state *connector_state;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008700 struct intel_encoder *encoder;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008701 int num_connectors = 0, i;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008702 bool is_lvds = false;
8703
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008704 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008705 if (connector_state->crtc != crtc_state->base.crtc)
8706 continue;
8707
8708 encoder = to_intel_encoder(connector_state->best_encoder);
8709
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008710 switch (encoder->type) {
8711 case INTEL_OUTPUT_LVDS:
8712 is_lvds = true;
8713 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008714 default:
8715 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008716 }
8717 num_connectors++;
8718 }
8719
8720 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008721 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03008722 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008723 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07008724 }
8725
8726 return 120000;
8727}
8728
Daniel Vetter6ff93602013-04-19 11:24:36 +02008729static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03008730{
8731 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8733 int pipe = intel_crtc->pipe;
8734 uint32_t val;
8735
Daniel Vetter78114072013-06-13 00:54:57 +02008736 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03008737
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008738 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03008739 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008740 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008741 break;
8742 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008743 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008744 break;
8745 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008746 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008747 break;
8748 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01008749 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03008750 break;
8751 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03008752 /* Case prevented by intel_choose_pipe_bpp_dither. */
8753 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03008754 }
8755
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008756 if (intel_crtc->config->dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03008757 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8758
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008759 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03008760 val |= PIPECONF_INTERLACED_ILK;
8761 else
8762 val |= PIPECONF_PROGRESSIVE;
8763
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008764 if (intel_crtc->config->limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02008765 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02008766
Paulo Zanonic8203562012-09-12 10:06:29 -03008767 I915_WRITE(PIPECONF(pipe), val);
8768 POSTING_READ(PIPECONF(pipe));
8769}
8770
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008771/*
8772 * Set up the pipe CSC unit.
8773 *
8774 * Currently only full range RGB to limited range RGB conversion
8775 * is supported, but eventually this should handle various
8776 * RGB<->YCbCr scenarios as well.
8777 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01008778static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008779{
8780 struct drm_device *dev = crtc->dev;
8781 struct drm_i915_private *dev_priv = dev->dev_private;
8782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8783 int pipe = intel_crtc->pipe;
8784 uint16_t coeff = 0x7800; /* 1.0 */
8785
8786 /*
8787 * TODO: Check what kind of values actually come out of the pipe
8788 * with these coeff/postoff values and adjust to get the best
8789 * accuracy. Perhaps we even need to take the bpc value into
8790 * consideration.
8791 */
8792
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008793 if (intel_crtc->config->limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008794 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8795
8796 /*
8797 * GY/GU and RY/RU should be the other way around according
8798 * to BSpec, but reality doesn't agree. Just set them up in
8799 * a way that results in the correct picture.
8800 */
8801 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8802 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8803
8804 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8805 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8806
8807 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8808 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8809
8810 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8811 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8812 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8813
8814 if (INTEL_INFO(dev)->gen > 6) {
8815 uint16_t postoff = 0;
8816
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008817 if (intel_crtc->config->limited_color_range)
Ville Syrjälä32cf0cb2013-11-28 22:10:38 +02008818 postoff = (16 * (1 << 12) / 255) & 0x1fff;
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008819
8820 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8821 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8822 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8823
8824 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8825 } else {
8826 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8827
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008828 if (intel_crtc->config->limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02008829 mode |= CSC_BLACK_SCREEN_OFFSET;
8830
8831 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8832 }
8833}
8834
Daniel Vetter6ff93602013-04-19 11:24:36 +02008835static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008836{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008837 struct drm_device *dev = crtc->dev;
8838 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008840 enum pipe pipe = intel_crtc->pipe;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008841 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008842 uint32_t val;
8843
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02008844 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008845
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008846 if (IS_HASWELL(dev) && intel_crtc->config->dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008847 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8848
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008849 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008850 val |= PIPECONF_INTERLACED_ILK;
8851 else
8852 val |= PIPECONF_PROGRESSIVE;
8853
Paulo Zanoni702e7a52012-10-23 18:29:59 -02008854 I915_WRITE(PIPECONF(cpu_transcoder), val);
8855 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02008856
8857 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8858 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008859
Satheeshakrishna M3cdf1222014-04-08 15:46:53 +05308860 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008861 val = 0;
8862
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008863 switch (intel_crtc->config->pipe_bpp) {
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008864 case 18:
8865 val |= PIPEMISC_DITHER_6_BPC;
8866 break;
8867 case 24:
8868 val |= PIPEMISC_DITHER_8_BPC;
8869 break;
8870 case 30:
8871 val |= PIPEMISC_DITHER_10_BPC;
8872 break;
8873 case 36:
8874 val |= PIPEMISC_DITHER_12_BPC;
8875 break;
8876 default:
8877 /* Case prevented by pipe_config_set_bpp. */
8878 BUG();
8879 }
8880
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02008881 if (intel_crtc->config->dither)
Paulo Zanoni756f85c2013-11-02 21:07:38 -07008882 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8883
8884 I915_WRITE(PIPEMISC(pipe), val);
8885 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03008886}
8887
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008888static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008889 struct intel_crtc_state *crtc_state,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008890 intel_clock_t *clock,
8891 bool *has_reduced_clock,
8892 intel_clock_t *reduced_clock)
8893{
8894 struct drm_device *dev = crtc->dev;
8895 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008896 int refclk;
8897 const intel_limit_t *limit;
Daniel Vetterc329a4e2015-06-18 10:30:23 +02008898 bool ret;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008899
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008900 refclk = ironlake_get_refclk(crtc_state);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008901
8902 /*
8903 * Returns a set of divisors for the desired target clock with the given
8904 * refclk, or FALSE. The returned values represent the clock equation:
8905 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8906 */
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +02008907 limit = intel_limit(crtc_state, refclk);
8908 ret = dev_priv->display.find_dpll(limit, crtc_state,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008909 crtc_state->port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02008910 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008911 if (!ret)
8912 return false;
8913
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03008914 return true;
8915}
8916
Paulo Zanonid4b19312012-11-29 11:29:32 -02008917int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8918{
8919 /*
8920 * Account for spread spectrum to avoid
8921 * oversubscribing the link. Max center spread
8922 * is 2.5%; use 5% for safety's sake.
8923 */
8924 u32 bps = target_clock * bpp * 21 / 20;
Ville Syrjälä619d4d02014-02-27 14:23:14 +02008925 return DIV_ROUND_UP(bps, link_bw * 8);
Paulo Zanonid4b19312012-11-29 11:29:32 -02008926}
8927
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008928static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02008929{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008930 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03008931}
8932
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008933static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008934 struct intel_crtc_state *crtc_state,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02008935 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02008936 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008937{
8938 struct drm_crtc *crtc = &intel_crtc->base;
8939 struct drm_device *dev = crtc->dev;
8940 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008941 struct drm_atomic_state *state = crtc_state->base.state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008942 struct drm_connector *connector;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008943 struct drm_connector_state *connector_state;
8944 struct intel_encoder *encoder;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008945 uint32_t dpll;
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008946 int factor, num_connectors = 0, i;
Daniel Vetter09ede542013-04-30 14:01:45 +02008947 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008948
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +03008949 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira55bb9992015-03-20 16:18:19 +02008950 if (connector_state->crtc != crtc_state->base.crtc)
8951 continue;
8952
8953 encoder = to_intel_encoder(connector_state->best_encoder);
8954
8955 switch (encoder->type) {
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008956 case INTEL_OUTPUT_LVDS:
8957 is_lvds = true;
8958 break;
8959 case INTEL_OUTPUT_SDVO:
8960 case INTEL_OUTPUT_HDMI:
8961 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008962 break;
Paulo Zanoni6847d71b2014-10-27 17:47:52 -02008963 default:
8964 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03008965 }
8966
8967 num_connectors++;
8968 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008969
Chris Wilsonc1858122010-12-03 21:35:48 +00008970 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07008971 factor = 21;
8972 if (is_lvds) {
8973 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02008974 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02008975 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07008976 factor = 25;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008977 } else if (crtc_state->sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07008978 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00008979
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008980 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02008981 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00008982
Daniel Vetter9a7c7892013-04-04 22:20:34 +02008983 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8984 *fp2 |= FP_CB_TUNE;
8985
Chris Wilson5eddb702010-09-11 13:48:45 +01008986 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08008987
Eric Anholta07d6782011-03-30 13:01:08 -07008988 if (is_lvds)
8989 dpll |= DPLLB_MODE_LVDS;
8990 else
8991 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02008992
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008993 dpll |= (crtc_state->pixel_multiplier - 1)
Daniel Vetteref1b4602013-06-01 17:17:04 +02008994 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02008995
8996 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02008997 dpll |= DPLL_SDVO_HIGH_SPEED;
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02008998 if (crtc_state->has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02008999 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08009000
Eric Anholta07d6782011-03-30 13:01:08 -07009001 /* compute bitmask from p1 value */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009002 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07009003 /* also FPA1 */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009004 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07009005
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009006 switch (crtc_state->dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07009007 case 5:
9008 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9009 break;
9010 case 7:
9011 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9012 break;
9013 case 10:
9014 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9015 break;
9016 case 14:
9017 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9018 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08009019 }
9020
Daniel Vetterb4c09f32013-04-30 14:01:42 +02009021 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05009022 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08009023 else
9024 dpll |= PLL_REF_INPUT_DREFCLK;
9025
Daniel Vetter959e16d2013-06-05 13:34:21 +02009026 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03009027}
9028
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009029static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9030 struct intel_crtc_state *crtc_state)
Jesse Barnes79e53942008-11-07 14:24:08 -08009031{
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009032 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08009033 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02009034 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03009035 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01009036 bool is_lvds = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02009037 struct intel_shared_dpll *pll;
Jesse Barnes79e53942008-11-07 14:24:08 -08009038
Ander Conselvan de Oliveiradd3cd742015-05-15 13:34:29 +03009039 memset(&crtc_state->dpll_hw_state, 0,
9040 sizeof(crtc_state->dpll_hw_state));
9041
Ville Syrjälä7905df22015-11-25 16:35:30 +02009042 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
Jesse Barnes79e53942008-11-07 14:24:08 -08009043
Paulo Zanoni5dc52982012-10-05 12:05:56 -03009044 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9045 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9046
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009047 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03009048 &has_reduced_clock, &reduced_clock);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009049 if (!ok && !crtc_state->clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009050 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9051 return -EINVAL;
9052 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01009053 /* Compat-code for transition, will disappear. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009054 if (!crtc_state->clock_set) {
9055 crtc_state->dpll.n = clock.n;
9056 crtc_state->dpll.m1 = clock.m1;
9057 crtc_state->dpll.m2 = clock.m2;
9058 crtc_state->dpll.p1 = clock.p1;
9059 crtc_state->dpll.p2 = clock.p2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01009060 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009061
Paulo Zanoni5dc52982012-10-05 12:05:56 -03009062 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009063 if (crtc_state->has_pch_encoder) {
9064 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02009065 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02009066 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02009067
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009068 dpll = ironlake_compute_dpll(crtc, crtc_state,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02009069 &fp, &reduced_clock,
9070 has_reduced_clock ? &fp2 : NULL);
9071
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009072 crtc_state->dpll_hw_state.dpll = dpll;
9073 crtc_state->dpll_hw_state.fp0 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02009074 if (has_reduced_clock)
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009075 crtc_state->dpll_hw_state.fp1 = fp2;
Daniel Vetter66e985c2013-06-05 13:34:20 +02009076 else
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009077 crtc_state->dpll_hw_state.fp1 = fp;
Daniel Vetter66e985c2013-06-05 13:34:20 +02009078
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009079 pll = intel_get_shared_dpll(crtc, crtc_state);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009080 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03009081 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009082 pipe_name(crtc->pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07009083 return -EINVAL;
9084 }
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +02009085 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009086
Rodrigo Viviab585de2015-03-24 12:40:09 -07009087 if (is_lvds && has_reduced_clock)
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009088 crtc->lowfreq_avail = true;
Daniel Vetterbcd644e2013-06-05 13:34:22 +02009089 else
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009090 crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02009091
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02009092 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009093}
9094
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009095static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9096 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02009097{
9098 struct drm_device *dev = crtc->base.dev;
9099 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009100 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02009101
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009102 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9103 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9104 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9105 & ~TU_SIZE_MASK;
9106 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9107 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9108 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9109}
9110
9111static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9112 enum transcoder transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009113 struct intel_link_m_n *m_n,
9114 struct intel_link_m_n *m2_n2)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009115{
9116 struct drm_device *dev = crtc->base.dev;
9117 struct drm_i915_private *dev_priv = dev->dev_private;
9118 enum pipe pipe = crtc->pipe;
9119
9120 if (INTEL_INFO(dev)->gen >= 5) {
9121 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9122 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9123 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9124 & ~TU_SIZE_MASK;
9125 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9126 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9127 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009128 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9129 * gen < 8) and if DRRS is supported (to make sure the
9130 * registers are not unnecessarily read).
9131 */
9132 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +02009133 crtc->config->has_drrs) {
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009134 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9135 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9136 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9137 & ~TU_SIZE_MASK;
9138 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9139 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9140 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9141 }
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009142 } else {
9143 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9144 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9145 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9146 & ~TU_SIZE_MASK;
9147 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9148 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9149 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9150 }
9151}
9152
9153void intel_dp_get_m_n(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009154 struct intel_crtc_state *pipe_config)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009155{
Ander Conselvan de Oliveira681a8502015-01-15 14:55:24 +02009156 if (pipe_config->has_pch_encoder)
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009157 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9158 else
9159 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009160 &pipe_config->dp_m_n,
9161 &pipe_config->dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009162}
9163
Daniel Vetter72419202013-04-04 13:28:53 +02009164static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009165 struct intel_crtc_state *pipe_config)
Daniel Vetter72419202013-04-04 13:28:53 +02009166{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009167 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
Vandana Kannanb95af8b2014-08-05 07:51:23 -07009168 &pipe_config->fdi_m_n, NULL);
Daniel Vetter72419202013-04-04 13:28:53 +02009169}
9170
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009171static void skylake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009172 struct intel_crtc_state *pipe_config)
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009173{
9174 struct drm_device *dev = crtc->base.dev;
9175 struct drm_i915_private *dev_priv = dev->dev_private;
Chandra Kondurua1b22782015-04-07 15:28:45 -07009176 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9177 uint32_t ps_ctrl = 0;
9178 int id = -1;
9179 int i;
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009180
Chandra Kondurua1b22782015-04-07 15:28:45 -07009181 /* find scaler attached to this pipe */
9182 for (i = 0; i < crtc->num_scalers; i++) {
9183 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9184 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9185 id = i;
9186 pipe_config->pch_pfit.enabled = true;
9187 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9188 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9189 break;
9190 }
9191 }
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009192
Chandra Kondurua1b22782015-04-07 15:28:45 -07009193 scaler_state->scaler_id = id;
9194 if (id >= 0) {
9195 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9196 } else {
9197 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
Jesse Barnesbd2e2442014-11-13 17:51:47 +00009198 }
9199}
9200
Damien Lespiau5724dbd2015-01-20 12:51:52 +00009201static void
9202skylake_get_initial_plane_config(struct intel_crtc *crtc,
9203 struct intel_initial_plane_config *plane_config)
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009204{
9205 struct drm_device *dev = crtc->base.dev;
9206 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau40f46282015-02-27 11:15:21 +00009207 u32 val, base, offset, stride_mult, tiling;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009208 int pipe = crtc->pipe;
9209 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00009210 unsigned int aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009211 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00009212 struct intel_framebuffer *intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009213
Damien Lespiaud9806c92015-01-21 14:07:19 +00009214 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00009215 if (!intel_fb) {
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009216 DRM_DEBUG_KMS("failed to alloc fb\n");
9217 return;
9218 }
9219
Damien Lespiau1b842c82015-01-21 13:50:54 +00009220 fb = &intel_fb->base;
9221
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009222 val = I915_READ(PLANE_CTL(pipe, 0));
Damien Lespiau42a7b082015-02-05 19:35:13 +00009223 if (!(val & PLANE_CTL_ENABLE))
9224 goto error;
9225
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009226 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9227 fourcc = skl_format_to_fourcc(pixel_format,
9228 val & PLANE_CTL_ORDER_RGBX,
9229 val & PLANE_CTL_ALPHA_MASK);
9230 fb->pixel_format = fourcc;
9231 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9232
Damien Lespiau40f46282015-02-27 11:15:21 +00009233 tiling = val & PLANE_CTL_TILED_MASK;
9234 switch (tiling) {
9235 case PLANE_CTL_TILED_LINEAR:
9236 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9237 break;
9238 case PLANE_CTL_TILED_X:
9239 plane_config->tiling = I915_TILING_X;
9240 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9241 break;
9242 case PLANE_CTL_TILED_Y:
9243 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9244 break;
9245 case PLANE_CTL_TILED_YF:
9246 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9247 break;
9248 default:
9249 MISSING_CASE(tiling);
9250 goto error;
9251 }
9252
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009253 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9254 plane_config->base = base;
9255
9256 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9257
9258 val = I915_READ(PLANE_SIZE(pipe, 0));
9259 fb->height = ((val >> 16) & 0xfff) + 1;
9260 fb->width = ((val >> 0) & 0x1fff) + 1;
9261
9262 val = I915_READ(PLANE_STRIDE(pipe, 0));
Damien Lespiau40f46282015-02-27 11:15:21 +00009263 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9264 fb->pixel_format);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009265 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9266
9267 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00009268 fb->pixel_format,
9269 fb->modifier[0]);
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009270
Daniel Vetterf37b5c22015-02-10 23:12:27 +01009271 plane_config->size = fb->pitches[0] * aligned_height;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009272
9273 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9274 pipe_name(pipe), fb->width, fb->height,
9275 fb->bits_per_pixel, base, fb->pitches[0],
9276 plane_config->size);
9277
Damien Lespiau2d140302015-02-05 17:22:18 +00009278 plane_config->fb = intel_fb;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +00009279 return;
9280
9281error:
9282 kfree(fb);
9283}
9284
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009285static void ironlake_get_pfit_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009286 struct intel_crtc_state *pipe_config)
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009287{
9288 struct drm_device *dev = crtc->base.dev;
9289 struct drm_i915_private *dev_priv = dev->dev_private;
9290 uint32_t tmp;
9291
9292 tmp = I915_READ(PF_CTL(crtc->pipe));
9293
9294 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009295 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009296 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9297 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02009298
9299 /* We currently do not free assignements of panel fitters on
9300 * ivb/hsw (since we don't use the higher upscaling modes which
9301 * differentiates them) so just WARN about this case for now. */
9302 if (IS_GEN7(dev)) {
9303 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9304 PF_PIPE_SEL_IVB(crtc->pipe));
9305 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009306 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009307}
9308
Damien Lespiau5724dbd2015-01-20 12:51:52 +00009309static void
9310ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9311 struct intel_initial_plane_config *plane_config)
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009312{
9313 struct drm_device *dev = crtc->base.dev;
9314 struct drm_i915_private *dev_priv = dev->dev_private;
9315 u32 val, base, offset;
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009316 int pipe = crtc->pipe;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009317 int fourcc, pixel_format;
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00009318 unsigned int aligned_height;
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009319 struct drm_framebuffer *fb;
Damien Lespiau1b842c82015-01-21 13:50:54 +00009320 struct intel_framebuffer *intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009321
Damien Lespiau42a7b082015-02-05 19:35:13 +00009322 val = I915_READ(DSPCNTR(pipe));
9323 if (!(val & DISPLAY_PLANE_ENABLE))
9324 return;
9325
Damien Lespiaud9806c92015-01-21 14:07:19 +00009326 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Damien Lespiau1b842c82015-01-21 13:50:54 +00009327 if (!intel_fb) {
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009328 DRM_DEBUG_KMS("failed to alloc fb\n");
9329 return;
9330 }
9331
Damien Lespiau1b842c82015-01-21 13:50:54 +00009332 fb = &intel_fb->base;
9333
Daniel Vetter18c52472015-02-10 17:16:09 +00009334 if (INTEL_INFO(dev)->gen >= 4) {
9335 if (val & DISPPLANE_TILED) {
Damien Lespiau49af4492015-01-20 12:51:44 +00009336 plane_config->tiling = I915_TILING_X;
Daniel Vetter18c52472015-02-10 17:16:09 +00009337 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9338 }
9339 }
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009340
9341 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
Damien Lespiaub35d63f2015-01-20 12:51:50 +00009342 fourcc = i9xx_format_to_fourcc(pixel_format);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009343 fb->pixel_format = fourcc;
9344 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009345
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009346 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009347 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009348 offset = I915_READ(DSPOFFSET(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009349 } else {
Damien Lespiau49af4492015-01-20 12:51:44 +00009350 if (plane_config->tiling)
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009351 offset = I915_READ(DSPTILEOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009352 else
Damien Lespiauaeee5a42015-01-20 12:51:47 +00009353 offset = I915_READ(DSPLINOFF(pipe));
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009354 }
9355 plane_config->base = base;
9356
9357 val = I915_READ(PIPESRC(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009358 fb->width = ((val >> 16) & 0xfff) + 1;
9359 fb->height = ((val >> 0) & 0xfff) + 1;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009360
9361 val = I915_READ(DSPSTRIDE(pipe));
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009362 fb->pitches[0] = val & 0xffffffc0;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009363
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009364 aligned_height = intel_fb_align_height(dev, fb->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +00009365 fb->pixel_format,
9366 fb->modifier[0]);
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009367
Daniel Vetterf37b5c22015-02-10 23:12:27 +01009368 plane_config->size = fb->pitches[0] * aligned_height;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009369
Damien Lespiau2844a922015-01-20 12:51:48 +00009370 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9371 pipe_name(pipe), fb->width, fb->height,
9372 fb->bits_per_pixel, base, fb->pitches[0],
9373 plane_config->size);
Damien Lespiaub113d5e2015-01-20 12:51:46 +00009374
Damien Lespiau2d140302015-02-05 17:22:18 +00009375 plane_config->fb = intel_fb;
Jesse Barnes4c6baa52014-03-07 08:57:50 -08009376}
9377
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009378static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009379 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009380{
9381 struct drm_device *dev = crtc->base.dev;
9382 struct drm_i915_private *dev_priv = dev->dev_private;
9383 uint32_t tmp;
9384
Daniel Vetterf458ebb2014-09-30 10:56:39 +02009385 if (!intel_display_power_is_enabled(dev_priv,
9386 POWER_DOMAIN_PIPE(crtc->pipe)))
Paulo Zanoni930e8c92014-07-04 13:38:34 -03009387 return false;
9388
Daniel Vettere143a212013-07-04 12:01:15 +02009389 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009390 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02009391
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009392 tmp = I915_READ(PIPECONF(crtc->pipe));
9393 if (!(tmp & PIPECONF_ENABLE))
9394 return false;
9395
Ville Syrjälä42571ae2013-09-06 23:29:00 +03009396 switch (tmp & PIPECONF_BPC_MASK) {
9397 case PIPECONF_6BPC:
9398 pipe_config->pipe_bpp = 18;
9399 break;
9400 case PIPECONF_8BPC:
9401 pipe_config->pipe_bpp = 24;
9402 break;
9403 case PIPECONF_10BPC:
9404 pipe_config->pipe_bpp = 30;
9405 break;
9406 case PIPECONF_12BPC:
9407 pipe_config->pipe_bpp = 36;
9408 break;
9409 default:
9410 break;
9411 }
9412
Daniel Vetterb5a9fa02014-04-24 23:54:49 +02009413 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9414 pipe_config->limited_color_range = true;
9415
Daniel Vetterab9412b2013-05-03 11:49:46 +02009416 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02009417 struct intel_shared_dpll *pll;
9418
Daniel Vetter88adfff2013-03-28 10:42:01 +01009419 pipe_config->has_pch_encoder = true;
9420
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009421 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9422 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9423 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02009424
9425 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009426
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009427 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02009428 pipe_config->shared_dpll =
9429 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009430 } else {
9431 tmp = I915_READ(PCH_DPLL_SEL);
9432 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9433 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9434 else
9435 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9436 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02009437
9438 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9439
9440 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9441 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009442
9443 tmp = pipe_config->dpll_hw_state.dpll;
9444 pipe_config->pixel_multiplier =
9445 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9446 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03009447
9448 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009449 } else {
9450 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009451 }
9452
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009453 intel_get_pipe_timings(crtc, pipe_config);
9454
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009455 ironlake_get_pfit_config(crtc, pipe_config);
9456
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009457 return true;
9458}
9459
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009460static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9461{
9462 struct drm_device *dev = dev_priv->dev;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009463 struct intel_crtc *crtc;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009464
Damien Lespiaud3fcc802014-05-13 23:32:22 +01009465 for_each_intel_crtc(dev, crtc)
Rob Clarke2c719b2014-12-15 13:56:32 -05009466 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009467 pipe_name(crtc->pipe));
9468
Rob Clarke2c719b2014-12-15 13:56:32 -05009469 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9470 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
Ville Syrjälä01403de2015-09-18 20:03:33 +03009471 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9472 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05009473 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9474 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009475 "CPU PWM1 enabled\n");
Paulo Zanonic5107b82014-07-04 11:50:30 -03009476 if (IS_HASWELL(dev))
Rob Clarke2c719b2014-12-15 13:56:32 -05009477 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
Paulo Zanonic5107b82014-07-04 11:50:30 -03009478 "CPU PWM2 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05009479 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009480 "PCH PWM1 enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05009481 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009482 "Utility pin enabled\n");
Rob Clarke2c719b2014-12-15 13:56:32 -05009483 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009484
Paulo Zanoni9926ada2014-04-01 19:39:47 -03009485 /*
9486 * In theory we can still leave IRQs enabled, as long as only the HPD
9487 * interrupts remain enabled. We used to check for that, but since it's
9488 * gen-specific and since we only disable LCPLL after we fully disable
9489 * the interrupts, the check below should be enough.
9490 */
Rob Clarke2c719b2014-12-15 13:56:32 -05009491 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009492}
9493
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009494static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9495{
9496 struct drm_device *dev = dev_priv->dev;
9497
9498 if (IS_HASWELL(dev))
9499 return I915_READ(D_COMP_HSW);
9500 else
9501 return I915_READ(D_COMP_BDW);
9502}
9503
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009504static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9505{
9506 struct drm_device *dev = dev_priv->dev;
9507
9508 if (IS_HASWELL(dev)) {
9509 mutex_lock(&dev_priv->rps.hw_lock);
9510 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9511 val))
Paulo Zanonif475dad2014-07-04 11:59:57 -03009512 DRM_ERROR("Failed to write to D_COMP\n");
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009513 mutex_unlock(&dev_priv->rps.hw_lock);
9514 } else {
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009515 I915_WRITE(D_COMP_BDW, val);
9516 POSTING_READ(D_COMP_BDW);
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009517 }
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009518}
9519
9520/*
9521 * This function implements pieces of two sequences from BSpec:
9522 * - Sequence for display software to disable LCPLL
9523 * - Sequence for display software to allow package C8+
9524 * The steps implemented here are just the steps that actually touch the LCPLL
9525 * register. Callers should take care of disabling all the display engine
9526 * functions, doing the mode unset, fixing interrupts, etc.
9527 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03009528static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9529 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009530{
9531 uint32_t val;
9532
9533 assert_can_disable_lcpll(dev_priv);
9534
9535 val = I915_READ(LCPLL_CTL);
9536
9537 if (switch_to_fclk) {
9538 val |= LCPLL_CD_SOURCE_FCLK;
9539 I915_WRITE(LCPLL_CTL, val);
9540
9541 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9542 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9543 DRM_ERROR("Switching to FCLK failed\n");
9544
9545 val = I915_READ(LCPLL_CTL);
9546 }
9547
9548 val |= LCPLL_PLL_DISABLE;
9549 I915_WRITE(LCPLL_CTL, val);
9550 POSTING_READ(LCPLL_CTL);
9551
9552 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9553 DRM_ERROR("LCPLL still locked\n");
9554
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009555 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009556 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009557 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009558 ndelay(100);
9559
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009560 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9561 1))
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009562 DRM_ERROR("D_COMP RCOMP still in progress\n");
9563
9564 if (allow_power_down) {
9565 val = I915_READ(LCPLL_CTL);
9566 val |= LCPLL_POWER_DOWN_ALLOW;
9567 I915_WRITE(LCPLL_CTL, val);
9568 POSTING_READ(LCPLL_CTL);
9569 }
9570}
9571
9572/*
9573 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9574 * source.
9575 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03009576static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009577{
9578 uint32_t val;
9579
9580 val = I915_READ(LCPLL_CTL);
9581
9582 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9583 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9584 return;
9585
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03009586 /*
9587 * Make sure we're not on PC8 state before disabling PC8, otherwise
9588 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03009589 */
Mika Kuoppala59bad942015-01-16 11:34:40 +02009590 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Paulo Zanoni215733f2013-08-19 13:18:07 -03009591
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009592 if (val & LCPLL_POWER_DOWN_ALLOW) {
9593 val &= ~LCPLL_POWER_DOWN_ALLOW;
9594 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02009595 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009596 }
9597
Paulo Zanoni9ccd5ae2014-07-04 11:59:58 -03009598 val = hsw_read_dcomp(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009599 val |= D_COMP_COMP_FORCE;
9600 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni3c4c9b82014-03-07 20:12:36 -03009601 hsw_write_dcomp(dev_priv, val);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009602
9603 val = I915_READ(LCPLL_CTL);
9604 val &= ~LCPLL_PLL_DISABLE;
9605 I915_WRITE(LCPLL_CTL, val);
9606
9607 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9608 DRM_ERROR("LCPLL not locked yet\n");
9609
9610 if (val & LCPLL_CD_SOURCE_FCLK) {
9611 val = I915_READ(LCPLL_CTL);
9612 val &= ~LCPLL_CD_SOURCE_FCLK;
9613 I915_WRITE(LCPLL_CTL, val);
9614
9615 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9616 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9617 DRM_ERROR("Switching back to LCPLL failed\n");
9618 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03009619
Mika Kuoppala59bad942015-01-16 11:34:40 +02009620 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Ville Syrjäläb6283052015-06-03 15:45:07 +03009621 intel_update_cdclk(dev_priv->dev);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03009622}
9623
Paulo Zanoni765dab672014-03-07 20:08:18 -03009624/*
9625 * Package states C8 and deeper are really deep PC states that can only be
9626 * reached when all the devices on the system allow it, so even if the graphics
9627 * device allows PC8+, it doesn't mean the system will actually get to these
9628 * states. Our driver only allows PC8+ when going into runtime PM.
9629 *
9630 * The requirements for PC8+ are that all the outputs are disabled, the power
9631 * well is disabled and most interrupts are disabled, and these are also
9632 * requirements for runtime PM. When these conditions are met, we manually do
9633 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9634 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9635 * hang the machine.
9636 *
9637 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9638 * the state of some registers, so when we come back from PC8+ we need to
9639 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9640 * need to take care of the registers kept by RC6. Notice that this happens even
9641 * if we don't put the device in PCI D3 state (which is what currently happens
9642 * because of the runtime PM support).
9643 *
9644 * For more, read "Display Sequences for Package C8" on the hardware
9645 * documentation.
9646 */
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03009647void hsw_enable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03009648{
Paulo Zanonic67a4702013-08-19 13:18:09 -03009649 struct drm_device *dev = dev_priv->dev;
9650 uint32_t val;
9651
Paulo Zanonic67a4702013-08-19 13:18:09 -03009652 DRM_DEBUG_KMS("Enabling package C8+\n");
9653
Ville Syrjäläc2699522015-08-27 23:55:59 +03009654 if (HAS_PCH_LPT_LP(dev)) {
Paulo Zanonic67a4702013-08-19 13:18:09 -03009655 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9656 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9657 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9658 }
9659
9660 lpt_disable_clkout_dp(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009661 hsw_disable_lcpll(dev_priv, true, true);
9662}
9663
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03009664void hsw_disable_pc8(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03009665{
9666 struct drm_device *dev = dev_priv->dev;
9667 uint32_t val;
9668
Paulo Zanonic67a4702013-08-19 13:18:09 -03009669 DRM_DEBUG_KMS("Disabling package C8+\n");
9670
9671 hsw_restore_lcpll(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009672 lpt_init_pch_refclk(dev);
9673
Ville Syrjäläc2699522015-08-27 23:55:59 +03009674 if (HAS_PCH_LPT_LP(dev)) {
Paulo Zanonic67a4702013-08-19 13:18:09 -03009675 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9676 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9677 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9678 }
9679
9680 intel_prepare_ddi(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03009681}
9682
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009683static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309684{
Ander Conselvan de Oliveiraa821fc42015-04-21 17:13:23 +03009685 struct drm_device *dev = old_state->dev;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009686 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309687
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009688 broxton_set_cdclk(dev, req_cdclk);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05309689}
9690
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009691/* compute the max rate for new configuration */
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009692static int ilk_max_pixel_rate(struct drm_atomic_state *state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009693{
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009694 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9695 struct drm_i915_private *dev_priv = state->dev->dev_private;
9696 struct drm_crtc *crtc;
9697 struct drm_crtc_state *cstate;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009698 struct intel_crtc_state *crtc_state;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009699 unsigned max_pixel_rate = 0, i;
9700 enum pipe pipe;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009701
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009702 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9703 sizeof(intel_state->min_pixclk));
9704
9705 for_each_crtc_in_state(state, crtc, cstate, i) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009706 int pixel_rate;
9707
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009708 crtc_state = to_intel_crtc_state(cstate);
9709 if (!crtc_state->base.enable) {
9710 intel_state->min_pixclk[i] = 0;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009711 continue;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009712 }
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009713
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009714 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009715
9716 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009717 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009718 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9719
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009720 intel_state->min_pixclk[i] = pixel_rate;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009721 }
9722
Maarten Lankhorst565602d2015-12-10 12:33:57 +01009723 if (!intel_state->active_crtcs)
9724 return 0;
9725
9726 for_each_pipe(dev_priv, pipe)
9727 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9728
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009729 return max_pixel_rate;
9730}
9731
9732static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9733{
9734 struct drm_i915_private *dev_priv = dev->dev_private;
9735 uint32_t val, data;
9736 int ret;
9737
9738 if (WARN((I915_READ(LCPLL_CTL) &
9739 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9740 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9741 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9742 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9743 "trying to change cdclk frequency with cdclk not enabled\n"))
9744 return;
9745
9746 mutex_lock(&dev_priv->rps.hw_lock);
9747 ret = sandybridge_pcode_write(dev_priv,
9748 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9749 mutex_unlock(&dev_priv->rps.hw_lock);
9750 if (ret) {
9751 DRM_ERROR("failed to inform pcode about cdclk change\n");
9752 return;
9753 }
9754
9755 val = I915_READ(LCPLL_CTL);
9756 val |= LCPLL_CD_SOURCE_FCLK;
9757 I915_WRITE(LCPLL_CTL, val);
9758
9759 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9760 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9761 DRM_ERROR("Switching to FCLK failed\n");
9762
9763 val = I915_READ(LCPLL_CTL);
9764 val &= ~LCPLL_CLK_FREQ_MASK;
9765
9766 switch (cdclk) {
9767 case 450000:
9768 val |= LCPLL_CLK_FREQ_450;
9769 data = 0;
9770 break;
9771 case 540000:
9772 val |= LCPLL_CLK_FREQ_54O_BDW;
9773 data = 1;
9774 break;
9775 case 337500:
9776 val |= LCPLL_CLK_FREQ_337_5_BDW;
9777 data = 2;
9778 break;
9779 case 675000:
9780 val |= LCPLL_CLK_FREQ_675_BDW;
9781 data = 3;
9782 break;
9783 default:
9784 WARN(1, "invalid cdclk frequency\n");
9785 return;
9786 }
9787
9788 I915_WRITE(LCPLL_CTL, val);
9789
9790 val = I915_READ(LCPLL_CTL);
9791 val &= ~LCPLL_CD_SOURCE_FCLK;
9792 I915_WRITE(LCPLL_CTL, val);
9793
9794 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9795 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9796 DRM_ERROR("Switching back to LCPLL failed\n");
9797
9798 mutex_lock(&dev_priv->rps.hw_lock);
9799 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9800 mutex_unlock(&dev_priv->rps.hw_lock);
9801
9802 intel_update_cdclk(dev);
9803
9804 WARN(cdclk != dev_priv->cdclk_freq,
9805 "cdclk requested %d kHz but got %d kHz\n",
9806 cdclk, dev_priv->cdclk_freq);
9807}
9808
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009809static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009810{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009811 struct drm_i915_private *dev_priv = to_i915(state->dev);
9812 int max_pixclk = ilk_max_pixel_rate(state);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009813 int cdclk;
9814
9815 /*
9816 * FIXME should also account for plane ratio
9817 * once 64bpp pixel formats are supported.
9818 */
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009819 if (max_pixclk > 540000)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009820 cdclk = 675000;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009821 else if (max_pixclk > 450000)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009822 cdclk = 540000;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009823 else if (max_pixclk > 337500)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009824 cdclk = 450000;
9825 else
9826 cdclk = 337500;
9827
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009828 if (cdclk > dev_priv->max_cdclk_freq) {
Maarten Lankhorst63ba5342015-11-24 11:29:03 +01009829 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9830 cdclk, dev_priv->max_cdclk_freq);
9831 return -EINVAL;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009832 }
9833
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009834 to_intel_atomic_state(state)->cdclk = cdclk;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009835
9836 return 0;
9837}
9838
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009839static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009840{
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009841 struct drm_device *dev = old_state->dev;
9842 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009843
Maarten Lankhorst27c329e2015-06-15 12:33:56 +02009844 broadwell_set_cdclk(dev, req_cdclk);
Ville Syrjäläb432e5c2015-06-03 15:45:13 +03009845}
9846
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009847static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9848 struct intel_crtc_state *crtc_state)
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03009849{
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02009850 if (!intel_ddi_pll_select(crtc, crtc_state))
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009851 return -EINVAL;
Daniel Vetter716c2e52014-06-25 22:02:02 +03009852
Ander Conselvan de Oliveirac7653192014-10-20 13:46:44 +03009853 crtc->lowfreq_avail = false;
Daniel Vetter644cef32014-04-24 23:55:07 +02009854
Daniel Vetterc8f7a0d2014-04-24 23:55:04 +02009855 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08009856}
9857
Satheeshakrishna M3760b592014-08-22 09:49:11 +05309858static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9859 enum port port,
9860 struct intel_crtc_state *pipe_config)
9861{
9862 switch (port) {
9863 case PORT_A:
9864 pipe_config->ddi_pll_sel = SKL_DPLL0;
9865 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9866 break;
9867 case PORT_B:
9868 pipe_config->ddi_pll_sel = SKL_DPLL1;
9869 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9870 break;
9871 case PORT_C:
9872 pipe_config->ddi_pll_sel = SKL_DPLL2;
9873 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9874 break;
9875 default:
9876 DRM_ERROR("Incorrect port type\n");
9877 }
9878}
9879
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009880static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9881 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009882 struct intel_crtc_state *pipe_config)
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009883{
Damien Lespiau3148ade2014-11-21 16:14:56 +00009884 u32 temp, dpll_ctl1;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009885
9886 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9887 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9888
9889 switch (pipe_config->ddi_pll_sel) {
Damien Lespiau3148ade2014-11-21 16:14:56 +00009890 case SKL_DPLL0:
9891 /*
9892 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9893 * of the shared DPLL framework and thus needs to be read out
9894 * separately
9895 */
9896 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9897 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9898 break;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009899 case SKL_DPLL1:
9900 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9901 break;
9902 case SKL_DPLL2:
9903 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9904 break;
9905 case SKL_DPLL3:
9906 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9907 break;
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009908 }
9909}
9910
Damien Lespiau7d2c8172014-07-29 18:06:18 +01009911static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9912 enum port port,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009913 struct intel_crtc_state *pipe_config)
Damien Lespiau7d2c8172014-07-29 18:06:18 +01009914{
9915 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9916
9917 switch (pipe_config->ddi_pll_sel) {
9918 case PORT_CLK_SEL_WRPLL1:
9919 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9920 break;
9921 case PORT_CLK_SEL_WRPLL2:
9922 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9923 break;
Maarten Lankhorst00490c22015-11-16 14:42:12 +01009924 case PORT_CLK_SEL_SPLL:
9925 pipe_config->shared_dpll = DPLL_ID_SPLL;
Ville Syrjälä79bd23d2015-12-01 23:32:07 +02009926 break;
Damien Lespiau7d2c8172014-07-29 18:06:18 +01009927 }
9928}
9929
Daniel Vetter26804af2014-06-25 22:01:55 +03009930static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009931 struct intel_crtc_state *pipe_config)
Daniel Vetter26804af2014-06-25 22:01:55 +03009932{
9933 struct drm_device *dev = crtc->base.dev;
9934 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterd452c5b2014-07-04 11:27:39 -03009935 struct intel_shared_dpll *pll;
Daniel Vetter26804af2014-06-25 22:01:55 +03009936 enum port port;
9937 uint32_t tmp;
9938
9939 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9940
9941 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9942
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07009943 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009944 skylake_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M3760b592014-08-22 09:49:11 +05309945 else if (IS_BROXTON(dev))
9946 bxt_get_ddi_pll(dev_priv, port, pipe_config);
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +00009947 else
9948 haswell_get_ddi_pll(dev_priv, port, pipe_config);
Daniel Vetter9cd86932014-06-25 22:01:57 +03009949
Daniel Vetterd452c5b2014-07-04 11:27:39 -03009950 if (pipe_config->shared_dpll >= 0) {
9951 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9952
9953 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9954 &pipe_config->dpll_hw_state));
9955 }
9956
Daniel Vetter26804af2014-06-25 22:01:55 +03009957 /*
9958 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9959 * DDI E. So just check whether this pipe is wired to DDI E and whether
9960 * the PCH transcoder is on.
9961 */
Damien Lespiauca370452013-12-03 13:56:24 +00009962 if (INTEL_INFO(dev)->gen < 9 &&
9963 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
Daniel Vetter26804af2014-06-25 22:01:55 +03009964 pipe_config->has_pch_encoder = true;
9965
9966 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9967 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9968 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9969
9970 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9971 }
9972}
9973
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009974static bool haswell_get_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02009975 struct intel_crtc_state *pipe_config)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009976{
9977 struct drm_device *dev = crtc->base.dev;
9978 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009979 enum intel_display_power_domain pfit_domain;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009980 uint32_t tmp;
9981
Daniel Vetterf458ebb2014-09-30 10:56:39 +02009982 if (!intel_display_power_is_enabled(dev_priv,
Imre Deakb5482bd2014-03-05 16:20:55 +02009983 POWER_DOMAIN_PIPE(crtc->pipe)))
9984 return false;
9985
Daniel Vettere143a212013-07-04 12:01:15 +02009986 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009987 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9988
Daniel Vettereccb1402013-05-22 00:50:22 +02009989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9990 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9991 enum pipe trans_edp_pipe;
9992 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9993 default:
9994 WARN(1, "unknown pipe linked to edp transcoder\n");
9995 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9996 case TRANS_DDI_EDP_INPUT_A_ON:
9997 trans_edp_pipe = PIPE_A;
9998 break;
9999 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10000 trans_edp_pipe = PIPE_B;
10001 break;
10002 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10003 trans_edp_pipe = PIPE_C;
10004 break;
10005 }
10006
10007 if (trans_edp_pipe == crtc->pipe)
10008 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10009 }
10010
Daniel Vetterf458ebb2014-09-30 10:56:39 +020010011 if (!intel_display_power_is_enabled(dev_priv,
Daniel Vettereccb1402013-05-22 00:50:22 +020010012 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
Paulo Zanoni2bfce952013-04-18 16:35:40 -030010013 return false;
10014
Daniel Vettereccb1402013-05-22 00:50:22 +020010015 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010016 if (!(tmp & PIPECONF_ENABLE))
10017 return false;
10018
Daniel Vetter26804af2014-06-25 22:01:55 +030010019 haswell_get_ddi_port_state(crtc, pipe_config);
Daniel Vetter627eb5a2013-04-29 19:33:42 +020010020
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020010021 intel_get_pipe_timings(crtc, pipe_config);
10022
Chandra Kondurua1b22782015-04-07 15:28:45 -070010023 if (INTEL_INFO(dev)->gen >= 9) {
10024 skl_init_scalers(dev, crtc, pipe_config);
10025 }
10026
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020010027 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Chandra Konduruaf99ced2015-05-11 14:35:47 -070010028
10029 if (INTEL_INFO(dev)->gen >= 9) {
10030 pipe_config->scaler_state.scaler_id = -1;
10031 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10032 }
10033
Jesse Barnesbd2e2442014-11-13 17:51:47 +000010034 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
Rodrigo Vivi1c132b42015-09-02 15:19:26 -070010035 if (INTEL_INFO(dev)->gen >= 9)
Jesse Barnesbd2e2442014-11-13 17:51:47 +000010036 skylake_get_pfit_config(crtc, pipe_config);
Jesse Barnesff6d9f52015-01-21 17:19:54 -080010037 else
Rodrigo Vivi1c132b42015-09-02 15:19:26 -070010038 ironlake_get_pfit_config(crtc, pipe_config);
Jesse Barnesbd2e2442014-11-13 17:51:47 +000010039 }
Daniel Vetter88adfff2013-03-28 10:42:01 +010010040
Jesse Barnese59150d2014-01-07 13:30:45 -080010041 if (IS_HASWELL(dev))
10042 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10043 (I915_READ(IPS_CTL) & IPS_ENABLE);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030010044
Clint Taylorebb69c92014-09-30 10:30:22 -070010045 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10046 pipe_config->pixel_multiplier =
10047 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10048 } else {
10049 pipe_config->pixel_multiplier = 1;
10050 }
Daniel Vetter6c49f242013-06-06 12:45:25 +020010051
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010052 return true;
10053}
10054
Ville Syrjälä663f3122015-12-14 13:16:48 +020010055static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
Chris Wilson560b85b2010-08-07 11:01:38 +010010056{
10057 struct drm_device *dev = crtc->dev;
10058 struct drm_i915_private *dev_priv = dev->dev_private;
10059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ville Syrjälädc41c152014-08-13 11:57:05 +030010060 uint32_t cntl = 0, size = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +010010061
Ville Syrjälä663f3122015-12-14 13:16:48 +020010062 if (on) {
Matt Roper3dd512f2015-02-27 10:12:00 -080010063 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10064 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
Ville Syrjälädc41c152014-08-13 11:57:05 +030010065 unsigned int stride = roundup_pow_of_two(width) * 4;
10066
10067 switch (stride) {
10068 default:
10069 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10070 width, stride);
10071 stride = 256;
10072 /* fallthrough */
10073 case 256:
10074 case 512:
10075 case 1024:
10076 case 2048:
10077 break;
Chris Wilson4b0e3332014-05-30 16:35:26 +030010078 }
10079
Ville Syrjälädc41c152014-08-13 11:57:05 +030010080 cntl |= CURSOR_ENABLE |
10081 CURSOR_GAMMA_ENABLE |
10082 CURSOR_FORMAT_ARGB |
10083 CURSOR_STRIDE(stride);
10084
10085 size = (height << 12) | width;
Chris Wilson4b0e3332014-05-30 16:35:26 +030010086 }
Chris Wilson560b85b2010-08-07 11:01:38 +010010087
Ville Syrjälädc41c152014-08-13 11:57:05 +030010088 if (intel_crtc->cursor_cntl != 0 &&
10089 (intel_crtc->cursor_base != base ||
10090 intel_crtc->cursor_size != size ||
10091 intel_crtc->cursor_cntl != cntl)) {
10092 /* On these chipsets we can only modify the base/size/stride
10093 * whilst the cursor is disabled.
10094 */
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010095 I915_WRITE(CURCNTR(PIPE_A), 0);
10096 POSTING_READ(CURCNTR(PIPE_A));
Ville Syrjälädc41c152014-08-13 11:57:05 +030010097 intel_crtc->cursor_cntl = 0;
10098 }
10099
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010100 if (intel_crtc->cursor_base != base) {
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010101 I915_WRITE(CURBASE(PIPE_A), base);
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010102 intel_crtc->cursor_base = base;
10103 }
Ville Syrjälädc41c152014-08-13 11:57:05 +030010104
10105 if (intel_crtc->cursor_size != size) {
10106 I915_WRITE(CURSIZE, size);
10107 intel_crtc->cursor_size = size;
10108 }
10109
Chris Wilson4b0e3332014-05-30 16:35:26 +030010110 if (intel_crtc->cursor_cntl != cntl) {
Ville Syrjälä0b87c242015-09-22 19:47:51 +030010111 I915_WRITE(CURCNTR(PIPE_A), cntl);
10112 POSTING_READ(CURCNTR(PIPE_A));
Chris Wilson4b0e3332014-05-30 16:35:26 +030010113 intel_crtc->cursor_cntl = cntl;
10114 }
Chris Wilson560b85b2010-08-07 11:01:38 +010010115}
10116
Ville Syrjälä663f3122015-12-14 13:16:48 +020010117static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
Chris Wilson560b85b2010-08-07 11:01:38 +010010118{
10119 struct drm_device *dev = crtc->dev;
10120 struct drm_i915_private *dev_priv = dev->dev_private;
10121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10122 int pipe = intel_crtc->pipe;
Ville Syrjälä663f3122015-12-14 13:16:48 +020010123 uint32_t cntl = 0;
Chris Wilson560b85b2010-08-07 11:01:38 +010010124
Ville Syrjälä663f3122015-12-14 13:16:48 +020010125 if (on) {
Chris Wilson4b0e3332014-05-30 16:35:26 +030010126 cntl = MCURSOR_GAMMA_ENABLE;
Matt Roper3dd512f2015-02-27 10:12:00 -080010127 switch (intel_crtc->base.cursor->state->crtc_w) {
Sagar Kamble4726e0b2014-03-10 17:06:23 +053010128 case 64:
10129 cntl |= CURSOR_MODE_64_ARGB_AX;
10130 break;
10131 case 128:
10132 cntl |= CURSOR_MODE_128_ARGB_AX;
10133 break;
10134 case 256:
10135 cntl |= CURSOR_MODE_256_ARGB_AX;
10136 break;
10137 default:
Matt Roper3dd512f2015-02-27 10:12:00 -080010138 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
Sagar Kamble4726e0b2014-03-10 17:06:23 +053010139 return;
Chris Wilson560b85b2010-08-07 11:01:38 +010010140 }
Chris Wilson4b0e3332014-05-30 16:35:26 +030010141 cntl |= pipe << 28; /* Connect to correct pipe */
Ville Syrjälä47bf17a2014-09-12 20:53:33 +030010142
Bob Paauwefc6f93b2015-08-31 14:03:30 -070010143 if (HAS_DDI(dev))
Ville Syrjälä47bf17a2014-09-12 20:53:33 +030010144 cntl |= CURSOR_PIPE_CSC_ENABLE;
Chris Wilson560b85b2010-08-07 11:01:38 +010010145 }
Chris Wilson4b0e3332014-05-30 16:35:26 +030010146
Matt Roper8e7d6882015-01-21 16:35:41 -080010147 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
Ville Syrjälä4398ad42014-10-23 07:41:34 -070010148 cntl |= CURSOR_ROTATE_180;
10149
Chris Wilson4b0e3332014-05-30 16:35:26 +030010150 if (intel_crtc->cursor_cntl != cntl) {
10151 I915_WRITE(CURCNTR(pipe), cntl);
10152 POSTING_READ(CURCNTR(pipe));
10153 intel_crtc->cursor_cntl = cntl;
10154 }
10155
Jesse Barnes65a21cd2011-10-12 11:10:21 -070010156 /* and commit changes on next vblank */
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010157 I915_WRITE(CURBASE(pipe), base);
10158 POSTING_READ(CURBASE(pipe));
Ville Syrjälä99d1f382014-09-12 20:53:32 +030010159
10160 intel_crtc->cursor_base = base;
Jesse Barnes65a21cd2011-10-12 11:10:21 -070010161}
10162
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010163/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +010010164static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10165 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010166{
10167 struct drm_device *dev = crtc->dev;
10168 struct drm_i915_private *dev_priv = dev->dev_private;
10169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10170 int pipe = intel_crtc->pipe;
Maarten Lankhorst9b4101b2015-09-10 16:07:59 +020010171 struct drm_plane_state *cursor_state = crtc->cursor->state;
10172 int x = cursor_state->crtc_x;
10173 int y = cursor_state->crtc_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +030010174 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010175
Ville Syrjälä663f3122015-12-14 13:16:48 +020010176 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010177
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020010178 if (x >= intel_crtc->config->pipe_src_w)
Ville Syrjälä663f3122015-12-14 13:16:48 +020010179 on = false;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +030010180
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020010181 if (y >= intel_crtc->config->pipe_src_h)
Ville Syrjälä663f3122015-12-14 13:16:48 +020010182 on = false;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010183
10184 if (x < 0) {
Maarten Lankhorst9b4101b2015-09-10 16:07:59 +020010185 if (x + cursor_state->crtc_w <= 0)
Ville Syrjälä663f3122015-12-14 13:16:48 +020010186 on = false;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010187
10188 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10189 x = -x;
10190 }
10191 pos |= x << CURSOR_X_SHIFT;
10192
10193 if (y < 0) {
Maarten Lankhorst9b4101b2015-09-10 16:07:59 +020010194 if (y + cursor_state->crtc_h <= 0)
Ville Syrjälä663f3122015-12-14 13:16:48 +020010195 on = false;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010196
10197 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10198 y = -y;
10199 }
10200 pos |= y << CURSOR_Y_SHIFT;
10201
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010202 I915_WRITE(CURPOS(pipe), pos);
10203
Ville Syrjälä4398ad42014-10-23 07:41:34 -070010204 /* ILK+ do this automagically */
10205 if (HAS_GMCH_DISPLAY(dev) &&
Matt Roper8e7d6882015-01-21 16:35:41 -080010206 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
Maarten Lankhorst9b4101b2015-09-10 16:07:59 +020010207 base += (cursor_state->crtc_h *
10208 cursor_state->crtc_w - 1) * 4;
Ville Syrjälä4398ad42014-10-23 07:41:34 -070010209 }
10210
Ville Syrjälä8ac54662014-08-12 19:39:54 +030010211 if (IS_845G(dev) || IS_I865G(dev))
Ville Syrjälä663f3122015-12-14 13:16:48 +020010212 i845_update_cursor(crtc, base, on);
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030010213 else
Ville Syrjälä663f3122015-12-14 13:16:48 +020010214 i9xx_update_cursor(crtc, base, on);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010010215}
10216
Ville Syrjälädc41c152014-08-13 11:57:05 +030010217static bool cursor_size_ok(struct drm_device *dev,
10218 uint32_t width, uint32_t height)
10219{
10220 if (width == 0 || height == 0)
10221 return false;
10222
10223 /*
10224 * 845g/865g are special in that they are only limited by
10225 * the width of their cursors, the height is arbitrary up to
10226 * the precision of the register. Everything else requires
10227 * square cursors, limited to a few power-of-two sizes.
10228 */
10229 if (IS_845G(dev) || IS_I865G(dev)) {
10230 if ((width & 63) != 0)
10231 return false;
10232
10233 if (width > (IS_845G(dev) ? 64 : 512))
10234 return false;
10235
10236 if (height > 1023)
10237 return false;
10238 } else {
10239 switch (width | height) {
10240 case 256:
10241 case 128:
10242 if (IS_GEN2(dev))
10243 return false;
10244 case 64:
10245 break;
10246 default:
10247 return false;
10248 }
10249 }
10250
10251 return true;
10252}
10253
Jesse Barnes79e53942008-11-07 14:24:08 -080010254static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +010010255 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -080010256{
James Simmons72034252010-08-03 01:33:19 +010010257 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -080010258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080010259
James Simmons72034252010-08-03 01:33:19 +010010260 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -080010261 intel_crtc->lut_r[i] = red[i] >> 8;
10262 intel_crtc->lut_g[i] = green[i] >> 8;
10263 intel_crtc->lut_b[i] = blue[i] >> 8;
10264 }
10265
10266 intel_crtc_load_lut(crtc);
10267}
10268
Jesse Barnes79e53942008-11-07 14:24:08 -080010269/* VESA 640x480x72Hz mode to set on the pipe */
10270static struct drm_display_mode load_detect_mode = {
10271 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10272 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10273};
10274
Daniel Vettera8bb6812014-02-10 18:00:39 +010010275struct drm_framebuffer *
10276__intel_framebuffer_create(struct drm_device *dev,
10277 struct drm_mode_fb_cmd2 *mode_cmd,
10278 struct drm_i915_gem_object *obj)
Chris Wilsond2dff872011-04-19 08:36:26 +010010279{
10280 struct intel_framebuffer *intel_fb;
10281 int ret;
10282
10283 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010284 if (!intel_fb)
Chris Wilsond2dff872011-04-19 08:36:26 +010010285 return ERR_PTR(-ENOMEM);
Chris Wilsond2dff872011-04-19 08:36:26 +010010286
10287 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010288 if (ret)
10289 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +010010290
10291 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010292
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010293err:
10294 kfree(intel_fb);
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010295 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +010010296}
10297
Daniel Vetterb5ea6422014-03-02 21:18:00 +010010298static struct drm_framebuffer *
Daniel Vettera8bb6812014-02-10 18:00:39 +010010299intel_framebuffer_create(struct drm_device *dev,
10300 struct drm_mode_fb_cmd2 *mode_cmd,
10301 struct drm_i915_gem_object *obj)
10302{
10303 struct drm_framebuffer *fb;
10304 int ret;
10305
10306 ret = i915_mutex_lock_interruptible(dev);
10307 if (ret)
10308 return ERR_PTR(ret);
10309 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10310 mutex_unlock(&dev->struct_mutex);
10311
10312 return fb;
10313}
10314
Chris Wilsond2dff872011-04-19 08:36:26 +010010315static u32
10316intel_framebuffer_pitch_for_width(int width, int bpp)
10317{
10318 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10319 return ALIGN(pitch, 64);
10320}
10321
10322static u32
10323intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10324{
10325 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
Fabian Frederick1267a262014-07-01 20:39:41 +020010326 return PAGE_ALIGN(pitch * mode->vdisplay);
Chris Wilsond2dff872011-04-19 08:36:26 +010010327}
10328
10329static struct drm_framebuffer *
10330intel_framebuffer_create_for_mode(struct drm_device *dev,
10331 struct drm_display_mode *mode,
10332 int depth, int bpp)
10333{
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010334 struct drm_framebuffer *fb;
Chris Wilsond2dff872011-04-19 08:36:26 +010010335 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +000010336 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +010010337
10338 obj = i915_gem_alloc_object(dev,
10339 intel_framebuffer_size_for_mode(mode, bpp));
10340 if (obj == NULL)
10341 return ERR_PTR(-ENOMEM);
10342
10343 mode_cmd.width = mode->hdisplay;
10344 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010345 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10346 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +000010347 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +010010348
Lukas Wunnerdcb13942015-07-04 11:50:58 +020010349 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10350 if (IS_ERR(fb))
10351 drm_gem_object_unreference_unlocked(&obj->base);
10352
10353 return fb;
Chris Wilsond2dff872011-04-19 08:36:26 +010010354}
10355
10356static struct drm_framebuffer *
10357mode_fits_in_fbdev(struct drm_device *dev,
10358 struct drm_display_mode *mode)
10359{
Daniel Vetter06957262015-08-10 13:34:08 +020010360#ifdef CONFIG_DRM_FBDEV_EMULATION
Chris Wilsond2dff872011-04-19 08:36:26 +010010361 struct drm_i915_private *dev_priv = dev->dev_private;
10362 struct drm_i915_gem_object *obj;
10363 struct drm_framebuffer *fb;
10364
Daniel Vetter4c0e5522014-02-14 16:35:54 +010010365 if (!dev_priv->fbdev)
10366 return NULL;
10367
10368 if (!dev_priv->fbdev->fb)
Chris Wilsond2dff872011-04-19 08:36:26 +010010369 return NULL;
10370
Jesse Barnes8bcd4552014-02-07 12:10:38 -080010371 obj = dev_priv->fbdev->fb->obj;
Daniel Vetter4c0e5522014-02-14 16:35:54 +010010372 BUG_ON(!obj);
Chris Wilsond2dff872011-04-19 08:36:26 +010010373
Jesse Barnes8bcd4552014-02-07 12:10:38 -080010374 fb = &dev_priv->fbdev->fb->base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +020010375 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10376 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +010010377 return NULL;
10378
Ville Syrjälä01f2c772011-12-20 00:06:49 +020010379 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +010010380 return NULL;
10381
10382 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +020010383#else
10384 return NULL;
10385#endif
Chris Wilsond2dff872011-04-19 08:36:26 +010010386}
10387
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030010388static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10389 struct drm_crtc *crtc,
10390 struct drm_display_mode *mode,
10391 struct drm_framebuffer *fb,
10392 int x, int y)
10393{
10394 struct drm_plane_state *plane_state;
10395 int hdisplay, vdisplay;
10396 int ret;
10397
10398 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10399 if (IS_ERR(plane_state))
10400 return PTR_ERR(plane_state);
10401
10402 if (mode)
10403 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10404 else
10405 hdisplay = vdisplay = 0;
10406
10407 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10408 if (ret)
10409 return ret;
10410 drm_atomic_set_fb_for_plane(plane_state, fb);
10411 plane_state->crtc_x = 0;
10412 plane_state->crtc_y = 0;
10413 plane_state->crtc_w = hdisplay;
10414 plane_state->crtc_h = vdisplay;
10415 plane_state->src_x = x << 16;
10416 plane_state->src_y = y << 16;
10417 plane_state->src_w = hdisplay << 16;
10418 plane_state->src_h = vdisplay << 16;
10419
10420 return 0;
10421}
10422
Daniel Vetterd2434ab2012-08-12 21:20:10 +020010423bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +010010424 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -050010425 struct intel_load_detect_pipe *old,
10426 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -080010427{
10428 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +020010429 struct intel_encoder *intel_encoder =
10430 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -080010431 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +010010432 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -080010433 struct drm_crtc *crtc = NULL;
10434 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +020010435 struct drm_framebuffer *fb;
Rob Clark51fd3712013-11-19 12:10:12 -050010436 struct drm_mode_config *config = &dev->mode_config;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010437 struct drm_atomic_state *state = NULL;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010438 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010439 struct intel_crtc_state *crtc_state;
Rob Clark51fd3712013-11-19 12:10:12 -050010440 int ret, i = -1;
Jesse Barnes79e53942008-11-07 14:24:08 -080010441
Chris Wilsond2dff872011-04-19 08:36:26 +010010442 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +030010443 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +030010444 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +010010445
Rob Clark51fd3712013-11-19 12:10:12 -050010446retry:
10447 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10448 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010449 goto fail;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020010450
Jesse Barnes79e53942008-11-07 14:24:08 -080010451 /*
10452 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +010010453 *
Jesse Barnes79e53942008-11-07 14:24:08 -080010454 * - if the connector already has an assigned crtc, use it (but make
10455 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +010010456 *
Jesse Barnes79e53942008-11-07 14:24:08 -080010457 * - try to find the first unused crtc that can drive this connector,
10458 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -080010459 */
10460
10461 /* See if we already have a CRTC for this connector */
10462 if (encoder->crtc) {
10463 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +010010464
Rob Clark51fd3712013-11-19 12:10:12 -050010465 ret = drm_modeset_lock(&crtc->mutex, ctx);
10466 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010467 goto fail;
Daniel Vetter4d02e2d2014-11-11 10:12:00 +010010468 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10469 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010470 goto fail;
Daniel Vetter7b240562012-12-12 00:35:33 +010010471
Daniel Vetter24218aa2012-08-12 19:27:11 +020010472 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +010010473 old->load_detect_temp = false;
10474
10475 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +020010476 if (connector->dpms != DRM_MODE_DPMS_ON)
10477 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +010010478
Chris Wilson71731882011-04-19 23:10:58 +010010479 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -080010480 }
10481
10482 /* Find an unused one (if possible) */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010010483 for_each_crtc(dev, possible_crtc) {
Jesse Barnes79e53942008-11-07 14:24:08 -080010484 i++;
10485 if (!(encoder->possible_crtcs & (1 << i)))
10486 continue;
Matt Roper83d65732015-02-25 13:12:16 -080010487 if (possible_crtc->state->enable)
Ville Syrjäläa4592492014-08-11 13:15:36 +030010488 continue;
Ville Syrjäläa4592492014-08-11 13:15:36 +030010489
10490 crtc = possible_crtc;
10491 break;
Jesse Barnes79e53942008-11-07 14:24:08 -080010492 }
10493
10494 /*
10495 * If we didn't find an unused CRTC, don't use any.
10496 */
10497 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +010010498 DRM_DEBUG_KMS("no pipe available for load-detect\n");
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010499 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080010500 }
10501
Rob Clark51fd3712013-11-19 12:10:12 -050010502 ret = drm_modeset_lock(&crtc->mutex, ctx);
10503 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010504 goto fail;
Daniel Vetter4d02e2d2014-11-11 10:12:00 +010010505 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10506 if (ret)
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010507 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080010508
10509 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +020010510 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +010010511 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +010010512 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -080010513
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010514 state = drm_atomic_state_alloc(dev);
10515 if (!state)
10516 return false;
10517
10518 state->acquire_ctx = ctx;
10519
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010520 connector_state = drm_atomic_get_connector_state(state, connector);
10521 if (IS_ERR(connector_state)) {
10522 ret = PTR_ERR(connector_state);
10523 goto fail;
10524 }
10525
10526 connector_state->crtc = crtc;
10527 connector_state->best_encoder = &intel_encoder->base;
10528
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010529 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10530 if (IS_ERR(crtc_state)) {
10531 ret = PTR_ERR(crtc_state);
10532 goto fail;
10533 }
10534
Maarten Lankhorst49d6fa22015-05-11 10:45:15 +020010535 crtc_state->base.active = crtc_state->base.enable = true;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010536
Chris Wilson64927112011-04-20 07:25:26 +010010537 if (!mode)
10538 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -080010539
Chris Wilsond2dff872011-04-19 08:36:26 +010010540 /* We need a framebuffer large enough to accommodate all accesses
10541 * that the plane may generate whilst we perform load detection.
10542 * We can not rely on the fbcon either being present (we get called
10543 * during its initialisation to detect all boot displays, or it may
10544 * not even exist) or that it is large enough to satisfy the
10545 * requested mode.
10546 */
Daniel Vetter94352cf2012-07-05 22:51:56 +020010547 fb = mode_fits_in_fbdev(dev, mode);
10548 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +010010549 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +020010550 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10551 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +010010552 } else
10553 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +020010554 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +010010555 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Ville Syrjälä412b61d2014-01-17 15:59:39 +020010556 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080010557 }
Chris Wilsond2dff872011-04-19 08:36:26 +010010558
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030010559 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10560 if (ret)
10561 goto fail;
10562
Ander Conselvan de Oliveira8c7b5cc2015-04-21 17:13:19 +030010563 drm_mode_copy(&crtc_state->base.mode, mode);
10564
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020010565 if (drm_atomic_commit(state)) {
Chris Wilson64927112011-04-20 07:25:26 +010010566 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +010010567 if (old->release_fb)
10568 old->release_fb->funcs->destroy(old->release_fb);
Ville Syrjälä412b61d2014-01-17 15:59:39 +020010569 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080010570 }
Daniel Vetter9128b042015-03-03 17:31:21 +010010571 crtc->primary->crtc = crtc;
Chris Wilson71731882011-04-19 23:10:58 +010010572
Jesse Barnes79e53942008-11-07 14:24:08 -080010573 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -070010574 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +010010575 return true;
Ville Syrjälä412b61d2014-01-17 15:59:39 +020010576
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020010577fail:
Ander Conselvan de Oliveirae5d958e2015-04-21 17:12:57 +030010578 drm_atomic_state_free(state);
10579 state = NULL;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010580
Rob Clark51fd3712013-11-19 12:10:12 -050010581 if (ret == -EDEADLK) {
10582 drm_modeset_backoff(ctx);
10583 goto retry;
10584 }
10585
Ville Syrjälä412b61d2014-01-17 15:59:39 +020010586 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -080010587}
10588
Daniel Vetterd2434ab2012-08-12 21:20:10 +020010589void intel_release_load_detect_pipe(struct drm_connector *connector,
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +020010590 struct intel_load_detect_pipe *old,
10591 struct drm_modeset_acquire_ctx *ctx)
Jesse Barnes79e53942008-11-07 14:24:08 -080010592{
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010593 struct drm_device *dev = connector->dev;
Daniel Vetterd2434ab2012-08-12 21:20:10 +020010594 struct intel_encoder *intel_encoder =
10595 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +010010596 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +010010597 struct drm_crtc *crtc = encoder->crtc;
Ville Syrjälä412b61d2014-01-17 15:59:39 +020010598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010599 struct drm_atomic_state *state;
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010600 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010601 struct intel_crtc_state *crtc_state;
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030010602 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080010603
Chris Wilsond2dff872011-04-19 08:36:26 +010010604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
Jani Nikulac23cc412014-06-03 14:56:17 +030010605 connector->base.id, connector->name,
Jani Nikula8e329a032014-06-03 14:56:21 +030010606 encoder->base.id, encoder->name);
Chris Wilsond2dff872011-04-19 08:36:26 +010010607
Chris Wilson8261b192011-04-19 23:18:09 +010010608 if (old->load_detect_temp) {
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010609 state = drm_atomic_state_alloc(dev);
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010610 if (!state)
10611 goto fail;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020010612
10613 state->acquire_ctx = ctx;
10614
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010615 connector_state = drm_atomic_get_connector_state(state, connector);
10616 if (IS_ERR(connector_state))
10617 goto fail;
10618
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010619 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10620 if (IS_ERR(crtc_state))
10621 goto fail;
10622
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010623 connector_state->best_encoder = NULL;
10624 connector_state->crtc = NULL;
10625
Maarten Lankhorst49d6fa22015-05-11 10:45:15 +020010626 crtc_state->base.enable = crtc_state->base.active = false;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030010627
Ander Conselvan de Oliveirad3a40d12015-04-21 17:13:09 +030010628 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10629 0, 0);
10630 if (ret)
10631 goto fail;
10632
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020010633 ret = drm_atomic_commit(state);
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030010634 if (ret)
10635 goto fail;
Chris Wilsond2dff872011-04-19 08:36:26 +010010636
Daniel Vetter36206362012-12-10 20:42:17 +010010637 if (old->release_fb) {
10638 drm_framebuffer_unregister_private(old->release_fb);
10639 drm_framebuffer_unreference(old->release_fb);
10640 }
Chris Wilsond2dff872011-04-19 08:36:26 +010010641
Chris Wilson0622a532011-04-21 09:32:11 +010010642 return;
Jesse Barnes79e53942008-11-07 14:24:08 -080010643 }
10644
Eric Anholtc751ce42010-03-25 11:48:48 -070010645 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +020010646 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10647 connector->funcs->dpms(connector, old->dpms_mode);
Ander Conselvan de Oliveira944b0c72015-03-20 16:18:07 +020010648
10649 return;
10650fail:
10651 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10652 drm_atomic_state_free(state);
Jesse Barnes79e53942008-11-07 14:24:08 -080010653}
10654
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010655static int i9xx_pll_refclk(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010656 const struct intel_crtc_state *pipe_config)
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010657{
10658 struct drm_i915_private *dev_priv = dev->dev_private;
10659 u32 dpll = pipe_config->dpll_hw_state.dpll;
10660
10661 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +020010662 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010663 else if (HAS_PCH_SPLIT(dev))
10664 return 120000;
10665 else if (!IS_GEN2(dev))
10666 return 96000;
10667 else
10668 return 48000;
10669}
10670
Jesse Barnes79e53942008-11-07 14:24:08 -080010671/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010672static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010673 struct intel_crtc_state *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -080010674{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010675 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080010676 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010677 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +030010678 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -080010679 u32 fp;
10680 intel_clock_t clock;
Imre Deakdccbea32015-06-22 23:35:51 +030010681 int port_clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010682 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -080010683
10684 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +030010685 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010686 else
Ville Syrjälä293623f2013-09-13 16:18:46 +030010687 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -080010688
10689 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -050010690 if (IS_PINEVIEW(dev)) {
10691 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10692 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +080010693 } else {
10694 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10695 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10696 }
10697
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010698 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -050010699 if (IS_PINEVIEW(dev))
10700 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10701 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +080010702 else
10703 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -080010704 DPLL_FPA01_P1_POST_DIV_SHIFT);
10705
10706 switch (dpll & DPLL_MODE_MASK) {
10707 case DPLLB_MODE_DAC_SERIAL:
10708 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10709 5 : 10;
10710 break;
10711 case DPLLB_MODE_LVDS:
10712 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10713 7 : 14;
10714 break;
10715 default:
Zhao Yakui28c97732009-10-09 11:39:41 +080010716 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -080010717 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010718 return;
Jesse Barnes79e53942008-11-07 14:24:08 -080010719 }
10720
Daniel Vetterac58c3f2013-06-01 17:16:17 +020010721 if (IS_PINEVIEW(dev))
Imre Deakdccbea32015-06-22 23:35:51 +030010722 port_clock = pnv_calc_dpll_params(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +020010723 else
Imre Deakdccbea32015-06-22 23:35:51 +030010724 port_clock = i9xx_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080010725 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +020010726 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020010727 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -080010728
10729 if (is_lvds) {
10730 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10731 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +020010732
10733 if (lvds & LVDS_CLKB_POWER_UP)
10734 clock.p2 = 7;
10735 else
10736 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -080010737 } else {
10738 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10739 clock.p1 = 2;
10740 else {
10741 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10742 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10743 }
10744 if (dpll & PLL_P2_DIVIDE_BY_4)
10745 clock.p2 = 4;
10746 else
10747 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -080010748 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +030010749
Imre Deakdccbea32015-06-22 23:35:51 +030010750 port_clock = i9xx_calc_dpll_params(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080010751 }
10752
Ville Syrjälä18442d02013-09-13 16:00:08 +030010753 /*
10754 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +010010755 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +030010756 * encoder's get_config() function.
10757 */
Imre Deakdccbea32015-06-22 23:35:51 +030010758 pipe_config->port_clock = port_clock;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010759}
10760
Ville Syrjälä6878da02013-09-13 15:59:11 +030010761int intel_dotclock_calculate(int link_freq,
10762 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010763{
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010764 /*
10765 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010766 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010767 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010768 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010769 *
10770 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +030010771 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -080010772 */
10773
Ville Syrjälä6878da02013-09-13 15:59:11 +030010774 if (!m_n->link_n)
10775 return 0;
10776
10777 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10778}
10779
Ville Syrjälä18442d02013-09-13 16:00:08 +030010780static void ironlake_pch_clock_get(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010781 struct intel_crtc_state *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +030010782{
10783 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +030010784
10785 /* read out port_clock from the DPLL */
10786 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +030010787
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010788 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +030010789 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +010010790 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +030010791 * agree once we know their relationship in the encoder's
10792 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010793 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020010794 pipe_config->base.adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +030010795 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10796 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -080010797}
10798
10799/** Returns the currently programmed mode of the given pipe. */
10800struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10801 struct drm_crtc *crtc)
10802{
Jesse Barnes548f2452011-02-17 10:40:53 -080010803 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020010805 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080010806 struct drm_display_mode *mode;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020010807 struct intel_crtc_state pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -020010808 int htot = I915_READ(HTOTAL(cpu_transcoder));
10809 int hsync = I915_READ(HSYNC(cpu_transcoder));
10810 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10811 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +030010812 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -080010813
10814 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10815 if (!mode)
10816 return NULL;
10817
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010818 /*
10819 * Construct a pipe_config sufficient for getting the clock info
10820 * back out of crtc_clock_get.
10821 *
10822 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10823 * to use a real value here instead.
10824 */
Ville Syrjälä293623f2013-09-13 16:18:46 +030010825 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010826 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +030010827 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10828 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10829 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +030010830 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10831
Ville Syrjälä773ae032013-09-23 17:48:20 +030010832 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -080010833 mode->hdisplay = (htot & 0xffff) + 1;
10834 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10835 mode->hsync_start = (hsync & 0xffff) + 1;
10836 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10837 mode->vdisplay = (vtot & 0xffff) + 1;
10838 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10839 mode->vsync_start = (vsync & 0xffff) + 1;
10840 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10841
10842 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -080010843
10844 return mode;
10845}
10846
Chris Wilsonf047e392012-07-21 12:31:41 +010010847void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -070010848{
Paulo Zanonic67a4702013-08-19 13:18:09 -030010849 struct drm_i915_private *dev_priv = dev->dev_private;
10850
Chris Wilsonf62a0072014-02-21 17:55:39 +000010851 if (dev_priv->mm.busy)
10852 return;
10853
Paulo Zanoni43694d62014-03-07 20:08:08 -030010854 intel_runtime_pm_get(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -030010855 i915_update_gfx_val(dev_priv);
Chris Wilson43cf3bf2015-03-18 09:48:22 +000010856 if (INTEL_INFO(dev)->gen >= 6)
10857 gen6_rps_busy(dev_priv);
Chris Wilsonf62a0072014-02-21 17:55:39 +000010858 dev_priv->mm.busy = true;
Chris Wilsonf047e392012-07-21 12:31:41 +010010859}
10860
10861void intel_mark_idle(struct drm_device *dev)
10862{
Paulo Zanonic67a4702013-08-19 13:18:09 -030010863 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +000010864
Chris Wilsonf62a0072014-02-21 17:55:39 +000010865 if (!dev_priv->mm.busy)
10866 return;
10867
10868 dev_priv->mm.busy = false;
10869
Damien Lespiau3d13ef22014-02-07 19:12:47 +000010870 if (INTEL_INFO(dev)->gen >= 6)
Chris Wilsonb29c19b2013-09-25 17:34:56 +010010871 gen6_rps_idle(dev->dev_private);
Paulo Zanonibb4cdd52014-02-21 13:52:19 -030010872
Paulo Zanoni43694d62014-03-07 20:08:08 -030010873 intel_runtime_pm_put(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +010010874}
10875
Jesse Barnes79e53942008-11-07 14:24:08 -080010876static void intel_crtc_destroy(struct drm_crtc *crtc)
10877{
10878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010879 struct drm_device *dev = crtc->dev;
10880 struct intel_unpin_work *work;
Daniel Vetter67e77c52010-08-20 22:26:30 +020010881
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010882 spin_lock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010883 work = intel_crtc->unpin_work;
10884 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020010885 spin_unlock_irq(&dev->event_lock);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010886
10887 if (work) {
10888 cancel_work_sync(&work->work);
10889 kfree(work);
10890 }
Jesse Barnes79e53942008-11-07 14:24:08 -080010891
10892 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +020010893
Jesse Barnes79e53942008-11-07 14:24:08 -080010894 kfree(intel_crtc);
10895}
10896
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010897static void intel_unpin_work_fn(struct work_struct *__work)
10898{
10899 struct intel_unpin_work *work =
10900 container_of(__work, struct intel_unpin_work, work);
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030010901 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10902 struct drm_device *dev = crtc->base.dev;
10903 struct drm_plane *primary = crtc->base.primary;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010904
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010905 mutex_lock(&dev->struct_mutex);
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030010906 intel_unpin_fb_obj(work->old_fb, primary->state);
Chris Wilson05394f32010-11-08 19:18:58 +000010907 drm_gem_object_unreference(&work->pending_flip_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +000010908
John Harrisonf06cc1b2014-11-24 18:49:37 +000010909 if (work->flip_queued_req)
John Harrison146d84f2014-12-05 13:49:33 +000010910 i915_gem_request_assign(&work->flip_queued_req, NULL);
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010911 mutex_unlock(&dev->struct_mutex);
10912
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030010913 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
Chris Wilson89ed88b2015-02-16 14:31:49 +000010914 drm_framebuffer_unreference(work->old_fb);
Daniel Vetterf99d7062014-06-19 16:01:59 +020010915
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030010916 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10917 atomic_dec(&crtc->unpin_work_count);
Chris Wilsonb4a98e52012-11-01 09:26:26 +000010918
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010919 kfree(work);
10920}
10921
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010922static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +010010923 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010924{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10926 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010927 unsigned long flags;
10928
10929 /* Ignore early vblank irqs */
10930 if (intel_crtc == NULL)
10931 return;
10932
Daniel Vetterf3260382014-09-15 14:55:23 +020010933 /*
10934 * This is called both by irq handlers and the reset code (to complete
10935 * lost pageflips) so needs the full irqsave spinlocks.
10936 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010937 spin_lock_irqsave(&dev->event_lock, flags);
10938 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +000010939
10940 /* Ensure we don't miss a work->pending update ... */
10941 smp_rmb();
10942
10943 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010944 spin_unlock_irqrestore(&dev->event_lock, flags);
10945 return;
10946 }
10947
Chris Wilsond6bbafa2014-09-05 07:13:24 +010010948 page_flip_completed(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +010010949
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010950 spin_unlock_irqrestore(&dev->event_lock, flags);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050010951}
10952
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010953void intel_finish_page_flip(struct drm_device *dev, int pipe)
10954{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010955 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010956 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10957
Mario Kleiner49b14a52010-12-09 07:00:07 +010010958 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010959}
10960
10961void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10962{
Jani Nikulafbee40d2014-03-31 14:27:18 +030010963 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010964 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10965
Mario Kleiner49b14a52010-12-09 07:00:07 +010010966 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -070010967}
10968
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010969/* Is 'a' after or equal to 'b'? */
10970static bool g4x_flip_count_after_eq(u32 a, u32 b)
10971{
10972 return !((a - b) & 0x80000000);
10973}
10974
10975static bool page_flip_finished(struct intel_crtc *crtc)
10976{
10977 struct drm_device *dev = crtc->base.dev;
10978 struct drm_i915_private *dev_priv = dev->dev_private;
10979
Ville Syrjäläbdfa7542014-05-27 21:33:09 +030010980 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10981 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10982 return true;
10983
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030010984 /*
10985 * The relevant registers doen't exist on pre-ctg.
10986 * As the flip done interrupt doesn't trigger for mmio
10987 * flips on gmch platforms, a flip count check isn't
10988 * really needed there. But since ctg has the registers,
10989 * include it in the check anyway.
10990 */
10991 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10992 return true;
10993
10994 /*
10995 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10996 * used the same base address. In that case the mmio flip might
10997 * have completed, but the CS hasn't even executed the flip yet.
10998 *
10999 * A flip count check isn't enough as the CS might have updated
11000 * the base address just after start of vblank, but before we
11001 * managed to process the interrupt. This means we'd complete the
11002 * CS flip too soon.
11003 *
11004 * Combining both checks should get us a good enough result. It may
11005 * still happen that the CS flip has been executed, but has not
11006 * yet actually completed. But in case the base address is the same
11007 * anyway, we don't really care.
11008 */
11009 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11010 crtc->unpin_work->gtt_offset &&
Ville Syrjäläfd8f5072015-09-18 20:03:42 +030011011 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011012 crtc->unpin_work->flip_count);
11013}
11014
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011015void intel_prepare_page_flip(struct drm_device *dev, int plane)
11016{
Jani Nikulafbee40d2014-03-31 14:27:18 +030011017 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011018 struct intel_crtc *intel_crtc =
11019 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11020 unsigned long flags;
11021
Daniel Vetterf3260382014-09-15 14:55:23 +020011022
11023 /*
11024 * This is called both by irq handlers and the reset code (to complete
11025 * lost pageflips) so needs the full irqsave spinlocks.
11026 *
11027 * NB: An MMIO update of the plane base pointer will also
Chris Wilsone7d841c2012-12-03 11:36:30 +000011028 * generate a page-flip completion irq, i.e. every modeset
11029 * is also accompanied by a spurious intel_prepare_page_flip().
11030 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011031 spin_lock_irqsave(&dev->event_lock, flags);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011032 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
Chris Wilsone7d841c2012-12-03 11:36:30 +000011033 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011034 spin_unlock_irqrestore(&dev->event_lock, flags);
11035}
11036
Chris Wilson60426392015-10-10 10:44:32 +010011037static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
Chris Wilsone7d841c2012-12-03 11:36:30 +000011038{
11039 /* Ensure that the work item is consistent when activating it ... */
11040 smp_wmb();
Chris Wilson60426392015-10-10 10:44:32 +010011041 atomic_set(&work->pending, INTEL_FLIP_PENDING);
Chris Wilsone7d841c2012-12-03 11:36:30 +000011042 /* and that it is marked active as soon as the irq could fire. */
11043 smp_wmb();
11044}
11045
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011046static int intel_gen2_queue_flip(struct drm_device *dev,
11047 struct drm_crtc *crtc,
11048 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011049 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011050 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011051 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011052{
John Harrison6258fbe2015-05-29 17:43:48 +010011053 struct intel_engine_cs *ring = req->ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011055 u32 flip_mask;
11056 int ret;
11057
John Harrison5fb9de12015-05-29 17:44:07 +010011058 ret = intel_ring_begin(req, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011059 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011060 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011061
11062 /* Can't queue multiple flips, so wait for the previous
11063 * one to finish before executing the next.
11064 */
11065 if (intel_crtc->plane)
11066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11067 else
11068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +020011069 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11070 intel_ring_emit(ring, MI_NOOP);
11071 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11073 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011074 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +020011075 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +000011076
Chris Wilson60426392015-10-10 10:44:32 +010011077 intel_mark_page_flip_active(intel_crtc->unpin_work);
Chris Wilson83d40922012-04-17 19:35:53 +010011078 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011079}
11080
11081static int intel_gen3_queue_flip(struct drm_device *dev,
11082 struct drm_crtc *crtc,
11083 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011084 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011085 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011086 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011087{
John Harrison6258fbe2015-05-29 17:43:48 +010011088 struct intel_engine_cs *ring = req->ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011090 u32 flip_mask;
11091 int ret;
11092
John Harrison5fb9de12015-05-29 17:44:07 +010011093 ret = intel_ring_begin(req, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011094 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011095 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011096
11097 if (intel_crtc->plane)
11098 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11099 else
11100 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +020011101 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11102 intel_ring_emit(ring, MI_NOOP);
11103 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11104 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11105 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011106 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +020011107 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011108
Chris Wilson60426392015-10-10 10:44:32 +010011109 intel_mark_page_flip_active(intel_crtc->unpin_work);
Chris Wilson83d40922012-04-17 19:35:53 +010011110 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011111}
11112
11113static int intel_gen4_queue_flip(struct drm_device *dev,
11114 struct drm_crtc *crtc,
11115 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011116 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011117 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011118 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011119{
John Harrison6258fbe2015-05-29 17:43:48 +010011120 struct intel_engine_cs *ring = req->ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011121 struct drm_i915_private *dev_priv = dev->dev_private;
11122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11123 uint32_t pf, pipesrc;
11124 int ret;
11125
John Harrison5fb9de12015-05-29 17:44:07 +010011126 ret = intel_ring_begin(req, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011127 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011128 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011129
11130 /* i965+ uses the linear or tiled offsets from the
11131 * Display Registers (which do not change across a page-flip)
11132 * so we need only reprogram the base address.
11133 */
Daniel Vetter6d90c952012-04-26 23:28:05 +020011134 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11135 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11136 intel_ring_emit(ring, fb->pitches[0]);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011137 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
Daniel Vetterc2c75132012-07-05 12:17:30 +020011138 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011139
11140 /* XXX Enabling the panel-fitter across page-flip is so far
11141 * untested on non-native modes, so ignore it for now.
11142 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11143 */
11144 pf = 0;
11145 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +020011146 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +000011147
Chris Wilson60426392015-10-10 10:44:32 +010011148 intel_mark_page_flip_active(intel_crtc->unpin_work);
Chris Wilson83d40922012-04-17 19:35:53 +010011149 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011150}
11151
11152static int intel_gen6_queue_flip(struct drm_device *dev,
11153 struct drm_crtc *crtc,
11154 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011155 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011156 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011157 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011158{
John Harrison6258fbe2015-05-29 17:43:48 +010011159 struct intel_engine_cs *ring = req->ring;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011160 struct drm_i915_private *dev_priv = dev->dev_private;
11161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11162 uint32_t pf, pipesrc;
11163 int ret;
11164
John Harrison5fb9de12015-05-29 17:44:07 +010011165 ret = intel_ring_begin(req, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011166 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011167 return ret;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011168
Daniel Vetter6d90c952012-04-26 23:28:05 +020011169 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11170 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11171 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011172 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011173
Chris Wilson99d9acd2012-04-17 20:37:00 +010011174 /* Contrary to the suggestions in the documentation,
11175 * "Enable Panel Fitter" does not seem to be required when page
11176 * flipping with a non-native mode, and worse causes a normal
11177 * modeset to fail.
11178 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11179 */
11180 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011181 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +020011182 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +000011183
Chris Wilson60426392015-10-10 10:44:32 +010011184 intel_mark_page_flip_active(intel_crtc->unpin_work);
Chris Wilson83d40922012-04-17 19:35:53 +010011185 return 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011186}
11187
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011188static int intel_gen7_queue_flip(struct drm_device *dev,
11189 struct drm_crtc *crtc,
11190 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011191 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011192 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011193 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011194{
John Harrison6258fbe2015-05-29 17:43:48 +010011195 struct intel_engine_cs *ring = req->ring;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettercb05d8d2012-05-23 14:02:00 +020011197 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +010011198 int len, ret;
11199
Robin Schroereba905b2014-05-18 02:24:50 +020011200 switch (intel_crtc->plane) {
Daniel Vettercb05d8d2012-05-23 14:02:00 +020011201 case PLANE_A:
11202 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11203 break;
11204 case PLANE_B:
11205 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11206 break;
11207 case PLANE_C:
11208 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11209 break;
11210 default:
11211 WARN_ONCE(1, "unknown plane in flip command\n");
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011212 return -ENODEV;
Daniel Vettercb05d8d2012-05-23 14:02:00 +020011213 }
11214
Chris Wilsonffe74d72013-08-26 20:58:12 +010011215 len = 4;
Damien Lespiauf4768282014-04-07 20:24:34 +010011216 if (ring->id == RCS) {
Chris Wilsonffe74d72013-08-26 20:58:12 +010011217 len += 6;
Damien Lespiauf4768282014-04-07 20:24:34 +010011218 /*
11219 * On Gen 8, SRM is now taking an extra dword to accommodate
11220 * 48bits addresses, and we need a NOOP for the batch size to
11221 * stay even.
11222 */
11223 if (IS_GEN8(dev))
11224 len += 2;
11225 }
Chris Wilsonffe74d72013-08-26 20:58:12 +010011226
Ville Syrjäläf66fab82014-02-11 19:52:06 +020011227 /*
11228 * BSpec MI_DISPLAY_FLIP for IVB:
11229 * "The full packet must be contained within the same cache line."
11230 *
11231 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11232 * cacheline, if we ever start emitting more commands before
11233 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11234 * then do the cacheline alignment, and finally emit the
11235 * MI_DISPLAY_FLIP.
11236 */
John Harrisonbba09b12015-05-29 17:44:06 +010011237 ret = intel_ring_cacheline_align(req);
Ville Syrjäläf66fab82014-02-11 19:52:06 +020011238 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011239 return ret;
Ville Syrjäläf66fab82014-02-11 19:52:06 +020011240
John Harrison5fb9de12015-05-29 17:44:07 +010011241 ret = intel_ring_begin(req, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011242 if (ret)
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011243 return ret;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011244
Chris Wilsonffe74d72013-08-26 20:58:12 +010011245 /* Unmask the flip-done completion message. Note that the bspec says that
11246 * we should do this for both the BCS and RCS, and that we must not unmask
11247 * more than one flip event at any time (or ensure that one flip message
11248 * can be sent by waiting for flip-done prior to queueing new flips).
11249 * Experimentation says that BCS works despite DERRMR masking all
11250 * flip-done completion events and that unmasking all planes at once
11251 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11252 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11253 */
11254 if (ring->id == RCS) {
11255 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
Ville Syrjäläf92a9162015-11-04 23:20:07 +020011256 intel_ring_emit_reg(ring, DERRMR);
Chris Wilsonffe74d72013-08-26 20:58:12 +010011257 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11258 DERRMR_PIPEB_PRI_FLIP_DONE |
11259 DERRMR_PIPEC_PRI_FLIP_DONE));
Damien Lespiauf4768282014-04-07 20:24:34 +010011260 if (IS_GEN8(dev))
Arun Siluveryf1afe242015-08-04 16:22:20 +010011261 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
Damien Lespiauf4768282014-04-07 20:24:34 +010011262 MI_SRM_LRM_GLOBAL_GTT);
11263 else
Arun Siluveryf1afe242015-08-04 16:22:20 +010011264 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
Damien Lespiauf4768282014-04-07 20:24:34 +010011265 MI_SRM_LRM_GLOBAL_GTT);
Ville Syrjäläf92a9162015-11-04 23:20:07 +020011266 intel_ring_emit_reg(ring, DERRMR);
Chris Wilsonffe74d72013-08-26 20:58:12 +010011267 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
Damien Lespiauf4768282014-04-07 20:24:34 +010011268 if (IS_GEN8(dev)) {
11269 intel_ring_emit(ring, 0);
11270 intel_ring_emit(ring, MI_NOOP);
11271 }
Chris Wilsonffe74d72013-08-26 20:58:12 +010011272 }
11273
Daniel Vettercb05d8d2012-05-23 14:02:00 +020011274 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +020011275 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011276 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011277 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +000011278
Chris Wilson60426392015-10-10 10:44:32 +010011279 intel_mark_page_flip_active(intel_crtc->unpin_work);
Chris Wilson83d40922012-04-17 19:35:53 +010011280 return 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070011281}
11282
Sourab Gupta84c33a62014-06-02 16:47:17 +053011283static bool use_mmio_flip(struct intel_engine_cs *ring,
11284 struct drm_i915_gem_object *obj)
11285{
11286 /*
11287 * This is not being used for older platforms, because
11288 * non-availability of flip done interrupt forces us to use
11289 * CS flips. Older platforms derive flip done using some clever
11290 * tricks involving the flip_pending status bits and vblank irqs.
11291 * So using MMIO flips there would disrupt this mechanism.
11292 */
11293
Chris Wilson8e09bf82014-07-08 10:40:30 +010011294 if (ring == NULL)
11295 return true;
11296
Sourab Gupta84c33a62014-06-02 16:47:17 +053011297 if (INTEL_INFO(ring->dev)->gen < 5)
11298 return false;
11299
11300 if (i915.use_mmio_flip < 0)
11301 return false;
11302 else if (i915.use_mmio_flip > 0)
11303 return true;
Oscar Mateo14bf9932014-07-24 17:04:34 +010011304 else if (i915.enable_execlists)
11305 return true;
Alex Goinsfd8e0582015-11-25 18:43:38 -080011306 else if (obj->base.dma_buf &&
11307 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11308 false))
11309 return true;
Sourab Gupta84c33a62014-06-02 16:47:17 +053011310 else
Chris Wilsonb4716182015-04-27 13:41:17 +010011311 return ring != i915_gem_request_get_ring(obj->last_write_req);
Sourab Gupta84c33a62014-06-02 16:47:17 +053011312}
11313
Chris Wilson60426392015-10-10 10:44:32 +010011314static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011315 unsigned int rotation,
Chris Wilson60426392015-10-10 10:44:32 +010011316 struct intel_unpin_work *work)
Damien Lespiauff944562014-11-20 14:58:16 +000011317{
11318 struct drm_device *dev = intel_crtc->base.dev;
11319 struct drm_i915_private *dev_priv = dev->dev_private;
11320 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
Damien Lespiauff944562014-11-20 14:58:16 +000011321 const enum pipe pipe = intel_crtc->pipe;
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011322 u32 ctl, stride, tile_height;
Damien Lespiauff944562014-11-20 14:58:16 +000011323
11324 ctl = I915_READ(PLANE_CTL(pipe, 0));
11325 ctl &= ~PLANE_CTL_TILED_MASK;
Tvrtko Ursulin2ebef632015-04-20 16:22:48 +010011326 switch (fb->modifier[0]) {
11327 case DRM_FORMAT_MOD_NONE:
11328 break;
11329 case I915_FORMAT_MOD_X_TILED:
Damien Lespiauff944562014-11-20 14:58:16 +000011330 ctl |= PLANE_CTL_TILED_X;
Tvrtko Ursulin2ebef632015-04-20 16:22:48 +010011331 break;
11332 case I915_FORMAT_MOD_Y_TILED:
11333 ctl |= PLANE_CTL_TILED_Y;
11334 break;
11335 case I915_FORMAT_MOD_Yf_TILED:
11336 ctl |= PLANE_CTL_TILED_YF;
11337 break;
11338 default:
11339 MISSING_CASE(fb->modifier[0]);
11340 }
Damien Lespiauff944562014-11-20 14:58:16 +000011341
11342 /*
11343 * The stride is either expressed as a multiple of 64 bytes chunks for
11344 * linear buffers or in number of tiles for tiled buffers.
11345 */
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011346 if (intel_rotation_90_or_270(rotation)) {
11347 /* stride = Surface height in tiles */
11348 tile_height = intel_tile_height(dev, fb->pixel_format,
11349 fb->modifier[0], 0);
11350 stride = DIV_ROUND_UP(fb->height, tile_height);
11351 } else {
11352 stride = fb->pitches[0] /
11353 intel_fb_stride_alignment(dev, fb->modifier[0],
11354 fb->pixel_format);
11355 }
Damien Lespiauff944562014-11-20 14:58:16 +000011356
11357 /*
11358 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11359 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11360 */
11361 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11362 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11363
Chris Wilson60426392015-10-10 10:44:32 +010011364 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
Damien Lespiauff944562014-11-20 14:58:16 +000011365 POSTING_READ(PLANE_SURF(pipe, 0));
11366}
11367
Chris Wilson60426392015-10-10 10:44:32 +010011368static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11369 struct intel_unpin_work *work)
Sourab Gupta84c33a62014-06-02 16:47:17 +053011370{
11371 struct drm_device *dev = intel_crtc->base.dev;
11372 struct drm_i915_private *dev_priv = dev->dev_private;
11373 struct intel_framebuffer *intel_fb =
11374 to_intel_framebuffer(intel_crtc->base.primary->fb);
11375 struct drm_i915_gem_object *obj = intel_fb->obj;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020011376 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
Sourab Gupta84c33a62014-06-02 16:47:17 +053011377 u32 dspcntr;
Sourab Gupta84c33a62014-06-02 16:47:17 +053011378
Sourab Gupta84c33a62014-06-02 16:47:17 +053011379 dspcntr = I915_READ(reg);
11380
Damien Lespiauc5d97472014-10-25 00:11:11 +010011381 if (obj->tiling_mode != I915_TILING_NONE)
11382 dspcntr |= DISPPLANE_TILED;
11383 else
11384 dspcntr &= ~DISPPLANE_TILED;
11385
Sourab Gupta84c33a62014-06-02 16:47:17 +053011386 I915_WRITE(reg, dspcntr);
11387
Chris Wilson60426392015-10-10 10:44:32 +010011388 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
Sourab Gupta84c33a62014-06-02 16:47:17 +053011389 POSTING_READ(DSPSURF(intel_crtc->plane));
Damien Lespiauff944562014-11-20 14:58:16 +000011390}
11391
11392/*
11393 * XXX: This is the temporary way to update the plane registers until we get
11394 * around to using the usual plane update functions for MMIO flips
11395 */
Chris Wilson60426392015-10-10 10:44:32 +010011396static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
Damien Lespiauff944562014-11-20 14:58:16 +000011397{
Chris Wilson60426392015-10-10 10:44:32 +010011398 struct intel_crtc *crtc = mmio_flip->crtc;
11399 struct intel_unpin_work *work;
Damien Lespiauff944562014-11-20 14:58:16 +000011400
Chris Wilson60426392015-10-10 10:44:32 +010011401 spin_lock_irq(&crtc->base.dev->event_lock);
11402 work = crtc->unpin_work;
11403 spin_unlock_irq(&crtc->base.dev->event_lock);
11404 if (work == NULL)
11405 return;
Damien Lespiauff944562014-11-20 14:58:16 +000011406
Chris Wilson60426392015-10-10 10:44:32 +010011407 intel_mark_page_flip_active(work);
Damien Lespiauff944562014-11-20 14:58:16 +000011408
Chris Wilson60426392015-10-10 10:44:32 +010011409 intel_pipe_update_start(crtc);
11410
11411 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011412 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
Damien Lespiauff944562014-11-20 14:58:16 +000011413 else
11414 /* use_mmio_flip() retricts MMIO flips to ilk+ */
Chris Wilson60426392015-10-10 10:44:32 +010011415 ilk_do_mmio_flip(crtc, work);
Damien Lespiauff944562014-11-20 14:58:16 +000011416
Chris Wilson60426392015-10-10 10:44:32 +010011417 intel_pipe_update_end(crtc);
Sourab Gupta84c33a62014-06-02 16:47:17 +053011418}
11419
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +020011420static void intel_mmio_flip_work_func(struct work_struct *work)
Sourab Gupta84c33a62014-06-02 16:47:17 +053011421{
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011422 struct intel_mmio_flip *mmio_flip =
11423 container_of(work, struct intel_mmio_flip, work);
Alex Goinsfd8e0582015-11-25 18:43:38 -080011424 struct intel_framebuffer *intel_fb =
11425 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11426 struct drm_i915_gem_object *obj = intel_fb->obj;
Sourab Gupta84c33a62014-06-02 16:47:17 +053011427
Chris Wilson60426392015-10-10 10:44:32 +010011428 if (mmio_flip->req) {
Daniel Vettereed29a52015-05-21 14:21:25 +020011429 WARN_ON(__i915_wait_request(mmio_flip->req,
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011430 mmio_flip->crtc->reset_counter,
Chris Wilsonbcafc4e2015-04-27 13:41:21 +010011431 false, NULL,
11432 &mmio_flip->i915->rps.mmioflips));
Chris Wilson60426392015-10-10 10:44:32 +010011433 i915_gem_request_unreference__unlocked(mmio_flip->req);
11434 }
Sourab Gupta84c33a62014-06-02 16:47:17 +053011435
Alex Goinsfd8e0582015-11-25 18:43:38 -080011436 /* For framebuffer backed by dmabuf, wait for fence */
11437 if (obj->base.dma_buf)
11438 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11439 false, false,
11440 MAX_SCHEDULE_TIMEOUT) < 0);
11441
Chris Wilson60426392015-10-10 10:44:32 +010011442 intel_do_mmio_flip(mmio_flip);
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011443 kfree(mmio_flip);
Sourab Gupta84c33a62014-06-02 16:47:17 +053011444}
11445
11446static int intel_queue_mmio_flip(struct drm_device *dev,
11447 struct drm_crtc *crtc,
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011448 struct drm_i915_gem_object *obj)
Sourab Gupta84c33a62014-06-02 16:47:17 +053011449{
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011450 struct intel_mmio_flip *mmio_flip;
Sourab Gupta84c33a62014-06-02 16:47:17 +053011451
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011452 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11453 if (mmio_flip == NULL)
11454 return -ENOMEM;
Sourab Gupta84c33a62014-06-02 16:47:17 +053011455
Chris Wilsonbcafc4e2015-04-27 13:41:21 +010011456 mmio_flip->i915 = to_i915(dev);
Daniel Vettereed29a52015-05-21 14:21:25 +020011457 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011458 mmio_flip->crtc = to_intel_crtc(crtc);
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011459 mmio_flip->rotation = crtc->primary->state->rotation;
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +010011460
11461 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11462 schedule_work(&mmio_flip->work);
Ander Conselvan de Oliveira536f5b52014-11-06 11:03:40 +020011463
Sourab Gupta84c33a62014-06-02 16:47:17 +053011464 return 0;
11465}
11466
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011467static int intel_default_queue_flip(struct drm_device *dev,
11468 struct drm_crtc *crtc,
11469 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011470 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +010011471 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -070011472 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011473{
11474 return -ENODEV;
11475}
11476
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011477static bool __intel_pageflip_stall_check(struct drm_device *dev,
11478 struct drm_crtc *crtc)
11479{
11480 struct drm_i915_private *dev_priv = dev->dev_private;
11481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11482 struct intel_unpin_work *work = intel_crtc->unpin_work;
11483 u32 addr;
11484
11485 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11486 return true;
11487
Chris Wilson908565c2015-08-12 13:08:22 +010011488 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11489 return false;
11490
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011491 if (!work->enable_stall_check)
11492 return false;
11493
11494 if (work->flip_ready_vblank == 0) {
Daniel Vetter3a8a9462014-11-26 14:39:48 +010011495 if (work->flip_queued_req &&
11496 !i915_gem_request_completed(work->flip_queued_req, true))
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011497 return false;
11498
Daniel Vetter1e3feef2015-02-13 21:03:45 +010011499 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011500 }
11501
Daniel Vetter1e3feef2015-02-13 21:03:45 +010011502 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011503 return false;
11504
11505 /* Potential stall - if we see that the flip has happened,
11506 * assume a missed interrupt. */
11507 if (INTEL_INFO(dev)->gen >= 4)
11508 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11509 else
11510 addr = I915_READ(DSPADDR(intel_crtc->plane));
11511
11512 /* There is a potential issue here with a false positive after a flip
11513 * to the same address. We could address this by checking for a
11514 * non-incrementing frame counter.
11515 */
11516 return addr == work->gtt_offset;
11517}
11518
11519void intel_check_page_flip(struct drm_device *dev, int pipe)
11520{
11521 struct drm_i915_private *dev_priv = dev->dev_private;
11522 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson6ad790c2015-04-07 16:20:31 +010011524 struct intel_unpin_work *work;
Daniel Vetterf3260382014-09-15 14:55:23 +020011525
Dave Gordon6c51d462015-03-06 15:34:26 +000011526 WARN_ON(!in_interrupt());
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011527
11528 if (crtc == NULL)
11529 return;
11530
Daniel Vetterf3260382014-09-15 14:55:23 +020011531 spin_lock(&dev->event_lock);
Chris Wilson6ad790c2015-04-07 16:20:31 +010011532 work = intel_crtc->unpin_work;
11533 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011534 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
Chris Wilson6ad790c2015-04-07 16:20:31 +010011535 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011536 page_flip_completed(intel_crtc);
Chris Wilson6ad790c2015-04-07 16:20:31 +010011537 work = NULL;
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011538 }
Chris Wilson6ad790c2015-04-07 16:20:31 +010011539 if (work != NULL &&
11540 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11541 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
Daniel Vetterf3260382014-09-15 14:55:23 +020011542 spin_unlock(&dev->event_lock);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011543}
11544
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011545static int intel_crtc_page_flip(struct drm_crtc *crtc,
11546 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -070011547 struct drm_pending_vblank_event *event,
11548 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011549{
11550 struct drm_device *dev = crtc->dev;
11551 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Roperf4510a22014-04-01 15:22:40 -070011552 struct drm_framebuffer *old_fb = crtc->primary->fb;
Matt Roper2ff8fde2014-07-08 07:50:07 -070011553 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Gustavo Padovan455a6802014-12-01 15:40:11 -080011555 struct drm_plane *primary = crtc->primary;
Daniel Vettera071fa02014-06-18 23:28:09 +020011556 enum pipe pipe = intel_crtc->pipe;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011557 struct intel_unpin_work *work;
Oscar Mateoa4872ba2014-05-22 14:13:33 +010011558 struct intel_engine_cs *ring;
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011559 bool mmio_flip;
John Harrison91af1272015-06-18 13:14:56 +010011560 struct drm_i915_gem_request *request = NULL;
Chris Wilson52e68632010-08-08 10:15:59 +010011561 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011562
Matt Roper2ff8fde2014-07-08 07:50:07 -070011563 /*
11564 * drm_mode_page_flip_ioctl() should already catch this, but double
11565 * check to be safe. In the future we may enable pageflipping from
11566 * a disabled primary plane.
11567 */
11568 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11569 return -EBUSY;
11570
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030011571 /* Can't change pixel format via MI display flips. */
Matt Roperf4510a22014-04-01 15:22:40 -070011572 if (fb->pixel_format != crtc->primary->fb->pixel_format)
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030011573 return -EINVAL;
11574
11575 /*
11576 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11577 * Note that pitch changes could also affect these register.
11578 */
11579 if (INTEL_INFO(dev)->gen > 3 &&
Matt Roperf4510a22014-04-01 15:22:40 -070011580 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11581 fb->pitches[0] != crtc->primary->fb->pitches[0]))
Ville Syrjäläe6a595d2012-05-24 21:08:59 +030011582 return -EINVAL;
11583
Chris Wilsonf900db42014-02-20 09:26:13 +000011584 if (i915_terminally_wedged(&dev_priv->gpu_error))
11585 goto out_hang;
11586
Daniel Vetterb14c5672013-09-19 12:18:32 +020011587 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011588 if (work == NULL)
11589 return -ENOMEM;
11590
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011591 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +000011592 work->crtc = crtc;
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011593 work->old_fb = old_fb;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011594 INIT_WORK(&work->work, intel_unpin_work_fn);
11595
Daniel Vetter87b6b102014-05-15 15:33:46 +020011596 ret = drm_crtc_vblank_get(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -070011597 if (ret)
11598 goto free_work;
11599
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011600 /* We borrow the event spin lock for protecting unpin_work */
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011601 spin_lock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011602 if (intel_crtc->unpin_work) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011603 /* Before declaring the flip queue wedged, check if
11604 * the hardware completed the operation behind our backs.
11605 */
11606 if (__intel_pageflip_stall_check(dev, crtc)) {
11607 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11608 page_flip_completed(intel_crtc);
11609 } else {
11610 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011611 spin_unlock_irq(&dev->event_lock);
Chris Wilson468f0b42010-05-27 13:18:13 +010011612
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011613 drm_crtc_vblank_put(crtc);
11614 kfree(work);
11615 return -EBUSY;
11616 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011617 }
11618 intel_crtc->unpin_work = work;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011619 spin_unlock_irq(&dev->event_lock);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011620
Chris Wilsonb4a98e52012-11-01 09:26:26 +000011621 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11622 flush_workqueue(dev_priv->wq);
11623
Jesse Barnes75dfca82010-02-10 15:09:44 -080011624 /* Reference the objects for the scheduled work. */
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011625 drm_framebuffer_reference(work->old_fb);
Chris Wilson05394f32010-11-08 19:18:58 +000011626 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011627
Matt Roperf4510a22014-04-01 15:22:40 -070011628 crtc->primary->fb = fb;
Matt Roperafd65eb2015-02-03 13:10:04 -080011629 update_state_fb(crtc->primary);
Matt Roper1ed1f962015-01-30 16:22:36 -080011630
Chris Wilsone1f99ce2010-10-27 12:45:26 +010011631 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +010011632
Chris Wilson89ed88b2015-02-16 14:31:49 +000011633 ret = i915_mutex_lock_interruptible(dev);
11634 if (ret)
11635 goto cleanup;
11636
Chris Wilsonb4a98e52012-11-01 09:26:26 +000011637 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +020011638 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +010011639
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011640 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
Ville Syrjäläfd8f5072015-09-18 20:03:42 +030011641 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +030011642
Wayne Boyer666a4532015-12-09 12:29:35 -080011643 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011644 ring = &dev_priv->ring[BCS];
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011645 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
Chris Wilson8e09bf82014-07-08 10:40:30 +010011646 /* vlv: DISPLAY_FLIP fails to change tiling */
11647 ring = NULL;
Chris Wilson48bf5b22014-12-27 09:48:28 +000011648 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Chris Wilson2a92d5b2014-07-08 10:40:29 +010011649 ring = &dev_priv->ring[BCS];
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011650 } else if (INTEL_INFO(dev)->gen >= 7) {
Chris Wilsonb4716182015-04-27 13:41:17 +010011651 ring = i915_gem_request_get_ring(obj->last_write_req);
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011652 if (ring == NULL || ring->id != RCS)
11653 ring = &dev_priv->ring[BCS];
11654 } else {
11655 ring = &dev_priv->ring[RCS];
11656 }
11657
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011658 mmio_flip = use_mmio_flip(ring, obj);
11659
11660 /* When using CS flips, we want to emit semaphores between rings.
11661 * However, when using mmio flips we will create a task to do the
11662 * synchronisation, so all we want here is to pin the framebuffer
11663 * into the display plane and skip any waits.
11664 */
Maarten Lankhorst7580d772015-08-18 13:40:06 +020011665 if (!mmio_flip) {
11666 ret = i915_gem_object_sync(obj, ring, &request);
11667 if (ret)
11668 goto cleanup_pending;
11669 }
11670
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000011671 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
Maarten Lankhorst7580d772015-08-18 13:40:06 +020011672 crtc->primary->state);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011673 if (ret)
11674 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011675
Tvrtko Ursulindedf2782015-09-21 10:45:35 +010011676 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11677 obj, 0);
11678 work->gtt_offset += intel_crtc->dspaddr_offset;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011679
Chris Wilsoncf5d8a42015-04-07 16:20:26 +010011680 if (mmio_flip) {
Tvrtko Ursulin86efe242015-10-20 16:20:21 +010011681 ret = intel_queue_mmio_flip(dev, crtc, obj);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011682 if (ret)
11683 goto cleanup_unpin;
11684
John Harrisonf06cc1b2014-11-24 18:49:37 +000011685 i915_gem_request_assign(&work->flip_queued_req,
11686 obj->last_write_req);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011687 } else {
John Harrison6258fbe2015-05-29 17:43:48 +010011688 if (!request) {
11689 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11690 if (ret)
11691 goto cleanup_unpin;
11692 }
11693
11694 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011695 page_flip_flags);
11696 if (ret)
11697 goto cleanup_unpin;
11698
John Harrison6258fbe2015-05-29 17:43:48 +010011699 i915_gem_request_assign(&work->flip_queued_req, request);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011700 }
11701
John Harrison91af1272015-06-18 13:14:56 +010011702 if (request)
John Harrison75289872015-05-29 17:43:49 +010011703 i915_add_request_no_flush(request);
John Harrison91af1272015-06-18 13:14:56 +010011704
Daniel Vetter1e3feef2015-02-13 21:03:45 +010011705 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
Chris Wilsond6bbafa2014-09-05 07:13:24 +010011706 work->enable_stall_check = true;
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011707
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +000011708 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030011709 to_intel_plane(primary)->frontbuffer_bit);
Paulo Zanonic80ac852015-07-02 19:25:13 -030011710 mutex_unlock(&dev->struct_mutex);
Daniel Vettera071fa02014-06-18 23:28:09 +020011711
Paulo Zanonid029bca2015-10-15 10:44:46 -030011712 intel_fbc_deactivate(intel_crtc);
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030011713 intel_frontbuffer_flip_prepare(dev,
11714 to_intel_plane(primary)->frontbuffer_bit);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011715
Jesse Barnese5510fa2010-07-01 16:48:37 -070011716 trace_i915_flip_request(intel_crtc->plane, obj);
11717
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011718 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +010011719
Ville Syrjälä4fa62c82014-04-15 21:41:38 +030011720cleanup_unpin:
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +000011721 intel_unpin_fb_obj(fb, crtc->primary->state);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070011722cleanup_pending:
John Harrison91af1272015-06-18 13:14:56 +010011723 if (request)
11724 i915_gem_request_cancel(request);
Chris Wilsonb4a98e52012-11-01 09:26:26 +000011725 atomic_dec(&intel_crtc->unpin_work_count);
Chris Wilson89ed88b2015-02-16 14:31:49 +000011726 mutex_unlock(&dev->struct_mutex);
11727cleanup:
Matt Roperf4510a22014-04-01 15:22:40 -070011728 crtc->primary->fb = old_fb;
Matt Roperafd65eb2015-02-03 13:10:04 -080011729 update_state_fb(crtc->primary);
Chris Wilson96b099f2010-06-07 14:03:04 +010011730
Chris Wilson89ed88b2015-02-16 14:31:49 +000011731 drm_gem_object_unreference_unlocked(&obj->base);
11732 drm_framebuffer_unreference(work->old_fb);
11733
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011734 spin_lock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +010011735 intel_crtc->unpin_work = NULL;
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011736 spin_unlock_irq(&dev->event_lock);
Chris Wilson96b099f2010-06-07 14:03:04 +010011737
Daniel Vetter87b6b102014-05-15 15:33:46 +020011738 drm_crtc_vblank_put(crtc);
Jesse Barnes7317c75e62011-08-29 09:45:28 -070011739free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +010011740 kfree(work);
11741
Chris Wilsonf900db42014-02-20 09:26:13 +000011742 if (ret == -EIO) {
Maarten Lankhorst02e0efb2015-06-12 11:15:40 +020011743 struct drm_atomic_state *state;
11744 struct drm_plane_state *plane_state;
11745
Chris Wilsonf900db42014-02-20 09:26:13 +000011746out_hang:
Maarten Lankhorst02e0efb2015-06-12 11:15:40 +020011747 state = drm_atomic_state_alloc(dev);
11748 if (!state)
11749 return -ENOMEM;
11750 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11751
11752retry:
11753 plane_state = drm_atomic_get_plane_state(state, primary);
11754 ret = PTR_ERR_OR_ZERO(plane_state);
11755 if (!ret) {
11756 drm_atomic_set_fb_for_plane(plane_state, fb);
11757
11758 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11759 if (!ret)
11760 ret = drm_atomic_commit(state);
11761 }
11762
11763 if (ret == -EDEADLK) {
11764 drm_modeset_backoff(state->acquire_ctx);
11765 drm_atomic_state_clear(state);
11766 goto retry;
11767 }
11768
11769 if (ret)
11770 drm_atomic_state_free(state);
11771
Chris Wilsonf0d3dad2014-09-07 16:51:12 +010011772 if (ret == 0 && event) {
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011773 spin_lock_irq(&dev->event_lock);
Daniel Vettera071fa02014-06-18 23:28:09 +020011774 drm_send_vblank_event(dev, pipe, event);
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020011775 spin_unlock_irq(&dev->event_lock);
Chris Wilsonf0d3dad2014-09-07 16:51:12 +010011776 }
Chris Wilsonf900db42014-02-20 09:26:13 +000011777 }
Chris Wilson96b099f2010-06-07 14:03:04 +010011778 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -050011779}
11780
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011781
11782/**
11783 * intel_wm_need_update - Check whether watermarks need updating
11784 * @plane: drm plane
11785 * @state: new plane state
11786 *
11787 * Check current plane state versus the new one to determine whether
11788 * watermarks need to be recalculated.
11789 *
11790 * Returns true or false.
11791 */
11792static bool intel_wm_need_update(struct drm_plane *plane,
11793 struct drm_plane_state *state)
11794{
Matt Roperd21fbe82015-09-24 15:53:12 -070011795 struct intel_plane_state *new = to_intel_plane_state(state);
11796 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11797
11798 /* Update watermarks on tiling or size changes. */
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010011799 if (new->visible != cur->visible)
11800 return true;
11801
11802 if (!cur->base.fb || !new->base.fb)
11803 return false;
11804
11805 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11806 cur->base.rotation != new->base.rotation ||
Matt Roperd21fbe82015-09-24 15:53:12 -070011807 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11808 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11809 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11810 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011811 return true;
11812
11813 return false;
11814}
11815
Matt Roperd21fbe82015-09-24 15:53:12 -070011816static bool needs_scaling(struct intel_plane_state *state)
11817{
11818 int src_w = drm_rect_width(&state->src) >> 16;
11819 int src_h = drm_rect_height(&state->src) >> 16;
11820 int dst_w = drm_rect_width(&state->dst);
11821 int dst_h = drm_rect_height(&state->dst);
11822
11823 return (src_w != dst_w || src_h != dst_h);
11824}
11825
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011826int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11827 struct drm_plane_state *plane_state)
11828{
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +010011829 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011830 struct drm_crtc *crtc = crtc_state->crtc;
11831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11832 struct drm_plane *plane = plane_state->plane;
11833 struct drm_device *dev = crtc->dev;
11834 struct drm_i915_private *dev_priv = dev->dev_private;
11835 struct intel_plane_state *old_plane_state =
11836 to_intel_plane_state(plane->state);
11837 int idx = intel_crtc->base.base.id, ret;
11838 int i = drm_plane_index(plane);
11839 bool mode_changed = needs_modeset(crtc_state);
11840 bool was_crtc_enabled = crtc->state->active;
11841 bool is_crtc_enabled = crtc_state->active;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011842 bool turn_off, turn_on, visible, was_visible;
11843 struct drm_framebuffer *fb = plane_state->fb;
11844
11845 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11846 plane->type != DRM_PLANE_TYPE_CURSOR) {
11847 ret = skl_update_scaler_plane(
11848 to_intel_crtc_state(crtc_state),
11849 to_intel_plane_state(plane_state));
11850 if (ret)
11851 return ret;
11852 }
11853
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011854 was_visible = old_plane_state->visible;
11855 visible = to_intel_plane_state(plane_state)->visible;
11856
11857 if (!was_crtc_enabled && WARN_ON(was_visible))
11858 was_visible = false;
11859
11860 if (!is_crtc_enabled && WARN_ON(visible))
11861 visible = false;
11862
11863 if (!was_visible && !visible)
11864 return 0;
11865
11866 turn_off = was_visible && (!visible || mode_changed);
11867 turn_on = visible && (!was_visible || mode_changed);
11868
11869 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11870 plane->base.id, fb ? fb->base.id : -1);
11871
11872 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11873 plane->base.id, was_visible, visible,
11874 turn_off, turn_on, mode_changed);
11875
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010011876 if (turn_on || turn_off) {
11877 pipe_config->wm_changed = true;
11878
Ville Syrjälä852eb002015-06-24 22:00:07 +030011879 /* must disable cxsr around plane enable/disable */
11880 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11881 if (is_crtc_enabled)
11882 intel_crtc->atomic.wait_vblank = true;
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +010011883 pipe_config->disable_cxsr = true;
Ville Syrjälä852eb002015-06-24 22:00:07 +030011884 }
11885 } else if (intel_wm_need_update(plane, plane_state)) {
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010011886 pipe_config->wm_changed = true;
Ville Syrjälä852eb002015-06-24 22:00:07 +030011887 }
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011888
Rodrigo Vivi8be6ca82015-08-24 16:38:23 -070011889 if (visible || was_visible)
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030011890 intel_crtc->atomic.fb_bits |=
11891 to_intel_plane(plane)->frontbuffer_bit;
11892
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011893 switch (plane->type) {
11894 case DRM_PLANE_TYPE_PRIMARY:
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011895 intel_crtc->atomic.pre_disable_primary = turn_off;
11896 intel_crtc->atomic.post_enable_primary = turn_on;
11897
Rodrigo Vivi066cf552015-06-26 13:55:54 -070011898 if (turn_off) {
11899 /*
11900 * FIXME: Actually if we will still have any other
11901 * plane enabled on the pipe we could let IPS enabled
11902 * still, but for now lets consider that when we make
11903 * primary invisible by setting DSPCNTR to 0 on
11904 * update_primary_plane function IPS needs to be
11905 * disable.
11906 */
11907 intel_crtc->atomic.disable_ips = true;
11908
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011909 intel_crtc->atomic.disable_fbc = true;
Rodrigo Vivi066cf552015-06-26 13:55:54 -070011910 }
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011911
11912 /*
11913 * FBC does not work on some platforms for rotated
11914 * planes, so disable it when rotation is not 0 and
11915 * update it when rotation is set back to 0.
11916 *
11917 * FIXME: This is redundant with the fbc update done in
11918 * the primary plane enable function except that that
11919 * one is done too late. We eventually need to unify
11920 * this.
11921 */
11922
11923 if (visible &&
11924 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11925 dev_priv->fbc.crtc == intel_crtc &&
11926 plane_state->rotation != BIT(DRM_ROTATE_0))
11927 intel_crtc->atomic.disable_fbc = true;
11928
11929 /*
11930 * BDW signals flip done immediately if the plane
11931 * is disabled, even if the plane enable is already
11932 * armed to occur at the next vblank :(
11933 */
11934 if (turn_on && IS_BROADWELL(dev))
11935 intel_crtc->atomic.wait_vblank = true;
11936
11937 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11938 break;
11939 case DRM_PLANE_TYPE_CURSOR:
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011940 break;
11941 case DRM_PLANE_TYPE_OVERLAY:
Matt Roperd21fbe82015-09-24 15:53:12 -070011942 /*
11943 * WaCxSRDisabledForSpriteScaling:ivb
11944 *
11945 * cstate->update_wm was already set above, so this flag will
11946 * take effect when we commit and program watermarks.
11947 */
11948 if (IS_IVYBRIDGE(dev) &&
11949 needs_scaling(to_intel_plane_state(plane_state)) &&
11950 !needs_scaling(old_plane_state)) {
11951 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11952 } else if (turn_off && !mode_changed) {
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011953 intel_crtc->atomic.wait_vblank = true;
11954 intel_crtc->atomic.update_sprite_watermarks |=
11955 1 << i;
11956 }
Matt Roperd21fbe82015-09-24 15:53:12 -070011957
11958 break;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020011959 }
11960 return 0;
11961}
11962
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020011963static bool encoders_cloneable(const struct intel_encoder *a,
11964 const struct intel_encoder *b)
11965{
11966 /* masks could be asymmetric, so check both ways */
11967 return a == b || (a->cloneable & (1 << b->type) &&
11968 b->cloneable & (1 << a->type));
11969}
11970
11971static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11972 struct intel_crtc *crtc,
11973 struct intel_encoder *encoder)
11974{
11975 struct intel_encoder *source_encoder;
11976 struct drm_connector *connector;
11977 struct drm_connector_state *connector_state;
11978 int i;
11979
11980 for_each_connector_in_state(state, connector, connector_state, i) {
11981 if (connector_state->crtc != &crtc->base)
11982 continue;
11983
11984 source_encoder =
11985 to_intel_encoder(connector_state->best_encoder);
11986 if (!encoders_cloneable(encoder, source_encoder))
11987 return false;
11988 }
11989
11990 return true;
11991}
11992
11993static bool check_encoder_cloning(struct drm_atomic_state *state,
11994 struct intel_crtc *crtc)
11995{
11996 struct intel_encoder *encoder;
11997 struct drm_connector *connector;
11998 struct drm_connector_state *connector_state;
11999 int i;
12000
12001 for_each_connector_in_state(state, connector, connector_state, i) {
12002 if (connector_state->crtc != &crtc->base)
12003 continue;
12004
12005 encoder = to_intel_encoder(connector_state->best_encoder);
12006 if (!check_single_encoder_cloning(state, crtc, encoder))
12007 return false;
12008 }
12009
12010 return true;
12011}
12012
12013static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12014 struct drm_crtc_state *crtc_state)
12015{
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +020012016 struct drm_device *dev = crtc->dev;
Maarten Lankhorstad421372015-06-15 12:33:42 +020012017 struct drm_i915_private *dev_priv = dev->dev_private;
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstcf5a15b2015-06-15 12:33:41 +020012019 struct intel_crtc_state *pipe_config =
12020 to_intel_crtc_state(crtc_state);
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012021 struct drm_atomic_state *state = crtc_state->state;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012022 int ret;
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012023 bool mode_changed = needs_modeset(crtc_state);
12024
12025 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12026 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12027 return -EINVAL;
12028 }
12029
Ville Syrjälä852eb002015-06-24 22:00:07 +030012030 if (mode_changed && !crtc_state->active)
Maarten Lankhorst92826fc2015-12-03 13:49:13 +010012031 pipe_config->wm_changed = true;
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +020012032
Maarten Lankhorstad421372015-06-15 12:33:42 +020012033 if (mode_changed && crtc_state->enable &&
12034 dev_priv->display.crtc_compute_clock &&
12035 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12036 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12037 pipe_config);
12038 if (ret)
12039 return ret;
12040 }
12041
Maarten Lankhorste435d6e2015-07-13 16:30:15 +020012042 ret = 0;
Matt Roper86c8bbb2015-09-24 15:53:16 -070012043 if (dev_priv->display.compute_pipe_wm) {
12044 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12045 if (ret)
12046 return ret;
12047 }
12048
Maarten Lankhorste435d6e2015-07-13 16:30:15 +020012049 if (INTEL_INFO(dev)->gen >= 9) {
12050 if (mode_changed)
12051 ret = skl_update_scaler_crtc(pipe_config);
12052
12053 if (!ret)
12054 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12055 pipe_config);
12056 }
12057
12058 return ret;
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012059}
12060
Jani Nikula65b38e02015-04-13 11:26:56 +030012061static const struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012062 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12063 .load_lut = intel_crtc_load_lut,
Matt Roperea2c67b2014-12-23 10:41:52 -080012064 .atomic_begin = intel_begin_crtc_commit,
12065 .atomic_flush = intel_finish_crtc_commit,
Maarten Lankhorst6d3a1ce2015-06-15 12:33:40 +020012066 .atomic_check = intel_crtc_atomic_check,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010012067};
12068
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020012069static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12070{
12071 struct intel_connector *connector;
12072
12073 for_each_intel_connector(dev, connector) {
12074 if (connector->base.encoder) {
12075 connector->base.state->best_encoder =
12076 connector->base.encoder;
12077 connector->base.state->crtc =
12078 connector->base.encoder->crtc;
12079 } else {
12080 connector->base.state->best_encoder = NULL;
12081 connector->base.state->crtc = NULL;
12082 }
12083 }
12084}
12085
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012086static void
Robin Schroereba905b2014-05-18 02:24:50 +020012087connected_sink_compute_bpp(struct intel_connector *connector,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012088 struct intel_crtc_state *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012089{
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012090 int bpp = pipe_config->pipe_bpp;
12091
12092 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12093 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030012094 connector->base.name);
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012095
12096 /* Don't use an invalid EDID bpc value */
12097 if (connector->base.display_info.bpc &&
12098 connector->base.display_info.bpc * 3 < bpp) {
12099 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12100 bpp, connector->base.display_info.bpc*3);
12101 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12102 }
12103
12104 /* Clamp bpp to 8 on screens without EDID 1.4 */
12105 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12106 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12107 bpp);
12108 pipe_config->pipe_bpp = 24;
12109 }
12110}
12111
12112static int
12113compute_baseline_pipe_bpp(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012114 struct intel_crtc_state *pipe_config)
Daniel Vetter050f7ae2013-06-02 13:26:23 +020012115{
12116 struct drm_device *dev = crtc->base.dev;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012117 struct drm_atomic_state *state;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012118 struct drm_connector *connector;
12119 struct drm_connector_state *connector_state;
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012120 int bpp, i;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012121
Wayne Boyer666a4532015-12-09 12:29:35 -080012122 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012123 bpp = 10*3;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012124 else if (INTEL_INFO(dev)->gen >= 5)
12125 bpp = 12*3;
12126 else
12127 bpp = 8*3;
12128
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012129
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012130 pipe_config->pipe_bpp = bpp;
12131
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012132 state = pipe_config->base.state;
12133
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012134 /* Clamp display bpp to EDID value */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012135 for_each_connector_in_state(state, connector, connector_state, i) {
12136 if (connector_state->crtc != &crtc->base)
Ander Conselvan de Oliveira14860172015-03-20 16:18:09 +020012137 continue;
12138
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012139 connected_sink_compute_bpp(to_intel_connector(connector),
12140 pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012141 }
12142
12143 return bpp;
12144}
12145
Daniel Vetter644db712013-09-19 14:53:58 +020012146static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12147{
12148 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12149 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +010012150 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +020012151 mode->crtc_hdisplay, mode->crtc_hsync_start,
12152 mode->crtc_hsync_end, mode->crtc_htotal,
12153 mode->crtc_vdisplay, mode->crtc_vsync_start,
12154 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12155}
12156
Daniel Vetterc0b03412013-05-28 12:05:54 +020012157static void intel_dump_pipe_config(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012158 struct intel_crtc_state *pipe_config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020012159 const char *context)
12160{
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012161 struct drm_device *dev = crtc->base.dev;
12162 struct drm_plane *plane;
12163 struct intel_plane *intel_plane;
12164 struct intel_plane_state *state;
12165 struct drm_framebuffer *fb;
12166
12167 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12168 context, pipe_config, pipe_name(crtc->pipe));
Daniel Vetterc0b03412013-05-28 12:05:54 +020012169
12170 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12171 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12172 pipe_config->pipe_bpp, pipe_config->dither);
12173 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12174 pipe_config->has_pch_encoder,
12175 pipe_config->fdi_lanes,
12176 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12177 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12178 pipe_config->fdi_m_n.tu);
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012179 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030012180 pipe_config->has_dp_encoder,
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012181 pipe_config->lane_count,
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030012182 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12183 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12184 pipe_config->dp_m_n.tu);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012185
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012186 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012187 pipe_config->has_dp_encoder,
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012188 pipe_config->lane_count,
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012189 pipe_config->dp_m2_n2.gmch_m,
12190 pipe_config->dp_m2_n2.gmch_n,
12191 pipe_config->dp_m2_n2.link_m,
12192 pipe_config->dp_m2_n2.link_n,
12193 pipe_config->dp_m2_n2.tu);
12194
Daniel Vetter55072d12014-11-20 16:10:28 +010012195 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12196 pipe_config->has_audio,
12197 pipe_config->has_infoframe);
12198
Daniel Vetterc0b03412013-05-28 12:05:54 +020012199 DRM_DEBUG_KMS("requested mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012200 drm_mode_debug_printmodeline(&pipe_config->base.mode);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012201 DRM_DEBUG_KMS("adjusted mode:\n");
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012202 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12203 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +030012204 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +030012205 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12206 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Tvrtko Ursulin0ec463d2015-05-13 16:51:08 +010012207 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12208 crtc->num_scalers,
12209 pipe_config->scaler_state.scaler_users,
12210 pipe_config->scaler_state.scaler_id);
Daniel Vetterc0b03412013-05-28 12:05:54 +020012211 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12212 pipe_config->gmch_pfit.control,
12213 pipe_config->gmch_pfit.pgm_ratios,
12214 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +010012215 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +020012216 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +010012217 pipe_config->pch_pfit.size,
12218 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -030012219 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +030012220 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012221
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012222 if (IS_BROXTON(dev)) {
Imre Deak05712c12015-06-18 17:25:54 +030012223 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012224 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
Imre Deakc8453332015-06-18 17:25:55 +030012225 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012226 pipe_config->ddi_pll_sel,
12227 pipe_config->dpll_hw_state.ebb0,
Imre Deak05712c12015-06-18 17:25:54 +030012228 pipe_config->dpll_hw_state.ebb4,
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012229 pipe_config->dpll_hw_state.pll0,
12230 pipe_config->dpll_hw_state.pll1,
12231 pipe_config->dpll_hw_state.pll2,
12232 pipe_config->dpll_hw_state.pll3,
12233 pipe_config->dpll_hw_state.pll6,
12234 pipe_config->dpll_hw_state.pll8,
Imre Deak05712c12015-06-18 17:25:54 +030012235 pipe_config->dpll_hw_state.pll9,
Imre Deakc8453332015-06-18 17:25:55 +030012236 pipe_config->dpll_hw_state.pll10,
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012237 pipe_config->dpll_hw_state.pcsdw12);
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070012238 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012239 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12240 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12241 pipe_config->ddi_pll_sel,
12242 pipe_config->dpll_hw_state.ctrl1,
12243 pipe_config->dpll_hw_state.cfgcr1,
12244 pipe_config->dpll_hw_state.cfgcr2);
12245 } else if (HAS_DDI(dev)) {
Maarten Lankhorst00490c22015-11-16 14:42:12 +010012246 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012247 pipe_config->ddi_pll_sel,
Maarten Lankhorst00490c22015-11-16 14:42:12 +010012248 pipe_config->dpll_hw_state.wrpll,
12249 pipe_config->dpll_hw_state.spll);
Tvrtko Ursulin415ff0f2015-05-14 13:38:31 +010012250 } else {
12251 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12252 "fp0: 0x%x, fp1: 0x%x\n",
12253 pipe_config->dpll_hw_state.dpll,
12254 pipe_config->dpll_hw_state.dpll_md,
12255 pipe_config->dpll_hw_state.fp0,
12256 pipe_config->dpll_hw_state.fp1);
12257 }
12258
Chandra Konduru6a60cd82015-04-07 15:28:40 -070012259 DRM_DEBUG_KMS("planes on this crtc\n");
12260 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12261 intel_plane = to_intel_plane(plane);
12262 if (intel_plane->pipe != crtc->pipe)
12263 continue;
12264
12265 state = to_intel_plane_state(plane->state);
12266 fb = state->base.fb;
12267 if (!fb) {
12268 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12269 "disabled, scaler_id = %d\n",
12270 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12271 plane->base.id, intel_plane->pipe,
12272 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12273 drm_plane_index(plane), state->scaler_id);
12274 continue;
12275 }
12276
12277 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12278 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12279 plane->base.id, intel_plane->pipe,
12280 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12281 drm_plane_index(plane));
12282 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12283 fb->base.id, fb->width, fb->height, fb->pixel_format);
12284 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12285 state->scaler_id,
12286 state->src.x1 >> 16, state->src.y1 >> 16,
12287 drm_rect_width(&state->src) >> 16,
12288 drm_rect_height(&state->src) >> 16,
12289 state->dst.x1, state->dst.y1,
12290 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12291 }
Daniel Vetterc0b03412013-05-28 12:05:54 +020012292}
12293
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012294static bool check_digital_port_conflicts(struct drm_atomic_state *state)
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012295{
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012296 struct drm_device *dev = state->dev;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012297 struct drm_connector *connector;
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012298 unsigned int used_ports = 0;
12299
12300 /*
12301 * Walk the connector list instead of the encoder
12302 * list to detect the problem on ddi platforms
12303 * where there's just one encoder per digital port.
12304 */
Ville Syrjälä0bff4852015-12-10 18:22:31 +020012305 drm_for_each_connector(connector, dev) {
12306 struct drm_connector_state *connector_state;
12307 struct intel_encoder *encoder;
12308
12309 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12310 if (!connector_state)
12311 connector_state = connector->state;
12312
Ander Conselvan de Oliveira5448a002015-04-02 14:47:59 +030012313 if (!connector_state->best_encoder)
12314 continue;
12315
12316 encoder = to_intel_encoder(connector_state->best_encoder);
12317
12318 WARN_ON(!connector_state->crtc);
Ville Syrjälä00f0b372014-12-02 14:10:46 +020012319
12320 switch (encoder->type) {
12321 unsigned int port_mask;
12322 case INTEL_OUTPUT_UNKNOWN:
12323 if (WARN_ON(!HAS_DDI(dev)))
12324 break;
12325 case INTEL_OUTPUT_DISPLAYPORT:
12326 case INTEL_OUTPUT_HDMI:
12327 case INTEL_OUTPUT_EDP:
12328 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12329
12330 /* the same port mustn't appear more than once */
12331 if (used_ports & port_mask)
12332 return false;
12333
12334 used_ports |= port_mask;
12335 default:
12336 break;
12337 }
12338 }
12339
12340 return true;
12341}
12342
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012343static void
12344clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12345{
12346 struct drm_crtc_state tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070012347 struct intel_crtc_scaler_state scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012348 struct intel_dpll_hw_state dpll_hw_state;
12349 enum intel_dpll_id shared_dpll;
Ander Conselvan de Oliveira8504c742015-05-15 11:51:50 +030012350 uint32_t ddi_pll_sel;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012351 bool force_thru;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012352
Ander Conselvan de Oliveira7546a382015-05-20 09:03:27 +030012353 /* FIXME: before the switch to atomic started, a new pipe_config was
12354 * kzalloc'd. Code that depends on any field being zero should be
12355 * fixed, so that the crtc_state can be safely duplicated. For now,
12356 * only fields that are know to not cause problems are preserved. */
12357
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012358 tmp_state = crtc_state->base;
Chandra Konduru663a3642015-04-07 15:28:41 -070012359 scaler_state = crtc_state->scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012360 shared_dpll = crtc_state->shared_dpll;
12361 dpll_hw_state = crtc_state->dpll_hw_state;
Ander Conselvan de Oliveira8504c742015-05-15 11:51:50 +030012362 ddi_pll_sel = crtc_state->ddi_pll_sel;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012363 force_thru = crtc_state->pch_pfit.force_thru;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012364
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012365 memset(crtc_state, 0, sizeof *crtc_state);
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012366
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012367 crtc_state->base = tmp_state;
Chandra Konduru663a3642015-04-07 15:28:41 -070012368 crtc_state->scaler_state = scaler_state;
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030012369 crtc_state->shared_dpll = shared_dpll;
12370 crtc_state->dpll_hw_state = dpll_hw_state;
Ander Conselvan de Oliveira8504c742015-05-15 11:51:50 +030012371 crtc_state->ddi_pll_sel = ddi_pll_sel;
Maarten Lankhorstc4e2d042015-08-05 12:36:59 +020012372 crtc_state->pch_pfit.force_thru = force_thru;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012373}
12374
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012375static int
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010012376intel_modeset_pipe_config(struct drm_crtc *crtc,
Maarten Lankhorstb3592832015-06-15 12:33:38 +020012377 struct intel_crtc_state *pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +020012378{
Maarten Lankhorstb3592832015-06-15 12:33:38 +020012379 struct drm_atomic_state *state = pipe_config->base.state;
Daniel Vetter7758a112012-07-08 19:40:39 +020012380 struct intel_encoder *encoder;
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012381 struct drm_connector *connector;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012382 struct drm_connector_state *connector_state;
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012383 int base_bpp, ret = -EINVAL;
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012384 int i;
Daniel Vettere29c22c2013-02-21 00:00:16 +010012385 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +020012386
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020012387 clear_intel_crtc_state(pipe_config);
Daniel Vetter7758a112012-07-08 19:40:39 +020012388
Daniel Vettere143a212013-07-04 12:01:15 +020012389 pipe_config->cpu_transcoder =
12390 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010012391
Imre Deak2960bc92013-07-30 13:36:32 +030012392 /*
12393 * Sanitize sync polarity flags based on requested ones. If neither
12394 * positive or negative polarity is requested, treat this as meaning
12395 * negative polarity.
12396 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012397 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030012398 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012399 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030012400
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012401 if (!(pipe_config->base.adjusted_mode.flags &
Imre Deak2960bc92013-07-30 13:36:32 +030012402 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012403 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
Imre Deak2960bc92013-07-30 13:36:32 +030012404
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012405 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12406 pipe_config);
12407 if (base_bpp < 0)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012408 goto fail;
12409
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030012410 /*
12411 * Determine the real pipe dimensions. Note that stereo modes can
12412 * increase the actual pipe size due to the frame doubling and
12413 * insertion of additional space for blanks between the frame. This
12414 * is stored in the crtc timings. We use the requested mode to do this
12415 * computation to clearly distinguish it from the adjusted mode, which
12416 * can be changed by the connectors in the below retry loop.
12417 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012418 drm_crtc_get_hv_timing(&pipe_config->base.mode,
Gustavo Padovanecb7e162014-12-01 15:40:09 -080012419 &pipe_config->pipe_src_w,
12420 &pipe_config->pipe_src_h);
Ville Syrjäläe41a56b2013-10-01 22:52:14 +030012421
Daniel Vettere29c22c2013-02-21 00:00:16 +010012422encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +020012423 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +020012424 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +020012425 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +020012426
Daniel Vetter135c81b2013-07-21 21:37:09 +020012427 /* Fill in default crtc timings, allow encoders to overwrite them. */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012428 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12429 CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +020012430
Daniel Vetter7758a112012-07-08 19:40:39 +020012431 /* Pass our mode to the connectors and the CRTC to give them a chance to
12432 * adjust it according to limitations or connector properties, and also
12433 * a chance to reject the mode entirely.
12434 */
Ander Conselvan de Oliveirada3ced2982015-04-21 17:12:59 +030012435 for_each_connector_in_state(state, connector, connector_state, i) {
Ander Conselvan de Oliveira0b901872015-03-20 16:18:08 +020012436 if (connector_state->crtc != crtc)
12437 continue;
12438
12439 encoder = to_intel_encoder(connector_state->best_encoder);
12440
Daniel Vetterefea6e82013-07-21 21:36:59 +020012441 if (!(encoder->compute_config(encoder, pipe_config))) {
12442 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +020012443 goto fail;
12444 }
12445 }
12446
Daniel Vetterff9a6752013-06-01 17:16:21 +020012447 /* Set default port clock if not overwritten by the encoder. Needs to be
12448 * done afterwards in case the encoder adjusts the mode. */
12449 if (!pipe_config->port_clock)
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012450 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
Damien Lespiau241bfc32013-09-25 16:45:37 +010012451 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +020012452
Daniel Vettera43f6e02013-06-07 23:10:32 +020012453 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +010012454 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +020012455 DRM_DEBUG_KMS("CRTC fixup failed\n");
12456 goto fail;
12457 }
Daniel Vettere29c22c2013-02-21 00:00:16 +010012458
12459 if (ret == RETRY) {
12460 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12461 ret = -EINVAL;
12462 goto fail;
12463 }
12464
12465 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12466 retry = false;
12467 goto encoder_retry;
12468 }
12469
Daniel Vettere8fa4272015-08-12 11:43:34 +020012470 /* Dithering seems to not pass-through bits correctly when it should, so
12471 * only enable it on 6bpc panels. */
12472 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
Daniel Vetter62f0ace2015-08-26 18:57:26 +020012473 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
Daniel Vetterd328c9d2015-04-10 16:22:37 +020012474 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +010012475
Daniel Vetter7758a112012-07-08 19:40:39 +020012476fail:
Ander Conselvan de Oliveira548ee152015-04-21 17:13:02 +030012477 return ret;
Daniel Vetter7758a112012-07-08 19:40:39 +020012478}
12479
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012480static void
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020012481intel_modeset_update_crtc_state(struct drm_atomic_state *state)
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012482{
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030012483 struct drm_crtc *crtc;
12484 struct drm_crtc_state *crtc_state;
Maarten Lankhorst8a75d152015-07-13 16:30:14 +020012485 int i;
Daniel Vetterea9d7582012-07-10 10:42:52 +020012486
Ville Syrjälä76688512014-01-10 11:28:06 +020012487 /* Double check state. */
Maarten Lankhorst8a75d152015-07-13 16:30:14 +020012488 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorst3cb480b2015-06-01 12:49:49 +020012489 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
Maarten Lankhorstfc467a222015-06-01 12:50:07 +020012490
12491 /* Update hwmode for vblank functions */
12492 if (crtc->state->active)
12493 crtc->hwmode = crtc->state->adjusted_mode;
12494 else
12495 crtc->hwmode.crtc_clock = 0;
Maarten Lankhorst61067a52015-09-23 16:29:36 +020012496
12497 /*
12498 * Update legacy state to satisfy fbc code. This can
12499 * be removed when fbc uses the atomic state.
12500 */
12501 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12502 struct drm_plane_state *plane_state = crtc->primary->state;
12503
12504 crtc->primary->fb = plane_state->fb;
12505 crtc->x = plane_state->src_x >> 16;
12506 crtc->y = plane_state->src_y >> 16;
12507 }
Daniel Vetterea9d7582012-07-10 10:42:52 +020012508 }
Daniel Vetterea9d7582012-07-10 10:42:52 +020012509}
12510
Ville Syrjälä3bd26262013-09-06 23:29:02 +030012511static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +030012512{
Ville Syrjälä3bd26262013-09-06 23:29:02 +030012513 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +030012514
12515 if (clock1 == clock2)
12516 return true;
12517
12518 if (!clock1 || !clock2)
12519 return false;
12520
12521 diff = abs(clock1 - clock2);
12522
12523 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12524 return true;
12525
12526 return false;
12527}
12528
Daniel Vetter25c5b262012-07-08 22:08:04 +020012529#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12530 list_for_each_entry((intel_crtc), \
12531 &(dev)->mode_config.crtc_list, \
12532 base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +020012533 for_each_if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +020012534
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012535static bool
12536intel_compare_m_n(unsigned int m, unsigned int n,
12537 unsigned int m2, unsigned int n2,
12538 bool exact)
12539{
12540 if (m == m2 && n == n2)
12541 return true;
12542
12543 if (exact || !m || !n || !m2 || !n2)
12544 return false;
12545
12546 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12547
12548 if (m > m2) {
12549 while (m > m2) {
12550 m2 <<= 1;
12551 n2 <<= 1;
12552 }
12553 } else if (m < m2) {
12554 while (m < m2) {
12555 m <<= 1;
12556 n <<= 1;
12557 }
12558 }
12559
12560 return m == m2 && n == n2;
12561}
12562
12563static bool
12564intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12565 struct intel_link_m_n *m2_n2,
12566 bool adjust)
12567{
12568 if (m_n->tu == m2_n2->tu &&
12569 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12570 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12571 intel_compare_m_n(m_n->link_m, m_n->link_n,
12572 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12573 if (adjust)
12574 *m2_n2 = *m_n;
12575
12576 return true;
12577 }
12578
12579 return false;
12580}
12581
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012582static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020012583intel_pipe_config_compare(struct drm_device *dev,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020012584 struct intel_crtc_state *current_config,
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012585 struct intel_crtc_state *pipe_config,
12586 bool adjust)
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012587{
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012588 bool ret = true;
12589
12590#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12591 do { \
12592 if (!adjust) \
12593 DRM_ERROR(fmt, ##__VA_ARGS__); \
12594 else \
12595 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12596 } while (0)
12597
Daniel Vetter66e985c2013-06-05 13:34:20 +020012598#define PIPE_CONF_CHECK_X(name) \
12599 if (current_config->name != pipe_config->name) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012600 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Daniel Vetter66e985c2013-06-05 13:34:20 +020012601 "(expected 0x%08x, found 0x%08x)\n", \
12602 current_config->name, \
12603 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012604 ret = false; \
Daniel Vetter66e985c2013-06-05 13:34:20 +020012605 }
12606
Daniel Vetter08a24032013-04-19 11:25:34 +020012607#define PIPE_CONF_CHECK_I(name) \
12608 if (current_config->name != pipe_config->name) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012609 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Daniel Vetter08a24032013-04-19 11:25:34 +020012610 "(expected %i, found %i)\n", \
12611 current_config->name, \
12612 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012613 ret = false; \
12614 }
12615
12616#define PIPE_CONF_CHECK_M_N(name) \
12617 if (!intel_compare_link_m_n(&current_config->name, \
12618 &pipe_config->name,\
12619 adjust)) { \
12620 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12621 "(expected tu %i gmch %i/%i link %i/%i, " \
12622 "found tu %i, gmch %i/%i link %i/%i)\n", \
12623 current_config->name.tu, \
12624 current_config->name.gmch_m, \
12625 current_config->name.gmch_n, \
12626 current_config->name.link_m, \
12627 current_config->name.link_n, \
12628 pipe_config->name.tu, \
12629 pipe_config->name.gmch_m, \
12630 pipe_config->name.gmch_n, \
12631 pipe_config->name.link_m, \
12632 pipe_config->name.link_n); \
12633 ret = false; \
12634 }
12635
12636#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12637 if (!intel_compare_link_m_n(&current_config->name, \
12638 &pipe_config->name, adjust) && \
12639 !intel_compare_link_m_n(&current_config->alt_name, \
12640 &pipe_config->name, adjust)) { \
12641 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12642 "(expected tu %i gmch %i/%i link %i/%i, " \
12643 "or tu %i gmch %i/%i link %i/%i, " \
12644 "found tu %i, gmch %i/%i link %i/%i)\n", \
12645 current_config->name.tu, \
12646 current_config->name.gmch_m, \
12647 current_config->name.gmch_n, \
12648 current_config->name.link_m, \
12649 current_config->name.link_n, \
12650 current_config->alt_name.tu, \
12651 current_config->alt_name.gmch_m, \
12652 current_config->alt_name.gmch_n, \
12653 current_config->alt_name.link_m, \
12654 current_config->alt_name.link_n, \
12655 pipe_config->name.tu, \
12656 pipe_config->name.gmch_m, \
12657 pipe_config->name.gmch_n, \
12658 pipe_config->name.link_m, \
12659 pipe_config->name.link_n); \
12660 ret = false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +010012661 }
12662
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012663/* This is required for BDW+ where there is only one set of registers for
12664 * switching between high and low RR.
12665 * This macro can be used whenever a comparison has to be made between one
12666 * hw state and multiple sw state variables.
12667 */
12668#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12669 if ((current_config->name != pipe_config->name) && \
12670 (current_config->alt_name != pipe_config->name)) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012671 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012672 "(expected %i or %i, found %i)\n", \
12673 current_config->name, \
12674 current_config->alt_name, \
12675 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012676 ret = false; \
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012677 }
12678
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012679#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12680 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012681 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012682 "(expected %i, found %i)\n", \
12683 current_config->name & (mask), \
12684 pipe_config->name & (mask)); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012685 ret = false; \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012686 }
12687
Ville Syrjälä5e550652013-09-06 23:29:07 +030012688#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12689 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012690 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
Ville Syrjälä5e550652013-09-06 23:29:07 +030012691 "(expected %i, found %i)\n", \
12692 current_config->name, \
12693 pipe_config->name); \
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012694 ret = false; \
Ville Syrjälä5e550652013-09-06 23:29:07 +030012695 }
12696
Daniel Vetterbb760062013-06-06 14:55:52 +020012697#define PIPE_CONF_QUIRK(quirk) \
12698 ((current_config->quirks | pipe_config->quirks) & (quirk))
12699
Daniel Vettereccb1402013-05-22 00:50:22 +020012700 PIPE_CONF_CHECK_I(cpu_transcoder);
12701
Daniel Vetter08a24032013-04-19 11:25:34 +020012702 PIPE_CONF_CHECK_I(has_pch_encoder);
12703 PIPE_CONF_CHECK_I(fdi_lanes);
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012704 PIPE_CONF_CHECK_M_N(fdi_m_n);
Daniel Vetter08a24032013-04-19 11:25:34 +020012705
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030012706 PIPE_CONF_CHECK_I(has_dp_encoder);
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +030012707 PIPE_CONF_CHECK_I(lane_count);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012708
12709 if (INTEL_INFO(dev)->gen < 8) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012710 PIPE_CONF_CHECK_M_N(dp_m_n);
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012711
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012712 if (current_config->has_drrs)
12713 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12714 } else
12715 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +030012716
Jani Nikulaa65347b2015-11-27 12:21:46 +020012717 PIPE_CONF_CHECK_I(has_dsi_encoder);
12718
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12722 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12723 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12724 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012725
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012726 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12727 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12728 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12729 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12730 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12731 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012732
Daniel Vetterc93f54c2013-06-27 19:47:19 +020012733 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6897b4b2014-04-24 23:54:47 +020012734 PIPE_CONF_CHECK_I(has_hdmi_sink);
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020012735 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
Wayne Boyer666a4532015-12-09 12:29:35 -080012736 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Daniel Vetterb5a9fa02014-04-24 23:54:49 +020012737 PIPE_CONF_CHECK_I(limited_color_range);
Jesse Barnese43823e2014-11-05 14:26:08 -080012738 PIPE_CONF_CHECK_I(has_infoframe);
Daniel Vetter6c49f242013-06-06 12:45:25 +020012739
Daniel Vetter9ed109a2014-04-24 23:54:52 +020012740 PIPE_CONF_CHECK_I(has_audio);
12741
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012742 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012743 DRM_MODE_FLAG_INTERLACE);
12744
Daniel Vetterbb760062013-06-06 14:55:52 +020012745 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012746 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020012747 DRM_MODE_FLAG_PHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012748 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020012749 DRM_MODE_FLAG_NHSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012750 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020012751 DRM_MODE_FLAG_PVSYNC);
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012752 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
Daniel Vetterbb760062013-06-06 14:55:52 +020012753 DRM_MODE_FLAG_NVSYNC);
12754 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -070012755
Ville Syrjälä333b8ca2015-09-03 21:50:16 +030012756 PIPE_CONF_CHECK_X(gmch_pfit.control);
Daniel Vettere2ff2d42015-07-15 14:15:50 +020012757 /* pfit ratios are autocomputed by the hw on gen4+ */
12758 if (INTEL_INFO(dev)->gen < 4)
12759 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
Ville Syrjälä333b8ca2015-09-03 21:50:16 +030012760 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
Daniel Vetter99535992014-04-13 12:00:33 +020012761
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020012762 if (!adjust) {
12763 PIPE_CONF_CHECK_I(pipe_src_w);
12764 PIPE_CONF_CHECK_I(pipe_src_h);
12765
12766 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12767 if (current_config->pch_pfit.enabled) {
12768 PIPE_CONF_CHECK_X(pch_pfit.pos);
12769 PIPE_CONF_CHECK_X(pch_pfit.size);
12770 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +020012771
Maarten Lankhorst7aefe2b2015-09-14 11:30:10 +020012772 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12773 }
Chandra Kondurua1b22782015-04-07 15:28:45 -070012774
Jesse Barnese59150d2014-01-07 13:30:45 -080012775 /* BDW+ don't expose a synchronous way to read the state */
12776 if (IS_HASWELL(dev))
12777 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -030012778
Ville Syrjälä282740f2013-09-04 18:30:03 +030012779 PIPE_CONF_CHECK_I(double_wide);
12780
Daniel Vetter26804af2014-06-25 22:01:55 +030012781 PIPE_CONF_CHECK_X(ddi_pll_sel);
12782
Daniel Vetterc0d43d62013-06-07 23:11:08 +020012783 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +020012784 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +020012785 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +020012786 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12787 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterd452c5b2014-07-04 11:27:39 -030012788 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
Maarten Lankhorst00490c22015-11-16 14:42:12 +010012789 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
Damien Lespiau3f4cd192014-11-13 14:55:21 +000012790 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12791 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12792 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
Daniel Vetterc0d43d62013-06-07 23:11:08 +020012793
Ville Syrjälä42571ae2013-09-06 23:29:00 +030012794 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12795 PIPE_CONF_CHECK_I(pipe_bpp);
12796
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020012797 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
Jesse Barnesa9a7e982014-01-20 14:18:04 -080012798 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
Ville Syrjälä5e550652013-09-06 23:29:07 +030012799
Daniel Vetter66e985c2013-06-05 13:34:20 +020012800#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +020012801#undef PIPE_CONF_CHECK_I
Vandana Kannanb95af8b2014-08-05 07:51:23 -070012802#undef PIPE_CONF_CHECK_I_ALT
Daniel Vetter1bd1bd82013-04-29 21:56:12 +020012803#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +030012804#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +020012805#undef PIPE_CONF_QUIRK
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012806#undef INTEL_ERR_OR_DBG_KMS
Daniel Vetter627eb5a2013-04-29 19:33:42 +020012807
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012808 return ret;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010012809}
12810
Damien Lespiau08db6652014-11-04 17:06:52 +000012811static void check_wm_state(struct drm_device *dev)
12812{
12813 struct drm_i915_private *dev_priv = dev->dev_private;
12814 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12815 struct intel_crtc *intel_crtc;
12816 int plane;
12817
12818 if (INTEL_INFO(dev)->gen < 9)
12819 return;
12820
12821 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12822 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12823
12824 for_each_intel_crtc(dev, intel_crtc) {
12825 struct skl_ddb_entry *hw_entry, *sw_entry;
12826 const enum pipe pipe = intel_crtc->pipe;
12827
12828 if (!intel_crtc->active)
12829 continue;
12830
12831 /* planes */
Damien Lespiaudd740782015-02-28 14:54:08 +000012832 for_each_plane(dev_priv, pipe, plane) {
Damien Lespiau08db6652014-11-04 17:06:52 +000012833 hw_entry = &hw_ddb.plane[pipe][plane];
12834 sw_entry = &sw_ddb->plane[pipe][plane];
12835
12836 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12837 continue;
12838
12839 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12840 "(expected (%u,%u), found (%u,%u))\n",
12841 pipe_name(pipe), plane + 1,
12842 sw_entry->start, sw_entry->end,
12843 hw_entry->start, hw_entry->end);
12844 }
12845
12846 /* cursor */
Matt Roper4969d332015-09-24 15:53:10 -070012847 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12848 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
Damien Lespiau08db6652014-11-04 17:06:52 +000012849
12850 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12851 continue;
12852
12853 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12854 "(expected (%u,%u), found (%u,%u))\n",
12855 pipe_name(pipe),
12856 sw_entry->start, sw_entry->end,
12857 hw_entry->start, hw_entry->end);
12858 }
12859}
12860
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012861static void
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020012862check_connector_state(struct drm_device *dev,
12863 struct drm_atomic_state *old_state)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012864{
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020012865 struct drm_connector_state *old_conn_state;
12866 struct drm_connector *connector;
12867 int i;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012868
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020012869 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12870 struct drm_encoder *encoder = connector->encoder;
12871 struct drm_connector_state *state = connector->state;
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020012872
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012873 /* This also checks the encoder/connector hw state with the
12874 * ->get_hw_state callbacks. */
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020012875 intel_connector_check_state(to_intel_connector(connector));
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012876
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020012877 I915_STATE_WARN(state->best_encoder != encoder,
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020012878 "connector's atomic encoder doesn't match legacy encoder\n");
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012879 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012880}
12881
12882static void
12883check_encoder_state(struct drm_device *dev)
12884{
12885 struct intel_encoder *encoder;
12886 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012887
Damien Lespiaub2784e12014-08-05 11:29:37 +010012888 for_each_intel_encoder(dev, encoder) {
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012889 bool enabled = false;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012890 enum pipe pipe;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012891
12892 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12893 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030012894 encoder->base.name);
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012895
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020012896 for_each_intel_connector(dev, connector) {
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012897 if (connector->base.state->best_encoder != &encoder->base)
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012898 continue;
12899 enabled = true;
Maarten Lankhorstad3c5582015-07-13 16:30:26 +020012900
12901 I915_STATE_WARN(connector->base.state->crtc !=
12902 encoder->base.crtc,
12903 "connector's crtc doesn't match encoder crtc\n");
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012904 }
Dave Airlie0e32b392014-05-02 14:02:48 +100012905
Rob Clarke2c719b2014-12-15 13:56:32 -050012906 I915_STATE_WARN(!!encoder->base.crtc != enabled,
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012907 "encoder's enabled state mismatch "
12908 "(expected %i, found %i)\n",
12909 !!encoder->base.crtc, enabled);
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020012910
12911 if (!encoder->base.crtc) {
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012912 bool active;
12913
12914 active = encoder->get_hw_state(encoder, &pipe);
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020012915 I915_STATE_WARN(active,
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012916 "encoder detached but still enabled on pipe %c.\n",
12917 pipe_name(pipe));
Maarten Lankhorst7c60d192015-08-05 12:37:04 +020012918 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012919 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012920}
12921
12922static void
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012923check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012924{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012925 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012926 struct intel_encoder *encoder;
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012927 struct drm_crtc_state *old_crtc_state;
12928 struct drm_crtc *crtc;
12929 int i;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012930
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012931 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12933 struct intel_crtc_state *pipe_config, *sw_config;
Maarten Lankhorst7b89b8d2015-08-05 12:37:03 +020012934 bool active;
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012935
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020012936 if (!needs_modeset(crtc->state) &&
12937 !to_intel_crtc_state(crtc->state)->update_pipe)
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020012938 continue;
12939
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012940 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12941 pipe_config = to_intel_crtc_state(old_crtc_state);
12942 memset(pipe_config, 0, sizeof(*pipe_config));
12943 pipe_config->base.crtc = crtc;
12944 pipe_config->base.state = old_state;
12945
12946 DRM_DEBUG_KMS("[CRTC:%d]\n",
12947 crtc->base.id);
12948
12949 active = dev_priv->display.get_pipe_config(intel_crtc,
12950 pipe_config);
12951
12952 /* hw state is inconsistent with the pipe quirk */
12953 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12954 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12955 active = crtc->state->active;
12956
12957 I915_STATE_WARN(crtc->state->active != active,
12958 "crtc active state doesn't match with hw state "
12959 "(expected %i, found %i)\n", crtc->state->active, active);
12960
12961 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12962 "transitional active state does not match atomic hw state "
12963 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12964
12965 for_each_encoder_on_crtc(dev, crtc, encoder) {
12966 enum pipe pipe;
12967
12968 active = encoder->get_hw_state(encoder, &pipe);
12969 I915_STATE_WARN(active != crtc->state->active,
12970 "[ENCODER:%i] active %i with crtc active %i\n",
12971 encoder->base.base.id, active, crtc->state->active);
12972
12973 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12974 "Encoder connected to wrong pipe %c\n",
12975 pipe_name(pipe));
12976
12977 if (active)
12978 encoder->get_config(encoder, pipe_config);
12979 }
12980
12981 if (!crtc->state->active)
12982 continue;
12983
12984 sw_config = to_intel_crtc_state(crtc->state);
12985 if (!intel_pipe_config_compare(dev, sw_config,
12986 pipe_config, false)) {
Rob Clarke2c719b2014-12-15 13:56:32 -050012987 I915_STATE_WARN(1, "pipe state doesn't match!\n");
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012988 intel_dump_pipe_config(intel_crtc, pipe_config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020012989 "[hw state]");
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020012990 intel_dump_pipe_config(intel_crtc, sw_config,
Daniel Vetterc0b03412013-05-28 12:05:54 +020012991 "[sw state]");
12992 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020012993 }
12994}
12995
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020012996static void
12997check_shared_dpll_state(struct drm_device *dev)
12998{
Jani Nikulafbee40d2014-03-31 14:27:18 +030012999 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013000 struct intel_crtc *crtc;
13001 struct intel_dpll_hw_state dpll_hw_state;
13002 int i;
Daniel Vetter53589012013-06-05 13:34:16 +020013003
13004 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13005 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13006 int enabled_crtcs = 0, active_crtcs = 0;
13007 bool active;
13008
13009 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13010
13011 DRM_DEBUG_KMS("%s\n", pll->name);
13012
13013 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13014
Rob Clarke2c719b2014-12-15 13:56:32 -050013015 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
Daniel Vetter53589012013-06-05 13:34:16 +020013016 "more active pll users than references: %i vs %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013017 pll->active, hweight32(pll->config.crtc_mask));
Rob Clarke2c719b2014-12-15 13:56:32 -050013018 I915_STATE_WARN(pll->active && !pll->on,
Daniel Vetter53589012013-06-05 13:34:16 +020013019 "pll in active use but not on in sw tracking\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050013020 I915_STATE_WARN(pll->on && !pll->active,
Daniel Vetter35c95372013-07-17 06:55:04 +020013021 "pll in on but not on in use in sw tracking\n");
Rob Clarke2c719b2014-12-15 13:56:32 -050013022 I915_STATE_WARN(pll->on != active,
Daniel Vetter53589012013-06-05 13:34:16 +020013023 "pll on state mismatch (expected %i, found %i)\n",
13024 pll->on, active);
13025
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013026 for_each_intel_crtc(dev, crtc) {
Matt Roper83d65732015-02-25 13:12:16 -080013027 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
Daniel Vetter53589012013-06-05 13:34:16 +020013028 enabled_crtcs++;
13029 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13030 active_crtcs++;
13031 }
Rob Clarke2c719b2014-12-15 13:56:32 -050013032 I915_STATE_WARN(pll->active != active_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020013033 "pll active crtcs mismatch (expected %i, found %i)\n",
13034 pll->active, active_crtcs);
Rob Clarke2c719b2014-12-15 13:56:32 -050013035 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
Daniel Vetter53589012013-06-05 13:34:16 +020013036 "pll enabled crtcs mismatch (expected %i, found %i)\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013037 hweight32(pll->config.crtc_mask), enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +020013038
Rob Clarke2c719b2014-12-15 13:56:32 -050013039 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
Daniel Vetter66e985c2013-06-05 13:34:20 +020013040 sizeof(dpll_hw_state)),
13041 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +020013042 }
Daniel Vettere2e1ed42012-07-08 21:14:38 +020013043}
13044
Maarten Lankhorstee165b12015-08-05 12:37:00 +020013045static void
13046intel_modeset_check_state(struct drm_device *dev,
13047 struct drm_atomic_state *old_state)
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013048{
Damien Lespiau08db6652014-11-04 17:06:52 +000013049 check_wm_state(dev);
Maarten Lankhorst35dd3c62015-08-06 13:49:22 +020013050 check_connector_state(dev, old_state);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013051 check_encoder_state(dev);
Maarten Lankhorst4d20cd82015-08-05 12:37:05 +020013052 check_crtc_state(dev, old_state);
Daniel Vetter91d1b4b2013-06-05 13:34:18 +020013053 check_shared_dpll_state(dev);
13054}
13055
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +020013056void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
Ville Syrjälä18442d02013-09-13 16:00:08 +030013057 int dotclock)
13058{
13059 /*
13060 * FDI already provided one idea for the dotclock.
13061 * Yell if the encoder disagrees.
13062 */
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013063 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +030013064 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +020013065 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +030013066}
13067
Ville Syrjälä80715b22014-05-15 20:23:23 +030013068static void update_scanline_offset(struct intel_crtc *crtc)
13069{
13070 struct drm_device *dev = crtc->base.dev;
13071
13072 /*
13073 * The scanline counter increments at the leading edge of hsync.
13074 *
13075 * On most platforms it starts counting from vtotal-1 on the
13076 * first active line. That means the scanline counter value is
13077 * always one less than what we would expect. Ie. just after
13078 * start of vblank, which also occurs at start of hsync (on the
13079 * last active line), the scanline counter will read vblank_start-1.
13080 *
13081 * On gen2 the scanline counter starts counting from 1 instead
13082 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13083 * to keep the value positive), instead of adding one.
13084 *
13085 * On HSW+ the behaviour of the scanline counter depends on the output
13086 * type. For DP ports it behaves like most other platforms, but on HDMI
13087 * there's an extra 1 line difference. So we need to add two instead of
13088 * one to the value.
13089 */
13090 if (IS_GEN2(dev)) {
Ville Syrjälä124abe02015-09-08 13:40:45 +030013091 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
Ville Syrjälä80715b22014-05-15 20:23:23 +030013092 int vtotal;
13093
Ville Syrjälä124abe02015-09-08 13:40:45 +030013094 vtotal = adjusted_mode->crtc_vtotal;
13095 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä80715b22014-05-15 20:23:23 +030013096 vtotal /= 2;
13097
13098 crtc->scanline_offset = vtotal - 1;
13099 } else if (HAS_DDI(dev) &&
Ander Conselvan de Oliveira409ee762014-10-20 13:46:45 +030013100 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
Ville Syrjälä80715b22014-05-15 20:23:23 +030013101 crtc->scanline_offset = 2;
13102 } else
13103 crtc->scanline_offset = 1;
13104}
13105
Maarten Lankhorstad421372015-06-15 12:33:42 +020013106static void intel_modeset_clear_plls(struct drm_atomic_state *state)
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013107{
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030013108 struct drm_device *dev = state->dev;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013109 struct drm_i915_private *dev_priv = to_i915(dev);
Maarten Lankhorstad421372015-06-15 12:33:42 +020013110 struct intel_shared_dpll_config *shared_dpll = NULL;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013111 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013112 struct intel_crtc_state *intel_crtc_state;
13113 struct drm_crtc *crtc;
13114 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013115 int i;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013116
13117 if (!dev_priv->display.crtc_compute_clock)
Maarten Lankhorstad421372015-06-15 12:33:42 +020013118 return;
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013119
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013120 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorstad421372015-06-15 12:33:42 +020013121 int dpll;
13122
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013123 intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira4978cc92015-04-21 17:13:21 +030013124 intel_crtc_state = to_intel_crtc_state(crtc_state);
Maarten Lankhorstad421372015-06-15 12:33:42 +020013125 dpll = intel_crtc_state->shared_dpll;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013126
Maarten Lankhorstad421372015-06-15 12:33:42 +020013127 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
Ander Conselvan de Oliveira225da592015-04-02 14:47:57 +030013128 continue;
13129
Maarten Lankhorstad421372015-06-15 12:33:42 +020013130 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013131
Maarten Lankhorstad421372015-06-15 12:33:42 +020013132 if (!shared_dpll)
13133 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13134
13135 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013136 }
Ander Conselvan de Oliveiraed6739e2015-01-29 16:55:08 +020013137}
13138
Maarten Lankhorst99d736a2015-06-01 12:50:09 +020013139/*
13140 * This implements the workaround described in the "notes" section of the mode
13141 * set sequence documentation. When going from no pipes or single pipe to
13142 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13143 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13144 */
13145static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13146{
13147 struct drm_crtc_state *crtc_state;
13148 struct intel_crtc *intel_crtc;
13149 struct drm_crtc *crtc;
13150 struct intel_crtc_state *first_crtc_state = NULL;
13151 struct intel_crtc_state *other_crtc_state = NULL;
13152 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13153 int i;
13154
13155 /* look at all crtc's that are going to be enabled in during modeset */
13156 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13157 intel_crtc = to_intel_crtc(crtc);
13158
13159 if (!crtc_state->active || !needs_modeset(crtc_state))
13160 continue;
13161
13162 if (first_crtc_state) {
13163 other_crtc_state = to_intel_crtc_state(crtc_state);
13164 break;
13165 } else {
13166 first_crtc_state = to_intel_crtc_state(crtc_state);
13167 first_pipe = intel_crtc->pipe;
13168 }
13169 }
13170
13171 /* No workaround needed? */
13172 if (!first_crtc_state)
13173 return 0;
13174
13175 /* w/a possibly needed, check how many crtc's are already enabled. */
13176 for_each_intel_crtc(state->dev, intel_crtc) {
13177 struct intel_crtc_state *pipe_config;
13178
13179 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13180 if (IS_ERR(pipe_config))
13181 return PTR_ERR(pipe_config);
13182
13183 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13184
13185 if (!pipe_config->base.active ||
13186 needs_modeset(&pipe_config->base))
13187 continue;
13188
13189 /* 2 or more enabled crtcs means no need for w/a */
13190 if (enabled_pipe != INVALID_PIPE)
13191 return 0;
13192
13193 enabled_pipe = intel_crtc->pipe;
13194 }
13195
13196 if (enabled_pipe != INVALID_PIPE)
13197 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13198 else if (other_crtc_state)
13199 other_crtc_state->hsw_workaround_pipe = first_pipe;
13200
13201 return 0;
13202}
13203
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013204static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13205{
13206 struct drm_crtc *crtc;
13207 struct drm_crtc_state *crtc_state;
13208 int ret = 0;
13209
13210 /* add all active pipes to the state */
13211 for_each_crtc(state->dev, crtc) {
13212 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13213 if (IS_ERR(crtc_state))
13214 return PTR_ERR(crtc_state);
13215
13216 if (!crtc_state->active || needs_modeset(crtc_state))
13217 continue;
13218
13219 crtc_state->mode_changed = true;
13220
13221 ret = drm_atomic_add_affected_connectors(state, crtc);
13222 if (ret)
13223 break;
13224
13225 ret = drm_atomic_add_affected_planes(state, crtc);
13226 if (ret)
13227 break;
13228 }
13229
13230 return ret;
13231}
13232
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013233static int intel_modeset_checks(struct drm_atomic_state *state)
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013234{
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013235 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13236 struct drm_i915_private *dev_priv = state->dev->dev_private;
13237 struct drm_crtc *crtc;
13238 struct drm_crtc_state *crtc_state;
13239 int ret = 0, i;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013240
Maarten Lankhorstb3592832015-06-15 12:33:38 +020013241 if (!check_digital_port_conflicts(state)) {
13242 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13243 return -EINVAL;
13244 }
13245
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013246 intel_state->modeset = true;
13247 intel_state->active_crtcs = dev_priv->active_crtcs;
13248
13249 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13250 if (crtc_state->active)
13251 intel_state->active_crtcs |= 1 << i;
13252 else
13253 intel_state->active_crtcs &= ~(1 << i);
13254 }
13255
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013256 /*
13257 * See if the config requires any additional preparation, e.g.
13258 * to adjust global state with pipes off. We need to do this
13259 * here so we can get the modeset_pipe updated config for the new
13260 * mode set on this crtc. For other crtcs we need to use the
13261 * adjusted_mode bits in the crtc directly.
13262 */
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013263 if (dev_priv->display.modeset_calc_cdclk) {
13264 unsigned int cdclk;
Ville Syrjäläb432e5c2015-06-03 15:45:13 +030013265
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013266 ret = dev_priv->display.modeset_calc_cdclk(state);
13267
13268 cdclk = to_intel_atomic_state(state)->cdclk;
13269 if (!ret && cdclk != dev_priv->cdclk_freq)
13270 ret = intel_modeset_all_pipes(state);
13271
13272 if (ret < 0)
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013273 return ret;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013274 } else
13275 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013276
Maarten Lankhorstad421372015-06-15 12:33:42 +020013277 intel_modeset_clear_plls(state);
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013278
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013279 if (IS_HASWELL(dev_priv))
Maarten Lankhorstad421372015-06-15 12:33:42 +020013280 return haswell_mode_set_planes_workaround(state);
Maarten Lankhorst99d736a2015-06-01 12:50:09 +020013281
Maarten Lankhorstad421372015-06-15 12:33:42 +020013282 return 0;
Ander Conselvan de Oliveira054518d2015-04-21 17:13:06 +030013283}
13284
Matt Roperaa363132015-09-24 15:53:18 -070013285/*
13286 * Handle calculation of various watermark data at the end of the atomic check
13287 * phase. The code here should be run after the per-crtc and per-plane 'check'
13288 * handlers to ensure that all derived state has been updated.
13289 */
13290static void calc_watermark_data(struct drm_atomic_state *state)
13291{
13292 struct drm_device *dev = state->dev;
13293 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13294 struct drm_crtc *crtc;
13295 struct drm_crtc_state *cstate;
13296 struct drm_plane *plane;
13297 struct drm_plane_state *pstate;
13298
13299 /*
13300 * Calculate watermark configuration details now that derived
13301 * plane/crtc state is all properly updated.
13302 */
13303 drm_for_each_crtc(crtc, dev) {
13304 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13305 crtc->state;
13306
13307 if (cstate->active)
13308 intel_state->wm_config.num_pipes_active++;
13309 }
13310 drm_for_each_legacy_plane(plane, dev) {
13311 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13312 plane->state;
13313
13314 if (!to_intel_plane_state(pstate)->visible)
13315 continue;
13316
13317 intel_state->wm_config.sprites_enabled = true;
13318 if (pstate->crtc_w != pstate->src_w >> 16 ||
13319 pstate->crtc_h != pstate->src_h >> 16)
13320 intel_state->wm_config.sprites_scaled = true;
13321 }
13322}
13323
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013324/**
13325 * intel_atomic_check - validate state object
13326 * @dev: drm device
13327 * @state: state to validate
13328 */
13329static int intel_atomic_check(struct drm_device *dev,
13330 struct drm_atomic_state *state)
Daniel Vettera6778b32012-07-02 09:56:42 +020013331{
Matt Roperaa363132015-09-24 15:53:18 -070013332 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013333 struct drm_crtc *crtc;
13334 struct drm_crtc_state *crtc_state;
13335 int ret, i;
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013336 bool any_ms = false;
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013337
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013338 ret = drm_atomic_helper_check_modeset(dev, state);
Daniel Vettera6778b32012-07-02 09:56:42 +020013339 if (ret)
13340 return ret;
13341
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013342 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013343 struct intel_crtc_state *pipe_config =
13344 to_intel_crtc_state(crtc_state);
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013345
Maarten Lankhorstba8af3e2015-11-16 12:49:14 +010013346 memset(&to_intel_crtc(crtc)->atomic, 0,
13347 sizeof(struct intel_crtc_atomic_commit));
13348
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013349 /* Catch I915_MODE_FLAG_INHERITED */
13350 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13351 crtc_state->mode_changed = true;
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013352
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013353 if (!crtc_state->enable) {
13354 if (needs_modeset(crtc_state))
13355 any_ms = true;
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013356 continue;
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013357 }
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013358
Daniel Vetter26495482015-07-15 14:15:52 +020013359 if (!needs_modeset(crtc_state))
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013360 continue;
13361
Daniel Vetter26495482015-07-15 14:15:52 +020013362 /* FIXME: For only active_changed we shouldn't need to do any
13363 * state recomputation at all. */
13364
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013365 ret = drm_atomic_add_affected_connectors(state, crtc);
13366 if (ret)
13367 return ret;
Maarten Lankhorstb3592832015-06-15 12:33:38 +020013368
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013369 ret = intel_modeset_pipe_config(crtc, pipe_config);
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013370 if (ret)
13371 return ret;
13372
Jani Nikula73831232015-11-19 10:26:30 +020013373 if (i915.fastboot &&
13374 intel_pipe_config_compare(state->dev,
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013375 to_intel_crtc_state(crtc->state),
Daniel Vetter1ed51de2015-07-15 14:15:51 +020013376 pipe_config, true)) {
Daniel Vetter26495482015-07-15 14:15:52 +020013377 crtc_state->mode_changed = false;
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013378 to_intel_crtc_state(crtc_state)->update_pipe = true;
Daniel Vetter26495482015-07-15 14:15:52 +020013379 }
13380
13381 if (needs_modeset(crtc_state)) {
13382 any_ms = true;
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013383
Maarten Lankhorstcfb23ed2015-07-14 12:17:40 +020013384 ret = drm_atomic_add_affected_planes(state, crtc);
13385 if (ret)
13386 return ret;
13387 }
13388
Daniel Vetter26495482015-07-15 14:15:52 +020013389 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13390 needs_modeset(crtc_state) ?
13391 "[modeset]" : "[fastset]");
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013392 }
13393
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013394 if (any_ms) {
13395 ret = intel_modeset_checks(state);
13396
13397 if (ret)
13398 return ret;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013399 } else
Matt Roperaa363132015-09-24 15:53:18 -070013400 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
Ander Conselvan de Oliveirac347a672015-06-01 12:50:02 +020013401
Matt Roperaa363132015-09-24 15:53:18 -070013402 ret = drm_atomic_helper_check_planes(state->dev, state);
13403 if (ret)
13404 return ret;
13405
13406 calc_watermark_data(state);
13407
13408 return 0;
Daniel Vettera6778b32012-07-02 09:56:42 +020013409}
13410
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013411static int intel_atomic_prepare_commit(struct drm_device *dev,
13412 struct drm_atomic_state *state,
13413 bool async)
13414{
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013415 struct drm_i915_private *dev_priv = dev->dev_private;
13416 struct drm_plane_state *plane_state;
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013417 struct drm_crtc_state *crtc_state;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013418 struct drm_plane *plane;
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013419 struct drm_crtc *crtc;
13420 int i, ret;
13421
13422 if (async) {
13423 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13424 return -EINVAL;
13425 }
13426
13427 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13428 ret = intel_crtc_wait_for_pending_flips(crtc);
13429 if (ret)
13430 return ret;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013431
13432 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13433 flush_workqueue(dev_priv->wq);
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013434 }
13435
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013436 ret = mutex_lock_interruptible(&dev->struct_mutex);
13437 if (ret)
13438 return ret;
13439
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013440 ret = drm_atomic_helper_prepare_planes(dev, state);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013441 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13442 u32 reset_counter;
13443
13444 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13445 mutex_unlock(&dev->struct_mutex);
13446
13447 for_each_plane_in_state(state, plane, plane_state, i) {
13448 struct intel_plane_state *intel_plane_state =
13449 to_intel_plane_state(plane_state);
13450
13451 if (!intel_plane_state->wait_req)
13452 continue;
13453
13454 ret = __i915_wait_request(intel_plane_state->wait_req,
13455 reset_counter, true,
13456 NULL, NULL);
13457
13458 /* Swallow -EIO errors to allow updates during hw lockup. */
13459 if (ret == -EIO)
13460 ret = 0;
13461
13462 if (ret)
13463 break;
13464 }
13465
13466 if (!ret)
13467 return 0;
13468
13469 mutex_lock(&dev->struct_mutex);
13470 drm_atomic_helper_cleanup_planes(dev, state);
13471 }
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013472
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013473 mutex_unlock(&dev->struct_mutex);
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013474 return ret;
13475}
13476
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013477/**
13478 * intel_atomic_commit - commit validated state object
13479 * @dev: DRM device
13480 * @state: the top-level driver state object
13481 * @async: asynchronous commit
13482 *
13483 * This function commits a top-level state object that has been validated
13484 * with drm_atomic_helper_check().
13485 *
13486 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13487 * we can only handle plane-related operations and do not yet support
13488 * asynchronous commit.
13489 *
13490 * RETURNS
13491 * Zero for success or -errno.
13492 */
13493static int intel_atomic_commit(struct drm_device *dev,
13494 struct drm_atomic_state *state,
13495 bool async)
Daniel Vettera6778b32012-07-02 09:56:42 +020013496{
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013497 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
Jani Nikulafbee40d2014-03-31 14:27:18 +030013498 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013499 struct drm_crtc_state *crtc_state;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013500 struct drm_crtc *crtc;
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013501 int ret = 0, i;
13502 bool hw_check = intel_state->modeset;
Daniel Vettera6778b32012-07-02 09:56:42 +020013503
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013504 ret = intel_atomic_prepare_commit(dev, state, async);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013505 if (ret) {
13506 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030013507 return ret;
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013508 }
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030013509
Maarten Lankhorst1c5e19f2015-06-01 12:50:06 +020013510 drm_atomic_helper_swap_state(dev, state);
Matt Roperaa363132015-09-24 15:53:18 -070013511 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
Maarten Lankhorst1c5e19f2015-06-01 12:50:06 +020013512
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013513 if (intel_state->modeset) {
13514 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13515 sizeof(intel_state->min_pixclk));
13516 dev_priv->active_crtcs = intel_state->active_crtcs;
13517 }
13518
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013519 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorsta5392052015-06-15 12:33:52 +020013520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13521
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013522 if (!needs_modeset(crtc->state))
13523 continue;
13524
Maarten Lankhorsta5392052015-06-15 12:33:52 +020013525 intel_pre_plane_update(intel_crtc);
Daniel Vetter460da9162013-03-27 00:44:51 +010013526
Maarten Lankhorsta5392052015-06-15 12:33:52 +020013527 if (crtc_state->active) {
13528 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13529 dev_priv->display.crtc_disable(crtc);
Maarten Lankhorsteddfcbc2015-06-15 12:33:53 +020013530 intel_crtc->active = false;
13531 intel_disable_shared_dpll(intel_crtc);
Ville Syrjälä9bbc8258a2015-11-20 22:09:20 +020013532
13533 /*
13534 * Underruns don't always raise
13535 * interrupts, so check manually.
13536 */
13537 intel_check_cpu_fifo_underruns(dev_priv);
13538 intel_check_pch_fifo_underruns(dev_priv);
Maarten Lankhorstb9001112015-11-19 16:07:16 +010013539
13540 if (!crtc->state->active)
13541 intel_update_watermarks(crtc);
Maarten Lankhorsta5392052015-06-15 12:33:52 +020013542 }
Daniel Vetterb8cecdf2013-03-27 00:44:50 +010013543 }
Daniel Vetter7758a112012-07-08 19:40:39 +020013544
Daniel Vetterea9d7582012-07-10 10:42:52 +020013545 /* Only after disabling all output pipelines that will be changed can we
13546 * update the the output configuration. */
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020013547 intel_modeset_update_crtc_state(state);
Daniel Vetterea9d7582012-07-10 10:42:52 +020013548
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013549 if (intel_state->modeset) {
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020013550 intel_shared_dpll_commit(state);
13551
13552 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
Maarten Lankhorst61333b62015-06-15 12:33:50 +020013553 modeset_update_crtc_power_domains(state);
Maarten Lankhorst4740b0f2015-08-05 12:37:10 +020013554 }
Daniel Vetter47fab732012-10-26 10:58:18 +020013555
Daniel Vettera6778b32012-07-02 09:56:42 +020013556 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Ander Conselvan de Oliveira0a9ab302015-04-21 17:13:04 +030013557 for_each_crtc_in_state(state, crtc, crtc_state, i) {
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020013558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13559 bool modeset = needs_modeset(crtc->state);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013560 bool update_pipe = !modeset &&
13561 to_intel_crtc_state(crtc->state)->update_pipe;
13562 unsigned long put_domains = 0;
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020013563
Patrik Jakobsson9f836f92015-11-16 16:20:01 +010013564 if (modeset)
13565 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13566
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020013567 if (modeset && crtc->state->active) {
Maarten Lankhorsta5392052015-06-15 12:33:52 +020013568 update_scanline_offset(to_intel_crtc(crtc));
13569 dev_priv->display.crtc_enable(crtc);
13570 }
13571
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013572 if (update_pipe) {
13573 put_domains = modeset_get_crtc_power_domains(crtc);
13574
13575 /* make sure intel_modeset_check_state runs */
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013576 hw_check = true;
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013577 }
13578
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020013579 if (!modeset)
13580 intel_pre_plane_update(intel_crtc);
13581
Maarten Lankhorst6173ee22015-09-23 16:29:39 +020013582 if (crtc->state->active &&
13583 (crtc->state->planes_changed || update_pipe))
Maarten Lankhorst62852622015-09-23 16:29:38 +020013584 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013585
13586 if (put_domains)
13587 modeset_put_power_domains(dev_priv, put_domains);
13588
Maarten Lankhorstf6ac4b22015-07-13 16:30:31 +020013589 intel_post_plane_update(intel_crtc);
Patrik Jakobsson9f836f92015-11-16 16:20:01 +010013590
13591 if (modeset)
13592 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
Ville Syrjälä80715b22014-05-15 20:23:23 +030013593 }
Daniel Vettera6778b32012-07-02 09:56:42 +020013594
Daniel Vettera6778b32012-07-02 09:56:42 +020013595 /* FIXME: add subpixel order */
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013596
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013597 drm_atomic_helper_wait_for_vblanks(dev, state);
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013598
13599 mutex_lock(&dev->struct_mutex);
Ander Conselvan de Oliveirad4afb8c2015-04-21 17:13:22 +030013600 drm_atomic_helper_cleanup_planes(dev, state);
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013601 mutex_unlock(&dev->struct_mutex);
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030013602
Maarten Lankhorst565602d2015-12-10 12:33:57 +010013603 if (hw_check)
Maarten Lankhorstee165b12015-08-05 12:37:00 +020013604 intel_modeset_check_state(dev, state);
13605
13606 drm_atomic_state_free(state);
Jesse Barnes7f27126e2014-11-05 14:26:06 -080013607
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013608 return 0;
Daniel Vetterf30da182013-04-11 20:22:50 +020013609}
13610
Chris Wilsonc0c36b942012-12-19 16:08:43 +000013611void intel_crtc_restore_mode(struct drm_crtc *crtc)
13612{
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013613 struct drm_device *dev = crtc->dev;
13614 struct drm_atomic_state *state;
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013615 struct drm_crtc_state *crtc_state;
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030013616 int ret;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013617
13618 state = drm_atomic_state_alloc(dev);
13619 if (!state) {
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013620 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013621 crtc->base.id);
13622 return;
13623 }
13624
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013625 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013626
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013627retry:
13628 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13629 ret = PTR_ERR_OR_ZERO(crtc_state);
13630 if (!ret) {
13631 if (!crtc_state->active)
13632 goto out;
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013633
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013634 crtc_state->mode_changed = true;
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013635 ret = drm_atomic_commit(state);
Ander Conselvan de Oliveira83a57152015-03-20 16:18:03 +020013636 }
13637
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013638 if (ret == -EDEADLK) {
13639 drm_atomic_state_clear(state);
13640 drm_modeset_backoff(state->acquire_ctx);
13641 goto retry;
Ander Conselvan de Oliveira4be07312015-04-21 17:13:01 +030013642 }
13643
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030013644 if (ret)
Maarten Lankhorste694eb02015-07-14 16:19:12 +020013645out:
Ander Conselvan de Oliveira2bfb4622015-04-21 17:13:20 +030013646 drm_atomic_state_free(state);
Chris Wilsonc0c36b942012-12-19 16:08:43 +000013647}
13648
Daniel Vetter25c5b262012-07-08 22:08:04 +020013649#undef for_each_intel_crtc_masked
13650
Chris Wilsonf6e5b162011-04-12 18:06:51 +010013651static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010013652 .gamma_set = intel_crtc_gamma_set,
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020013653 .set_config = drm_atomic_helper_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010013654 .destroy = intel_crtc_destroy,
13655 .page_flip = intel_crtc_page_flip,
Matt Roper13568372015-01-21 16:35:47 -080013656 .atomic_duplicate_state = intel_crtc_duplicate_state,
13657 .atomic_destroy_state = intel_crtc_destroy_state,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010013658};
13659
Daniel Vetter53589012013-06-05 13:34:16 +020013660static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13661 struct intel_shared_dpll *pll,
13662 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013663{
Daniel Vetter53589012013-06-05 13:34:16 +020013664 uint32_t val;
13665
Daniel Vetterf458ebb2014-09-30 10:56:39 +020013666 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030013667 return false;
13668
Daniel Vetter53589012013-06-05 13:34:16 +020013669 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020013670 hw_state->dpll = val;
13671 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13672 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020013673
13674 return val & DPLL_VCO_ENABLE;
13675}
13676
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013677static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13678 struct intel_shared_dpll *pll)
13679{
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013680 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13681 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013682}
13683
Daniel Vettere7b903d2013-06-05 13:34:14 +020013684static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13685 struct intel_shared_dpll *pll)
13686{
Daniel Vettere7b903d2013-06-05 13:34:14 +020013687 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020013688 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020013689
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013690 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013691
13692 /* Wait for the clocks to stabilize. */
13693 POSTING_READ(PCH_DPLL(pll->id));
13694 udelay(150);
13695
13696 /* The pixel multiplier can only be updated once the
13697 * DPLL is enabled and the clocks are stable.
13698 *
13699 * So write it again.
13700 */
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020013701 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013702 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020013703 udelay(200);
13704}
13705
13706static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13707 struct intel_shared_dpll *pll)
13708{
13709 struct drm_device *dev = dev_priv->dev;
13710 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020013711
13712 /* Make sure no transcoder isn't still depending on us. */
Damien Lespiaud3fcc802014-05-13 23:32:22 +010013713 for_each_intel_crtc(dev, crtc) {
Daniel Vettere7b903d2013-06-05 13:34:14 +020013714 if (intel_crtc_to_shared_dpll(crtc) == pll)
13715 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13716 }
13717
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013718 I915_WRITE(PCH_DPLL(pll->id), 0);
13719 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020013720 udelay(200);
13721}
13722
Daniel Vetter46edb022013-06-05 13:34:12 +020013723static char *ibx_pch_dpll_names[] = {
13724 "PCH DPLL A",
13725 "PCH DPLL B",
13726};
13727
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013728static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013729{
Daniel Vettere7b903d2013-06-05 13:34:14 +020013730 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013731 int i;
13732
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013733 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013734
Daniel Vettere72f9fb2013-06-05 13:34:06 +020013735 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020013736 dev_priv->shared_dplls[i].id = i;
13737 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020013738 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020013739 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13740 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020013741 dev_priv->shared_dplls[i].get_hw_state =
13742 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010013743 }
13744}
13745
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013746static void intel_shared_dpll_init(struct drm_device *dev)
13747{
Daniel Vettere7b903d2013-06-05 13:34:14 +020013748 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013749
Daniel Vetter9cd86932014-06-25 22:01:57 +030013750 if (HAS_DDI(dev))
13751 intel_ddi_pll_init(dev);
13752 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013753 ibx_pch_dpll_init(dev);
13754 else
13755 dev_priv->num_shared_dpll = 0;
13756
13757 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020013758}
13759
Matt Roper6beb8c232014-12-01 15:40:14 -080013760/**
13761 * intel_prepare_plane_fb - Prepare fb for usage on plane
13762 * @plane: drm plane to prepare for
13763 * @fb: framebuffer to prepare for presentation
13764 *
13765 * Prepares a framebuffer for usage on a display plane. Generally this
13766 * involves pinning the underlying object and updating the frontbuffer tracking
13767 * bits. Some older platforms need special physical address handling for
13768 * cursor planes.
13769 *
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013770 * Must be called with struct_mutex held.
13771 *
Matt Roper6beb8c232014-12-01 15:40:14 -080013772 * Returns 0 on success, negative error code on failure.
13773 */
13774int
13775intel_prepare_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +000013776 const struct drm_plane_state *new_state)
Matt Roper465c1202014-05-29 08:06:54 -070013777{
13778 struct drm_device *dev = plane->dev;
Maarten Lankhorst844f9112015-09-02 10:42:40 +020013779 struct drm_framebuffer *fb = new_state->fb;
Matt Roper6beb8c232014-12-01 15:40:14 -080013780 struct intel_plane *intel_plane = to_intel_plane(plane);
Matt Roper6beb8c232014-12-01 15:40:14 -080013781 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013782 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
Matt Roper6beb8c232014-12-01 15:40:14 -080013783 int ret = 0;
Matt Roper465c1202014-05-29 08:06:54 -070013784
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013785 if (!obj && !old_obj)
Matt Roper465c1202014-05-29 08:06:54 -070013786 return 0;
13787
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013788 if (old_obj) {
13789 struct drm_crtc_state *crtc_state =
13790 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13791
13792 /* Big Hammer, we also need to ensure that any pending
13793 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13794 * current scanout is retired before unpinning the old
13795 * framebuffer. Note that we rely on userspace rendering
13796 * into the buffer attached to the pipe they are waiting
13797 * on. If not, userspace generates a GPU hang with IPEHR
13798 * point to the MI_WAIT_FOR_EVENT.
13799 *
13800 * This should only fail upon a hung GPU, in which case we
13801 * can safely continue.
13802 */
13803 if (needs_modeset(crtc_state))
13804 ret = i915_gem_object_wait_rendering(old_obj, true);
13805
13806 /* Swallow -EIO errors to allow updates during hw lockup. */
13807 if (ret && ret != -EIO)
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013808 return ret;
Maarten Lankhorst5008e872015-08-18 13:40:05 +020013809 }
13810
Alex Goins3c28ff22015-11-25 18:43:39 -080013811 /* For framebuffer backed by dmabuf, wait for fence */
13812 if (obj && obj->base.dma_buf) {
13813 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13814 false, true,
13815 MAX_SCHEDULE_TIMEOUT);
13816 if (ret == -ERESTARTSYS)
13817 return ret;
13818
13819 WARN_ON(ret < 0);
13820 }
13821
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013822 if (!obj) {
13823 ret = 0;
13824 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
Matt Roper6beb8c232014-12-01 15:40:14 -080013825 INTEL_INFO(dev)->cursor_needs_physical) {
13826 int align = IS_I830(dev) ? 16 * 1024 : 256;
13827 ret = i915_gem_object_attach_phys(obj, align);
13828 if (ret)
13829 DRM_DEBUG_KMS("failed to attach phys object\n");
13830 } else {
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013831 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
Matt Roper6beb8c232014-12-01 15:40:14 -080013832 }
13833
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013834 if (ret == 0) {
13835 if (obj) {
13836 struct intel_plane_state *plane_state =
13837 to_intel_plane_state(new_state);
13838
13839 i915_gem_request_assign(&plane_state->wait_req,
13840 obj->last_write_req);
13841 }
13842
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030013843 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013844 }
Matt Roper6beb8c232014-12-01 15:40:14 -080013845
Matt Roper6beb8c232014-12-01 15:40:14 -080013846 return ret;
13847}
13848
Matt Roper38f3ce32014-12-02 07:45:25 -080013849/**
13850 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13851 * @plane: drm plane to clean up for
13852 * @fb: old framebuffer that was on plane
13853 *
13854 * Cleans up a framebuffer that has just been removed from a plane.
Maarten Lankhorstf9356752015-08-18 13:40:05 +020013855 *
13856 * Must be called with struct_mutex held.
Matt Roper38f3ce32014-12-02 07:45:25 -080013857 */
13858void
13859intel_cleanup_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +000013860 const struct drm_plane_state *old_state)
Matt Roper38f3ce32014-12-02 07:45:25 -080013861{
13862 struct drm_device *dev = plane->dev;
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013863 struct intel_plane *intel_plane = to_intel_plane(plane);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013864 struct intel_plane_state *old_intel_state;
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013865 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13866 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
Matt Roper38f3ce32014-12-02 07:45:25 -080013867
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013868 old_intel_state = to_intel_plane_state(old_state);
13869
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013870 if (!obj && !old_obj)
Matt Roper38f3ce32014-12-02 07:45:25 -080013871 return;
13872
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013873 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13874 !INTEL_INFO(dev)->cursor_needs_physical))
Maarten Lankhorst844f9112015-09-02 10:42:40 +020013875 intel_unpin_fb_obj(old_state->fb, old_state);
Maarten Lankhorst1ee49392015-09-23 13:27:08 +020013876
13877 /* prepare_fb aborted? */
13878 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13879 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13880 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
Maarten Lankhorst7580d772015-08-18 13:40:06 +020013881
13882 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13883
Matt Roper465c1202014-05-29 08:06:54 -070013884}
13885
Chandra Konduru6156a452015-04-27 13:48:39 -070013886int
13887skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13888{
13889 int max_scale;
13890 struct drm_device *dev;
13891 struct drm_i915_private *dev_priv;
13892 int crtc_clock, cdclk;
13893
Maarten Lankhorstbf8a0af2015-11-24 11:29:02 +010013894 if (!intel_crtc || !crtc_state->base.enable)
Chandra Konduru6156a452015-04-27 13:48:39 -070013895 return DRM_PLANE_HELPER_NO_SCALING;
13896
13897 dev = intel_crtc->base.dev;
13898 dev_priv = dev->dev_private;
13899 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020013900 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
Chandra Konduru6156a452015-04-27 13:48:39 -070013901
Tvrtko Ursulin54bf1ce2015-10-20 17:17:07 +010013902 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
Chandra Konduru6156a452015-04-27 13:48:39 -070013903 return DRM_PLANE_HELPER_NO_SCALING;
13904
13905 /*
13906 * skl max scale is lower of:
13907 * close to 3 but not 3, -1 is for that purpose
13908 * or
13909 * cdclk/crtc_clock
13910 */
13911 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13912
13913 return max_scale;
13914}
13915
Matt Roper465c1202014-05-29 08:06:54 -070013916static int
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013917intel_check_primary_plane(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020013918 struct intel_crtc_state *crtc_state,
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013919 struct intel_plane_state *state)
Matt Roper465c1202014-05-29 08:06:54 -070013920{
Matt Roper2b875c22014-12-01 15:40:13 -080013921 struct drm_crtc *crtc = state->base.crtc;
13922 struct drm_framebuffer *fb = state->base.fb;
Chandra Konduru6156a452015-04-27 13:48:39 -070013923 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020013924 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13925 bool can_position = false;
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013926
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020013927 /* use scaler when colorkey is not required */
13928 if (INTEL_INFO(plane->dev)->gen >= 9 &&
Maarten Lankhorst818ed962015-06-15 12:33:54 +020013929 state->ckey.flags == I915_SET_COLORKEY_NONE) {
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020013930 min_scale = 1;
13931 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
Sonika Jindald8106362015-04-10 14:37:28 +053013932 can_position = true;
Chandra Konduru6156a452015-04-27 13:48:39 -070013933 }
Sonika Jindald8106362015-04-10 14:37:28 +053013934
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020013935 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13936 &state->dst, &state->clip,
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020013937 min_scale, max_scale,
13938 can_position, true,
13939 &state->visible);
Matt Roper465c1202014-05-29 08:06:54 -070013940}
13941
Gustavo Padovan14af2932014-10-24 14:51:31 +010013942static void
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013943intel_commit_primary_plane(struct drm_plane *plane,
13944 struct intel_plane_state *state)
13945{
Matt Roper2b875c22014-12-01 15:40:13 -080013946 struct drm_crtc *crtc = state->base.crtc;
13947 struct drm_framebuffer *fb = state->base.fb;
13948 struct drm_device *dev = plane->dev;
Sonika Jindal48404c12014-08-22 14:06:04 +053013949 struct drm_i915_private *dev_priv = dev->dev_private;
Matt Ropercf4c7c12014-12-04 10:27:42 -080013950
Matt Roperea2c67b2014-12-23 10:41:52 -080013951 crtc = crtc ? crtc : plane->crtc;
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013952
Maarten Lankhorstd4b08632015-09-10 16:07:56 +020013953 dev_priv->display.update_primary_plane(crtc, fb,
13954 state->src.x1 >> 16,
13955 state->src.y1 >> 16);
Matt Roper32b7eee2014-12-24 07:59:06 -080013956}
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013957
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013958static void
13959intel_disable_primary_plane(struct drm_plane *plane,
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +020013960 struct drm_crtc *crtc)
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013961{
13962 struct drm_device *dev = plane->dev;
13963 struct drm_i915_private *dev_priv = dev->dev_private;
13964
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030013965 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13966}
13967
Maarten Lankhorst613d2b22015-07-21 13:28:58 +020013968static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13969 struct drm_crtc_state *old_crtc_state)
Matt Roper32b7eee2014-12-24 07:59:06 -080013970{
13971 struct drm_device *dev = crtc->dev;
Matt Roper32b7eee2014-12-24 07:59:06 -080013972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013973 struct intel_crtc_state *old_intel_state =
13974 to_intel_crtc_state(old_crtc_state);
13975 bool modeset = needs_modeset(crtc->state);
Gustavo Padovanccc759dc2014-09-24 14:20:22 -030013976
Matt Roperc34c9ee2014-12-23 10:41:50 -080013977 /* Perform vblank evasion around commit operation */
Maarten Lankhorst62852622015-09-23 16:29:38 +020013978 intel_pipe_update_start(intel_crtc);
Maarten Lankhorst05832362015-06-15 12:33:48 +020013979
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +020013980 if (modeset)
13981 return;
13982
13983 if (to_intel_crtc_state(crtc->state)->update_pipe)
13984 intel_update_pipe_config(intel_crtc, old_intel_state);
13985 else if (INTEL_INFO(dev)->gen >= 9)
Maarten Lankhorst05832362015-06-15 12:33:48 +020013986 skl_detach_scalers(intel_crtc);
Matt Roper32b7eee2014-12-24 07:59:06 -080013987}
13988
Maarten Lankhorst613d2b22015-07-21 13:28:58 +020013989static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13990 struct drm_crtc_state *old_crtc_state)
Matt Roper32b7eee2014-12-24 07:59:06 -080013991{
Matt Roper32b7eee2014-12-24 07:59:06 -080013992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roper32b7eee2014-12-24 07:59:06 -080013993
Maarten Lankhorst62852622015-09-23 16:29:38 +020013994 intel_pipe_update_end(intel_crtc);
Gustavo Padovan3c692a42014-09-05 17:04:49 -030013995}
13996
Matt Ropercf4c7c12014-12-04 10:27:42 -080013997/**
Matt Roper4a3b8762014-12-23 10:41:51 -080013998 * intel_plane_destroy - destroy a plane
13999 * @plane: plane to destroy
Matt Ropercf4c7c12014-12-04 10:27:42 -080014000 *
Matt Roper4a3b8762014-12-23 10:41:51 -080014001 * Common destruction function for all types of planes (primary, cursor,
14002 * sprite).
Matt Ropercf4c7c12014-12-04 10:27:42 -080014003 */
Matt Roper4a3b8762014-12-23 10:41:51 -080014004void intel_plane_destroy(struct drm_plane *plane)
Matt Roper465c1202014-05-29 08:06:54 -070014005{
14006 struct intel_plane *intel_plane = to_intel_plane(plane);
14007 drm_plane_cleanup(plane);
14008 kfree(intel_plane);
14009}
14010
Matt Roper65a3fea2015-01-21 16:35:42 -080014011const struct drm_plane_funcs intel_plane_funcs = {
Matt Roper70a101f2015-04-08 18:56:53 -070014012 .update_plane = drm_atomic_helper_update_plane,
14013 .disable_plane = drm_atomic_helper_disable_plane,
Matt Roper3d7d6512014-06-10 08:28:13 -070014014 .destroy = intel_plane_destroy,
Matt Roperc196e1d2015-01-21 16:35:48 -080014015 .set_property = drm_atomic_helper_plane_set_property,
Matt Ropera98b3432015-01-21 16:35:43 -080014016 .atomic_get_property = intel_plane_atomic_get_property,
14017 .atomic_set_property = intel_plane_atomic_set_property,
Matt Roperea2c67b2014-12-23 10:41:52 -080014018 .atomic_duplicate_state = intel_plane_duplicate_state,
14019 .atomic_destroy_state = intel_plane_destroy_state,
14020
Matt Roper465c1202014-05-29 08:06:54 -070014021};
14022
14023static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14024 int pipe)
14025{
14026 struct intel_plane *primary;
Matt Roper8e7d6882015-01-21 16:35:41 -080014027 struct intel_plane_state *state;
Matt Roper465c1202014-05-29 08:06:54 -070014028 const uint32_t *intel_primary_formats;
Thierry Reding45e37432015-08-12 16:54:28 +020014029 unsigned int num_formats;
Matt Roper465c1202014-05-29 08:06:54 -070014030
14031 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14032 if (primary == NULL)
14033 return NULL;
14034
Matt Roper8e7d6882015-01-21 16:35:41 -080014035 state = intel_create_plane_state(&primary->base);
14036 if (!state) {
Matt Roperea2c67b2014-12-23 10:41:52 -080014037 kfree(primary);
14038 return NULL;
14039 }
Matt Roper8e7d6882015-01-21 16:35:41 -080014040 primary->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080014041
Matt Roper465c1202014-05-29 08:06:54 -070014042 primary->can_scale = false;
14043 primary->max_downscale = 1;
Chandra Konduru6156a452015-04-27 13:48:39 -070014044 if (INTEL_INFO(dev)->gen >= 9) {
14045 primary->can_scale = true;
Chandra Konduruaf99ced2015-05-11 14:35:47 -070014046 state->scaler_id = -1;
Chandra Konduru6156a452015-04-27 13:48:39 -070014047 }
Matt Roper465c1202014-05-29 08:06:54 -070014048 primary->pipe = pipe;
14049 primary->plane = pipe;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030014050 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
Matt Roperc59cb172014-12-01 15:40:16 -080014051 primary->check_plane = intel_check_primary_plane;
14052 primary->commit_plane = intel_commit_primary_plane;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030014053 primary->disable_plane = intel_disable_primary_plane;
Matt Roper465c1202014-05-29 08:06:54 -070014054 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14055 primary->plane = !pipe;
14056
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014057 if (INTEL_INFO(dev)->gen >= 9) {
14058 intel_primary_formats = skl_primary_formats;
14059 num_formats = ARRAY_SIZE(skl_primary_formats);
14060 } else if (INTEL_INFO(dev)->gen >= 4) {
Damien Lespiau568db4f2015-05-12 16:13:18 +010014061 intel_primary_formats = i965_primary_formats;
14062 num_formats = ARRAY_SIZE(i965_primary_formats);
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014063 } else {
14064 intel_primary_formats = i8xx_primary_formats;
14065 num_formats = ARRAY_SIZE(i8xx_primary_formats);
Matt Roper465c1202014-05-29 08:06:54 -070014066 }
14067
14068 drm_universal_plane_init(dev, &primary->base, 0,
Matt Roper65a3fea2015-01-21 16:35:42 -080014069 &intel_plane_funcs,
Matt Roper465c1202014-05-29 08:06:54 -070014070 intel_primary_formats, num_formats,
14071 DRM_PLANE_TYPE_PRIMARY);
Sonika Jindal48404c12014-08-22 14:06:04 +053014072
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014073 if (INTEL_INFO(dev)->gen >= 4)
14074 intel_create_rotation_property(dev, primary);
Sonika Jindal48404c12014-08-22 14:06:04 +053014075
Matt Roperea2c67b2014-12-23 10:41:52 -080014076 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14077
Matt Roper465c1202014-05-29 08:06:54 -070014078 return &primary->base;
14079}
14080
Sonika Jindal3b7a5112015-04-10 14:37:29 +053014081void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14082{
14083 if (!dev->mode_config.rotation_property) {
14084 unsigned long flags = BIT(DRM_ROTATE_0) |
14085 BIT(DRM_ROTATE_180);
14086
14087 if (INTEL_INFO(dev)->gen >= 9)
14088 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14089
14090 dev->mode_config.rotation_property =
14091 drm_mode_create_rotation_property(dev, flags);
14092 }
14093 if (dev->mode_config.rotation_property)
14094 drm_object_attach_property(&plane->base.base,
14095 dev->mode_config.rotation_property,
14096 plane->base.state->rotation);
14097}
14098
Matt Roper3d7d6512014-06-10 08:28:13 -070014099static int
Gustavo Padovan852e7872014-09-05 17:22:31 -030014100intel_check_cursor_plane(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014101 struct intel_crtc_state *crtc_state,
Gustavo Padovan852e7872014-09-05 17:22:31 -030014102 struct intel_plane_state *state)
Matt Roper3d7d6512014-06-10 08:28:13 -070014103{
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014104 struct drm_crtc *crtc = crtc_state->base.crtc;
Matt Roper2b875c22014-12-01 15:40:13 -080014105 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014106 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
Ville Syrjäläb29ec922015-12-18 19:24:39 +020014107 enum pipe pipe = to_intel_plane(plane)->pipe;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014108 unsigned stride;
14109 int ret;
Gustavo Padovan852e7872014-09-05 17:22:31 -030014110
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014111 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14112 &state->dst, &state->clip,
Gustavo Padovan852e7872014-09-05 17:22:31 -030014113 DRM_PLANE_HELPER_NO_SCALING,
14114 DRM_PLANE_HELPER_NO_SCALING,
14115 true, true, &state->visible);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014116 if (ret)
14117 return ret;
14118
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014119 /* if we want to turn off the cursor ignore width and height */
14120 if (!obj)
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020014121 return 0;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014122
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014123 /* Check for which cursor types we support */
Maarten Lankhorst061e4b82015-06-15 12:33:46 +020014124 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
Matt Roperea2c67b2014-12-23 10:41:52 -080014125 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14126 state->base.crtc_w, state->base.crtc_h);
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014127 return -EINVAL;
14128 }
14129
Matt Roperea2c67b2014-12-23 10:41:52 -080014130 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14131 if (obj->base.size < stride * state->base.crtc_h) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014132 DRM_DEBUG_KMS("buffer is too small\n");
14133 return -ENOMEM;
14134 }
14135
Ville Syrjälä3a656b52015-03-09 21:08:37 +020014136 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014137 DRM_DEBUG_KMS("cursor cannot be tiled\n");
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020014138 return -EINVAL;
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014139 }
Gustavo Padovan757f9a32014-09-24 14:20:24 -030014140
Ville Syrjäläb29ec922015-12-18 19:24:39 +020014141 /*
14142 * There's something wrong with the cursor on CHV pipe C.
14143 * If it straddles the left edge of the screen then
14144 * moving it away from the edge or disabling it often
14145 * results in a pipe underrun, and often that can lead to
14146 * dead pipe (constant underrun reported, and it scans
14147 * out just a solid color). To recover from that, the
14148 * display power well must be turned off and on again.
14149 * Refuse the put the cursor into that compromised position.
14150 */
14151 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14152 state->visible && state->base.crtc_x < 0) {
14153 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14154 return -EINVAL;
14155 }
14156
Maarten Lankhorstda20eab2015-06-15 12:33:44 +020014157 return 0;
Gustavo Padovan852e7872014-09-05 17:22:31 -030014158}
14159
Matt Roperf4a2cf22014-12-01 15:40:12 -080014160static void
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030014161intel_disable_cursor_plane(struct drm_plane *plane,
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +020014162 struct drm_crtc *crtc)
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030014163{
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030014164 intel_crtc_update_cursor(crtc, false);
14165}
14166
14167static void
Gustavo Padovan852e7872014-09-05 17:22:31 -030014168intel_commit_cursor_plane(struct drm_plane *plane,
14169 struct intel_plane_state *state)
14170{
Matt Roper2b875c22014-12-01 15:40:13 -080014171 struct drm_crtc *crtc = state->base.crtc;
Matt Roperea2c67b2014-12-23 10:41:52 -080014172 struct drm_device *dev = plane->dev;
14173 struct intel_crtc *intel_crtc;
Matt Roper2b875c22014-12-01 15:40:13 -080014174 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
Gustavo Padovana912f122014-12-01 15:40:10 -080014175 uint32_t addr;
Matt Roper3d7d6512014-06-10 08:28:13 -070014176
Matt Roperea2c67b2014-12-23 10:41:52 -080014177 crtc = crtc ? crtc : plane->crtc;
14178 intel_crtc = to_intel_crtc(crtc);
Sonika Jindala919db92014-10-23 07:41:33 -070014179
Matt Roperf4a2cf22014-12-01 15:40:12 -080014180 if (!obj)
Gustavo Padovana912f122014-12-01 15:40:10 -080014181 addr = 0;
Matt Roperf4a2cf22014-12-01 15:40:12 -080014182 else if (!INTEL_INFO(dev)->cursor_needs_physical)
Gustavo Padovana912f122014-12-01 15:40:10 -080014183 addr = i915_gem_obj_ggtt_offset(obj);
Matt Roperf4a2cf22014-12-01 15:40:12 -080014184 else
Gustavo Padovana912f122014-12-01 15:40:10 -080014185 addr = obj->phys_handle->busaddr;
Gustavo Padovana912f122014-12-01 15:40:10 -080014186
Gustavo Padovana912f122014-12-01 15:40:10 -080014187 intel_crtc->cursor_addr = addr;
Gustavo Padovana912f122014-12-01 15:40:10 -080014188
Maarten Lankhorst62852622015-09-23 16:29:38 +020014189 intel_crtc_update_cursor(crtc, state->visible);
Matt Roper3d7d6512014-06-10 08:28:13 -070014190}
Gustavo Padovan852e7872014-09-05 17:22:31 -030014191
Matt Roper3d7d6512014-06-10 08:28:13 -070014192static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14193 int pipe)
14194{
14195 struct intel_plane *cursor;
Matt Roper8e7d6882015-01-21 16:35:41 -080014196 struct intel_plane_state *state;
Matt Roper3d7d6512014-06-10 08:28:13 -070014197
14198 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14199 if (cursor == NULL)
14200 return NULL;
14201
Matt Roper8e7d6882015-01-21 16:35:41 -080014202 state = intel_create_plane_state(&cursor->base);
14203 if (!state) {
Matt Roperea2c67b2014-12-23 10:41:52 -080014204 kfree(cursor);
14205 return NULL;
14206 }
Matt Roper8e7d6882015-01-21 16:35:41 -080014207 cursor->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -080014208
Matt Roper3d7d6512014-06-10 08:28:13 -070014209 cursor->can_scale = false;
14210 cursor->max_downscale = 1;
14211 cursor->pipe = pipe;
14212 cursor->plane = pipe;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +030014213 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
Matt Roperc59cb172014-12-01 15:40:16 -080014214 cursor->check_plane = intel_check_cursor_plane;
14215 cursor->commit_plane = intel_commit_cursor_plane;
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +030014216 cursor->disable_plane = intel_disable_cursor_plane;
Matt Roper3d7d6512014-06-10 08:28:13 -070014217
14218 drm_universal_plane_init(dev, &cursor->base, 0,
Matt Roper65a3fea2015-01-21 16:35:42 -080014219 &intel_plane_funcs,
Matt Roper3d7d6512014-06-10 08:28:13 -070014220 intel_cursor_formats,
14221 ARRAY_SIZE(intel_cursor_formats),
14222 DRM_PLANE_TYPE_CURSOR);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070014223
14224 if (INTEL_INFO(dev)->gen >= 4) {
14225 if (!dev->mode_config.rotation_property)
14226 dev->mode_config.rotation_property =
14227 drm_mode_create_rotation_property(dev,
14228 BIT(DRM_ROTATE_0) |
14229 BIT(DRM_ROTATE_180));
14230 if (dev->mode_config.rotation_property)
14231 drm_object_attach_property(&cursor->base.base,
14232 dev->mode_config.rotation_property,
Matt Roper8e7d6882015-01-21 16:35:41 -080014233 state->base.rotation);
Ville Syrjälä4398ad42014-10-23 07:41:34 -070014234 }
14235
Chandra Konduruaf99ced2015-05-11 14:35:47 -070014236 if (INTEL_INFO(dev)->gen >=9)
14237 state->scaler_id = -1;
14238
Matt Roperea2c67b2014-12-23 10:41:52 -080014239 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14240
Matt Roper3d7d6512014-06-10 08:28:13 -070014241 return &cursor->base;
14242}
14243
Chandra Konduru549e2bf2015-04-07 15:28:38 -070014244static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14245 struct intel_crtc_state *crtc_state)
14246{
14247 int i;
14248 struct intel_scaler *intel_scaler;
14249 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14250
14251 for (i = 0; i < intel_crtc->num_scalers; i++) {
14252 intel_scaler = &scaler_state->scalers[i];
14253 intel_scaler->in_use = 0;
Chandra Konduru549e2bf2015-04-07 15:28:38 -070014254 intel_scaler->mode = PS_SCALER_MODE_DYN;
14255 }
14256
14257 scaler_state->scaler_id = -1;
14258}
14259
Hannes Ederb358d0a2008-12-18 21:18:47 +010014260static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080014261{
Jani Nikulafbee40d2014-03-31 14:27:18 +030014262 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080014263 struct intel_crtc *intel_crtc;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020014264 struct intel_crtc_state *crtc_state = NULL;
Matt Roper3d7d6512014-06-10 08:28:13 -070014265 struct drm_plane *primary = NULL;
14266 struct drm_plane *cursor = NULL;
Matt Roper465c1202014-05-29 08:06:54 -070014267 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080014268
Daniel Vetter955382f2013-09-19 14:05:45 +020014269 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080014270 if (intel_crtc == NULL)
14271 return;
14272
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020014273 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14274 if (!crtc_state)
14275 goto fail;
Ander Conselvan de Oliveira550acef2015-04-21 17:13:24 +030014276 intel_crtc->config = crtc_state;
14277 intel_crtc->base.state = &crtc_state->base;
Matt Roper07878242015-02-25 11:43:26 -080014278 crtc_state->base.crtc = &intel_crtc->base;
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020014279
Chandra Konduru549e2bf2015-04-07 15:28:38 -070014280 /* initialize shared scalers */
14281 if (INTEL_INFO(dev)->gen >= 9) {
14282 if (pipe == PIPE_C)
14283 intel_crtc->num_scalers = 1;
14284 else
14285 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14286
14287 skl_init_scalers(dev, intel_crtc, crtc_state);
14288 }
14289
Matt Roper465c1202014-05-29 08:06:54 -070014290 primary = intel_primary_plane_create(dev, pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070014291 if (!primary)
14292 goto fail;
14293
14294 cursor = intel_cursor_plane_create(dev, pipe);
14295 if (!cursor)
14296 goto fail;
14297
Matt Roper465c1202014-05-29 08:06:54 -070014298 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
Matt Roper3d7d6512014-06-10 08:28:13 -070014299 cursor, &intel_crtc_funcs);
14300 if (ret)
14301 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -080014302
14303 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080014304 for (i = 0; i < 256; i++) {
14305 intel_crtc->lut_r[i] = i;
14306 intel_crtc->lut_g[i] = i;
14307 intel_crtc->lut_b[i] = i;
14308 }
14309
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020014310 /*
14311 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
Daniel Vetter8c0f92e2014-06-16 02:08:26 +020014312 * is hooked to pipe B. Hence we want plane A feeding pipe B.
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020014313 */
Jesse Barnes80824002009-09-10 15:28:06 -070014314 intel_crtc->pipe = pipe;
14315 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010014316 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080014317 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010014318 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070014319 }
14320
Chris Wilson4b0e3332014-05-30 16:35:26 +030014321 intel_crtc->cursor_base = ~0;
14322 intel_crtc->cursor_cntl = ~0;
Ville Syrjälädc41c152014-08-13 11:57:05 +030014323 intel_crtc->cursor_size = ~0;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030014324
Ville Syrjälä852eb002015-06-24 22:00:07 +030014325 intel_crtc->wm.cxsr_allowed = true;
14326
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080014327 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14328 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14329 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14330 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14331
Jesse Barnes79e53942008-11-07 14:24:08 -080014332 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Daniel Vetter87b6b102014-05-15 15:33:46 +020014333
14334 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
Matt Roper3d7d6512014-06-10 08:28:13 -070014335 return;
14336
14337fail:
14338 if (primary)
14339 drm_plane_cleanup(primary);
14340 if (cursor)
14341 drm_plane_cleanup(cursor);
Ander Conselvan de Oliveiraf5de6e02015-01-15 14:55:26 +020014342 kfree(crtc_state);
Matt Roper3d7d6512014-06-10 08:28:13 -070014343 kfree(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080014344}
14345
Jesse Barnes752aa882013-10-31 18:55:49 +020014346enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14347{
14348 struct drm_encoder *encoder = connector->base.encoder;
Daniel Vetter6e9f7982014-05-29 23:54:47 +020014349 struct drm_device *dev = connector->base.dev;
Jesse Barnes752aa882013-10-31 18:55:49 +020014350
Rob Clark51fd3712013-11-19 12:10:12 -050014351 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Jesse Barnes752aa882013-10-31 18:55:49 +020014352
Ville Syrjäläd3babd32014-11-07 11:16:01 +020014353 if (!encoder || WARN_ON(!encoder->crtc))
Jesse Barnes752aa882013-10-31 18:55:49 +020014354 return INVALID_PIPE;
14355
14356 return to_intel_crtc(encoder->crtc)->pipe;
14357}
14358
Carl Worth08d7b3d2009-04-29 14:43:54 -070014359int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000014360 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070014361{
Carl Worth08d7b3d2009-04-29 14:43:54 -070014362 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Rob Clark7707e652014-07-17 23:30:04 -040014363 struct drm_crtc *drmmode_crtc;
Daniel Vetterc05422d2009-08-11 16:05:30 +020014364 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070014365
Rob Clark7707e652014-07-17 23:30:04 -040014366 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
Carl Worth08d7b3d2009-04-29 14:43:54 -070014367
Rob Clark7707e652014-07-17 23:30:04 -040014368 if (!drmmode_crtc) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070014369 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030014370 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070014371 }
14372
Rob Clark7707e652014-07-17 23:30:04 -040014373 crtc = to_intel_crtc(drmmode_crtc);
Daniel Vetterc05422d2009-08-11 16:05:30 +020014374 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070014375
Daniel Vetterc05422d2009-08-11 16:05:30 +020014376 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070014377}
14378
Daniel Vetter66a92782012-07-12 20:08:18 +020014379static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080014380{
Daniel Vetter66a92782012-07-12 20:08:18 +020014381 struct drm_device *dev = encoder->base.dev;
14382 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080014383 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080014384 int entry = 0;
14385
Damien Lespiaub2784e12014-08-05 11:29:37 +010014386 for_each_intel_encoder(dev, source_encoder) {
Ville Syrjäläbc079e82014-03-03 16:15:28 +020014387 if (encoders_cloneable(encoder, source_encoder))
Daniel Vetter66a92782012-07-12 20:08:18 +020014388 index_mask |= (1 << entry);
14389
Jesse Barnes79e53942008-11-07 14:24:08 -080014390 entry++;
14391 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010014392
Jesse Barnes79e53942008-11-07 14:24:08 -080014393 return index_mask;
14394}
14395
Chris Wilson4d302442010-12-14 19:21:29 +000014396static bool has_edp_a(struct drm_device *dev)
14397{
14398 struct drm_i915_private *dev_priv = dev->dev_private;
14399
14400 if (!IS_MOBILE(dev))
14401 return false;
14402
14403 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14404 return false;
14405
Damien Lespiaue3589902014-02-07 19:12:50 +000014406 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
Chris Wilson4d302442010-12-14 19:21:29 +000014407 return false;
14408
14409 return true;
14410}
14411
Jesse Barnes84b4e042014-06-25 08:24:29 -070014412static bool intel_crt_present(struct drm_device *dev)
14413{
14414 struct drm_i915_private *dev_priv = dev->dev_private;
14415
Damien Lespiau884497e2013-12-03 13:56:23 +000014416 if (INTEL_INFO(dev)->gen >= 9)
14417 return false;
14418
Damien Lespiaucf404ce2014-10-01 20:04:15 +010014419 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
Jesse Barnes84b4e042014-06-25 08:24:29 -070014420 return false;
14421
14422 if (IS_CHERRYVIEW(dev))
14423 return false;
14424
Ville Syrjälä65e472e2015-12-01 23:28:55 +020014425 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14426 return false;
14427
Ville Syrjälä70ac54d2015-12-01 23:29:56 +020014428 /* DDI E can't be used if DDI A requires 4 lanes */
14429 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14430 return false;
14431
Ville Syrjäläe4abb732015-12-01 23:31:33 +020014432 if (!dev_priv->vbt.int_crt_support)
Jesse Barnes84b4e042014-06-25 08:24:29 -070014433 return false;
14434
14435 return true;
14436}
14437
Jesse Barnes79e53942008-11-07 14:24:08 -080014438static void intel_setup_outputs(struct drm_device *dev)
14439{
Eric Anholt725e30a2009-01-22 13:01:02 -080014440 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010014441 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040014442 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080014443
Daniel Vetterc9093352013-06-06 22:22:47 +020014444 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080014445
Jesse Barnes84b4e042014-06-25 08:24:29 -070014446 if (intel_crt_present(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020014447 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040014448
Vandana Kannanc776eb22014-08-19 12:05:01 +053014449 if (IS_BROXTON(dev)) {
14450 /*
14451 * FIXME: Broxton doesn't support port detection via the
14452 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14453 * detect the ports.
14454 */
14455 intel_ddi_init(dev, PORT_A);
14456 intel_ddi_init(dev, PORT_B);
14457 intel_ddi_init(dev, PORT_C);
14458 } else if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030014459 int found;
14460
Jesse Barnesde31fac2015-03-06 15:53:32 -080014461 /*
14462 * Haswell uses DDI functions to detect digital outputs.
14463 * On SKL pre-D0 the strap isn't connected, so we assume
14464 * it's there.
14465 */
Ville Syrjälä77179402015-09-18 20:03:35 +030014466 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
Jesse Barnesde31fac2015-03-06 15:53:32 -080014467 /* WaIgnoreDDIAStrap: skl */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070014468 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030014469 intel_ddi_init(dev, PORT_A);
14470
14471 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14472 * register */
14473 found = I915_READ(SFUSE_STRAP);
14474
14475 if (found & SFUSE_STRAP_DDIB_DETECTED)
14476 intel_ddi_init(dev, PORT_B);
14477 if (found & SFUSE_STRAP_DDIC_DETECTED)
14478 intel_ddi_init(dev, PORT_C);
14479 if (found & SFUSE_STRAP_DDID_DETECTED)
14480 intel_ddi_init(dev, PORT_D);
Rodrigo Vivi2800e4c2015-08-07 17:35:21 -070014481 /*
14482 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14483 */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070014484 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
Rodrigo Vivi2800e4c2015-08-07 17:35:21 -070014485 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14486 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14487 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14488 intel_ddi_init(dev, PORT_E);
14489
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030014490 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040014491 int found;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +020014492 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
Daniel Vetter270b3042012-10-27 15:52:05 +020014493
14494 if (has_edp_a(dev))
14495 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040014496
Paulo Zanonidc0fa712013-02-19 16:21:46 -030014497 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080014498 /* PCH SDVOB multiplex with HDMIB */
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020014499 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080014500 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030014501 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080014502 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014503 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080014504 }
14505
Paulo Zanonidc0fa712013-02-19 16:21:46 -030014506 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030014507 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080014508
Paulo Zanonidc0fa712013-02-19 16:21:46 -030014509 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030014510 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080014511
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080014512 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014513 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080014514
Daniel Vetter270b3042012-10-27 15:52:05 +020014515 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014516 intel_dp_init(dev, PCH_DP_D, PORT_D);
Wayne Boyer666a4532015-12-09 12:29:35 -080014517 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030014518 /*
14519 * The DP_DETECTED bit is the latched state of the DDC
14520 * SDA pin at boot. However since eDP doesn't require DDC
14521 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14522 * eDP ports may have been muxed to an alternate function.
14523 * Thus we can't rely on the DP_DETECTED bit alone to detect
14524 * eDP ports. Consult the VBT as well as DP_DETECTED to
14525 * detect eDP ports.
14526 */
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014527 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
Ville Syrjäläd2182a62015-01-09 14:21:14 +020014528 !intel_dp_is_edp(dev, PORT_B))
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014529 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14530 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030014531 intel_dp_is_edp(dev, PORT_B))
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014532 intel_dp_init(dev, VLV_DP_B, PORT_B);
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030014533
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014534 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
Ville Syrjäläd2182a62015-01-09 14:21:14 +020014535 !intel_dp_is_edp(dev, PORT_C))
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014536 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14537 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030014538 intel_dp_is_edp(dev, PORT_C))
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014539 intel_dp_init(dev, VLV_DP_C, PORT_C);
Gajanan Bhat19c03922012-09-27 19:13:07 +053014540
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030014541 if (IS_CHERRYVIEW(dev)) {
Ville Syrjäläe17ac6d2014-10-09 19:37:15 +030014542 /* eDP not supported on port D, so don't check VBT */
Ville Syrjäläe66eb812015-09-18 20:03:34 +030014543 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14544 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14545 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14546 intel_dp_init(dev, CHV_DP_D, PORT_D);
Ville Syrjälä9418c1f2014-04-09 13:28:56 +030014547 }
14548
Jani Nikula3cfca972013-08-27 15:12:26 +030014549 intel_dsi_init(dev);
Daniel Vetter09da55d2015-07-07 11:44:32 +020014550 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080014551 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080014552
Paulo Zanonie2debe92013-02-18 19:00:27 -030014553 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014554 DRM_DEBUG_KMS("probing SDVOB\n");
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020014555 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
Daniel Vetter3fec3d22015-07-07 09:10:07 +020014556 if (!found && IS_G4X(dev)) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014557 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030014558 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014559 }
Ma Ling27185ae2009-08-24 13:50:23 +080014560
Daniel Vetter3fec3d22015-07-07 09:10:07 +020014561 if (!found && IS_G4X(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014562 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080014563 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040014564
14565 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040014566
Paulo Zanonie2debe92013-02-18 19:00:27 -030014567 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014568 DRM_DEBUG_KMS("probing SDVOC\n");
Ville Syrjälä2a5c0832015-11-06 21:29:59 +020014569 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014570 }
Ma Ling27185ae2009-08-24 13:50:23 +080014571
Paulo Zanonie2debe92013-02-18 19:00:27 -030014572 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080014573
Daniel Vetter3fec3d22015-07-07 09:10:07 +020014574 if (IS_G4X(dev)) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014575 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030014576 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080014577 }
Daniel Vetter3fec3d22015-07-07 09:10:07 +020014578 if (IS_G4X(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014579 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080014580 }
Ma Ling27185ae2009-08-24 13:50:23 +080014581
Daniel Vetter3fec3d22015-07-07 09:10:07 +020014582 if (IS_G4X(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030014583 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030014584 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070014585 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080014586 intel_dvo_init(dev);
14587
Zhenyu Wang103a1962009-11-27 11:44:36 +080014588 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080014589 intel_tv_init(dev);
14590
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -080014591 intel_psr_init(dev);
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -070014592
Damien Lespiaub2784e12014-08-05 11:29:37 +010014593 for_each_intel_encoder(dev, encoder) {
Chris Wilson4ef69c72010-09-09 15:14:28 +010014594 encoder->base.possible_crtcs = encoder->crtc_mask;
14595 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020014596 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080014597 }
Chris Wilson47356eb2011-01-11 17:06:04 +000014598
Paulo Zanonidde86e22012-12-01 12:04:25 -020014599 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020014600
14601 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080014602}
14603
14604static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14605{
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030014606 struct drm_device *dev = fb->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -080014607 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080014608
Daniel Vetteref2d6332014-02-10 18:00:38 +010014609 drm_framebuffer_cleanup(fb);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030014610 mutex_lock(&dev->struct_mutex);
Daniel Vetteref2d6332014-02-10 18:00:38 +010014611 WARN_ON(!intel_fb->obj->framebuffer_references--);
Ville Syrjälä60a5ca02014-06-13 11:10:53 +030014612 drm_gem_object_unreference(&intel_fb->obj->base);
14613 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080014614 kfree(intel_fb);
14615}
14616
14617static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000014618 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080014619 unsigned int *handle)
14620{
14621 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000014622 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080014623
Chris Wilsoncc917ab2015-10-13 14:22:26 +010014624 if (obj->userptr.mm) {
14625 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14626 return -EINVAL;
14627 }
14628
Chris Wilson05394f32010-11-08 19:18:58 +000014629 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080014630}
14631
Rodrigo Vivi86c98582015-07-08 16:22:45 -070014632static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14633 struct drm_file *file,
14634 unsigned flags, unsigned color,
14635 struct drm_clip_rect *clips,
14636 unsigned num_clips)
14637{
14638 struct drm_device *dev = fb->dev;
14639 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14640 struct drm_i915_gem_object *obj = intel_fb->obj;
14641
14642 mutex_lock(&dev->struct_mutex);
Paulo Zanoni74b4ea12015-07-14 16:29:14 -030014643 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
Rodrigo Vivi86c98582015-07-08 16:22:45 -070014644 mutex_unlock(&dev->struct_mutex);
14645
14646 return 0;
14647}
14648
Jesse Barnes79e53942008-11-07 14:24:08 -080014649static const struct drm_framebuffer_funcs intel_fb_funcs = {
14650 .destroy = intel_user_framebuffer_destroy,
14651 .create_handle = intel_user_framebuffer_create_handle,
Rodrigo Vivi86c98582015-07-08 16:22:45 -070014652 .dirty = intel_user_framebuffer_dirty,
Jesse Barnes79e53942008-11-07 14:24:08 -080014653};
14654
Damien Lespiaub3218032015-02-27 11:15:18 +000014655static
14656u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14657 uint32_t pixel_format)
14658{
14659 u32 gen = INTEL_INFO(dev)->gen;
14660
14661 if (gen >= 9) {
14662 /* "The stride in bytes must not exceed the of the size of 8K
14663 * pixels and 32K bytes."
14664 */
14665 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
Wayne Boyer666a4532015-12-09 12:29:35 -080014666 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Damien Lespiaub3218032015-02-27 11:15:18 +000014667 return 32*1024;
14668 } else if (gen >= 4) {
14669 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14670 return 16*1024;
14671 else
14672 return 32*1024;
14673 } else if (gen >= 3) {
14674 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14675 return 8*1024;
14676 else
14677 return 16*1024;
14678 } else {
14679 /* XXX DSPC is limited to 4k tiled */
14680 return 8*1024;
14681 }
14682}
14683
Daniel Vetterb5ea6422014-03-02 21:18:00 +010014684static int intel_framebuffer_init(struct drm_device *dev,
14685 struct intel_framebuffer *intel_fb,
14686 struct drm_mode_fb_cmd2 *mode_cmd,
14687 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080014688{
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +000014689 unsigned int aligned_height;
Jesse Barnes79e53942008-11-07 14:24:08 -080014690 int ret;
Damien Lespiaub3218032015-02-27 11:15:18 +000014691 u32 pitch_limit, stride_alignment;
Jesse Barnes79e53942008-11-07 14:24:08 -080014692
Daniel Vetterdd4916c2013-10-09 21:23:51 +020014693 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14694
Daniel Vetter2a80ead2015-02-10 17:16:06 +000014695 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14696 /* Enforce that fb modifier and tiling mode match, but only for
14697 * X-tiled. This is needed for FBC. */
14698 if (!!(obj->tiling_mode == I915_TILING_X) !=
14699 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14700 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14701 return -EINVAL;
14702 }
14703 } else {
14704 if (obj->tiling_mode == I915_TILING_X)
14705 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14706 else if (obj->tiling_mode == I915_TILING_Y) {
14707 DRM_DEBUG("No Y tiling for legacy addfb\n");
14708 return -EINVAL;
14709 }
14710 }
14711
Tvrtko Ursulin9a8f0a12015-02-27 11:15:24 +000014712 /* Passed in modifier sanity checking. */
14713 switch (mode_cmd->modifier[0]) {
14714 case I915_FORMAT_MOD_Y_TILED:
14715 case I915_FORMAT_MOD_Yf_TILED:
14716 if (INTEL_INFO(dev)->gen < 9) {
14717 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14718 mode_cmd->modifier[0]);
14719 return -EINVAL;
14720 }
14721 case DRM_FORMAT_MOD_NONE:
14722 case I915_FORMAT_MOD_X_TILED:
14723 break;
14724 default:
Jesse Barnesc0f40422015-03-23 12:43:50 -070014725 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14726 mode_cmd->modifier[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010014727 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014728 }
Chris Wilson57cd6502010-08-08 12:34:44 +010014729
Damien Lespiaub3218032015-02-27 11:15:18 +000014730 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14731 mode_cmd->pixel_format);
14732 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14733 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14734 mode_cmd->pitches[0], stride_alignment);
Chris Wilson57cd6502010-08-08 12:34:44 +010014735 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014736 }
Chris Wilson57cd6502010-08-08 12:34:44 +010014737
Damien Lespiaub3218032015-02-27 11:15:18 +000014738 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14739 mode_cmd->pixel_format);
Chris Wilsona35cdaa2013-06-25 17:26:45 +010014740 if (mode_cmd->pitches[0] > pitch_limit) {
Damien Lespiaub3218032015-02-27 11:15:18 +000014741 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14742 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
Daniel Vetter2a80ead2015-02-10 17:16:06 +000014743 "tiled" : "linear",
Chris Wilsona35cdaa2013-06-25 17:26:45 +010014744 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020014745 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014746 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020014747
Daniel Vetter2a80ead2015-02-10 17:16:06 +000014748 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014749 mode_cmd->pitches[0] != obj->stride) {
14750 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14751 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020014752 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014753 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020014754
Ville Syrjälä57779d02012-10-31 17:50:14 +020014755 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080014756 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020014757 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020014758 case DRM_FORMAT_RGB565:
14759 case DRM_FORMAT_XRGB8888:
14760 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020014761 break;
14762 case DRM_FORMAT_XRGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014763 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000014764 DRM_DEBUG("unsupported pixel format: %s\n",
14765 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020014766 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014767 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020014768 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +020014769 case DRM_FORMAT_ABGR8888:
Wayne Boyer666a4532015-12-09 12:29:35 -080014770 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14771 INTEL_INFO(dev)->gen < 9) {
Damien Lespiau6c0fd452015-05-19 12:29:16 +010014772 DRM_DEBUG("unsupported pixel format: %s\n",
14773 drm_get_format_name(mode_cmd->pixel_format));
14774 return -EINVAL;
14775 }
14776 break;
14777 case DRM_FORMAT_XBGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020014778 case DRM_FORMAT_XRGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020014779 case DRM_FORMAT_XBGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014780 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000014781 DRM_DEBUG("unsupported pixel format: %s\n",
14782 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020014783 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014784 }
Jesse Barnesb5626742011-06-24 12:19:27 -070014785 break;
Damien Lespiau75312082015-05-15 19:06:01 +010014786 case DRM_FORMAT_ABGR2101010:
Wayne Boyer666a4532015-12-09 12:29:35 -080014787 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
Damien Lespiau75312082015-05-15 19:06:01 +010014788 DRM_DEBUG("unsupported pixel format: %s\n",
14789 drm_get_format_name(mode_cmd->pixel_format));
14790 return -EINVAL;
14791 }
14792 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020014793 case DRM_FORMAT_YUYV:
14794 case DRM_FORMAT_UYVY:
14795 case DRM_FORMAT_YVYU:
14796 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014797 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000014798 DRM_DEBUG("unsupported pixel format: %s\n",
14799 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020014800 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000014801 }
Chris Wilson57cd6502010-08-08 12:34:44 +010014802 break;
14803 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000014804 DRM_DEBUG("unsupported pixel format: %s\n",
14805 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010014806 return -EINVAL;
14807 }
14808
Ville Syrjälä90f9a332012-10-31 17:50:19 +020014809 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14810 if (mode_cmd->offsets[0] != 0)
14811 return -EINVAL;
14812
Damien Lespiauec2c9812015-01-20 12:51:45 +000014813 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
Daniel Vetter091df6c2015-02-10 17:16:10 +000014814 mode_cmd->pixel_format,
14815 mode_cmd->modifier[0]);
Daniel Vetter53155c02013-10-09 21:55:33 +020014816 /* FIXME drm helper for size checks (especially planar formats)? */
14817 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14818 return -EINVAL;
14819
Daniel Vetterc7d73f62012-12-13 23:38:38 +010014820 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14821 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020014822 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010014823
Jesse Barnes79e53942008-11-07 14:24:08 -080014824 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14825 if (ret) {
14826 DRM_ERROR("framebuffer init failed %d\n", ret);
14827 return ret;
14828 }
14829
Jesse Barnes79e53942008-11-07 14:24:08 -080014830 return 0;
14831}
14832
Jesse Barnes79e53942008-11-07 14:24:08 -080014833static struct drm_framebuffer *
14834intel_user_framebuffer_create(struct drm_device *dev,
14835 struct drm_file *filp,
Ville Syrjälä1eb83452015-11-11 19:11:29 +020014836 const struct drm_mode_fb_cmd2 *user_mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080014837{
Lukas Wunnerdcb13942015-07-04 11:50:58 +020014838 struct drm_framebuffer *fb;
Chris Wilson05394f32010-11-08 19:18:58 +000014839 struct drm_i915_gem_object *obj;
Ville Syrjälä76dc3762015-11-11 19:11:28 +020014840 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
Jesse Barnes79e53942008-11-07 14:24:08 -080014841
Jesse Barnes308e5bc2011-11-14 14:51:28 -080014842 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
Ville Syrjälä76dc3762015-11-11 19:11:28 +020014843 mode_cmd.handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000014844 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010014845 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080014846
Daniel Vetter92907cb2015-11-23 09:04:05 +010014847 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
Lukas Wunnerdcb13942015-07-04 11:50:58 +020014848 if (IS_ERR(fb))
14849 drm_gem_object_unreference_unlocked(&obj->base);
14850
14851 return fb;
Jesse Barnes79e53942008-11-07 14:24:08 -080014852}
14853
Daniel Vetter06957262015-08-10 13:34:08 +020014854#ifndef CONFIG_DRM_FBDEV_EMULATION
Daniel Vetter0632fef2013-10-08 17:44:49 +020014855static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020014856{
14857}
14858#endif
14859
Jesse Barnes79e53942008-11-07 14:24:08 -080014860static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080014861 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020014862 .output_poll_changed = intel_fbdev_output_poll_changed,
Matt Roper5ee67f12015-01-21 16:35:44 -080014863 .atomic_check = intel_atomic_check,
14864 .atomic_commit = intel_atomic_commit,
Maarten Lankhorstde419ab2015-06-04 10:21:28 +020014865 .atomic_state_alloc = intel_atomic_state_alloc,
14866 .atomic_state_clear = intel_atomic_state_clear,
Jesse Barnes79e53942008-11-07 14:24:08 -080014867};
14868
Jesse Barnese70236a2009-09-21 10:42:27 -070014869/* Set up chip specific display functions */
14870static void intel_init_display(struct drm_device *dev)
14871{
14872 struct drm_i915_private *dev_priv = dev->dev_private;
14873
Daniel Vetteree9300b2013-06-03 22:40:22 +020014874 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14875 dev_priv->display.find_dpll = g4x_find_best_dpll;
Chon Ming Leeef9348c2014-04-09 13:28:18 +030014876 else if (IS_CHERRYVIEW(dev))
14877 dev_priv->display.find_dpll = chv_find_best_dpll;
Daniel Vetteree9300b2013-06-03 22:40:22 +020014878 else if (IS_VALLEYVIEW(dev))
14879 dev_priv->display.find_dpll = vlv_find_best_dpll;
14880 else if (IS_PINEVIEW(dev))
14881 dev_priv->display.find_dpll = pnv_find_best_dpll;
14882 else
14883 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14884
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014885 if (INTEL_INFO(dev)->gen >= 9) {
14886 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014887 dev_priv->display.get_initial_plane_config =
14888 skylake_get_initial_plane_config;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014889 dev_priv->display.crtc_compute_clock =
14890 haswell_crtc_compute_clock;
14891 dev_priv->display.crtc_enable = haswell_crtc_enable;
14892 dev_priv->display.crtc_disable = haswell_crtc_disable;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014893 dev_priv->display.update_primary_plane =
14894 skylake_update_primary_plane;
14895 } else if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014896 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014897 dev_priv->display.get_initial_plane_config =
14898 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira797d0252014-10-29 11:32:34 +020014899 dev_priv->display.crtc_compute_clock =
14900 haswell_crtc_compute_clock;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020014901 dev_priv->display.crtc_enable = haswell_crtc_enable;
14902 dev_priv->display.crtc_disable = haswell_crtc_disable;
Damien Lespiaubc8d7df2015-01-20 12:51:51 +000014903 dev_priv->display.update_primary_plane =
14904 ironlake_update_primary_plane;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030014905 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014906 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014907 dev_priv->display.get_initial_plane_config =
14908 ironlake_get_initial_plane_config;
Ander Conselvan de Oliveira3fb37702014-10-29 11:32:35 +020014909 dev_priv->display.crtc_compute_clock =
14910 ironlake_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020014911 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14912 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Matt Roper262ca2b2014-03-18 17:22:55 -070014913 dev_priv->display.update_primary_plane =
14914 ironlake_update_primary_plane;
Wayne Boyer666a4532015-12-09 12:29:35 -080014915 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Jesse Barnes89b667f2013-04-18 14:51:36 -070014916 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014917 dev_priv->display.get_initial_plane_config =
14918 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020014919 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Jesse Barnes89b667f2013-04-18 14:51:36 -070014920 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14921 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Matt Roper262ca2b2014-03-18 17:22:55 -070014922 dev_priv->display.update_primary_plane =
14923 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070014924 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010014925 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Damien Lespiau5724dbd2015-01-20 12:51:52 +000014926 dev_priv->display.get_initial_plane_config =
14927 i9xx_get_initial_plane_config;
Ander Conselvan de Oliveirad6dfee72014-10-29 11:32:36 +020014928 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
Daniel Vetter76e5a892012-06-29 22:39:33 +020014929 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14930 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Matt Roper262ca2b2014-03-18 17:22:55 -070014931 dev_priv->display.update_primary_plane =
14932 i9xx_update_primary_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070014933 }
Jesse Barnese70236a2009-09-21 10:42:27 -070014934
Jesse Barnese70236a2009-09-21 10:42:27 -070014935 /* Returns the core display clock speed */
Rodrigo Vivief11bdb2015-10-28 04:16:45 -070014936 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Ville Syrjälä1652d192015-03-31 14:12:01 +030014937 dev_priv->display.get_display_clock_speed =
14938 skylake_get_display_clock_speed;
Bob Paauweacd3f3d2015-06-23 14:14:26 -070014939 else if (IS_BROXTON(dev))
14940 dev_priv->display.get_display_clock_speed =
14941 broxton_get_display_clock_speed;
Ville Syrjälä1652d192015-03-31 14:12:01 +030014942 else if (IS_BROADWELL(dev))
14943 dev_priv->display.get_display_clock_speed =
14944 broadwell_get_display_clock_speed;
14945 else if (IS_HASWELL(dev))
14946 dev_priv->display.get_display_clock_speed =
14947 haswell_get_display_clock_speed;
Wayne Boyer666a4532015-12-09 12:29:35 -080014948 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070014949 dev_priv->display.get_display_clock_speed =
14950 valleyview_get_display_clock_speed;
Ville Syrjäläb37a6432015-03-31 14:11:54 +030014951 else if (IS_GEN5(dev))
14952 dev_priv->display.get_display_clock_speed =
14953 ilk_get_display_clock_speed;
Ville Syrjäläa7c66cd2015-03-31 14:11:56 +030014954 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
Ville Syrjälä34edce22015-05-22 11:22:33 +030014955 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070014956 dev_priv->display.get_display_clock_speed =
14957 i945_get_display_clock_speed;
Ville Syrjälä34edce22015-05-22 11:22:33 +030014958 else if (IS_GM45(dev))
14959 dev_priv->display.get_display_clock_speed =
14960 gm45_get_display_clock_speed;
14961 else if (IS_CRESTLINE(dev))
14962 dev_priv->display.get_display_clock_speed =
14963 i965gm_get_display_clock_speed;
14964 else if (IS_PINEVIEW(dev))
14965 dev_priv->display.get_display_clock_speed =
14966 pnv_get_display_clock_speed;
14967 else if (IS_G33(dev) || IS_G4X(dev))
14968 dev_priv->display.get_display_clock_speed =
14969 g33_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070014970 else if (IS_I915G(dev))
14971 dev_priv->display.get_display_clock_speed =
14972 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020014973 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070014974 dev_priv->display.get_display_clock_speed =
14975 i9xx_misc_get_display_clock_speed;
14976 else if (IS_I915GM(dev))
14977 dev_priv->display.get_display_clock_speed =
14978 i915gm_get_display_clock_speed;
14979 else if (IS_I865G(dev))
14980 dev_priv->display.get_display_clock_speed =
14981 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020014982 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070014983 dev_priv->display.get_display_clock_speed =
Ville Syrjälä1b1d2712015-05-22 11:22:31 +030014984 i85x_get_display_clock_speed;
Ville Syrjälä623e01e2015-05-22 11:22:34 +030014985 else { /* 830 */
14986 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
Jesse Barnese70236a2009-09-21 10:42:27 -070014987 dev_priv->display.get_display_clock_speed =
14988 i830_get_display_clock_speed;
Ville Syrjälä623e01e2015-05-22 11:22:34 +030014989 }
Jesse Barnese70236a2009-09-21 10:42:27 -070014990
Jani Nikula7c10a2b2014-10-27 16:26:43 +020014991 if (IS_GEN5(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014992 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014993 } else if (IS_GEN6(dev)) {
14994 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014995 } else if (IS_IVYBRIDGE(dev)) {
14996 /* FIXME: detect B0+ stepping and use auto training */
14997 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Paulo Zanoni059b2fe2014-09-02 16:53:57 -030014998 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Sonika Jindal3bb11b52014-08-11 09:06:39 +053014999 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015000 if (IS_BROADWELL(dev)) {
15001 dev_priv->display.modeset_commit_cdclk =
15002 broadwell_modeset_commit_cdclk;
15003 dev_priv->display.modeset_calc_cdclk =
15004 broadwell_modeset_calc_cdclk;
15005 }
Wayne Boyer666a4532015-12-09 12:29:35 -080015006 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015007 dev_priv->display.modeset_commit_cdclk =
15008 valleyview_modeset_commit_cdclk;
15009 dev_priv->display.modeset_calc_cdclk =
15010 valleyview_modeset_calc_cdclk;
Vandana Kannanf8437dd12014-11-24 13:37:39 +053015011 } else if (IS_BROXTON(dev)) {
Maarten Lankhorst27c329e2015-06-15 12:33:56 +020015012 dev_priv->display.modeset_commit_cdclk =
15013 broxton_modeset_commit_cdclk;
15014 dev_priv->display.modeset_calc_cdclk =
15015 broxton_modeset_calc_cdclk;
Jesse Barnese70236a2009-09-21 10:42:27 -070015016 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070015017
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070015018 switch (INTEL_INFO(dev)->gen) {
15019 case 2:
15020 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15021 break;
15022
15023 case 3:
15024 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15025 break;
15026
15027 case 4:
15028 case 5:
15029 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15030 break;
15031
15032 case 6:
15033 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15034 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070015035 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070015036 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070015037 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15038 break;
Damien Lespiau830c81d2014-11-13 17:51:46 +000015039 case 9:
Tvrtko Ursulinba343e02015-02-10 17:16:12 +000015040 /* Drop through - unsupported since execlist only. */
15041 default:
15042 /* Default just returns -ENODEV to indicate unsupported */
15043 dev_priv->display.queue_flip = intel_default_queue_flip;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070015044 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020015045
Ville Syrjäläe39b9992014-09-04 14:53:14 +030015046 mutex_init(&dev_priv->pps_mutex);
Jesse Barnese70236a2009-09-21 10:42:27 -070015047}
15048
Jesse Barnesb690e962010-07-19 13:53:12 -070015049/*
15050 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15051 * resume, or other times. This quirk makes sure that's the case for
15052 * affected systems.
15053 */
Akshay Joshi0206e352011-08-16 15:34:10 -040015054static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070015055{
15056 struct drm_i915_private *dev_priv = dev->dev_private;
15057
15058 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020015059 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070015060}
15061
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030015062static void quirk_pipeb_force(struct drm_device *dev)
15063{
15064 struct drm_i915_private *dev_priv = dev->dev_private;
15065
15066 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15067 DRM_INFO("applying pipe b force quirk\n");
15068}
15069
Keith Packard435793d2011-07-12 14:56:22 -070015070/*
15071 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15072 */
15073static void quirk_ssc_force_disable(struct drm_device *dev)
15074{
15075 struct drm_i915_private *dev_priv = dev->dev_private;
15076 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020015077 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070015078}
15079
Carsten Emde4dca20e2012-03-15 15:56:26 +010015080/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010015081 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15082 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010015083 */
15084static void quirk_invert_brightness(struct drm_device *dev)
15085{
15086 struct drm_i915_private *dev_priv = dev->dev_private;
15087 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020015088 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070015089}
15090
Scot Doyle9c72cc62014-07-03 23:27:50 +000015091/* Some VBT's incorrectly indicate no backlight is present */
15092static void quirk_backlight_present(struct drm_device *dev)
15093{
15094 struct drm_i915_private *dev_priv = dev->dev_private;
15095 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15096 DRM_INFO("applying backlight present quirk\n");
15097}
15098
Jesse Barnesb690e962010-07-19 13:53:12 -070015099struct intel_quirk {
15100 int device;
15101 int subsystem_vendor;
15102 int subsystem_device;
15103 void (*hook)(struct drm_device *dev);
15104};
15105
Egbert Eich5f85f172012-10-14 15:46:38 +020015106/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15107struct intel_dmi_quirk {
15108 void (*hook)(struct drm_device *dev);
15109 const struct dmi_system_id (*dmi_id_list)[];
15110};
15111
15112static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15113{
15114 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15115 return 1;
15116}
15117
15118static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15119 {
15120 .dmi_id_list = &(const struct dmi_system_id[]) {
15121 {
15122 .callback = intel_dmi_reverse_brightness,
15123 .ident = "NCR Corporation",
15124 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15125 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15126 },
15127 },
15128 { } /* terminating entry */
15129 },
15130 .hook = quirk_invert_brightness,
15131 },
15132};
15133
Ben Widawskyc43b5632012-04-16 14:07:40 -070015134static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070015135 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15136 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15137
Jesse Barnesb690e962010-07-19 13:53:12 -070015138 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15139 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15140
Ville Syrjälä5f080c02014-08-15 01:22:06 +030015141 /* 830 needs to leave pipe A & dpll A up */
15142 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15143
Ville Syrjäläb6b5d042014-08-15 01:22:07 +030015144 /* 830 needs to leave pipe B & dpll B up */
15145 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15146
Keith Packard435793d2011-07-12 14:56:22 -070015147 /* Lenovo U160 cannot use SSC on LVDS */
15148 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020015149
15150 /* Sony Vaio Y cannot use SSC on LVDS */
15151 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010015152
Alexander van Heukelumbe505f62013-12-28 21:00:39 +010015153 /* Acer Aspire 5734Z must invert backlight brightness */
15154 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15155
15156 /* Acer/eMachines G725 */
15157 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15158
15159 /* Acer/eMachines e725 */
15160 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15161
15162 /* Acer/Packard Bell NCL20 */
15163 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15164
15165 /* Acer Aspire 4736Z */
15166 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
Jani Nikula0f540c32014-01-13 17:30:34 +020015167
15168 /* Acer Aspire 5336 */
15169 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
Scot Doyle2e93a1a2014-07-03 23:27:51 +000015170
15171 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15172 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
Scot Doyled4967d82014-07-03 23:27:52 +000015173
Scot Doyledfb3d47b2014-08-21 16:08:02 +000015174 /* Acer C720 Chromebook (Core i3 4005U) */
15175 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15176
jens steinb2a96012014-10-28 20:25:53 +010015177 /* Apple Macbook 2,1 (Core 2 T7400) */
15178 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15179
Jani Nikula1b9448b2015-11-05 11:49:59 +020015180 /* Apple Macbook 4,1 */
15181 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15182
Scot Doyled4967d82014-07-03 23:27:52 +000015183 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15184 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
Scot Doyle724cb062014-07-11 22:16:30 +000015185
15186 /* HP Chromebook 14 (Celeron 2955U) */
15187 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
Jani Nikulacf6f0af2015-02-19 10:53:39 +020015188
15189 /* Dell Chromebook 11 */
15190 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
Jani Nikula9be64ee2015-10-30 14:50:24 +020015191
15192 /* Dell Chromebook 11 (2015 version) */
15193 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
Jesse Barnesb690e962010-07-19 13:53:12 -070015194};
15195
15196static void intel_init_quirks(struct drm_device *dev)
15197{
15198 struct pci_dev *d = dev->pdev;
15199 int i;
15200
15201 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15202 struct intel_quirk *q = &intel_quirks[i];
15203
15204 if (d->device == q->device &&
15205 (d->subsystem_vendor == q->subsystem_vendor ||
15206 q->subsystem_vendor == PCI_ANY_ID) &&
15207 (d->subsystem_device == q->subsystem_device ||
15208 q->subsystem_device == PCI_ANY_ID))
15209 q->hook(dev);
15210 }
Egbert Eich5f85f172012-10-14 15:46:38 +020015211 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15212 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15213 intel_dmi_quirks[i].hook(dev);
15214 }
Jesse Barnesb690e962010-07-19 13:53:12 -070015215}
15216
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015217/* Disable the VGA plane that we never use */
15218static void i915_disable_vga(struct drm_device *dev)
15219{
15220 struct drm_i915_private *dev_priv = dev->dev_private;
15221 u8 sr1;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020015222 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015223
Ville Syrjälä2b37c612014-01-22 21:32:38 +020015224 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015225 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070015226 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015227 sr1 = inb(VGA_SR_DATA);
15228 outb(sr1 | 1<<5, VGA_SR_DATA);
15229 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15230 udelay(300);
15231
Ville Syrjälä01f5a622014-12-16 18:38:37 +020015232 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015233 POSTING_READ(vga_reg);
15234}
15235
Daniel Vetterf8175862012-04-10 15:50:11 +020015236void intel_modeset_init_hw(struct drm_device *dev)
15237{
Ville Syrjäläb6283052015-06-03 15:45:07 +030015238 intel_update_cdclk(dev);
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030015239 intel_prepare_ddi(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020015240 intel_init_clock_gating(dev);
Daniel Vetter8090c6b2012-06-24 16:42:32 +020015241 intel_enable_gt_powersave(dev);
Daniel Vetterf8175862012-04-10 15:50:11 +020015242}
15243
Jesse Barnes79e53942008-11-07 14:24:08 -080015244void intel_modeset_init(struct drm_device *dev)
15245{
Jesse Barnes652c3932009-08-17 13:31:43 -070015246 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau1fe47782014-03-03 17:31:47 +000015247 int sprite, ret;
Damien Lespiau8cc87b72014-03-03 17:31:44 +000015248 enum pipe pipe;
Jesse Barnes46f297f2014-03-07 08:57:48 -080015249 struct intel_crtc *crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -080015250
15251 drm_mode_config_init(dev);
15252
15253 dev->mode_config.min_width = 0;
15254 dev->mode_config.min_height = 0;
15255
Dave Airlie019d96c2011-09-29 16:20:42 +010015256 dev->mode_config.preferred_depth = 24;
15257 dev->mode_config.prefer_shadow = 1;
15258
Tvrtko Ursulin25bab382015-02-10 17:16:16 +000015259 dev->mode_config.allow_fb_modifiers = true;
15260
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020015261 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080015262
Jesse Barnesb690e962010-07-19 13:53:12 -070015263 intel_init_quirks(dev);
15264
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030015265 intel_init_pm(dev);
15266
Ben Widawskye3c74752013-04-05 13:12:39 -070015267 if (INTEL_INFO(dev)->num_pipes == 0)
15268 return;
15269
Lukas Wunner69f92f62015-07-15 13:57:35 +020015270 /*
15271 * There may be no VBT; and if the BIOS enabled SSC we can
15272 * just keep using it to avoid unnecessary flicker. Whereas if the
15273 * BIOS isn't using it, don't assume it will work even if the VBT
15274 * indicates as much.
15275 */
15276 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15277 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15278 DREF_SSC1_ENABLE);
15279
15280 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15281 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15282 bios_lvds_use_ssc ? "en" : "dis",
15283 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15284 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15285 }
15286 }
15287
Jesse Barnese70236a2009-09-21 10:42:27 -070015288 intel_init_display(dev);
Jani Nikula7c10a2b2014-10-27 16:26:43 +020015289 intel_init_audio(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070015290
Chris Wilsona6c45cf2010-09-17 00:32:17 +010015291 if (IS_GEN2(dev)) {
15292 dev->mode_config.max_width = 2048;
15293 dev->mode_config.max_height = 2048;
15294 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070015295 dev->mode_config.max_width = 4096;
15296 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080015297 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010015298 dev->mode_config.max_width = 8192;
15299 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080015300 }
Damien Lespiau068be562014-03-28 14:17:49 +000015301
Ville Syrjälädc41c152014-08-13 11:57:05 +030015302 if (IS_845G(dev) || IS_I865G(dev)) {
15303 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15304 dev->mode_config.cursor_height = 1023;
15305 } else if (IS_GEN2(dev)) {
Damien Lespiau068be562014-03-28 14:17:49 +000015306 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15307 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15308 } else {
15309 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15310 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15311 }
15312
Ben Widawsky5d4545a2013-01-17 12:45:15 -080015313 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080015314
Zhao Yakui28c97732009-10-09 11:39:41 +080015315 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070015316 INTEL_INFO(dev)->num_pipes,
15317 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080015318
Damien Lespiau055e3932014-08-18 13:49:10 +010015319 for_each_pipe(dev_priv, pipe) {
Damien Lespiau8cc87b72014-03-03 17:31:44 +000015320 intel_crtc_init(dev, pipe);
Damien Lespiau3bdcfc02015-02-28 14:54:09 +000015321 for_each_sprite(dev_priv, pipe, sprite) {
Damien Lespiau1fe47782014-03-03 17:31:47 +000015322 ret = intel_plane_init(dev, pipe, sprite);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070015323 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030015324 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
Damien Lespiau1fe47782014-03-03 17:31:47 +000015325 pipe_name(pipe), sprite_name(pipe, sprite), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070015326 }
Jesse Barnes79e53942008-11-07 14:24:08 -080015327 }
15328
Ville Syrjäläbfa7df02015-09-24 23:29:18 +030015329 intel_update_czclk(dev_priv);
15330 intel_update_cdclk(dev);
15331
Daniel Vettere72f9fb2013-06-05 13:34:06 +020015332 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010015333
Jesse Barnes9cce37f2010-08-13 15:11:26 -070015334 /* Just disable it once at startup */
15335 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080015336 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000015337
Daniel Vetter6e9f7982014-05-29 23:54:47 +020015338 drm_modeset_lock_all(dev);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015339 intel_modeset_setup_hw_state(dev);
Daniel Vetter6e9f7982014-05-29 23:54:47 +020015340 drm_modeset_unlock_all(dev);
Jesse Barnes46f297f2014-03-07 08:57:48 -080015341
Damien Lespiaud3fcc802014-05-13 23:32:22 +010015342 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorsteeebeac2015-07-14 12:33:29 +020015343 struct intel_initial_plane_config plane_config = {};
15344
Jesse Barnes46f297f2014-03-07 08:57:48 -080015345 if (!crtc->active)
15346 continue;
15347
Jesse Barnes46f297f2014-03-07 08:57:48 -080015348 /*
Jesse Barnes46f297f2014-03-07 08:57:48 -080015349 * Note that reserving the BIOS fb up front prevents us
15350 * from stuffing other stolen allocations like the ring
15351 * on top. This prevents some ugliness at boot time, and
15352 * can even allow for smooth boot transitions if the BIOS
15353 * fb is large enough for the active pipe configuration.
15354 */
Maarten Lankhorsteeebeac2015-07-14 12:33:29 +020015355 dev_priv->display.get_initial_plane_config(crtc,
15356 &plane_config);
15357
15358 /*
15359 * If the fb is shared between multiple heads, we'll
15360 * just get the first one.
15361 */
15362 intel_find_initial_plane_obj(crtc, &plane_config);
Jesse Barnes46f297f2014-03-07 08:57:48 -080015363 }
Chris Wilson2c7111d2011-03-29 10:40:27 +010015364}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080015365
Daniel Vetter7fad7982012-07-04 17:51:47 +020015366static void intel_enable_pipe_a(struct drm_device *dev)
15367{
15368 struct intel_connector *connector;
15369 struct drm_connector *crt = NULL;
15370 struct intel_load_detect_pipe load_detect_temp;
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030015371 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
Daniel Vetter7fad7982012-07-04 17:51:47 +020015372
15373 /* We can't just switch on the pipe A, we need to set things up with a
15374 * proper mode and output configuration. As a gross hack, enable pipe A
15375 * by enabling the load detect pipe once. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020015376 for_each_intel_connector(dev, connector) {
Daniel Vetter7fad7982012-07-04 17:51:47 +020015377 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15378 crt = &connector->base;
15379 break;
15380 }
15381 }
15382
15383 if (!crt)
15384 return;
15385
Ville Syrjälä208bf9f2014-08-11 13:15:35 +030015386 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +020015387 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
Daniel Vetter7fad7982012-07-04 17:51:47 +020015388}
15389
Daniel Vetterfa555832012-10-10 23:14:00 +020015390static bool
15391intel_check_plane_mapping(struct intel_crtc *crtc)
15392{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070015393 struct drm_device *dev = crtc->base.dev;
15394 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä649636e2015-09-22 19:50:01 +030015395 u32 val;
Daniel Vetterfa555832012-10-10 23:14:00 +020015396
Ben Widawsky7eb552a2013-03-13 14:05:41 -070015397 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020015398 return true;
15399
Ville Syrjälä649636e2015-09-22 19:50:01 +030015400 val = I915_READ(DSPCNTR(!crtc->plane));
Daniel Vetterfa555832012-10-10 23:14:00 +020015401
15402 if ((val & DISPLAY_PLANE_ENABLE) &&
15403 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15404 return false;
15405
15406 return true;
15407}
15408
Ville Syrjälä02e93c32015-08-26 19:39:19 +030015409static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15410{
15411 struct drm_device *dev = crtc->base.dev;
15412 struct intel_encoder *encoder;
15413
15414 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15415 return true;
15416
15417 return false;
15418}
15419
Daniel Vetter24929352012-07-02 20:28:59 +020015420static void intel_sanitize_crtc(struct intel_crtc *crtc)
15421{
15422 struct drm_device *dev = crtc->base.dev;
15423 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020015424 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020015425
Daniel Vetter24929352012-07-02 20:28:59 +020015426 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter24929352012-07-02 20:28:59 +020015427 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15428
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030015429 /* restore vblank interrupts to correct state */
Daniel Vetter96256042015-02-13 21:03:42 +010015430 drm_crtc_vblank_reset(&crtc->base);
Ville Syrjäläd297e102014-08-06 14:50:01 +030015431 if (crtc->active) {
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015432 struct intel_plane *plane;
15433
Daniel Vetter96256042015-02-13 21:03:42 +010015434 drm_crtc_vblank_on(&crtc->base);
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015435
15436 /* Disable everything but the primary plane */
15437 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15438 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15439 continue;
15440
15441 plane->disable_plane(&plane->base, &crtc->base);
15442 }
Daniel Vetter96256042015-02-13 21:03:42 +010015443 }
Ville Syrjäläd3eaf882014-05-20 17:20:05 +030015444
Daniel Vetter24929352012-07-02 20:28:59 +020015445 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020015446 * disable the crtc (and hence change the state) if it is wrong. Note
15447 * that gen4+ has a fixed plane -> pipe mapping. */
15448 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020015449 bool plane;
15450
Daniel Vetter24929352012-07-02 20:28:59 +020015451 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15452 crtc->base.base.id);
15453
15454 /* Pipe has the wrong plane attached and the plane is active.
15455 * Temporarily change the plane mapping and disable everything
15456 * ... */
15457 plane = crtc->plane;
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030015458 to_intel_plane_state(crtc->base.primary->state)->visible = true;
Daniel Vetter24929352012-07-02 20:28:59 +020015459 crtc->plane = !plane;
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +020015460 intel_crtc_disable_noatomic(&crtc->base);
Daniel Vetter24929352012-07-02 20:28:59 +020015461 crtc->plane = plane;
Daniel Vetter24929352012-07-02 20:28:59 +020015462 }
Daniel Vetter24929352012-07-02 20:28:59 +020015463
Daniel Vetter7fad7982012-07-04 17:51:47 +020015464 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15465 crtc->pipe == PIPE_A && !crtc->active) {
15466 /* BIOS forgot to enable pipe A, this mostly happens after
15467 * resume. Force-enable the pipe to fix this, the update_dpms
15468 * call below we restore the pipe to the right state, but leave
15469 * the required bits on. */
15470 intel_enable_pipe_a(dev);
15471 }
15472
Daniel Vetter24929352012-07-02 20:28:59 +020015473 /* Adjust the state of the output pipe according to whether we
15474 * have active connectors/encoders. */
Ville Syrjälä02e93c32015-08-26 19:39:19 +030015475 if (!intel_crtc_has_encoders(crtc))
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +020015476 intel_crtc_disable_noatomic(&crtc->base);
Daniel Vetter24929352012-07-02 20:28:59 +020015477
Maarten Lankhorst53d9f4e2015-06-01 12:49:52 +020015478 if (crtc->active != crtc->base.state->active) {
Ville Syrjälä02e93c32015-08-26 19:39:19 +030015479 struct intel_encoder *encoder;
Daniel Vetter24929352012-07-02 20:28:59 +020015480
15481 /* This can happen either due to bugs in the get_hw_state
Maarten Lankhorstb17d48e2015-06-12 11:15:39 +020015482 * functions or because of calls to intel_crtc_disable_noatomic,
15483 * or because the pipe is force-enabled due to the
Daniel Vetter24929352012-07-02 20:28:59 +020015484 * pipe A quirk. */
15485 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15486 crtc->base.base.id,
Matt Roper83d65732015-02-25 13:12:16 -080015487 crtc->base.state->enable ? "enabled" : "disabled",
Daniel Vetter24929352012-07-02 20:28:59 +020015488 crtc->active ? "enabled" : "disabled");
15489
Maarten Lankhorst4be40c92015-07-14 13:45:32 +020015490 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
Maarten Lankhorst49d6fa22015-05-11 10:45:15 +020015491 crtc->base.state->active = crtc->active;
Daniel Vetter24929352012-07-02 20:28:59 +020015492 crtc->base.enabled = crtc->active;
15493
15494 /* Because we only establish the connector -> encoder ->
15495 * crtc links if something is active, this means the
15496 * crtc is now deactivated. Break the links. connector
15497 * -> encoder links are only establish when things are
15498 * actually up, hence no need to break them. */
15499 WARN_ON(crtc->active);
15500
Maarten Lankhorst2d406bb2015-08-05 12:37:09 +020015501 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
Daniel Vetter24929352012-07-02 20:28:59 +020015502 encoder->base.crtc = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020015503 }
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020015504
Ville Syrjäläa3ed6aa2014-09-03 14:09:52 +030015505 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
Daniel Vetter4cc31482014-03-24 00:01:41 +010015506 /*
15507 * We start out with underrun reporting disabled to avoid races.
15508 * For correct bookkeeping mark this on active crtcs.
15509 *
Daniel Vetterc5ab3bc2014-05-14 15:40:34 +020015510 * Also on gmch platforms we dont have any hardware bits to
15511 * disable the underrun reporting. Which means we need to start
15512 * out with underrun reporting disabled also on inactive pipes,
15513 * since otherwise we'll complain about the garbage we read when
15514 * e.g. coming up after runtime pm.
15515 *
Daniel Vetter4cc31482014-03-24 00:01:41 +010015516 * No protection against concurrent access is required - at
15517 * worst a fifo underrun happens which also sets this to false.
15518 */
15519 crtc->cpu_fifo_underrun_disabled = true;
15520 crtc->pch_fifo_underrun_disabled = true;
15521 }
Daniel Vetter24929352012-07-02 20:28:59 +020015522}
15523
15524static void intel_sanitize_encoder(struct intel_encoder *encoder)
15525{
15526 struct intel_connector *connector;
15527 struct drm_device *dev = encoder->base.dev;
Maarten Lankhorst873ffe62015-08-05 12:37:07 +020015528 bool active = false;
Daniel Vetter24929352012-07-02 20:28:59 +020015529
15530 /* We need to check both for a crtc link (meaning that the
15531 * encoder is active and trying to read from a pipe) and the
15532 * pipe itself being active. */
15533 bool has_active_crtc = encoder->base.crtc &&
15534 to_intel_crtc(encoder->base.crtc)->active;
15535
Maarten Lankhorst873ffe62015-08-05 12:37:07 +020015536 for_each_intel_connector(dev, connector) {
15537 if (connector->base.encoder != &encoder->base)
15538 continue;
15539
15540 active = true;
15541 break;
15542 }
15543
15544 if (active && !has_active_crtc) {
Daniel Vetter24929352012-07-02 20:28:59 +020015545 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15546 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030015547 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020015548
15549 /* Connector is active, but has no active pipe. This is
15550 * fallout from our resume register restoring. Disable
15551 * the encoder manually again. */
15552 if (encoder->base.crtc) {
15553 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15554 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030015555 encoder->base.name);
Daniel Vetter24929352012-07-02 20:28:59 +020015556 encoder->disable(encoder);
Ville Syrjäläa62d1492014-06-28 02:04:01 +030015557 if (encoder->post_disable)
15558 encoder->post_disable(encoder);
Daniel Vetter24929352012-07-02 20:28:59 +020015559 }
Egbert Eich7f1950f2014-04-25 10:56:22 +020015560 encoder->base.crtc = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020015561
15562 /* Inconsistent output/port/pipe state happens presumably due to
15563 * a bug in one of the get_hw_state functions. Or someplace else
15564 * in our code, like the register restore mess on resume. Clamp
15565 * things to off as a safer default. */
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020015566 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020015567 if (connector->encoder != encoder)
15568 continue;
Egbert Eich7f1950f2014-04-25 10:56:22 +020015569 connector->base.dpms = DRM_MODE_DPMS_OFF;
15570 connector->base.encoder = NULL;
Daniel Vetter24929352012-07-02 20:28:59 +020015571 }
15572 }
15573 /* Enabled encoders without active connectors will be fixed in
15574 * the crtc fixup. */
15575}
15576
Imre Deak04098752014-02-18 00:02:16 +020015577void i915_redisable_vga_power_on(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010015578{
15579 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020015580 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010015581
Imre Deak04098752014-02-18 00:02:16 +020015582 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15583 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15584 i915_disable_vga(dev);
15585 }
15586}
15587
15588void i915_redisable_vga(struct drm_device *dev)
15589{
15590 struct drm_i915_private *dev_priv = dev->dev_private;
15591
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030015592 /* This function can be called both from intel_modeset_setup_hw_state or
15593 * at a very early point in our resume sequence, where the power well
15594 * structures are not yet restored. Since this function is at a very
15595 * paranoid "someone might have enabled VGA while we were not looking"
15596 * level, just check if the power well is enabled instead of trying to
15597 * follow the "don't touch the power well if we don't need it" policy
15598 * the rest of the driver uses. */
Daniel Vetterf458ebb2014-09-30 10:56:39 +020015599 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030015600 return;
15601
Imre Deak04098752014-02-18 00:02:16 +020015602 i915_redisable_vga_power_on(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010015603}
15604
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015605static bool primary_get_hw_state(struct intel_plane *plane)
Ville Syrjälä98ec7732014-04-30 17:43:01 +030015606{
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015607 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjälä98ec7732014-04-30 17:43:01 +030015608
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015609 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020015610}
Ville Syrjälä98ec7732014-04-30 17:43:01 +030015611
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015612/* FIXME read out full plane state for all planes */
15613static void readout_plane_state(struct intel_crtc *crtc)
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020015614{
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020015615 struct drm_plane *primary = crtc->base.primary;
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015616 struct intel_plane_state *plane_state =
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020015617 to_intel_plane_state(primary->state);
Maarten Lankhorstd032ffa2015-06-15 12:33:51 +020015618
Matt Roper19b8d382015-09-24 15:53:17 -070015619 plane_state->visible = crtc->active &&
Maarten Lankhorstb26d3ea2015-09-23 16:11:41 +020015620 primary_get_hw_state(to_intel_plane(primary));
15621
15622 if (plane_state->visible)
15623 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
Ville Syrjälä98ec7732014-04-30 17:43:01 +030015624}
15625
Daniel Vetter30e984d2013-06-05 13:34:17 +020015626static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020015627{
15628 struct drm_i915_private *dev_priv = dev->dev_private;
15629 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020015630 struct intel_crtc *crtc;
15631 struct intel_encoder *encoder;
15632 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020015633 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020015634
Maarten Lankhorst565602d2015-12-10 12:33:57 +010015635 dev_priv->active_crtcs = 0;
15636
Damien Lespiaud3fcc802014-05-13 23:32:22 +010015637 for_each_intel_crtc(dev, crtc) {
Maarten Lankhorst565602d2015-12-10 12:33:57 +010015638 struct intel_crtc_state *crtc_state = crtc->config;
15639 int pixclk = 0;
Daniel Vetter3b117c82013-04-17 20:15:07 +020015640
Maarten Lankhorst565602d2015-12-10 12:33:57 +010015641 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15642 memset(crtc_state, 0, sizeof(*crtc_state));
15643 crtc_state->base.crtc = &crtc->base;
Daniel Vetter24929352012-07-02 20:28:59 +020015644
Maarten Lankhorst565602d2015-12-10 12:33:57 +010015645 crtc_state->base.active = crtc_state->base.enable =
15646 dev_priv->display.get_pipe_config(crtc, crtc_state);
15647
15648 crtc->base.enabled = crtc_state->base.enable;
15649 crtc->active = crtc_state->base.active;
15650
15651 if (crtc_state->base.active) {
15652 dev_priv->active_crtcs |= 1 << crtc->pipe;
15653
15654 if (IS_BROADWELL(dev_priv)) {
15655 pixclk = ilk_pipe_pixel_rate(crtc_state);
15656
15657 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15658 if (crtc_state->ips_enabled)
15659 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15660 } else if (IS_VALLEYVIEW(dev_priv) ||
15661 IS_CHERRYVIEW(dev_priv) ||
15662 IS_BROXTON(dev_priv))
15663 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15664 else
15665 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15666 }
15667
15668 dev_priv->min_pixclk[crtc->pipe] = pixclk;
Maarten Lankhorstb70709a2015-04-21 17:12:53 +030015669
Ville Syrjäläf9cd7b82015-09-10 18:59:08 +030015670 readout_plane_state(crtc);
Daniel Vetter24929352012-07-02 20:28:59 +020015671
15672 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15673 crtc->base.base.id,
15674 crtc->active ? "enabled" : "disabled");
15675 }
15676
Daniel Vetter53589012013-06-05 13:34:16 +020015677 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15678 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15679
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020015680 pll->on = pll->get_hw_state(dev_priv, pll,
15681 &pll->config.hw_state);
Daniel Vetter53589012013-06-05 13:34:16 +020015682 pll->active = 0;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020015683 pll->config.crtc_mask = 0;
Damien Lespiaud3fcc802014-05-13 23:32:22 +010015684 for_each_intel_crtc(dev, crtc) {
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020015685 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
Daniel Vetter53589012013-06-05 13:34:16 +020015686 pll->active++;
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020015687 pll->config.crtc_mask |= 1 << crtc->pipe;
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020015688 }
Daniel Vetter53589012013-06-05 13:34:16 +020015689 }
Daniel Vetter53589012013-06-05 13:34:16 +020015690
Ander Conselvan de Oliveira1e6f2dd2014-10-29 11:32:31 +020015691 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020015692 pll->name, pll->config.crtc_mask, pll->on);
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030015693
Ander Conselvan de Oliveira3e369b72014-10-29 11:32:32 +020015694 if (pll->config.crtc_mask)
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -030015695 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
Daniel Vetter53589012013-06-05 13:34:16 +020015696 }
15697
Damien Lespiaub2784e12014-08-05 11:29:37 +010015698 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020015699 pipe = 0;
15700
15701 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070015702 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15703 encoder->base.crtc = &crtc->base;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020015704 encoder->get_config(encoder, crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020015705 } else {
15706 encoder->base.crtc = NULL;
15707 }
15708
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010015709 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020015710 encoder->base.base.id,
Jani Nikula8e329a032014-06-03 14:56:21 +030015711 encoder->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020015712 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010015713 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020015714 }
15715
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +020015716 for_each_intel_connector(dev, connector) {
Daniel Vetter24929352012-07-02 20:28:59 +020015717 if (connector->get_hw_state(connector)) {
15718 connector->base.dpms = DRM_MODE_DPMS_ON;
Daniel Vetter24929352012-07-02 20:28:59 +020015719 connector->base.encoder = &connector->encoder->base;
15720 } else {
15721 connector->base.dpms = DRM_MODE_DPMS_OFF;
15722 connector->base.encoder = NULL;
15723 }
15724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15725 connector->base.base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +030015726 connector->base.name,
Daniel Vetter24929352012-07-02 20:28:59 +020015727 connector->base.encoder ? "enabled" : "disabled");
15728 }
Ville Syrjälä7f4c6282015-09-10 18:59:07 +030015729
15730 for_each_intel_crtc(dev, crtc) {
15731 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15732
15733 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15734 if (crtc->base.state->active) {
15735 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15736 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15737 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15738
15739 /*
15740 * The initial mode needs to be set in order to keep
15741 * the atomic core happy. It wants a valid mode if the
15742 * crtc's enabled, so we do the above call.
15743 *
15744 * At this point some state updated by the connectors
15745 * in their ->detect() callback has not run yet, so
15746 * no recalculation can be done yet.
15747 *
15748 * Even if we could do a recalculation and modeset
15749 * right now it would cause a double modeset if
15750 * fbdev or userspace chooses a different initial mode.
15751 *
15752 * If that happens, someone indicated they wanted a
15753 * mode change, which means it's safe to do a full
15754 * recalculation.
15755 */
15756 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
Ville Syrjälä9eca68322015-09-10 18:59:10 +030015757
15758 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15759 update_scanline_offset(crtc);
Ville Syrjälä7f4c6282015-09-10 18:59:07 +030015760 }
15761 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020015762}
15763
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015764/* Scan out the current hw modeset state,
15765 * and sanitizes it to the current state
15766 */
15767static void
15768intel_modeset_setup_hw_state(struct drm_device *dev)
Daniel Vetter30e984d2013-06-05 13:34:17 +020015769{
15770 struct drm_i915_private *dev_priv = dev->dev_private;
15771 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020015772 struct intel_crtc *crtc;
15773 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020015774 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020015775
15776 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020015777
15778 /* HW state is read out, now we need to sanitize this mess. */
Damien Lespiaub2784e12014-08-05 11:29:37 +010015779 for_each_intel_encoder(dev, encoder) {
Daniel Vetter24929352012-07-02 20:28:59 +020015780 intel_sanitize_encoder(encoder);
15781 }
15782
Damien Lespiau055e3932014-08-18 13:49:10 +010015783 for_each_pipe(dev_priv, pipe) {
Daniel Vetter24929352012-07-02 20:28:59 +020015784 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15785 intel_sanitize_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +020015786 intel_dump_pipe_config(crtc, crtc->config,
15787 "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020015788 }
Daniel Vetter9a935852012-07-05 22:34:27 +020015789
Ander Conselvan de Oliveirad29b2f92015-03-20 16:18:05 +020015790 intel_modeset_update_connector_atomic_state(dev);
15791
Daniel Vetter35c95372013-07-17 06:55:04 +020015792 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15793 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15794
15795 if (!pll->on || pll->active)
15796 continue;
15797
15798 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15799
15800 pll->disable(dev_priv, pll);
15801 pll->on = false;
15802 }
15803
Wayne Boyer666a4532015-12-09 12:29:35 -080015804 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjälä6eb1a682015-06-24 22:00:03 +030015805 vlv_wm_get_hw_state(dev);
15806 else if (IS_GEN9(dev))
Pradeep Bhat30789992014-11-04 17:06:45 +000015807 skl_wm_get_hw_state(dev);
15808 else if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030015809 ilk_wm_get_hw_state(dev);
Maarten Lankhorst292b9902015-07-13 16:30:27 +020015810
15811 for_each_intel_crtc(dev, crtc) {
15812 unsigned long put_domains;
15813
15814 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15815 if (WARN_ON(put_domains))
15816 modeset_put_power_domains(dev_priv, put_domains);
15817 }
15818 intel_display_set_init_power(dev_priv, false);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015819}
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030015820
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015821void intel_display_resume(struct drm_device *dev)
15822{
15823 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15824 struct intel_connector *conn;
15825 struct intel_plane *plane;
15826 struct drm_crtc *crtc;
15827 int ret;
Daniel Vetterf30da182013-04-11 20:22:50 +020015828
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015829 if (!state)
15830 return;
15831
15832 state->acquire_ctx = dev->mode_config.acquire_ctx;
15833
15834 /* preserve complete old state, including dpll */
15835 intel_atomic_get_shared_dpll_state(state);
15836
15837 for_each_crtc(dev, crtc) {
15838 struct drm_crtc_state *crtc_state =
15839 drm_atomic_get_crtc_state(state, crtc);
15840
15841 ret = PTR_ERR_OR_ZERO(crtc_state);
15842 if (ret)
15843 goto err;
15844
15845 /* force a restore */
15846 crtc_state->mode_changed = true;
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010015847 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020015848
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015849 for_each_intel_plane(dev, plane) {
15850 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15851 if (ret)
15852 goto err;
15853 }
15854
15855 for_each_intel_connector(dev, conn) {
15856 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15857 if (ret)
15858 goto err;
15859 }
15860
15861 intel_modeset_setup_hw_state(dev);
15862
15863 i915_redisable_vga(dev);
Maarten Lankhorst74c090b2015-07-13 16:30:30 +020015864 ret = drm_atomic_commit(state);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +020015865 if (!ret)
15866 return;
15867
15868err:
15869 DRM_ERROR("Restoring old state failed with %i\n", ret);
15870 drm_atomic_state_free(state);
Chris Wilson2c7111d2011-03-29 10:40:27 +010015871}
15872
15873void intel_modeset_gem_init(struct drm_device *dev)
15874{
Jesse Barnes484b41d2014-03-07 08:57:55 -080015875 struct drm_crtc *c;
Matt Roper2ff8fde2014-07-08 07:50:07 -070015876 struct drm_i915_gem_object *obj;
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010015877 int ret;
Jesse Barnes484b41d2014-03-07 08:57:55 -080015878
Imre Deakae484342014-03-31 15:10:44 +030015879 mutex_lock(&dev->struct_mutex);
15880 intel_init_gt_powersave(dev);
15881 mutex_unlock(&dev->struct_mutex);
15882
Chris Wilson1833b132012-05-09 11:56:28 +010015883 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020015884
15885 intel_setup_overlay(dev);
Jesse Barnes484b41d2014-03-07 08:57:55 -080015886
15887 /*
15888 * Make sure any fbs we allocated at startup are properly
15889 * pinned & fenced. When we do the allocation it's too early
15890 * for this.
15891 */
Damien Lespiau70e1e0e2014-05-13 23:32:24 +010015892 for_each_crtc(dev, c) {
Matt Roper2ff8fde2014-07-08 07:50:07 -070015893 obj = intel_fb_obj(c->primary->fb);
15894 if (obj == NULL)
Jesse Barnes484b41d2014-03-07 08:57:55 -080015895 continue;
15896
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010015897 mutex_lock(&dev->struct_mutex);
15898 ret = intel_pin_and_fence_fb_obj(c->primary,
15899 c->primary->fb,
Maarten Lankhorst7580d772015-08-18 13:40:06 +020015900 c->primary->state);
Tvrtko Ursuline0d61492015-04-13 16:03:03 +010015901 mutex_unlock(&dev->struct_mutex);
15902 if (ret) {
Jesse Barnes484b41d2014-03-07 08:57:55 -080015903 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15904 to_intel_crtc(c)->pipe);
Dave Airlie66e514c2014-04-03 07:51:54 +100015905 drm_framebuffer_unreference(c->primary->fb);
15906 c->primary->fb = NULL;
Maarten Lankhorst36750f22015-06-01 12:49:54 +020015907 c->primary->crtc = c->primary->state->crtc = NULL;
Matt Roperafd65eb2015-02-03 13:10:04 -080015908 update_state_fb(c->primary);
Maarten Lankhorst36750f22015-06-01 12:49:54 +020015909 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
Jesse Barnes484b41d2014-03-07 08:57:55 -080015910 }
15911 }
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020015912
15913 intel_backlight_register(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080015914}
15915
Imre Deak4932e2c2014-02-11 17:12:48 +020015916void intel_connector_unregister(struct intel_connector *intel_connector)
15917{
15918 struct drm_connector *connector = &intel_connector->base;
15919
15920 intel_panel_destroy_backlight(connector);
Thomas Wood34ea3d32014-05-29 16:57:41 +010015921 drm_connector_unregister(connector);
Imre Deak4932e2c2014-02-11 17:12:48 +020015922}
15923
Jesse Barnes79e53942008-11-07 14:24:08 -080015924void intel_modeset_cleanup(struct drm_device *dev)
15925{
Jesse Barnes652c3932009-08-17 13:31:43 -070015926 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikula19c80542015-12-16 12:48:16 +020015927 struct intel_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070015928
Imre Deak2eb52522014-11-19 15:30:05 +020015929 intel_disable_gt_powersave(dev);
15930
Ville Syrjälä0962c3c2014-11-07 15:19:46 +020015931 intel_backlight_unregister(dev);
15932
Daniel Vetterfd0c0642013-04-24 11:13:35 +020015933 /*
15934 * Interrupts and polling as the first thing to avoid creating havoc.
Imre Deak2eb52522014-11-19 15:30:05 +020015935 * Too much stuff here (turning of connectors, ...) would
Daniel Vetterfd0c0642013-04-24 11:13:35 +020015936 * experience fancy races otherwise.
15937 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +020015938 intel_irq_uninstall(dev_priv);
Jesse Barneseb21b922014-06-20 11:57:33 -070015939
Daniel Vetterfd0c0642013-04-24 11:13:35 +020015940 /*
15941 * Due to the hpd irq storm handling the hotplug work can re-arm the
15942 * poll handlers. Hence disable polling after hpd handling is shut down.
15943 */
Keith Packardf87ea762010-10-03 19:36:26 -070015944 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020015945
Jesse Barnes723bfd72010-10-07 16:01:13 -070015946 intel_unregister_dsm_handler();
15947
Paulo Zanoni7733b492015-07-07 15:26:04 -030015948 intel_fbc_disable(dev_priv);
Kristian Høgsberg69341a52009-11-11 12:19:17 -050015949
Chris Wilson1630fe72011-07-08 12:22:42 +010015950 /* flush any delayed tasks or pending work */
15951 flush_scheduled_work();
15952
Jani Nikuladb31af1d2013-11-08 16:48:53 +020015953 /* destroy the backlight and sysfs files before encoders/connectors */
Jani Nikula19c80542015-12-16 12:48:16 +020015954 for_each_intel_connector(dev, connector)
15955 connector->unregister(connector);
Paulo Zanonid9255d52013-09-26 20:05:59 -030015956
Jesse Barnes79e53942008-11-07 14:24:08 -080015957 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010015958
15959 intel_cleanup_overlay(dev);
Imre Deakae484342014-03-31 15:10:44 +030015960
15961 mutex_lock(&dev->struct_mutex);
15962 intel_cleanup_gt_powersave(dev);
15963 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080015964}
15965
Dave Airlie28d52042009-09-21 14:33:58 +100015966/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080015967 * Return which encoder is currently attached for connector.
15968 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010015969struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080015970{
Chris Wilsondf0e9242010-09-09 16:20:55 +010015971 return &intel_attached_encoder(connector)->base;
15972}
Jesse Barnes79e53942008-11-07 14:24:08 -080015973
Chris Wilsondf0e9242010-09-09 16:20:55 +010015974void intel_connector_attach_encoder(struct intel_connector *connector,
15975 struct intel_encoder *encoder)
15976{
15977 connector->encoder = encoder;
15978 drm_mode_connector_attach_encoder(&connector->base,
15979 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080015980}
Dave Airlie28d52042009-09-21 14:33:58 +100015981
15982/*
15983 * set vga decode state - true == enable VGA decode
15984 */
15985int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15986{
15987 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona885b3c2013-12-17 14:34:50 +000015988 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
Dave Airlie28d52042009-09-21 14:33:58 +100015989 u16 gmch_ctrl;
15990
Chris Wilson75fa0412014-02-07 18:37:02 -020015991 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15992 DRM_ERROR("failed to read control word\n");
15993 return -EIO;
15994 }
15995
Chris Wilsonc0cc8a52014-02-07 18:37:03 -020015996 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15997 return 0;
15998
Dave Airlie28d52042009-09-21 14:33:58 +100015999 if (state)
16000 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16001 else
16002 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
Chris Wilson75fa0412014-02-07 18:37:02 -020016003
16004 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16005 DRM_ERROR("failed to write control word\n");
16006 return -EIO;
16007 }
16008
Dave Airlie28d52042009-09-21 14:33:58 +100016009 return 0;
16010}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016011
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016012struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030016013
16014 u32 power_well_driver;
16015
Chris Wilson63b66e52013-08-08 15:12:06 +020016016 int num_transcoders;
16017
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016018 struct intel_cursor_error_state {
16019 u32 control;
16020 u32 position;
16021 u32 base;
16022 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010016023 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016024
16025 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020016026 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016027 u32 source;
Imre Deakf301b1e2014-04-18 15:55:04 +030016028 u32 stat;
Damien Lespiau52331302012-08-15 19:23:25 +010016029 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016030
16031 struct intel_plane_error_state {
16032 u32 control;
16033 u32 stride;
16034 u32 size;
16035 u32 pos;
16036 u32 addr;
16037 u32 surface;
16038 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010016039 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020016040
16041 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020016042 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020016043 enum transcoder cpu_transcoder;
16044
16045 u32 conf;
16046
16047 u32 htotal;
16048 u32 hblank;
16049 u32 hsync;
16050 u32 vtotal;
16051 u32 vblank;
16052 u32 vsync;
16053 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016054};
16055
16056struct intel_display_error_state *
16057intel_display_capture_error_state(struct drm_device *dev)
16058{
Jani Nikulafbee40d2014-03-31 14:27:18 +030016059 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016060 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020016061 int transcoders[] = {
16062 TRANSCODER_A,
16063 TRANSCODER_B,
16064 TRANSCODER_C,
16065 TRANSCODER_EDP,
16066 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016067 int i;
16068
Chris Wilson63b66e52013-08-08 15:12:06 +020016069 if (INTEL_INFO(dev)->num_pipes == 0)
16070 return NULL;
16071
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020016072 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016073 if (error == NULL)
16074 return NULL;
16075
Imre Deak190be112013-11-25 17:15:31 +020016076 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030016077 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16078
Damien Lespiau055e3932014-08-18 13:49:10 +010016079 for_each_pipe(dev_priv, i) {
Imre Deakddf9c532013-11-27 22:02:02 +020016080 error->pipe[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020016081 __intel_display_power_is_enabled(dev_priv,
16082 POWER_DOMAIN_PIPE(i));
Imre Deakddf9c532013-11-27 22:02:02 +020016083 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020016084 continue;
16085
Ville Syrjälä5efb3e22014-04-09 13:28:53 +030016086 error->cursor[i].control = I915_READ(CURCNTR(i));
16087 error->cursor[i].position = I915_READ(CURPOS(i));
16088 error->cursor[i].base = I915_READ(CURBASE(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016089
16090 error->plane[i].control = I915_READ(DSPCNTR(i));
16091 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030016092 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030016093 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030016094 error->plane[i].pos = I915_READ(DSPPOS(i));
16095 }
Paulo Zanonica291362013-03-06 20:03:14 -030016096 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16097 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016098 if (INTEL_INFO(dev)->gen >= 4) {
16099 error->plane[i].surface = I915_READ(DSPSURF(i));
16100 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16101 }
16102
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016103 error->pipe[i].source = I915_READ(PIPESRC(i));
Imre Deakf301b1e2014-04-18 15:55:04 +030016104
Sonika Jindal3abfce72014-07-21 15:23:43 +053016105 if (HAS_GMCH_DISPLAY(dev))
Imre Deakf301b1e2014-04-18 15:55:04 +030016106 error->pipe[i].stat = I915_READ(PIPESTAT(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020016107 }
16108
16109 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16110 if (HAS_DDI(dev_priv->dev))
16111 error->num_transcoders++; /* Account for eDP. */
16112
16113 for (i = 0; i < error->num_transcoders; i++) {
16114 enum transcoder cpu_transcoder = transcoders[i];
16115
Imre Deakddf9c532013-11-27 22:02:02 +020016116 error->transcoder[i].power_domain_on =
Daniel Vetterf458ebb2014-09-30 10:56:39 +020016117 __intel_display_power_is_enabled(dev_priv,
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020016118 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020016119 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020016120 continue;
16121
Chris Wilson63b66e52013-08-08 15:12:06 +020016122 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16123
16124 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16125 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16126 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16127 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16128 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16129 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16130 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016131 }
16132
16133 return error;
16134}
16135
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016136#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16137
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016138void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016139intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016140 struct drm_device *dev,
16141 struct intel_display_error_state *error)
16142{
Damien Lespiau055e3932014-08-18 13:49:10 +010016143 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016144 int i;
16145
Chris Wilson63b66e52013-08-08 15:12:06 +020016146 if (!error)
16147 return;
16148
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016149 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020016150 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016151 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030016152 error->power_well_driver);
Damien Lespiau055e3932014-08-18 13:49:10 +010016153 for_each_pipe(dev_priv, i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016154 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020016155 err_printf(m, " Power: %s\n",
16156 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016157 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Imre Deakf301b1e2014-04-18 15:55:04 +030016158 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016159
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016160 err_printf(m, "Plane [%d]:\n", i);
16161 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16162 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030016163 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016164 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16165 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030016166 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030016167 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016168 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016169 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016170 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16171 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016172 }
16173
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030016174 err_printf(m, "Cursor [%d]:\n", i);
16175 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16176 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16177 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016178 }
Chris Wilson63b66e52013-08-08 15:12:06 +020016179
16180 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010016181 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020016182 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020016183 err_printf(m, " Power: %s\n",
16184 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020016185 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16186 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16187 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16188 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16189 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16190 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16191 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16192 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000016193}
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030016194
16195void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16196{
16197 struct intel_crtc *crtc;
16198
16199 for_each_intel_crtc(dev, crtc) {
16200 struct intel_unpin_work *work;
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030016201
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020016202 spin_lock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030016203
16204 work = crtc->unpin_work;
16205
16206 if (work && work->event &&
16207 work->event->base.file_priv == file) {
16208 kfree(work->event);
16209 work->event = NULL;
16210 }
16211
Daniel Vetter5e2d7af2014-09-15 14:55:22 +020016212 spin_unlock_irq(&dev->event_lock);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +030016213 }
16214}