Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/i915_drm.h> |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 33 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 34 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 35 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 36 | bool |
| 37 | intel_ring_initialized(struct intel_engine_cs *ring) |
| 38 | { |
| 39 | struct drm_device *dev = ring->dev; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 40 | |
Oscar Mateo | 48d8238 | 2014-07-24 17:04:23 +0100 | [diff] [blame] | 41 | if (!dev) |
| 42 | return false; |
| 43 | |
| 44 | if (i915.enable_execlists) { |
| 45 | struct intel_context *dctx = ring->default_context; |
| 46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; |
| 47 | |
| 48 | return ringbuf->obj; |
| 49 | } else |
| 50 | return ring->buffer && ring->buffer->obj; |
| 51 | } |
| 52 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 53 | int __intel_ring_space(int head, int tail, int size) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 54 | { |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 55 | int space = head - tail; |
| 56 | if (space <= 0) |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 57 | space += size; |
Dave Gordon | 4f54741 | 2014-11-27 11:22:48 +0000 | [diff] [blame] | 58 | return space - I915_RING_FREE_SPACE; |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 59 | } |
| 60 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
| 62 | { |
| 63 | if (ringbuf->last_retired_head != -1) { |
| 64 | ringbuf->head = ringbuf->last_retired_head; |
| 65 | ringbuf->last_retired_head = -1; |
| 66 | } |
| 67 | |
| 68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, |
| 69 | ringbuf->tail, ringbuf->size); |
| 70 | } |
| 71 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 73 | { |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 74 | intel_ring_update_space(ringbuf); |
| 75 | return ringbuf->space; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 76 | } |
| 77 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 79 | { |
| 80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
| 82 | } |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 83 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 84 | void __intel_ring_advance(struct intel_engine_cs *ring) |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 85 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 87 | ringbuf->tail &= ringbuf->size - 1; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 88 | if (intel_ring_stopped(ring)) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 89 | return; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 90 | ring->write_tail(ring, ringbuf->tail); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 93 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 94 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 95 | u32 invalidate_domains, |
| 96 | u32 flush_domains) |
| 97 | { |
| 98 | u32 cmd; |
| 99 | int ret; |
| 100 | |
| 101 | cmd = MI_FLUSH; |
Daniel Vetter | 31b14c9 | 2012-04-19 16:45:22 +0200 | [diff] [blame] | 102 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 103 | cmd |= MI_NO_WRITE_FLUSH; |
| 104 | |
| 105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 106 | cmd |= MI_READ_FLUSH; |
| 107 | |
| 108 | ret = intel_ring_begin(ring, 2); |
| 109 | if (ret) |
| 110 | return ret; |
| 111 | |
| 112 | intel_ring_emit(ring, cmd); |
| 113 | intel_ring_emit(ring, MI_NOOP); |
| 114 | intel_ring_advance(ring); |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 120 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 121 | u32 invalidate_domains, |
| 122 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 123 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 124 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 125 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 126 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 127 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 128 | /* |
| 129 | * read/write caches: |
| 130 | * |
| 131 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 132 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 133 | * also flushed at 2d versus 3d pipeline switches. |
| 134 | * |
| 135 | * read-only caches: |
| 136 | * |
| 137 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 138 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 139 | * |
| 140 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 141 | * |
| 142 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 143 | * invalidated when MI_EXE_FLUSH is set. |
| 144 | * |
| 145 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 146 | * invalidated with every MI_FLUSH. |
| 147 | * |
| 148 | * TLBs: |
| 149 | * |
| 150 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 151 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 152 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 153 | * are flushed at any MI_FLUSH. |
| 154 | */ |
| 155 | |
| 156 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 157 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 158 | cmd &= ~MI_NO_WRITE_FLUSH; |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 159 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 160 | cmd |= MI_EXE_FLUSH; |
| 161 | |
| 162 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 163 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 164 | cmd |= MI_INVALIDATE_ISP; |
| 165 | |
| 166 | ret = intel_ring_begin(ring, 2); |
| 167 | if (ret) |
| 168 | return ret; |
| 169 | |
| 170 | intel_ring_emit(ring, cmd); |
| 171 | intel_ring_emit(ring, MI_NOOP); |
| 172 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 173 | |
| 174 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 175 | } |
| 176 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 177 | /** |
| 178 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 179 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 180 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 181 | * |
| 182 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 183 | * produced by non-pipelined state commands), software needs to first |
| 184 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 185 | * 0. |
| 186 | * |
| 187 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 188 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 189 | * |
| 190 | * And the workaround for these two requires this workaround first: |
| 191 | * |
| 192 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 193 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 194 | * flushes. |
| 195 | * |
| 196 | * And this last workaround is tricky because of the requirements on |
| 197 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 198 | * volume 2 part 1: |
| 199 | * |
| 200 | * "1 of the following must also be set: |
| 201 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 202 | * - Depth Cache Flush Enable ([0] of DW1) |
| 203 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 204 | * - Depth Stall ([13] of DW1) |
| 205 | * - Post-Sync Operation ([13] of DW1) |
| 206 | * - Notify Enable ([8] of DW1)" |
| 207 | * |
| 208 | * The cache flushes require the workaround flush that triggered this |
| 209 | * one, so we can't use it. Depth stall would trigger the same. |
| 210 | * Post-sync nonzero is what triggered this second workaround, so we |
| 211 | * can't use that one either. Notify enable is IRQs, which aren't |
| 212 | * really our business. That leaves only stall at scoreboard. |
| 213 | */ |
| 214 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 215 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 216 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 217 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 218 | int ret; |
| 219 | |
| 220 | |
| 221 | ret = intel_ring_begin(ring, 6); |
| 222 | if (ret) |
| 223 | return ret; |
| 224 | |
| 225 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 226 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 227 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 228 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 229 | intel_ring_emit(ring, 0); /* low dword */ |
| 230 | intel_ring_emit(ring, 0); /* high dword */ |
| 231 | intel_ring_emit(ring, MI_NOOP); |
| 232 | intel_ring_advance(ring); |
| 233 | |
| 234 | ret = intel_ring_begin(ring, 6); |
| 235 | if (ret) |
| 236 | return ret; |
| 237 | |
| 238 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 239 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 240 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 241 | intel_ring_emit(ring, 0); |
| 242 | intel_ring_emit(ring, 0); |
| 243 | intel_ring_emit(ring, MI_NOOP); |
| 244 | intel_ring_advance(ring); |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 250 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 251 | u32 invalidate_domains, u32 flush_domains) |
| 252 | { |
| 253 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 254 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 255 | int ret; |
| 256 | |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 258 | ret = intel_emit_post_sync_nonzero_flush(ring); |
| 259 | if (ret) |
| 260 | return ret; |
| 261 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 262 | /* Just flush everything. Experiments have shown that reducing the |
| 263 | * number of bits based on the write domains has little performance |
| 264 | * impact. |
| 265 | */ |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 266 | if (flush_domains) { |
| 267 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 268 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 269 | /* |
| 270 | * Ensure that any following seqno writes only happen |
| 271 | * when the render cache is indeed flushed. |
| 272 | */ |
Daniel Vetter | 97f209b | 2012-06-28 09:48:42 +0200 | [diff] [blame] | 273 | flags |= PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 274 | } |
| 275 | if (invalidate_domains) { |
| 276 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 277 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 278 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 279 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 280 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 281 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 282 | /* |
| 283 | * TLB invalidate requires a post-sync write. |
| 284 | */ |
Jesse Barnes | 3ac7831 | 2012-10-25 12:15:47 -0700 | [diff] [blame] | 285 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
Chris Wilson | 7d54a90 | 2012-08-10 10:18:10 +0100 | [diff] [blame] | 286 | } |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 287 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 288 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 289 | if (ret) |
| 290 | return ret; |
| 291 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 292 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 293 | intel_ring_emit(ring, flags); |
| 294 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 295 | intel_ring_emit(ring, 0); |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 296 | intel_ring_advance(ring); |
| 297 | |
| 298 | return 0; |
| 299 | } |
| 300 | |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 301 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 302 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 303 | { |
| 304 | int ret; |
| 305 | |
| 306 | ret = intel_ring_begin(ring, 4); |
| 307 | if (ret) |
| 308 | return ret; |
| 309 | |
| 310 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 311 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 312 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 313 | intel_ring_emit(ring, 0); |
| 314 | intel_ring_emit(ring, 0); |
| 315 | intel_ring_advance(ring); |
| 316 | |
| 317 | return 0; |
| 318 | } |
| 319 | |
| 320 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 321 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 322 | u32 invalidate_domains, u32 flush_domains) |
| 323 | { |
| 324 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 325 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 326 | int ret; |
| 327 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 328 | /* |
| 329 | * Ensure that any following seqno writes only happen when the render |
| 330 | * cache is indeed flushed. |
| 331 | * |
| 332 | * Workaround: 4th PIPE_CONTROL command (except the ones with only |
| 333 | * read-cache invalidate bits set) must have the CS_STALL bit set. We |
| 334 | * don't try to be clever and just set it unconditionally. |
| 335 | */ |
| 336 | flags |= PIPE_CONTROL_CS_STALL; |
| 337 | |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 338 | /* Just flush everything. Experiments have shown that reducing the |
| 339 | * number of bits based on the write domains has little performance |
| 340 | * impact. |
| 341 | */ |
| 342 | if (flush_domains) { |
| 343 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 344 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 345 | } |
| 346 | if (invalidate_domains) { |
| 347 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 348 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 349 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 350 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 351 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 352 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
Chris Wilson | 148b83d | 2014-12-16 08:44:31 +0000 | [diff] [blame] | 353 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 354 | /* |
| 355 | * TLB invalidate requires a post-sync write. |
| 356 | */ |
| 357 | flags |= PIPE_CONTROL_QW_WRITE; |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 358 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 359 | |
Chris Wilson | add284a | 2014-12-16 08:44:32 +0000 | [diff] [blame] | 360 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
| 361 | |
Paulo Zanoni | f398763 | 2012-08-17 18:35:43 -0300 | [diff] [blame] | 362 | /* Workaround: we must issue a pipe_control with CS-stall bit |
| 363 | * set before a pipe_control command that has the state cache |
| 364 | * invalidate bit set. */ |
| 365 | gen7_render_ring_cs_stall_wa(ring); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | ret = intel_ring_begin(ring, 4); |
| 369 | if (ret) |
| 370 | return ret; |
| 371 | |
| 372 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
| 373 | intel_ring_emit(ring, flags); |
Ville Syrjälä | b9e1faa | 2013-02-14 21:53:51 +0200 | [diff] [blame] | 374 | intel_ring_emit(ring, scratch_addr); |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 375 | intel_ring_emit(ring, 0); |
| 376 | intel_ring_advance(ring); |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 381 | static int |
Kenneth Graunke | 884ceac | 2014-06-28 02:04:20 +0300 | [diff] [blame] | 382 | gen8_emit_pipe_control(struct intel_engine_cs *ring, |
| 383 | u32 flags, u32 scratch_addr) |
| 384 | { |
| 385 | int ret; |
| 386 | |
| 387 | ret = intel_ring_begin(ring, 6); |
| 388 | if (ret) |
| 389 | return ret; |
| 390 | |
| 391 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
| 392 | intel_ring_emit(ring, flags); |
| 393 | intel_ring_emit(ring, scratch_addr); |
| 394 | intel_ring_emit(ring, 0); |
| 395 | intel_ring_emit(ring, 0); |
| 396 | intel_ring_emit(ring, 0); |
| 397 | intel_ring_advance(ring); |
| 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 403 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 404 | u32 invalidate_domains, u32 flush_domains) |
| 405 | { |
| 406 | u32 flags = 0; |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 407 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 408 | int ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 409 | |
| 410 | flags |= PIPE_CONTROL_CS_STALL; |
| 411 | |
| 412 | if (flush_domains) { |
| 413 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 414 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 415 | } |
| 416 | if (invalidate_domains) { |
| 417 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
| 418 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 419 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 420 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 421 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 422 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 423 | flags |= PIPE_CONTROL_QW_WRITE; |
| 424 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
Kenneth Graunke | 02c9f7e | 2014-01-27 14:20:16 -0800 | [diff] [blame] | 425 | |
| 426 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ |
| 427 | ret = gen8_emit_pipe_control(ring, |
| 428 | PIPE_CONTROL_CS_STALL | |
| 429 | PIPE_CONTROL_STALL_AT_SCOREBOARD, |
| 430 | 0); |
| 431 | if (ret) |
| 432 | return ret; |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 433 | } |
| 434 | |
kbuild test robot | 6e0b3f8 | 2015-03-05 22:03:08 +0800 | [diff] [blame] | 435 | return gen8_emit_pipe_control(ring, flags, scratch_addr); |
Ben Widawsky | a5f3d68 | 2013-11-02 21:07:27 -0700 | [diff] [blame] | 436 | } |
| 437 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 438 | static void ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 439 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 440 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 441 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 442 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 443 | } |
| 444 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 445 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 446 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 447 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 448 | u64 acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 449 | |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 450 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 451 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), |
| 452 | RING_ACTHD_UDW(ring->mmio_base)); |
| 453 | else if (INTEL_INFO(ring->dev)->gen >= 4) |
| 454 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); |
| 455 | else |
| 456 | acthd = I915_READ(ACTHD); |
| 457 | |
| 458 | return acthd; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 459 | } |
| 460 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 461 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 462 | { |
| 463 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 464 | u32 addr; |
| 465 | |
| 466 | addr = dev_priv->status_page_dmah->busaddr; |
| 467 | if (INTEL_INFO(ring->dev)->gen >= 4) |
| 468 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
| 469 | I915_WRITE(HWS_PGA, addr); |
| 470 | } |
| 471 | |
Damien Lespiau | af75f26 | 2015-02-10 19:32:17 +0000 | [diff] [blame] | 472 | static void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
| 473 | { |
| 474 | struct drm_device *dev = ring->dev; |
| 475 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 476 | u32 mmio = 0; |
| 477 | |
| 478 | /* The ring status page addresses are no longer next to the rest of |
| 479 | * the ring registers as of gen7. |
| 480 | */ |
| 481 | if (IS_GEN7(dev)) { |
| 482 | switch (ring->id) { |
| 483 | case RCS: |
| 484 | mmio = RENDER_HWS_PGA_GEN7; |
| 485 | break; |
| 486 | case BCS: |
| 487 | mmio = BLT_HWS_PGA_GEN7; |
| 488 | break; |
| 489 | /* |
| 490 | * VCS2 actually doesn't exist on Gen7. Only shut up |
| 491 | * gcc switch check warning |
| 492 | */ |
| 493 | case VCS2: |
| 494 | case VCS: |
| 495 | mmio = BSD_HWS_PGA_GEN7; |
| 496 | break; |
| 497 | case VECS: |
| 498 | mmio = VEBOX_HWS_PGA_GEN7; |
| 499 | break; |
| 500 | } |
| 501 | } else if (IS_GEN6(ring->dev)) { |
| 502 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 503 | } else { |
| 504 | /* XXX: gen8 returns to sanity */ |
| 505 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 506 | } |
| 507 | |
| 508 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 509 | POSTING_READ(mmio); |
| 510 | |
| 511 | /* |
| 512 | * Flush the TLB for this page |
| 513 | * |
| 514 | * FIXME: These two bits have disappeared on gen8, so a question |
| 515 | * arises: do we still need this and if so how should we go about |
| 516 | * invalidating the TLB? |
| 517 | */ |
| 518 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { |
| 519 | u32 reg = RING_INSTPM(ring->mmio_base); |
| 520 | |
| 521 | /* ring should be idle before issuing a sync flush*/ |
| 522 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); |
| 523 | |
| 524 | I915_WRITE(reg, |
| 525 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | |
| 526 | INSTPM_SYNC_FLUSH)); |
| 527 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, |
| 528 | 1000)) |
| 529 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
| 530 | ring->name); |
| 531 | } |
| 532 | } |
| 533 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 534 | static bool stop_ring(struct intel_engine_cs *ring) |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 535 | { |
| 536 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
| 537 | |
| 538 | if (!IS_GEN2(ring->dev)) { |
| 539 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); |
Daniel Vetter | 403bdd1 | 2014-08-07 16:05:39 +0200 | [diff] [blame] | 540 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
| 541 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); |
Chris Wilson | 9bec9b1 | 2014-08-11 09:21:35 +0100 | [diff] [blame] | 542 | /* Sometimes we observe that the idle flag is not |
| 543 | * set even though the ring is empty. So double |
| 544 | * check before giving up. |
| 545 | */ |
| 546 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) |
| 547 | return false; |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 548 | } |
| 549 | } |
| 550 | |
| 551 | I915_WRITE_CTL(ring, 0); |
| 552 | I915_WRITE_HEAD(ring, 0); |
| 553 | ring->write_tail(ring, 0); |
| 554 | |
| 555 | if (!IS_GEN2(ring->dev)) { |
| 556 | (void)I915_READ_CTL(ring); |
| 557 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
| 558 | } |
| 559 | |
| 560 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
| 561 | } |
| 562 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 563 | static int init_ring_common(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 564 | { |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 565 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 566 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 567 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 568 | struct drm_i915_gem_object *obj = ringbuf->obj; |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 569 | int ret = 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 570 | |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 571 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 572 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 573 | if (!stop_ring(ring)) { |
| 574 | /* G45 ring initialization often fails to reset head to zero */ |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 575 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 576 | "ctl %08x head %08x tail %08x start %08x\n", |
| 577 | ring->name, |
| 578 | I915_READ_CTL(ring), |
| 579 | I915_READ_HEAD(ring), |
| 580 | I915_READ_TAIL(ring), |
| 581 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 582 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 583 | if (!stop_ring(ring)) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 584 | DRM_ERROR("failed to set %s head to zero " |
| 585 | "ctl %08x head %08x tail %08x start %08x\n", |
| 586 | ring->name, |
| 587 | I915_READ_CTL(ring), |
| 588 | I915_READ_HEAD(ring), |
| 589 | I915_READ_TAIL(ring), |
| 590 | I915_READ_START(ring)); |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 591 | ret = -EIO; |
| 592 | goto out; |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 593 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 594 | } |
| 595 | |
Chris Wilson | 9991ae7 | 2014-04-02 16:36:07 +0100 | [diff] [blame] | 596 | if (I915_NEED_GFX_HWS(dev)) |
| 597 | intel_ring_setup_status_page(ring); |
| 598 | else |
| 599 | ring_setup_phys_status_page(ring); |
| 600 | |
Jiri Kosina | ece4a17 | 2014-08-07 16:29:53 +0200 | [diff] [blame] | 601 | /* Enforce ordering by reading HEAD register back */ |
| 602 | I915_READ_HEAD(ring); |
| 603 | |
Daniel Vetter | 0d8957c | 2012-08-07 09:54:14 +0200 | [diff] [blame] | 604 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
| 605 | * registers with the above sequence (the readback of the HEAD registers |
| 606 | * also enforces ordering), otherwise the hw might lose the new ring |
| 607 | * register values. */ |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 608 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
Chris Wilson | 9546889 | 2014-08-07 15:39:54 +0100 | [diff] [blame] | 609 | |
| 610 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ |
| 611 | if (I915_READ_HEAD(ring)) |
| 612 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
| 613 | ring->name, I915_READ_HEAD(ring)); |
| 614 | I915_WRITE_HEAD(ring, 0); |
| 615 | (void)I915_READ_HEAD(ring); |
| 616 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 617 | I915_WRITE_CTL(ring, |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 618 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 619 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 620 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 621 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 622 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 623 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 624 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 625 | DRM_ERROR("%s initialization failed " |
Chris Wilson | 48e48a0 | 2014-04-09 09:19:44 +0100 | [diff] [blame] | 626 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
| 627 | ring->name, |
| 628 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, |
| 629 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), |
| 630 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 631 | ret = -EIO; |
| 632 | goto out; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 633 | } |
| 634 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 635 | ringbuf->last_retired_head = -1; |
Chris Wilson | 5c6c600 | 2014-09-06 10:28:27 +0100 | [diff] [blame] | 636 | ringbuf->head = I915_READ_HEAD(ring); |
| 637 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 638 | intel_ring_update_space(ringbuf); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 639 | |
Chris Wilson | 50f018d | 2013-06-10 11:20:19 +0100 | [diff] [blame] | 640 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
| 641 | |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 642 | out: |
Mika Kuoppala | 59bad94 | 2015-01-16 11:34:40 +0200 | [diff] [blame] | 643 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Daniel Vetter | b7884eb | 2012-06-04 11:18:15 +0200 | [diff] [blame] | 644 | |
| 645 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 646 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 647 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 648 | void |
| 649 | intel_fini_pipe_control(struct intel_engine_cs *ring) |
| 650 | { |
| 651 | struct drm_device *dev = ring->dev; |
| 652 | |
| 653 | if (ring->scratch.obj == NULL) |
| 654 | return; |
| 655 | |
| 656 | if (INTEL_INFO(dev)->gen >= 5) { |
| 657 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 658 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
| 659 | } |
| 660 | |
| 661 | drm_gem_object_unreference(&ring->scratch.obj->base); |
| 662 | ring->scratch.obj = NULL; |
| 663 | } |
| 664 | |
| 665 | int |
| 666 | intel_init_pipe_control(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 667 | { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 668 | int ret; |
| 669 | |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 670 | WARN_ON(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 671 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 672 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
| 673 | if (ring->scratch.obj == NULL) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 674 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 675 | ret = -ENOMEM; |
| 676 | goto err; |
| 677 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 678 | |
Daniel Vetter | a9cc726 | 2014-02-14 14:01:13 +0100 | [diff] [blame] | 679 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
| 680 | if (ret) |
| 681 | goto err_unref; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 682 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 683 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 684 | if (ret) |
| 685 | goto err_unref; |
| 686 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 687 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
| 688 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); |
| 689 | if (ring->scratch.cpu_page == NULL) { |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 690 | ret = -ENOMEM; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 691 | goto err_unpin; |
Wei Yongjun | 56b085a | 2013-05-28 17:51:44 +0800 | [diff] [blame] | 692 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 693 | |
Ville Syrjälä | 2b1086c | 2013-02-12 22:01:38 +0200 | [diff] [blame] | 694 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 695 | ring->name, ring->scratch.gtt_offset); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 696 | return 0; |
| 697 | |
| 698 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 699 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 700 | err_unref: |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 701 | drm_gem_object_unreference(&ring->scratch.obj->base); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 702 | err: |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 703 | return ret; |
| 704 | } |
| 705 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 706 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
| 707 | struct intel_context *ctx) |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 708 | { |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 709 | int ret, i; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 710 | struct drm_device *dev = ring->dev; |
| 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 712 | struct i915_workarounds *w = &dev_priv->workarounds; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 713 | |
Michel Thierry | e6c1abb | 2014-11-26 14:21:02 +0000 | [diff] [blame] | 714 | if (WARN_ON_ONCE(w->count == 0)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 715 | return 0; |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 716 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 717 | ring->gpu_caches_dirty = true; |
| 718 | ret = intel_ring_flush_all_caches(ring); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 719 | if (ret) |
| 720 | return ret; |
| 721 | |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 722 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 723 | if (ret) |
| 724 | return ret; |
| 725 | |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 726 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 727 | for (i = 0; i < w->count; i++) { |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 728 | intel_ring_emit(ring, w->reg[i].addr); |
| 729 | intel_ring_emit(ring, w->reg[i].value); |
| 730 | } |
Arun Siluvery | 22a916a | 2014-10-22 18:59:52 +0100 | [diff] [blame] | 731 | intel_ring_emit(ring, MI_NOOP); |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 732 | |
| 733 | intel_ring_advance(ring); |
| 734 | |
| 735 | ring->gpu_caches_dirty = true; |
| 736 | ret = intel_ring_flush_all_caches(ring); |
| 737 | if (ret) |
| 738 | return ret; |
| 739 | |
| 740 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
| 741 | |
| 742 | return 0; |
| 743 | } |
| 744 | |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 745 | static int intel_rcs_ctx_init(struct intel_engine_cs *ring, |
| 746 | struct intel_context *ctx) |
| 747 | { |
| 748 | int ret; |
| 749 | |
| 750 | ret = intel_ring_workarounds_emit(ring, ctx); |
| 751 | if (ret != 0) |
| 752 | return ret; |
| 753 | |
| 754 | ret = i915_gem_render_state_init(ring); |
| 755 | if (ret) |
| 756 | DRM_ERROR("init render state: %d\n", ret); |
| 757 | |
| 758 | return ret; |
| 759 | } |
| 760 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 761 | static int wa_add(struct drm_i915_private *dev_priv, |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 762 | const u32 addr, const u32 mask, const u32 val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 763 | { |
| 764 | const u32 idx = dev_priv->workarounds.count; |
| 765 | |
| 766 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) |
| 767 | return -ENOSPC; |
| 768 | |
| 769 | dev_priv->workarounds.reg[idx].addr = addr; |
| 770 | dev_priv->workarounds.reg[idx].value = val; |
| 771 | dev_priv->workarounds.reg[idx].mask = mask; |
| 772 | |
| 773 | dev_priv->workarounds.count++; |
| 774 | |
| 775 | return 0; |
| 776 | } |
| 777 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 778 | #define WA_REG(addr, mask, val) { \ |
| 779 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 780 | if (r) \ |
| 781 | return r; \ |
| 782 | } |
| 783 | |
| 784 | #define WA_SET_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 785 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 786 | |
| 787 | #define WA_CLR_BIT_MASKED(addr, mask) \ |
Damien Lespiau | 2645934 | 2014-12-08 17:35:38 +0000 | [diff] [blame] | 788 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 789 | |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 790 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 791 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 792 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 793 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
| 794 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 795 | |
Damien Lespiau | cf4b0de | 2014-12-08 17:35:37 +0000 | [diff] [blame] | 796 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 797 | |
| 798 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
| 799 | { |
| 800 | struct drm_device *dev = ring->dev; |
| 801 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 802 | |
Ville Syrjälä | 9cc8302 | 2015-06-02 15:37:36 +0300 | [diff] [blame^] | 803 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); |
| 804 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 805 | /* WaDisablePartialInstShootdown:bdw */ |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 806 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 807 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 808 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
| 809 | STALL_DOP_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 810 | |
Rodrigo Vivi | 101b376 | 2014-10-09 07:11:47 -0700 | [diff] [blame] | 811 | /* WaDisableDopClockGating:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 812 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
| 813 | DOP_CLOCK_GATING_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 814 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 815 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 816 | GEN8_SAMPLER_POWER_BYPASS_DIS); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 817 | |
| 818 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 819 | * workaround for for a possible hang in the unlikely event a TLB |
| 820 | * invalidation occurs during a PSD flush. |
| 821 | */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 822 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 823 | /* WaForceEnableNonCoherent:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 824 | HDC_FORCE_NON_COHERENT | |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 825 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
| 826 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | |
| 827 | /* WaHdcDisableFetchWhenMasked:bdw */ |
Michel Thierry | f3f3236 | 2014-12-04 15:07:52 +0000 | [diff] [blame] | 828 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
Damien Lespiau | 35cb6f3 | 2015-02-10 10:31:00 +0000 | [diff] [blame] | 829 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 830 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 831 | |
Kenneth Graunke | 2701fc4 | 2015-01-13 12:46:52 -0800 | [diff] [blame] | 832 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
| 833 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping |
| 834 | * polygons in the same 8x4 pixel/sample area to be processed without |
| 835 | * stalling waiting for the earlier ones to write to Hierarchical Z |
| 836 | * buffer." |
| 837 | * |
| 838 | * This optimization is off by default for Broadwell; turn it on. |
| 839 | */ |
| 840 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); |
| 841 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 842 | /* Wa4x4STCOptimizationDisable:bdw */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 843 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
| 844 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 845 | |
| 846 | /* |
| 847 | * BSpec recommends 8x4 when MSAA is used, |
| 848 | * however in practice 16x4 seems fastest. |
| 849 | * |
| 850 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 851 | * disable bit, which we don't touch here, but it's good |
| 852 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 853 | */ |
Damien Lespiau | 9853325 | 2014-12-08 17:33:51 +0000 | [diff] [blame] | 854 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 855 | GEN6_WIZ_HASHING_MASK, |
| 856 | GEN6_WIZ_HASHING_16x4); |
Arun Siluvery | 888b599 | 2014-08-26 14:44:51 +0100 | [diff] [blame] | 857 | |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 858 | return 0; |
| 859 | } |
| 860 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 861 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
| 862 | { |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 863 | struct drm_device *dev = ring->dev; |
| 864 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 865 | |
Ville Syrjälä | 9cc8302 | 2015-06-02 15:37:36 +0300 | [diff] [blame^] | 866 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); |
| 867 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 868 | /* WaDisablePartialInstShootdown:chv */ |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 869 | /* WaDisableThreadStallDopClockGating:chv */ |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 870 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
Arun Siluvery | 605f143 | 2014-10-28 18:33:13 +0000 | [diff] [blame] | 871 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
| 872 | STALL_DOP_GATING_DISABLE); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 873 | |
Arun Siluvery | 95289009 | 2014-10-28 18:33:14 +0000 | [diff] [blame] | 874 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 875 | * workaround for a possible hang in the unlikely event a TLB |
| 876 | * invalidation occurs during a PSD flush. |
| 877 | */ |
| 878 | /* WaForceEnableNonCoherent:chv */ |
| 879 | /* WaHdcDisableFetchWhenMasked:chv */ |
| 880 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 881 | HDC_FORCE_NON_COHERENT | |
| 882 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); |
| 883 | |
Kenneth Graunke | 973a5b0 | 2015-01-13 12:46:53 -0800 | [diff] [blame] | 884 | /* According to the CACHE_MODE_0 default value documentation, some |
| 885 | * CHV platforms disable this optimization by default. Turn it on. |
| 886 | */ |
| 887 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); |
| 888 | |
Ville Syrjälä | 14bc16e | 2015-01-21 19:37:58 +0200 | [diff] [blame] | 889 | /* Wa4x4STCOptimizationDisable:chv */ |
| 890 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
| 891 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
| 892 | |
Kenneth Graunke | d60de81 | 2015-01-10 18:02:22 -0800 | [diff] [blame] | 893 | /* Improve HiZ throughput on CHV. */ |
| 894 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); |
| 895 | |
Ville Syrjälä | e7fc243 | 2015-01-21 19:38:00 +0200 | [diff] [blame] | 896 | /* |
| 897 | * BSpec recommends 8x4 when MSAA is used, |
| 898 | * however in practice 16x4 seems fastest. |
| 899 | * |
| 900 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 901 | * disable bit, which we don't touch here, but it's good |
| 902 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
| 903 | */ |
| 904 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 905 | GEN6_WIZ_HASHING_MASK, |
| 906 | GEN6_WIZ_HASHING_16x4); |
| 907 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 908 | return 0; |
| 909 | } |
| 910 | |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 911 | static int gen9_init_workarounds(struct intel_engine_cs *ring) |
| 912 | { |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 913 | struct drm_device *dev = ring->dev; |
| 914 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 915 | uint32_t tmp; |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 916 | |
Nick Hoath | b0e6f6d | 2015-05-07 14:15:29 +0100 | [diff] [blame] | 917 | /* WaDisablePartialInstShootdown:skl,bxt */ |
Hoath, Nicholas | ab0dfaf | 2015-02-05 10:47:18 +0000 | [diff] [blame] | 918 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 919 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
| 920 | |
Nick Hoath | a119a6e | 2015-05-07 14:15:30 +0100 | [diff] [blame] | 921 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
Nick Hoath | 8424171 | 2015-02-05 10:47:20 +0000 | [diff] [blame] | 922 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
| 923 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); |
| 924 | |
Nick Hoath | d2a31db | 2015-05-07 14:15:31 +0100 | [diff] [blame] | 925 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || |
| 926 | INTEL_REVID(dev) == SKL_REVID_B0)) || |
| 927 | (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { |
| 928 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
Damien Lespiau | a86eb58 | 2015-02-11 18:21:44 +0000 | [diff] [blame] | 929 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 930 | GEN9_DG_MIRROR_FIX_ENABLE); |
Nick Hoath | 1de4582 | 2015-02-05 10:47:19 +0000 | [diff] [blame] | 931 | } |
| 932 | |
Nick Hoath | a13d215 | 2015-05-07 14:15:32 +0100 | [diff] [blame] | 933 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || |
| 934 | (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { |
| 935 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
Damien Lespiau | 183c6da | 2015-02-09 19:33:11 +0000 | [diff] [blame] | 936 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
| 937 | GEN9_RHWO_OPTIMIZATION_DISABLE); |
| 938 | WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0, |
| 939 | DISABLE_PIXEL_MASK_CAMMING); |
| 940 | } |
| 941 | |
Nick Hoath | 27a1b68 | 2015-05-07 14:15:33 +0100 | [diff] [blame] | 942 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) || |
| 943 | IS_BROXTON(dev)) { |
| 944 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
Nick Hoath | cac23df | 2015-02-05 10:47:22 +0000 | [diff] [blame] | 945 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
| 946 | GEN9_ENABLE_YV12_BUGFIX); |
| 947 | } |
| 948 | |
Nick Hoath | 5068368 | 2015-05-07 14:15:35 +0100 | [diff] [blame] | 949 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
Hoath, Nicholas | 1840481 | 2015-02-05 10:47:23 +0000 | [diff] [blame] | 950 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); |
| 951 | |
Nick Hoath | 27160c9 | 2015-05-07 14:15:36 +0100 | [diff] [blame] | 952 | /* WaDisablePartialResolveInVc:skl,bxt */ |
Damien Lespiau | 9370cd9 | 2015-02-09 19:33:17 +0000 | [diff] [blame] | 953 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); |
| 954 | |
Nick Hoath | 16be17a | 2015-05-07 14:15:37 +0100 | [diff] [blame] | 955 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
Damien Lespiau | e2db707 | 2015-02-09 19:33:21 +0000 | [diff] [blame] | 956 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
| 957 | GEN9_CCS_TLB_PREFETCH_ENABLE); |
| 958 | |
Imre Deak | 5a2ae95 | 2015-05-19 15:04:59 +0300 | [diff] [blame] | 959 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
| 960 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || |
| 961 | (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) |
Ben Widawsky | 38a39a7 | 2015-03-11 10:54:53 +0200 | [diff] [blame] | 962 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
| 963 | PIXEL_MASK_CAMMING_DISABLE); |
| 964 | |
Imre Deak | 8ea6f89 | 2015-05-19 17:05:42 +0300 | [diff] [blame] | 965 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
| 966 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; |
| 967 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) || |
| 968 | (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0)) |
| 969 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
| 970 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); |
| 971 | |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 972 | return 0; |
| 973 | } |
| 974 | |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 975 | static int skl_tune_iz_hashing(struct intel_engine_cs *ring) |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 976 | { |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 977 | struct drm_device *dev = ring->dev; |
| 978 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 979 | u8 vals[3] = { 0, 0, 0 }; |
| 980 | unsigned int i; |
| 981 | |
| 982 | for (i = 0; i < 3; i++) { |
| 983 | u8 ss; |
| 984 | |
| 985 | /* |
| 986 | * Only consider slices where one, and only one, subslice has 7 |
| 987 | * EUs |
| 988 | */ |
| 989 | if (hweight8(dev_priv->info.subslice_7eu[i]) != 1) |
| 990 | continue; |
| 991 | |
| 992 | /* |
| 993 | * subslice_7eu[i] != 0 (because of the check above) and |
| 994 | * ss_max == 4 (maximum number of subslices possible per slice) |
| 995 | * |
| 996 | * -> 0 <= ss <= 3; |
| 997 | */ |
| 998 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; |
| 999 | vals[i] = 3 - ss; |
| 1000 | } |
| 1001 | |
| 1002 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) |
| 1003 | return 0; |
| 1004 | |
| 1005 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ |
| 1006 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
| 1007 | GEN9_IZ_HASHING_MASK(2) | |
| 1008 | GEN9_IZ_HASHING_MASK(1) | |
| 1009 | GEN9_IZ_HASHING_MASK(0), |
| 1010 | GEN9_IZ_HASHING(2, vals[2]) | |
| 1011 | GEN9_IZ_HASHING(1, vals[1]) | |
| 1012 | GEN9_IZ_HASHING(0, vals[0])); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1013 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1014 | return 0; |
| 1015 | } |
| 1016 | |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1017 | |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1018 | static int skl_init_workarounds(struct intel_engine_cs *ring) |
| 1019 | { |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1020 | struct drm_device *dev = ring->dev; |
| 1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1022 | |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1023 | gen9_init_workarounds(ring); |
| 1024 | |
Damien Lespiau | d0bbbc4 | 2015-02-09 19:33:16 +0000 | [diff] [blame] | 1025 | /* WaDisablePowerCompilerClockGating:skl */ |
| 1026 | if (INTEL_REVID(dev) == SKL_REVID_B0) |
| 1027 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
| 1028 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); |
| 1029 | |
Nick Hoath | b62adbd | 2015-05-07 14:15:34 +0100 | [diff] [blame] | 1030 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
| 1031 | /* |
| 1032 | *Use Force Non-Coherent whenever executing a 3D context. This |
| 1033 | * is a workaround for a possible hang in the unlikely event |
| 1034 | * a TLB invalidation occurs during a PSD flush. |
| 1035 | */ |
| 1036 | /* WaForceEnableNonCoherent:skl */ |
| 1037 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1038 | HDC_FORCE_NON_COHERENT); |
| 1039 | } |
| 1040 | |
Ville Syrjälä | 5b6fd12 | 2015-06-02 15:37:35 +0300 | [diff] [blame] | 1041 | if (INTEL_REVID(dev) == SKL_REVID_C0 || |
| 1042 | INTEL_REVID(dev) == SKL_REVID_D0) |
| 1043 | /* WaBarrierPerformanceFixDisable:skl */ |
| 1044 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
| 1045 | HDC_FENCE_DEST_SLM_DISABLE | |
| 1046 | HDC_BARRIER_PERFORMANCE_DISABLE); |
| 1047 | |
Damien Lespiau | b766879 | 2015-02-14 18:30:29 +0000 | [diff] [blame] | 1048 | return skl_tune_iz_hashing(ring); |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1049 | } |
| 1050 | |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1051 | static int bxt_init_workarounds(struct intel_engine_cs *ring) |
| 1052 | { |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1053 | struct drm_device *dev = ring->dev; |
| 1054 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1055 | |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1056 | gen9_init_workarounds(ring); |
| 1057 | |
Nick Hoath | dfb601e | 2015-04-10 13:12:24 +0100 | [diff] [blame] | 1058 | /* WaDisableThreadStallDopClockGating:bxt */ |
| 1059 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
| 1060 | STALL_DOP_GATING_DISABLE); |
| 1061 | |
Nick Hoath | 983b4b9 | 2015-04-10 13:12:25 +0100 | [diff] [blame] | 1062 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
| 1063 | if (INTEL_REVID(dev) <= BXT_REVID_B0) { |
| 1064 | WA_SET_BIT_MASKED( |
| 1065 | GEN7_HALF_SLICE_CHICKEN1, |
| 1066 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| 1067 | } |
| 1068 | |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1069 | return 0; |
| 1070 | } |
| 1071 | |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 1072 | int init_workarounds_ring(struct intel_engine_cs *ring) |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1073 | { |
| 1074 | struct drm_device *dev = ring->dev; |
| 1075 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1076 | |
| 1077 | WARN_ON(ring->id != RCS); |
| 1078 | |
| 1079 | dev_priv->workarounds.count = 0; |
| 1080 | |
| 1081 | if (IS_BROADWELL(dev)) |
| 1082 | return bdw_init_workarounds(ring); |
| 1083 | |
| 1084 | if (IS_CHERRYVIEW(dev)) |
| 1085 | return chv_init_workarounds(ring); |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1086 | |
Damien Lespiau | 8d20549 | 2015-02-09 19:33:15 +0000 | [diff] [blame] | 1087 | if (IS_SKYLAKE(dev)) |
| 1088 | return skl_init_workarounds(ring); |
Nick Hoath | cae0437 | 2015-03-17 11:39:38 +0200 | [diff] [blame] | 1089 | |
| 1090 | if (IS_BROXTON(dev)) |
| 1091 | return bxt_init_workarounds(ring); |
Hoath, Nicholas | 3b10653 | 2015-02-05 10:47:16 +0000 | [diff] [blame] | 1092 | |
Ville Syrjälä | 00e1e62 | 2014-08-27 17:33:12 +0300 | [diff] [blame] | 1093 | return 0; |
| 1094 | } |
| 1095 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1096 | static int init_render_ring(struct intel_engine_cs *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1097 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1098 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1099 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1100 | int ret = init_ring_common(ring); |
Konrad Zapalowicz | 9c33baa | 2014-06-19 19:07:15 +0200 | [diff] [blame] | 1101 | if (ret) |
| 1102 | return ret; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 1103 | |
Akash Goel | 61a563a | 2014-03-25 18:01:50 +0530 | [diff] [blame] | 1104 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
| 1105 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1106 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1107 | |
| 1108 | /* We need to disable the AsyncFlip performance optimisations in order |
| 1109 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be |
| 1110 | * programmed to '1' on all products. |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 1111 | * |
Ville Syrjälä | b3f797a | 2014-04-28 14:31:09 +0300 | [diff] [blame] | 1112 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1113 | */ |
Imre Deak | fbdcb06 | 2013-02-13 15:27:34 +0000 | [diff] [blame] | 1114 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1115 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
| 1116 | |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1117 | /* Required for the hardware to program scanline values for waiting */ |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1118 | /* WaEnableFlushTlbInvalidationMode:snb */ |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1119 | if (INTEL_INFO(dev)->gen == 6) |
| 1120 | I915_WRITE(GFX_MODE, |
Chris Wilson | aa83e30 | 2014-03-21 17:18:54 +0000 | [diff] [blame] | 1121 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
Chris Wilson | f05bb0c | 2013-01-20 16:33:32 +0000 | [diff] [blame] | 1122 | |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1123 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1124 | if (IS_GEN7(dev)) |
| 1125 | I915_WRITE(GFX_MODE_GEN7, |
Akash Goel | 01fa030 | 2014-03-24 23:00:04 +0530 | [diff] [blame] | 1126 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
Chris Wilson | 1c8c38c | 2013-01-20 16:11:20 +0000 | [diff] [blame] | 1127 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1128 | |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 1129 | if (IS_GEN6(dev)) { |
Kenneth Graunke | 3a69ddd | 2012-04-27 12:44:41 -0700 | [diff] [blame] | 1130 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
| 1131 | * "If this bit is set, STCunit will have LRA as replacement |
| 1132 | * policy. [...] This bit must be reset. LRA replacement |
| 1133 | * policy is not supported." |
| 1134 | */ |
| 1135 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5e13a0c | 2012-05-08 13:39:59 +0200 | [diff] [blame] | 1136 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 1137 | } |
| 1138 | |
Ville Syrjälä | 9cc8302 | 2015-06-02 15:37:36 +0300 | [diff] [blame^] | 1139 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1140 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1141 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1142 | if (HAS_L3_DPF(dev)) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1143 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1144 | |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 1145 | return init_workarounds_ring(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1146 | } |
| 1147 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1148 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1149 | { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1150 | struct drm_device *dev = ring->dev; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1152 | |
| 1153 | if (dev_priv->semaphore_obj) { |
| 1154 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); |
| 1155 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); |
| 1156 | dev_priv->semaphore_obj = NULL; |
| 1157 | } |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1158 | |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 1159 | intel_fini_pipe_control(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1160 | } |
| 1161 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1162 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
| 1163 | unsigned int num_dwords) |
| 1164 | { |
| 1165 | #define MBOX_UPDATE_DWORDS 8 |
| 1166 | struct drm_device *dev = signaller->dev; |
| 1167 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1168 | struct intel_engine_cs *waiter; |
| 1169 | int i, ret, num_rings; |
| 1170 | |
| 1171 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1172 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1173 | #undef MBOX_UPDATE_DWORDS |
| 1174 | |
| 1175 | ret = intel_ring_begin(signaller, num_dwords); |
| 1176 | if (ret) |
| 1177 | return ret; |
| 1178 | |
| 1179 | for_each_ring(waiter, dev_priv, i) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1180 | u32 seqno; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1181 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 1182 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1183 | continue; |
| 1184 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1185 | seqno = i915_gem_request_get_seqno( |
| 1186 | signaller->outstanding_lazy_request); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1187 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
| 1188 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | |
| 1189 | PIPE_CONTROL_QW_WRITE | |
| 1190 | PIPE_CONTROL_FLUSH_ENABLE); |
| 1191 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
| 1192 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1193 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1194 | intel_ring_emit(signaller, 0); |
| 1195 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 1196 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 1197 | intel_ring_emit(signaller, 0); |
| 1198 | } |
| 1199 | |
| 1200 | return 0; |
| 1201 | } |
| 1202 | |
| 1203 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, |
| 1204 | unsigned int num_dwords) |
| 1205 | { |
| 1206 | #define MBOX_UPDATE_DWORDS 6 |
| 1207 | struct drm_device *dev = signaller->dev; |
| 1208 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1209 | struct intel_engine_cs *waiter; |
| 1210 | int i, ret, num_rings; |
| 1211 | |
| 1212 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1213 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
| 1214 | #undef MBOX_UPDATE_DWORDS |
| 1215 | |
| 1216 | ret = intel_ring_begin(signaller, num_dwords); |
| 1217 | if (ret) |
| 1218 | return ret; |
| 1219 | |
| 1220 | for_each_ring(waiter, dev_priv, i) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1221 | u32 seqno; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1222 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
| 1223 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
| 1224 | continue; |
| 1225 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1226 | seqno = i915_gem_request_get_seqno( |
| 1227 | signaller->outstanding_lazy_request); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1228 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
| 1229 | MI_FLUSH_DW_OP_STOREDW); |
| 1230 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | |
| 1231 | MI_FLUSH_DW_USE_GTT); |
| 1232 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1233 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 1234 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
| 1235 | MI_SEMAPHORE_TARGET(waiter->id)); |
| 1236 | intel_ring_emit(signaller, 0); |
| 1237 | } |
| 1238 | |
| 1239 | return 0; |
| 1240 | } |
| 1241 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1242 | static int gen6_signal(struct intel_engine_cs *signaller, |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1243 | unsigned int num_dwords) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1244 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1245 | struct drm_device *dev = signaller->dev; |
| 1246 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1247 | struct intel_engine_cs *useless; |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1248 | int i, ret, num_rings; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1249 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1250 | #define MBOX_UPDATE_DWORDS 3 |
| 1251 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
| 1252 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
| 1253 | #undef MBOX_UPDATE_DWORDS |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1254 | |
| 1255 | ret = intel_ring_begin(signaller, num_dwords); |
| 1256 | if (ret) |
| 1257 | return ret; |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1258 | |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1259 | for_each_ring(useless, dev_priv, i) { |
| 1260 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; |
| 1261 | if (mbox_reg != GEN6_NOSYNC) { |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1262 | u32 seqno = i915_gem_request_get_seqno( |
| 1263 | signaller->outstanding_lazy_request); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1264 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
| 1265 | intel_ring_emit(signaller, mbox_reg); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1266 | intel_ring_emit(signaller, seqno); |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 1267 | } |
| 1268 | } |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1269 | |
Ben Widawsky | a1444b7 | 2014-06-30 09:53:35 -0700 | [diff] [blame] | 1270 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
| 1271 | if (num_rings % 2 == 0) |
| 1272 | intel_ring_emit(signaller, MI_NOOP); |
| 1273 | |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1274 | return 0; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1275 | } |
| 1276 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1277 | /** |
| 1278 | * gen6_add_request - Update the semaphore mailbox registers |
| 1279 | * |
| 1280 | * @ring - ring that is adding a request |
| 1281 | * @seqno - return seqno stuck into the ring |
| 1282 | * |
| 1283 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 1284 | * This acts like a signal in the canonical semaphore. |
| 1285 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1286 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1287 | gen6_add_request(struct intel_engine_cs *ring) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1288 | { |
Ben Widawsky | 024a43e | 2014-04-29 14:52:30 -0700 | [diff] [blame] | 1289 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1290 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 1291 | if (ring->semaphore.signal) |
| 1292 | ret = ring->semaphore.signal(ring, 4); |
| 1293 | else |
| 1294 | ret = intel_ring_begin(ring, 4); |
| 1295 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1296 | if (ret) |
| 1297 | return ret; |
| 1298 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1299 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1300 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1301 | intel_ring_emit(ring, |
| 1302 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1303 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1304 | __intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1305 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1306 | return 0; |
| 1307 | } |
| 1308 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1309 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
| 1310 | u32 seqno) |
| 1311 | { |
| 1312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1313 | return dev_priv->last_seqno < seqno; |
| 1314 | } |
| 1315 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1316 | /** |
| 1317 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 1318 | * |
| 1319 | * @waiter - ring that is waiting |
| 1320 | * @signaller - ring which has, or will signal |
| 1321 | * @seqno - seqno which the waiter will block on |
| 1322 | */ |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1323 | |
| 1324 | static int |
| 1325 | gen8_ring_sync(struct intel_engine_cs *waiter, |
| 1326 | struct intel_engine_cs *signaller, |
| 1327 | u32 seqno) |
| 1328 | { |
| 1329 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
| 1330 | int ret; |
| 1331 | |
| 1332 | ret = intel_ring_begin(waiter, 4); |
| 1333 | if (ret) |
| 1334 | return ret; |
| 1335 | |
| 1336 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | |
| 1337 | MI_SEMAPHORE_GLOBAL_GTT | |
Ben Widawsky | bae4fcd | 2014-06-30 09:53:43 -0700 | [diff] [blame] | 1338 | MI_SEMAPHORE_POLL | |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 1339 | MI_SEMAPHORE_SAD_GTE_SDD); |
| 1340 | intel_ring_emit(waiter, seqno); |
| 1341 | intel_ring_emit(waiter, |
| 1342 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1343 | intel_ring_emit(waiter, |
| 1344 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); |
| 1345 | intel_ring_advance(waiter); |
| 1346 | return 0; |
| 1347 | } |
| 1348 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1349 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1350 | gen6_ring_sync(struct intel_engine_cs *waiter, |
| 1351 | struct intel_engine_cs *signaller, |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1352 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1353 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1354 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 1355 | MI_SEMAPHORE_COMPARE | |
| 1356 | MI_SEMAPHORE_REGISTER; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1357 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
| 1358 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1359 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 1360 | /* Throughout all of the GEM code, seqno passed implies our current |
| 1361 | * seqno is >= the last seqno executed. However for hardware the |
| 1362 | * comparison is strictly greater than. |
| 1363 | */ |
| 1364 | seqno -= 1; |
| 1365 | |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1366 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1367 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1368 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1369 | if (ret) |
| 1370 | return ret; |
| 1371 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1372 | /* If seqno wrap happened, omit the wait with no-ops */ |
| 1373 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 1374 | intel_ring_emit(waiter, dw1 | wait_mbox); |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1375 | intel_ring_emit(waiter, seqno); |
| 1376 | intel_ring_emit(waiter, 0); |
| 1377 | intel_ring_emit(waiter, MI_NOOP); |
| 1378 | } else { |
| 1379 | intel_ring_emit(waiter, MI_NOOP); |
| 1380 | intel_ring_emit(waiter, MI_NOOP); |
| 1381 | intel_ring_emit(waiter, MI_NOOP); |
| 1382 | intel_ring_emit(waiter, MI_NOOP); |
| 1383 | } |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 1384 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1385 | |
| 1386 | return 0; |
| 1387 | } |
| 1388 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1389 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 1390 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1391 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 1392 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1393 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 1394 | intel_ring_emit(ring__, 0); \ |
| 1395 | intel_ring_emit(ring__, 0); \ |
| 1396 | } while (0) |
| 1397 | |
| 1398 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1399 | pc_render_add_request(struct intel_engine_cs *ring) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1400 | { |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1401 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1402 | int ret; |
| 1403 | |
| 1404 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 1405 | * incoherent with writes to memory, i.e. completely fubar, |
| 1406 | * so we need to use PIPE_NOTIFY instead. |
| 1407 | * |
| 1408 | * However, we also need to workaround the qword write |
| 1409 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 1410 | * memory before requesting an interrupt. |
| 1411 | */ |
| 1412 | ret = intel_ring_begin(ring, 32); |
| 1413 | if (ret) |
| 1414 | return ret; |
| 1415 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1416 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1417 | PIPE_CONTROL_WRITE_FLUSH | |
| 1418 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1419 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1420 | intel_ring_emit(ring, |
| 1421 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1422 | intel_ring_emit(ring, 0); |
| 1423 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1424 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1425 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1426 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1427 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1428 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1429 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1430 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1431 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 1432 | scratch_addr += 2 * CACHELINE_BYTES; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1433 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1434 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 1435 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 1436 | PIPE_CONTROL_WRITE_FLUSH | |
| 1437 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1438 | PIPE_CONTROL_NOTIFY); |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1439 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1440 | intel_ring_emit(ring, |
| 1441 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1442 | intel_ring_emit(ring, 0); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1443 | __intel_ring_advance(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1444 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1445 | return 0; |
| 1446 | } |
| 1447 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1448 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1449 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1450 | { |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1451 | /* Workaround to force correct ordering between irq and seqno writes on |
| 1452 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 1453 | * ACTHD) before reading the status page. */ |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 1454 | if (!lazy_coherency) { |
| 1455 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1456 | POSTING_READ(RING_ACTHD(ring->mmio_base)); |
| 1457 | } |
| 1458 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1459 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1460 | } |
| 1461 | |
| 1462 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1463 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1464 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1465 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 1466 | } |
| 1467 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1468 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1469 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1470 | { |
| 1471 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); |
| 1472 | } |
| 1473 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1474 | static u32 |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1475 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1476 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1477 | return ring->scratch.cpu_page[0]; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1478 | } |
| 1479 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1480 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1481 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1482 | { |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 1483 | ring->scratch.cpu_page[0] = seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 1484 | } |
| 1485 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1486 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1487 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1488 | { |
| 1489 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1490 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1491 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1492 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1493 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1494 | return false; |
| 1495 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1496 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1497 | if (ring->irq_refcount++ == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1498 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1499 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1500 | |
| 1501 | return true; |
| 1502 | } |
| 1503 | |
| 1504 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1505 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1506 | { |
| 1507 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1508 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1509 | unsigned long flags; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1510 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1511 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 1512 | if (--ring->irq_refcount == 0) |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1513 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1514 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1515 | } |
| 1516 | |
| 1517 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1518 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1519 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1520 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1521 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1522 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1523 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1524 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1525 | return false; |
| 1526 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1527 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1528 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1529 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1530 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1531 | POSTING_READ(IMR); |
| 1532 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1533 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1534 | |
| 1535 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1536 | } |
| 1537 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1538 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1539 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1540 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1541 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1542 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1543 | unsigned long flags; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1544 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1545 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1546 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | f637fde | 2012-04-11 22:12:59 +0200 | [diff] [blame] | 1547 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1548 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 1549 | POSTING_READ(IMR); |
| 1550 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1551 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1552 | } |
| 1553 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1554 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1555 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1556 | { |
| 1557 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1558 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1559 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1560 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1561 | if (!intel_irqs_enabled(dev_priv)) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1562 | return false; |
| 1563 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1564 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1565 | if (ring->irq_refcount++ == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1566 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
| 1567 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1568 | POSTING_READ16(IMR); |
| 1569 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1570 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1571 | |
| 1572 | return true; |
| 1573 | } |
| 1574 | |
| 1575 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1576 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1577 | { |
| 1578 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1579 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1580 | unsigned long flags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1581 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1582 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1583 | if (--ring->irq_refcount == 0) { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1584 | dev_priv->irq_mask |= ring->irq_enable_mask; |
| 1585 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 1586 | POSTING_READ16(IMR); |
| 1587 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1588 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 1589 | } |
| 1590 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1591 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1592 | bsd_ring_flush(struct intel_engine_cs *ring, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1593 | u32 invalidate_domains, |
| 1594 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1595 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1596 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1597 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1598 | ret = intel_ring_begin(ring, 2); |
| 1599 | if (ret) |
| 1600 | return ret; |
| 1601 | |
| 1602 | intel_ring_emit(ring, MI_FLUSH); |
| 1603 | intel_ring_emit(ring, MI_NOOP); |
| 1604 | intel_ring_advance(ring); |
| 1605 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1606 | } |
| 1607 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1608 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1609 | i9xx_add_request(struct intel_engine_cs *ring) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1610 | { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1611 | int ret; |
| 1612 | |
| 1613 | ret = intel_ring_begin(ring, 4); |
| 1614 | if (ret) |
| 1615 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 1616 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1617 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 1618 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 1619 | intel_ring_emit(ring, |
| 1620 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1621 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 1622 | __intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1623 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1624 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1625 | } |
| 1626 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 1627 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1628 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1629 | { |
| 1630 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1631 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1632 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1633 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1634 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
| 1635 | return false; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1636 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1637 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1638 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1639 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1640 | I915_WRITE_IMR(ring, |
| 1641 | ~(ring->irq_enable_mask | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1642 | GT_PARITY_ERROR(dev))); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1643 | else |
| 1644 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1645 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1646 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1647 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1648 | |
| 1649 | return true; |
| 1650 | } |
| 1651 | |
| 1652 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1653 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1654 | { |
| 1655 | struct drm_device *dev = ring->dev; |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 1656 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1657 | unsigned long flags; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 1658 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1659 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1660 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1661 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1662 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
Ben Widawsky | 15b9f80 | 2012-05-25 16:56:23 -0700 | [diff] [blame] | 1663 | else |
| 1664 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1665 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1666 | } |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 1667 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1668 | } |
| 1669 | |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1670 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1671 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1672 | { |
| 1673 | struct drm_device *dev = ring->dev; |
| 1674 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1675 | unsigned long flags; |
| 1676 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1677 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1678 | return false; |
| 1679 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1680 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1681 | if (ring->irq_refcount++ == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1682 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1683 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1684 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1685 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1686 | |
| 1687 | return true; |
| 1688 | } |
| 1689 | |
| 1690 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1691 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1692 | { |
| 1693 | struct drm_device *dev = ring->dev; |
| 1694 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1695 | unsigned long flags; |
| 1696 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1697 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Daniel Vetter | c7113cc | 2013-07-04 23:35:29 +0200 | [diff] [blame] | 1698 | if (--ring->irq_refcount == 0) { |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1699 | I915_WRITE_IMR(ring, ~0); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 1700 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1701 | } |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1702 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
Ben Widawsky | a19d293 | 2013-05-28 19:22:30 -0700 | [diff] [blame] | 1703 | } |
| 1704 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1705 | static bool |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1706 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1707 | { |
| 1708 | struct drm_device *dev = ring->dev; |
| 1709 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1710 | unsigned long flags; |
| 1711 | |
Daniel Vetter | 7cd512f | 2014-09-15 11:38:57 +0200 | [diff] [blame] | 1712 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1713 | return false; |
| 1714 | |
| 1715 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1716 | if (ring->irq_refcount++ == 0) { |
| 1717 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1718 | I915_WRITE_IMR(ring, |
| 1719 | ~(ring->irq_enable_mask | |
| 1720 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
| 1721 | } else { |
| 1722 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 1723 | } |
| 1724 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1725 | } |
| 1726 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1727 | |
| 1728 | return true; |
| 1729 | } |
| 1730 | |
| 1731 | static void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1732 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1733 | { |
| 1734 | struct drm_device *dev = ring->dev; |
| 1735 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1736 | unsigned long flags; |
| 1737 | |
| 1738 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 1739 | if (--ring->irq_refcount == 0) { |
| 1740 | if (HAS_L3_DPF(dev) && ring->id == RCS) { |
| 1741 | I915_WRITE_IMR(ring, |
| 1742 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
| 1743 | } else { |
| 1744 | I915_WRITE_IMR(ring, ~0); |
| 1745 | } |
| 1746 | POSTING_READ(RING_IMR(ring->mmio_base)); |
| 1747 | } |
| 1748 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1749 | } |
| 1750 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1751 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1752 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1753 | u64 offset, u32 length, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1754 | unsigned dispatch_flags) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1755 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1756 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1757 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1758 | ret = intel_ring_begin(ring, 2); |
| 1759 | if (ret) |
| 1760 | return ret; |
| 1761 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1762 | intel_ring_emit(ring, |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1763 | MI_BATCH_BUFFER_START | |
| 1764 | MI_BATCH_GTT | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1765 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1766 | 0 : MI_BATCH_NON_SECURE_I965)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1767 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1768 | intel_ring_advance(ring); |
| 1769 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1770 | return 0; |
| 1771 | } |
| 1772 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1773 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
| 1774 | #define I830_BATCH_LIMIT (256*1024) |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1775 | #define I830_TLB_ENTRIES (2) |
| 1776 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1777 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1778 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1779 | u64 offset, u32 len, |
| 1780 | unsigned dispatch_flags) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1781 | { |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1782 | u32 cs_offset = ring->scratch.gtt_offset; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1783 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1784 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1785 | ret = intel_ring_begin(ring, 6); |
| 1786 | if (ret) |
| 1787 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1788 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1789 | /* Evict the invalid PTE TLBs */ |
| 1790 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
| 1791 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); |
| 1792 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ |
| 1793 | intel_ring_emit(ring, cs_offset); |
| 1794 | intel_ring_emit(ring, 0xdeadbeef); |
| 1795 | intel_ring_emit(ring, MI_NOOP); |
| 1796 | intel_ring_advance(ring); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1797 | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1798 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1799 | if (len > I830_BATCH_LIMIT) |
| 1800 | return -ENOSPC; |
| 1801 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1802 | ret = intel_ring_begin(ring, 6 + 2); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1803 | if (ret) |
| 1804 | return ret; |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1805 | |
| 1806 | /* Blit the batch (which has now all relocs applied) to the |
| 1807 | * stable batch scratch bo area (so that the CS never |
| 1808 | * stumbles over its tlb invalidation bug) ... |
| 1809 | */ |
| 1810 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
| 1811 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
Chris Wilson | 611a7a4 | 2014-09-12 07:37:42 +0100 | [diff] [blame] | 1812 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1813 | intel_ring_emit(ring, cs_offset); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1814 | intel_ring_emit(ring, 4096); |
| 1815 | intel_ring_emit(ring, offset); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1816 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1817 | intel_ring_emit(ring, MI_FLUSH); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1818 | intel_ring_emit(ring, MI_NOOP); |
| 1819 | intel_ring_advance(ring); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1820 | |
| 1821 | /* ... and execute it. */ |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1822 | offset = cs_offset; |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 1823 | } |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1824 | |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1825 | ret = intel_ring_begin(ring, 4); |
| 1826 | if (ret) |
| 1827 | return ret; |
| 1828 | |
| 1829 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1830 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1831 | 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 1832 | intel_ring_emit(ring, offset + len - 8); |
| 1833 | intel_ring_emit(ring, MI_NOOP); |
| 1834 | intel_ring_advance(ring); |
| 1835 | |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1836 | return 0; |
| 1837 | } |
| 1838 | |
| 1839 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1840 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 1841 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1842 | unsigned dispatch_flags) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 1843 | { |
| 1844 | int ret; |
| 1845 | |
| 1846 | ret = intel_ring_begin(ring, 2); |
| 1847 | if (ret) |
| 1848 | return ret; |
| 1849 | |
Chris Wilson | 65f5687 | 2012-04-17 16:38:12 +0100 | [diff] [blame] | 1850 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 1851 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 1852 | 0 : MI_BATCH_NON_SECURE)); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1853 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1854 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1855 | return 0; |
| 1856 | } |
| 1857 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1858 | static void cleanup_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1859 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1860 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1861 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1862 | obj = ring->status_page.obj; |
| 1863 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1864 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1865 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1866 | kunmap(sg_page(obj->pages->sgl)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1867 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1868 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1869 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1870 | } |
| 1871 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1872 | static int init_status_page(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1873 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1874 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1875 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1876 | if ((obj = ring->status_page.obj) == NULL) { |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1877 | unsigned flags; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1878 | int ret; |
| 1879 | |
| 1880 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 1881 | if (obj == NULL) { |
| 1882 | DRM_ERROR("Failed to allocate status page\n"); |
| 1883 | return -ENOMEM; |
| 1884 | } |
| 1885 | |
| 1886 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 1887 | if (ret) |
| 1888 | goto err_unref; |
| 1889 | |
Chris Wilson | 1f767e0 | 2014-07-03 17:33:03 -0400 | [diff] [blame] | 1890 | flags = 0; |
| 1891 | if (!HAS_LLC(ring->dev)) |
| 1892 | /* On g33, we cannot place HWS above 256MiB, so |
| 1893 | * restrict its pinning to the low mappable arena. |
| 1894 | * Though this restriction is not documented for |
| 1895 | * gen4, gen5, or byt, they also behave similarly |
| 1896 | * and hang if the HWS is placed at the top of the |
| 1897 | * GTT. To generalise, it appears that all !llc |
| 1898 | * platforms have issues with us placing the HWS |
| 1899 | * above the mappable region (even though we never |
| 1900 | * actualy map it). |
| 1901 | */ |
| 1902 | flags |= PIN_MAPPABLE; |
| 1903 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1904 | if (ret) { |
| 1905 | err_unref: |
| 1906 | drm_gem_object_unreference(&obj->base); |
| 1907 | return ret; |
| 1908 | } |
| 1909 | |
| 1910 | ring->status_page.obj = obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1911 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 1912 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1913 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1914 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1915 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1916 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1917 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 1918 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1919 | |
| 1920 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1921 | } |
| 1922 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1923 | static int init_phys_status_page(struct intel_engine_cs *ring) |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1924 | { |
| 1925 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1926 | |
| 1927 | if (!dev_priv->status_page_dmah) { |
| 1928 | dev_priv->status_page_dmah = |
| 1929 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); |
| 1930 | if (!dev_priv->status_page_dmah) |
| 1931 | return -ENOMEM; |
| 1932 | } |
| 1933 | |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 1934 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1935 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1936 | |
| 1937 | return 0; |
| 1938 | } |
| 1939 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1940 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
| 1941 | { |
| 1942 | iounmap(ringbuf->virtual_start); |
| 1943 | ringbuf->virtual_start = NULL; |
| 1944 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
| 1945 | } |
| 1946 | |
| 1947 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
| 1948 | struct intel_ringbuffer *ringbuf) |
| 1949 | { |
| 1950 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1951 | struct drm_i915_gem_object *obj = ringbuf->obj; |
| 1952 | int ret; |
| 1953 | |
| 1954 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| 1955 | if (ret) |
| 1956 | return ret; |
| 1957 | |
| 1958 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 1959 | if (ret) { |
| 1960 | i915_gem_object_ggtt_unpin(obj); |
| 1961 | return ret; |
| 1962 | } |
| 1963 | |
| 1964 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
| 1965 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
| 1966 | if (ringbuf->virtual_start == NULL) { |
| 1967 | i915_gem_object_ggtt_unpin(obj); |
| 1968 | return -EINVAL; |
| 1969 | } |
| 1970 | |
| 1971 | return 0; |
| 1972 | } |
| 1973 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1974 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1975 | { |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1976 | drm_gem_object_unreference(&ringbuf->obj->base); |
| 1977 | ringbuf->obj = NULL; |
| 1978 | } |
| 1979 | |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 1980 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
| 1981 | struct intel_ringbuffer *ringbuf) |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 1982 | { |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1983 | struct drm_i915_gem_object *obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1984 | |
| 1985 | obj = NULL; |
| 1986 | if (!HAS_LLC(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1987 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1988 | if (obj == NULL) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1989 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1990 | if (obj == NULL) |
| 1991 | return -ENOMEM; |
| 1992 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1993 | /* mark ring buffers as read-only from GPU side by default */ |
| 1994 | obj->gt_ro = 1; |
| 1995 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 1996 | ringbuf->obj = obj; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1997 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 1998 | return 0; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 1999 | } |
| 2000 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2001 | static int intel_init_ring_buffer(struct drm_device *dev, |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2002 | struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2003 | { |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2004 | struct intel_ringbuffer *ringbuf; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 2005 | int ret; |
| 2006 | |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2007 | WARN_ON(ring->buffer); |
| 2008 | |
| 2009 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
| 2010 | if (!ringbuf) |
| 2011 | return -ENOMEM; |
| 2012 | ring->buffer = ringbuf; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2013 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2014 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2015 | INIT_LIST_HEAD(&ring->active_list); |
| 2016 | INIT_LIST_HEAD(&ring->request_list); |
Oscar Mateo | cc9130b | 2014-07-24 17:04:42 +0100 | [diff] [blame] | 2017 | INIT_LIST_HEAD(&ring->execlist_queue); |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 2018 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2019 | ringbuf->size = 32 * PAGE_SIZE; |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 2020 | ringbuf->ring = ring; |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 2021 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 2022 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 2023 | init_waitqueue_head(&ring->irq_queue); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2024 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2025 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2026 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2027 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2028 | goto error; |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2029 | } else { |
| 2030 | BUG_ON(ring->id != RCS); |
Daniel Vetter | 035dc1e | 2013-07-03 12:56:54 +0200 | [diff] [blame] | 2031 | ret = init_phys_status_page(ring); |
Chris Wilson | 6b8294a | 2012-11-16 11:43:20 +0000 | [diff] [blame] | 2032 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2033 | goto error; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2034 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2035 | |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2036 | WARN_ON(ringbuf->obj); |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2037 | |
Daniel Vetter | bfc882b | 2014-11-20 00:33:08 +0100 | [diff] [blame] | 2038 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
| 2039 | if (ret) { |
| 2040 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", |
| 2041 | ring->name, ret); |
| 2042 | goto error; |
| 2043 | } |
| 2044 | |
| 2045 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
| 2046 | if (ret) { |
| 2047 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", |
| 2048 | ring->name, ret); |
| 2049 | intel_destroy_ringbuffer_obj(ringbuf); |
| 2050 | goto error; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2051 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2052 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 2053 | /* Workaround an erratum on the i830 which causes a hang if |
| 2054 | * the TAIL pointer points to within the last 2 cachelines |
| 2055 | * of the buffer. |
| 2056 | */ |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2057 | ringbuf->effective_size = ringbuf->size; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2058 | if (IS_I830(dev) || IS_845G(dev)) |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2059 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 2060 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2061 | ret = i915_cmd_parser_init_ring(ring); |
| 2062 | if (ret) |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2063 | goto error; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2064 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2065 | return 0; |
| 2066 | |
| 2067 | error: |
| 2068 | kfree(ringbuf); |
| 2069 | ring->buffer = NULL; |
| 2070 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2071 | } |
| 2072 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2073 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2074 | { |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2075 | struct drm_i915_private *dev_priv; |
| 2076 | struct intel_ringbuffer *ringbuf; |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2077 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2078 | if (!intel_ring_initialized(ring)) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2079 | return; |
| 2080 | |
John Harrison | 6402c33 | 2014-10-31 12:00:26 +0000 | [diff] [blame] | 2081 | dev_priv = to_i915(ring->dev); |
| 2082 | ringbuf = ring->buffer; |
| 2083 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2084 | intel_stop_ring_buffer(ring); |
Ville Syrjälä | de8f0a5 | 2014-05-28 19:12:13 +0300 | [diff] [blame] | 2085 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 2086 | |
Thomas Daniel | 7ba717c | 2014-11-13 10:28:56 +0000 | [diff] [blame] | 2087 | intel_unpin_ringbuffer_obj(ringbuf); |
Oscar Mateo | 2919d29 | 2014-07-03 16:28:02 +0100 | [diff] [blame] | 2088 | intel_destroy_ringbuffer_obj(ringbuf); |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2089 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2090 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2091 | if (ring->cleanup) |
| 2092 | ring->cleanup(ring); |
| 2093 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2094 | cleanup_status_page(ring); |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 2095 | |
| 2096 | i915_cmd_parser_fini_ring(ring); |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 2097 | i915_gem_batch_pool_fini(&ring->batch_pool); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2098 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2099 | kfree(ringbuf); |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 2100 | ring->buffer = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 2101 | } |
| 2102 | |
Chris Wilson | 595e1ee | 2015-04-07 16:20:51 +0100 | [diff] [blame] | 2103 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2104 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2105 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2106 | struct drm_i915_gem_request *request; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2107 | unsigned space; |
| 2108 | int ret; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2109 | |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 2110 | if (intel_ring_space(ringbuf) >= n) |
| 2111 | return 0; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2112 | |
| 2113 | list_for_each_entry(request, &ring->request_list, list) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2114 | space = __intel_ring_space(request->postfix, ringbuf->tail, |
| 2115 | ringbuf->size); |
| 2116 | if (space >= n) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2117 | break; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2118 | } |
| 2119 | |
Chris Wilson | 595e1ee | 2015-04-07 16:20:51 +0100 | [diff] [blame] | 2120 | if (WARN_ON(&request->list == &ring->request_list)) |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2121 | return -ENOSPC; |
| 2122 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2123 | ret = i915_wait_request(request); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2124 | if (ret) |
| 2125 | return ret; |
| 2126 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2127 | ringbuf->space = space; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2128 | return 0; |
| 2129 | } |
| 2130 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2131 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2132 | { |
| 2133 | uint32_t __iomem *virt; |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2134 | struct intel_ringbuffer *ringbuf = ring->buffer; |
| 2135 | int rem = ringbuf->size - ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2136 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2137 | if (ringbuf->space < rem) { |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2138 | int ret = ring_wait_for_space(ring, rem); |
| 2139 | if (ret) |
| 2140 | return ret; |
| 2141 | } |
| 2142 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2143 | virt = ringbuf->virtual_start + ringbuf->tail; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2144 | rem /= 4; |
| 2145 | while (rem--) |
| 2146 | iowrite32(MI_NOOP, virt++); |
| 2147 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2148 | ringbuf->tail = 0; |
Dave Gordon | ebd0fd4 | 2014-11-27 11:22:49 +0000 | [diff] [blame] | 2149 | intel_ring_update_space(ringbuf); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2150 | |
| 2151 | return 0; |
| 2152 | } |
| 2153 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2154 | int intel_ring_idle(struct intel_engine_cs *ring) |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2155 | { |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2156 | struct drm_i915_gem_request *req; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2157 | int ret; |
| 2158 | |
| 2159 | /* We need to add any requests required to flush the objects and ring */ |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2160 | if (ring->outstanding_lazy_request) { |
John Harrison | 9400ae5 | 2014-11-24 18:49:36 +0000 | [diff] [blame] | 2161 | ret = i915_add_request(ring); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2162 | if (ret) |
| 2163 | return ret; |
| 2164 | } |
| 2165 | |
| 2166 | /* Wait upon the last request to be completed */ |
| 2167 | if (list_empty(&ring->request_list)) |
| 2168 | return 0; |
| 2169 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 2170 | req = list_entry(ring->request_list.prev, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2171 | struct drm_i915_gem_request, |
| 2172 | list); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2173 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2174 | /* Make sure we do not trigger any retires */ |
| 2175 | return __i915_wait_request(req, |
| 2176 | atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter), |
| 2177 | to_i915(ring->dev)->mm.interruptible, |
| 2178 | NULL, NULL); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2179 | } |
| 2180 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2181 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2182 | { |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2183 | request->ringbuf = request->ring->buffer; |
John Harrison | 9eba5d4 | 2014-11-24 18:49:23 +0000 | [diff] [blame] | 2184 | return 0; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2185 | } |
| 2186 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2187 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2188 | int bytes) |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2189 | { |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2190 | struct intel_ringbuffer *ringbuf = ring->buffer; |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2191 | int ret; |
| 2192 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2193 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2194 | ret = intel_wrap_ring_buffer(ring); |
| 2195 | if (unlikely(ret)) |
| 2196 | return ret; |
| 2197 | } |
| 2198 | |
Oscar Mateo | 93b0a4e | 2014-05-22 14:13:36 +0100 | [diff] [blame] | 2199 | if (unlikely(ringbuf->space < bytes)) { |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2200 | ret = ring_wait_for_space(ring, bytes); |
| 2201 | if (unlikely(ret)) |
| 2202 | return ret; |
| 2203 | } |
| 2204 | |
Mika Kuoppala | cbcc80d | 2012-12-04 15:12:03 +0200 | [diff] [blame] | 2205 | return 0; |
| 2206 | } |
| 2207 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2208 | int intel_ring_begin(struct intel_engine_cs *ring, |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2209 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2210 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2211 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2212 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2213 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2214 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
| 2215 | dev_priv->mm.interruptible); |
Daniel Vetter | de2b998 | 2012-07-04 22:52:50 +0200 | [diff] [blame] | 2216 | if (ret) |
| 2217 | return ret; |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 2218 | |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2219 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
| 2220 | if (ret) |
| 2221 | return ret; |
| 2222 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2223 | /* Preallocate the olr before touching the ring */ |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2224 | ret = i915_gem_request_alloc(ring, ring->default_context); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2225 | if (ret) |
| 2226 | return ret; |
| 2227 | |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2228 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
Chris Wilson | 304d695 | 2014-01-02 14:32:35 +0000 | [diff] [blame] | 2229 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2230 | } |
| 2231 | |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2232 | /* Align the ring tail to a cacheline boundary */ |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2233 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2234 | { |
Oscar Mateo | ee1b1e5 | 2014-05-22 14:13:35 +0100 | [diff] [blame] | 2235 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2236 | int ret; |
| 2237 | |
| 2238 | if (num_dwords == 0) |
| 2239 | return 0; |
| 2240 | |
Chris Wilson | 18393f6 | 2014-04-09 09:19:40 +0100 | [diff] [blame] | 2241 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
Ville Syrjälä | 753b1ad | 2014-02-11 19:52:05 +0200 | [diff] [blame] | 2242 | ret = intel_ring_begin(ring, num_dwords); |
| 2243 | if (ret) |
| 2244 | return ret; |
| 2245 | |
| 2246 | while (num_dwords--) |
| 2247 | intel_ring_emit(ring, MI_NOOP); |
| 2248 | |
| 2249 | intel_ring_advance(ring); |
| 2250 | |
| 2251 | return 0; |
| 2252 | } |
| 2253 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2254 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2255 | { |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2256 | struct drm_device *dev = ring->dev; |
| 2257 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2258 | |
John Harrison | 6259cea | 2014-11-24 18:49:29 +0000 | [diff] [blame] | 2259 | BUG_ON(ring->outstanding_lazy_request); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2260 | |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2261 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2262 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
| 2263 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); |
Oscar Mateo | 3b2cc8a | 2014-06-11 16:17:16 +0100 | [diff] [blame] | 2264 | if (HAS_VEBOX(dev)) |
Ben Widawsky | 5020150 | 2013-08-12 16:53:03 -0700 | [diff] [blame] | 2265 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2266 | } |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 2267 | |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 2268 | ring->set_seqno(ring, seqno); |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2269 | ring->hangcheck.seqno = seqno; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2270 | } |
| 2271 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2272 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2273 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2274 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2275 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2276 | |
| 2277 | /* Every tail move must follow the sequence below */ |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2278 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2279 | /* Disable notification that the ring is IDLE. The GT |
| 2280 | * will then assume that it is busy and bring it out of rc6. |
| 2281 | */ |
| 2282 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 2283 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
| 2284 | |
| 2285 | /* Clear the context id. Here be magic! */ |
| 2286 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); |
| 2287 | |
| 2288 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2289 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2290 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
| 2291 | 50)) |
| 2292 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2293 | |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2294 | /* Now that the ring is fully powered up, update the tail */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2295 | I915_WRITE_TAIL(ring, value); |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2296 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
| 2297 | |
| 2298 | /* Let the ring send IDLE messages to the GT again, |
| 2299 | * and so let it sleep to conserve power when idle. |
| 2300 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2301 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
Chris Wilson | 12f5581 | 2012-07-05 17:14:01 +0100 | [diff] [blame] | 2302 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2303 | } |
| 2304 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2305 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2306 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2307 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2308 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2309 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2310 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2311 | ret = intel_ring_begin(ring, 4); |
| 2312 | if (ret) |
| 2313 | return ret; |
| 2314 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2315 | cmd = MI_FLUSH_DW; |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2316 | if (INTEL_INFO(ring->dev)->gen >= 8) |
| 2317 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2318 | |
| 2319 | /* We always require a command barrier so that subsequent |
| 2320 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2321 | * wrt the contents of the write cache being flushed to memory |
| 2322 | * (and thus being coherent from the CPU). |
| 2323 | */ |
| 2324 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2325 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2326 | /* |
| 2327 | * Bspec vol 1c.5 - video engine command streamer: |
| 2328 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2329 | * operation is complete. This bit is only valid when the |
| 2330 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2331 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2332 | if (invalidate & I915_GEM_GPU_DOMAINS) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2333 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 2334 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2335 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2336 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2337 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
| 2338 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2339 | intel_ring_emit(ring, 0); /* value */ |
| 2340 | } else { |
| 2341 | intel_ring_emit(ring, 0); |
| 2342 | intel_ring_emit(ring, MI_NOOP); |
| 2343 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2344 | intel_ring_advance(ring); |
| 2345 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2346 | } |
| 2347 | |
| 2348 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2349 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2350 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2351 | unsigned dispatch_flags) |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2352 | { |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2353 | bool ppgtt = USES_PPGTT(ring->dev) && |
| 2354 | !(dispatch_flags & I915_DISPATCH_SECURE); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2355 | int ret; |
| 2356 | |
| 2357 | ret = intel_ring_begin(ring, 4); |
| 2358 | if (ret) |
| 2359 | return ret; |
| 2360 | |
| 2361 | /* FIXME(BDW): Address space and security selectors. */ |
Ben Widawsky | 28cf541 | 2013-11-02 21:07:26 -0700 | [diff] [blame] | 2362 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2363 | intel_ring_emit(ring, lower_32_bits(offset)); |
| 2364 | intel_ring_emit(ring, upper_32_bits(offset)); |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2365 | intel_ring_emit(ring, MI_NOOP); |
| 2366 | intel_ring_advance(ring); |
| 2367 | |
| 2368 | return 0; |
| 2369 | } |
| 2370 | |
| 2371 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2372 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2373 | u64 offset, u32 len, |
| 2374 | unsigned dispatch_flags) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2375 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2376 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2377 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2378 | ret = intel_ring_begin(ring, 2); |
| 2379 | if (ret) |
| 2380 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 2381 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2382 | intel_ring_emit(ring, |
Chris Wilson | 7707225 | 2014-09-10 12:18:27 +0100 | [diff] [blame] | 2383 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2384 | (dispatch_flags & I915_DISPATCH_SECURE ? |
Chris Wilson | 7707225 | 2014-09-10 12:18:27 +0100 | [diff] [blame] | 2385 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2386 | /* bit0-7 is the length on GEN6+ */ |
| 2387 | intel_ring_emit(ring, offset); |
| 2388 | intel_ring_advance(ring); |
| 2389 | |
| 2390 | return 0; |
| 2391 | } |
| 2392 | |
| 2393 | static int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2394 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
Ben Widawsky | 9bcb144 | 2014-04-28 19:29:25 -0700 | [diff] [blame] | 2395 | u64 offset, u32 len, |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2396 | unsigned dispatch_flags) |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2397 | { |
| 2398 | int ret; |
| 2399 | |
| 2400 | ret = intel_ring_begin(ring, 2); |
| 2401 | if (ret) |
| 2402 | return ret; |
| 2403 | |
| 2404 | intel_ring_emit(ring, |
| 2405 | MI_BATCH_BUFFER_START | |
John Harrison | 8e004ef | 2015-02-13 11:48:10 +0000 | [diff] [blame] | 2406 | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 2407 | 0 : MI_BATCH_NON_SECURE_I965)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2408 | /* bit0-7 is the length on GEN6+ */ |
| 2409 | intel_ring_emit(ring, offset); |
| 2410 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 2411 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2412 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 2413 | } |
| 2414 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2415 | /* Blitter support (SandyBridge+) */ |
| 2416 | |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2417 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2418 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2419 | { |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2420 | struct drm_device *dev = ring->dev; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2421 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2422 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2423 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 2424 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2425 | if (ret) |
| 2426 | return ret; |
| 2427 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2428 | cmd = MI_FLUSH_DW; |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 2429 | if (INTEL_INFO(dev)->gen >= 8) |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2430 | cmd += 1; |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2431 | |
| 2432 | /* We always require a command barrier so that subsequent |
| 2433 | * commands, such as breadcrumb interrupts, are strictly ordered |
| 2434 | * wrt the contents of the write cache being flushed to memory |
| 2435 | * (and thus being coherent from the CPU). |
| 2436 | */ |
| 2437 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; |
| 2438 | |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2439 | /* |
| 2440 | * Bspec vol 1c.3 - blitter engine command streamer: |
| 2441 | * "If ENABLED, all TLBs will be invalidated once the flush |
| 2442 | * operation is complete. This bit is only valid when the |
| 2443 | * Post-Sync Operation field is a value of 1h or 3h." |
| 2444 | */ |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2445 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
Chris Wilson | f0a1fb1 | 2015-01-22 13:42:00 +0000 | [diff] [blame] | 2446 | cmd |= MI_INVALIDATE_TLB; |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 2447 | intel_ring_emit(ring, cmd); |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 2448 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
Paulo Zanoni | dbef0f1 | 2015-02-13 17:23:46 -0200 | [diff] [blame] | 2449 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 075b3bb | 2013-11-02 21:07:13 -0700 | [diff] [blame] | 2450 | intel_ring_emit(ring, 0); /* upper addr */ |
| 2451 | intel_ring_emit(ring, 0); /* value */ |
| 2452 | } else { |
| 2453 | intel_ring_emit(ring, 0); |
| 2454 | intel_ring_emit(ring, MI_NOOP); |
| 2455 | } |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2456 | intel_ring_advance(ring); |
Rodrigo Vivi | fd3da6c | 2013-06-06 16:58:16 -0300 | [diff] [blame] | 2457 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 2458 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 2459 | } |
| 2460 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2461 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 2462 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2463 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2464 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2465 | struct drm_i915_gem_object *obj; |
| 2466 | int ret; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2467 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2468 | ring->name = "render ring"; |
| 2469 | ring->id = RCS; |
| 2470 | ring->mmio_base = RENDER_RING_BASE; |
| 2471 | |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2472 | if (INTEL_INFO(dev)->gen >= 8) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2473 | if (i915_semaphore_is_enabled(dev)) { |
| 2474 | obj = i915_gem_alloc_object(dev, 4096); |
| 2475 | if (obj == NULL) { |
| 2476 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
| 2477 | i915.semaphores = 0; |
| 2478 | } else { |
| 2479 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
| 2480 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); |
| 2481 | if (ret != 0) { |
| 2482 | drm_gem_object_unreference(&obj->base); |
| 2483 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
| 2484 | i915.semaphores = 0; |
| 2485 | } else |
| 2486 | dev_priv->semaphore_obj = obj; |
| 2487 | } |
| 2488 | } |
Mika Kuoppala | 7225342 | 2014-10-07 17:21:26 +0300 | [diff] [blame] | 2489 | |
Daniel Vetter | 8f0e2b9 | 2014-12-02 16:19:07 +0100 | [diff] [blame] | 2490 | ring->init_context = intel_rcs_ctx_init; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2491 | ring->add_request = gen6_add_request; |
| 2492 | ring->flush = gen8_render_ring_flush; |
| 2493 | ring->irq_get = gen8_ring_get_irq; |
| 2494 | ring->irq_put = gen8_ring_put_irq; |
| 2495 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
| 2496 | ring->get_seqno = gen6_ring_get_seqno; |
| 2497 | ring->set_seqno = ring_set_seqno; |
| 2498 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2499 | WARN_ON(!dev_priv->semaphore_obj); |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2500 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2501 | ring->semaphore.signal = gen8_rcs_signal; |
| 2502 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2503 | } |
| 2504 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2505 | ring->add_request = gen6_add_request; |
Paulo Zanoni | 4772eae | 2012-08-17 18:35:41 -0300 | [diff] [blame] | 2506 | ring->flush = gen7_render_ring_flush; |
Chris Wilson | 6c6cf5a | 2012-07-20 18:02:28 +0100 | [diff] [blame] | 2507 | if (INTEL_INFO(dev)->gen == 6) |
Paulo Zanoni | b311150 | 2012-08-17 18:35:42 -0300 | [diff] [blame] | 2508 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2509 | ring->irq_get = gen6_ring_get_irq; |
| 2510 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2511 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 2512 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2513 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2514 | if (i915_semaphore_is_enabled(dev)) { |
| 2515 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2516 | ring->semaphore.signal = gen6_signal; |
| 2517 | /* |
| 2518 | * The current semaphore is only applied on pre-gen8 |
| 2519 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2520 | * platform. So the semaphore between RCS and VCS2 is |
| 2521 | * initialized as INVALID. Gen8 will initialize the |
| 2522 | * sema between VCS2 and RCS later. |
| 2523 | */ |
| 2524 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2525 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; |
| 2526 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; |
| 2527 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; |
| 2528 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2529 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; |
| 2530 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; |
| 2531 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; |
| 2532 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; |
| 2533 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2534 | } |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2535 | } else if (IS_GEN5(dev)) { |
| 2536 | ring->add_request = pc_render_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2537 | ring->flush = gen4_render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 2538 | ring->get_seqno = pc_render_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2539 | ring->set_seqno = pc_render_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2540 | ring->irq_get = gen5_ring_get_irq; |
| 2541 | ring->irq_put = gen5_ring_put_irq; |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2542 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
| 2543 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2544 | } else { |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2545 | ring->add_request = i9xx_add_request; |
Chris Wilson | 46f0f8d | 2012-04-18 11:12:11 +0100 | [diff] [blame] | 2546 | if (INTEL_INFO(dev)->gen < 4) |
| 2547 | ring->flush = gen2_render_ring_flush; |
| 2548 | else |
| 2549 | ring->flush = gen4_render_ring_flush; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2550 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2551 | ring->set_seqno = ring_set_seqno; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2552 | if (IS_GEN2(dev)) { |
| 2553 | ring->irq_get = i8xx_ring_get_irq; |
| 2554 | ring->irq_put = i8xx_ring_put_irq; |
| 2555 | } else { |
| 2556 | ring->irq_get = i9xx_ring_get_irq; |
| 2557 | ring->irq_put = i9xx_ring_put_irq; |
| 2558 | } |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2559 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2560 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2561 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2562 | |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2563 | if (IS_HASWELL(dev)) |
| 2564 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2565 | else if (IS_GEN8(dev)) |
| 2566 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 2567 | else if (INTEL_INFO(dev)->gen >= 6) |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2568 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
| 2569 | else if (INTEL_INFO(dev)->gen >= 4) |
| 2570 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
| 2571 | else if (IS_I830(dev) || IS_845G(dev)) |
| 2572 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; |
| 2573 | else |
| 2574 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 2575 | ring->init_hw = init_render_ring; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 2576 | ring->cleanup = render_ring_cleanup; |
| 2577 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2578 | /* Workaround batchbuffer to combat CS tlb bug. */ |
| 2579 | if (HAS_BROKEN_CS_TLB(dev)) { |
Chris Wilson | c4d69da | 2014-09-08 14:25:41 +0100 | [diff] [blame] | 2580 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2581 | if (obj == NULL) { |
| 2582 | DRM_ERROR("Failed to allocate batch bo\n"); |
| 2583 | return -ENOMEM; |
| 2584 | } |
| 2585 | |
Daniel Vetter | be1fa12 | 2014-02-14 14:01:14 +0100 | [diff] [blame] | 2586 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2587 | if (ret != 0) { |
| 2588 | drm_gem_object_unreference(&obj->base); |
| 2589 | DRM_ERROR("Failed to ping batch bo\n"); |
| 2590 | return ret; |
| 2591 | } |
| 2592 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 2593 | ring->scratch.obj = obj; |
| 2594 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2595 | } |
| 2596 | |
Daniel Vetter | 99be1df | 2014-11-20 00:33:06 +0100 | [diff] [blame] | 2597 | ret = intel_init_ring_buffer(dev, ring); |
| 2598 | if (ret) |
| 2599 | return ret; |
| 2600 | |
| 2601 | if (INTEL_INFO(dev)->gen >= 5) { |
| 2602 | ret = intel_init_pipe_control(ring); |
| 2603 | if (ret) |
| 2604 | return ret; |
| 2605 | } |
| 2606 | |
| 2607 | return 0; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2608 | } |
| 2609 | |
| 2610 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 2611 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2612 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2613 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2614 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2615 | ring->name = "bsd ring"; |
| 2616 | ring->id = VCS; |
| 2617 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2618 | ring->write_tail = ring_write_tail; |
Ben Widawsky | 780f18c | 2013-11-02 21:07:28 -0700 | [diff] [blame] | 2619 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2620 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame] | 2621 | /* gen6 bsd needs a special wa for tail updates */ |
| 2622 | if (IS_GEN6(dev)) |
| 2623 | ring->write_tail = gen6_bsd_ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2624 | ring->flush = gen6_bsd_ring_flush; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2625 | ring->add_request = gen6_add_request; |
| 2626 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2627 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2628 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2629 | ring->irq_enable_mask = |
| 2630 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
| 2631 | ring->irq_get = gen8_ring_get_irq; |
| 2632 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2633 | ring->dispatch_execbuffer = |
| 2634 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2635 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2636 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2637 | ring->semaphore.signal = gen8_xcs_signal; |
| 2638 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2639 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2640 | } else { |
| 2641 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
| 2642 | ring->irq_get = gen6_ring_get_irq; |
| 2643 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2644 | ring->dispatch_execbuffer = |
| 2645 | gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2646 | if (i915_semaphore_is_enabled(dev)) { |
| 2647 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2648 | ring->semaphore.signal = gen6_signal; |
| 2649 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
| 2650 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2651 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; |
| 2652 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; |
| 2653 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2654 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; |
| 2655 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; |
| 2656 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; |
| 2657 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; |
| 2658 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2659 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2660 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2661 | } else { |
| 2662 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2663 | ring->flush = bsd_ring_flush; |
Daniel Vetter | 8620a3a | 2012-04-11 22:12:57 +0200 | [diff] [blame] | 2664 | ring->add_request = i9xx_add_request; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2665 | ring->get_seqno = ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2666 | ring->set_seqno = ring_set_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2667 | if (IS_GEN5(dev)) { |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 2668 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2669 | ring->irq_get = gen5_ring_get_irq; |
| 2670 | ring->irq_put = gen5_ring_put_irq; |
| 2671 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 2672 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 2673 | ring->irq_get = i9xx_ring_get_irq; |
| 2674 | ring->irq_put = i9xx_ring_put_irq; |
| 2675 | } |
Daniel Vetter | fb3256d | 2012-04-11 22:12:56 +0200 | [diff] [blame] | 2676 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2677 | } |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 2678 | ring->init_hw = init_ring_common; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 2679 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2680 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 2681 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2682 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2683 | /** |
Damien Lespiau | 6265992 | 2015-01-29 14:13:40 +0000 | [diff] [blame] | 2684 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2685 | */ |
| 2686 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) |
| 2687 | { |
| 2688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2689 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2690 | |
Rodrigo Vivi | f7b6423 | 2014-07-01 02:41:36 -0700 | [diff] [blame] | 2691 | ring->name = "bsd2 ring"; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2692 | ring->id = VCS2; |
| 2693 | |
| 2694 | ring->write_tail = ring_write_tail; |
| 2695 | ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 2696 | ring->flush = gen6_bsd_ring_flush; |
| 2697 | ring->add_request = gen6_add_request; |
| 2698 | ring->get_seqno = gen6_ring_get_seqno; |
| 2699 | ring->set_seqno = ring_set_seqno; |
| 2700 | ring->irq_enable_mask = |
| 2701 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
| 2702 | ring->irq_get = gen8_ring_get_irq; |
| 2703 | ring->irq_put = gen8_ring_put_irq; |
| 2704 | ring->dispatch_execbuffer = |
| 2705 | gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2706 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2707 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2708 | ring->semaphore.signal = gen8_xcs_signal; |
| 2709 | GEN8_RING_SEMAPHORE_INIT; |
| 2710 | } |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 2711 | ring->init_hw = init_ring_common; |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 2712 | |
| 2713 | return intel_init_ring_buffer(dev, ring); |
| 2714 | } |
| 2715 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2716 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 2717 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2718 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2719 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2720 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2721 | ring->name = "blitter ring"; |
| 2722 | ring->id = BCS; |
| 2723 | |
| 2724 | ring->mmio_base = BLT_RING_BASE; |
| 2725 | ring->write_tail = ring_write_tail; |
Ben Widawsky | ea25132 | 2013-05-28 19:22:21 -0700 | [diff] [blame] | 2726 | ring->flush = gen6_ring_flush; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 2727 | ring->add_request = gen6_add_request; |
| 2728 | ring->get_seqno = gen6_ring_get_seqno; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 2729 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2730 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2731 | ring->irq_enable_mask = |
| 2732 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
| 2733 | ring->irq_get = gen8_ring_get_irq; |
| 2734 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2735 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2736 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2737 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2738 | ring->semaphore.signal = gen8_xcs_signal; |
| 2739 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2740 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2741 | } else { |
| 2742 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
| 2743 | ring->irq_get = gen6_ring_get_irq; |
| 2744 | ring->irq_put = gen6_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2745 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2746 | if (i915_semaphore_is_enabled(dev)) { |
| 2747 | ring->semaphore.signal = gen6_signal; |
| 2748 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2749 | /* |
| 2750 | * The current semaphore is only applied on pre-gen8 |
| 2751 | * platform. And there is no VCS2 ring on the pre-gen8 |
| 2752 | * platform. So the semaphore between BCS and VCS2 is |
| 2753 | * initialized as INVALID. Gen8 will initialize the |
| 2754 | * sema between BCS and VCS2 later. |
| 2755 | */ |
| 2756 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
| 2757 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; |
| 2758 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2759 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; |
| 2760 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2761 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; |
| 2762 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; |
| 2763 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; |
| 2764 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; |
| 2765 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2766 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2767 | } |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 2768 | ring->init_hw = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2769 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2770 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2771 | } |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2772 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2773 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
| 2774 | { |
Jani Nikula | 4640c4f | 2014-03-31 14:27:19 +0300 | [diff] [blame] | 2775 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2776 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2777 | |
| 2778 | ring->name = "video enhancement ring"; |
| 2779 | ring->id = VECS; |
| 2780 | |
| 2781 | ring->mmio_base = VEBOX_RING_BASE; |
| 2782 | ring->write_tail = ring_write_tail; |
| 2783 | ring->flush = gen6_ring_flush; |
| 2784 | ring->add_request = gen6_add_request; |
| 2785 | ring->get_seqno = gen6_ring_get_seqno; |
| 2786 | ring->set_seqno = ring_set_seqno; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2787 | |
| 2788 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2789 | ring->irq_enable_mask = |
Daniel Vetter | 40c499f | 2013-11-07 21:40:39 -0800 | [diff] [blame] | 2790 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2791 | ring->irq_get = gen8_ring_get_irq; |
| 2792 | ring->irq_put = gen8_ring_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2793 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2794 | if (i915_semaphore_is_enabled(dev)) { |
Ben Widawsky | 5ee426c | 2014-06-30 09:53:38 -0700 | [diff] [blame] | 2795 | ring->semaphore.sync_to = gen8_ring_sync; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 2796 | ring->semaphore.signal = gen8_xcs_signal; |
| 2797 | GEN8_RING_SEMAPHORE_INIT; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2798 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2799 | } else { |
| 2800 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
| 2801 | ring->irq_get = hsw_vebox_get_irq; |
| 2802 | ring->irq_put = hsw_vebox_put_irq; |
Ben Widawsky | 1c7a062 | 2013-11-02 21:07:12 -0700 | [diff] [blame] | 2803 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Ben Widawsky | 707d9cf | 2014-06-30 09:53:36 -0700 | [diff] [blame] | 2804 | if (i915_semaphore_is_enabled(dev)) { |
| 2805 | ring->semaphore.sync_to = gen6_ring_sync; |
| 2806 | ring->semaphore.signal = gen6_signal; |
| 2807 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
| 2808 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; |
| 2809 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; |
| 2810 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; |
| 2811 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; |
| 2812 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; |
| 2813 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; |
| 2814 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; |
| 2815 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; |
| 2816 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; |
| 2817 | } |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2818 | } |
Daniel Vetter | ecfe00d | 2014-11-20 00:33:04 +0100 | [diff] [blame] | 2819 | ring->init_hw = init_ring_common; |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 2820 | |
| 2821 | return intel_init_ring_buffer(dev, ring); |
| 2822 | } |
| 2823 | |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2824 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2825 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2826 | { |
| 2827 | int ret; |
| 2828 | |
| 2829 | if (!ring->gpu_caches_dirty) |
| 2830 | return 0; |
| 2831 | |
| 2832 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2833 | if (ret) |
| 2834 | return ret; |
| 2835 | |
| 2836 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); |
| 2837 | |
| 2838 | ring->gpu_caches_dirty = false; |
| 2839 | return 0; |
| 2840 | } |
| 2841 | |
| 2842 | int |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2843 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2844 | { |
| 2845 | uint32_t flush_domains; |
| 2846 | int ret; |
| 2847 | |
| 2848 | flush_domains = 0; |
| 2849 | if (ring->gpu_caches_dirty) |
| 2850 | flush_domains = I915_GEM_GPU_DOMAINS; |
| 2851 | |
| 2852 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2853 | if (ret) |
| 2854 | return ret; |
| 2855 | |
| 2856 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); |
| 2857 | |
| 2858 | ring->gpu_caches_dirty = false; |
| 2859 | return 0; |
| 2860 | } |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2861 | |
| 2862 | void |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 2863 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 2864 | { |
| 2865 | int ret; |
| 2866 | |
| 2867 | if (!intel_ring_initialized(ring)) |
| 2868 | return; |
| 2869 | |
| 2870 | ret = intel_ring_idle(ring); |
| 2871 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) |
| 2872 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 2873 | ring->name, ret); |
| 2874 | |
| 2875 | stop_ring(ring); |
| 2876 | } |