Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
| 34 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 36 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 39 | static const u32 hpd_ibx[] = { |
| 40 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 41 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 42 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 43 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 44 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 45 | }; |
| 46 | |
| 47 | static const u32 hpd_cpt[] = { |
| 48 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 49 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 50 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 51 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 52 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 53 | }; |
| 54 | |
| 55 | static const u32 hpd_mask_i915[] = { |
| 56 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 57 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 58 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 59 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 60 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 61 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 62 | }; |
| 63 | |
| 64 | static const u32 hpd_status_gen4[] = { |
| 65 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 71 | }; |
| 72 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 73 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
| 74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 80 | }; |
| 81 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 82 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 83 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 84 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 85 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 86 | assert_spin_locked(&dev_priv->irq_lock); |
| 87 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 88 | if ((dev_priv->irq_mask & mask) != 0) { |
| 89 | dev_priv->irq_mask &= ~mask; |
| 90 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 91 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 92 | } |
| 93 | } |
| 94 | |
Paulo Zanoni | 0ff9800 | 2013-02-22 17:05:31 -0300 | [diff] [blame] | 95 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 96 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 97 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 98 | assert_spin_locked(&dev_priv->irq_lock); |
| 99 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 100 | if ((dev_priv->irq_mask & mask) != mask) { |
| 101 | dev_priv->irq_mask |= mask; |
| 102 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 103 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 104 | } |
| 105 | } |
| 106 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 107 | /** |
| 108 | * ilk_update_gt_irq - update GTIMR |
| 109 | * @dev_priv: driver private |
| 110 | * @interrupt_mask: mask of interrupt bits to update |
| 111 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 112 | */ |
| 113 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 114 | uint32_t interrupt_mask, |
| 115 | uint32_t enabled_irq_mask) |
| 116 | { |
| 117 | assert_spin_locked(&dev_priv->irq_lock); |
| 118 | |
| 119 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 120 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 121 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 122 | POSTING_READ(GTIMR); |
| 123 | } |
| 124 | |
| 125 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 126 | { |
| 127 | ilk_update_gt_irq(dev_priv, mask, mask); |
| 128 | } |
| 129 | |
| 130 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 131 | { |
| 132 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 133 | } |
| 134 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame^] | 135 | /** |
| 136 | * snb_update_pm_irq - update GEN6_PMIMR |
| 137 | * @dev_priv: driver private |
| 138 | * @interrupt_mask: mask of interrupt bits to update |
| 139 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 140 | */ |
| 141 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 142 | uint32_t interrupt_mask, |
| 143 | uint32_t enabled_irq_mask) |
| 144 | { |
| 145 | uint32_t pmimr = I915_READ(GEN6_PMIMR); |
| 146 | pmimr &= ~interrupt_mask; |
| 147 | pmimr |= (~enabled_irq_mask & interrupt_mask); |
| 148 | |
| 149 | assert_spin_locked(&dev_priv->irq_lock); |
| 150 | |
| 151 | I915_WRITE(GEN6_PMIMR, pmimr); |
| 152 | POSTING_READ(GEN6_PMIMR); |
| 153 | } |
| 154 | |
| 155 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 156 | { |
| 157 | snb_update_pm_irq(dev_priv, mask, mask); |
| 158 | } |
| 159 | |
| 160 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 161 | { |
| 162 | snb_update_pm_irq(dev_priv, mask, 0); |
| 163 | } |
| 164 | |
| 165 | static void snb_set_pm_irq(struct drm_i915_private *dev_priv, uint32_t val) |
| 166 | { |
| 167 | snb_update_pm_irq(dev_priv, 0xffffffff, ~val); |
| 168 | } |
| 169 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 170 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
| 171 | { |
| 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 173 | struct intel_crtc *crtc; |
| 174 | enum pipe pipe; |
| 175 | |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 176 | assert_spin_locked(&dev_priv->irq_lock); |
| 177 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 178 | for_each_pipe(pipe) { |
| 179 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 180 | |
| 181 | if (crtc->cpu_fifo_underrun_disabled) |
| 182 | return false; |
| 183 | } |
| 184 | |
| 185 | return true; |
| 186 | } |
| 187 | |
| 188 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
| 189 | { |
| 190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 191 | enum pipe pipe; |
| 192 | struct intel_crtc *crtc; |
| 193 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 194 | assert_spin_locked(&dev_priv->irq_lock); |
| 195 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 196 | for_each_pipe(pipe) { |
| 197 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 198 | |
| 199 | if (crtc->pch_fifo_underrun_disabled) |
| 200 | return false; |
| 201 | } |
| 202 | |
| 203 | return true; |
| 204 | } |
| 205 | |
| 206 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
| 207 | enum pipe pipe, bool enable) |
| 208 | { |
| 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 210 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
| 211 | DE_PIPEB_FIFO_UNDERRUN; |
| 212 | |
| 213 | if (enable) |
| 214 | ironlake_enable_display_irq(dev_priv, bit); |
| 215 | else |
| 216 | ironlake_disable_display_irq(dev_priv, bit); |
| 217 | } |
| 218 | |
| 219 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 220 | enum pipe pipe, bool enable) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 221 | { |
| 222 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 223 | if (enable) { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 224 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
| 225 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 226 | if (!ivb_can_enable_err_int(dev)) |
| 227 | return; |
| 228 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 229 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 230 | } else { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 231 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
| 232 | |
| 233 | /* Change the state _after_ we've read out the current one. */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 234 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 235 | |
| 236 | if (!was_enabled && |
| 237 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { |
| 238 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", |
| 239 | pipe_name(pipe)); |
| 240 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 241 | } |
| 242 | } |
| 243 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 244 | /** |
| 245 | * ibx_display_interrupt_update - update SDEIMR |
| 246 | * @dev_priv: driver private |
| 247 | * @interrupt_mask: mask of interrupt bits to update |
| 248 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 249 | */ |
| 250 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 251 | uint32_t interrupt_mask, |
| 252 | uint32_t enabled_irq_mask) |
| 253 | { |
| 254 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 255 | sdeimr &= ~interrupt_mask; |
| 256 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 257 | |
| 258 | assert_spin_locked(&dev_priv->irq_lock); |
| 259 | |
| 260 | I915_WRITE(SDEIMR, sdeimr); |
| 261 | POSTING_READ(SDEIMR); |
| 262 | } |
| 263 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
| 264 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
| 265 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
| 266 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
| 267 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 268 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 269 | enum transcoder pch_transcoder, |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 270 | bool enable) |
| 271 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 272 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 273 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
| 274 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 275 | |
| 276 | if (enable) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 277 | ibx_enable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 278 | else |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 279 | ibx_disable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
| 283 | enum transcoder pch_transcoder, |
| 284 | bool enable) |
| 285 | { |
| 286 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 287 | |
| 288 | if (enable) { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 289 | I915_WRITE(SERR_INT, |
| 290 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
| 291 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 292 | if (!cpt_can_enable_serr_int(dev)) |
| 293 | return; |
| 294 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 295 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 296 | } else { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 297 | uint32_t tmp = I915_READ(SERR_INT); |
| 298 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); |
| 299 | |
| 300 | /* Change the state _after_ we've read out the current one. */ |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 301 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 302 | |
| 303 | if (!was_enabled && |
| 304 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { |
| 305 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", |
| 306 | transcoder_name(pch_transcoder)); |
| 307 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 308 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | /** |
| 312 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 313 | * @dev: drm device |
| 314 | * @pipe: pipe |
| 315 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 316 | * |
| 317 | * This function makes us disable or enable CPU fifo underruns for a specific |
| 318 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun |
| 319 | * reporting for one pipe may also disable all the other CPU error interruts for |
| 320 | * the other pipes, due to the fact that there's just one interrupt mask/enable |
| 321 | * bit for all the pipes. |
| 322 | * |
| 323 | * Returns the previous state of underrun reporting. |
| 324 | */ |
| 325 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 326 | enum pipe pipe, bool enable) |
| 327 | { |
| 328 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 329 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 330 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 331 | unsigned long flags; |
| 332 | bool ret; |
| 333 | |
| 334 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 335 | |
| 336 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
| 337 | |
| 338 | if (enable == ret) |
| 339 | goto done; |
| 340 | |
| 341 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
| 342 | |
| 343 | if (IS_GEN5(dev) || IS_GEN6(dev)) |
| 344 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
| 345 | else if (IS_GEN7(dev)) |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 346 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 347 | |
| 348 | done: |
| 349 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 350 | return ret; |
| 351 | } |
| 352 | |
| 353 | /** |
| 354 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 355 | * @dev: drm device |
| 356 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
| 357 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 358 | * |
| 359 | * This function makes us disable or enable PCH fifo underruns for a specific |
| 360 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
| 361 | * underrun reporting for one transcoder may also disable all the other PCH |
| 362 | * error interruts for the other transcoders, due to the fact that there's just |
| 363 | * one interrupt mask/enable bit for all the transcoders. |
| 364 | * |
| 365 | * Returns the previous state of underrun reporting. |
| 366 | */ |
| 367 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 368 | enum transcoder pch_transcoder, |
| 369 | bool enable) |
| 370 | { |
| 371 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 372 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
| 373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 374 | unsigned long flags; |
| 375 | bool ret; |
| 376 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 377 | /* |
| 378 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
| 379 | * has only one pch transcoder A that all pipes can use. To avoid racy |
| 380 | * pch transcoder -> pipe lookups from interrupt code simply store the |
| 381 | * underrun statistics in crtc A. Since we never expose this anywhere |
| 382 | * nor use it outside of the fifo underrun code here using the "wrong" |
| 383 | * crtc on LPT won't cause issues. |
| 384 | */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 385 | |
| 386 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 387 | |
| 388 | ret = !intel_crtc->pch_fifo_underrun_disabled; |
| 389 | |
| 390 | if (enable == ret) |
| 391 | goto done; |
| 392 | |
| 393 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
| 394 | |
| 395 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 396 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 397 | else |
| 398 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
| 399 | |
| 400 | done: |
| 401 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 402 | return ret; |
| 403 | } |
| 404 | |
| 405 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 406 | void |
| 407 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 408 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 409 | u32 reg = PIPESTAT(pipe); |
| 410 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 411 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 412 | assert_spin_locked(&dev_priv->irq_lock); |
| 413 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 414 | if ((pipestat & mask) == mask) |
| 415 | return; |
| 416 | |
| 417 | /* Enable the interrupt, clear any pending status */ |
| 418 | pipestat |= mask | (mask >> 16); |
| 419 | I915_WRITE(reg, pipestat); |
| 420 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | void |
| 424 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 425 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 426 | u32 reg = PIPESTAT(pipe); |
| 427 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 428 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 429 | assert_spin_locked(&dev_priv->irq_lock); |
| 430 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 431 | if ((pipestat & mask) == 0) |
| 432 | return; |
| 433 | |
| 434 | pipestat &= ~mask; |
| 435 | I915_WRITE(reg, pipestat); |
| 436 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 437 | } |
| 438 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 439 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 440 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 441 | */ |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 442 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 443 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 444 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 445 | unsigned long irqflags; |
| 446 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 447 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
| 448 | return; |
| 449 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 450 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 451 | |
Jani Nikula | f898780 | 2013-04-29 13:02:53 +0300 | [diff] [blame] | 452 | i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); |
| 453 | if (INTEL_INFO(dev)->gen >= 4) |
| 454 | i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 455 | |
| 456 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 460 | * i915_pipe_enabled - check if a pipe is enabled |
| 461 | * @dev: DRM device |
| 462 | * @pipe: pipe to check |
| 463 | * |
| 464 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 465 | * Use this routine to make sure the PLL is running and the pipe is active |
| 466 | * before reading such registers if unsure. |
| 467 | */ |
| 468 | static int |
| 469 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 470 | { |
| 471 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 472 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 473 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 474 | /* Locking is horribly broken here, but whatever. */ |
| 475 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 476 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 71f8ba6 | 2013-05-03 12:15:39 -0300 | [diff] [blame] | 477 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 478 | return intel_crtc->active; |
| 479 | } else { |
| 480 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
| 481 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 482 | } |
| 483 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 484 | /* Called from drm generic code, passed a 'crtc', which |
| 485 | * we use as a pipe index |
| 486 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 487 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 488 | { |
| 489 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 490 | unsigned long high_frame; |
| 491 | unsigned long low_frame; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 492 | u32 high1, high2, low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 493 | |
| 494 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 495 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 496 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 497 | return 0; |
| 498 | } |
| 499 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 500 | high_frame = PIPEFRAME(pipe); |
| 501 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 502 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 503 | /* |
| 504 | * High & low register fields aren't synchronized, so make sure |
| 505 | * we get a low value that's stable across two reads of the high |
| 506 | * register. |
| 507 | */ |
| 508 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 509 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
| 510 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; |
| 511 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 512 | } while (high1 != high2); |
| 513 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 514 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
| 515 | low >>= PIPE_FRAME_LOW_SHIFT; |
| 516 | return (high1 << 8) | low; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 517 | } |
| 518 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 519 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 520 | { |
| 521 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 522 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 523 | |
| 524 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 525 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 526 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | return I915_READ(reg); |
| 531 | } |
| 532 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 533 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 534 | int *vpos, int *hpos) |
| 535 | { |
| 536 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 537 | u32 vbl = 0, position = 0; |
| 538 | int vbl_start, vbl_end, htotal, vtotal; |
| 539 | bool in_vbl = true; |
| 540 | int ret = 0; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 541 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 542 | pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 543 | |
| 544 | if (!i915_pipe_enabled(dev, pipe)) { |
| 545 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 546 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | /* Get vtotal. */ |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 551 | vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 552 | |
| 553 | if (INTEL_INFO(dev)->gen >= 4) { |
| 554 | /* No obvious pixelcount register. Only query vertical |
| 555 | * scanout position from Display scan line register. |
| 556 | */ |
| 557 | position = I915_READ(PIPEDSL(pipe)); |
| 558 | |
| 559 | /* Decode into vertical scanout position. Don't have |
| 560 | * horizontal scanout position. |
| 561 | */ |
| 562 | *vpos = position & 0x1fff; |
| 563 | *hpos = 0; |
| 564 | } else { |
| 565 | /* Have access to pixelcount since start of frame. |
| 566 | * We can split this into vertical and horizontal |
| 567 | * scanout position. |
| 568 | */ |
| 569 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
| 570 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 571 | htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 572 | *vpos = position / htotal; |
| 573 | *hpos = position - (*vpos * htotal); |
| 574 | } |
| 575 | |
| 576 | /* Query vblank area. */ |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 577 | vbl = I915_READ(VBLANK(cpu_transcoder)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 578 | |
| 579 | /* Test position against vblank region. */ |
| 580 | vbl_start = vbl & 0x1fff; |
| 581 | vbl_end = (vbl >> 16) & 0x1fff; |
| 582 | |
| 583 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) |
| 584 | in_vbl = false; |
| 585 | |
| 586 | /* Inside "upper part" of vblank area? Apply corrective offset: */ |
| 587 | if (in_vbl && (*vpos >= vbl_start)) |
| 588 | *vpos = *vpos - vtotal; |
| 589 | |
| 590 | /* Readouts valid? */ |
| 591 | if (vbl > 0) |
| 592 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 593 | |
| 594 | /* In vblank? */ |
| 595 | if (in_vbl) |
| 596 | ret |= DRM_SCANOUTPOS_INVBL; |
| 597 | |
| 598 | return ret; |
| 599 | } |
| 600 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 601 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 602 | int *max_error, |
| 603 | struct timeval *vblank_time, |
| 604 | unsigned flags) |
| 605 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 606 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 607 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 608 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 609 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 610 | return -EINVAL; |
| 611 | } |
| 612 | |
| 613 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 614 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 615 | if (crtc == NULL) { |
| 616 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 617 | return -EINVAL; |
| 618 | } |
| 619 | |
| 620 | if (!crtc->enabled) { |
| 621 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 622 | return -EBUSY; |
| 623 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 624 | |
| 625 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 626 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 627 | vblank_time, flags, |
| 628 | crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 629 | } |
| 630 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 631 | static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector) |
| 632 | { |
| 633 | enum drm_connector_status old_status; |
| 634 | |
| 635 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 636 | old_status = connector->status; |
| 637 | |
| 638 | connector->status = connector->funcs->detect(connector, false); |
| 639 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n", |
| 640 | connector->base.id, |
| 641 | drm_get_connector_name(connector), |
| 642 | old_status, connector->status); |
| 643 | return (old_status != connector->status); |
| 644 | } |
| 645 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 646 | /* |
| 647 | * Handle hotplug events outside the interrupt handler proper. |
| 648 | */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 649 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
| 650 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 651 | static void i915_hotplug_work_func(struct work_struct *work) |
| 652 | { |
| 653 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 654 | hotplug_work); |
| 655 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 656 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 657 | struct intel_connector *intel_connector; |
| 658 | struct intel_encoder *intel_encoder; |
| 659 | struct drm_connector *connector; |
| 660 | unsigned long irqflags; |
| 661 | bool hpd_disabled = false; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 662 | bool changed = false; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 663 | u32 hpd_event_bits; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 664 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 665 | /* HPD irq before everything is fully set up. */ |
| 666 | if (!dev_priv->enable_hotplug_processing) |
| 667 | return; |
| 668 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 669 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 670 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 671 | |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 672 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 673 | |
| 674 | hpd_event_bits = dev_priv->hpd_event_bits; |
| 675 | dev_priv->hpd_event_bits = 0; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 676 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 677 | intel_connector = to_intel_connector(connector); |
| 678 | intel_encoder = intel_connector->encoder; |
| 679 | if (intel_encoder->hpd_pin > HPD_NONE && |
| 680 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && |
| 681 | connector->polled == DRM_CONNECTOR_POLL_HPD) { |
| 682 | DRM_INFO("HPD interrupt storm detected on connector %s: " |
| 683 | "switching from hotplug detection to polling\n", |
| 684 | drm_get_connector_name(connector)); |
| 685 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
| 686 | connector->polled = DRM_CONNECTOR_POLL_CONNECT |
| 687 | | DRM_CONNECTOR_POLL_DISCONNECT; |
| 688 | hpd_disabled = true; |
| 689 | } |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 690 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 691 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", |
| 692 | drm_get_connector_name(connector), intel_encoder->hpd_pin); |
| 693 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 694 | } |
| 695 | /* if there were no outputs to poll, poll was disabled, |
| 696 | * therefore make sure it's enabled when disabling HPD on |
| 697 | * some connectors */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 698 | if (hpd_disabled) { |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 699 | drm_kms_helper_poll_enable(dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 700 | mod_timer(&dev_priv->hotplug_reenable_timer, |
| 701 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
| 702 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 703 | |
| 704 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 705 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 706 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 707 | intel_connector = to_intel_connector(connector); |
| 708 | intel_encoder = intel_connector->encoder; |
| 709 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 710 | if (intel_encoder->hot_plug) |
| 711 | intel_encoder->hot_plug(intel_encoder); |
| 712 | if (intel_hpd_irq_event(dev, connector)) |
| 713 | changed = true; |
| 714 | } |
| 715 | } |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 716 | mutex_unlock(&mode_config->mutex); |
| 717 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 718 | if (changed) |
| 719 | drm_kms_helper_hotplug_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 720 | } |
| 721 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 722 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 723 | { |
| 724 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 725 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 726 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 727 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 728 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 729 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 730 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 731 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 732 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 733 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 734 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 735 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 736 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 737 | max_avg = I915_READ(RCBMAXAVG); |
| 738 | min_avg = I915_READ(RCBMINAVG); |
| 739 | |
| 740 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 741 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 742 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 743 | new_delay = dev_priv->ips.cur_delay - 1; |
| 744 | if (new_delay < dev_priv->ips.max_delay) |
| 745 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 746 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 747 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 748 | new_delay = dev_priv->ips.cur_delay + 1; |
| 749 | if (new_delay > dev_priv->ips.min_delay) |
| 750 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 751 | } |
| 752 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 753 | if (ironlake_set_drps(dev, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 754 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 755 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 756 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 757 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 758 | return; |
| 759 | } |
| 760 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 761 | static void notify_ring(struct drm_device *dev, |
| 762 | struct intel_ring_buffer *ring) |
| 763 | { |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 764 | if (ring->obj == NULL) |
| 765 | return; |
| 766 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 767 | trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 768 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 769 | wake_up_all(&ring->irq_queue); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 770 | i915_queue_hangcheck(dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 771 | } |
| 772 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 773 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 774 | { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 775 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 776 | rps.work); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame^] | 777 | u32 pm_iir; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 778 | u8 new_delay; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 779 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 780 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 781 | pm_iir = dev_priv->rps.pm_iir; |
| 782 | dev_priv->rps.pm_iir = 0; |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 783 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame^] | 784 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 785 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 786 | |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 787 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 788 | return; |
| 789 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 790 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 791 | |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 792 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 793 | new_delay = dev_priv->rps.cur_delay + 1; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 794 | |
| 795 | /* |
| 796 | * For better performance, jump directly |
| 797 | * to RPe if we're below it. |
| 798 | */ |
| 799 | if (IS_VALLEYVIEW(dev_priv->dev) && |
| 800 | dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay) |
| 801 | new_delay = dev_priv->rps.rpe_delay; |
| 802 | } else |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 803 | new_delay = dev_priv->rps.cur_delay - 1; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 804 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 805 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 806 | * interrupt |
| 807 | */ |
Ville Syrjälä | d8289c9 | 2013-06-25 19:21:05 +0300 | [diff] [blame] | 808 | if (new_delay >= dev_priv->rps.min_delay && |
| 809 | new_delay <= dev_priv->rps.max_delay) { |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 810 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 811 | valleyview_set_rps(dev_priv->dev, new_delay); |
| 812 | else |
| 813 | gen6_set_rps(dev_priv->dev, new_delay); |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 814 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 815 | |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 816 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 817 | /* |
| 818 | * On VLV, when we enter RC6 we may not be at the minimum |
| 819 | * voltage level, so arm a timer to check. It should only |
| 820 | * fire when there's activity or once after we've entered |
| 821 | * RC6, and then won't be re-armed until the next RPS interrupt. |
| 822 | */ |
| 823 | mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work, |
| 824 | msecs_to_jiffies(100)); |
| 825 | } |
| 826 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 827 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 828 | } |
| 829 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 830 | |
| 831 | /** |
| 832 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 833 | * occurred. |
| 834 | * @work: workqueue struct |
| 835 | * |
| 836 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 837 | * this event, userspace should try to remap the bad rows since statistically |
| 838 | * it is likely the same row is more likely to go bad again. |
| 839 | */ |
| 840 | static void ivybridge_parity_work(struct work_struct *work) |
| 841 | { |
| 842 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 843 | l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 844 | u32 error_status, row, bank, subbank; |
| 845 | char *parity_event[5]; |
| 846 | uint32_t misccpctl; |
| 847 | unsigned long flags; |
| 848 | |
| 849 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 850 | * In order to prevent a get/put style interface, acquire struct mutex |
| 851 | * any time we access those registers. |
| 852 | */ |
| 853 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 854 | |
| 855 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 856 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 857 | POSTING_READ(GEN7_MISCCPCTL); |
| 858 | |
| 859 | error_status = I915_READ(GEN7_L3CDERRST1); |
| 860 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 861 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 862 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 863 | |
| 864 | I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | |
| 865 | GEN7_L3CDERRST1_ENABLE); |
| 866 | POSTING_READ(GEN7_L3CDERRST1); |
| 867 | |
| 868 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 869 | |
| 870 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 871 | ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 872 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 873 | |
| 874 | mutex_unlock(&dev_priv->dev->struct_mutex); |
| 875 | |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 876 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 877 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 878 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 879 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 880 | parity_event[4] = NULL; |
| 881 | |
| 882 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, |
| 883 | KOBJ_CHANGE, parity_event); |
| 884 | |
| 885 | DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", |
| 886 | row, bank, subbank); |
| 887 | |
| 888 | kfree(parity_event[3]); |
| 889 | kfree(parity_event[2]); |
| 890 | kfree(parity_event[1]); |
| 891 | } |
| 892 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 893 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 894 | { |
| 895 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 896 | |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 897 | if (!HAS_L3_GPU_CACHE(dev)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 898 | return; |
| 899 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 900 | spin_lock(&dev_priv->irq_lock); |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 901 | ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 902 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 903 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 904 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 905 | } |
| 906 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 907 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 908 | struct drm_i915_private *dev_priv, |
| 909 | u32 gt_iir) |
| 910 | { |
| 911 | if (gt_iir & |
| 912 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
| 913 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 914 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
| 915 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 916 | } |
| 917 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 918 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 919 | struct drm_i915_private *dev_priv, |
| 920 | u32 gt_iir) |
| 921 | { |
| 922 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 923 | if (gt_iir & |
| 924 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 925 | notify_ring(dev, &dev_priv->ring[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 926 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 927 | notify_ring(dev, &dev_priv->ring[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 928 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 929 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 930 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 931 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 932 | GT_BSD_CS_ERROR_INTERRUPT | |
| 933 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 934 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
| 935 | i915_handle_error(dev, false); |
| 936 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 937 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 938 | if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 939 | ivybridge_parity_error_irq_handler(dev); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 940 | } |
| 941 | |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 942 | /* Legacy way of handling PM interrupts */ |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 943 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, |
| 944 | u32 pm_iir) |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 945 | { |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 946 | /* |
| 947 | * IIR bits should never already be set because IMR should |
| 948 | * prevent an interrupt from being shown in IIR. The warning |
| 949 | * displays a case where we've unsafely cleared |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 950 | * dev_priv->rps.pm_iir. Although missing an interrupt of the same |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 951 | * type is not a problem, it displays a problem in the logic. |
| 952 | * |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 953 | * The mask bit in IMR is cleared by dev_priv->rps.work. |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 954 | */ |
| 955 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 956 | spin_lock(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 957 | dev_priv->rps.pm_iir |= pm_iir; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame^] | 958 | snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 959 | spin_unlock(&dev_priv->irq_lock); |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 960 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 961 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 962 | } |
| 963 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 964 | #define HPD_STORM_DETECT_PERIOD 1000 |
| 965 | #define HPD_STORM_THRESHOLD 5 |
| 966 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 967 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 968 | u32 hotplug_trigger, |
| 969 | const u32 *hpd) |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 970 | { |
| 971 | drm_i915_private_t *dev_priv = dev->dev_private; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 972 | int i; |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 973 | bool storm_detected = false; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 974 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 975 | if (!hotplug_trigger) |
| 976 | return; |
| 977 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 978 | spin_lock(&dev_priv->irq_lock); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 979 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 980 | |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 981 | WARN(((hpd[i] & hotplug_trigger) && |
| 982 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), |
| 983 | "Received HPD interrupt although disabled\n"); |
| 984 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 985 | if (!(hpd[i] & hotplug_trigger) || |
| 986 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
| 987 | continue; |
| 988 | |
Jani Nikula | bc5ead8c | 2013-05-07 15:10:29 +0300 | [diff] [blame] | 989 | dev_priv->hpd_event_bits |= (1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 990 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
| 991 | dev_priv->hpd_stats[i].hpd_last_jiffies |
| 992 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { |
| 993 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; |
| 994 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 995 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 996 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
| 997 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 998 | dev_priv->hpd_event_bits &= ~(1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 999 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1000 | storm_detected = true; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1001 | } else { |
| 1002 | dev_priv->hpd_stats[i].hpd_cnt++; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1003 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
| 1004 | dev_priv->hpd_stats[i].hpd_cnt); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1005 | } |
| 1006 | } |
| 1007 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1008 | if (storm_detected) |
| 1009 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1010 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 5876fa0 | 2013-06-27 17:52:13 +0200 | [diff] [blame] | 1011 | |
| 1012 | queue_work(dev_priv->wq, |
| 1013 | &dev_priv->hotplug_work); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1014 | } |
| 1015 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1016 | static void gmbus_irq_handler(struct drm_device *dev) |
| 1017 | { |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1018 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1019 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1020 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1021 | } |
| 1022 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1023 | static void dp_aux_irq_handler(struct drm_device *dev) |
| 1024 | { |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1025 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1026 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1027 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1028 | } |
| 1029 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1030 | /* Unlike gen6_rps_irq_handler() from which this function is originally derived, |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1031 | * we must be able to deal with other PM interrupts. This is complicated because |
| 1032 | * of the way in which we use the masks to defer the RPS work (which for |
| 1033 | * posterity is necessary because of forcewake). |
| 1034 | */ |
| 1035 | static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv, |
| 1036 | u32 pm_iir) |
| 1037 | { |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1038 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1039 | spin_lock(&dev_priv->irq_lock); |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1040 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame^] | 1041 | snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir); |
| 1042 | /* never want to mask useful interrupts. */ |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 1043 | WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1044 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 2adbee6 | 2013-07-04 23:35:27 +0200 | [diff] [blame] | 1045 | |
| 1046 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1047 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1048 | |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1049 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
| 1050 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1051 | |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1052 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
| 1053 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); |
| 1054 | i915_handle_error(dev_priv->dev, false); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1055 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1056 | } |
| 1057 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 1058 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1059 | { |
| 1060 | struct drm_device *dev = (struct drm_device *) arg; |
| 1061 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1062 | u32 iir, gt_iir, pm_iir; |
| 1063 | irqreturn_t ret = IRQ_NONE; |
| 1064 | unsigned long irqflags; |
| 1065 | int pipe; |
| 1066 | u32 pipe_stats[I915_MAX_PIPES]; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1067 | |
| 1068 | atomic_inc(&dev_priv->irq_received); |
| 1069 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1070 | while (true) { |
| 1071 | iir = I915_READ(VLV_IIR); |
| 1072 | gt_iir = I915_READ(GTIIR); |
| 1073 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1074 | |
| 1075 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 1076 | goto out; |
| 1077 | |
| 1078 | ret = IRQ_HANDLED; |
| 1079 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1080 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1081 | |
| 1082 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1083 | for_each_pipe(pipe) { |
| 1084 | int reg = PIPESTAT(pipe); |
| 1085 | pipe_stats[pipe] = I915_READ(reg); |
| 1086 | |
| 1087 | /* |
| 1088 | * Clear the PIPE*STAT regs before the IIR |
| 1089 | */ |
| 1090 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 1091 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1092 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 1093 | pipe_name(pipe)); |
| 1094 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1095 | } |
| 1096 | } |
| 1097 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1098 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1099 | for_each_pipe(pipe) { |
| 1100 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) |
| 1101 | drm_handle_vblank(dev, pipe); |
| 1102 | |
| 1103 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { |
| 1104 | intel_prepare_page_flip(dev, pipe); |
| 1105 | intel_finish_page_flip(dev, pipe); |
| 1106 | } |
| 1107 | } |
| 1108 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1109 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1110 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
| 1111 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1112 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1113 | |
| 1114 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 1115 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1116 | |
| 1117 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 1118 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1119 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1120 | I915_READ(PORT_HOTPLUG_STAT); |
| 1121 | } |
| 1122 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1123 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 1124 | gmbus_irq_handler(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1125 | |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 1126 | if (pm_iir & GEN6_PM_RPS_EVENTS) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1127 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1128 | |
| 1129 | I915_WRITE(GTIIR, gt_iir); |
| 1130 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1131 | I915_WRITE(VLV_IIR, iir); |
| 1132 | } |
| 1133 | |
| 1134 | out: |
| 1135 | return ret; |
| 1136 | } |
| 1137 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1138 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1139 | { |
| 1140 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1141 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1142 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1143 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1144 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
| 1145 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1146 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 1147 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 1148 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1149 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1150 | port_name(port)); |
| 1151 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1152 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1153 | if (pch_iir & SDE_AUX_MASK) |
| 1154 | dp_aux_irq_handler(dev); |
| 1155 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1156 | if (pch_iir & SDE_GMBUS) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1157 | gmbus_irq_handler(dev); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1158 | |
| 1159 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 1160 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 1161 | |
| 1162 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 1163 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 1164 | |
| 1165 | if (pch_iir & SDE_POISON) |
| 1166 | DRM_ERROR("PCH poison interrupt\n"); |
| 1167 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1168 | if (pch_iir & SDE_FDI_MASK) |
| 1169 | for_each_pipe(pipe) |
| 1170 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1171 | pipe_name(pipe), |
| 1172 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1173 | |
| 1174 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 1175 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 1176 | |
| 1177 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 1178 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 1179 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1180 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1181 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1182 | false)) |
| 1183 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1184 | |
| 1185 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 1186 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1187 | false)) |
| 1188 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1189 | } |
| 1190 | |
| 1191 | static void ivb_err_int_handler(struct drm_device *dev) |
| 1192 | { |
| 1193 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1194 | u32 err_int = I915_READ(GEN7_ERR_INT); |
| 1195 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1196 | if (err_int & ERR_INT_POISON) |
| 1197 | DRM_ERROR("Poison interrupt\n"); |
| 1198 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1199 | if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
| 1200 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| 1201 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| 1202 | |
| 1203 | if (err_int & ERR_INT_FIFO_UNDERRUN_B) |
| 1204 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) |
| 1205 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); |
| 1206 | |
| 1207 | if (err_int & ERR_INT_FIFO_UNDERRUN_C) |
| 1208 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) |
| 1209 | DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); |
| 1210 | |
| 1211 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 1212 | } |
| 1213 | |
| 1214 | static void cpt_serr_int_handler(struct drm_device *dev) |
| 1215 | { |
| 1216 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1217 | u32 serr_int = I915_READ(SERR_INT); |
| 1218 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1219 | if (serr_int & SERR_INT_POISON) |
| 1220 | DRM_ERROR("PCH poison interrupt\n"); |
| 1221 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1222 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
| 1223 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1224 | false)) |
| 1225 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1226 | |
| 1227 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) |
| 1228 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1229 | false)) |
| 1230 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1231 | |
| 1232 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) |
| 1233 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, |
| 1234 | false)) |
| 1235 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); |
| 1236 | |
| 1237 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1238 | } |
| 1239 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1240 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
| 1241 | { |
| 1242 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1243 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1244 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1245 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1246 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
| 1247 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1248 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 1249 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 1250 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 1251 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 1252 | port_name(port)); |
| 1253 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1254 | |
| 1255 | if (pch_iir & SDE_AUX_MASK_CPT) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1256 | dp_aux_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1257 | |
| 1258 | if (pch_iir & SDE_GMBUS_CPT) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1259 | gmbus_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1260 | |
| 1261 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 1262 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 1263 | |
| 1264 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 1265 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 1266 | |
| 1267 | if (pch_iir & SDE_FDI_MASK_CPT) |
| 1268 | for_each_pipe(pipe) |
| 1269 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1270 | pipe_name(pipe), |
| 1271 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1272 | |
| 1273 | if (pch_iir & SDE_ERROR_CPT) |
| 1274 | cpt_serr_int_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1275 | } |
| 1276 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1277 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1278 | { |
| 1279 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1280 | |
| 1281 | if (de_iir & DE_AUX_CHANNEL_A) |
| 1282 | dp_aux_irq_handler(dev); |
| 1283 | |
| 1284 | if (de_iir & DE_GSE) |
| 1285 | intel_opregion_asle_intr(dev); |
| 1286 | |
| 1287 | if (de_iir & DE_PIPEA_VBLANK) |
| 1288 | drm_handle_vblank(dev, 0); |
| 1289 | |
| 1290 | if (de_iir & DE_PIPEB_VBLANK) |
| 1291 | drm_handle_vblank(dev, 1); |
| 1292 | |
| 1293 | if (de_iir & DE_POISON) |
| 1294 | DRM_ERROR("Poison interrupt\n"); |
| 1295 | |
| 1296 | if (de_iir & DE_PIPEA_FIFO_UNDERRUN) |
| 1297 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) |
| 1298 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); |
| 1299 | |
| 1300 | if (de_iir & DE_PIPEB_FIFO_UNDERRUN) |
| 1301 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) |
| 1302 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); |
| 1303 | |
| 1304 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
| 1305 | intel_prepare_page_flip(dev, 0); |
| 1306 | intel_finish_page_flip_plane(dev, 0); |
| 1307 | } |
| 1308 | |
| 1309 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
| 1310 | intel_prepare_page_flip(dev, 1); |
| 1311 | intel_finish_page_flip_plane(dev, 1); |
| 1312 | } |
| 1313 | |
| 1314 | /* check event from PCH */ |
| 1315 | if (de_iir & DE_PCH_EVENT) { |
| 1316 | u32 pch_iir = I915_READ(SDEIIR); |
| 1317 | |
| 1318 | if (HAS_PCH_CPT(dev)) |
| 1319 | cpt_irq_handler(dev, pch_iir); |
| 1320 | else |
| 1321 | ibx_irq_handler(dev, pch_iir); |
| 1322 | |
| 1323 | /* should clear PCH hotplug event before clear CPU irq */ |
| 1324 | I915_WRITE(SDEIIR, pch_iir); |
| 1325 | } |
| 1326 | |
| 1327 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
| 1328 | ironlake_rps_change_irq_handler(dev); |
| 1329 | } |
| 1330 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1331 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1332 | { |
| 1333 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1334 | int i; |
| 1335 | |
| 1336 | if (de_iir & DE_ERR_INT_IVB) |
| 1337 | ivb_err_int_handler(dev); |
| 1338 | |
| 1339 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
| 1340 | dp_aux_irq_handler(dev); |
| 1341 | |
| 1342 | if (de_iir & DE_GSE_IVB) |
| 1343 | intel_opregion_asle_intr(dev); |
| 1344 | |
| 1345 | for (i = 0; i < 3; i++) { |
| 1346 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) |
| 1347 | drm_handle_vblank(dev, i); |
| 1348 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { |
| 1349 | intel_prepare_page_flip(dev, i); |
| 1350 | intel_finish_page_flip_plane(dev, i); |
| 1351 | } |
| 1352 | } |
| 1353 | |
| 1354 | /* check event from PCH */ |
| 1355 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
| 1356 | u32 pch_iir = I915_READ(SDEIIR); |
| 1357 | |
| 1358 | cpt_irq_handler(dev, pch_iir); |
| 1359 | |
| 1360 | /* clear PCH hotplug event before clear CPU irq */ |
| 1361 | I915_WRITE(SDEIIR, pch_iir); |
| 1362 | } |
| 1363 | } |
| 1364 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1365 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1366 | { |
| 1367 | struct drm_device *dev = (struct drm_device *) arg; |
| 1368 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1369 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1370 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1371 | |
| 1372 | atomic_inc(&dev_priv->irq_received); |
| 1373 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1374 | /* We get interrupts on unclaimed registers, so check for this before we |
| 1375 | * do any I915_{READ,WRITE}. */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1376 | intel_uncore_check_errors(dev); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1377 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1378 | /* disable master interrupt before clearing iir */ |
| 1379 | de_ier = I915_READ(DEIER); |
| 1380 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 1381 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1382 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1383 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 1384 | * interrupts will will be stored on its back queue, and then we'll be |
| 1385 | * able to process them after we restore SDEIER (as soon as we restore |
| 1386 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 1387 | * due to its back queue). */ |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1388 | if (!HAS_PCH_NOP(dev)) { |
| 1389 | sde_ier = I915_READ(SDEIER); |
| 1390 | I915_WRITE(SDEIER, 0); |
| 1391 | POSTING_READ(SDEIER); |
| 1392 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1393 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1394 | /* On Haswell, also mask ERR_INT because we don't want to risk |
| 1395 | * generating "unclaimed register" interrupts from inside the interrupt |
| 1396 | * handler. */ |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1397 | if (IS_HASWELL(dev)) { |
| 1398 | spin_lock(&dev_priv->irq_lock); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1399 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1400 | spin_unlock(&dev_priv->irq_lock); |
| 1401 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1402 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1403 | gt_iir = I915_READ(GTIIR); |
| 1404 | if (gt_iir) { |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1405 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1406 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1407 | else |
| 1408 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1409 | I915_WRITE(GTIIR, gt_iir); |
| 1410 | ret = IRQ_HANDLED; |
| 1411 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1412 | |
| 1413 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1414 | if (de_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1415 | if (INTEL_INFO(dev)->gen >= 7) |
| 1416 | ivb_display_irq_handler(dev, de_iir); |
| 1417 | else |
| 1418 | ilk_display_irq_handler(dev, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1419 | I915_WRITE(DEIIR, de_iir); |
| 1420 | ret = IRQ_HANDLED; |
| 1421 | } |
| 1422 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1423 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1424 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 1425 | if (pm_iir) { |
| 1426 | if (IS_HASWELL(dev)) |
| 1427 | hsw_pm_irq_handler(dev_priv, pm_iir); |
| 1428 | else if (pm_iir & GEN6_PM_RPS_EVENTS) |
| 1429 | gen6_rps_irq_handler(dev_priv, pm_iir); |
| 1430 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1431 | ret = IRQ_HANDLED; |
| 1432 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1433 | } |
| 1434 | |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 1435 | if (IS_HASWELL(dev)) { |
| 1436 | spin_lock(&dev_priv->irq_lock); |
| 1437 | if (ivb_can_enable_err_int(dev)) |
| 1438 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 1439 | spin_unlock(&dev_priv->irq_lock); |
| 1440 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1441 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1442 | I915_WRITE(DEIER, de_ier); |
| 1443 | POSTING_READ(DEIER); |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1444 | if (!HAS_PCH_NOP(dev)) { |
| 1445 | I915_WRITE(SDEIER, sde_ier); |
| 1446 | POSTING_READ(SDEIER); |
| 1447 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1448 | |
| 1449 | return ret; |
| 1450 | } |
| 1451 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1452 | /** |
| 1453 | * i915_error_work_func - do process context error handling work |
| 1454 | * @work: work struct |
| 1455 | * |
| 1456 | * Fire an error uevent so userspace can see that a hang or error |
| 1457 | * was detected. |
| 1458 | */ |
| 1459 | static void i915_error_work_func(struct work_struct *work) |
| 1460 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1461 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
| 1462 | work); |
| 1463 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, |
| 1464 | gpu_error); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1465 | struct drm_device *dev = dev_priv->dev; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1466 | struct intel_ring_buffer *ring; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 1467 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 1468 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 1469 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1470 | int i, ret; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1471 | |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1472 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1473 | |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1474 | /* |
| 1475 | * Note that there's only one work item which does gpu resets, so we |
| 1476 | * need not worry about concurrent gpu resets potentially incrementing |
| 1477 | * error->reset_counter twice. We only need to take care of another |
| 1478 | * racing irq/hangcheck declaring the gpu dead for a second time. A |
| 1479 | * quick check for that is good enough: schedule_work ensures the |
| 1480 | * correct ordering between hang detection and this work item, and since |
| 1481 | * the reset in-progress bit is only ever set by code outside of this |
| 1482 | * work we don't need to worry about any other races. |
| 1483 | */ |
| 1484 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 1485 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1486 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
| 1487 | reset_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1488 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1489 | ret = i915_reset(dev); |
| 1490 | |
| 1491 | if (ret == 0) { |
| 1492 | /* |
| 1493 | * After all the gem state is reset, increment the reset |
| 1494 | * counter and wake up everyone waiting for the reset to |
| 1495 | * complete. |
| 1496 | * |
| 1497 | * Since unlock operations are a one-sided barrier only, |
| 1498 | * we need to insert a barrier here to order any seqno |
| 1499 | * updates before |
| 1500 | * the counter increment. |
| 1501 | */ |
| 1502 | smp_mb__before_atomic_inc(); |
| 1503 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
| 1504 | |
| 1505 | kobject_uevent_env(&dev->primary->kdev.kobj, |
| 1506 | KOBJ_CHANGE, reset_done_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1507 | } else { |
| 1508 | atomic_set(&error->reset_counter, I915_WEDGED); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1509 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1510 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1511 | for_each_ring(ring, dev_priv, i) |
| 1512 | wake_up_all(&ring->irq_queue); |
| 1513 | |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 1514 | intel_display_handle_reset(dev); |
| 1515 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1516 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1517 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1518 | } |
| 1519 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1520 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1521 | { |
| 1522 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 1523 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1524 | u32 eir = I915_READ(EIR); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1525 | int pipe, i; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1526 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1527 | if (!eir) |
| 1528 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1529 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1530 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1531 | |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 1532 | i915_get_extra_instdone(dev, instdone); |
| 1533 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1534 | if (IS_G4X(dev)) { |
| 1535 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 1536 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1537 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1538 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1539 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1540 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 1541 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1542 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1543 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1544 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1545 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1546 | } |
| 1547 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 1548 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1549 | pr_err("page table error\n"); |
| 1550 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1551 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1552 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1553 | } |
| 1554 | } |
| 1555 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1556 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1557 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 1558 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1559 | pr_err("page table error\n"); |
| 1560 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1561 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1562 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1563 | } |
| 1564 | } |
| 1565 | |
| 1566 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1567 | pr_err("memory refresh error:\n"); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1568 | for_each_pipe(pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1569 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1570 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1571 | /* pipestat has already been acked */ |
| 1572 | } |
| 1573 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1574 | pr_err("instruction error\n"); |
| 1575 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 1576 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 1577 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1578 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1579 | u32 ipeir = I915_READ(IPEIR); |
| 1580 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1581 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 1582 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1583 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1584 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1585 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1586 | } else { |
| 1587 | u32 ipeir = I915_READ(IPEIR_I965); |
| 1588 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1589 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 1590 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1591 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 1592 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1593 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1594 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1595 | } |
| 1596 | } |
| 1597 | |
| 1598 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 1599 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1600 | eir = I915_READ(EIR); |
| 1601 | if (eir) { |
| 1602 | /* |
| 1603 | * some errors might have become stuck, |
| 1604 | * mask them. |
| 1605 | */ |
| 1606 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 1607 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 1608 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 1609 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1610 | } |
| 1611 | |
| 1612 | /** |
| 1613 | * i915_handle_error - handle an error interrupt |
| 1614 | * @dev: drm device |
| 1615 | * |
| 1616 | * Do some basic checking of regsiter state at error interrupt time and |
| 1617 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 1618 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 1619 | * so userspace knows something bad happened (should trigger collection |
| 1620 | * of a ring dump etc.). |
| 1621 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 1622 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1623 | { |
| 1624 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1625 | struct intel_ring_buffer *ring; |
| 1626 | int i; |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 1627 | |
| 1628 | i915_capture_error_state(dev); |
| 1629 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1630 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1631 | if (wedged) { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1632 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
| 1633 | &dev_priv->gpu_error.reset_counter); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1634 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1635 | /* |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1636 | * Wakeup waiting processes so that the reset work item |
| 1637 | * doesn't deadlock trying to grab various locks. |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1638 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1639 | for_each_ring(ring, dev_priv, i) |
| 1640 | wake_up_all(&ring->irq_queue); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 1641 | } |
| 1642 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1643 | queue_work(dev_priv->wq, &dev_priv->gpu_error.work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1644 | } |
| 1645 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 1646 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1647 | { |
| 1648 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1649 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 1650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1651 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1652 | struct intel_unpin_work *work; |
| 1653 | unsigned long flags; |
| 1654 | bool stall_detected; |
| 1655 | |
| 1656 | /* Ignore early vblank irqs */ |
| 1657 | if (intel_crtc == NULL) |
| 1658 | return; |
| 1659 | |
| 1660 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1661 | work = intel_crtc->unpin_work; |
| 1662 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 1663 | if (work == NULL || |
| 1664 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || |
| 1665 | !work->enable_stall_check) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1666 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 1667 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1668 | return; |
| 1669 | } |
| 1670 | |
| 1671 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1672 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1673 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1674 | int dspsurf = DSPSURF(intel_crtc->plane); |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 1675 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1676 | i915_gem_obj_ggtt_offset(obj); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1677 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1678 | int dspaddr = DSPADDR(intel_crtc->plane); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1679 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1680 | crtc->y * crtc->fb->pitches[0] + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 1681 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 1682 | } |
| 1683 | |
| 1684 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1685 | |
| 1686 | if (stall_detected) { |
| 1687 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 1688 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 1689 | } |
| 1690 | } |
| 1691 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1692 | /* Called from drm generic code, passed 'crtc' which |
| 1693 | * we use as a pipe index |
| 1694 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1695 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1696 | { |
| 1697 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1698 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1699 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 1700 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 1701 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1702 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1703 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1704 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1705 | i915_enable_pipestat(dev_priv, pipe, |
| 1706 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1707 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 1708 | i915_enable_pipestat(dev_priv, pipe, |
| 1709 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1710 | |
| 1711 | /* maintain vblank delivery even in deep C-states */ |
| 1712 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1713 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1714 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1715 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1716 | return 0; |
| 1717 | } |
| 1718 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1719 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1720 | { |
| 1721 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1722 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1723 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
| 1724 | DE_PIPE_VBLANK_ILK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1725 | |
| 1726 | if (!i915_pipe_enabled(dev, pipe)) |
| 1727 | return -EINVAL; |
| 1728 | |
| 1729 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1730 | ironlake_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1731 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1732 | |
| 1733 | return 0; |
| 1734 | } |
| 1735 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1736 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 1737 | { |
| 1738 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1739 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1740 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1741 | |
| 1742 | if (!i915_pipe_enabled(dev, pipe)) |
| 1743 | return -EINVAL; |
| 1744 | |
| 1745 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1746 | imr = I915_READ(VLV_IMR); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1747 | if (pipe == 0) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1748 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1749 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1750 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1751 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1752 | i915_enable_pipestat(dev_priv, pipe, |
| 1753 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1754 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1755 | |
| 1756 | return 0; |
| 1757 | } |
| 1758 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 1759 | /* Called from drm generic code, passed 'crtc' which |
| 1760 | * we use as a pipe index |
| 1761 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1762 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1763 | { |
| 1764 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 1765 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 1766 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1767 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1768 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 1769 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 1770 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1771 | i915_disable_pipestat(dev_priv, pipe, |
| 1772 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 1773 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
| 1774 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1775 | } |
| 1776 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 1777 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1778 | { |
| 1779 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1780 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1781 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
| 1782 | DE_PIPE_VBLANK_ILK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 1783 | |
| 1784 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 1785 | ironlake_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1786 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1787 | } |
| 1788 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1789 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 1790 | { |
| 1791 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1792 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1793 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1794 | |
| 1795 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1796 | i915_disable_pipestat(dev_priv, pipe, |
| 1797 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1798 | imr = I915_READ(VLV_IMR); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1799 | if (pipe == 0) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1800 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1801 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1802 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1803 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1804 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1805 | } |
| 1806 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1807 | static u32 |
| 1808 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1809 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1810 | return list_entry(ring->request_list.prev, |
| 1811 | struct drm_i915_gem_request, list)->seqno; |
| 1812 | } |
| 1813 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1814 | static bool |
| 1815 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1816 | { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1817 | return (list_empty(&ring->request_list) || |
| 1818 | i915_seqno_passed(seqno, ring_last_seqno(ring))); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1819 | } |
| 1820 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1821 | static struct intel_ring_buffer * |
| 1822 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1823 | { |
| 1824 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1825 | u32 cmd, ipehr, acthd, acthd_min; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1826 | |
| 1827 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
| 1828 | if ((ipehr & ~(0x3 << 16)) != |
| 1829 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1830 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1831 | |
| 1832 | /* ACTHD is likely pointing to the dword after the actual command, |
| 1833 | * so scan backwards until we find the MBOX. |
| 1834 | */ |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1835 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1836 | acthd_min = max((int)acthd - 3 * 4, 0); |
| 1837 | do { |
| 1838 | cmd = ioread32(ring->virtual_start + acthd); |
| 1839 | if (cmd == ipehr) |
| 1840 | break; |
| 1841 | |
| 1842 | acthd -= 4; |
| 1843 | if (acthd < acthd_min) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1844 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1845 | } while (1); |
| 1846 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1847 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
| 1848 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1849 | } |
| 1850 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1851 | static int semaphore_passed(struct intel_ring_buffer *ring) |
| 1852 | { |
| 1853 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1854 | struct intel_ring_buffer *signaller; |
| 1855 | u32 seqno, ctl; |
| 1856 | |
| 1857 | ring->hangcheck.deadlock = true; |
| 1858 | |
| 1859 | signaller = semaphore_waits_for(ring, &seqno); |
| 1860 | if (signaller == NULL || signaller->hangcheck.deadlock) |
| 1861 | return -1; |
| 1862 | |
| 1863 | /* cursory check for an unkickable deadlock */ |
| 1864 | ctl = I915_READ_CTL(signaller); |
| 1865 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) |
| 1866 | return -1; |
| 1867 | |
| 1868 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); |
| 1869 | } |
| 1870 | |
| 1871 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
| 1872 | { |
| 1873 | struct intel_ring_buffer *ring; |
| 1874 | int i; |
| 1875 | |
| 1876 | for_each_ring(ring, dev_priv, i) |
| 1877 | ring->hangcheck.deadlock = false; |
| 1878 | } |
| 1879 | |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 1880 | static enum intel_ring_hangcheck_action |
| 1881 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1882 | { |
| 1883 | struct drm_device *dev = ring->dev; |
| 1884 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1885 | u32 tmp; |
| 1886 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1887 | if (ring->hangcheck.acthd != acthd) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1888 | return HANGCHECK_ACTIVE; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1889 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1890 | if (IS_GEN2(dev)) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1891 | return HANGCHECK_HUNG; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1892 | |
| 1893 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 1894 | * If so we can simply poke the RB_WAIT bit |
| 1895 | * and break the hang. This should work on |
| 1896 | * all but the second generation chipsets. |
| 1897 | */ |
| 1898 | tmp = I915_READ_CTL(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1899 | if (tmp & RING_WAIT) { |
| 1900 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 1901 | ring->name); |
| 1902 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1903 | return HANGCHECK_KICK; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1904 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 1905 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1906 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
| 1907 | switch (semaphore_passed(ring)) { |
| 1908 | default: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1909 | return HANGCHECK_HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1910 | case 1: |
| 1911 | DRM_ERROR("Kicking stuck semaphore on %s\n", |
| 1912 | ring->name); |
| 1913 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1914 | return HANGCHECK_KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1915 | case 0: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1916 | return HANGCHECK_WAIT; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1917 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1918 | } |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 1919 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1920 | return HANGCHECK_HUNG; |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 1921 | } |
| 1922 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1923 | /** |
| 1924 | * This is called when the chip hasn't reported back with completed |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1925 | * batchbuffers in a long time. We keep track per ring seqno progress and |
| 1926 | * if there are no progress, hangcheck score for that ring is increased. |
| 1927 | * Further, acthd is inspected to see if the ring is stuck. On stuck case |
| 1928 | * we kick the ring. If we see no progress on three subsequent calls |
| 1929 | * we assume chip is wedged and try to fix it by resetting the chip. |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1930 | */ |
Damien Lespiau | a658b5d | 2013-08-08 22:28:56 +0100 | [diff] [blame] | 1931 | static void i915_hangcheck_elapsed(unsigned long data) |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1932 | { |
| 1933 | struct drm_device *dev = (struct drm_device *)data; |
| 1934 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1935 | struct intel_ring_buffer *ring; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1936 | int i; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1937 | int busy_count = 0, rings_hung = 0; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1938 | bool stuck[I915_NUM_RINGS] = { 0 }; |
| 1939 | #define BUSY 1 |
| 1940 | #define KICK 5 |
| 1941 | #define HUNG 20 |
| 1942 | #define FIRE 30 |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 1943 | |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 1944 | if (!i915_enable_hangcheck) |
| 1945 | return; |
| 1946 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1947 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1948 | u32 seqno, acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1949 | bool busy = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1950 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1951 | semaphore_clear_deadlocks(dev_priv); |
| 1952 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1953 | seqno = ring->get_seqno(ring, false); |
| 1954 | acthd = intel_ring_get_active_head(ring); |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 1955 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 1956 | if (ring->hangcheck.seqno == seqno) { |
| 1957 | if (ring_idle(ring, seqno)) { |
| 1958 | if (waitqueue_active(&ring->irq_queue)) { |
| 1959 | /* Issue a wake-up to catch stuck h/w. */ |
| 1960 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", |
| 1961 | ring->name); |
| 1962 | wake_up_all(&ring->irq_queue); |
| 1963 | ring->hangcheck.score += HUNG; |
| 1964 | } else |
| 1965 | busy = false; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1966 | } else { |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1967 | /* We always increment the hangcheck score |
| 1968 | * if the ring is busy and still processing |
| 1969 | * the same request, so that no single request |
| 1970 | * can run indefinitely (such as a chain of |
| 1971 | * batches). The only time we do not increment |
| 1972 | * the hangcheck score on this ring, if this |
| 1973 | * ring is in a legitimate wait for another |
| 1974 | * ring. In that case the waiting ring is a |
| 1975 | * victim and we want to be sure we catch the |
| 1976 | * right culprit. Then every time we do kick |
| 1977 | * the ring, add a small increment to the |
| 1978 | * score so that we can catch a batch that is |
| 1979 | * being repeatedly kicked and so responsible |
| 1980 | * for stalling the machine. |
| 1981 | */ |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 1982 | ring->hangcheck.action = ring_stuck(ring, |
| 1983 | acthd); |
| 1984 | |
| 1985 | switch (ring->hangcheck.action) { |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1986 | case HANGCHECK_WAIT: |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1987 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1988 | case HANGCHECK_ACTIVE: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 1989 | ring->hangcheck.score += BUSY; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1990 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1991 | case HANGCHECK_KICK: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 1992 | ring->hangcheck.score += KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1993 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 1994 | case HANGCHECK_HUNG: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 1995 | ring->hangcheck.score += HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 1996 | stuck[i] = true; |
| 1997 | break; |
| 1998 | } |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 1999 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2000 | } else { |
| 2001 | /* Gradually reduce the count so that we catch DoS |
| 2002 | * attempts across multiple batches. |
| 2003 | */ |
| 2004 | if (ring->hangcheck.score > 0) |
| 2005 | ring->hangcheck.score--; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2006 | } |
| 2007 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2008 | ring->hangcheck.seqno = seqno; |
| 2009 | ring->hangcheck.acthd = acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2010 | busy_count += busy; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2011 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 2012 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2013 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2014 | if (ring->hangcheck.score > FIRE) { |
Ben Widawsky | acd78c1 | 2013-06-13 21:33:33 -0700 | [diff] [blame] | 2015 | DRM_ERROR("%s on %s\n", |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2016 | stuck[i] ? "stuck" : "no progress", |
Chris Wilson | a43adf0 | 2013-06-10 11:20:22 +0100 | [diff] [blame] | 2017 | ring->name); |
| 2018 | rings_hung++; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2019 | } |
| 2020 | } |
| 2021 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2022 | if (rings_hung) |
| 2023 | return i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2024 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2025 | if (busy_count) |
| 2026 | /* Reset timer case chip hangs without another request |
| 2027 | * being added */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2028 | i915_queue_hangcheck(dev); |
| 2029 | } |
| 2030 | |
| 2031 | void i915_queue_hangcheck(struct drm_device *dev) |
| 2032 | { |
| 2033 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2034 | if (!i915_enable_hangcheck) |
| 2035 | return; |
| 2036 | |
| 2037 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 2038 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2039 | } |
| 2040 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2041 | static void ibx_irq_preinstall(struct drm_device *dev) |
| 2042 | { |
| 2043 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2044 | |
| 2045 | if (HAS_PCH_NOP(dev)) |
| 2046 | return; |
| 2047 | |
| 2048 | /* south display irq */ |
| 2049 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2050 | /* |
| 2051 | * SDEIER is also touched by the interrupt handler to work around missed |
| 2052 | * PCH interrupts. Hence we can't update it after the interrupt handler |
| 2053 | * is enabled - instead we unconditionally enable all PCH interrupt |
| 2054 | * sources here, but then only unmask them as needed with SDEIMR. |
| 2055 | */ |
| 2056 | I915_WRITE(SDEIER, 0xffffffff); |
| 2057 | POSTING_READ(SDEIER); |
| 2058 | } |
| 2059 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2060 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
| 2061 | { |
| 2062 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2063 | |
| 2064 | /* and GT */ |
| 2065 | I915_WRITE(GTIMR, 0xffffffff); |
| 2066 | I915_WRITE(GTIER, 0x0); |
| 2067 | POSTING_READ(GTIER); |
| 2068 | |
| 2069 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2070 | /* and PM */ |
| 2071 | I915_WRITE(GEN6_PMIMR, 0xffffffff); |
| 2072 | I915_WRITE(GEN6_PMIER, 0x0); |
| 2073 | POSTING_READ(GEN6_PMIER); |
| 2074 | } |
| 2075 | } |
| 2076 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2077 | /* drm_dma.h hooks |
| 2078 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2079 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2080 | { |
| 2081 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2082 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2083 | atomic_set(&dev_priv->irq_received, 0); |
| 2084 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2085 | I915_WRITE(HWSTAM, 0xeffe); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 2086 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2087 | I915_WRITE(DEIMR, 0xffffffff); |
| 2088 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2089 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2090 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2091 | gen5_gt_irq_preinstall(dev); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 2092 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2093 | ibx_irq_preinstall(dev); |
Ben Widawsky | 7d99163 | 2013-05-28 19:22:25 -0700 | [diff] [blame] | 2094 | } |
| 2095 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2096 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 2097 | { |
| 2098 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2099 | int pipe; |
| 2100 | |
| 2101 | atomic_set(&dev_priv->irq_received, 0); |
| 2102 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2103 | /* VLV magic */ |
| 2104 | I915_WRITE(VLV_IMR, 0); |
| 2105 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 2106 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 2107 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 2108 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2109 | /* and GT */ |
| 2110 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2111 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2112 | |
| 2113 | gen5_gt_irq_preinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2114 | |
| 2115 | I915_WRITE(DPINVGTT, 0xff); |
| 2116 | |
| 2117 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2118 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2119 | for_each_pipe(pipe) |
| 2120 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2121 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2122 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2123 | I915_WRITE(VLV_IER, 0x0); |
| 2124 | POSTING_READ(VLV_IER); |
| 2125 | } |
| 2126 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2127 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2128 | { |
| 2129 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2130 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2131 | struct intel_encoder *intel_encoder; |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2132 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2133 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2134 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2135 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2136 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2137 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2138 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2139 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2140 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2141 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2142 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2143 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2144 | } |
| 2145 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2146 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2147 | |
| 2148 | /* |
| 2149 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 2150 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 2151 | * |
| 2152 | * This register is the same on all known PCH chips. |
| 2153 | */ |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2154 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 2155 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 2156 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 2157 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 2158 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 2159 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 2160 | } |
| 2161 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2162 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 2163 | { |
| 2164 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2165 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2166 | |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 2167 | if (HAS_PCH_NOP(dev)) |
| 2168 | return; |
| 2169 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2170 | if (HAS_PCH_IBX(dev)) { |
| 2171 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2172 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2173 | } else { |
| 2174 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; |
| 2175 | |
| 2176 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
| 2177 | } |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2178 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2179 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 2180 | I915_WRITE(SDEIMR, ~mask); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2181 | } |
| 2182 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2183 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 2184 | { |
| 2185 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2186 | u32 pm_irqs, gt_irqs; |
| 2187 | |
| 2188 | pm_irqs = gt_irqs = 0; |
| 2189 | |
| 2190 | dev_priv->gt_irq_mask = ~0; |
| 2191 | if (HAS_L3_GPU_CACHE(dev)) { |
| 2192 | /* L3 parity interrupt is always unmasked. */ |
| 2193 | dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
| 2194 | gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
| 2195 | } |
| 2196 | |
| 2197 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
| 2198 | if (IS_GEN5(dev)) { |
| 2199 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
| 2200 | ILK_BSD_USER_INTERRUPT; |
| 2201 | } else { |
| 2202 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 2203 | } |
| 2204 | |
| 2205 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2206 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 2207 | I915_WRITE(GTIER, gt_irqs); |
| 2208 | POSTING_READ(GTIER); |
| 2209 | |
| 2210 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2211 | pm_irqs |= GEN6_PM_RPS_EVENTS; |
| 2212 | |
| 2213 | if (HAS_VEBOX(dev)) |
| 2214 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| 2215 | |
| 2216 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
| 2217 | I915_WRITE(GEN6_PMIMR, 0xffffffff); |
| 2218 | I915_WRITE(GEN6_PMIER, pm_irqs); |
| 2219 | POSTING_READ(GEN6_PMIER); |
| 2220 | } |
| 2221 | } |
| 2222 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2223 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2224 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2225 | unsigned long irqflags; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2226 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2227 | u32 display_mask, extra_mask; |
| 2228 | |
| 2229 | if (INTEL_INFO(dev)->gen >= 7) { |
| 2230 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 2231 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | |
| 2232 | DE_PLANEB_FLIP_DONE_IVB | |
| 2233 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | |
| 2234 | DE_ERR_INT_IVB); |
| 2235 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
| 2236 | DE_PIPEA_VBLANK_IVB); |
| 2237 | |
| 2238 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
| 2239 | } else { |
| 2240 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 2241 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
| 2242 | DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | |
| 2243 | DE_PIPEA_FIFO_UNDERRUN | DE_POISON); |
| 2244 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
| 2245 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2246 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2247 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2248 | |
| 2249 | /* should always can generate irq */ |
| 2250 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2251 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2252 | I915_WRITE(DEIER, display_mask | extra_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2253 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2254 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2255 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2256 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2257 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2258 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2259 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 2260 | /* Enable PCU event interrupts |
| 2261 | * |
| 2262 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2263 | * setup is guaranteed to run in single-threaded context. But we |
| 2264 | * need it to make the assert_spin_locked happy. */ |
| 2265 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2266 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2267 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2268 | } |
| 2269 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2270 | return 0; |
| 2271 | } |
| 2272 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2273 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 2274 | { |
| 2275 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2276 | u32 enable_mask; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2277 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2278 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2279 | |
| 2280 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2281 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2282 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2283 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2284 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 2285 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2286 | /* |
| 2287 | *Leave vblank interrupts masked initially. enable/disable will |
| 2288 | * toggle them based on usage. |
| 2289 | */ |
| 2290 | dev_priv->irq_mask = (~enable_mask) | |
| 2291 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2292 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2293 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2294 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2295 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2296 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2297 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 2298 | I915_WRITE(VLV_IER, enable_mask); |
| 2299 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2300 | I915_WRITE(PIPESTAT(0), 0xffff); |
| 2301 | I915_WRITE(PIPESTAT(1), 0xffff); |
| 2302 | POSTING_READ(VLV_IER); |
| 2303 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2304 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 2305 | * just to make the assert_spin_locked check happy. */ |
| 2306 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2307 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2308 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2309 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2310 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2311 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2312 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2313 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2314 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2315 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2316 | |
| 2317 | /* ack & enable invalid PTE error interrupts */ |
| 2318 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 2319 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 2320 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 2321 | #endif |
| 2322 | |
| 2323 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2324 | |
| 2325 | return 0; |
| 2326 | } |
| 2327 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2328 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 2329 | { |
| 2330 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2331 | int pipe; |
| 2332 | |
| 2333 | if (!dev_priv) |
| 2334 | return; |
| 2335 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2336 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2337 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2338 | for_each_pipe(pipe) |
| 2339 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2340 | |
| 2341 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2342 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2343 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2344 | for_each_pipe(pipe) |
| 2345 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2346 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2347 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2348 | I915_WRITE(VLV_IER, 0x0); |
| 2349 | POSTING_READ(VLV_IER); |
| 2350 | } |
| 2351 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2352 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2353 | { |
| 2354 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2355 | |
| 2356 | if (!dev_priv) |
| 2357 | return; |
| 2358 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2359 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2360 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2361 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2362 | |
| 2363 | I915_WRITE(DEIMR, 0xffffffff); |
| 2364 | I915_WRITE(DEIER, 0x0); |
| 2365 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2366 | if (IS_GEN7(dev)) |
| 2367 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2368 | |
| 2369 | I915_WRITE(GTIMR, 0xffffffff); |
| 2370 | I915_WRITE(GTIER, 0x0); |
| 2371 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2372 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2373 | if (HAS_PCH_NOP(dev)) |
| 2374 | return; |
| 2375 | |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 2376 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2377 | I915_WRITE(SDEIER, 0x0); |
| 2378 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2379 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
| 2380 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2381 | } |
| 2382 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2383 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 2384 | { |
| 2385 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2386 | int pipe; |
| 2387 | |
| 2388 | atomic_set(&dev_priv->irq_received, 0); |
| 2389 | |
| 2390 | for_each_pipe(pipe) |
| 2391 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2392 | I915_WRITE16(IMR, 0xffff); |
| 2393 | I915_WRITE16(IER, 0x0); |
| 2394 | POSTING_READ16(IER); |
| 2395 | } |
| 2396 | |
| 2397 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 2398 | { |
| 2399 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2400 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2401 | I915_WRITE16(EMR, |
| 2402 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2403 | |
| 2404 | /* Unmask the interrupts that we always want on. */ |
| 2405 | dev_priv->irq_mask = |
| 2406 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2407 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2408 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2409 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2410 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2411 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 2412 | |
| 2413 | I915_WRITE16(IER, |
| 2414 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2415 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2416 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2417 | I915_USER_INTERRUPT); |
| 2418 | POSTING_READ16(IER); |
| 2419 | |
| 2420 | return 0; |
| 2421 | } |
| 2422 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2423 | /* |
| 2424 | * Returns true when a page flip has completed. |
| 2425 | */ |
| 2426 | static bool i8xx_handle_vblank(struct drm_device *dev, |
| 2427 | int pipe, u16 iir) |
| 2428 | { |
| 2429 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2430 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); |
| 2431 | |
| 2432 | if (!drm_handle_vblank(dev, pipe)) |
| 2433 | return false; |
| 2434 | |
| 2435 | if ((iir & flip_pending) == 0) |
| 2436 | return false; |
| 2437 | |
| 2438 | intel_prepare_page_flip(dev, pipe); |
| 2439 | |
| 2440 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 2441 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 2442 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 2443 | * the flip is completed (no longer pending). Since this doesn't raise |
| 2444 | * an interrupt per se, we watch for the change at vblank. |
| 2445 | */ |
| 2446 | if (I915_READ16(ISR) & flip_pending) |
| 2447 | return false; |
| 2448 | |
| 2449 | intel_finish_page_flip(dev, pipe); |
| 2450 | |
| 2451 | return true; |
| 2452 | } |
| 2453 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2454 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2455 | { |
| 2456 | struct drm_device *dev = (struct drm_device *) arg; |
| 2457 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2458 | u16 iir, new_iir; |
| 2459 | u32 pipe_stats[2]; |
| 2460 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2461 | int pipe; |
| 2462 | u16 flip_mask = |
| 2463 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2464 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 2465 | |
| 2466 | atomic_inc(&dev_priv->irq_received); |
| 2467 | |
| 2468 | iir = I915_READ16(IIR); |
| 2469 | if (iir == 0) |
| 2470 | return IRQ_NONE; |
| 2471 | |
| 2472 | while (iir & ~flip_mask) { |
| 2473 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2474 | * have been cleared after the pipestat interrupt was received. |
| 2475 | * It doesn't set the bit in iir again, but it still produces |
| 2476 | * interrupts (for non-MSI). |
| 2477 | */ |
| 2478 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2479 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2480 | i915_handle_error(dev, false); |
| 2481 | |
| 2482 | for_each_pipe(pipe) { |
| 2483 | int reg = PIPESTAT(pipe); |
| 2484 | pipe_stats[pipe] = I915_READ(reg); |
| 2485 | |
| 2486 | /* |
| 2487 | * Clear the PIPE*STAT regs before the IIR |
| 2488 | */ |
| 2489 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2490 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2491 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2492 | pipe_name(pipe)); |
| 2493 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2494 | } |
| 2495 | } |
| 2496 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2497 | |
| 2498 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 2499 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 2500 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2501 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2502 | |
| 2503 | if (iir & I915_USER_INTERRUPT) |
| 2504 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2505 | |
| 2506 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2507 | i8xx_handle_vblank(dev, 0, iir)) |
| 2508 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2509 | |
| 2510 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2511 | i8xx_handle_vblank(dev, 1, iir)) |
| 2512 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2513 | |
| 2514 | iir = new_iir; |
| 2515 | } |
| 2516 | |
| 2517 | return IRQ_HANDLED; |
| 2518 | } |
| 2519 | |
| 2520 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 2521 | { |
| 2522 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2523 | int pipe; |
| 2524 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 2525 | for_each_pipe(pipe) { |
| 2526 | /* Clear enable bits; then clear status bits */ |
| 2527 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2528 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2529 | } |
| 2530 | I915_WRITE16(IMR, 0xffff); |
| 2531 | I915_WRITE16(IER, 0x0); |
| 2532 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 2533 | } |
| 2534 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2535 | static void i915_irq_preinstall(struct drm_device * dev) |
| 2536 | { |
| 2537 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2538 | int pipe; |
| 2539 | |
| 2540 | atomic_set(&dev_priv->irq_received, 0); |
| 2541 | |
| 2542 | if (I915_HAS_HOTPLUG(dev)) { |
| 2543 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2544 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2545 | } |
| 2546 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2547 | I915_WRITE16(HWSTAM, 0xeffe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2548 | for_each_pipe(pipe) |
| 2549 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2550 | I915_WRITE(IMR, 0xffffffff); |
| 2551 | I915_WRITE(IER, 0x0); |
| 2552 | POSTING_READ(IER); |
| 2553 | } |
| 2554 | |
| 2555 | static int i915_irq_postinstall(struct drm_device *dev) |
| 2556 | { |
| 2557 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2558 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2559 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2560 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 2561 | |
| 2562 | /* Unmask the interrupts that we always want on. */ |
| 2563 | dev_priv->irq_mask = |
| 2564 | ~(I915_ASLE_INTERRUPT | |
| 2565 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2566 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2567 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2568 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2569 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2570 | |
| 2571 | enable_mask = |
| 2572 | I915_ASLE_INTERRUPT | |
| 2573 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2574 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2575 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 2576 | I915_USER_INTERRUPT; |
| 2577 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2578 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2579 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2580 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2581 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2582 | /* Enable in IER... */ |
| 2583 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 2584 | /* and unmask in IMR */ |
| 2585 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 2586 | } |
| 2587 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2588 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2589 | I915_WRITE(IER, enable_mask); |
| 2590 | POSTING_READ(IER); |
| 2591 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 2592 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2593 | |
| 2594 | return 0; |
| 2595 | } |
| 2596 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2597 | /* |
| 2598 | * Returns true when a page flip has completed. |
| 2599 | */ |
| 2600 | static bool i915_handle_vblank(struct drm_device *dev, |
| 2601 | int plane, int pipe, u32 iir) |
| 2602 | { |
| 2603 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2604 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
| 2605 | |
| 2606 | if (!drm_handle_vblank(dev, pipe)) |
| 2607 | return false; |
| 2608 | |
| 2609 | if ((iir & flip_pending) == 0) |
| 2610 | return false; |
| 2611 | |
| 2612 | intel_prepare_page_flip(dev, plane); |
| 2613 | |
| 2614 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 2615 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 2616 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 2617 | * the flip is completed (no longer pending). Since this doesn't raise |
| 2618 | * an interrupt per se, we watch for the change at vblank. |
| 2619 | */ |
| 2620 | if (I915_READ(ISR) & flip_pending) |
| 2621 | return false; |
| 2622 | |
| 2623 | intel_finish_page_flip(dev, pipe); |
| 2624 | |
| 2625 | return true; |
| 2626 | } |
| 2627 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2628 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2629 | { |
| 2630 | struct drm_device *dev = (struct drm_device *) arg; |
| 2631 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2632 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2633 | unsigned long irqflags; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2634 | u32 flip_mask = |
| 2635 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2636 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2637 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2638 | |
| 2639 | atomic_inc(&dev_priv->irq_received); |
| 2640 | |
| 2641 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2642 | do { |
| 2643 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2644 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2645 | |
| 2646 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2647 | * have been cleared after the pipestat interrupt was received. |
| 2648 | * It doesn't set the bit in iir again, but it still produces |
| 2649 | * interrupts (for non-MSI). |
| 2650 | */ |
| 2651 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2652 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2653 | i915_handle_error(dev, false); |
| 2654 | |
| 2655 | for_each_pipe(pipe) { |
| 2656 | int reg = PIPESTAT(pipe); |
| 2657 | pipe_stats[pipe] = I915_READ(reg); |
| 2658 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2659 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2660 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2661 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2662 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2663 | pipe_name(pipe)); |
| 2664 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2665 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2666 | } |
| 2667 | } |
| 2668 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2669 | |
| 2670 | if (!irq_received) |
| 2671 | break; |
| 2672 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2673 | /* Consume port. Then clear IIR or we'll miss events */ |
| 2674 | if ((I915_HAS_HOTPLUG(dev)) && |
| 2675 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 2676 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2677 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2678 | |
| 2679 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2680 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2681 | |
| 2682 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 2683 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2684 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2685 | POSTING_READ(PORT_HOTPLUG_STAT); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2686 | } |
| 2687 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2688 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2689 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2690 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2691 | if (iir & I915_USER_INTERRUPT) |
| 2692 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2693 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2694 | for_each_pipe(pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2695 | int plane = pipe; |
| 2696 | if (IS_MOBILE(dev)) |
| 2697 | plane = !plane; |
Ville Syrjälä | 5e2032d | 2013-02-19 15:16:38 +0200 | [diff] [blame] | 2698 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2699 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 2700 | i915_handle_vblank(dev, plane, pipe, iir)) |
| 2701 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2702 | |
| 2703 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2704 | blc_event = true; |
| 2705 | } |
| 2706 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2707 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2708 | intel_opregion_asle_intr(dev); |
| 2709 | |
| 2710 | /* With MSI, interrupts are only generated when iir |
| 2711 | * transitions from zero to nonzero. If another bit got |
| 2712 | * set while we were handling the existing iir bits, then |
| 2713 | * we would never get another interrupt. |
| 2714 | * |
| 2715 | * This is fine on non-MSI as well, as if we hit this path |
| 2716 | * we avoid exiting the interrupt handler only to generate |
| 2717 | * another one. |
| 2718 | * |
| 2719 | * Note that for MSI this could cause a stray interrupt report |
| 2720 | * if an interrupt landed in the time between writing IIR and |
| 2721 | * the posting read. This should be rare enough to never |
| 2722 | * trigger the 99% of 100,000 interrupts test for disabling |
| 2723 | * stray interrupts. |
| 2724 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2725 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2726 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 2727 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2728 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2729 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 2730 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2731 | return ret; |
| 2732 | } |
| 2733 | |
| 2734 | static void i915_irq_uninstall(struct drm_device * dev) |
| 2735 | { |
| 2736 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2737 | int pipe; |
| 2738 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2739 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2740 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2741 | if (I915_HAS_HOTPLUG(dev)) { |
| 2742 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2743 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2744 | } |
| 2745 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 2746 | I915_WRITE16(HWSTAM, 0xffff); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2747 | for_each_pipe(pipe) { |
| 2748 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2749 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 2750 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 2751 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2752 | I915_WRITE(IMR, 0xffffffff); |
| 2753 | I915_WRITE(IER, 0x0); |
| 2754 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2755 | I915_WRITE(IIR, I915_READ(IIR)); |
| 2756 | } |
| 2757 | |
| 2758 | static void i965_irq_preinstall(struct drm_device * dev) |
| 2759 | { |
| 2760 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2761 | int pipe; |
| 2762 | |
| 2763 | atomic_set(&dev_priv->irq_received, 0); |
| 2764 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2765 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2766 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2767 | |
| 2768 | I915_WRITE(HWSTAM, 0xeffe); |
| 2769 | for_each_pipe(pipe) |
| 2770 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2771 | I915_WRITE(IMR, 0xffffffff); |
| 2772 | I915_WRITE(IER, 0x0); |
| 2773 | POSTING_READ(IER); |
| 2774 | } |
| 2775 | |
| 2776 | static int i965_irq_postinstall(struct drm_device *dev) |
| 2777 | { |
| 2778 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2779 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2780 | u32 error_mask; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2781 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2782 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2783 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2784 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2785 | I915_DISPLAY_PORT_INTERRUPT | |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2786 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2787 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 2788 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2789 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 2790 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2791 | |
| 2792 | enable_mask = ~dev_priv->irq_mask; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2793 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2794 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 2795 | enable_mask |= I915_USER_INTERRUPT; |
| 2796 | |
| 2797 | if (IS_G4X(dev)) |
| 2798 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2799 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2800 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 2801 | * just to make the assert_spin_locked check happy. */ |
| 2802 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2803 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2804 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2805 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2806 | /* |
| 2807 | * Enable some error detection, note the instruction error mask |
| 2808 | * bit is reserved, so we leave it masked. |
| 2809 | */ |
| 2810 | if (IS_G4X(dev)) { |
| 2811 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 2812 | GM45_ERROR_MEM_PRIV | |
| 2813 | GM45_ERROR_CP_PRIV | |
| 2814 | I915_ERROR_MEMORY_REFRESH); |
| 2815 | } else { |
| 2816 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 2817 | I915_ERROR_MEMORY_REFRESH); |
| 2818 | } |
| 2819 | I915_WRITE(EMR, error_mask); |
| 2820 | |
| 2821 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 2822 | I915_WRITE(IER, enable_mask); |
| 2823 | POSTING_READ(IER); |
| 2824 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2825 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2826 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2827 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 2828 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2829 | |
| 2830 | return 0; |
| 2831 | } |
| 2832 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2833 | static void i915_hpd_irq_setup(struct drm_device *dev) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2834 | { |
| 2835 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 2836 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2837 | struct intel_encoder *intel_encoder; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2838 | u32 hotplug_en; |
| 2839 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 2840 | assert_spin_locked(&dev_priv->irq_lock); |
| 2841 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2842 | if (I915_HAS_HOTPLUG(dev)) { |
| 2843 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 2844 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; |
| 2845 | /* Note HDMI and DP share hotplug bits */ |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 2846 | /* enable bits are the same for all generations */ |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2847 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
| 2848 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
| 2849 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2850 | /* Programming the CRT detection parameters tends |
| 2851 | to generate a spurious hotplug event about three |
| 2852 | seconds later. So just do it once. |
| 2853 | */ |
| 2854 | if (IS_G4X(dev)) |
| 2855 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Daniel Vetter | 85fc95b | 2013-03-27 15:47:11 +0100 | [diff] [blame] | 2856 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2857 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2858 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 2859 | /* Ignore TV since it's buggy */ |
| 2860 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 2861 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2862 | } |
| 2863 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 2864 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2865 | { |
| 2866 | struct drm_device *dev = (struct drm_device *) arg; |
| 2867 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2868 | u32 iir, new_iir; |
| 2869 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2870 | unsigned long irqflags; |
| 2871 | int irq_received; |
| 2872 | int ret = IRQ_NONE, pipe; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2873 | u32 flip_mask = |
| 2874 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 2875 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2876 | |
| 2877 | atomic_inc(&dev_priv->irq_received); |
| 2878 | |
| 2879 | iir = I915_READ(IIR); |
| 2880 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2881 | for (;;) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2882 | bool blc_event = false; |
| 2883 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2884 | irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2885 | |
| 2886 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 2887 | * have been cleared after the pipestat interrupt was received. |
| 2888 | * It doesn't set the bit in iir again, but it still produces |
| 2889 | * interrupts (for non-MSI). |
| 2890 | */ |
| 2891 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 2892 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 2893 | i915_handle_error(dev, false); |
| 2894 | |
| 2895 | for_each_pipe(pipe) { |
| 2896 | int reg = PIPESTAT(pipe); |
| 2897 | pipe_stats[pipe] = I915_READ(reg); |
| 2898 | |
| 2899 | /* |
| 2900 | * Clear the PIPE*STAT regs before the IIR |
| 2901 | */ |
| 2902 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 2903 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 2904 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 2905 | pipe_name(pipe)); |
| 2906 | I915_WRITE(reg, pipe_stats[pipe]); |
| 2907 | irq_received = 1; |
| 2908 | } |
| 2909 | } |
| 2910 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2911 | |
| 2912 | if (!irq_received) |
| 2913 | break; |
| 2914 | |
| 2915 | ret = IRQ_HANDLED; |
| 2916 | |
| 2917 | /* Consume port. Then clear IIR or we'll miss events */ |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2918 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2919 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 2920 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
| 2921 | HOTPLUG_INT_STATUS_G4X : |
Daniel Vetter | 4f7fd70 | 2013-06-24 21:33:28 +0200 | [diff] [blame] | 2922 | HOTPLUG_INT_STATUS_I915); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2923 | |
| 2924 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 2925 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 2926 | |
| 2927 | intel_hpd_irq_handler(dev, hotplug_trigger, |
| 2928 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); |
| 2929 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2930 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 2931 | I915_READ(PORT_HOTPLUG_STAT); |
| 2932 | } |
| 2933 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2934 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2935 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 2936 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2937 | if (iir & I915_USER_INTERRUPT) |
| 2938 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 2939 | if (iir & I915_BSD_USER_INTERRUPT) |
| 2940 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 2941 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2942 | for_each_pipe(pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2943 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 2944 | i915_handle_vblank(dev, pipe, pipe, iir)) |
| 2945 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2946 | |
| 2947 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 2948 | blc_event = true; |
| 2949 | } |
| 2950 | |
| 2951 | |
| 2952 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 2953 | intel_opregion_asle_intr(dev); |
| 2954 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 2955 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 2956 | gmbus_irq_handler(dev); |
| 2957 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2958 | /* With MSI, interrupts are only generated when iir |
| 2959 | * transitions from zero to nonzero. If another bit got |
| 2960 | * set while we were handling the existing iir bits, then |
| 2961 | * we would never get another interrupt. |
| 2962 | * |
| 2963 | * This is fine on non-MSI as well, as if we hit this path |
| 2964 | * we avoid exiting the interrupt handler only to generate |
| 2965 | * another one. |
| 2966 | * |
| 2967 | * Note that for MSI this could cause a stray interrupt report |
| 2968 | * if an interrupt landed in the time between writing IIR and |
| 2969 | * the posting read. This should be rare enough to never |
| 2970 | * trigger the 99% of 100,000 interrupts test for disabling |
| 2971 | * stray interrupts. |
| 2972 | */ |
| 2973 | iir = new_iir; |
| 2974 | } |
| 2975 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2976 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 2977 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2978 | return ret; |
| 2979 | } |
| 2980 | |
| 2981 | static void i965_irq_uninstall(struct drm_device * dev) |
| 2982 | { |
| 2983 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2984 | int pipe; |
| 2985 | |
| 2986 | if (!dev_priv) |
| 2987 | return; |
| 2988 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 2989 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 2990 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 2991 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2992 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 2993 | |
| 2994 | I915_WRITE(HWSTAM, 0xffffffff); |
| 2995 | for_each_pipe(pipe) |
| 2996 | I915_WRITE(PIPESTAT(pipe), 0); |
| 2997 | I915_WRITE(IMR, 0xffffffff); |
| 2998 | I915_WRITE(IER, 0x0); |
| 2999 | |
| 3000 | for_each_pipe(pipe) |
| 3001 | I915_WRITE(PIPESTAT(pipe), |
| 3002 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 3003 | I915_WRITE(IIR, I915_READ(IIR)); |
| 3004 | } |
| 3005 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3006 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
| 3007 | { |
| 3008 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; |
| 3009 | struct drm_device *dev = dev_priv->dev; |
| 3010 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3011 | unsigned long irqflags; |
| 3012 | int i; |
| 3013 | |
| 3014 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3015 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 3016 | struct drm_connector *connector; |
| 3017 | |
| 3018 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) |
| 3019 | continue; |
| 3020 | |
| 3021 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3022 | |
| 3023 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3024 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3025 | |
| 3026 | if (intel_connector->encoder->hpd_pin == i) { |
| 3027 | if (connector->polled != intel_connector->polled) |
| 3028 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", |
| 3029 | drm_get_connector_name(connector)); |
| 3030 | connector->polled = intel_connector->polled; |
| 3031 | if (!connector->polled) |
| 3032 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3033 | } |
| 3034 | } |
| 3035 | } |
| 3036 | if (dev_priv->display.hpd_irq_setup) |
| 3037 | dev_priv->display.hpd_irq_setup(dev); |
| 3038 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3039 | } |
| 3040 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3041 | void intel_irq_init(struct drm_device *dev) |
| 3042 | { |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3043 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3044 | |
| 3045 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3046 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3047 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3048 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3049 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3050 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 3051 | i915_hangcheck_elapsed, |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3052 | (unsigned long) dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3053 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
| 3054 | (unsigned long) dev_priv); |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3055 | |
Tomas Janousek | 97a19a2 | 2012-12-08 13:48:13 +0100 | [diff] [blame] | 3056 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 3057 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3058 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 3059 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Eugeni Dodonov | 7d4e146 | 2012-05-09 15:37:09 -0300 | [diff] [blame] | 3060 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3061 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 3062 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
| 3063 | } |
| 3064 | |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 3065 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 3066 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
| 3067 | else |
| 3068 | dev->driver->get_vblank_timestamp = NULL; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3069 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 3070 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3071 | if (IS_VALLEYVIEW(dev)) { |
| 3072 | dev->driver->irq_handler = valleyview_irq_handler; |
| 3073 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 3074 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 3075 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 3076 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 3077 | dev->driver->disable_vblank = valleyview_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 3078 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3079 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3080 | dev->driver->irq_handler = ironlake_irq_handler; |
| 3081 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 3082 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 3083 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 3084 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 3085 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3086 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3087 | } else { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3088 | if (INTEL_INFO(dev)->gen == 2) { |
| 3089 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 3090 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 3091 | dev->driver->irq_handler = i8xx_irq_handler; |
| 3092 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3093 | } else if (INTEL_INFO(dev)->gen == 3) { |
| 3094 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 3095 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 3096 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 3097 | dev->driver->irq_handler = i915_irq_handler; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3098 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3099 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3100 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 3101 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 3102 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 3103 | dev->driver->irq_handler = i965_irq_handler; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3104 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3105 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3106 | dev->driver->enable_vblank = i915_enable_vblank; |
| 3107 | dev->driver->disable_vblank = i915_disable_vblank; |
| 3108 | } |
| 3109 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3110 | |
| 3111 | void intel_hpd_init(struct drm_device *dev) |
| 3112 | { |
| 3113 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3114 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3115 | struct drm_connector *connector; |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3116 | unsigned long irqflags; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3117 | int i; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3118 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3119 | for (i = 1; i < HPD_NUM_PINS; i++) { |
| 3120 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
| 3121 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3122 | } |
| 3123 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3124 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3125 | connector->polled = intel_connector->polled; |
| 3126 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
| 3127 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3128 | } |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3129 | |
| 3130 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3131 | * just to make the assert_spin_locked checks happy. */ |
| 3132 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3133 | if (dev_priv->display.hpd_irq_setup) |
| 3134 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3135 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3136 | } |