blob: 3c17e959a0eb7d72e703a4d8b342022dddef62f7 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Daniel Vetter3dec0092010-08-20 21:40:52 +020044static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010045static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080046
Jesse Barnesf1f644d2013-06-27 00:39:25 +030047static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030049static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030051
Damien Lespiaue7457a92013-08-08 22:28:59 +010052static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
Jesse Barnes79e53942008-11-07 14:24:08 -080056typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040057 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080058} intel_range_t;
59
60typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040061 int dot_limit;
62 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080063} intel_p2_t;
64
Ma Lingd4906092009-03-18 20:13:27 +080065typedef struct intel_limit intel_limit_t;
66struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040067 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080069};
Jesse Barnes79e53942008-11-07 14:24:08 -080070
Daniel Vetterd2acd212012-10-20 20:57:43 +020071int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
Chris Wilson021357a2010-09-07 20:54:59 +010081static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
Chris Wilson8b99e682010-10-13 09:59:17 +010084 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +010089}
90
Daniel Vetter5d536e22013-07-06 12:52:06 +020091static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -040092 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700102};
103
Daniel Vetter5d536e22013-07-06 12:52:06 +0200104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
Keith Packarde4b36692009-06-05 19:22:17 -0700117static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700128};
Eric Anholt273e27c2011-03-30 13:01:10 -0700129
Keith Packarde4b36692009-06-05 19:22:17 -0700130static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700154};
155
Eric Anholt273e27c2011-03-30 13:01:10 -0700156
Keith Packarde4b36692009-06-05 19:22:17 -0700157static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800169 },
Keith Packarde4b36692009-06-05 19:22:17 -0700170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800196 },
Keith Packarde4b36692009-06-05 19:22:17 -0700197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800210 },
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500213static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700216 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700219 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700226};
227
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500228static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700239};
240
Eric Anholt273e27c2011-03-30 13:01:10 -0700241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800246static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700257};
258
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800259static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800283};
284
Eric Anholt273e27c2011-03-30 13:01:10 -0700285/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400294 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400307 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800310};
311
Ville Syrjälädc730512013-09-24 21:26:30 +0300312static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200320 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700321 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300324 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700326};
327
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300334}
335
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
Chris Wilson1b894b52010-12-14 20:04:54 +0000351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800353{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800354 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800355 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100358 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000359 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000364 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200369 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800370 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800371
372 return limit;
373}
374
Ma Ling044c7c42009-03-18 20:13:23 +0800375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100381 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700382 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800383 else
Keith Packarde4b36692009-06-05 19:22:17 -0700384 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700387 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700389 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800390 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700391 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800392
393 return limit;
394}
395
Chris Wilson1b894b52010-12-14 20:04:54 +0000396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
Eric Anholtbad720f2009-10-22 16:11:14 -0700401 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000402 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800403 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800404 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500405 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500407 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800408 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500409 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700410 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300411 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700419 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700421 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200422 else
423 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800424 }
425 return limit;
426}
427
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800430{
Shaohua Li21778322009-02-23 15:19:16 +0800431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800435}
436
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200442static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800443{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200444 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800445 clock->p = clock->p1 * clock->p2;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800448}
449
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
Chris Wilson1b894b52010-12-14 20:04:54 +0000456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800459{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400463 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400465 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400467 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
Jesse Barnes79e53942008-11-07 14:24:08 -0800480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400481 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400486 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800487
488 return true;
489}
490
Ma Lingd4906092009-03-18 20:13:27 +0800491static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800495{
496 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800497 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800498 int err = target;
499
Daniel Vettera210b022012-11-26 17:22:08 +0100500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800505 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100506 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
Akshay Joshi0206e352011-08-16 15:34:10 -0400517 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800518
Zhao Yakui42158662009-11-20 11:24:18 +0800519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200523 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800529 int this_err;
530
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200531 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800534 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
Ma Lingd4906092009-03-18 20:13:27 +0800552static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200556{
557 struct drm_device *dev = crtc->dev;
558 intel_clock_t clock;
559 int err = target;
560
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
562 /*
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
566 */
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
578 memset(best_clock, 0, sizeof(*best_clock));
579
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
588 int this_err;
589
590 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
593 continue;
594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
Ma Lingd4906092009-03-18 20:13:27 +0800611static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800615{
616 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800617 intel_clock_t clock;
618 int max_n;
619 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100625 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200638 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200640 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200649 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800652 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000653
654 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800665 return found;
666}
Ma Lingd4906092009-03-18 20:13:27 +0800667
Zhenyu Wang2c072452009-06-05 15:38:42 +0800668static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700672{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300673 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300674 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300675 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300678 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700679
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700683
684 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300689 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700690 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300692 unsigned int ppm, diff;
693
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300696
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300697 vlv_clock(refclk, &clock);
698
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300701 continue;
702
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300707 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300708 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300709 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300710 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300711
Ville Syrjäläc6861222013-09-24 21:26:21 +0300712 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300713 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300714 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300715 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700716 }
717 }
718 }
719 }
720 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700721
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300722 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700723}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700724
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100732 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100739 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300740}
741
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
Daniel Vetter3b117c82013-04-17 20:15:07 +0200748 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200749}
750
Paulo Zanonia928d532012-05-04 17:18:15 -0300751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800771{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700772 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800773 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700774
Paulo Zanonia928d532012-05-04 17:18:15 -0300775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
Chris Wilson300387c2010-09-05 20:25:43 +0100780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700796 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300803static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
807 u32 line1, line2;
808 u32 line_mask;
809
810 if (IS_GEN2(dev))
811 line_mask = DSL_LINEMASK_GEN2;
812 else
813 line_mask = DSL_LINEMASK_GEN3;
814
815 line1 = I915_READ(reg) & line_mask;
816 mdelay(5);
817 line2 = I915_READ(reg) & line_mask;
818
819 return line1 == line2;
820}
821
Keith Packardab7ad7f2010-10-03 00:33:06 -0700822/*
823 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700824 * @dev: drm device
825 * @pipe: pipe to wait for
826 *
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
830 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700831 * On Gen4 and above:
832 * wait for the pipe register state bit to turn off
833 *
834 * Otherwise:
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100837 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700838 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100839void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700840{
841 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
843 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700844
Keith Packardab7ad7f2010-10-03 00:33:06 -0700845 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200846 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700847
Keith Packardab7ad7f2010-10-03 00:33:06 -0700848 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
850 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200851 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700852 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700853 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200855 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700856 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800857}
858
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000859/*
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
863 *
864 * Returns true if @port is connected, false otherwise.
865 */
866bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
868{
869 u32 bit;
870
Damien Lespiauc36346e2012-12-13 16:09:03 +0000871 if (HAS_PCH_IBX(dev_priv->dev)) {
872 switch(port->port) {
873 case PORT_B:
874 bit = SDE_PORTB_HOTPLUG;
875 break;
876 case PORT_C:
877 bit = SDE_PORTC_HOTPLUG;
878 break;
879 case PORT_D:
880 bit = SDE_PORTD_HOTPLUG;
881 break;
882 default:
883 return true;
884 }
885 } else {
886 switch(port->port) {
887 case PORT_B:
888 bit = SDE_PORTB_HOTPLUG_CPT;
889 break;
890 case PORT_C:
891 bit = SDE_PORTC_HOTPLUG_CPT;
892 break;
893 case PORT_D:
894 bit = SDE_PORTD_HOTPLUG_CPT;
895 break;
896 default:
897 return true;
898 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000899 }
900
901 return I915_READ(SDEISR) & bit;
902}
903
Jesse Barnesb24e7172011-01-04 15:09:30 -0800904static const char *state_string(bool enabled)
905{
906 return enabled ? "on" : "off";
907}
908
909/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +0200910void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800912{
913 int reg;
914 u32 val;
915 bool cur_state;
916
917 reg = DPLL(pipe);
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
923}
Jesse Barnesb24e7172011-01-04 15:09:30 -0800924
Jani Nikula23538ef2013-08-27 15:12:22 +0300925/* XXX: the dsi pll is shared between MIPI DSI ports */
926static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
927{
928 u32 val;
929 bool cur_state;
930
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
934
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939}
940#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
942
Daniel Vetter55607e82013-06-16 21:42:39 +0200943struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +0200944intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -0800945{
Daniel Vettere2b78262013-06-07 23:10:03 +0200946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
947
Daniel Vettera43f6e02013-06-07 23:10:32 +0200948 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +0200949 return NULL;
950
Daniel Vettera43f6e02013-06-07 23:10:32 +0200951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +0200952}
953
Jesse Barnesb24e7172011-01-04 15:09:30 -0800954/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +0200955void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
957 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -0800958{
Jesse Barnes040484a2011-01-03 12:14:26 -0800959 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +0200960 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -0800961
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -0300962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
964 return;
965 }
966
Chris Wilson92b27b02012-05-20 18:10:50 +0100967 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +0200968 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100969 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100970
Daniel Vetter53589012013-06-05 13:34:16 +0200971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +0100972 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +0200973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -0800975}
Jesse Barnes040484a2011-01-03 12:14:26 -0800976
977static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
979{
980 int reg;
981 u32 val;
982 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -0200983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
984 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -0800985
Paulo Zanoniaffa9352012-11-23 15:30:39 -0200986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -0200988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300989 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -0200990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300991 } else {
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
995 }
Jesse Barnes040484a2011-01-03 12:14:26 -0800996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999}
1000#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1028 return;
1029
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001031 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001032 return;
1033
Jesse Barnes040484a2011-01-03 12:14:26 -08001034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037}
1038
Daniel Vetter55607e82013-06-16 21:42:39 +02001039void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001041{
1042 int reg;
1043 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001044 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001045
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001052}
1053
Jesse Barnesea0760c2011-01-04 15:09:32 -08001054static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int pp_reg, lvds_reg;
1058 u32 val;
1059 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001060 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001061
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1065 } else {
1066 pp_reg = PP_CONTROL;
1067 lvds_reg = LVDS;
1068 }
1069
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073 locked = false;
1074
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1077
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001080 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001081}
1082
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001083static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085{
1086 struct drm_device *dev = dev_priv->dev;
1087 bool cur_state;
1088
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093 else
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1099}
1100#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001103void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001105{
1106 int reg;
1107 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001108 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001111
Daniel Vetter8e636782012-01-22 01:36:48 +01001112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
Paulo Zanonib97186f2013-05-03 12:15:36 -03001116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001127 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001128}
1129
Chris Wilson931872f2012-01-16 23:01:13 +00001130static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001132{
1133 int reg;
1134 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001135 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001143}
1144
Chris Wilson931872f2012-01-16 23:01:13 +00001145#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
Jesse Barnesb24e7172011-01-04 15:09:30 -08001148static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001151 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001152 int reg, i;
1153 u32 val;
1154 int cur_pipe;
1155
Ville Syrjälä653e1022013-06-04 13:49:05 +03001156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1162 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001163 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001164 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001165
Jesse Barnesb24e7172011-01-04 15:09:30 -08001166 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001167 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001168 reg = DSPCNTR(i);
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001175 }
1176}
1177
Jesse Barnes19332d72013-03-28 09:55:38 -07001178static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001181 struct drm_device *dev = dev_priv->dev;
Jesse Barnes19332d72013-03-28 09:55:38 -07001182 int reg, i;
1183 u32 val;
1184
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1192 }
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1194 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001195 val = I915_READ(reg);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001196 WARN((val & SPRITE_ENABLE),
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & DVS_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001205 }
1206}
1207
Jesse Barnes92f25842011-01-04 15:09:34 -08001208static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209{
1210 u32 val;
1211 bool enabled;
1212
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215 return;
1216 }
1217
Jesse Barnes92f25842011-01-04 15:09:34 -08001218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222}
1223
Daniel Vetterab9412b2013-05-03 11:49:46 +02001224static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001226{
1227 int reg;
1228 u32 val;
1229 bool enabled;
1230
Daniel Vetterab9412b2013-05-03 11:49:46 +02001231 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001234 WARN(enabled,
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001237}
1238
Keith Packard4e634382011-08-06 10:39:45 -07001239static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001241{
1242 if ((val & DP_PORT_EN) == 0)
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249 return false;
1250 } else {
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 return false;
1253 }
1254 return true;
1255}
1256
Keith Packard1519b992011-08-06 10:35:34 -07001257static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001260 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001261 return false;
1262
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001265 return false;
1266 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001268 return false;
1269 }
1270 return true;
1271}
1272
1273static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1275{
1276 if ((val & LVDS_PORT_EN) == 0)
1277 return false;
1278
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
1289static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1291{
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1293 return false;
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296 return false;
1297 } else {
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 return false;
1300 }
1301 return true;
1302}
1303
Jesse Barnes291906f2011-02-02 12:28:03 -08001304static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001305 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001306{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001307 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001310 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001311
Daniel Vetter75c5da22012-09-10 21:58:29 +02001312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001314 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001315}
1316
1317static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1319{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001320 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001323 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001324
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001326 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001327 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001328}
1329
1330static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332{
1333 int reg;
1334 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001335
Keith Packardf0575e92011-07-25 22:12:43 -07001336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001339
1340 reg = PCH_ADPA;
1341 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001343 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001344 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001345
1346 reg = PCH_LVDS;
1347 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001350 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001351
Paulo Zanonie2debe92013-02-18 19:00:27 -03001352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001355}
1356
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001357static void intel_init_dpio(struct drm_device *dev)
1358{
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361 if (!IS_VALLEYVIEW(dev))
1362 return;
1363
1364 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1369 * to 0.
1370 *
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373 */
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375}
1376
Daniel Vetter426115c2013-07-11 22:13:42 +02001377static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001378{
Daniel Vetter426115c2013-07-11 22:13:42 +02001379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001383
Daniel Vetter426115c2013-07-11 22:13:42 +02001384 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001385
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001386 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001391 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001392
Daniel Vetter426115c2013-07-11 22:13:42 +02001393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150);
1396
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001402
1403 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001404 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001407 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001410 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
1413}
1414
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001415static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001416{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001421
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001422 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001423
1424 /* No really, not for ILK+ */
1425 BUG_ON(dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001426
1427 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001430
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001431 I915_WRITE(reg, dpll);
1432
1433 /* Wait for the clocks to stabilize. */
1434 POSTING_READ(reg);
1435 udelay(150);
1436
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1440 } else {
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1443 *
1444 * So write it again.
1445 */
1446 I915_WRITE(reg, dpll);
1447 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001448
1449 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001450 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001453 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001456 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001462 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001470static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001471{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474 return;
1475
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1478
Daniel Vetter50b44a42013-06-05 13:34:33 +02001479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001481}
1482
Jesse Barnesf6071162013-10-01 10:41:38 -07001483static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484{
1485 u32 val = 0;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 /* Leave integrated clock source enabled */
1491 if (pipe == PIPE_B)
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1495}
1496
Jesse Barnes89b667f2013-04-18 14:51:36 -07001497void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498{
1499 u32 port_mask;
1500
1501 if (!port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1503 else
1504 port_mask = DPLL_PORTC_READY_MASK;
1505
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1509}
1510
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001511/**
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001512 * ironlake_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1515 *
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1518 */
Daniel Vettere2b78262013-06-07 23:10:03 +02001519static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001520{
Daniel Vettere2b78262013-06-07 23:10:03 +02001521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001523
Chris Wilson48da64a2012-05-13 20:16:12 +01001524 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001525 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001526 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001527 return;
1528
1529 if (WARN_ON(pll->refcount == 0))
1530 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001531
Daniel Vetter46edb022013-06-05 13:34:12 +02001532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001534 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001535
Daniel Vettercdbd2312013-06-05 13:34:03 +02001536 if (pll->active++) {
1537 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001538 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001539 return;
1540 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001541 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001542
Daniel Vetter46edb022013-06-05 13:34:12 +02001543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001544 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001545 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001546}
1547
Daniel Vettere2b78262013-06-07 23:10:03 +02001548static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001549{
Daniel Vettere2b78262013-06-07 23:10:03 +02001550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001552
Jesse Barnes92f25842011-01-04 15:09:34 -08001553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001555 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001556 return;
1557
Chris Wilson48da64a2012-05-13 20:16:12 +01001558 if (WARN_ON(pll->refcount == 0))
1559 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001560
Daniel Vetter46edb022013-06-05 13:34:12 +02001561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001563 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001564
Chris Wilson48da64a2012-05-13 20:16:12 +01001565 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001566 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001567 return;
1568 }
1569
Daniel Vettere9d69442013-06-05 13:34:15 +02001570 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001571 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001572 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001573 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001574
Daniel Vetter46edb022013-06-05 13:34:12 +02001575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001576 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001577 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001578}
1579
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001582{
Daniel Vetter23670b322012-11-01 09:15:30 +01001583 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001586 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001587
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1590
1591 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001592 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001593 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
Daniel Vetter23670b322012-11-01 09:15:30 +01001599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001606 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001607
Daniel Vetterab9412b2013-05-03 11:49:46 +02001608 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001609 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001610 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001619 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001628 else
1629 val |= TRANS_PROGRESSIVE;
1630
Jesse Barnes040484a2011-01-03 12:14:26 -08001631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001634}
1635
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001637 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001638{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001639 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001644 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001647
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001653 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001655
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001658 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001659 else
1660 val |= TRANS_PROGRESSIVE;
1661
Daniel Vetterab9412b2013-05-03 11:49:46 +02001662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001664 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001665}
1666
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001669{
Daniel Vetter23670b322012-11-01 09:15:30 +01001670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
Jesse Barnes291906f2011-02-02 12:28:03 -08001677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
Daniel Vetterab9412b2013-05-03 11:49:46 +02001680 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001695}
1696
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001698{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001699 u32 val;
1700
Daniel Vetterab9412b2013-05-03 11:49:46 +02001701 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001702 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001703 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001704 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001706 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001711 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001712}
1713
1714/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001715 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03001729 bool pch_port, bool dsi)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001730{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001733 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001734 int reg;
1735 u32 val;
1736
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001737 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001738 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001739 assert_sprites_disabled(dev_priv, pipe);
1740
Paulo Zanoni681e5812012-12-06 11:12:38 -02001741 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001742 pch_transcoder = TRANSCODER_A;
1743 else
1744 pch_transcoder = pipe;
1745
Jesse Barnesb24e7172011-01-04 15:09:30 -08001746 /*
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1749 * need the check.
1750 */
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
Jani Nikula23538ef2013-08-27 15:12:22 +03001752 if (dsi)
1753 assert_dsi_pll_enabled(dev_priv);
1754 else
1755 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001756 else {
1757 if (pch_port) {
1758 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001762 }
1763 /* FIXME: assert CPU port conditions for SNB+ */
1764 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001765
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001766 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001767 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001768 if (val & PIPECONF_ENABLE)
1769 return;
1770
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
1775/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001776 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1779 *
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782 *
1783 * @pipe should be %PIPE_A or %PIPE_B.
1784 *
1785 * Will wait until the pipe has shut down before returning.
1786 */
1787static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788 enum pipe pipe)
1789{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001792 int reg;
1793 u32 val;
1794
1795 /*
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1798 */
1799 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001800 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001801 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001802
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805 return;
1806
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001807 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001808 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001809 if ((val & PIPECONF_ENABLE) == 0)
1810 return;
1811
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814}
1815
Keith Packardd74362c2011-07-28 14:47:14 -07001816/*
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1819 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001820void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07001822{
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825 I915_WRITE(reg, I915_READ(reg));
1826 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07001827}
1828
Jesse Barnesb24e7172011-01-04 15:09:30 -08001829/**
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001830 * intel_enable_primary_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1834 *
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1836 */
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001837static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001839{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001842 int reg;
1843 u32 val;
1844
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1847
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
Ville Syrjälä0037f712013-10-01 18:02:20 +03001849
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001850 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001851
Jesse Barnesb24e7172011-01-04 15:09:30 -08001852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001858 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
Jesse Barnesb24e7172011-01-04 15:09:30 -08001862/**
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001863 * intel_disable_primary_plane - disable the primary plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08001864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001870static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001872{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001875 int reg;
1876 u32 val;
1877
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
Ville Syrjälä0037f712013-10-01 18:02:20 +03001879
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001880 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001881
Jesse Barnesb24e7172011-01-04 15:09:30 -08001882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001888 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001889 intel_wait_for_vblank(dev_priv->dev, pipe);
1890}
1891
Chris Wilson693db182013-03-05 14:52:39 +00001892static bool need_vtd_wa(struct drm_device *dev)
1893{
1894#ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896 return true;
1897#endif
1898 return false;
1899}
1900
Chris Wilson127bd2a2010-07-23 23:32:05 +01001901int
Chris Wilson48b956c2010-09-14 12:50:34 +01001902intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001903 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001904 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001905{
Chris Wilsonce453d82011-02-21 14:43:56 +00001906 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001907 u32 alignment;
1908 int ret;
1909
Chris Wilson05394f32010-11-08 19:18:58 +00001910 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001911 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001914 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001915 alignment = 4 * 1024;
1916 else
1917 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001918 break;
1919 case I915_TILING_X:
1920 /* pin() will align the object as required by fence */
1921 alignment = 0;
1922 break;
1923 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02001924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
Chris Wilson693db182013-03-05 14:52:39 +00001930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1933 * the VT-d warning.
1934 */
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1937
Chris Wilsonce453d82011-02-21 14:43:56 +00001938 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001940 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001941 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001942
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1947 */
Chris Wilson06d98132012-04-17 15:31:24 +01001948 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001949 if (ret)
1950 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001951
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001952 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001953
Chris Wilsonce453d82011-02-21 14:43:56 +00001954 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001955 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001956
1957err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01001958 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001959err_interruptible:
1960 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001961 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001962}
1963
Chris Wilson1690e1e2011-12-14 13:57:08 +01001964void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965{
1966 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01001967 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01001968}
1969
Daniel Vetterc2c75132012-07-05 12:17:30 +02001970/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00001972unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1974 unsigned int cpp,
1975 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02001976{
Chris Wilsonbc752862013-02-21 20:04:31 +00001977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001979
Chris Wilsonbc752862013-02-21 20:04:31 +00001980 tile_rows = *y / 8;
1981 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02001982
Chris Wilsonbc752862013-02-21 20:04:31 +00001983 tiles = *x / (512/cpp);
1984 *x %= 512/cpp;
1985
1986 return tile_rows * pitch * 8 + tiles * 4096;
1987 } else {
1988 unsigned int offset;
1989
1990 offset = *y * pitch + *x * cpp;
1991 *y = 0;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1994 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02001995}
1996
Jesse Barnes17638cd2011-06-24 12:19:23 -07001997static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001999{
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002004 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002005 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002006 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002007 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002008 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002009
2010 switch (plane) {
2011 case 0:
2012 case 1:
2013 break;
2014 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes81255562010-08-02 12:07:50 -07002016 return -EINVAL;
2017 }
2018
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002021
Chris Wilson5eddb702010-09-11 13:48:45 +01002022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002026 switch (fb->pixel_format) {
2027 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002028 dspcntr |= DISPPLANE_8BPP;
2029 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002033 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2036 break;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2040 break;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2044 break;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2048 break;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002052 break;
2053 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002054 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002055 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002056
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002057 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002058 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002059 dspcntr |= DISPPLANE_TILED;
2060 else
2061 dspcntr &= ~DISPPLANE_TILED;
2062 }
2063
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002064 if (IS_G4X(dev))
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
Chris Wilson5eddb702010-09-11 13:48:45 +01002067 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002068
Daniel Vettere506a0c2012-07-05 12:17:29 +02002069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002070
Daniel Vetterc2c75132012-07-05 12:17:30 +02002071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2075 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002076 linear_offset -= intel_crtc->dspaddr_offset;
2077 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002078 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002079 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002080
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002085 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002086 I915_MODIFY_DISPBASE(DSPSURF(plane),
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002089 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002090 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002092 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002093
Jesse Barnes17638cd2011-06-24 12:19:23 -07002094 return 0;
2095}
2096
2097static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2099{
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002106 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002107 u32 dspcntr;
2108 u32 reg;
2109
2110 switch (plane) {
2111 case 0:
2112 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002113 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002114 break;
2115 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes17638cd2011-06-24 12:19:23 -07002117 return -EINVAL;
2118 }
2119
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2122
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002127 switch (fb->pixel_format) {
2128 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002129 dspcntr |= DISPPLANE_8BPP;
2130 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002133 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2137 break;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2141 break;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2145 break;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002149 break;
2150 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002151 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002159 if (IS_HASWELL(dev))
2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161 else
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002163
2164 I915_WRITE(reg, dspcntr);
2165
Daniel Vettere506a0c2012-07-05 12:17:29 +02002166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002167 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2170 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002171 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002172
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002177 I915_MODIFY_DISPBASE(DSPSURF(plane),
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002179 if (IS_HASWELL(dev)) {
2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181 } else {
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002185 POSTING_READ(reg);
2186
2187 return 0;
2188}
2189
2190/* Assume fb object is pinned & idle & fenced and just update base pointers */
2191static int
2192intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2194{
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002197
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002200 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002201
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002202 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002203}
2204
Ville Syrjälä96a02912013-02-18 19:08:49 +02002205void intel_display_handle_reset(struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2209
2210 /*
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2214 *
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2218 *
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2222 */
2223
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2227
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2230 }
2231
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex);
2240 }
2241}
2242
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002243static int
Chris Wilson14667a42012-04-03 17:58:35 +01002244intel_finish_fb(struct drm_framebuffer *old_fb)
2245{
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2249 int ret;
2250
Chris Wilson14667a42012-04-03 17:58:35 +01002251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2254 * framebuffer.
2255 *
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2258 */
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2262
2263 return ret;
2264}
2265
Ville Syrjälä198598d2012-10-31 17:50:24 +02002266static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267{
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272 if (!dev->primary->master)
2273 return;
2274
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2277 return;
2278
2279 switch (intel_crtc->pipe) {
2280 case 0:
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2283 break;
2284 case 1:
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2287 break;
2288 default:
2289 break;
2290 }
2291}
2292
Chris Wilson14667a42012-04-03 17:58:35 +01002293static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002294intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002295 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002296{
2297 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002298 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002300 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002301 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002302
2303 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002304 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002305 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002306 return 0;
2307 }
2308
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002313 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002314 }
2315
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002316 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002317 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002318 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002319 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002320 if (ret != 0) {
2321 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002322 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002323 return ret;
2324 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002325
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002326 /*
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * sized surface.
2333 *
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2338 */
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002339 if (i915_fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2342
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002343 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002346 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352 }
2353 }
2354
Daniel Vetter94352cf2012-07-05 22:51:56 +02002355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002356 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002358 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002359 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002360 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002361 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002362
Daniel Vetter94352cf2012-07-05 22:51:56 +02002363 old_fb = crtc->fb;
2364 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002365 crtc->x = x;
2366 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002367
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002368 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002372 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002373
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002374 intel_update_fbc(dev);
Rodrigo Vivi49065572013-07-11 18:45:05 -03002375 intel_edp_psr_update(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002376 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002377
Ville Syrjälä198598d2012-10-31 17:50:24 +02002378 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002379
2380 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002381}
2382
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002383static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002394 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002400 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002422}
2423
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002424static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002425{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002426 return crtc->base.enabled && crtc->active &&
2427 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002428}
2429
Daniel Vetter01a415f2012-10-27 15:58:40 +02002430static void ivb_modeset_global_resources(struct drm_device *dev)
2431{
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *pipe_B_crtc =
2434 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435 struct intel_crtc *pipe_C_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437 uint32_t temp;
2438
Daniel Vetter1e833f42013-02-19 22:31:57 +01002439 /*
2440 * When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. Note that we don't care about enabled pipes without
2442 * an enabled pch encoder.
2443 */
2444 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454}
2455
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002456/* The FDI link training functions for ILK/Ibexpeak. */
2457static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002463 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002464 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002465
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
Adam Jacksone1a44742010-06-25 15:32:14 -04002470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002478 udelay(150);
2479
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002480 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002488
Chris Wilson5eddb702010-09-11 13:48:45 +01002489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002496 udelay(150);
2497
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002498 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002502
Chris Wilson5eddb702010-09-11 13:48:45 +01002503 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002504 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002505 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002511 break;
2512 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002513 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002514 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002515 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002516
2517 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002522 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002523
Chris Wilson5eddb702010-09-11 13:48:45 +01002524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002531 udelay(150);
2532
Chris Wilson5eddb702010-09-11 13:48:45 +01002533 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002534 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002535 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002543 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002544 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002545 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002546
2547 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002548
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002549}
2550
Akshay Joshi0206e352011-08-16 15:34:10 -04002551static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556};
2557
2558/* The FDI link training functions for SNB/Cougarpoint. */
2559static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560{
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002565 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002566
Adam Jacksone1a44742010-06-25 15:32:14 -04002567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002576 udelay(150);
2577
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002578 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002581 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002589
Daniel Vetterd74cf322012-10-26 10:58:13 +02002590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
Chris Wilson5eddb702010-09-11 13:48:45 +01002593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002605 udelay(150);
2606
Akshay Joshi0206e352011-08-16 15:34:10 -04002607 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002615 udelay(500);
2616
Sean Paulfa37d392012-03-02 12:53:39 -05002617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 break;
2625 }
2626 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002627 }
Sean Paulfa37d392012-03-02 12:53:39 -05002628 if (retry < 5)
2629 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002630 }
2631 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002632 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002633
2634 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 if (IS_GEN6(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 /* SNB-B */
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002644 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002645
Chris Wilson5eddb702010-09-11 13:48:45 +01002646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 } else {
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002658 udelay(150);
2659
Akshay Joshi0206e352011-08-16 15:34:10 -04002660 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002668 udelay(500);
2669
Sean Paulfa37d392012-03-02 12:53:39 -05002670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002680 }
Sean Paulfa37d392012-03-02 12:53:39 -05002681 if (retry < 5)
2682 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002683 }
2684 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002685 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688}
2689
Jesse Barnes357555c2011-04-28 15:09:55 -07002690/* Manual link training for Ivy Bridge A0 parts */
2691static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692{
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07002697 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07002698
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 for train result */
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
Daniel Vetter01a415f2012-10-27 15:58:40 +02002710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2712
Jesse Barnes139ccd32013-08-19 11:04:55 -07002713 /* Try each vswing and preemphasis setting twice before moving on */
2714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07002716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07002718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp &= ~FDI_TX_ENABLE;
2720 I915_WRITE(reg, temp);
2721
2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_AUTO;
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp &= ~FDI_RX_ENABLE;
2727 I915_WRITE(reg, temp);
2728
2729 /* enable CPU FDI TX and PCH FDI RX */
2730 reg = FDI_TX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07002735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07002736 temp |= snb_b_fdi_train_param[j/2];
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2748
2749 POSTING_READ(reg);
2750 udelay(1); /* should be 0.5us */
2751
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2756
2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761 i);
2762 break;
2763 }
2764 udelay(1); /* should be 0.5us */
2765 }
2766 if (i == 4) {
2767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2768 continue;
2769 }
2770
2771 /* Train 2 */
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 I915_WRITE(reg, temp);
2777
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07002782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07002785 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07002786
Jesse Barnes139ccd32013-08-19 11:04:55 -07002787 for (i = 0; i < 4; i++) {
2788 reg = FDI_RX_IIR(pipe);
2789 temp = I915_READ(reg);
2790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07002791
Jesse Barnes139ccd32013-08-19 11:04:55 -07002792 if (temp & FDI_RX_SYMBOL_LOCK ||
2793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796 i);
2797 goto train_done;
2798 }
2799 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07002800 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07002801 if (i == 4)
2802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07002803 }
Jesse Barnes357555c2011-04-28 15:09:55 -07002804
Jesse Barnes139ccd32013-08-19 11:04:55 -07002805train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07002806 DRM_DEBUG_KMS("FDI train done.\n");
2807}
2808
Daniel Vetter88cefb62012-08-12 19:27:14 +02002809static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002810{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002811 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002812 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002813 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002814 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002815
Jesse Barnesc64e3112010-09-10 11:27:03 -07002816
Jesse Barnes0e23b992010-09-10 11:10:00 -07002817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01002823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002826 udelay(200);
2827
2828 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002833 udelay(200);
2834
Paulo Zanoni20749732012-11-23 15:30:38 -02002835 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002840
Paulo Zanoni20749732012-11-23 15:30:38 -02002841 POSTING_READ(reg);
2842 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002843 }
2844}
2845
Daniel Vetter88cefb62012-08-12 19:27:14 +02002846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002875static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002901 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926}
2927
Chris Wilson5bb61642012-09-27 21:25:58 +01002928static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä10d83732013-01-29 18:13:34 +02002932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5bb61642012-09-27 21:25:58 +01002933 unsigned long flags;
2934 bool pending;
2935
Ville Syrjälä10d83732013-01-29 18:13:34 +02002936 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
Chris Wilson5bb61642012-09-27 21:25:58 +01002938 return false;
2939
2940 spin_lock_irqsave(&dev->event_lock, flags);
2941 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942 spin_unlock_irqrestore(&dev->event_lock, flags);
2943
2944 return pending;
2945}
2946
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002947static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2948{
Chris Wilson0f911282012-04-17 10:05:38 +01002949 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002950 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002951
2952 if (crtc->fb == NULL)
2953 return;
2954
Daniel Vetter2c10d572012-12-20 21:24:07 +01002955 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2956
Chris Wilson5bb61642012-09-27 21:25:58 +01002957 wait_event(dev_priv->pending_flip_queue,
2958 !intel_crtc_has_pending_flip(crtc));
2959
Chris Wilson0f911282012-04-17 10:05:38 +01002960 mutex_lock(&dev->struct_mutex);
2961 intel_finish_fb(crtc->fb);
2962 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002963}
2964
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002965/* Program iCLKIP clock to the desired frequency */
2966static void lpt_program_iclkip(struct drm_crtc *crtc)
2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01002970 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002971 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2972 u32 temp;
2973
Daniel Vetter09153002012-12-12 14:06:44 +01002974 mutex_lock(&dev_priv->dpio_lock);
2975
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002976 /* It is necessary to ungate the pixclk gate prior to programming
2977 * the divisors, and gate it back when it is done.
2978 */
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2980
2981 /* Disable SSCCTL */
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02002983 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984 SBI_SSCCTL_DISABLE,
2985 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002986
2987 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03002988 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002989 auxdiv = 1;
2990 divsel = 0x41;
2991 phaseinc = 0x20;
2992 } else {
2993 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01002994 * but the adjusted_mode->crtc_clock in in KHz. To get the
2995 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002996 * convert the virtual clock precision to KHz here for higher
2997 * precision.
2998 */
2999 u32 iclk_virtual_root_freq = 172800 * 1000;
3000 u32 iclk_pi_range = 64;
3001 u32 desired_divisor, msb_divisor_value, pi_value;
3002
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003003 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003004 msb_divisor_value = desired_divisor / iclk_pi_range;
3005 pi_value = desired_divisor % iclk_pi_range;
3006
3007 auxdiv = 0;
3008 divsel = msb_divisor_value - 2;
3009 phaseinc = pi_value;
3010 }
3011
3012 /* This should not happen with any sane values */
3013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3017
3018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003019 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003020 auxdiv,
3021 divsel,
3022 phasedir,
3023 phaseinc);
3024
3025 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003026 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003027 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003033 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003034
3035 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003036 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003037 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003039 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003040
3041 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003043 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003044 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003045
3046 /* Wait for initialization time */
3047 udelay(24);
3048
3049 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003050
3051 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003052}
3053
Daniel Vetter275f01b22013-05-03 11:49:47 +02003054static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055 enum pipe pch_transcoder)
3056{
3057 struct drm_device *dev = crtc->base.dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3060
3061 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062 I915_READ(HTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064 I915_READ(HBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066 I915_READ(HSYNC(cpu_transcoder)));
3067
3068 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069 I915_READ(VTOTAL(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071 I915_READ(VBLANK(cpu_transcoder)));
3072 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073 I915_READ(VSYNC(cpu_transcoder)));
3074 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076}
3077
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003078static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3079{
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 uint32_t temp;
3082
3083 temp = I915_READ(SOUTH_CHICKEN1);
3084 if (temp & FDI_BC_BIFURCATION_SELECT)
3085 return;
3086
3087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3089
3090 temp |= FDI_BC_BIFURCATION_SELECT;
3091 DRM_DEBUG_KMS("enabling fdi C rx\n");
3092 I915_WRITE(SOUTH_CHICKEN1, temp);
3093 POSTING_READ(SOUTH_CHICKEN1);
3094}
3095
3096static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3097{
3098 struct drm_device *dev = intel_crtc->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 switch (intel_crtc->pipe) {
3102 case PIPE_A:
3103 break;
3104 case PIPE_B:
3105 if (intel_crtc->config.fdi_lanes > 2)
3106 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3107 else
3108 cpt_enable_fdi_bc_bifurcation(dev);
3109
3110 break;
3111 case PIPE_C:
3112 cpt_enable_fdi_bc_bifurcation(dev);
3113
3114 break;
3115 default:
3116 BUG();
3117 }
3118}
3119
Jesse Barnesf67a5592011-01-05 10:31:48 -08003120/*
3121 * Enable PCH resources required for PCH ports:
3122 * - PCH PLLs
3123 * - FDI training & RX/TX
3124 * - update transcoder timings
3125 * - DP transcoding bits
3126 * - transcoder
3127 */
3128static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003129{
3130 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003134 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003135
Daniel Vetterab9412b2013-05-03 11:49:46 +02003136 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003137
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003138 if (IS_IVYBRIDGE(dev))
3139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3140
Daniel Vettercd986ab2012-10-26 10:58:12 +02003141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003146 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003147 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003148
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003149 /* We need to program the right clock selection before writing the pixel
3150 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003151 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003152 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003153
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003154 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003155 temp |= TRANS_DPLL_ENABLE(pipe);
3156 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003157 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003158 temp |= sel;
3159 else
3160 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003161 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003162 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003163
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003164 /* XXX: pch pll's can be enabled any time before we enable the PCH
3165 * transcoder, and we actually should do this to not upset any PCH
3166 * transcoder that already use the clock when we share it.
3167 *
3168 * Note that enable_shared_dpll tries to do the right thing, but
3169 * get_shared_dpll unconditionally resets the pll - we need that to have
3170 * the right LVDS enable sequence. */
3171 ironlake_enable_shared_dpll(intel_crtc);
3172
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003173 /* set transcoder timing, panel must allow it */
3174 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003176
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003177 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003178
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003179 /* For PCH DP, enable TRANS_DP_CTL */
3180 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003181 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003184 reg = TRANS_DP_CTL(pipe);
3185 temp = I915_READ(reg);
3186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003187 TRANS_DP_SYNC_MASK |
3188 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003189 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003191 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003192
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003197
3198 switch (intel_trans_dp_port_sel(crtc)) {
3199 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003200 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003201 break;
3202 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003203 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003204 break;
3205 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003206 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003207 break;
3208 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003209 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003210 }
3211
Chris Wilson5eddb702010-09-11 13:48:45 +01003212 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003213 }
3214
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003215 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003216}
3217
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003218static void lpt_pch_enable(struct drm_crtc *crtc)
3219{
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003224
Daniel Vetterab9412b2013-05-03 11:49:46 +02003225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003226
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003227 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003228
Paulo Zanoni0540e482012-10-31 18:12:40 -02003229 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003231
Paulo Zanoni937bb612012-10-31 18:12:47 -02003232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003233}
3234
Daniel Vettere2b78262013-06-07 23:10:03 +02003235static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003236{
Daniel Vettere2b78262013-06-07 23:10:03 +02003237 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003238
3239 if (pll == NULL)
3240 return;
3241
3242 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003243 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003244 return;
3245 }
3246
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003247 if (--pll->refcount == 0) {
3248 WARN_ON(pll->on);
3249 WARN_ON(pll->active);
3250 }
3251
Daniel Vettera43f6e02013-06-07 23:10:32 +02003252 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003253}
3254
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003255static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003256{
Daniel Vettere2b78262013-06-07 23:10:03 +02003257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003260
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003261 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003262 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003264 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003265 }
3266
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003267 if (HAS_PCH_IBX(dev_priv->dev)) {
3268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003269 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003270 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003271
Daniel Vetter46edb022013-06-05 13:34:12 +02003272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003274
3275 goto found;
3276 }
3277
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003280
3281 /* Only want to check enabled timings first */
3282 if (pll->refcount == 0)
3283 continue;
3284
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003285 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003288 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003289 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003290
3291 goto found;
3292 }
3293 }
3294
3295 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003298 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003301 goto found;
3302 }
3303 }
3304
3305 return NULL;
3306
3307found:
Daniel Vettera43f6e02013-06-07 23:10:32 +02003308 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003309 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003311
Daniel Vettercdbd2312013-06-05 13:34:03 +02003312 if (pll->active == 0) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02003313 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314 sizeof(pll->hw_state));
3315
Daniel Vetter46edb022013-06-05 13:34:12 +02003316 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003317 WARN_ON(pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02003318 assert_shared_dpll_disabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003319
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02003320 pll->mode_set(dev_priv, pll);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003321 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003322 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003323
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003324 return pll;
3325}
3326
Daniel Vettera1520312013-05-03 11:49:50 +02003327static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003330 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003336 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003337 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003338 }
3339}
3340
Jesse Barnesb074cec2013-04-25 12:55:02 -07003341static void ironlake_pfit_enable(struct intel_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe = crtc->pipe;
3346
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003347 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3350 * e.g. x201.
3351 */
3352 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354 PF_PIPE_SEL_IVB(pipe));
3355 else
3356 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003359 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003360}
3361
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003362static void intel_enable_planes(struct drm_crtc *crtc)
3363{
3364 struct drm_device *dev = crtc->dev;
3365 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366 struct intel_plane *intel_plane;
3367
3368 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369 if (intel_plane->pipe == pipe)
3370 intel_plane_restore(&intel_plane->base);
3371}
3372
3373static void intel_disable_planes(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377 struct intel_plane *intel_plane;
3378
3379 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380 if (intel_plane->pipe == pipe)
3381 intel_plane_disable(&intel_plane->base);
3382}
3383
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003384void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003385{
3386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3387
3388 if (!crtc->config.ips_enabled)
3389 return;
3390
3391 /* We can only enable IPS after we enable a plane and wait for a vblank.
3392 * We guarantee that the plane is enabled by calling intel_enable_ips
3393 * only after intel_enable_plane. And intel_enable_plane already waits
3394 * for a vblank, so all we need to do here is to enable the IPS bit. */
3395 assert_plane_enabled(dev_priv, crtc->plane);
3396 I915_WRITE(IPS_CTL, IPS_ENABLE);
Paulo Zanoni5ade2c22013-09-19 17:03:06 -03003397
3398 /* The bit only becomes 1 in the next vblank, so this wait here is
3399 * essentially intel_wait_for_vblank. If we don't have this and don't
3400 * wait for vblanks until the end of crtc_enable, then the HW state
3401 * readout code will complain that the expected IPS_CTL value is not the
3402 * one we read. */
3403 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3404 DRM_ERROR("Timed out waiting for IPS enable\n");
Paulo Zanonid77e4532013-09-24 13:52:55 -03003405}
3406
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003407void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003408{
3409 struct drm_device *dev = crtc->base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412 if (!crtc->config.ips_enabled)
3413 return;
3414
3415 assert_plane_enabled(dev_priv, crtc->plane);
3416 I915_WRITE(IPS_CTL, 0);
3417 POSTING_READ(IPS_CTL);
3418
3419 /* We need to wait for a vblank before we can disable the plane. */
3420 intel_wait_for_vblank(dev, crtc->pipe);
3421}
3422
3423/** Loads the palette/gamma unit for the CRTC with the prepared values */
3424static void intel_crtc_load_lut(struct drm_crtc *crtc)
3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 enum pipe pipe = intel_crtc->pipe;
3430 int palreg = PALETTE(pipe);
3431 int i;
3432 bool reenable_ips = false;
3433
3434 /* The clocks have to be on to load the palette. */
3435 if (!crtc->enabled || !intel_crtc->active)
3436 return;
3437
3438 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3440 assert_dsi_pll_enabled(dev_priv);
3441 else
3442 assert_pll_enabled(dev_priv, pipe);
3443 }
3444
3445 /* use legacy palette for Ironlake */
3446 if (HAS_PCH_SPLIT(dev))
3447 palreg = LGC_PALETTE(pipe);
3448
3449 /* Workaround : Do not read or write the pipe palette/gamma data while
3450 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3451 */
3452 if (intel_crtc->config.ips_enabled &&
3453 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3454 GAMMA_MODE_MODE_SPLIT)) {
3455 hsw_disable_ips(intel_crtc);
3456 reenable_ips = true;
3457 }
3458
3459 for (i = 0; i < 256; i++) {
3460 I915_WRITE(palreg + 4 * i,
3461 (intel_crtc->lut_r[i] << 16) |
3462 (intel_crtc->lut_g[i] << 8) |
3463 intel_crtc->lut_b[i]);
3464 }
3465
3466 if (reenable_ips)
3467 hsw_enable_ips(intel_crtc);
3468}
3469
Jesse Barnesf67a5592011-01-05 10:31:48 -08003470static void ironlake_crtc_enable(struct drm_crtc *crtc)
3471{
3472 struct drm_device *dev = crtc->dev;
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003475 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003476 int pipe = intel_crtc->pipe;
3477 int plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003478
Daniel Vetter08a48462012-07-02 11:43:47 +02003479 WARN_ON(!crtc->enabled);
3480
Jesse Barnesf67a5592011-01-05 10:31:48 -08003481 if (intel_crtc->active)
3482 return;
3483
3484 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003485
3486 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3487 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3488
Daniel Vetterf6736a12013-06-05 13:34:30 +02003489 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003490 if (encoder->pre_enable)
3491 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003492
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003493 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003494 /* Note: FDI PLL enabling _must_ be done before we enable the
3495 * cpu pipes, hence this is separate from all the other fdi/pch
3496 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003497 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003498 } else {
3499 assert_fdi_tx_disabled(dev_priv, pipe);
3500 assert_fdi_rx_disabled(dev_priv, pipe);
3501 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003502
Jesse Barnesb074cec2013-04-25 12:55:02 -07003503 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003504
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003505 /*
3506 * On ILK+ LUT must be loaded before the pipe is running but with
3507 * clocks enabled
3508 */
3509 intel_crtc_load_lut(crtc);
3510
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003511 intel_update_watermarks(crtc);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003512 intel_enable_pipe(dev_priv, pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03003513 intel_crtc->config.has_pch_encoder, false);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003514 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003515 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003516 intel_crtc_update_cursor(crtc, true);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003517
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003518 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003519 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003520
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003521 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003522 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003523 mutex_unlock(&dev->struct_mutex);
3524
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003527
3528 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003529 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003530
3531 /*
3532 * There seems to be a race in PCH platform hw (at least on some
3533 * outputs) where an enabled pipe still completes any pageflip right
3534 * away (as if the pipe is off) instead of waiting for vblank. As soon
3535 * as the first vblank happend, everything works as expected. Hence just
3536 * wait for one vblank before returning to avoid strange things
3537 * happening.
3538 */
3539 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003540}
3541
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003542/* IPS only exists on ULT machines and is tied to pipe A. */
3543static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3544{
Damien Lespiauf5adf942013-06-24 18:29:34 +01003545 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003546}
3547
Ville Syrjälädda9a662013-09-19 17:00:37 -03003548static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3549{
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 int pipe = intel_crtc->pipe;
3554 int plane = intel_crtc->plane;
3555
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003556 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003557 intel_enable_planes(crtc);
3558 intel_crtc_update_cursor(crtc, true);
3559
3560 hsw_enable_ips(intel_crtc);
3561
3562 mutex_lock(&dev->struct_mutex);
3563 intel_update_fbc(dev);
3564 mutex_unlock(&dev->struct_mutex);
3565}
3566
3567static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3568{
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
3573 int plane = intel_crtc->plane;
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577
3578 /* FBC must be disabled before disabling the plane on HSW. */
3579 if (dev_priv->fbc.plane == plane)
3580 intel_disable_fbc(dev);
3581
3582 hsw_disable_ips(intel_crtc);
3583
3584 intel_crtc_update_cursor(crtc, false);
3585 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003586 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003587}
3588
Paulo Zanonie4916942013-09-20 16:21:19 -03003589/*
3590 * This implements the workaround described in the "notes" section of the mode
3591 * set sequence documentation. When going from no pipes or single pipe to
3592 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3593 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3594 */
3595static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3596{
3597 struct drm_device *dev = crtc->base.dev;
3598 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3599
3600 /* We want to get the other_active_crtc only if there's only 1 other
3601 * active crtc. */
3602 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3603 if (!crtc_it->active || crtc_it == crtc)
3604 continue;
3605
3606 if (other_active_crtc)
3607 return;
3608
3609 other_active_crtc = crtc_it;
3610 }
3611 if (!other_active_crtc)
3612 return;
3613
3614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3615 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3616}
3617
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003618static void haswell_crtc_enable(struct drm_crtc *crtc)
3619{
3620 struct drm_device *dev = crtc->dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 struct intel_encoder *encoder;
3624 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003625
3626 WARN_ON(!crtc->enabled);
3627
3628 if (intel_crtc->active)
3629 return;
3630
3631 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003632
3633 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3634 if (intel_crtc->config.has_pch_encoder)
3635 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3636
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003637 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02003638 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003639
3640 for_each_encoder_on_crtc(dev, crtc, encoder)
3641 if (encoder->pre_enable)
3642 encoder->pre_enable(encoder);
3643
Paulo Zanoni1f544382012-10-24 11:32:00 -02003644 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003645
Jesse Barnesb074cec2013-04-25 12:55:02 -07003646 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003647
3648 /*
3649 * On ILK+ LUT must be loaded before the pipe is running but with
3650 * clocks enabled
3651 */
3652 intel_crtc_load_lut(crtc);
3653
Paulo Zanoni1f544382012-10-24 11:32:00 -02003654 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00003655 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003656
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003657 intel_update_watermarks(crtc);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003658 intel_enable_pipe(dev_priv, pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03003659 intel_crtc->config.has_pch_encoder, false);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003660
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003661 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003662 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003663
Jani Nikula8807e552013-08-30 19:40:32 +03003664 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003665 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03003666 intel_opregion_notify_encoder(encoder, true);
3667 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003668
Paulo Zanonie4916942013-09-20 16:21:19 -03003669 /* If we change the relative order between pipe/planes enabling, we need
3670 * to change the workaround. */
3671 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003672 haswell_crtc_enable_planes(crtc);
3673
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003674 /*
3675 * There seems to be a race in PCH platform hw (at least on some
3676 * outputs) where an enabled pipe still completes any pageflip right
3677 * away (as if the pipe is off) instead of waiting for vblank. As soon
3678 * as the first vblank happend, everything works as expected. Hence just
3679 * wait for one vblank before returning to avoid strange things
3680 * happening.
3681 */
3682 intel_wait_for_vblank(dev, intel_crtc->pipe);
3683}
3684
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003685static void ironlake_pfit_disable(struct intel_crtc *crtc)
3686{
3687 struct drm_device *dev = crtc->base.dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 int pipe = crtc->pipe;
3690
3691 /* To avoid upsetting the power well on haswell only disable the pfit if
3692 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003693 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003694 I915_WRITE(PF_CTL(pipe), 0);
3695 I915_WRITE(PF_WIN_POS(pipe), 0);
3696 I915_WRITE(PF_WIN_SZ(pipe), 0);
3697 }
3698}
3699
Jesse Barnes6be4a602010-09-10 10:26:01 -07003700static void ironlake_crtc_disable(struct drm_crtc *crtc)
3701{
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003705 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003708 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003709
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003710
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003711 if (!intel_crtc->active)
3712 return;
3713
Daniel Vetterea9d7582012-07-10 10:42:52 +02003714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->disable(encoder);
3716
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003717 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003718 drm_vblank_off(dev, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003719
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07003720 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01003721 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003722
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003723 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003724 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003725 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003726
Daniel Vetterd925c592013-06-05 13:34:04 +02003727 if (intel_crtc->config.has_pch_encoder)
3728 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3729
Jesse Barnesb24e7172011-01-04 15:09:30 -08003730 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003731
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003732 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003733
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->post_disable)
3736 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003737
Daniel Vetterd925c592013-06-05 13:34:04 +02003738 if (intel_crtc->config.has_pch_encoder) {
3739 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003740
Daniel Vetterd925c592013-06-05 13:34:04 +02003741 ironlake_disable_pch_transcoder(dev_priv, pipe);
3742 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003743
Daniel Vetterd925c592013-06-05 13:34:04 +02003744 if (HAS_PCH_CPT(dev)) {
3745 /* disable TRANS_DP_CTL */
3746 reg = TRANS_DP_CTL(pipe);
3747 temp = I915_READ(reg);
3748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3749 TRANS_DP_PORT_SEL_MASK);
3750 temp |= TRANS_DP_PORT_SEL_NONE;
3751 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003752
Daniel Vetterd925c592013-06-05 13:34:04 +02003753 /* disable DPLL_SEL */
3754 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02003756 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003757 }
Daniel Vetterd925c592013-06-05 13:34:04 +02003758
3759 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003760 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02003761
3762 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003763 }
3764
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003765 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003766 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003767
3768 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003769 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003770 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003771}
3772
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003773static void haswell_crtc_disable(struct drm_crtc *crtc)
3774{
3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778 struct intel_encoder *encoder;
3779 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02003780 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003781
3782 if (!intel_crtc->active)
3783 return;
3784
Ville Syrjälädda9a662013-09-19 17:00:37 -03003785 haswell_crtc_disable_planes(crtc);
3786
Jani Nikula8807e552013-08-30 19:40:32 +03003787 for_each_encoder_on_crtc(dev, crtc, encoder) {
3788 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003789 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03003790 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003791
Paulo Zanoni86642812013-04-12 17:57:57 -03003792 if (intel_crtc->config.has_pch_encoder)
3793 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003794 intel_disable_pipe(dev_priv, pipe);
3795
Paulo Zanoniad80a812012-10-24 16:06:19 -02003796 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003797
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003798 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003799
Paulo Zanoni1f544382012-10-24 11:32:00 -02003800 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003801
3802 for_each_encoder_on_crtc(dev, crtc, encoder)
3803 if (encoder->post_disable)
3804 encoder->post_disable(encoder);
3805
Daniel Vetter88adfff2013-03-28 10:42:01 +01003806 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003807 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03003808 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003809 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003810 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003811
3812 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003813 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003814
3815 mutex_lock(&dev->struct_mutex);
3816 intel_update_fbc(dev);
3817 mutex_unlock(&dev->struct_mutex);
3818}
3819
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003820static void ironlake_crtc_off(struct drm_crtc *crtc)
3821{
3822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003823 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003824}
3825
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003826static void haswell_crtc_off(struct drm_crtc *crtc)
3827{
3828 intel_ddi_put_crtc_pll(crtc);
3829}
3830
Daniel Vetter02e792f2009-09-15 22:57:34 +02003831static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3832{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003833 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003834 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003835 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003836
Chris Wilson23f09ce2010-08-12 13:53:37 +01003837 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003838 dev_priv->mm.interruptible = false;
3839 (void) intel_overlay_switch_off(intel_crtc->overlay);
3840 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003841 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003842 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003843
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003844 /* Let userspace switch the overlay on again. In most cases userspace
3845 * has to recompute where to put it anyway.
3846 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003847}
3848
Egbert Eich61bc95c2013-03-04 09:24:38 -05003849/**
3850 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3851 * cursor plane briefly if not already running after enabling the display
3852 * plane.
3853 * This workaround avoids occasional blank screens when self refresh is
3854 * enabled.
3855 */
3856static void
3857g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3858{
3859 u32 cntl = I915_READ(CURCNTR(pipe));
3860
3861 if ((cntl & CURSOR_MODE) == 0) {
3862 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3863
3864 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3865 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3866 intel_wait_for_vblank(dev_priv->dev, pipe);
3867 I915_WRITE(CURCNTR(pipe), cntl);
3868 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3869 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3870 }
3871}
3872
Jesse Barnes2dd24552013-04-25 12:55:01 -07003873static void i9xx_pfit_enable(struct intel_crtc *crtc)
3874{
3875 struct drm_device *dev = crtc->base.dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc_config *pipe_config = &crtc->config;
3878
Daniel Vetter328d8e82013-05-08 10:36:31 +02003879 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07003880 return;
3881
Daniel Vetterc0b03412013-05-28 12:05:54 +02003882 /*
3883 * The panel fitter should only be adjusted whilst the pipe is disabled,
3884 * according to register description and PRM.
3885 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07003886 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3887 assert_pipe_disabled(dev_priv, crtc->pipe);
3888
Jesse Barnesb074cec2013-04-25 12:55:02 -07003889 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3890 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02003891
3892 /* Border color in case we don't scale up to the full screen. Black by
3893 * default, change to something else for debugging. */
3894 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07003895}
3896
Jesse Barnes586f49d2013-11-04 16:06:59 -08003897int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08003898{
Jesse Barnes586f49d2013-11-04 16:06:59 -08003899 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08003900
Jesse Barnes586f49d2013-11-04 16:06:59 -08003901 /* Obtain SKU information */
3902 mutex_lock(&dev_priv->dpio_lock);
3903 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3904 CCK_FUSE_HPLL_FREQ_MASK;
3905 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08003906
Jesse Barnes586f49d2013-11-04 16:06:59 -08003907 return vco_freq[hpll_freq];
Jesse Barnes30a970c2013-11-04 13:48:12 -08003908}
3909
3910/* Adjust CDclk dividers to allow high res or save power if possible */
3911static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3912{
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 u32 val, cmd;
3915
3916 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3917 cmd = 2;
3918 else if (cdclk == 266)
3919 cmd = 1;
3920 else
3921 cmd = 0;
3922
3923 mutex_lock(&dev_priv->rps.hw_lock);
3924 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3925 val &= ~DSPFREQGUAR_MASK;
3926 val |= (cmd << DSPFREQGUAR_SHIFT);
3927 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3928 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3929 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3930 50)) {
3931 DRM_ERROR("timed out waiting for CDclk change\n");
3932 }
3933 mutex_unlock(&dev_priv->rps.hw_lock);
3934
3935 if (cdclk == 400) {
3936 u32 divider, vco;
3937
3938 vco = valleyview_get_vco(dev_priv);
3939 divider = ((vco << 1) / cdclk) - 1;
3940
3941 mutex_lock(&dev_priv->dpio_lock);
3942 /* adjust cdclk divider */
3943 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3944 val &= ~0xf;
3945 val |= divider;
3946 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3947 mutex_unlock(&dev_priv->dpio_lock);
3948 }
3949
3950 mutex_lock(&dev_priv->dpio_lock);
3951 /* adjust self-refresh exit latency value */
3952 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3953 val &= ~0x7f;
3954
3955 /*
3956 * For high bandwidth configs, we set a higher latency in the bunit
3957 * so that the core display fetch happens in time to avoid underruns.
3958 */
3959 if (cdclk == 400)
3960 val |= 4500 / 250; /* 4.5 usec */
3961 else
3962 val |= 3000 / 250; /* 3.0 usec */
3963 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
3964 mutex_unlock(&dev_priv->dpio_lock);
3965
3966 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
3967 intel_i2c_reset(dev);
3968}
3969
3970static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
3971{
3972 int cur_cdclk, vco;
3973 int divider;
3974
3975 vco = valleyview_get_vco(dev_priv);
3976
3977 mutex_lock(&dev_priv->dpio_lock);
3978 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3979 mutex_unlock(&dev_priv->dpio_lock);
3980
3981 divider &= 0xf;
3982
3983 cur_cdclk = (vco << 1) / (divider + 1);
3984
3985 return cur_cdclk;
3986}
3987
3988static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
3989 int max_pixclk)
3990{
3991 int cur_cdclk;
3992
3993 cur_cdclk = valleyview_cur_cdclk(dev_priv);
3994
3995 /*
3996 * Really only a few cases to deal with, as only 4 CDclks are supported:
3997 * 200MHz
3998 * 267MHz
3999 * 320MHz
4000 * 400MHz
4001 * So we check to see whether we're above 90% of the lower bin and
4002 * adjust if needed.
4003 */
4004 if (max_pixclk > 288000) {
4005 return 400;
4006 } else if (max_pixclk > 240000) {
4007 return 320;
4008 } else
4009 return 266;
4010 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4011}
4012
4013static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4014 unsigned modeset_pipes,
4015 struct intel_crtc_config *pipe_config)
4016{
4017 struct drm_device *dev = dev_priv->dev;
4018 struct intel_crtc *intel_crtc;
4019 int max_pixclk = 0;
4020
4021 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4022 base.head) {
4023 if (modeset_pipes & (1 << intel_crtc->pipe))
4024 max_pixclk = max(max_pixclk,
4025 pipe_config->adjusted_mode.crtc_clock);
4026 else if (intel_crtc->base.enabled)
4027 max_pixclk = max(max_pixclk,
4028 intel_crtc->config.adjusted_mode.crtc_clock);
4029 }
4030
4031 return max_pixclk;
4032}
4033
4034static void valleyview_modeset_global_pipes(struct drm_device *dev,
4035 unsigned *prepare_pipes,
4036 unsigned modeset_pipes,
4037 struct intel_crtc_config *pipe_config)
4038{
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 struct intel_crtc *intel_crtc;
4041 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4042 pipe_config);
4043 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4044
4045 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4046 return;
4047
4048 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4049 base.head)
4050 if (intel_crtc->base.enabled)
4051 *prepare_pipes |= (1 << intel_crtc->pipe);
4052}
4053
4054static void valleyview_modeset_global_resources(struct drm_device *dev)
4055{
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4058 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4059 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4060
4061 if (req_cdclk != cur_cdclk)
4062 valleyview_set_cdclk(dev, req_cdclk);
4063}
4064
Jesse Barnes89b667f2013-04-18 14:51:36 -07004065static void valleyview_crtc_enable(struct drm_crtc *crtc)
4066{
4067 struct drm_device *dev = crtc->dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4070 struct intel_encoder *encoder;
4071 int pipe = intel_crtc->pipe;
4072 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004073 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004074
4075 WARN_ON(!crtc->enabled);
4076
4077 if (intel_crtc->active)
4078 return;
4079
4080 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004081
Jesse Barnes89b667f2013-04-18 14:51:36 -07004082 for_each_encoder_on_crtc(dev, crtc, encoder)
4083 if (encoder->pre_pll_enable)
4084 encoder->pre_pll_enable(encoder);
4085
Jani Nikula23538ef2013-08-27 15:12:22 +03004086 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4087
Jani Nikulae9fd1c02013-08-27 15:12:23 +03004088 if (!is_dsi)
4089 vlv_enable_pll(intel_crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004090
4091 for_each_encoder_on_crtc(dev, crtc, encoder)
4092 if (encoder->pre_enable)
4093 encoder->pre_enable(encoder);
4094
Jesse Barnes2dd24552013-04-25 12:55:01 -07004095 i9xx_pfit_enable(intel_crtc);
4096
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004097 intel_crtc_load_lut(crtc);
4098
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004099 intel_update_watermarks(crtc);
Jani Nikula23538ef2013-08-27 15:12:22 +03004100 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004101 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004102 intel_enable_planes(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004103 intel_crtc_update_cursor(crtc, true);
4104
Ville Syrjäläf440eb12013-06-04 13:49:01 +03004105 intel_update_fbc(dev);
Jani Nikula50049452013-07-30 12:20:32 +03004106
4107 for_each_encoder_on_crtc(dev, crtc, encoder)
4108 encoder->enable(encoder);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004109}
4110
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004111static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004112{
4113 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08004114 struct drm_i915_private *dev_priv = dev->dev_private;
4115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004116 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004117 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004118 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08004119
Daniel Vetter08a48462012-07-02 11:43:47 +02004120 WARN_ON(!crtc->enabled);
4121
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004122 if (intel_crtc->active)
4123 return;
4124
4125 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004126
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004127 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004128 if (encoder->pre_enable)
4129 encoder->pre_enable(encoder);
4130
Daniel Vetterf6736a12013-06-05 13:34:30 +02004131 i9xx_enable_pll(intel_crtc);
4132
Jesse Barnes2dd24552013-04-25 12:55:01 -07004133 i9xx_pfit_enable(intel_crtc);
4134
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004135 intel_crtc_load_lut(crtc);
4136
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004137 intel_update_watermarks(crtc);
Jani Nikula23538ef2013-08-27 15:12:22 +03004138 intel_enable_pipe(dev_priv, pipe, false, false);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004139 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004140 intel_enable_planes(crtc);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03004141 /* The fixup needs to happen before cursor is enabled */
Egbert Eich61bc95c2013-03-04 09:24:38 -05004142 if (IS_G4X(dev))
4143 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03004144 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004145
4146 /* Give the overlay scaler a chance to enable if it's on this pipe */
4147 intel_crtc_dpms_overlay(intel_crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004148
Ville Syrjäläf440eb12013-06-04 13:49:01 +03004149 intel_update_fbc(dev);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004150
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004151 for_each_encoder_on_crtc(dev, crtc, encoder)
4152 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004153}
4154
Daniel Vetter87476d62013-04-11 16:29:06 +02004155static void i9xx_pfit_disable(struct intel_crtc *crtc)
4156{
4157 struct drm_device *dev = crtc->base.dev;
4158 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004159
4160 if (!crtc->config.gmch_pfit.control)
4161 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004162
4163 assert_pipe_disabled(dev_priv, crtc->pipe);
4164
Daniel Vetter328d8e82013-05-08 10:36:31 +02004165 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4166 I915_READ(PFIT_CONTROL));
4167 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004168}
4169
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004170static void i9xx_crtc_disable(struct drm_crtc *crtc)
4171{
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004175 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004176 int pipe = intel_crtc->pipe;
4177 int plane = intel_crtc->plane;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004178
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004179 if (!intel_crtc->active)
4180 return;
4181
Daniel Vetterea9d7582012-07-10 10:42:52 +02004182 for_each_encoder_on_crtc(dev, crtc, encoder)
4183 encoder->disable(encoder);
4184
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004185 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01004186 intel_crtc_wait_for_pending_flips(crtc);
4187 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004188
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07004189 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01004190 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004191
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03004192 intel_crtc_dpms_overlay(intel_crtc, false);
4193 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004194 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004195 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03004196
Jesse Barnesb24e7172011-01-04 15:09:30 -08004197 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004198
Daniel Vetter87476d62013-04-11 16:29:06 +02004199 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004200
Jesse Barnes89b667f2013-04-18 14:51:36 -07004201 for_each_encoder_on_crtc(dev, crtc, encoder)
4202 if (encoder->post_disable)
4203 encoder->post_disable(encoder);
4204
Jesse Barnesf6071162013-10-01 10:41:38 -07004205 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4206 vlv_disable_pll(dev_priv, pipe);
4207 else if (!IS_VALLEYVIEW(dev))
Jani Nikulae9fd1c02013-08-27 15:12:23 +03004208 i9xx_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004209
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004210 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004211 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004212
Chris Wilson6b383a72010-09-13 13:54:26 +01004213 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004214}
4215
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004216static void i9xx_crtc_off(struct drm_crtc *crtc)
4217{
4218}
4219
Daniel Vetter976f8a22012-07-08 22:34:21 +02004220static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4221 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004222{
4223 struct drm_device *dev = crtc->dev;
4224 struct drm_i915_master_private *master_priv;
4225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004227
4228 if (!dev->primary->master)
4229 return;
4230
4231 master_priv = dev->primary->master->driver_priv;
4232 if (!master_priv->sarea_priv)
4233 return;
4234
Jesse Barnes79e53942008-11-07 14:24:08 -08004235 switch (pipe) {
4236 case 0:
4237 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4238 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4239 break;
4240 case 1:
4241 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4242 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4243 break;
4244 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004245 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004246 break;
4247 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004248}
4249
Daniel Vetter976f8a22012-07-08 22:34:21 +02004250/**
4251 * Sets the power management mode of the pipe and plane.
4252 */
4253void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004254{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004255 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004256 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004257 struct intel_encoder *intel_encoder;
4258 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004259
Daniel Vetter976f8a22012-07-08 22:34:21 +02004260 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4261 enable |= intel_encoder->connectors_active;
4262
4263 if (enable)
4264 dev_priv->display.crtc_enable(crtc);
4265 else
4266 dev_priv->display.crtc_disable(crtc);
4267
4268 intel_crtc_update_sarea(crtc, enable);
4269}
4270
Daniel Vetter976f8a22012-07-08 22:34:21 +02004271static void intel_crtc_disable(struct drm_crtc *crtc)
4272{
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_connector *connector;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08004276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004277
4278 /* crtc should still be enabled when we disable it. */
4279 WARN_ON(!crtc->enabled);
4280
4281 dev_priv->display.crtc_disable(crtc);
Paulo Zanonic77bf562013-05-03 12:15:40 -03004282 intel_crtc->eld_vld = false;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004283 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004284 dev_priv->display.off(crtc);
4285
Chris Wilson931872f2012-01-16 23:01:13 +00004286 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03004287 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Chris Wilson931872f2012-01-16 23:01:13 +00004288 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004289
4290 if (crtc->fb) {
4291 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01004292 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004293 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004294 crtc->fb = NULL;
4295 }
4296
4297 /* Update computed state. */
4298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4299 if (!connector->encoder || !connector->encoder->crtc)
4300 continue;
4301
4302 if (connector->encoder->crtc != crtc)
4303 continue;
4304
4305 connector->dpms = DRM_MODE_DPMS_OFF;
4306 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004307 }
4308}
4309
Chris Wilsonea5b2132010-08-04 13:50:23 +01004310void intel_encoder_destroy(struct drm_encoder *encoder)
4311{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004312 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004313
Chris Wilsonea5b2132010-08-04 13:50:23 +01004314 drm_encoder_cleanup(encoder);
4315 kfree(intel_encoder);
4316}
4317
Damien Lespiau92373292013-08-08 22:28:57 +01004318/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004319 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4320 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004321static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004322{
4323 if (mode == DRM_MODE_DPMS_ON) {
4324 encoder->connectors_active = true;
4325
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004326 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004327 } else {
4328 encoder->connectors_active = false;
4329
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004330 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004331 }
4332}
4333
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004334/* Cross check the actual hw state with our own modeset state tracking (and it's
4335 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004336static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004337{
4338 if (connector->get_hw_state(connector)) {
4339 struct intel_encoder *encoder = connector->encoder;
4340 struct drm_crtc *crtc;
4341 bool encoder_enabled;
4342 enum pipe pipe;
4343
4344 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4345 connector->base.base.id,
4346 drm_get_connector_name(&connector->base));
4347
4348 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4349 "wrong connector dpms state\n");
4350 WARN(connector->base.encoder != &encoder->base,
4351 "active connector not linked to encoder\n");
4352 WARN(!encoder->connectors_active,
4353 "encoder->connectors_active not set\n");
4354
4355 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4356 WARN(!encoder_enabled, "encoder not enabled\n");
4357 if (WARN_ON(!encoder->base.crtc))
4358 return;
4359
4360 crtc = encoder->base.crtc;
4361
4362 WARN(!crtc->enabled, "crtc not enabled\n");
4363 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4364 WARN(pipe != to_intel_crtc(crtc)->pipe,
4365 "encoder active on the wrong pipe\n");
4366 }
4367}
4368
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004369/* Even simpler default implementation, if there's really no special case to
4370 * consider. */
4371void intel_connector_dpms(struct drm_connector *connector, int mode)
4372{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004373 /* All the simple cases only support two dpms states. */
4374 if (mode != DRM_MODE_DPMS_ON)
4375 mode = DRM_MODE_DPMS_OFF;
4376
4377 if (mode == connector->dpms)
4378 return;
4379
4380 connector->dpms = mode;
4381
4382 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01004383 if (connector->encoder)
4384 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004385
Daniel Vetterb9805142012-08-31 17:37:33 +02004386 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004387}
4388
Daniel Vetterf0947c32012-07-02 13:10:34 +02004389/* Simple connector->get_hw_state implementation for encoders that support only
4390 * one connector and no cloning and hence the encoder state determines the state
4391 * of the connector. */
4392bool intel_connector_get_hw_state(struct intel_connector *connector)
4393{
Daniel Vetter24929352012-07-02 20:28:59 +02004394 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02004395 struct intel_encoder *encoder = connector->encoder;
4396
4397 return encoder->get_hw_state(encoder, &pipe);
4398}
4399
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004400static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4401 struct intel_crtc_config *pipe_config)
4402{
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 struct intel_crtc *pipe_B_crtc =
4405 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4406
4407 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4408 pipe_name(pipe), pipe_config->fdi_lanes);
4409 if (pipe_config->fdi_lanes > 4) {
4410 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4411 pipe_name(pipe), pipe_config->fdi_lanes);
4412 return false;
4413 }
4414
4415 if (IS_HASWELL(dev)) {
4416 if (pipe_config->fdi_lanes > 2) {
4417 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4418 pipe_config->fdi_lanes);
4419 return false;
4420 } else {
4421 return true;
4422 }
4423 }
4424
4425 if (INTEL_INFO(dev)->num_pipes == 2)
4426 return true;
4427
4428 /* Ivybridge 3 pipe is really complicated */
4429 switch (pipe) {
4430 case PIPE_A:
4431 return true;
4432 case PIPE_B:
4433 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4434 pipe_config->fdi_lanes > 2) {
4435 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4436 pipe_name(pipe), pipe_config->fdi_lanes);
4437 return false;
4438 }
4439 return true;
4440 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01004441 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004442 pipe_B_crtc->config.fdi_lanes <= 2) {
4443 if (pipe_config->fdi_lanes > 2) {
4444 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4445 pipe_name(pipe), pipe_config->fdi_lanes);
4446 return false;
4447 }
4448 } else {
4449 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4450 return false;
4451 }
4452 return true;
4453 default:
4454 BUG();
4455 }
4456}
4457
Daniel Vettere29c22c2013-02-21 00:00:16 +01004458#define RETRY 1
4459static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4460 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02004461{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004462 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004463 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02004464 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01004465 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004466
Daniel Vettere29c22c2013-02-21 00:00:16 +01004467retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02004468 /* FDI is a binary signal running at ~2.7GHz, encoding
4469 * each output octet as 10 bits. The actual frequency
4470 * is stored as a divider into a 100MHz clock, and the
4471 * mode pixel clock is stored in units of 1KHz.
4472 * Hence the bw of each lane in terms of the mode signal
4473 * is:
4474 */
4475 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4476
Damien Lespiau241bfc32013-09-25 16:45:37 +01004477 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004478
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004479 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004480 pipe_config->pipe_bpp);
4481
4482 pipe_config->fdi_lanes = lane;
4483
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004484 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004485 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004486
Daniel Vettere29c22c2013-02-21 00:00:16 +01004487 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4488 intel_crtc->pipe, pipe_config);
4489 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4490 pipe_config->pipe_bpp -= 2*3;
4491 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4492 pipe_config->pipe_bpp);
4493 needs_recompute = true;
4494 pipe_config->bw_constrained = true;
4495
4496 goto retry;
4497 }
4498
4499 if (needs_recompute)
4500 return RETRY;
4501
4502 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004503}
4504
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004505static void hsw_compute_ips_config(struct intel_crtc *crtc,
4506 struct intel_crtc_config *pipe_config)
4507{
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03004508 pipe_config->ips_enabled = i915_enable_ips &&
4509 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07004510 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004511}
4512
Daniel Vettera43f6e02013-06-07 23:10:32 +02004513static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01004514 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08004515{
Daniel Vettera43f6e02013-06-07 23:10:32 +02004516 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004517 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01004518
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004519 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004520 if (INTEL_INFO(dev)->gen < 4) {
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 int clock_limit =
4523 dev_priv->display.get_display_clock_speed(dev);
4524
4525 /*
4526 * Enable pixel doubling when the dot clock
4527 * is > 90% of the (display) core speed.
4528 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03004529 * GDG double wide on either pipe,
4530 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004531 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03004532 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01004533 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004534 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004535 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004536 }
4537
Damien Lespiau241bfc32013-09-25 16:45:37 +01004538 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004539 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004540 }
Chris Wilson89749352010-09-12 18:25:19 +01004541
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03004542 /*
4543 * Pipe horizontal size must be even in:
4544 * - DVO ganged mode
4545 * - LVDS dual channel mode
4546 * - Double wide pipe
4547 */
4548 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4549 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4550 pipe_config->pipe_src_w &= ~1;
4551
Damien Lespiau8693a822013-05-03 18:48:11 +01004552 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4553 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03004554 */
4555 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4556 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004557 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03004558
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004559 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004560 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004561 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004562 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4563 * for lvds. */
4564 pipe_config->pipe_bpp = 8*3;
4565 }
4566
Damien Lespiauf5adf942013-06-24 18:29:34 +01004567 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02004568 hsw_compute_ips_config(crtc, pipe_config);
4569
4570 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4571 * clock survives for now. */
4572 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4573 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004574
Daniel Vetter877d48d2013-04-19 11:24:43 +02004575 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02004576 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02004577
Daniel Vettere29c22c2013-02-21 00:00:16 +01004578 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004579}
4580
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07004581static int valleyview_get_display_clock_speed(struct drm_device *dev)
4582{
4583 return 400000; /* FIXME */
4584}
4585
Jesse Barnese70236a2009-09-21 10:42:27 -07004586static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08004587{
Jesse Barnese70236a2009-09-21 10:42:27 -07004588 return 400000;
4589}
Jesse Barnes79e53942008-11-07 14:24:08 -08004590
Jesse Barnese70236a2009-09-21 10:42:27 -07004591static int i915_get_display_clock_speed(struct drm_device *dev)
4592{
4593 return 333000;
4594}
Jesse Barnes79e53942008-11-07 14:24:08 -08004595
Jesse Barnese70236a2009-09-21 10:42:27 -07004596static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4597{
4598 return 200000;
4599}
Jesse Barnes79e53942008-11-07 14:24:08 -08004600
Daniel Vetter257a7ff2013-07-26 08:35:42 +02004601static int pnv_get_display_clock_speed(struct drm_device *dev)
4602{
4603 u16 gcfgc = 0;
4604
4605 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4606
4607 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4608 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4609 return 267000;
4610 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4611 return 333000;
4612 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4613 return 444000;
4614 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4615 return 200000;
4616 default:
4617 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4618 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4619 return 133000;
4620 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4621 return 167000;
4622 }
4623}
4624
Jesse Barnese70236a2009-09-21 10:42:27 -07004625static int i915gm_get_display_clock_speed(struct drm_device *dev)
4626{
4627 u16 gcfgc = 0;
4628
4629 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4630
4631 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08004632 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07004633 else {
4634 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4635 case GC_DISPLAY_CLOCK_333_MHZ:
4636 return 333000;
4637 default:
4638 case GC_DISPLAY_CLOCK_190_200_MHZ:
4639 return 190000;
4640 }
4641 }
4642}
Jesse Barnes79e53942008-11-07 14:24:08 -08004643
Jesse Barnese70236a2009-09-21 10:42:27 -07004644static int i865_get_display_clock_speed(struct drm_device *dev)
4645{
4646 return 266000;
4647}
4648
4649static int i855_get_display_clock_speed(struct drm_device *dev)
4650{
4651 u16 hpllcc = 0;
4652 /* Assume that the hardware is in the high speed state. This
4653 * should be the default.
4654 */
4655 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4656 case GC_CLOCK_133_200:
4657 case GC_CLOCK_100_200:
4658 return 200000;
4659 case GC_CLOCK_166_250:
4660 return 250000;
4661 case GC_CLOCK_100_133:
4662 return 133000;
4663 }
4664
4665 /* Shouldn't happen */
4666 return 0;
4667}
4668
4669static int i830_get_display_clock_speed(struct drm_device *dev)
4670{
4671 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004672}
4673
Zhenyu Wang2c072452009-06-05 15:38:42 +08004674static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004675intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004676{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004677 while (*num > DATA_LINK_M_N_MASK ||
4678 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004679 *num >>= 1;
4680 *den >>= 1;
4681 }
4682}
4683
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004684static void compute_m_n(unsigned int m, unsigned int n,
4685 uint32_t *ret_m, uint32_t *ret_n)
4686{
4687 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4688 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4689 intel_reduce_m_n_ratio(ret_m, ret_n);
4690}
4691
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004692void
4693intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4694 int pixel_clock, int link_clock,
4695 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004696{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004697 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004698
4699 compute_m_n(bits_per_pixel * pixel_clock,
4700 link_clock * nlanes * 8,
4701 &m_n->gmch_m, &m_n->gmch_n);
4702
4703 compute_m_n(pixel_clock, link_clock,
4704 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004705}
4706
Chris Wilsona7615032011-01-12 17:04:08 +00004707static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4708{
Keith Packard72bbe582011-09-26 16:09:45 -07004709 if (i915_panel_use_ssc >= 0)
4710 return i915_panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004711 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004712 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004713}
4714
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004715static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4716{
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 int refclk;
4720
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004721 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02004722 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004723 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004724 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004725 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004726 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4727 refclk / 1000);
4728 } else if (!IS_GEN2(dev)) {
4729 refclk = 96000;
4730 } else {
4731 refclk = 48000;
4732 }
4733
4734 return refclk;
4735}
4736
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004737static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004738{
Daniel Vetter7df00d72013-05-21 21:54:55 +02004739 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004740}
Daniel Vetterf47709a2013-03-28 10:42:02 +01004741
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004742static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4743{
4744 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004745}
4746
Daniel Vetterf47709a2013-03-28 10:42:02 +01004747static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08004748 intel_clock_t *reduced_clock)
4749{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004750 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004751 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004752 int pipe = crtc->pipe;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004753 u32 fp, fp2 = 0;
4754
4755 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004756 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004757 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004758 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004759 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004760 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004761 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004762 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004763 }
4764
4765 I915_WRITE(FP0(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004766 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004767
Daniel Vetterf47709a2013-03-28 10:42:02 +01004768 crtc->lowfreq_avail = false;
4769 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jesse Barnesa7516a02011-12-15 12:30:37 -08004770 reduced_clock && i915_powersave) {
4771 I915_WRITE(FP1(pipe), fp2);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004772 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004773 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004774 } else {
4775 I915_WRITE(FP1(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004776 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004777 }
4778}
4779
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004780static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4781 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07004782{
4783 u32 reg_val;
4784
4785 /*
4786 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4787 * and set it to a reasonable value instead.
4788 */
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004789 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004790 reg_val &= 0xffffff00;
4791 reg_val |= 0x00000030;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004792 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004793
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004794 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004795 reg_val &= 0x8cffffff;
4796 reg_val = 0x8c000000;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004797 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004798
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004799 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004800 reg_val &= 0xffffff00;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004801 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004802
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004803 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004804 reg_val &= 0x00ffffff;
4805 reg_val |= 0xb0000000;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004806 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004807}
4808
Daniel Vetterb5518422013-05-03 11:49:48 +02004809static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4810 struct intel_link_m_n *m_n)
4811{
4812 struct drm_device *dev = crtc->base.dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814 int pipe = crtc->pipe;
4815
Daniel Vettere3b95f12013-05-03 11:49:49 +02004816 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4817 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4818 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4819 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004820}
4821
4822static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4823 struct intel_link_m_n *m_n)
4824{
4825 struct drm_device *dev = crtc->base.dev;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 int pipe = crtc->pipe;
4828 enum transcoder transcoder = crtc->config.cpu_transcoder;
4829
4830 if (INTEL_INFO(dev)->gen >= 5) {
4831 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4832 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4833 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4834 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4835 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02004836 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4837 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4838 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4839 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004840 }
4841}
4842
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004843static void intel_dp_set_m_n(struct intel_crtc *crtc)
4844{
4845 if (crtc->config.has_pch_encoder)
4846 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4847 else
4848 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4849}
4850
Daniel Vetterf47709a2013-03-28 10:42:02 +01004851static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004852{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004853 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004854 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004855 int pipe = crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004856 u32 dpll, mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004857 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetter198a037f2013-04-19 11:14:37 +02004858 u32 coreclk, reg_val, dpll_md;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004859
Daniel Vetter09153002012-12-12 14:06:44 +01004860 mutex_lock(&dev_priv->dpio_lock);
4861
Daniel Vetterf47709a2013-03-28 10:42:02 +01004862 bestn = crtc->config.dpll.n;
4863 bestm1 = crtc->config.dpll.m1;
4864 bestm2 = crtc->config.dpll.m2;
4865 bestp1 = crtc->config.dpll.p1;
4866 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004867
Jesse Barnes89b667f2013-04-18 14:51:36 -07004868 /* See eDP HDMI DPIO driver vbios notes doc */
4869
4870 /* PLL B needs special handling */
4871 if (pipe)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004872 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004873
4874 /* Set up Tx target for periodic Rcomp update */
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004875 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004876
4877 /* Disable target IRef on PLL */
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004878 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004879 reg_val &= 0x00ffffff;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004880 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004881
4882 /* Disable fast lock */
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004883 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004884
4885 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004886 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4887 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4888 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004889 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07004890
4891 /*
4892 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4893 * but we don't support that).
4894 * Note: don't use the DAC post divider as it seems unstable.
4895 */
4896 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004897 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004898
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004899 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004900 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004901
Jesse Barnes89b667f2013-04-18 14:51:36 -07004902 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02004903 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03004904 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07004905 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004906 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03004907 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004908 else
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004909 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004910 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004911
Jesse Barnes89b667f2013-04-18 14:51:36 -07004912 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4913 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4914 /* Use SSC source */
4915 if (!pipe)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004916 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004917 0x0df40000);
4918 else
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004919 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004920 0x0df70000);
4921 } else { /* HDMI or VGA */
4922 /* Use bend source */
4923 if (!pipe)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004924 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004925 0x0df70000);
4926 else
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004927 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004928 0x0df40000);
4929 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004930
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004931 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004932 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4933 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4934 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4935 coreclk |= 0x01000000;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004936 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004937
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004938 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004939
Jesse Barnes89b667f2013-04-18 14:51:36 -07004940 /* Enable DPIO clock input */
4941 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4942 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07004943 /* We should never disable this, set it here for state tracking */
4944 if (pipe == PIPE_B)
Jesse Barnes89b667f2013-04-18 14:51:36 -07004945 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004946 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004947 crtc->config.dpll_hw_state.dpll = dpll;
4948
Daniel Vetteref1b4602013-06-01 17:17:04 +02004949 dpll_md = (crtc->config.pixel_multiplier - 1)
4950 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004951 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4952
Daniel Vetterf47709a2013-03-28 10:42:02 +01004953 if (crtc->config.has_dp_encoder)
4954 intel_dp_set_m_n(crtc);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304955
Daniel Vetter09153002012-12-12 14:06:44 +01004956 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004957}
4958
Daniel Vetterf47709a2013-03-28 10:42:02 +01004959static void i9xx_update_pll(struct intel_crtc *crtc,
4960 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004961 int num_connectors)
4962{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004963 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004964 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004965 u32 dpll;
4966 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004967 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004968
Daniel Vetterf47709a2013-03-28 10:42:02 +01004969 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304970
Daniel Vetterf47709a2013-03-28 10:42:02 +01004971 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4972 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004973
4974 dpll = DPLL_VGA_MODE_DIS;
4975
Daniel Vetterf47709a2013-03-28 10:42:02 +01004976 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004977 dpll |= DPLLB_MODE_LVDS;
4978 else
4979 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01004980
Daniel Vetteref1b4602013-06-01 17:17:04 +02004981 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02004982 dpll |= (crtc->config.pixel_multiplier - 1)
4983 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004984 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02004985
4986 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02004987 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02004988
Daniel Vetterf47709a2013-03-28 10:42:02 +01004989 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02004990 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004991
4992 /* compute bitmask from p1 value */
4993 if (IS_PINEVIEW(dev))
4994 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4995 else {
4996 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4997 if (IS_G4X(dev) && reduced_clock)
4998 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4999 }
5000 switch (clock->p2) {
5001 case 5:
5002 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5003 break;
5004 case 7:
5005 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5006 break;
5007 case 10:
5008 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5009 break;
5010 case 14:
5011 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5012 break;
5013 }
5014 if (INTEL_INFO(dev)->gen >= 4)
5015 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5016
Daniel Vetter09ede542013-04-30 14:01:45 +02005017 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005018 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005019 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005020 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5021 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5022 else
5023 dpll |= PLL_REF_INPUT_DREFCLK;
5024
5025 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005026 crtc->config.dpll_hw_state.dpll = dpll;
5027
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005028 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005029 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5030 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005031 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005032 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005033
5034 if (crtc->config.has_dp_encoder)
5035 intel_dp_set_m_n(crtc);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005036}
5037
Daniel Vetterf47709a2013-03-28 10:42:02 +01005038static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005039 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005040 int num_connectors)
5041{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005042 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005043 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005044 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005045 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005046
Daniel Vetterf47709a2013-03-28 10:42:02 +01005047 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305048
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005049 dpll = DPLL_VGA_MODE_DIS;
5050
Daniel Vetterf47709a2013-03-28 10:42:02 +01005051 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005052 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5053 } else {
5054 if (clock->p1 == 2)
5055 dpll |= PLL_P1_DIVIDE_BY_TWO;
5056 else
5057 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5058 if (clock->p2 == 4)
5059 dpll |= PLL_P2_DIVIDE_BY_4;
5060 }
5061
Daniel Vetter4a33e482013-07-06 12:52:05 +02005062 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5063 dpll |= DPLL_DVO_2X_MODE;
5064
Daniel Vetterf47709a2013-03-28 10:42:02 +01005065 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005066 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5067 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5068 else
5069 dpll |= PLL_REF_INPUT_DREFCLK;
5070
5071 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005072 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005073}
5074
Daniel Vetter8a654f32013-06-01 17:16:22 +02005075static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005076{
5077 struct drm_device *dev = intel_crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005080 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005081 struct drm_display_mode *adjusted_mode =
5082 &intel_crtc->config.adjusted_mode;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005083 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5084
5085 /* We need to be careful not to changed the adjusted mode, for otherwise
5086 * the hw state checker will get angry at the mismatch. */
5087 crtc_vtotal = adjusted_mode->crtc_vtotal;
5088 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005089
5090 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5091 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005092 crtc_vtotal -= 1;
5093 crtc_vblank_end -= 1;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005094 vsyncshift = adjusted_mode->crtc_hsync_start
5095 - adjusted_mode->crtc_htotal / 2;
5096 } else {
5097 vsyncshift = 0;
5098 }
5099
5100 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005101 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005102
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005103 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005104 (adjusted_mode->crtc_hdisplay - 1) |
5105 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005106 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005107 (adjusted_mode->crtc_hblank_start - 1) |
5108 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005109 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005110 (adjusted_mode->crtc_hsync_start - 1) |
5111 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5112
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005113 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005114 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005115 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005116 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005117 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005118 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005119 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005120 (adjusted_mode->crtc_vsync_start - 1) |
5121 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5122
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005123 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5124 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5125 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5126 * bits. */
5127 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5128 (pipe == PIPE_B || pipe == PIPE_C))
5129 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5130
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005131 /* pipesrc controls the size that is scaled from, which should
5132 * always be the user's requested size.
5133 */
5134 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005135 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5136 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005137}
5138
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005139static void intel_get_pipe_timings(struct intel_crtc *crtc,
5140 struct intel_crtc_config *pipe_config)
5141{
5142 struct drm_device *dev = crtc->base.dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5145 uint32_t tmp;
5146
5147 tmp = I915_READ(HTOTAL(cpu_transcoder));
5148 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5149 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5150 tmp = I915_READ(HBLANK(cpu_transcoder));
5151 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5152 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5153 tmp = I915_READ(HSYNC(cpu_transcoder));
5154 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5155 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5156
5157 tmp = I915_READ(VTOTAL(cpu_transcoder));
5158 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5159 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5160 tmp = I915_READ(VBLANK(cpu_transcoder));
5161 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5162 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5163 tmp = I915_READ(VSYNC(cpu_transcoder));
5164 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5165 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5166
5167 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5168 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5169 pipe_config->adjusted_mode.crtc_vtotal += 1;
5170 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5171 }
5172
5173 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005174 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5175 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5176
5177 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5178 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005179}
5180
Jesse Barnesbabea612013-06-26 18:57:38 +03005181static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5182 struct intel_crtc_config *pipe_config)
5183{
5184 struct drm_crtc *crtc = &intel_crtc->base;
5185
5186 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5187 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5188 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5189 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5190
5191 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5192 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5193 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5194 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5195
5196 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5197
Damien Lespiau241bfc32013-09-25 16:45:37 +01005198 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
Jesse Barnesbabea612013-06-26 18:57:38 +03005199 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5200}
5201
Daniel Vetter84b046f2013-02-19 18:48:54 +01005202static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5203{
5204 struct drm_device *dev = intel_crtc->base.dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 uint32_t pipeconf;
5207
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005208 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005209
Daniel Vetter67c72a12013-09-24 11:46:14 +02005210 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5211 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5212 pipeconf |= PIPECONF_ENABLE;
5213
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005214 if (intel_crtc->config.double_wide)
5215 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005216
Daniel Vetterff9ce462013-04-24 14:57:17 +02005217 /* only g4x and later have fancy bpc/dither controls */
5218 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005219 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5220 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5221 pipeconf |= PIPECONF_DITHER_EN |
5222 PIPECONF_DITHER_TYPE_SP;
5223
5224 switch (intel_crtc->config.pipe_bpp) {
5225 case 18:
5226 pipeconf |= PIPECONF_6BPC;
5227 break;
5228 case 24:
5229 pipeconf |= PIPECONF_8BPC;
5230 break;
5231 case 30:
5232 pipeconf |= PIPECONF_10BPC;
5233 break;
5234 default:
5235 /* Case prevented by intel_choose_pipe_bpp_dither. */
5236 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005237 }
5238 }
5239
5240 if (HAS_PIPE_CXSR(dev)) {
5241 if (intel_crtc->lowfreq_avail) {
5242 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5243 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5244 } else {
5245 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005246 }
5247 }
5248
Daniel Vetter84b046f2013-02-19 18:48:54 +01005249 if (!IS_GEN2(dev) &&
5250 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5251 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5252 else
5253 pipeconf |= PIPECONF_PROGRESSIVE;
5254
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005255 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5256 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03005257
Daniel Vetter84b046f2013-02-19 18:48:54 +01005258 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5259 POSTING_READ(PIPECONF(intel_crtc->pipe));
5260}
5261
Eric Anholtf564048e2011-03-30 13:01:02 -07005262static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005263 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005264 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005265{
5266 struct drm_device *dev = crtc->dev;
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5269 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07005270 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07005271 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005272 intel_clock_t clock, reduced_clock;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005273 u32 dspcntr;
Daniel Vettera16af7212013-04-30 14:01:44 +02005274 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005275 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01005276 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005277 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005278 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005279
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005280 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005281 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005282 case INTEL_OUTPUT_LVDS:
5283 is_lvds = true;
5284 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005285 case INTEL_OUTPUT_DSI:
5286 is_dsi = true;
5287 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005288 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005289
Eric Anholtc751ce42010-03-25 11:48:48 -07005290 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005291 }
5292
Jani Nikulaf2335332013-09-13 11:03:09 +03005293 if (is_dsi)
5294 goto skip_dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08005295
Jani Nikulaf2335332013-09-13 11:03:09 +03005296 if (!intel_crtc->config.clock_set) {
5297 refclk = i9xx_get_refclk(crtc, num_connectors);
5298
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005299 /*
5300 * Returns a set of divisors for the desired target clock with
5301 * the given refclk, or FALSE. The returned values represent
5302 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5303 * 2) / p1 / p2.
5304 */
5305 limit = intel_limit(crtc, refclk);
5306 ok = dev_priv->display.find_dpll(limit, crtc,
5307 intel_crtc->config.port_clock,
5308 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03005309 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005310 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5311 return -EINVAL;
5312 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005313
Jani Nikulaf2335332013-09-13 11:03:09 +03005314 if (is_lvds && dev_priv->lvds_downclock_avail) {
5315 /*
5316 * Ensure we match the reduced clock's P to the target
5317 * clock. If the clocks don't match, we can't switch
5318 * the display clock by using the FP0/FP1. In such case
5319 * we will disable the LVDS downclock feature.
5320 */
5321 has_reduced_clock =
5322 dev_priv->display.find_dpll(limit, crtc,
5323 dev_priv->lvds_downclock,
5324 refclk, &clock,
5325 &reduced_clock);
5326 }
5327 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01005328 intel_crtc->config.dpll.n = clock.n;
5329 intel_crtc->config.dpll.m1 = clock.m1;
5330 intel_crtc->config.dpll.m2 = clock.m2;
5331 intel_crtc->config.dpll.p1 = clock.p1;
5332 intel_crtc->config.dpll.p2 = clock.p2;
5333 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005334
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005335 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02005336 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305337 has_reduced_clock ? &reduced_clock : NULL,
5338 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005339 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03005340 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005341 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01005342 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005343 has_reduced_clock ? &reduced_clock : NULL,
Jesse Barnes89b667f2013-04-18 14:51:36 -07005344 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005345 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005346
Jani Nikulaf2335332013-09-13 11:03:09 +03005347skip_dpll:
Eric Anholtf564048e2011-03-30 13:01:02 -07005348 /* Set up the display plane register */
5349 dspcntr = DISPPLANE_GAMMA_ENABLE;
5350
Jesse Barnesda6ecc52013-03-08 10:46:00 -08005351 if (!IS_VALLEYVIEW(dev)) {
5352 if (pipe == 0)
5353 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5354 else
5355 dspcntr |= DISPPLANE_SEL_PIPE_B;
5356 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005357
Daniel Vetter8a654f32013-06-01 17:16:22 +02005358 intel_set_pipe_timings(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07005359
5360 /* pipesrc and dspsize control the size that is scaled from,
5361 * which should always be the user's requested size.
5362 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005363 I915_WRITE(DSPSIZE(plane),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005364 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5365 (intel_crtc->config.pipe_src_w - 1));
Eric Anholt929c77f2011-03-30 13:01:04 -07005366 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07005367
Daniel Vetter84b046f2013-02-19 18:48:54 +01005368 i9xx_set_pipeconf(intel_crtc);
5369
Eric Anholtf564048e2011-03-30 13:01:02 -07005370 I915_WRITE(DSPCNTR(plane), dspcntr);
5371 POSTING_READ(DSPCNTR(plane));
5372
Daniel Vetter94352cf2012-07-05 22:51:56 +02005373 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07005374
Eric Anholtf564048e2011-03-30 13:01:02 -07005375 return ret;
5376}
5377
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005378static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5379 struct intel_crtc_config *pipe_config)
5380{
5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383 uint32_t tmp;
5384
5385 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02005386 if (!(tmp & PFIT_ENABLE))
5387 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005388
Daniel Vetter06922822013-07-11 13:35:40 +02005389 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005390 if (INTEL_INFO(dev)->gen < 4) {
5391 if (crtc->pipe != PIPE_B)
5392 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005393 } else {
5394 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5395 return;
5396 }
5397
Daniel Vetter06922822013-07-11 13:35:40 +02005398 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005399 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5400 if (INTEL_INFO(dev)->gen < 5)
5401 pipe_config->gmch_pfit.lvds_border_bits =
5402 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5403}
5404
Jesse Barnesacbec812013-09-20 11:29:32 -07005405static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5406 struct intel_crtc_config *pipe_config)
5407{
5408 struct drm_device *dev = crtc->base.dev;
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410 int pipe = pipe_config->cpu_transcoder;
5411 intel_clock_t clock;
5412 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07005413 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07005414
5415 mutex_lock(&dev_priv->dpio_lock);
5416 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5417 mutex_unlock(&dev_priv->dpio_lock);
5418
5419 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5420 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5421 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5422 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5423 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5424
Ville Syrjäläf6466282013-10-14 14:50:31 +03005425 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07005426
Ville Syrjäläf6466282013-10-14 14:50:31 +03005427 /* clock.dot is the fast clock */
5428 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07005429}
5430
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005431static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5432 struct intel_crtc_config *pipe_config)
5433{
5434 struct drm_device *dev = crtc->base.dev;
5435 struct drm_i915_private *dev_priv = dev->dev_private;
5436 uint32_t tmp;
5437
Daniel Vettere143a212013-07-04 12:01:15 +02005438 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005439 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02005440
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005441 tmp = I915_READ(PIPECONF(crtc->pipe));
5442 if (!(tmp & PIPECONF_ENABLE))
5443 return false;
5444
Ville Syrjälä42571ae2013-09-06 23:29:00 +03005445 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5446 switch (tmp & PIPECONF_BPC_MASK) {
5447 case PIPECONF_6BPC:
5448 pipe_config->pipe_bpp = 18;
5449 break;
5450 case PIPECONF_8BPC:
5451 pipe_config->pipe_bpp = 24;
5452 break;
5453 case PIPECONF_10BPC:
5454 pipe_config->pipe_bpp = 30;
5455 break;
5456 default:
5457 break;
5458 }
5459 }
5460
Ville Syrjälä282740f2013-09-04 18:30:03 +03005461 if (INTEL_INFO(dev)->gen < 4)
5462 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5463
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005464 intel_get_pipe_timings(crtc, pipe_config);
5465
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005466 i9xx_get_pfit_config(crtc, pipe_config);
5467
Daniel Vetter6c49f242013-06-06 12:45:25 +02005468 if (INTEL_INFO(dev)->gen >= 4) {
5469 tmp = I915_READ(DPLL_MD(crtc->pipe));
5470 pipe_config->pixel_multiplier =
5471 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5472 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005473 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02005474 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5475 tmp = I915_READ(DPLL(crtc->pipe));
5476 pipe_config->pixel_multiplier =
5477 ((tmp & SDVO_MULTIPLIER_MASK)
5478 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5479 } else {
5480 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5481 * port and will be fixed up in the encoder->get_config
5482 * function. */
5483 pipe_config->pixel_multiplier = 1;
5484 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005485 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5486 if (!IS_VALLEYVIEW(dev)) {
5487 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5488 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03005489 } else {
5490 /* Mask out read-only status bits. */
5491 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5492 DPLL_PORTC_READY_MASK |
5493 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005494 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02005495
Jesse Barnesacbec812013-09-20 11:29:32 -07005496 if (IS_VALLEYVIEW(dev))
5497 vlv_crtc_clock_get(crtc, pipe_config);
5498 else
5499 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03005500
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005501 return true;
5502}
5503
Paulo Zanonidde86e22012-12-01 12:04:25 -02005504static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07005505{
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005508 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005509 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005510 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005511 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005512 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07005513 bool has_ck505 = false;
5514 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005515
5516 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07005517 list_for_each_entry(encoder, &mode_config->encoder_list,
5518 base.head) {
5519 switch (encoder->type) {
5520 case INTEL_OUTPUT_LVDS:
5521 has_panel = true;
5522 has_lvds = true;
5523 break;
5524 case INTEL_OUTPUT_EDP:
5525 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03005526 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07005527 has_cpu_edp = true;
5528 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005529 }
5530 }
5531
Keith Packard99eb6a02011-09-26 14:29:12 -07005532 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005533 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07005534 can_ssc = has_ck505;
5535 } else {
5536 has_ck505 = false;
5537 can_ssc = true;
5538 }
5539
Imre Deak2de69052013-05-08 13:14:04 +03005540 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5541 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005542
5543 /* Ironlake: try to setup display ref clock before DPLL
5544 * enabling. This is only under driver's control after
5545 * PCH B stepping, previous chipset stepping should be
5546 * ignoring this setting.
5547 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005548 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005549
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005550 /* As we must carefully and slowly disable/enable each source in turn,
5551 * compute the final state we want first and check if we need to
5552 * make any changes at all.
5553 */
5554 final = val;
5555 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07005556 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005557 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07005558 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005559 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5560
5561 final &= ~DREF_SSC_SOURCE_MASK;
5562 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5563 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005564
Keith Packard199e5d72011-09-22 12:01:57 -07005565 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005566 final |= DREF_SSC_SOURCE_ENABLE;
5567
5568 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5569 final |= DREF_SSC1_ENABLE;
5570
5571 if (has_cpu_edp) {
5572 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5573 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5574 else
5575 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5576 } else
5577 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5578 } else {
5579 final |= DREF_SSC_SOURCE_DISABLE;
5580 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5581 }
5582
5583 if (final == val)
5584 return;
5585
5586 /* Always enable nonspread source */
5587 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5588
5589 if (has_ck505)
5590 val |= DREF_NONSPREAD_CK505_ENABLE;
5591 else
5592 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5593
5594 if (has_panel) {
5595 val &= ~DREF_SSC_SOURCE_MASK;
5596 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005597
Keith Packard199e5d72011-09-22 12:01:57 -07005598 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005599 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005600 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005601 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02005602 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005603 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005604
5605 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005606 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005607 POSTING_READ(PCH_DREF_CONTROL);
5608 udelay(200);
5609
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005610 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005611
5612 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005613 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005614 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005615 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005616 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005617 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005618 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005619 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005620 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005621 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005622
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005623 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005624 POSTING_READ(PCH_DREF_CONTROL);
5625 udelay(200);
5626 } else {
5627 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5628
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005629 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07005630
5631 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005632 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005633
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005634 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005635 POSTING_READ(PCH_DREF_CONTROL);
5636 udelay(200);
5637
5638 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005639 val &= ~DREF_SSC_SOURCE_MASK;
5640 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005641
5642 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005643 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005644
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005645 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005646 POSTING_READ(PCH_DREF_CONTROL);
5647 udelay(200);
5648 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005649
5650 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005651}
5652
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005653static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02005654{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005655 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02005656
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005657 tmp = I915_READ(SOUTH_CHICKEN2);
5658 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5659 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005660
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005661 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5662 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5663 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02005664
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005665 tmp = I915_READ(SOUTH_CHICKEN2);
5666 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5667 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005668
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005669 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5670 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5671 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005672}
5673
5674/* WaMPhyProgramming:hsw */
5675static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5676{
5677 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02005678
5679 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5680 tmp &= ~(0xFF << 24);
5681 tmp |= (0x12 << 24);
5682 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5683
Paulo Zanonidde86e22012-12-01 12:04:25 -02005684 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5685 tmp |= (1 << 11);
5686 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5687
5688 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5689 tmp |= (1 << 11);
5690 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5691
Paulo Zanonidde86e22012-12-01 12:04:25 -02005692 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5693 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5694 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5695
5696 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5697 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5698 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5699
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005700 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5701 tmp &= ~(7 << 13);
5702 tmp |= (5 << 13);
5703 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005704
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005705 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5706 tmp &= ~(7 << 13);
5707 tmp |= (5 << 13);
5708 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005709
5710 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5711 tmp &= ~0xFF;
5712 tmp |= 0x1C;
5713 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5714
5715 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5716 tmp &= ~0xFF;
5717 tmp |= 0x1C;
5718 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5719
5720 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5721 tmp &= ~(0xFF << 16);
5722 tmp |= (0x1C << 16);
5723 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5724
5725 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5726 tmp &= ~(0xFF << 16);
5727 tmp |= (0x1C << 16);
5728 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5729
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005730 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5731 tmp |= (1 << 27);
5732 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005733
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005734 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5735 tmp |= (1 << 27);
5736 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005737
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005738 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5739 tmp &= ~(0xF << 28);
5740 tmp |= (4 << 28);
5741 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005742
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005743 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5744 tmp &= ~(0xF << 28);
5745 tmp |= (4 << 28);
5746 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005747}
5748
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005749/* Implements 3 different sequences from BSpec chapter "Display iCLK
5750 * Programming" based on the parameters passed:
5751 * - Sequence to enable CLKOUT_DP
5752 * - Sequence to enable CLKOUT_DP without spread
5753 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5754 */
5755static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5756 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005757{
5758 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005759 uint32_t reg, tmp;
5760
5761 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5762 with_spread = true;
5763 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5764 with_fdi, "LP PCH doesn't have FDI\n"))
5765 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005766
5767 mutex_lock(&dev_priv->dpio_lock);
5768
5769 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5770 tmp &= ~SBI_SSCCTL_DISABLE;
5771 tmp |= SBI_SSCCTL_PATHALT;
5772 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5773
5774 udelay(24);
5775
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005776 if (with_spread) {
5777 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5778 tmp &= ~SBI_SSCCTL_PATHALT;
5779 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005780
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005781 if (with_fdi) {
5782 lpt_reset_fdi_mphy(dev_priv);
5783 lpt_program_fdi_mphy(dev_priv);
5784 }
5785 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02005786
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005787 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5788 SBI_GEN0 : SBI_DBUFF0;
5789 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5790 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5791 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01005792
5793 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005794}
5795
Paulo Zanoni47701c32013-07-23 11:19:25 -03005796/* Sequence to disable CLKOUT_DP */
5797static void lpt_disable_clkout_dp(struct drm_device *dev)
5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 uint32_t reg, tmp;
5801
5802 mutex_lock(&dev_priv->dpio_lock);
5803
5804 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5805 SBI_GEN0 : SBI_DBUFF0;
5806 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5807 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5808 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5809
5810 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5811 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5812 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5813 tmp |= SBI_SSCCTL_PATHALT;
5814 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5815 udelay(32);
5816 }
5817 tmp |= SBI_SSCCTL_DISABLE;
5818 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5819 }
5820
5821 mutex_unlock(&dev_priv->dpio_lock);
5822}
5823
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03005824static void lpt_init_pch_refclk(struct drm_device *dev)
5825{
5826 struct drm_mode_config *mode_config = &dev->mode_config;
5827 struct intel_encoder *encoder;
5828 bool has_vga = false;
5829
5830 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5831 switch (encoder->type) {
5832 case INTEL_OUTPUT_ANALOG:
5833 has_vga = true;
5834 break;
5835 }
5836 }
5837
Paulo Zanoni47701c32013-07-23 11:19:25 -03005838 if (has_vga)
5839 lpt_enable_clkout_dp(dev, true, true);
5840 else
5841 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03005842}
5843
Paulo Zanonidde86e22012-12-01 12:04:25 -02005844/*
5845 * Initialize reference clocks when the driver loads
5846 */
5847void intel_init_pch_refclk(struct drm_device *dev)
5848{
5849 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5850 ironlake_init_pch_refclk(dev);
5851 else if (HAS_PCH_LPT(dev))
5852 lpt_init_pch_refclk(dev);
5853}
5854
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005855static int ironlake_get_refclk(struct drm_crtc *crtc)
5856{
5857 struct drm_device *dev = crtc->dev;
5858 struct drm_i915_private *dev_priv = dev->dev_private;
5859 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005860 int num_connectors = 0;
5861 bool is_lvds = false;
5862
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005863 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005864 switch (encoder->type) {
5865 case INTEL_OUTPUT_LVDS:
5866 is_lvds = true;
5867 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005868 }
5869 num_connectors++;
5870 }
5871
5872 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5873 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005874 dev_priv->vbt.lvds_ssc_freq);
5875 return dev_priv->vbt.lvds_ssc_freq * 1000;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005876 }
5877
5878 return 120000;
5879}
5880
Daniel Vetter6ff93602013-04-19 11:24:36 +02005881static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03005882{
5883 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885 int pipe = intel_crtc->pipe;
5886 uint32_t val;
5887
Daniel Vetter78114072013-06-13 00:54:57 +02005888 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03005889
Daniel Vetter965e0c42013-03-27 00:44:57 +01005890 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03005891 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005892 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005893 break;
5894 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005895 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005896 break;
5897 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005898 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005899 break;
5900 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005901 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005902 break;
5903 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005904 /* Case prevented by intel_choose_pipe_bpp_dither. */
5905 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005906 }
5907
Daniel Vetterd8b32242013-04-25 17:54:44 +02005908 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03005909 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5910
Daniel Vetter6ff93602013-04-19 11:24:36 +02005911 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03005912 val |= PIPECONF_INTERLACED_ILK;
5913 else
5914 val |= PIPECONF_PROGRESSIVE;
5915
Daniel Vetter50f3b012013-03-27 00:44:56 +01005916 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005917 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005918
Paulo Zanonic8203562012-09-12 10:06:29 -03005919 I915_WRITE(PIPECONF(pipe), val);
5920 POSTING_READ(PIPECONF(pipe));
5921}
5922
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005923/*
5924 * Set up the pipe CSC unit.
5925 *
5926 * Currently only full range RGB to limited range RGB conversion
5927 * is supported, but eventually this should handle various
5928 * RGB<->YCbCr scenarios as well.
5929 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01005930static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005931{
5932 struct drm_device *dev = crtc->dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5935 int pipe = intel_crtc->pipe;
5936 uint16_t coeff = 0x7800; /* 1.0 */
5937
5938 /*
5939 * TODO: Check what kind of values actually come out of the pipe
5940 * with these coeff/postoff values and adjust to get the best
5941 * accuracy. Perhaps we even need to take the bpc value into
5942 * consideration.
5943 */
5944
Daniel Vetter50f3b012013-03-27 00:44:56 +01005945 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005946 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5947
5948 /*
5949 * GY/GU and RY/RU should be the other way around according
5950 * to BSpec, but reality doesn't agree. Just set them up in
5951 * a way that results in the correct picture.
5952 */
5953 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5954 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5955
5956 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5957 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5958
5959 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5960 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5961
5962 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5963 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5964 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5965
5966 if (INTEL_INFO(dev)->gen > 6) {
5967 uint16_t postoff = 0;
5968
Daniel Vetter50f3b012013-03-27 00:44:56 +01005969 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005970 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5971
5972 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5973 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5974 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5975
5976 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5977 } else {
5978 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5979
Daniel Vetter50f3b012013-03-27 00:44:56 +01005980 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005981 mode |= CSC_BLACK_SCREEN_OFFSET;
5982
5983 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5984 }
5985}
5986
Daniel Vetter6ff93602013-04-19 11:24:36 +02005987static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005988{
5989 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02005991 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005992 uint32_t val;
5993
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02005994 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005995
Daniel Vetterd8b32242013-04-25 17:54:44 +02005996 if (intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005997 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5998
Daniel Vetter6ff93602013-04-19 11:24:36 +02005999 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006000 val |= PIPECONF_INTERLACED_ILK;
6001 else
6002 val |= PIPECONF_PROGRESSIVE;
6003
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006004 I915_WRITE(PIPECONF(cpu_transcoder), val);
6005 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006006
6007 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6008 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006009}
6010
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006011static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006012 intel_clock_t *clock,
6013 bool *has_reduced_clock,
6014 intel_clock_t *reduced_clock)
6015{
6016 struct drm_device *dev = crtc->dev;
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 struct intel_encoder *intel_encoder;
6019 int refclk;
6020 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006021 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006022
6023 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6024 switch (intel_encoder->type) {
6025 case INTEL_OUTPUT_LVDS:
6026 is_lvds = true;
6027 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006028 }
6029 }
6030
6031 refclk = ironlake_get_refclk(crtc);
6032
6033 /*
6034 * Returns a set of divisors for the desired target clock with the given
6035 * refclk, or FALSE. The returned values represent the clock equation:
6036 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6037 */
6038 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006039 ret = dev_priv->display.find_dpll(limit, crtc,
6040 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006041 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006042 if (!ret)
6043 return false;
6044
6045 if (is_lvds && dev_priv->lvds_downclock_avail) {
6046 /*
6047 * Ensure we match the reduced clock's P to the target clock.
6048 * If the clocks don't match, we can't switch the display clock
6049 * by using the FP0/FP1. In such case we will disable the LVDS
6050 * downclock feature.
6051 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006052 *has_reduced_clock =
6053 dev_priv->display.find_dpll(limit, crtc,
6054 dev_priv->lvds_downclock,
6055 refclk, clock,
6056 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006057 }
6058
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006059 return true;
6060}
6061
Paulo Zanonid4b19312012-11-29 11:29:32 -02006062int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6063{
6064 /*
6065 * Account for spread spectrum to avoid
6066 * oversubscribing the link. Max center spread
6067 * is 2.5%; use 5% for safety's sake.
6068 */
6069 u32 bps = target_clock * bpp * 21 / 20;
6070 return bps / (link_bw * 8) + 1;
6071}
6072
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006073static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006074{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006075 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006076}
6077
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006078static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006079 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006080 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006081{
6082 struct drm_crtc *crtc = &intel_crtc->base;
6083 struct drm_device *dev = crtc->dev;
6084 struct drm_i915_private *dev_priv = dev->dev_private;
6085 struct intel_encoder *intel_encoder;
6086 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006087 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006088 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006089
6090 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6091 switch (intel_encoder->type) {
6092 case INTEL_OUTPUT_LVDS:
6093 is_lvds = true;
6094 break;
6095 case INTEL_OUTPUT_SDVO:
6096 case INTEL_OUTPUT_HDMI:
6097 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006098 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006099 }
6100
6101 num_connectors++;
6102 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006103
Chris Wilsonc1858122010-12-03 21:35:48 +00006104 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006105 factor = 21;
6106 if (is_lvds) {
6107 if ((intel_panel_use_ssc(dev_priv) &&
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03006108 dev_priv->vbt.lvds_ssc_freq == 100) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006109 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006110 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006111 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006112 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006113
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006114 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006115 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006116
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006117 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6118 *fp2 |= FP_CB_TUNE;
6119
Chris Wilson5eddb702010-09-11 13:48:45 +01006120 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006121
Eric Anholta07d6782011-03-30 13:01:08 -07006122 if (is_lvds)
6123 dpll |= DPLLB_MODE_LVDS;
6124 else
6125 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006126
Daniel Vetteref1b4602013-06-01 17:17:04 +02006127 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6128 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006129
6130 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006131 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006132 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006133 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006134
Eric Anholta07d6782011-03-30 13:01:08 -07006135 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006136 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006137 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006138 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006139
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006140 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006141 case 5:
6142 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6143 break;
6144 case 7:
6145 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6146 break;
6147 case 10:
6148 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6149 break;
6150 case 14:
6151 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6152 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006153 }
6154
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006155 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006156 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08006157 else
6158 dpll |= PLL_REF_INPUT_DREFCLK;
6159
Daniel Vetter959e16d2013-06-05 13:34:21 +02006160 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006161}
6162
Jesse Barnes79e53942008-11-07 14:24:08 -08006163static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006164 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006165 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006166{
6167 struct drm_device *dev = crtc->dev;
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6170 int pipe = intel_crtc->pipe;
6171 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006172 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006173 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006174 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03006175 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01006176 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006177 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02006178 struct intel_shared_dpll *pll;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006179 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006180
6181 for_each_encoder_on_crtc(dev, crtc, encoder) {
6182 switch (encoder->type) {
6183 case INTEL_OUTPUT_LVDS:
6184 is_lvds = true;
6185 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006186 }
6187
6188 num_connectors++;
6189 }
6190
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006191 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6192 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6193
Daniel Vetterff9a6752013-06-01 17:16:21 +02006194 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006195 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02006196 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006197 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6198 return -EINVAL;
6199 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01006200 /* Compat-code for transition, will disappear. */
6201 if (!intel_crtc->config.clock_set) {
6202 intel_crtc->config.dpll.n = clock.n;
6203 intel_crtc->config.dpll.m1 = clock.m1;
6204 intel_crtc->config.dpll.m2 = clock.m2;
6205 intel_crtc->config.dpll.p1 = clock.p1;
6206 intel_crtc->config.dpll.p2 = clock.p2;
6207 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006208
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006209 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01006210 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006211 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006212 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006213 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006214
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006215 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006216 &fp, &reduced_clock,
6217 has_reduced_clock ? &fp2 : NULL);
6218
Daniel Vetter959e16d2013-06-05 13:34:21 +02006219 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02006220 intel_crtc->config.dpll_hw_state.fp0 = fp;
6221 if (has_reduced_clock)
6222 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6223 else
6224 intel_crtc->config.dpll_hw_state.fp1 = fp;
6225
Daniel Vetterb89a1d32013-06-05 13:34:24 +02006226 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006227 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03006228 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6229 pipe_name(pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07006230 return -EINVAL;
6231 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006232 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02006233 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006234
Daniel Vetter03afc4a2013-04-02 23:42:31 +02006235 if (intel_crtc->config.has_dp_encoder)
6236 intel_dp_set_m_n(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006237
Daniel Vetterbcd644e2013-06-05 13:34:22 +02006238 if (is_lvds && has_reduced_clock && i915_powersave)
6239 intel_crtc->lowfreq_avail = true;
6240 else
6241 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02006242
Daniel Vetter8a654f32013-06-01 17:16:22 +02006243 intel_set_pipe_timings(intel_crtc);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02006244
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01006245 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01006246 intel_cpu_transcoder_set_m_n(intel_crtc,
6247 &intel_crtc->config.fdi_m_n);
6248 }
Chris Wilson5eddb702010-09-11 13:48:45 +01006249
Daniel Vetter6ff93602013-04-19 11:24:36 +02006250 ironlake_set_pipeconf(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006251
Paulo Zanonia1f9e772012-09-12 10:06:32 -03006252 /* Set up the display plane register */
6253 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08006254 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08006255
Daniel Vetter94352cf2012-07-05 22:51:56 +02006256 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08006257
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006258 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006259}
6260
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006261static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6262 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02006263{
6264 struct drm_device *dev = crtc->base.dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006266 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02006267
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006268 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6269 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6270 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6271 & ~TU_SIZE_MASK;
6272 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6273 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6274 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6275}
6276
6277static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6278 enum transcoder transcoder,
6279 struct intel_link_m_n *m_n)
6280{
6281 struct drm_device *dev = crtc->base.dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283 enum pipe pipe = crtc->pipe;
6284
6285 if (INTEL_INFO(dev)->gen >= 5) {
6286 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6287 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6288 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6289 & ~TU_SIZE_MASK;
6290 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6291 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6292 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6293 } else {
6294 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6295 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6296 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6297 & ~TU_SIZE_MASK;
6298 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6299 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6300 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6301 }
6302}
6303
6304void intel_dp_get_m_n(struct intel_crtc *crtc,
6305 struct intel_crtc_config *pipe_config)
6306{
6307 if (crtc->config.has_pch_encoder)
6308 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6309 else
6310 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6311 &pipe_config->dp_m_n);
6312}
6313
Daniel Vetter72419202013-04-04 13:28:53 +02006314static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6315 struct intel_crtc_config *pipe_config)
6316{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006317 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6318 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02006319}
6320
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006321static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6322 struct intel_crtc_config *pipe_config)
6323{
6324 struct drm_device *dev = crtc->base.dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 uint32_t tmp;
6327
6328 tmp = I915_READ(PF_CTL(crtc->pipe));
6329
6330 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01006331 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006332 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6333 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02006334
6335 /* We currently do not free assignements of panel fitters on
6336 * ivb/hsw (since we don't use the higher upscaling modes which
6337 * differentiates them) so just WARN about this case for now. */
6338 if (IS_GEN7(dev)) {
6339 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6340 PF_PIPE_SEL_IVB(crtc->pipe));
6341 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006342 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006343}
6344
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006345static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6346 struct intel_crtc_config *pipe_config)
6347{
6348 struct drm_device *dev = crtc->base.dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 uint32_t tmp;
6351
Daniel Vettere143a212013-07-04 12:01:15 +02006352 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006353 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006354
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006355 tmp = I915_READ(PIPECONF(crtc->pipe));
6356 if (!(tmp & PIPECONF_ENABLE))
6357 return false;
6358
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006359 switch (tmp & PIPECONF_BPC_MASK) {
6360 case PIPECONF_6BPC:
6361 pipe_config->pipe_bpp = 18;
6362 break;
6363 case PIPECONF_8BPC:
6364 pipe_config->pipe_bpp = 24;
6365 break;
6366 case PIPECONF_10BPC:
6367 pipe_config->pipe_bpp = 30;
6368 break;
6369 case PIPECONF_12BPC:
6370 pipe_config->pipe_bpp = 36;
6371 break;
6372 default:
6373 break;
6374 }
6375
Daniel Vetterab9412b2013-05-03 11:49:46 +02006376 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02006377 struct intel_shared_dpll *pll;
6378
Daniel Vetter88adfff2013-03-28 10:42:01 +01006379 pipe_config->has_pch_encoder = true;
6380
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006381 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6382 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6383 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02006384
6385 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02006386
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006387 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02006388 pipe_config->shared_dpll =
6389 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006390 } else {
6391 tmp = I915_READ(PCH_DPLL_SEL);
6392 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6393 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6394 else
6395 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6396 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02006397
6398 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6399
6400 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6401 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02006402
6403 tmp = pipe_config->dpll_hw_state.dpll;
6404 pipe_config->pixel_multiplier =
6405 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6406 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03006407
6408 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02006409 } else {
6410 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006411 }
6412
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006413 intel_get_pipe_timings(crtc, pipe_config);
6414
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006415 ironlake_get_pfit_config(crtc, pipe_config);
6416
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006417 return true;
6418}
6419
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006420static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6421{
6422 struct drm_device *dev = dev_priv->dev;
6423 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6424 struct intel_crtc *crtc;
6425 unsigned long irqflags;
Paulo Zanonibd633a72013-08-19 13:18:08 -03006426 uint32_t val;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006427
6428 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6429 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6430 pipe_name(crtc->pipe));
6431
6432 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6433 WARN(plls->spll_refcount, "SPLL enabled\n");
6434 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6435 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6436 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6437 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6438 "CPU PWM1 enabled\n");
6439 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6440 "CPU PWM2 enabled\n");
6441 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6442 "PCH PWM1 enabled\n");
6443 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6444 "Utility pin enabled\n");
6445 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6446
6447 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6448 val = I915_READ(DEIMR);
6449 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6450 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6451 val = I915_READ(SDEIMR);
Paulo Zanonibd633a72013-08-19 13:18:08 -03006452 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006453 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6454 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6455}
6456
6457/*
6458 * This function implements pieces of two sequences from BSpec:
6459 * - Sequence for display software to disable LCPLL
6460 * - Sequence for display software to allow package C8+
6461 * The steps implemented here are just the steps that actually touch the LCPLL
6462 * register. Callers should take care of disabling all the display engine
6463 * functions, doing the mode unset, fixing interrupts, etc.
6464 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03006465static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6466 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006467{
6468 uint32_t val;
6469
6470 assert_can_disable_lcpll(dev_priv);
6471
6472 val = I915_READ(LCPLL_CTL);
6473
6474 if (switch_to_fclk) {
6475 val |= LCPLL_CD_SOURCE_FCLK;
6476 I915_WRITE(LCPLL_CTL, val);
6477
6478 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6479 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6480 DRM_ERROR("Switching to FCLK failed\n");
6481
6482 val = I915_READ(LCPLL_CTL);
6483 }
6484
6485 val |= LCPLL_PLL_DISABLE;
6486 I915_WRITE(LCPLL_CTL, val);
6487 POSTING_READ(LCPLL_CTL);
6488
6489 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6490 DRM_ERROR("LCPLL still locked\n");
6491
6492 val = I915_READ(D_COMP);
6493 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni515b2392013-09-10 19:36:37 -03006494 mutex_lock(&dev_priv->rps.hw_lock);
6495 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6496 DRM_ERROR("Failed to disable D_COMP\n");
6497 mutex_unlock(&dev_priv->rps.hw_lock);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006498 POSTING_READ(D_COMP);
6499 ndelay(100);
6500
6501 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6502 DRM_ERROR("D_COMP RCOMP still in progress\n");
6503
6504 if (allow_power_down) {
6505 val = I915_READ(LCPLL_CTL);
6506 val |= LCPLL_POWER_DOWN_ALLOW;
6507 I915_WRITE(LCPLL_CTL, val);
6508 POSTING_READ(LCPLL_CTL);
6509 }
6510}
6511
6512/*
6513 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6514 * source.
6515 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03006516static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006517{
6518 uint32_t val;
6519
6520 val = I915_READ(LCPLL_CTL);
6521
6522 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6523 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6524 return;
6525
Paulo Zanoni215733f2013-08-19 13:18:07 -03006526 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6527 * we'll hang the machine! */
6528 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6529
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006530 if (val & LCPLL_POWER_DOWN_ALLOW) {
6531 val &= ~LCPLL_POWER_DOWN_ALLOW;
6532 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02006533 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006534 }
6535
6536 val = I915_READ(D_COMP);
6537 val |= D_COMP_COMP_FORCE;
6538 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni515b2392013-09-10 19:36:37 -03006539 mutex_lock(&dev_priv->rps.hw_lock);
6540 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6541 DRM_ERROR("Failed to enable D_COMP\n");
6542 mutex_unlock(&dev_priv->rps.hw_lock);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02006543 POSTING_READ(D_COMP);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006544
6545 val = I915_READ(LCPLL_CTL);
6546 val &= ~LCPLL_PLL_DISABLE;
6547 I915_WRITE(LCPLL_CTL, val);
6548
6549 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6550 DRM_ERROR("LCPLL not locked yet\n");
6551
6552 if (val & LCPLL_CD_SOURCE_FCLK) {
6553 val = I915_READ(LCPLL_CTL);
6554 val &= ~LCPLL_CD_SOURCE_FCLK;
6555 I915_WRITE(LCPLL_CTL, val);
6556
6557 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6558 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6559 DRM_ERROR("Switching back to LCPLL failed\n");
6560 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03006561
6562 dev_priv->uncore.funcs.force_wake_put(dev_priv);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006563}
6564
Paulo Zanonic67a4702013-08-19 13:18:09 -03006565void hsw_enable_pc8_work(struct work_struct *__work)
6566{
6567 struct drm_i915_private *dev_priv =
6568 container_of(to_delayed_work(__work), struct drm_i915_private,
6569 pc8.enable_work);
6570 struct drm_device *dev = dev_priv->dev;
6571 uint32_t val;
6572
6573 if (dev_priv->pc8.enabled)
6574 return;
6575
6576 DRM_DEBUG_KMS("Enabling package C8+\n");
6577
6578 dev_priv->pc8.enabled = true;
6579
6580 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6581 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6582 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6583 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6584 }
6585
6586 lpt_disable_clkout_dp(dev);
6587 hsw_pc8_disable_interrupts(dev);
6588 hsw_disable_lcpll(dev_priv, true, true);
6589}
6590
6591static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6592{
6593 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6594 WARN(dev_priv->pc8.disable_count < 1,
6595 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6596
6597 dev_priv->pc8.disable_count--;
6598 if (dev_priv->pc8.disable_count != 0)
6599 return;
6600
6601 schedule_delayed_work(&dev_priv->pc8.enable_work,
Paulo Zanoni90058742013-08-19 13:18:11 -03006602 msecs_to_jiffies(i915_pc8_timeout));
Paulo Zanonic67a4702013-08-19 13:18:09 -03006603}
6604
6605static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6606{
6607 struct drm_device *dev = dev_priv->dev;
6608 uint32_t val;
6609
6610 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6611 WARN(dev_priv->pc8.disable_count < 0,
6612 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6613
6614 dev_priv->pc8.disable_count++;
6615 if (dev_priv->pc8.disable_count != 1)
6616 return;
6617
6618 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6619 if (!dev_priv->pc8.enabled)
6620 return;
6621
6622 DRM_DEBUG_KMS("Disabling package C8+\n");
6623
6624 hsw_restore_lcpll(dev_priv);
6625 hsw_pc8_restore_interrupts(dev);
6626 lpt_init_pch_refclk(dev);
6627
6628 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6629 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6630 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6631 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6632 }
6633
6634 intel_prepare_ddi(dev);
6635 i915_gem_init_swizzling(dev);
6636 mutex_lock(&dev_priv->rps.hw_lock);
6637 gen6_update_ring_freq(dev);
6638 mutex_unlock(&dev_priv->rps.hw_lock);
6639 dev_priv->pc8.enabled = false;
6640}
6641
6642void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6643{
6644 mutex_lock(&dev_priv->pc8.lock);
6645 __hsw_enable_package_c8(dev_priv);
6646 mutex_unlock(&dev_priv->pc8.lock);
6647}
6648
6649void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6650{
6651 mutex_lock(&dev_priv->pc8.lock);
6652 __hsw_disable_package_c8(dev_priv);
6653 mutex_unlock(&dev_priv->pc8.lock);
6654}
6655
6656static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6657{
6658 struct drm_device *dev = dev_priv->dev;
6659 struct intel_crtc *crtc;
6660 uint32_t val;
6661
6662 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6663 if (crtc->base.enabled)
6664 return false;
6665
6666 /* This case is still possible since we have the i915.disable_power_well
6667 * parameter and also the KVMr or something else might be requesting the
6668 * power well. */
6669 val = I915_READ(HSW_PWR_WELL_DRIVER);
6670 if (val != 0) {
6671 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6672 return false;
6673 }
6674
6675 return true;
6676}
6677
6678/* Since we're called from modeset_global_resources there's no way to
6679 * symmetrically increase and decrease the refcount, so we use
6680 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6681 * or not.
6682 */
6683static void hsw_update_package_c8(struct drm_device *dev)
6684{
6685 struct drm_i915_private *dev_priv = dev->dev_private;
6686 bool allow;
6687
6688 if (!i915_enable_pc8)
6689 return;
6690
6691 mutex_lock(&dev_priv->pc8.lock);
6692
6693 allow = hsw_can_enable_package_c8(dev_priv);
6694
6695 if (allow == dev_priv->pc8.requirements_met)
6696 goto done;
6697
6698 dev_priv->pc8.requirements_met = allow;
6699
6700 if (allow)
6701 __hsw_enable_package_c8(dev_priv);
6702 else
6703 __hsw_disable_package_c8(dev_priv);
6704
6705done:
6706 mutex_unlock(&dev_priv->pc8.lock);
6707}
6708
6709static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6710{
6711 if (!dev_priv->pc8.gpu_idle) {
6712 dev_priv->pc8.gpu_idle = true;
6713 hsw_enable_package_c8(dev_priv);
6714 }
6715}
6716
6717static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6718{
6719 if (dev_priv->pc8.gpu_idle) {
6720 dev_priv->pc8.gpu_idle = false;
6721 hsw_disable_package_c8(dev_priv);
6722 }
Daniel Vetter94352cf2012-07-05 22:51:56 +02006723}
Eric Anholtf564048e2011-03-30 13:01:02 -07006724
Imre Deak6efdf352013-10-16 17:25:52 +03006725#define for_each_power_domain(domain, mask) \
6726 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6727 if ((1 << (domain)) & (mask))
6728
6729static unsigned long get_pipe_power_domains(struct drm_device *dev,
6730 enum pipe pipe, bool pfit_enabled)
6731{
6732 unsigned long mask;
6733 enum transcoder transcoder;
6734
6735 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6736
6737 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6738 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6739 if (pfit_enabled)
6740 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6741
6742 return mask;
6743}
6744
Imre Deakbaa70702013-10-25 17:36:48 +03006745void intel_display_set_init_power(struct drm_device *dev, bool enable)
6746{
6747 struct drm_i915_private *dev_priv = dev->dev_private;
6748
6749 if (dev_priv->power_domains.init_power_on == enable)
6750 return;
6751
6752 if (enable)
6753 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6754 else
6755 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6756
6757 dev_priv->power_domains.init_power_on = enable;
6758}
6759
Imre Deak4f074122013-10-16 17:25:51 +03006760static void modeset_update_power_wells(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08006761{
Imre Deak6efdf352013-10-16 17:25:52 +03006762 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
Jesse Barnes79e53942008-11-07 14:24:08 -08006763 struct intel_crtc *crtc;
6764
Imre Deak6efdf352013-10-16 17:25:52 +03006765 /*
6766 * First get all needed power domains, then put all unneeded, to avoid
6767 * any unnecessary toggling of the power wells.
6768 */
Jesse Barnes79e53942008-11-07 14:24:08 -08006769 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Imre Deak6efdf352013-10-16 17:25:52 +03006770 enum intel_display_power_domain domain;
6771
Jesse Barnes79e53942008-11-07 14:24:08 -08006772 if (!crtc->base.enabled)
6773 continue;
6774
Imre Deak6efdf352013-10-16 17:25:52 +03006775 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6776 crtc->pipe,
6777 crtc->config.pch_pfit.enabled);
6778
6779 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6780 intel_display_power_get(dev, domain);
Jesse Barnes79e53942008-11-07 14:24:08 -08006781 }
6782
Imre Deak6efdf352013-10-16 17:25:52 +03006783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6784 enum intel_display_power_domain domain;
6785
6786 for_each_power_domain(domain, crtc->enabled_power_domains)
6787 intel_display_power_put(dev, domain);
6788
6789 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6790 }
Imre Deakbaa70702013-10-25 17:36:48 +03006791
6792 intel_display_set_init_power(dev, false);
Imre Deak4f074122013-10-16 17:25:51 +03006793}
Paulo Zanonic67a4702013-08-19 13:18:09 -03006794
Imre Deak4f074122013-10-16 17:25:51 +03006795static void haswell_modeset_global_resources(struct drm_device *dev)
6796{
6797 modeset_update_power_wells(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006798 hsw_update_package_c8(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006799}
6800
6801static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6802 int x, int y,
6803 struct drm_framebuffer *fb)
6804{
6805 struct drm_device *dev = crtc->dev;
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808 int plane = intel_crtc->plane;
6809 int ret;
6810
6811 if (!intel_ddi_pll_mode_set(crtc))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006812 return -EINVAL;
Eric Anholtbad720f2009-10-22 16:11:14 -07006813
Chris Wilson560b85b2010-08-07 11:01:38 +01006814 if (intel_crtc->config.has_dp_encoder)
6815 intel_dp_set_m_n(intel_crtc);
6816
6817 intel_crtc->lowfreq_avail = false;
6818
6819 intel_set_pipe_timings(intel_crtc);
6820
6821 if (intel_crtc->config.has_pch_encoder) {
6822 intel_cpu_transcoder_set_m_n(intel_crtc,
6823 &intel_crtc->config.fdi_m_n);
6824 }
6825
6826 haswell_set_pipeconf(crtc);
6827
6828 intel_set_pipe_csc(crtc);
6829
6830 /* Set up the display plane register */
6831 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6832 POSTING_READ(DSPCNTR(plane));
6833
6834 ret = intel_pipe_set_base(crtc, x, y, fb);
6835
Chris Wilson560b85b2010-08-07 11:01:38 +01006836 return ret;
6837}
6838
6839static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6840 struct intel_crtc_config *pipe_config)
6841{
6842 struct drm_device *dev = crtc->base.dev;
6843 struct drm_i915_private *dev_priv = dev->dev_private;
6844 enum intel_display_power_domain pfit_domain;
6845 uint32_t tmp;
6846
6847 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6848 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6849
6850 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6851 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6852 enum pipe trans_edp_pipe;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006853 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
Chris Wilson6b383a72010-09-13 13:54:26 +01006854 default:
6855 WARN(1, "unknown pipe linked to edp transcoder\n");
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006856 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6857 case TRANS_DDI_EDP_INPUT_A_ON:
6858 trans_edp_pipe = PIPE_A;
6859 break;
6860 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6861 trans_edp_pipe = PIPE_B;
6862 break;
Chris Wilson560b85b2010-08-07 11:01:38 +01006863 case TRANS_DDI_EDP_INPUT_C_ONOFF:
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006864 trans_edp_pipe = PIPE_C;
6865 break;
6866 }
6867
Chris Wilson6b383a72010-09-13 13:54:26 +01006868 if (trans_edp_pipe == crtc->pipe)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006869 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6870 }
6871
6872 if (!intel_display_power_enabled(dev,
6873 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6874 return false;
6875
6876 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6877 if (!(tmp & PIPECONF_ENABLE))
6878 return false;
6879
6880 /*
6881 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6882 * DDI E. So just check whether this pipe is wired to DDI E and whether
6883 * the PCH transcoder is on.
6884 */
6885 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6886 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6887 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6888 pipe_config->has_pch_encoder = true;
6889
6890 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6891 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6892 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6893
6894 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6895 }
6896
Chris Wilson560b85b2010-08-07 11:01:38 +01006897 intel_get_pipe_timings(crtc, pipe_config);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006898
6899 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6900 if (intel_display_power_enabled(dev, pfit_domain))
Chris Wilson560b85b2010-08-07 11:01:38 +01006901 ironlake_get_pfit_config(crtc, pipe_config);
6902
6903 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6904 (I915_READ(IPS_CTL) & IPS_ENABLE);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006905
6906 pipe_config->pixel_multiplier = 1;
6907
6908 return true;
6909}
Jesse Barnes79e53942008-11-07 14:24:08 -08006910
Chris Wilson05394f32010-11-08 19:18:58 +00006911static int intel_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006912 int x, int y,
6913 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07006914{
Daniel Vetter9256aa12012-10-31 19:26:13 +01006915 struct drm_device *dev = crtc->dev;
6916 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholtf564048e2011-03-30 13:01:02 -07006917 struct intel_encoder *encoder;
Eric Anholt0b701d22011-03-30 13:01:03 -07006918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01006919 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Eric Anholt0b701d22011-03-30 13:01:03 -07006920 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07006921 int ret;
6922
Eric Anholt0b701d22011-03-30 13:01:03 -07006923 drm_vblank_pre_modeset(dev, pipe);
6924
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01006925 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6926
Jesse Barnes79e53942008-11-07 14:24:08 -08006927 drm_vblank_post_modeset(dev, pipe);
6928
Daniel Vetter9256aa12012-10-31 19:26:13 +01006929 if (ret != 0)
6930 return ret;
6931
6932 for_each_encoder_on_crtc(dev, crtc, encoder) {
6933 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6934 encoder->base.base.id,
6935 drm_get_encoder_name(&encoder->base),
6936 mode->base.id, mode->name);
Daniel Vetter36f2d1f2013-07-21 21:37:08 +02006937 encoder->mode_set(encoder);
Daniel Vetter9256aa12012-10-31 19:26:13 +01006938 }
6939
6940 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006941}
6942
Jani Nikula1a915102013-10-16 12:34:48 +03006943static struct {
6944 int clock;
6945 u32 config;
6946} hdmi_audio_clock[] = {
6947 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6948 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6949 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6950 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6951 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6952 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6953 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6954 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6955 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6956 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6957};
6958
6959/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6960static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6961{
6962 int i;
6963
6964 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6965 if (mode->clock == hdmi_audio_clock[i].clock)
6966 break;
6967 }
6968
6969 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6970 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6971 i = 1;
6972 }
6973
6974 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6975 hdmi_audio_clock[i].clock,
6976 hdmi_audio_clock[i].config);
6977
6978 return hdmi_audio_clock[i].config;
6979}
6980
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006981static bool intel_eld_uptodate(struct drm_connector *connector,
6982 int reg_eldv, uint32_t bits_eldv,
6983 int reg_elda, uint32_t bits_elda,
6984 int reg_edid)
6985{
6986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6987 uint8_t *eld = connector->eld;
6988 uint32_t i;
6989
6990 i = I915_READ(reg_eldv);
6991 i &= bits_eldv;
6992
6993 if (!eld[0])
6994 return !i;
6995
6996 if (!i)
6997 return false;
6998
6999 i = I915_READ(reg_elda);
7000 i &= ~bits_elda;
7001 I915_WRITE(reg_elda, i);
7002
7003 for (i = 0; i < eld[2]; i++)
7004 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7005 return false;
7006
7007 return true;
7008}
7009
Wu Fengguange0dac652011-09-05 14:25:34 +08007010static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007011 struct drm_crtc *crtc,
7012 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007013{
7014 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7015 uint8_t *eld = connector->eld;
7016 uint32_t eldv;
7017 uint32_t len;
7018 uint32_t i;
7019
7020 i = I915_READ(G4X_AUD_VID_DID);
7021
7022 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7023 eldv = G4X_ELDV_DEVCL_DEVBLC;
7024 else
7025 eldv = G4X_ELDV_DEVCTG;
7026
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007027 if (intel_eld_uptodate(connector,
7028 G4X_AUD_CNTL_ST, eldv,
7029 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7030 G4X_HDMIW_HDMIEDID))
7031 return;
7032
Wu Fengguange0dac652011-09-05 14:25:34 +08007033 i = I915_READ(G4X_AUD_CNTL_ST);
7034 i &= ~(eldv | G4X_ELD_ADDR);
7035 len = (i >> 9) & 0x1f; /* ELD buffer size */
7036 I915_WRITE(G4X_AUD_CNTL_ST, i);
7037
7038 if (!eld[0])
7039 return;
7040
7041 len = min_t(uint8_t, eld[2], len);
7042 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7043 for (i = 0; i < len; i++)
7044 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7045
7046 i = I915_READ(G4X_AUD_CNTL_ST);
7047 i |= eldv;
7048 I915_WRITE(G4X_AUD_CNTL_ST, i);
7049}
7050
Wang Xingchao83358c852012-08-16 22:43:37 +08007051static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007052 struct drm_crtc *crtc,
7053 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007054{
7055 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7056 uint8_t *eld = connector->eld;
7057 struct drm_device *dev = crtc->dev;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08007058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Wang Xingchao83358c852012-08-16 22:43:37 +08007059 uint32_t eldv;
7060 uint32_t i;
7061 int len;
7062 int pipe = to_intel_crtc(crtc)->pipe;
7063 int tmp;
7064
7065 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7066 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7067 int aud_config = HSW_AUD_CFG(pipe);
7068 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7069
7070
7071 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7072
7073 /* Audio output enable */
7074 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7075 tmp = I915_READ(aud_cntrl_st2);
7076 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7077 I915_WRITE(aud_cntrl_st2, tmp);
7078
7079 /* Wait for 1 vertical blank */
7080 intel_wait_for_vblank(dev, pipe);
7081
7082 /* Set ELD valid state */
7083 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007084 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007085 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7086 I915_WRITE(aud_cntrl_st2, tmp);
7087 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007088 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007089
7090 /* Enable HDMI mode */
7091 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007092 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007093 /* clear N_programing_enable and N_value_index */
7094 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7095 I915_WRITE(aud_config, tmp);
7096
7097 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7098
7099 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08007100 intel_crtc->eld_vld = true;
Wang Xingchao83358c852012-08-16 22:43:37 +08007101
7102 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7103 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7104 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7105 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007106 } else {
7107 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7108 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007109
7110 if (intel_eld_uptodate(connector,
7111 aud_cntrl_st2, eldv,
7112 aud_cntl_st, IBX_ELD_ADDRESS,
7113 hdmiw_hdmiedid))
7114 return;
7115
7116 i = I915_READ(aud_cntrl_st2);
7117 i &= ~eldv;
7118 I915_WRITE(aud_cntrl_st2, i);
7119
7120 if (!eld[0])
7121 return;
7122
7123 i = I915_READ(aud_cntl_st);
7124 i &= ~IBX_ELD_ADDRESS;
7125 I915_WRITE(aud_cntl_st, i);
7126 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7127 DRM_DEBUG_DRIVER("port num:%d\n", i);
7128
7129 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7130 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7131 for (i = 0; i < len; i++)
7132 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7133
7134 i = I915_READ(aud_cntrl_st2);
7135 i |= eldv;
7136 I915_WRITE(aud_cntrl_st2, i);
7137
7138}
7139
Wu Fengguange0dac652011-09-05 14:25:34 +08007140static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007141 struct drm_crtc *crtc,
7142 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007143{
7144 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7145 uint8_t *eld = connector->eld;
7146 uint32_t eldv;
7147 uint32_t i;
7148 int len;
7149 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007150 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007151 int aud_cntl_st;
7152 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007153 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007154
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007155 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007156 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7157 aud_config = IBX_AUD_CFG(pipe);
7158 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007159 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007160 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007161 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7162 aud_config = CPT_AUD_CFG(pipe);
7163 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007164 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007165 }
7166
Wang Xingchao9b138a82012-08-09 16:52:18 +08007167 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007168
7169 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08007170 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08007171 if (!i) {
7172 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7173 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007174 eldv = IBX_ELD_VALIDB;
7175 eldv |= IBX_ELD_VALIDB << 4;
7176 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007177 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007178 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007179 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007180 }
7181
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7183 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7184 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007185 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007186 } else {
7187 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7188 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007189
7190 if (intel_eld_uptodate(connector,
7191 aud_cntrl_st2, eldv,
7192 aud_cntl_st, IBX_ELD_ADDRESS,
7193 hdmiw_hdmiedid))
7194 return;
7195
Wu Fengguange0dac652011-09-05 14:25:34 +08007196 i = I915_READ(aud_cntrl_st2);
7197 i &= ~eldv;
7198 I915_WRITE(aud_cntrl_st2, i);
7199
7200 if (!eld[0])
7201 return;
7202
Wu Fengguange0dac652011-09-05 14:25:34 +08007203 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007204 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007205 I915_WRITE(aud_cntl_st, i);
7206
7207 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7208 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7209 for (i = 0; i < len; i++)
7210 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7211
7212 i = I915_READ(aud_cntrl_st2);
7213 i |= eldv;
7214 I915_WRITE(aud_cntrl_st2, i);
7215}
7216
7217void intel_write_eld(struct drm_encoder *encoder,
7218 struct drm_display_mode *mode)
7219{
7220 struct drm_crtc *crtc = encoder->crtc;
7221 struct drm_connector *connector;
7222 struct drm_device *dev = encoder->dev;
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224
7225 connector = drm_select_eld(encoder, mode);
7226 if (!connector)
7227 return;
7228
7229 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7230 connector->base.id,
7231 drm_get_connector_name(connector),
7232 connector->encoder->base.id,
7233 drm_get_encoder_name(connector->encoder));
7234
7235 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7236
7237 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007238 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007239}
7240
Jesse Barnes79e53942008-11-07 14:24:08 -08007241static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7242{
7243 struct drm_device *dev = crtc->dev;
7244 struct drm_i915_private *dev_priv = dev->dev_private;
7245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7246 bool visible = base != 0;
7247 u32 cntl;
7248
7249 if (intel_crtc->cursor_visible == visible)
7250 return;
7251
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007252 cntl = I915_READ(_CURACNTR);
Jesse Barnes79e53942008-11-07 14:24:08 -08007253 if (visible) {
7254 /* On these chipsets we can only modify the base whilst
7255 * the cursor is disabled.
7256 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007257 I915_WRITE(_CURABASE, base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007258
7259 cntl &= ~(CURSOR_FORMAT_MASK);
7260 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7261 cntl |= CURSOR_ENABLE |
7262 CURSOR_GAMMA_ENABLE |
7263 CURSOR_FORMAT_ARGB;
7264 } else
7265 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007266 I915_WRITE(_CURACNTR, cntl);
Jesse Barnes79e53942008-11-07 14:24:08 -08007267
7268 intel_crtc->cursor_visible = visible;
7269}
7270
7271static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7272{
7273 struct drm_device *dev = crtc->dev;
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7276 int pipe = intel_crtc->pipe;
7277 bool visible = base != 0;
7278
7279 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08007280 uint32_t cntl = I915_READ(CURCNTR(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08007281 if (base) {
7282 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7283 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7284 cntl |= pipe << 28; /* Connect to correct pipe */
7285 } else {
7286 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7287 cntl |= CURSOR_MODE_DISABLE;
7288 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007289 I915_WRITE(CURCNTR(pipe), cntl);
Jesse Barnes79e53942008-11-07 14:24:08 -08007290
7291 intel_crtc->cursor_visible = visible;
7292 }
7293 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007294 I915_WRITE(CURBASE(pipe), base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007295}
7296
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007297static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7298{
7299 struct drm_device *dev = crtc->dev;
7300 struct drm_i915_private *dev_priv = dev->dev_private;
7301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7302 int pipe = intel_crtc->pipe;
7303 bool visible = base != 0;
7304
7305 if (intel_crtc->cursor_visible != visible) {
7306 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7307 if (base) {
7308 cntl &= ~CURSOR_MODE;
7309 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7310 } else {
7311 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7312 cntl |= CURSOR_MODE_DISABLE;
7313 }
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03007314 if (IS_HASWELL(dev)) {
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007315 cntl |= CURSOR_PIPE_CSC_ENABLE;
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03007316 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7317 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007318 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7319
7320 intel_crtc->cursor_visible = visible;
7321 }
7322 /* and commit changes on next vblank */
7323 I915_WRITE(CURBASE_IVB(pipe), base);
7324}
7325
Jesse Barnes79e53942008-11-07 14:24:08 -08007326/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7327static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7328 bool on)
7329{
7330 struct drm_device *dev = crtc->dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7333 int pipe = intel_crtc->pipe;
7334 int x = intel_crtc->cursor_x;
7335 int y = intel_crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007336 u32 base = 0, pos = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007337 bool visible;
7338
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007339 if (on)
Jesse Barnes79e53942008-11-07 14:24:08 -08007340 base = intel_crtc->cursor_addr;
Jesse Barnes79e53942008-11-07 14:24:08 -08007341
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007342 if (x >= intel_crtc->config.pipe_src_w)
7343 base = 0;
7344
7345 if (y >= intel_crtc->config.pipe_src_h)
Jesse Barnes79e53942008-11-07 14:24:08 -08007346 base = 0;
7347
7348 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007349 if (x + intel_crtc->cursor_width <= 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08007350 base = 0;
7351
7352 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7353 x = -x;
7354 }
7355 pos |= x << CURSOR_X_SHIFT;
7356
7357 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007358 if (y + intel_crtc->cursor_height <= 0)
Jesse Barnes79e53942008-11-07 14:24:08 -08007359 base = 0;
7360
7361 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7362 y = -y;
7363 }
7364 pos |= y << CURSOR_Y_SHIFT;
7365
7366 visible = base != 0;
7367 if (!visible && !intel_crtc->cursor_visible)
7368 return;
7369
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03007370 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007371 I915_WRITE(CURPOS_IVB(pipe), pos);
7372 ivb_update_cursor(crtc, base);
7373 } else {
7374 I915_WRITE(CURPOS(pipe), pos);
7375 if (IS_845G(dev) || IS_I865G(dev))
7376 i845_update_cursor(crtc, base);
7377 else
7378 i9xx_update_cursor(crtc, base);
7379 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007380}
7381
7382static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7383 struct drm_file *file,
7384 uint32_t handle,
7385 uint32_t width, uint32_t height)
7386{
7387 struct drm_device *dev = crtc->dev;
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00007390 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007391 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007392 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007393
Jesse Barnes79e53942008-11-07 14:24:08 -08007394 /* if we want to turn off the cursor ignore width and height */
7395 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007396 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007397 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00007398 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10007399 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007400 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08007401 }
7402
7403 /* Currently we only support 64x64 cursors */
7404 if (width != 64 || height != 64) {
7405 DRM_ERROR("we currently only support 64x64 cursors\n");
7406 return -EINVAL;
7407 }
7408
Chris Wilson05394f32010-11-08 19:18:58 +00007409 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00007410 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08007411 return -ENOENT;
7412
Chris Wilson05394f32010-11-08 19:18:58 +00007413 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007414 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10007415 ret = -ENOMEM;
7416 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08007417 }
7418
Dave Airlie71acb5e2008-12-30 20:31:46 +10007419 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007420 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05007421 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00007422 unsigned alignment;
7423
Chris Wilsond9e86c02010-11-10 16:40:20 +00007424 if (obj->tiling_mode) {
7425 DRM_ERROR("cursor cannot be tiled\n");
7426 ret = -EINVAL;
7427 goto fail_locked;
7428 }
7429
Chris Wilson693db182013-03-05 14:52:39 +00007430 /* Note that the w/a also requires 2 PTE of padding following
7431 * the bo. We currently fill all unused PTE with the shadow
7432 * page and so we should always have valid PTE following the
7433 * cursor preventing the VT-d warning.
7434 */
7435 alignment = 0;
7436 if (need_vtd_wa(dev))
7437 alignment = 64*1024;
7438
7439 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01007440 if (ret) {
7441 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01007442 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01007443 }
7444
Chris Wilsond9e86c02010-11-10 16:40:20 +00007445 ret = i915_gem_object_put_fence(obj);
7446 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01007447 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00007448 goto fail_unpin;
7449 }
7450
Ben Widawskyf343c5f2013-07-05 14:41:04 -07007451 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10007452 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01007453 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00007454 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01007455 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7456 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10007457 if (ret) {
7458 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007459 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10007460 }
Chris Wilson05394f32010-11-08 19:18:58 +00007461 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007462 }
7463
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007464 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04007465 I915_WRITE(CURSIZE, (height << 12) | width);
7466
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007467 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007468 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05007469 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00007470 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10007471 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7472 } else
Chris Wilsoncc98b412013-08-09 12:25:09 +01007473 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00007474 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007475 }
Jesse Barnes80824002009-09-10 15:28:06 -07007476
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007477 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007478
7479 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00007480 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007481 intel_crtc->cursor_width = width;
7482 intel_crtc->cursor_height = height;
7483
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03007484 if (intel_crtc->active)
7485 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007486
Jesse Barnes79e53942008-11-07 14:24:08 -08007487 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01007488fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01007489 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007490fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10007491 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00007492fail:
Chris Wilson05394f32010-11-08 19:18:58 +00007493 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10007494 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007495}
7496
7497static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7498{
Jesse Barnes79e53942008-11-07 14:24:08 -08007499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007500
Ville Syrjälä92e76c82013-10-21 19:01:58 +03007501 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7502 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
Jesse Barnes652c3932009-08-17 13:31:43 -07007503
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03007504 if (intel_crtc->active)
7505 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08007506
7507 return 0;
7508}
7509
Jesse Barnes79e53942008-11-07 14:24:08 -08007510static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01007511 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08007512{
James Simmons72034252010-08-03 01:33:19 +01007513 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08007514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007515
James Simmons72034252010-08-03 01:33:19 +01007516 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007517 intel_crtc->lut_r[i] = red[i] >> 8;
7518 intel_crtc->lut_g[i] = green[i] >> 8;
7519 intel_crtc->lut_b[i] = blue[i] >> 8;
7520 }
7521
7522 intel_crtc_load_lut(crtc);
7523}
7524
Jesse Barnes79e53942008-11-07 14:24:08 -08007525/* VESA 640x480x72Hz mode to set on the pipe */
7526static struct drm_display_mode load_detect_mode = {
7527 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7528 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7529};
7530
Chris Wilsond2dff872011-04-19 08:36:26 +01007531static struct drm_framebuffer *
7532intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007533 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01007534 struct drm_i915_gem_object *obj)
7535{
7536 struct intel_framebuffer *intel_fb;
7537 int ret;
7538
7539 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7540 if (!intel_fb) {
7541 drm_gem_object_unreference_unlocked(&obj->base);
7542 return ERR_PTR(-ENOMEM);
7543 }
7544
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007545 ret = i915_mutex_lock_interruptible(dev);
7546 if (ret)
7547 goto err;
7548
Chris Wilsond2dff872011-04-19 08:36:26 +01007549 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007550 mutex_unlock(&dev->struct_mutex);
7551 if (ret)
7552 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01007553
7554 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007555err:
7556 drm_gem_object_unreference_unlocked(&obj->base);
7557 kfree(intel_fb);
7558
7559 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01007560}
7561
7562static u32
7563intel_framebuffer_pitch_for_width(int width, int bpp)
7564{
7565 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7566 return ALIGN(pitch, 64);
7567}
7568
7569static u32
7570intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7571{
7572 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7573 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7574}
7575
7576static struct drm_framebuffer *
7577intel_framebuffer_create_for_mode(struct drm_device *dev,
7578 struct drm_display_mode *mode,
7579 int depth, int bpp)
7580{
7581 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00007582 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01007583
7584 obj = i915_gem_alloc_object(dev,
7585 intel_framebuffer_size_for_mode(mode, bpp));
7586 if (obj == NULL)
7587 return ERR_PTR(-ENOMEM);
7588
7589 mode_cmd.width = mode->hdisplay;
7590 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007591 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7592 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00007593 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01007594
7595 return intel_framebuffer_create(dev, &mode_cmd, obj);
7596}
7597
7598static struct drm_framebuffer *
7599mode_fits_in_fbdev(struct drm_device *dev,
7600 struct drm_display_mode *mode)
7601{
Daniel Vetter4520f532013-10-09 09:18:51 +02007602#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01007603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 struct drm_i915_gem_object *obj;
7605 struct drm_framebuffer *fb;
7606
7607 if (dev_priv->fbdev == NULL)
7608 return NULL;
7609
7610 obj = dev_priv->fbdev->ifb.obj;
7611 if (obj == NULL)
7612 return NULL;
7613
7614 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007615 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7616 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01007617 return NULL;
7618
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007619 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01007620 return NULL;
7621
7622 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02007623#else
7624 return NULL;
7625#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01007626}
7627
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007628bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01007629 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01007630 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08007631{
7632 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007633 struct intel_encoder *intel_encoder =
7634 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08007635 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007636 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08007637 struct drm_crtc *crtc = NULL;
7638 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02007639 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08007640 int i = -1;
7641
Chris Wilsond2dff872011-04-19 08:36:26 +01007642 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7643 connector->base.id, drm_get_connector_name(connector),
7644 encoder->base.id, drm_get_encoder_name(encoder));
7645
Jesse Barnes79e53942008-11-07 14:24:08 -08007646 /*
7647 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01007648 *
Jesse Barnes79e53942008-11-07 14:24:08 -08007649 * - if the connector already has an assigned crtc, use it (but make
7650 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01007651 *
Jesse Barnes79e53942008-11-07 14:24:08 -08007652 * - try to find the first unused crtc that can drive this connector,
7653 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08007654 */
7655
7656 /* See if we already have a CRTC for this connector */
7657 if (encoder->crtc) {
7658 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01007659
Daniel Vetter7b240562012-12-12 00:35:33 +01007660 mutex_lock(&crtc->mutex);
7661
Daniel Vetter24218aa2012-08-12 19:27:11 +02007662 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01007663 old->load_detect_temp = false;
7664
7665 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02007666 if (connector->dpms != DRM_MODE_DPMS_ON)
7667 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01007668
Chris Wilson71731882011-04-19 23:10:58 +01007669 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08007670 }
7671
7672 /* Find an unused one (if possible) */
7673 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7674 i++;
7675 if (!(encoder->possible_crtcs & (1 << i)))
7676 continue;
7677 if (!possible_crtc->enabled) {
7678 crtc = possible_crtc;
7679 break;
7680 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007681 }
7682
7683 /*
7684 * If we didn't find an unused CRTC, don't use any.
7685 */
7686 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01007687 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7688 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007689 }
7690
Daniel Vetter7b240562012-12-12 00:35:33 +01007691 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02007692 intel_encoder->new_crtc = to_intel_crtc(crtc);
7693 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007694
7695 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02007696 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01007697 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01007698 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08007699
Chris Wilson64927112011-04-20 07:25:26 +01007700 if (!mode)
7701 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08007702
Chris Wilsond2dff872011-04-19 08:36:26 +01007703 /* We need a framebuffer large enough to accommodate all accesses
7704 * that the plane may generate whilst we perform load detection.
7705 * We can not rely on the fbcon either being present (we get called
7706 * during its initialisation to detect all boot displays, or it may
7707 * not even exist) or that it is large enough to satisfy the
7708 * requested mode.
7709 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02007710 fb = mode_fits_in_fbdev(dev, mode);
7711 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01007712 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02007713 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7714 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01007715 } else
7716 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02007717 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01007718 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter7b240562012-12-12 00:35:33 +01007719 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00007720 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007721 }
Chris Wilsond2dff872011-04-19 08:36:26 +01007722
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007723 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01007724 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01007725 if (old->release_fb)
7726 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter7b240562012-12-12 00:35:33 +01007727 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00007728 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007729 }
Chris Wilson71731882011-04-19 23:10:58 +01007730
Jesse Barnes79e53942008-11-07 14:24:08 -08007731 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007732 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01007733 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08007734}
7735
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007736void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01007737 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08007738{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007739 struct intel_encoder *intel_encoder =
7740 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01007741 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01007742 struct drm_crtc *crtc = encoder->crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -08007743
Chris Wilsond2dff872011-04-19 08:36:26 +01007744 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7745 connector->base.id, drm_get_connector_name(connector),
7746 encoder->base.id, drm_get_encoder_name(encoder));
7747
Chris Wilson8261b192011-04-19 23:18:09 +01007748 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02007749 to_intel_connector(connector)->new_encoder = NULL;
7750 intel_encoder->new_crtc = NULL;
7751 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01007752
Daniel Vetter36206362012-12-10 20:42:17 +01007753 if (old->release_fb) {
7754 drm_framebuffer_unregister_private(old->release_fb);
7755 drm_framebuffer_unreference(old->release_fb);
7756 }
Chris Wilsond2dff872011-04-19 08:36:26 +01007757
Daniel Vetter67c96402013-01-23 16:25:09 +00007758 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01007759 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08007760 }
7761
Eric Anholtc751ce42010-03-25 11:48:48 -07007762 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02007763 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7764 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01007765
7766 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08007767}
7768
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007769static int i9xx_pll_refclk(struct drm_device *dev,
7770 const struct intel_crtc_config *pipe_config)
7771{
7772 struct drm_i915_private *dev_priv = dev->dev_private;
7773 u32 dpll = pipe_config->dpll_hw_state.dpll;
7774
7775 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7776 return dev_priv->vbt.lvds_ssc_freq * 1000;
7777 else if (HAS_PCH_SPLIT(dev))
7778 return 120000;
7779 else if (!IS_GEN2(dev))
7780 return 96000;
7781 else
7782 return 48000;
7783}
7784
Jesse Barnes79e53942008-11-07 14:24:08 -08007785/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007786static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7787 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08007788{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007789 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007790 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007791 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03007792 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007793 u32 fp;
7794 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007795 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08007796
7797 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03007798 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007799 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03007800 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08007801
7802 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007803 if (IS_PINEVIEW(dev)) {
7804 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7805 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08007806 } else {
7807 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7808 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7809 }
7810
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007811 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007812 if (IS_PINEVIEW(dev))
7813 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7814 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08007815 else
7816 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08007817 DPLL_FPA01_P1_POST_DIV_SHIFT);
7818
7819 switch (dpll & DPLL_MODE_MASK) {
7820 case DPLLB_MODE_DAC_SERIAL:
7821 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7822 5 : 10;
7823 break;
7824 case DPLLB_MODE_LVDS:
7825 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7826 7 : 14;
7827 break;
7828 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08007829 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08007830 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007831 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08007832 }
7833
Daniel Vetterac58c3f2013-06-01 17:16:17 +02007834 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007835 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02007836 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007837 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08007838 } else {
7839 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7840
7841 if (is_lvds) {
7842 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7843 DPLL_FPA01_P1_POST_DIV_SHIFT);
7844 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08007845 } else {
7846 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7847 clock.p1 = 2;
7848 else {
7849 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7850 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7851 }
7852 if (dpll & PLL_P2_DIVIDE_BY_4)
7853 clock.p2 = 4;
7854 else
7855 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08007856 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007857
7858 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08007859 }
7860
Ville Syrjälä18442d02013-09-13 16:00:08 +03007861 /*
7862 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01007863 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03007864 * encoder's get_config() function.
7865 */
7866 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007867}
7868
Ville Syrjälä6878da02013-09-13 15:59:11 +03007869int intel_dotclock_calculate(int link_freq,
7870 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007871{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007872 /*
7873 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03007874 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007875 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03007876 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007877 *
7878 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03007879 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08007880 */
7881
Ville Syrjälä6878da02013-09-13 15:59:11 +03007882 if (!m_n->link_n)
7883 return 0;
7884
7885 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7886}
7887
Ville Syrjälä18442d02013-09-13 16:00:08 +03007888static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7889 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03007890{
7891 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03007892
7893 /* read out port_clock from the DPLL */
7894 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03007895
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007896 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03007897 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01007898 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03007899 * agree once we know their relationship in the encoder's
7900 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007901 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01007902 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03007903 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7904 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08007905}
7906
7907/** Returns the currently programmed mode of the given pipe. */
7908struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7909 struct drm_crtc *crtc)
7910{
Jesse Barnes548f2452011-02-17 10:40:53 -08007911 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02007913 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007914 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007915 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02007916 int htot = I915_READ(HTOTAL(cpu_transcoder));
7917 int hsync = I915_READ(HSYNC(cpu_transcoder));
7918 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7919 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03007920 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08007921
7922 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7923 if (!mode)
7924 return NULL;
7925
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007926 /*
7927 * Construct a pipe_config sufficient for getting the clock info
7928 * back out of crtc_clock_get.
7929 *
7930 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7931 * to use a real value here instead.
7932 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03007933 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007934 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03007935 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7936 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7937 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007938 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7939
Ville Syrjälä773ae032013-09-23 17:48:20 +03007940 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08007941 mode->hdisplay = (htot & 0xffff) + 1;
7942 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7943 mode->hsync_start = (hsync & 0xffff) + 1;
7944 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7945 mode->vdisplay = (vtot & 0xffff) + 1;
7946 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7947 mode->vsync_start = (vsync & 0xffff) + 1;
7948 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7949
7950 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08007951
7952 return mode;
7953}
7954
Daniel Vetter3dec0092010-08-20 21:40:52 +02007955static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07007956{
7957 struct drm_device *dev = crtc->dev;
7958 drm_i915_private_t *dev_priv = dev->dev_private;
7959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7960 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007961 int dpll_reg = DPLL(pipe);
7962 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07007963
Eric Anholtbad720f2009-10-22 16:11:14 -07007964 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007965 return;
7966
7967 if (!dev_priv->lvds_downclock_avail)
7968 return;
7969
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007970 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07007971 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08007972 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007973
Sean Paul8ac5a6d2012-02-13 13:14:51 -05007974 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007975
7976 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7977 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007978 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08007979
Jesse Barnes652c3932009-08-17 13:31:43 -07007980 dpll = I915_READ(dpll_reg);
7981 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08007982 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007983 }
Jesse Barnes652c3932009-08-17 13:31:43 -07007984}
7985
7986static void intel_decrease_pllclock(struct drm_crtc *crtc)
7987{
7988 struct drm_device *dev = crtc->dev;
7989 drm_i915_private_t *dev_priv = dev->dev_private;
7990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007991
Eric Anholtbad720f2009-10-22 16:11:14 -07007992 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007993 return;
7994
7995 if (!dev_priv->lvds_downclock_avail)
7996 return;
7997
7998 /*
7999 * Since this is called by a timer, we should never get here in
8000 * the manual case.
8001 */
8002 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008003 int pipe = intel_crtc->pipe;
8004 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008005 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008006
Zhao Yakui44d98a62009-10-09 11:39:40 +08008007 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008008
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008009 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008010
Chris Wilson074b5e12012-05-02 12:07:06 +01008011 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008012 dpll |= DISPLAY_RATE_SELECT_FPA1;
8013 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008014 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008015 dpll = I915_READ(dpll_reg);
8016 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008017 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008018 }
8019
8020}
8021
Chris Wilsonf047e392012-07-21 12:31:41 +01008022void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008023{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008024 struct drm_i915_private *dev_priv = dev->dev_private;
8025
8026 hsw_package_c8_gpu_busy(dev_priv);
8027 i915_update_gfx_val(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008028}
8029
8030void intel_mark_idle(struct drm_device *dev)
8031{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008032 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008033 struct drm_crtc *crtc;
8034
Paulo Zanonic67a4702013-08-19 13:18:09 -03008035 hsw_package_c8_gpu_idle(dev_priv);
8036
Chris Wilson725a5b52013-01-08 11:02:57 +00008037 if (!i915_powersave)
8038 return;
8039
8040 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8041 if (!crtc->fb)
8042 continue;
8043
8044 intel_decrease_pllclock(crtc);
8045 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008046
8047 if (dev_priv->info->gen >= 6)
8048 gen6_rps_idle(dev->dev_private);
Chris Wilsonf047e392012-07-21 12:31:41 +01008049}
8050
Chris Wilsonc65355b2013-06-06 16:53:41 -03008051void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8052 struct intel_ring_buffer *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008053{
8054 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07008055 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07008056
8057 if (!i915_powersave)
8058 return;
8059
Jesse Barnes652c3932009-08-17 13:31:43 -07008060 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07008061 if (!crtc->fb)
8062 continue;
8063
Chris Wilsonc65355b2013-06-06 16:53:41 -03008064 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8065 continue;
8066
8067 intel_increase_pllclock(crtc);
8068 if (ring && intel_fbc_enabled(dev))
8069 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008070 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008071}
8072
Jesse Barnes79e53942008-11-07 14:24:08 -08008073static void intel_crtc_destroy(struct drm_crtc *crtc)
8074{
8075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008076 struct drm_device *dev = crtc->dev;
8077 struct intel_unpin_work *work;
8078 unsigned long flags;
8079
8080 spin_lock_irqsave(&dev->event_lock, flags);
8081 work = intel_crtc->unpin_work;
8082 intel_crtc->unpin_work = NULL;
8083 spin_unlock_irqrestore(&dev->event_lock, flags);
8084
8085 if (work) {
8086 cancel_work_sync(&work->work);
8087 kfree(work);
8088 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008089
Mika Kuoppala40ccc722013-04-23 17:27:08 +03008090 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8091
Jesse Barnes79e53942008-11-07 14:24:08 -08008092 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008093
Jesse Barnes79e53942008-11-07 14:24:08 -08008094 kfree(intel_crtc);
8095}
8096
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008097static void intel_unpin_work_fn(struct work_struct *__work)
8098{
8099 struct intel_unpin_work *work =
8100 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008101 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008102
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008103 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008104 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008105 drm_gem_object_unreference(&work->pending_flip_obj->base);
8106 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008107
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008108 intel_update_fbc(dev);
8109 mutex_unlock(&dev->struct_mutex);
8110
8111 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8112 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8113
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008114 kfree(work);
8115}
8116
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008117static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01008118 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008119{
8120 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8122 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008123 unsigned long flags;
8124
8125 /* Ignore early vblank irqs */
8126 if (intel_crtc == NULL)
8127 return;
8128
8129 spin_lock_irqsave(&dev->event_lock, flags);
8130 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00008131
8132 /* Ensure we don't miss a work->pending update ... */
8133 smp_rmb();
8134
8135 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008136 spin_unlock_irqrestore(&dev->event_lock, flags);
8137 return;
8138 }
8139
Chris Wilsone7d841c2012-12-03 11:36:30 +00008140 /* and that the unpin work is consistent wrt ->pending. */
8141 smp_rmb();
8142
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008143 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008144
Rob Clark45a066e2012-10-08 14:50:40 -05008145 if (work->event)
8146 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008147
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01008148 drm_vblank_put(dev, intel_crtc->pipe);
8149
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008150 spin_unlock_irqrestore(&dev->event_lock, flags);
8151
Daniel Vetter2c10d572012-12-20 21:24:07 +01008152 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008153
8154 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07008155
8156 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008157}
8158
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008159void intel_finish_page_flip(struct drm_device *dev, int pipe)
8160{
8161 drm_i915_private_t *dev_priv = dev->dev_private;
8162 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8163
Mario Kleiner49b14a52010-12-09 07:00:07 +01008164 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008165}
8166
8167void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8168{
8169 drm_i915_private_t *dev_priv = dev->dev_private;
8170 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8171
Mario Kleiner49b14a52010-12-09 07:00:07 +01008172 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008173}
8174
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008175void intel_prepare_page_flip(struct drm_device *dev, int plane)
8176{
8177 drm_i915_private_t *dev_priv = dev->dev_private;
8178 struct intel_crtc *intel_crtc =
8179 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8180 unsigned long flags;
8181
Chris Wilsone7d841c2012-12-03 11:36:30 +00008182 /* NB: An MMIO update of the plane base pointer will also
8183 * generate a page-flip completion irq, i.e. every modeset
8184 * is also accompanied by a spurious intel_prepare_page_flip().
8185 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008186 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008187 if (intel_crtc->unpin_work)
8188 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008189 spin_unlock_irqrestore(&dev->event_lock, flags);
8190}
8191
Chris Wilsone7d841c2012-12-03 11:36:30 +00008192inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8193{
8194 /* Ensure that the work item is consistent when activating it ... */
8195 smp_wmb();
8196 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8197 /* and that it is marked active as soon as the irq could fire. */
8198 smp_wmb();
8199}
8200
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008201static int intel_gen2_queue_flip(struct drm_device *dev,
8202 struct drm_crtc *crtc,
8203 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008204 struct drm_i915_gem_object *obj,
8205 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008206{
8207 struct drm_i915_private *dev_priv = dev->dev_private;
8208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008209 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008210 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008211 int ret;
8212
Daniel Vetter6d90c952012-04-26 23:28:05 +02008213 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008214 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008215 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008216
Daniel Vetter6d90c952012-04-26 23:28:05 +02008217 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008218 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008219 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008220
8221 /* Can't queue multiple flips, so wait for the previous
8222 * one to finish before executing the next.
8223 */
8224 if (intel_crtc->plane)
8225 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8226 else
8227 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008228 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8229 intel_ring_emit(ring, MI_NOOP);
8230 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8231 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8232 intel_ring_emit(ring, fb->pitches[0]);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008233 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008234 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00008235
8236 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008237 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008238 return 0;
8239
8240err_unpin:
8241 intel_unpin_fb_obj(obj);
8242err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008243 return ret;
8244}
8245
8246static int intel_gen3_queue_flip(struct drm_device *dev,
8247 struct drm_crtc *crtc,
8248 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008249 struct drm_i915_gem_object *obj,
8250 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008251{
8252 struct drm_i915_private *dev_priv = dev->dev_private;
8253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008254 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008255 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008256 int ret;
8257
Daniel Vetter6d90c952012-04-26 23:28:05 +02008258 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008259 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008260 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008261
Daniel Vetter6d90c952012-04-26 23:28:05 +02008262 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008263 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008264 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008265
8266 if (intel_crtc->plane)
8267 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8268 else
8269 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008270 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8271 intel_ring_emit(ring, MI_NOOP);
8272 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8273 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8274 intel_ring_emit(ring, fb->pitches[0]);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008275 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008276 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008277
Chris Wilsone7d841c2012-12-03 11:36:30 +00008278 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008279 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008280 return 0;
8281
8282err_unpin:
8283 intel_unpin_fb_obj(obj);
8284err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008285 return ret;
8286}
8287
8288static int intel_gen4_queue_flip(struct drm_device *dev,
8289 struct drm_crtc *crtc,
8290 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008291 struct drm_i915_gem_object *obj,
8292 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008293{
8294 struct drm_i915_private *dev_priv = dev->dev_private;
8295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8296 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008297 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008298 int ret;
8299
Daniel Vetter6d90c952012-04-26 23:28:05 +02008300 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008301 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008302 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008303
Daniel Vetter6d90c952012-04-26 23:28:05 +02008304 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008305 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008306 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008307
8308 /* i965+ uses the linear or tiled offsets from the
8309 * Display Registers (which do not change across a page-flip)
8310 * so we need only reprogram the base address.
8311 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02008312 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8313 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8314 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02008315 intel_ring_emit(ring,
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008316 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
Daniel Vetterc2c75132012-07-05 12:17:30 +02008317 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008318
8319 /* XXX Enabling the panel-fitter across page-flip is so far
8320 * untested on non-native modes, so ignore it for now.
8321 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8322 */
8323 pf = 0;
8324 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008325 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008326
8327 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008328 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008329 return 0;
8330
8331err_unpin:
8332 intel_unpin_fb_obj(obj);
8333err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008334 return ret;
8335}
8336
8337static int intel_gen6_queue_flip(struct drm_device *dev,
8338 struct drm_crtc *crtc,
8339 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008340 struct drm_i915_gem_object *obj,
8341 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008342{
8343 struct drm_i915_private *dev_priv = dev->dev_private;
8344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008345 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008346 uint32_t pf, pipesrc;
8347 int ret;
8348
Daniel Vetter6d90c952012-04-26 23:28:05 +02008349 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008350 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008351 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008352
Daniel Vetter6d90c952012-04-26 23:28:05 +02008353 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008354 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008355 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008356
Daniel Vetter6d90c952012-04-26 23:28:05 +02008357 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8358 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8359 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008360 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008361
Chris Wilson99d9acd2012-04-17 20:37:00 +01008362 /* Contrary to the suggestions in the documentation,
8363 * "Enable Panel Fitter" does not seem to be required when page
8364 * flipping with a non-native mode, and worse causes a normal
8365 * modeset to fail.
8366 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8367 */
8368 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008369 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008370 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008371
8372 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008373 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008374 return 0;
8375
8376err_unpin:
8377 intel_unpin_fb_obj(obj);
8378err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008379 return ret;
8380}
8381
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008382static int intel_gen7_queue_flip(struct drm_device *dev,
8383 struct drm_crtc *crtc,
8384 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008385 struct drm_i915_gem_object *obj,
8386 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008387{
8388 struct drm_i915_private *dev_priv = dev->dev_private;
8389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilsonffe74d72013-08-26 20:58:12 +01008390 struct intel_ring_buffer *ring;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008391 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01008392 int len, ret;
8393
8394 ring = obj->ring;
Chris Wilson1c5fd082013-09-04 10:54:30 +01008395 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
Chris Wilsonffe74d72013-08-26 20:58:12 +01008396 ring = &dev_priv->ring[BCS];
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008397
8398 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8399 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008400 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008401
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008402 switch(intel_crtc->plane) {
8403 case PLANE_A:
8404 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8405 break;
8406 case PLANE_B:
8407 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8408 break;
8409 case PLANE_C:
8410 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8411 break;
8412 default:
8413 WARN_ONCE(1, "unknown plane in flip command\n");
8414 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03008415 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008416 }
8417
Chris Wilsonffe74d72013-08-26 20:58:12 +01008418 len = 4;
8419 if (ring->id == RCS)
8420 len += 6;
8421
8422 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008423 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008424 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008425
Chris Wilsonffe74d72013-08-26 20:58:12 +01008426 /* Unmask the flip-done completion message. Note that the bspec says that
8427 * we should do this for both the BCS and RCS, and that we must not unmask
8428 * more than one flip event at any time (or ensure that one flip message
8429 * can be sent by waiting for flip-done prior to queueing new flips).
8430 * Experimentation says that BCS works despite DERRMR masking all
8431 * flip-done completion events and that unmasking all planes at once
8432 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8433 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8434 */
8435 if (ring->id == RCS) {
8436 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8437 intel_ring_emit(ring, DERRMR);
8438 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8439 DERRMR_PIPEB_PRI_FLIP_DONE |
8440 DERRMR_PIPEC_PRI_FLIP_DONE));
8441 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8442 intel_ring_emit(ring, DERRMR);
8443 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8444 }
8445
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008446 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008447 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008448 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008449 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00008450
8451 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008452 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008453 return 0;
8454
8455err_unpin:
8456 intel_unpin_fb_obj(obj);
8457err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008458 return ret;
8459}
8460
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008461static int intel_default_queue_flip(struct drm_device *dev,
8462 struct drm_crtc *crtc,
8463 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008464 struct drm_i915_gem_object *obj,
8465 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008466{
8467 return -ENODEV;
8468}
8469
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008470static int intel_crtc_page_flip(struct drm_crtc *crtc,
8471 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008472 struct drm_pending_vblank_event *event,
8473 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008474{
8475 struct drm_device *dev = crtc->dev;
8476 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008477 struct drm_framebuffer *old_fb = crtc->fb;
8478 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8480 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008481 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01008482 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008483
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03008484 /* Can't change pixel format via MI display flips. */
8485 if (fb->pixel_format != crtc->fb->pixel_format)
8486 return -EINVAL;
8487
8488 /*
8489 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8490 * Note that pitch changes could also affect these register.
8491 */
8492 if (INTEL_INFO(dev)->gen > 3 &&
8493 (fb->offsets[0] != crtc->fb->offsets[0] ||
8494 fb->pitches[0] != crtc->fb->pitches[0]))
8495 return -EINVAL;
8496
Daniel Vetterb14c5672013-09-19 12:18:32 +02008497 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008498 if (work == NULL)
8499 return -ENOMEM;
8500
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008501 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008502 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008503 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008504 INIT_WORK(&work->work, intel_unpin_work_fn);
8505
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008506 ret = drm_vblank_get(dev, intel_crtc->pipe);
8507 if (ret)
8508 goto free_work;
8509
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008510 /* We borrow the event spin lock for protecting unpin_work */
8511 spin_lock_irqsave(&dev->event_lock, flags);
8512 if (intel_crtc->unpin_work) {
8513 spin_unlock_irqrestore(&dev->event_lock, flags);
8514 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008515 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01008516
8517 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008518 return -EBUSY;
8519 }
8520 intel_crtc->unpin_work = work;
8521 spin_unlock_irqrestore(&dev->event_lock, flags);
8522
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008523 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8524 flush_workqueue(dev_priv->wq);
8525
Chris Wilson79158102012-05-23 11:13:58 +01008526 ret = i915_mutex_lock_interruptible(dev);
8527 if (ret)
8528 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008529
Jesse Barnes75dfca82010-02-10 15:09:44 -08008530 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00008531 drm_gem_object_reference(&work->old_fb_obj->base);
8532 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008533
8534 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01008535
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008536 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008537
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01008538 work->enable_stall_check = true;
8539
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008540 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02008541 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008542
Keith Packarded8d1972013-07-22 18:49:58 -07008543 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008544 if (ret)
8545 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008546
Chris Wilson7782de32011-07-08 12:22:41 +01008547 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03008548 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008549 mutex_unlock(&dev->struct_mutex);
8550
Jesse Barnese5510fa2010-07-01 16:48:37 -07008551 trace_i915_flip_request(intel_crtc->plane, obj);
8552
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008553 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01008554
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008555cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008556 atomic_dec(&intel_crtc->unpin_work_count);
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008557 crtc->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00008558 drm_gem_object_unreference(&work->old_fb_obj->base);
8559 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01008560 mutex_unlock(&dev->struct_mutex);
8561
Chris Wilson79158102012-05-23 11:13:58 +01008562cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01008563 spin_lock_irqsave(&dev->event_lock, flags);
8564 intel_crtc->unpin_work = NULL;
8565 spin_unlock_irqrestore(&dev->event_lock, flags);
8566
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008567 drm_vblank_put(dev, intel_crtc->pipe);
8568free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01008569 kfree(work);
8570
8571 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008572}
8573
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008574static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008575 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8576 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008577};
8578
Daniel Vetter50f56112012-07-02 09:35:43 +02008579static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8580 struct drm_crtc *crtc)
8581{
8582 struct drm_device *dev;
8583 struct drm_crtc *tmp;
8584 int crtc_mask = 1;
8585
8586 WARN(!crtc, "checking null crtc?\n");
8587
8588 dev = crtc->dev;
8589
8590 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8591 if (tmp == crtc)
8592 break;
8593 crtc_mask <<= 1;
8594 }
8595
8596 if (encoder->possible_crtcs & crtc_mask)
8597 return true;
8598 return false;
8599}
8600
Daniel Vetter9a935852012-07-05 22:34:27 +02008601/**
8602 * intel_modeset_update_staged_output_state
8603 *
8604 * Updates the staged output configuration state, e.g. after we've read out the
8605 * current hw state.
8606 */
8607static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8608{
8609 struct intel_encoder *encoder;
8610 struct intel_connector *connector;
8611
8612 list_for_each_entry(connector, &dev->mode_config.connector_list,
8613 base.head) {
8614 connector->new_encoder =
8615 to_intel_encoder(connector->base.encoder);
8616 }
8617
8618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8619 base.head) {
8620 encoder->new_crtc =
8621 to_intel_crtc(encoder->base.crtc);
8622 }
8623}
8624
8625/**
8626 * intel_modeset_commit_output_state
8627 *
8628 * This function copies the stage display pipe configuration to the real one.
8629 */
8630static void intel_modeset_commit_output_state(struct drm_device *dev)
8631{
8632 struct intel_encoder *encoder;
8633 struct intel_connector *connector;
8634
8635 list_for_each_entry(connector, &dev->mode_config.connector_list,
8636 base.head) {
8637 connector->base.encoder = &connector->new_encoder->base;
8638 }
8639
8640 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8641 base.head) {
8642 encoder->base.crtc = &encoder->new_crtc->base;
8643 }
8644}
8645
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008646static void
8647connected_sink_compute_bpp(struct intel_connector * connector,
8648 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008649{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008650 int bpp = pipe_config->pipe_bpp;
8651
8652 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8653 connector->base.base.id,
8654 drm_get_connector_name(&connector->base));
8655
8656 /* Don't use an invalid EDID bpc value */
8657 if (connector->base.display_info.bpc &&
8658 connector->base.display_info.bpc * 3 < bpp) {
8659 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8660 bpp, connector->base.display_info.bpc*3);
8661 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8662 }
8663
8664 /* Clamp bpp to 8 on screens without EDID 1.4 */
8665 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8666 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8667 bpp);
8668 pipe_config->pipe_bpp = 24;
8669 }
8670}
8671
8672static int
8673compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8674 struct drm_framebuffer *fb,
8675 struct intel_crtc_config *pipe_config)
8676{
8677 struct drm_device *dev = crtc->base.dev;
8678 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008679 int bpp;
8680
Daniel Vetterd42264b2013-03-28 16:38:08 +01008681 switch (fb->pixel_format) {
8682 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008683 bpp = 8*3; /* since we go through a colormap */
8684 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008685 case DRM_FORMAT_XRGB1555:
8686 case DRM_FORMAT_ARGB1555:
8687 /* checked in intel_framebuffer_init already */
8688 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8689 return -EINVAL;
8690 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008691 bpp = 6*3; /* min is 18bpp */
8692 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008693 case DRM_FORMAT_XBGR8888:
8694 case DRM_FORMAT_ABGR8888:
8695 /* checked in intel_framebuffer_init already */
8696 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8697 return -EINVAL;
8698 case DRM_FORMAT_XRGB8888:
8699 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008700 bpp = 8*3;
8701 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008702 case DRM_FORMAT_XRGB2101010:
8703 case DRM_FORMAT_ARGB2101010:
8704 case DRM_FORMAT_XBGR2101010:
8705 case DRM_FORMAT_ABGR2101010:
8706 /* checked in intel_framebuffer_init already */
8707 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01008708 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008709 bpp = 10*3;
8710 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01008711 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008712 default:
8713 DRM_DEBUG_KMS("unsupported depth\n");
8714 return -EINVAL;
8715 }
8716
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008717 pipe_config->pipe_bpp = bpp;
8718
8719 /* Clamp display bpp to EDID value */
8720 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008721 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02008722 if (!connector->new_encoder ||
8723 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008724 continue;
8725
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008726 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008727 }
8728
8729 return bpp;
8730}
8731
Daniel Vetter644db712013-09-19 14:53:58 +02008732static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8733{
8734 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8735 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01008736 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02008737 mode->crtc_hdisplay, mode->crtc_hsync_start,
8738 mode->crtc_hsync_end, mode->crtc_htotal,
8739 mode->crtc_vdisplay, mode->crtc_vsync_start,
8740 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8741}
8742
Daniel Vetterc0b03412013-05-28 12:05:54 +02008743static void intel_dump_pipe_config(struct intel_crtc *crtc,
8744 struct intel_crtc_config *pipe_config,
8745 const char *context)
8746{
8747 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8748 context, pipe_name(crtc->pipe));
8749
8750 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8751 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8752 pipe_config->pipe_bpp, pipe_config->dither);
8753 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8754 pipe_config->has_pch_encoder,
8755 pipe_config->fdi_lanes,
8756 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8757 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8758 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008759 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8760 pipe_config->has_dp_encoder,
8761 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8762 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8763 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008764 DRM_DEBUG_KMS("requested mode:\n");
8765 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8766 DRM_DEBUG_KMS("adjusted mode:\n");
8767 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02008768 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03008769 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03008770 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8771 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008772 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8773 pipe_config->gmch_pfit.control,
8774 pipe_config->gmch_pfit.pgm_ratios,
8775 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01008776 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02008777 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01008778 pipe_config->pch_pfit.size,
8779 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008780 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03008781 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008782}
8783
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02008784static bool check_encoder_cloning(struct drm_crtc *crtc)
8785{
8786 int num_encoders = 0;
8787 bool uncloneable_encoders = false;
8788 struct intel_encoder *encoder;
8789
8790 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8791 base.head) {
8792 if (&encoder->new_crtc->base != crtc)
8793 continue;
8794
8795 num_encoders++;
8796 if (!encoder->cloneable)
8797 uncloneable_encoders = true;
8798 }
8799
8800 return !(num_encoders > 1 && uncloneable_encoders);
8801}
8802
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008803static struct intel_crtc_config *
8804intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008805 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008806 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02008807{
8808 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02008809 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008810 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01008811 int plane_bpp, ret = -EINVAL;
8812 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02008813
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02008814 if (!check_encoder_cloning(crtc)) {
8815 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8816 return ERR_PTR(-EINVAL);
8817 }
8818
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008819 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8820 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02008821 return ERR_PTR(-ENOMEM);
8822
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008823 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8824 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03008825
Daniel Vettere143a212013-07-04 12:01:15 +02008826 pipe_config->cpu_transcoder =
8827 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008828 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008829
Imre Deak2960bc92013-07-30 13:36:32 +03008830 /*
8831 * Sanitize sync polarity flags based on requested ones. If neither
8832 * positive or negative polarity is requested, treat this as meaning
8833 * negative polarity.
8834 */
8835 if (!(pipe_config->adjusted_mode.flags &
8836 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8837 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8838
8839 if (!(pipe_config->adjusted_mode.flags &
8840 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8841 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8842
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008843 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8844 * plane pixel format and any sink constraints into account. Returns the
8845 * source plane bpp so that dithering can be selected on mismatches
8846 * after encoders and crtc also have had their say. */
8847 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8848 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008849 if (plane_bpp < 0)
8850 goto fail;
8851
Ville Syrjäläe41a56b2013-10-01 22:52:14 +03008852 /*
8853 * Determine the real pipe dimensions. Note that stereo modes can
8854 * increase the actual pipe size due to the frame doubling and
8855 * insertion of additional space for blanks between the frame. This
8856 * is stored in the crtc timings. We use the requested mode to do this
8857 * computation to clearly distinguish it from the adjusted mode, which
8858 * can be changed by the connectors in the below retry loop.
8859 */
8860 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8861 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8862 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8863
Daniel Vettere29c22c2013-02-21 00:00:16 +01008864encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02008865 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02008866 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02008867 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02008868
Daniel Vetter135c81b2013-07-21 21:37:09 +02008869 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +01008870 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +02008871
Daniel Vetter7758a112012-07-08 19:40:39 +02008872 /* Pass our mode to the connectors and the CRTC to give them a chance to
8873 * adjust it according to limitations or connector properties, and also
8874 * a chance to reject the mode entirely.
8875 */
8876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8877 base.head) {
8878
8879 if (&encoder->new_crtc->base != crtc)
8880 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01008881
Daniel Vetterefea6e82013-07-21 21:36:59 +02008882 if (!(encoder->compute_config(encoder, pipe_config))) {
8883 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +02008884 goto fail;
8885 }
8886 }
8887
Daniel Vetterff9a6752013-06-01 17:16:21 +02008888 /* Set default port clock if not overwritten by the encoder. Needs to be
8889 * done afterwards in case the encoder adjusts the mode. */
8890 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +01008891 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8892 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +02008893
Daniel Vettera43f6e02013-06-07 23:10:32 +02008894 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01008895 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02008896 DRM_DEBUG_KMS("CRTC fixup failed\n");
8897 goto fail;
8898 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01008899
8900 if (ret == RETRY) {
8901 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8902 ret = -EINVAL;
8903 goto fail;
8904 }
8905
8906 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8907 retry = false;
8908 goto encoder_retry;
8909 }
8910
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008911 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8912 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8913 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8914
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008915 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02008916fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008917 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01008918 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02008919}
8920
Daniel Vettere2e1ed42012-07-08 21:14:38 +02008921/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8922 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8923static void
8924intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8925 unsigned *prepare_pipes, unsigned *disable_pipes)
8926{
8927 struct intel_crtc *intel_crtc;
8928 struct drm_device *dev = crtc->dev;
8929 struct intel_encoder *encoder;
8930 struct intel_connector *connector;
8931 struct drm_crtc *tmp_crtc;
8932
8933 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8934
8935 /* Check which crtcs have changed outputs connected to them, these need
8936 * to be part of the prepare_pipes mask. We don't (yet) support global
8937 * modeset across multiple crtcs, so modeset_pipes will only have one
8938 * bit set at most. */
8939 list_for_each_entry(connector, &dev->mode_config.connector_list,
8940 base.head) {
8941 if (connector->base.encoder == &connector->new_encoder->base)
8942 continue;
8943
8944 if (connector->base.encoder) {
8945 tmp_crtc = connector->base.encoder->crtc;
8946
8947 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8948 }
8949
8950 if (connector->new_encoder)
8951 *prepare_pipes |=
8952 1 << connector->new_encoder->new_crtc->pipe;
8953 }
8954
8955 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8956 base.head) {
8957 if (encoder->base.crtc == &encoder->new_crtc->base)
8958 continue;
8959
8960 if (encoder->base.crtc) {
8961 tmp_crtc = encoder->base.crtc;
8962
8963 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8964 }
8965
8966 if (encoder->new_crtc)
8967 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8968 }
8969
8970 /* Check for any pipes that will be fully disabled ... */
8971 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8972 base.head) {
8973 bool used = false;
8974
8975 /* Don't try to disable disabled crtcs. */
8976 if (!intel_crtc->base.enabled)
8977 continue;
8978
8979 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8980 base.head) {
8981 if (encoder->new_crtc == intel_crtc)
8982 used = true;
8983 }
8984
8985 if (!used)
8986 *disable_pipes |= 1 << intel_crtc->pipe;
8987 }
8988
8989
8990 /* set_mode is also used to update properties on life display pipes. */
8991 intel_crtc = to_intel_crtc(crtc);
8992 if (crtc->enabled)
8993 *prepare_pipes |= 1 << intel_crtc->pipe;
8994
Daniel Vetterb6c51642013-04-12 18:48:43 +02008995 /*
8996 * For simplicity do a full modeset on any pipe where the output routing
8997 * changed. We could be more clever, but that would require us to be
8998 * more careful with calling the relevant encoder->mode_set functions.
8999 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009000 if (*prepare_pipes)
9001 *modeset_pipes = *prepare_pipes;
9002
9003 /* ... and mask these out. */
9004 *modeset_pipes &= ~(*disable_pipes);
9005 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02009006
9007 /*
9008 * HACK: We don't (yet) fully support global modesets. intel_set_config
9009 * obies this rule, but the modeset restore mode of
9010 * intel_modeset_setup_hw_state does not.
9011 */
9012 *modeset_pipes &= 1 << intel_crtc->pipe;
9013 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02009014
9015 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9016 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009017}
9018
Daniel Vetterea9d7582012-07-10 10:42:52 +02009019static bool intel_crtc_in_use(struct drm_crtc *crtc)
9020{
9021 struct drm_encoder *encoder;
9022 struct drm_device *dev = crtc->dev;
9023
9024 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9025 if (encoder->crtc == crtc)
9026 return true;
9027
9028 return false;
9029}
9030
9031static void
9032intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9033{
9034 struct intel_encoder *intel_encoder;
9035 struct intel_crtc *intel_crtc;
9036 struct drm_connector *connector;
9037
9038 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9039 base.head) {
9040 if (!intel_encoder->base.crtc)
9041 continue;
9042
9043 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9044
9045 if (prepare_pipes & (1 << intel_crtc->pipe))
9046 intel_encoder->connectors_active = false;
9047 }
9048
9049 intel_modeset_commit_output_state(dev);
9050
9051 /* Update computed state. */
9052 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9053 base.head) {
9054 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9055 }
9056
9057 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9058 if (!connector->encoder || !connector->encoder->crtc)
9059 continue;
9060
9061 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9062
9063 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02009064 struct drm_property *dpms_property =
9065 dev->mode_config.dpms_property;
9066
Daniel Vetterea9d7582012-07-10 10:42:52 +02009067 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05009068 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02009069 dpms_property,
9070 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009071
9072 intel_encoder = to_intel_encoder(connector->encoder);
9073 intel_encoder->connectors_active = true;
9074 }
9075 }
9076
9077}
9078
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009079static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009080{
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009081 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009082
9083 if (clock1 == clock2)
9084 return true;
9085
9086 if (!clock1 || !clock2)
9087 return false;
9088
9089 diff = abs(clock1 - clock2);
9090
9091 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9092 return true;
9093
9094 return false;
9095}
9096
Daniel Vetter25c5b262012-07-08 22:08:04 +02009097#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9098 list_for_each_entry((intel_crtc), \
9099 &(dev)->mode_config.crtc_list, \
9100 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02009101 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02009102
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009103static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009104intel_pipe_config_compare(struct drm_device *dev,
9105 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009106 struct intel_crtc_config *pipe_config)
9107{
Daniel Vetter66e985c2013-06-05 13:34:20 +02009108#define PIPE_CONF_CHECK_X(name) \
9109 if (current_config->name != pipe_config->name) { \
9110 DRM_ERROR("mismatch in " #name " " \
9111 "(expected 0x%08x, found 0x%08x)\n", \
9112 current_config->name, \
9113 pipe_config->name); \
9114 return false; \
9115 }
9116
Daniel Vetter08a24032013-04-19 11:25:34 +02009117#define PIPE_CONF_CHECK_I(name) \
9118 if (current_config->name != pipe_config->name) { \
9119 DRM_ERROR("mismatch in " #name " " \
9120 "(expected %i, found %i)\n", \
9121 current_config->name, \
9122 pipe_config->name); \
9123 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01009124 }
9125
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009126#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9127 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07009128 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009129 "(expected %i, found %i)\n", \
9130 current_config->name & (mask), \
9131 pipe_config->name & (mask)); \
9132 return false; \
9133 }
9134
Ville Syrjälä5e550652013-09-06 23:29:07 +03009135#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9136 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9137 DRM_ERROR("mismatch in " #name " " \
9138 "(expected %i, found %i)\n", \
9139 current_config->name, \
9140 pipe_config->name); \
9141 return false; \
9142 }
9143
Daniel Vetterbb760062013-06-06 14:55:52 +02009144#define PIPE_CONF_QUIRK(quirk) \
9145 ((current_config->quirks | pipe_config->quirks) & (quirk))
9146
Daniel Vettereccb1402013-05-22 00:50:22 +02009147 PIPE_CONF_CHECK_I(cpu_transcoder);
9148
Daniel Vetter08a24032013-04-19 11:25:34 +02009149 PIPE_CONF_CHECK_I(has_pch_encoder);
9150 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02009151 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9152 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9153 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9154 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9155 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02009156
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009157 PIPE_CONF_CHECK_I(has_dp_encoder);
9158 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9159 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9160 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9161 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9162 PIPE_CONF_CHECK_I(dp_m_n.tu);
9163
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009164 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9165 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9166 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9167 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9168 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9169 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9170
9171 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9172 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9173 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9174 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9175 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9176 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9177
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009178 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009179
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009180 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9181 DRM_MODE_FLAG_INTERLACE);
9182
Daniel Vetterbb760062013-06-06 14:55:52 +02009183 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9184 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9185 DRM_MODE_FLAG_PHSYNC);
9186 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9187 DRM_MODE_FLAG_NHSYNC);
9188 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9189 DRM_MODE_FLAG_PVSYNC);
9190 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9191 DRM_MODE_FLAG_NVSYNC);
9192 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009193
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009194 PIPE_CONF_CHECK_I(pipe_src_w);
9195 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009196
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009197 PIPE_CONF_CHECK_I(gmch_pfit.control);
9198 /* pfit ratios are autocomputed by the hw on gen4+ */
9199 if (INTEL_INFO(dev)->gen < 4)
9200 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9201 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009202 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9203 if (current_config->pch_pfit.enabled) {
9204 PIPE_CONF_CHECK_I(pch_pfit.pos);
9205 PIPE_CONF_CHECK_I(pch_pfit.size);
9206 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009207
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009208 PIPE_CONF_CHECK_I(ips_enabled);
9209
Ville Syrjälä282740f2013-09-04 18:30:03 +03009210 PIPE_CONF_CHECK_I(double_wide);
9211
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009212 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009213 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02009214 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009215 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9216 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009217
Ville Syrjälä42571ae2013-09-06 23:29:00 +03009218 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9219 PIPE_CONF_CHECK_I(pipe_bpp);
9220
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009221 if (!IS_HASWELL(dev)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01009222 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009223 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9224 }
Ville Syrjälä5e550652013-09-06 23:29:07 +03009225
Daniel Vetter66e985c2013-06-05 13:34:20 +02009226#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +02009227#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009228#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +03009229#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +02009230#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009231
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009232 return true;
9233}
9234
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009235static void
9236check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009237{
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009238 struct intel_connector *connector;
9239
9240 list_for_each_entry(connector, &dev->mode_config.connector_list,
9241 base.head) {
9242 /* This also checks the encoder/connector hw state with the
9243 * ->get_hw_state callbacks. */
9244 intel_connector_check_state(connector);
9245
9246 WARN(&connector->new_encoder->base != connector->base.encoder,
9247 "connector's staged encoder doesn't match current encoder\n");
9248 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009249}
9250
9251static void
9252check_encoder_state(struct drm_device *dev)
9253{
9254 struct intel_encoder *encoder;
9255 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009256
9257 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9258 base.head) {
9259 bool enabled = false;
9260 bool active = false;
9261 enum pipe pipe, tracked_pipe;
9262
9263 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9264 encoder->base.base.id,
9265 drm_get_encoder_name(&encoder->base));
9266
9267 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9268 "encoder's stage crtc doesn't match current crtc\n");
9269 WARN(encoder->connectors_active && !encoder->base.crtc,
9270 "encoder's active_connectors set, but no crtc\n");
9271
9272 list_for_each_entry(connector, &dev->mode_config.connector_list,
9273 base.head) {
9274 if (connector->base.encoder != &encoder->base)
9275 continue;
9276 enabled = true;
9277 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9278 active = true;
9279 }
9280 WARN(!!encoder->base.crtc != enabled,
9281 "encoder's enabled state mismatch "
9282 "(expected %i, found %i)\n",
9283 !!encoder->base.crtc, enabled);
9284 WARN(active && !encoder->base.crtc,
9285 "active encoder with no crtc\n");
9286
9287 WARN(encoder->connectors_active != active,
9288 "encoder's computed active state doesn't match tracked active state "
9289 "(expected %i, found %i)\n", active, encoder->connectors_active);
9290
9291 active = encoder->get_hw_state(encoder, &pipe);
9292 WARN(active != encoder->connectors_active,
9293 "encoder's hw state doesn't match sw tracking "
9294 "(expected %i, found %i)\n",
9295 encoder->connectors_active, active);
9296
9297 if (!encoder->base.crtc)
9298 continue;
9299
9300 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9301 WARN(active && pipe != tracked_pipe,
9302 "active encoder's pipe doesn't match"
9303 "(expected %i, found %i)\n",
9304 tracked_pipe, pipe);
9305
9306 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009307}
9308
9309static void
9310check_crtc_state(struct drm_device *dev)
9311{
9312 drm_i915_private_t *dev_priv = dev->dev_private;
9313 struct intel_crtc *crtc;
9314 struct intel_encoder *encoder;
9315 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009316
9317 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9318 base.head) {
9319 bool enabled = false;
9320 bool active = false;
9321
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009322 memset(&pipe_config, 0, sizeof(pipe_config));
9323
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009324 DRM_DEBUG_KMS("[CRTC:%d]\n",
9325 crtc->base.base.id);
9326
9327 WARN(crtc->active && !crtc->base.enabled,
9328 "active crtc, but not enabled in sw tracking\n");
9329
9330 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9331 base.head) {
9332 if (encoder->base.crtc != &crtc->base)
9333 continue;
9334 enabled = true;
9335 if (encoder->connectors_active)
9336 active = true;
9337 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02009338
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009339 WARN(active != crtc->active,
9340 "crtc's computed active state doesn't match tracked active state "
9341 "(expected %i, found %i)\n", active, crtc->active);
9342 WARN(enabled != crtc->base.enabled,
9343 "crtc's computed enabled state doesn't match tracked enabled state "
9344 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9345
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009346 active = dev_priv->display.get_pipe_config(crtc,
9347 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +02009348
9349 /* hw state is inconsistent with the pipe A quirk */
9350 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9351 active = crtc->active;
9352
Daniel Vetter6c49f242013-06-06 12:45:25 +02009353 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9354 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +03009355 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +02009356 if (encoder->base.crtc != &crtc->base)
9357 continue;
Ville Syrjälä3eaba512013-08-05 17:57:48 +03009358 if (encoder->get_config &&
9359 encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +02009360 encoder->get_config(encoder, &pipe_config);
9361 }
9362
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009363 WARN(crtc->active != active,
9364 "crtc active state doesn't match with hw state "
9365 "(expected %i, found %i)\n", crtc->active, active);
9366
Daniel Vetterc0b03412013-05-28 12:05:54 +02009367 if (active &&
9368 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9369 WARN(1, "pipe state doesn't match!\n");
9370 intel_dump_pipe_config(crtc, &pipe_config,
9371 "[hw state]");
9372 intel_dump_pipe_config(crtc, &crtc->config,
9373 "[sw state]");
9374 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009375 }
9376}
9377
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009378static void
9379check_shared_dpll_state(struct drm_device *dev)
9380{
9381 drm_i915_private_t *dev_priv = dev->dev_private;
9382 struct intel_crtc *crtc;
9383 struct intel_dpll_hw_state dpll_hw_state;
9384 int i;
Daniel Vetter53589012013-06-05 13:34:16 +02009385
9386 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9387 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9388 int enabled_crtcs = 0, active_crtcs = 0;
9389 bool active;
9390
9391 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9392
9393 DRM_DEBUG_KMS("%s\n", pll->name);
9394
9395 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9396
9397 WARN(pll->active > pll->refcount,
9398 "more active pll users than references: %i vs %i\n",
9399 pll->active, pll->refcount);
9400 WARN(pll->active && !pll->on,
9401 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +02009402 WARN(pll->on && !pll->active,
9403 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +02009404 WARN(pll->on != active,
9405 "pll on state mismatch (expected %i, found %i)\n",
9406 pll->on, active);
9407
9408 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9409 base.head) {
9410 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9411 enabled_crtcs++;
9412 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9413 active_crtcs++;
9414 }
9415 WARN(pll->active != active_crtcs,
9416 "pll active crtcs mismatch (expected %i, found %i)\n",
9417 pll->active, active_crtcs);
9418 WARN(pll->refcount != enabled_crtcs,
9419 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9420 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009421
9422 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9423 sizeof(dpll_hw_state)),
9424 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +02009425 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009426}
9427
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009428void
9429intel_modeset_check_state(struct drm_device *dev)
9430{
9431 check_connector_state(dev);
9432 check_encoder_state(dev);
9433 check_crtc_state(dev);
9434 check_shared_dpll_state(dev);
9435}
9436
Ville Syrjälä18442d02013-09-13 16:00:08 +03009437void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9438 int dotclock)
9439{
9440 /*
9441 * FDI already provided one idea for the dotclock.
9442 * Yell if the encoder disagrees.
9443 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01009444 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +03009445 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +01009446 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +03009447}
9448
Daniel Vetterf30da182013-04-11 20:22:50 +02009449static int __intel_set_mode(struct drm_crtc *crtc,
9450 struct drm_display_mode *mode,
9451 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02009452{
9453 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02009454 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009455 struct drm_display_mode *saved_mode, *saved_hwmode;
9456 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +02009457 struct intel_crtc *intel_crtc;
9458 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009459 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +02009460
Daniel Vettera1e22652013-09-21 00:35:38 +02009461 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009462 if (!saved_mode)
9463 return -ENOMEM;
Tim Gardner3ac18232012-12-07 07:54:26 -07009464 saved_hwmode = saved_mode + 1;
Daniel Vettera6778b32012-07-02 09:56:42 +02009465
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009466 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02009467 &prepare_pipes, &disable_pipes);
9468
Tim Gardner3ac18232012-12-07 07:54:26 -07009469 *saved_hwmode = crtc->hwmode;
9470 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009471
Daniel Vetter25c5b262012-07-08 22:08:04 +02009472 /* Hack: Because we don't (yet) support global modeset on multiple
9473 * crtcs, we don't keep track of the new mode for more than one crtc.
9474 * Hence simply check whether any bit is set in modeset_pipes in all the
9475 * pieces of code that are not yet converted to deal with mutliple crtcs
9476 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009477 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009478 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009479 if (IS_ERR(pipe_config)) {
9480 ret = PTR_ERR(pipe_config);
9481 pipe_config = NULL;
9482
Tim Gardner3ac18232012-12-07 07:54:26 -07009483 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +02009484 }
Daniel Vetterc0b03412013-05-28 12:05:54 +02009485 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9486 "[modeset]");
Daniel Vettera6778b32012-07-02 09:56:42 +02009487 }
9488
Jesse Barnes30a970c2013-11-04 13:48:12 -08009489 /*
9490 * See if the config requires any additional preparation, e.g.
9491 * to adjust global state with pipes off. We need to do this
9492 * here so we can get the modeset_pipe updated config for the new
9493 * mode set on this crtc. For other crtcs we need to use the
9494 * adjusted_mode bits in the crtc directly.
9495 */
9496 if (IS_VALLEYVIEW(dev))
9497 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9498 modeset_pipes, pipe_config);
9499
Daniel Vetter460da9162013-03-27 00:44:51 +01009500 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9501 intel_crtc_disable(&intel_crtc->base);
9502
Daniel Vetterea9d7582012-07-10 10:42:52 +02009503 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9504 if (intel_crtc->base.enabled)
9505 dev_priv->display.crtc_disable(&intel_crtc->base);
9506 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009507
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02009508 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9509 * to set it here already despite that we pass it down the callchain.
9510 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009511 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +02009512 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009513 /* mode_set/enable/disable functions rely on a correct pipe
9514 * config. */
9515 to_intel_crtc(crtc)->config = *pipe_config;
9516 }
Daniel Vetter7758a112012-07-08 19:40:39 +02009517
Daniel Vetterea9d7582012-07-10 10:42:52 +02009518 /* Only after disabling all output pipelines that will be changed can we
9519 * update the the output configuration. */
9520 intel_modeset_update_state(dev, prepare_pipes);
9521
Daniel Vetter47fab732012-10-26 10:58:18 +02009522 if (dev_priv->display.modeset_global_resources)
9523 dev_priv->display.modeset_global_resources(dev);
9524
Daniel Vettera6778b32012-07-02 09:56:42 +02009525 /* Set up the DPLL and any encoders state that needs to adjust or depend
9526 * on the DPLL.
9527 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009528 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009529 ret = intel_crtc_mode_set(&intel_crtc->base,
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009530 x, y, fb);
9531 if (ret)
9532 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02009533 }
9534
9535 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009536 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9537 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02009538
Daniel Vetter25c5b262012-07-08 22:08:04 +02009539 if (modeset_pipes) {
9540 /* Store real post-adjustment hardware mode. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009541 crtc->hwmode = pipe_config->adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009542
Daniel Vetter25c5b262012-07-08 22:08:04 +02009543 /* Calculate and store various constants which
9544 * are later needed by vblank and swap-completion
9545 * timestamping. They are derived from true hwmode.
9546 */
9547 drm_calc_timestamping_constants(crtc);
9548 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009549
9550 /* FIXME: add subpixel order */
9551done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009552 if (ret && crtc->enabled) {
Tim Gardner3ac18232012-12-07 07:54:26 -07009553 crtc->hwmode = *saved_hwmode;
9554 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009555 }
9556
Tim Gardner3ac18232012-12-07 07:54:26 -07009557out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009558 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -07009559 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +02009560 return ret;
9561}
9562
Damien Lespiaue7457a92013-08-08 22:28:59 +01009563static int intel_set_mode(struct drm_crtc *crtc,
9564 struct drm_display_mode *mode,
9565 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +02009566{
9567 int ret;
9568
9569 ret = __intel_set_mode(crtc, mode, x, y, fb);
9570
9571 if (ret == 0)
9572 intel_modeset_check_state(crtc->dev);
9573
9574 return ret;
9575}
9576
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009577void intel_crtc_restore_mode(struct drm_crtc *crtc)
9578{
9579 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9580}
9581
Daniel Vetter25c5b262012-07-08 22:08:04 +02009582#undef for_each_intel_crtc_masked
9583
Daniel Vetterd9e55602012-07-04 22:16:09 +02009584static void intel_set_config_free(struct intel_set_config *config)
9585{
9586 if (!config)
9587 return;
9588
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009589 kfree(config->save_connector_encoders);
9590 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02009591 kfree(config);
9592}
9593
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009594static int intel_set_config_save_state(struct drm_device *dev,
9595 struct intel_set_config *config)
9596{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009597 struct drm_encoder *encoder;
9598 struct drm_connector *connector;
9599 int count;
9600
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009601 config->save_encoder_crtcs =
9602 kcalloc(dev->mode_config.num_encoder,
9603 sizeof(struct drm_crtc *), GFP_KERNEL);
9604 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009605 return -ENOMEM;
9606
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009607 config->save_connector_encoders =
9608 kcalloc(dev->mode_config.num_connector,
9609 sizeof(struct drm_encoder *), GFP_KERNEL);
9610 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009611 return -ENOMEM;
9612
9613 /* Copy data. Note that driver private data is not affected.
9614 * Should anything bad happen only the expected state is
9615 * restored, not the drivers personal bookkeeping.
9616 */
9617 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009618 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009619 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009620 }
9621
9622 count = 0;
9623 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009624 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009625 }
9626
9627 return 0;
9628}
9629
9630static void intel_set_config_restore_state(struct drm_device *dev,
9631 struct intel_set_config *config)
9632{
Daniel Vetter9a935852012-07-05 22:34:27 +02009633 struct intel_encoder *encoder;
9634 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009635 int count;
9636
9637 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02009638 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9639 encoder->new_crtc =
9640 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009641 }
9642
9643 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02009644 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9645 connector->new_encoder =
9646 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009647 }
9648}
9649
Imre Deake3de42b2013-05-03 19:44:07 +02009650static bool
Chris Wilson2e57f472013-07-17 12:14:40 +01009651is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +02009652{
9653 int i;
9654
Chris Wilson2e57f472013-07-17 12:14:40 +01009655 if (set->num_connectors == 0)
9656 return false;
9657
9658 if (WARN_ON(set->connectors == NULL))
9659 return false;
9660
9661 for (i = 0; i < set->num_connectors; i++)
9662 if (set->connectors[i]->encoder &&
9663 set->connectors[i]->encoder->crtc == set->crtc &&
9664 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +02009665 return true;
9666
9667 return false;
9668}
9669
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009670static void
9671intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9672 struct intel_set_config *config)
9673{
9674
9675 /* We should be able to check here if the fb has the same properties
9676 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +01009677 if (is_crtc_connector_off(set)) {
9678 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009679 } else if (set->crtc->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009680 /* If we have no fb then treat it as a full mode set */
9681 if (set->crtc->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +03009682 struct intel_crtc *intel_crtc =
9683 to_intel_crtc(set->crtc);
9684
9685 if (intel_crtc->active && i915_fastboot) {
9686 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9687 config->fb_changed = true;
9688 } else {
9689 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9690 config->mode_changed = true;
9691 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009692 } else if (set->fb == NULL) {
9693 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +01009694 } else if (set->fb->pixel_format !=
9695 set->crtc->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009696 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009697 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009698 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009699 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009700 }
9701
Daniel Vetter835c5872012-07-10 18:11:08 +02009702 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009703 config->fb_changed = true;
9704
9705 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9706 DRM_DEBUG_KMS("modes are different, full mode set\n");
9707 drm_mode_debug_printmodeline(&set->crtc->mode);
9708 drm_mode_debug_printmodeline(set->mode);
9709 config->mode_changed = true;
9710 }
Chris Wilsona1d95702013-08-13 18:48:47 +01009711
9712 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9713 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009714}
9715
Daniel Vetter2e431052012-07-04 22:42:15 +02009716static int
Daniel Vetter9a935852012-07-05 22:34:27 +02009717intel_modeset_stage_output_state(struct drm_device *dev,
9718 struct drm_mode_set *set,
9719 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02009720{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009721 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009722 struct intel_connector *connector;
9723 struct intel_encoder *encoder;
Paulo Zanonif3f08572013-08-12 14:56:53 -03009724 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02009725
Damien Lespiau9abdda72013-02-13 13:29:23 +00009726 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +02009727 * of connectors. For paranoia, double-check this. */
9728 WARN_ON(!set->fb && (set->num_connectors != 0));
9729 WARN_ON(set->fb && (set->num_connectors == 0));
9730
Daniel Vetter9a935852012-07-05 22:34:27 +02009731 list_for_each_entry(connector, &dev->mode_config.connector_list,
9732 base.head) {
9733 /* Otherwise traverse passed in connector list and get encoders
9734 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02009735 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009736 if (set->connectors[ro] == &connector->base) {
9737 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02009738 break;
9739 }
9740 }
9741
Daniel Vetter9a935852012-07-05 22:34:27 +02009742 /* If we disable the crtc, disable all its connectors. Also, if
9743 * the connector is on the changing crtc but not on the new
9744 * connector list, disable it. */
9745 if ((!set->fb || ro == set->num_connectors) &&
9746 connector->base.encoder &&
9747 connector->base.encoder->crtc == set->crtc) {
9748 connector->new_encoder = NULL;
9749
9750 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9751 connector->base.base.id,
9752 drm_get_connector_name(&connector->base));
9753 }
9754
9755
9756 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02009757 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009758 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02009759 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009760 }
9761 /* connector->new_encoder is now updated for all connectors. */
9762
9763 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +02009764 list_for_each_entry(connector, &dev->mode_config.connector_list,
9765 base.head) {
9766 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02009767 continue;
9768
Daniel Vetter9a935852012-07-05 22:34:27 +02009769 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02009770
9771 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009772 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02009773 new_crtc = set->crtc;
9774 }
9775
9776 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02009777 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9778 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009779 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02009780 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009781 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9782
9783 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9784 connector->base.base.id,
9785 drm_get_connector_name(&connector->base),
9786 new_crtc->base.id);
9787 }
9788
9789 /* Check for any encoders that needs to be disabled. */
9790 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9791 base.head) {
9792 list_for_each_entry(connector,
9793 &dev->mode_config.connector_list,
9794 base.head) {
9795 if (connector->new_encoder == encoder) {
9796 WARN_ON(!connector->new_encoder->new_crtc);
9797
9798 goto next_encoder;
9799 }
9800 }
9801 encoder->new_crtc = NULL;
9802next_encoder:
9803 /* Only now check for crtc changes so we don't miss encoders
9804 * that will be disabled. */
9805 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02009806 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009807 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02009808 }
9809 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009810 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02009811
Daniel Vetter2e431052012-07-04 22:42:15 +02009812 return 0;
9813}
9814
9815static int intel_crtc_set_config(struct drm_mode_set *set)
9816{
9817 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02009818 struct drm_mode_set save_set;
9819 struct intel_set_config *config;
9820 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02009821
Daniel Vetter8d3e3752012-07-05 16:09:09 +02009822 BUG_ON(!set);
9823 BUG_ON(!set->crtc);
9824 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02009825
Daniel Vetter7e53f3a2013-01-21 10:52:17 +01009826 /* Enforce sane interface api - has been abused by the fb helper. */
9827 BUG_ON(!set->mode && set->fb);
9828 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +02009829
Daniel Vetter2e431052012-07-04 22:42:15 +02009830 if (set->fb) {
9831 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9832 set->crtc->base.id, set->fb->base.id,
9833 (int)set->num_connectors, set->x, set->y);
9834 } else {
9835 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02009836 }
9837
9838 dev = set->crtc->dev;
9839
9840 ret = -ENOMEM;
9841 config = kzalloc(sizeof(*config), GFP_KERNEL);
9842 if (!config)
9843 goto out_config;
9844
9845 ret = intel_set_config_save_state(dev, config);
9846 if (ret)
9847 goto out_config;
9848
9849 save_set.crtc = set->crtc;
9850 save_set.mode = &set->crtc->mode;
9851 save_set.x = set->crtc->x;
9852 save_set.y = set->crtc->y;
9853 save_set.fb = set->crtc->fb;
9854
9855 /* Compute whether we need a full modeset, only an fb base update or no
9856 * change at all. In the future we might also check whether only the
9857 * mode changed, e.g. for LVDS where we only change the panel fitter in
9858 * such cases. */
9859 intel_set_config_compute_mode_changes(set, config);
9860
Daniel Vetter9a935852012-07-05 22:34:27 +02009861 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02009862 if (ret)
9863 goto fail;
9864
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009865 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009866 ret = intel_set_mode(set->crtc, set->mode,
9867 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009868 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +02009869 intel_crtc_wait_for_pending_flips(set->crtc);
9870
Daniel Vetter4f660f42012-07-02 09:47:37 +02009871 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02009872 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02009873 }
9874
Chris Wilson2d05eae2013-05-03 17:36:25 +01009875 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +02009876 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9877 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +02009878fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +01009879 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02009880
Chris Wilson2d05eae2013-05-03 17:36:25 +01009881 /* Try to restore the config */
9882 if (config->mode_changed &&
9883 intel_set_mode(save_set.crtc, save_set.mode,
9884 save_set.x, save_set.y, save_set.fb))
9885 DRM_ERROR("failed to restore config after modeset failure\n");
9886 }
Daniel Vetter50f56112012-07-02 09:35:43 +02009887
Daniel Vetterd9e55602012-07-04 22:16:09 +02009888out_config:
9889 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02009890 return ret;
9891}
9892
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009893static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009894 .cursor_set = intel_crtc_cursor_set,
9895 .cursor_move = intel_crtc_cursor_move,
9896 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02009897 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01009898 .destroy = intel_crtc_destroy,
9899 .page_flip = intel_crtc_page_flip,
9900};
9901
Paulo Zanoni79f689a2012-10-05 12:05:52 -03009902static void intel_cpu_pll_init(struct drm_device *dev)
9903{
Paulo Zanoniaffa9352012-11-23 15:30:39 -02009904 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -03009905 intel_ddi_pll_init(dev);
9906}
9907
Daniel Vetter53589012013-06-05 13:34:16 +02009908static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9909 struct intel_shared_dpll *pll,
9910 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009911{
Daniel Vetter53589012013-06-05 13:34:16 +02009912 uint32_t val;
9913
9914 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +02009915 hw_state->dpll = val;
9916 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9917 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +02009918
9919 return val & DPLL_VCO_ENABLE;
9920}
9921
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02009922static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9923 struct intel_shared_dpll *pll)
9924{
9925 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9926 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9927}
9928
Daniel Vettere7b903d2013-06-05 13:34:14 +02009929static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9930 struct intel_shared_dpll *pll)
9931{
Daniel Vettere7b903d2013-06-05 13:34:14 +02009932 /* PCH refclock must be enabled first */
9933 assert_pch_refclk_enabled(dev_priv);
9934
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02009935 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9936
9937 /* Wait for the clocks to stabilize. */
9938 POSTING_READ(PCH_DPLL(pll->id));
9939 udelay(150);
9940
9941 /* The pixel multiplier can only be updated once the
9942 * DPLL is enabled and the clocks are stable.
9943 *
9944 * So write it again.
9945 */
9946 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9947 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02009948 udelay(200);
9949}
9950
9951static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9952 struct intel_shared_dpll *pll)
9953{
9954 struct drm_device *dev = dev_priv->dev;
9955 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +02009956
9957 /* Make sure no transcoder isn't still depending on us. */
9958 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9959 if (intel_crtc_to_shared_dpll(crtc) == pll)
9960 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9961 }
9962
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02009963 I915_WRITE(PCH_DPLL(pll->id), 0);
9964 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +02009965 udelay(200);
9966}
9967
Daniel Vetter46edb022013-06-05 13:34:12 +02009968static char *ibx_pch_dpll_names[] = {
9969 "PCH DPLL A",
9970 "PCH DPLL B",
9971};
9972
Daniel Vetter7c74ade2013-06-05 13:34:11 +02009973static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009974{
Daniel Vettere7b903d2013-06-05 13:34:14 +02009975 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009976 int i;
9977
Daniel Vetter7c74ade2013-06-05 13:34:11 +02009978 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009979
Daniel Vettere72f9fb2013-06-05 13:34:06 +02009980 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +02009981 dev_priv->shared_dplls[i].id = i;
9982 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02009983 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +02009984 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9985 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +02009986 dev_priv->shared_dplls[i].get_hw_state =
9987 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01009988 }
9989}
9990
Daniel Vetter7c74ade2013-06-05 13:34:11 +02009991static void intel_shared_dpll_init(struct drm_device *dev)
9992{
Daniel Vettere7b903d2013-06-05 13:34:14 +02009993 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +02009994
9995 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9996 ibx_pch_dpll_init(dev);
9997 else
9998 dev_priv->num_shared_dpll = 0;
9999
10000 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10001 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10002 dev_priv->num_shared_dpll);
10003}
10004
Hannes Ederb358d0a2008-12-18 21:18:47 +010010005static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080010006{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010007 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010008 struct intel_crtc *intel_crtc;
10009 int i;
10010
Daniel Vetter955382f2013-09-19 14:05:45 +020010011 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080010012 if (intel_crtc == NULL)
10013 return;
10014
10015 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10016
10017 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080010018 for (i = 0; i < 256; i++) {
10019 intel_crtc->lut_r[i] = i;
10020 intel_crtc->lut_g[i] = i;
10021 intel_crtc->lut_b[i] = i;
10022 }
10023
Jesse Barnes80824002009-09-10 15:28:06 -070010024 /* Swap pipes & planes for FBC on pre-965 */
10025 intel_crtc->pipe = pipe;
10026 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +010010027 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +080010028 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010010029 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070010030 }
10031
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010032 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10033 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10034 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10035 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10036
Jesse Barnes79e53942008-11-07 14:24:08 -080010037 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -080010038}
10039
Carl Worth08d7b3d2009-04-29 14:43:54 -070010040int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000010041 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070010042{
Carl Worth08d7b3d2009-04-29 14:43:54 -070010043 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020010044 struct drm_mode_object *drmmode_obj;
10045 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010046
Daniel Vetter1cff8f62012-04-24 09:55:08 +020010047 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10048 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010049
Daniel Vetterc05422d2009-08-11 16:05:30 +020010050 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10051 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070010052
Daniel Vetterc05422d2009-08-11 16:05:30 +020010053 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070010054 DRM_ERROR("no such CRTC id\n");
10055 return -EINVAL;
10056 }
10057
Daniel Vetterc05422d2009-08-11 16:05:30 +020010058 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10059 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010060
Daniel Vetterc05422d2009-08-11 16:05:30 +020010061 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010062}
10063
Daniel Vetter66a92782012-07-12 20:08:18 +020010064static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080010065{
Daniel Vetter66a92782012-07-12 20:08:18 +020010066 struct drm_device *dev = encoder->base.dev;
10067 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080010068 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010069 int entry = 0;
10070
Daniel Vetter66a92782012-07-12 20:08:18 +020010071 list_for_each_entry(source_encoder,
10072 &dev->mode_config.encoder_list, base.head) {
10073
10074 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080010075 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +020010076
10077 /* Intel hw has only one MUX where enocoders could be cloned. */
10078 if (encoder->cloneable && source_encoder->cloneable)
10079 index_mask |= (1 << entry);
10080
Jesse Barnes79e53942008-11-07 14:24:08 -080010081 entry++;
10082 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010010083
Jesse Barnes79e53942008-11-07 14:24:08 -080010084 return index_mask;
10085}
10086
Chris Wilson4d302442010-12-14 19:21:29 +000010087static bool has_edp_a(struct drm_device *dev)
10088{
10089 struct drm_i915_private *dev_priv = dev->dev_private;
10090
10091 if (!IS_MOBILE(dev))
10092 return false;
10093
10094 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10095 return false;
10096
10097 if (IS_GEN5(dev) &&
10098 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10099 return false;
10100
10101 return true;
10102}
10103
Jesse Barnes79e53942008-11-07 14:24:08 -080010104static void intel_setup_outputs(struct drm_device *dev)
10105{
Eric Anholt725e30a2009-01-22 13:01:02 -080010106 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010010107 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010108 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080010109
Daniel Vetterc9093352013-06-06 22:22:47 +020010110 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010111
Paulo Zanonic40c0f52013-04-12 18:16:53 -030010112 if (!IS_ULT(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020010113 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010114
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010115 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030010116 int found;
10117
10118 /* Haswell uses DDI functions to detect digital outputs */
10119 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10120 /* DDI A only supports eDP */
10121 if (found)
10122 intel_ddi_init(dev, PORT_A);
10123
10124 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10125 * register */
10126 found = I915_READ(SFUSE_STRAP);
10127
10128 if (found & SFUSE_STRAP_DDIB_DETECTED)
10129 intel_ddi_init(dev, PORT_B);
10130 if (found & SFUSE_STRAP_DDIC_DETECTED)
10131 intel_ddi_init(dev, PORT_C);
10132 if (found & SFUSE_STRAP_DDID_DETECTED)
10133 intel_ddi_init(dev, PORT_D);
10134 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010135 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +020010136 dpd_is_edp = intel_dpd_is_edp(dev);
10137
10138 if (has_edp_a(dev))
10139 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010140
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010141 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080010142 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010010143 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010144 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010145 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010146 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010147 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010148 }
10149
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010150 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010151 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010152
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010153 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010154 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010155
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010156 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010157 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010158
Daniel Vetter270b3042012-10-27 15:52:05 +020010159 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010160 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070010161 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030010162 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10163 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10164 PORT_B);
10165 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10166 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10167 }
10168
Jesse Barnes6f6005a2013-08-09 09:34:35 -070010169 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10170 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10171 PORT_C);
10172 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10174 PORT_C);
10175 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053010176
Jani Nikula3cfca972013-08-27 15:12:26 +030010177 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080010178 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080010179 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080010180
Paulo Zanonie2debe92013-02-18 19:00:27 -030010181 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010182 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010183 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010184 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10185 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010186 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010187 }
Ma Ling27185ae2009-08-24 13:50:23 +080010188
Imre Deake7281ea2013-05-08 13:14:08 +030010189 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010190 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080010191 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040010192
10193 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040010194
Paulo Zanonie2debe92013-02-18 19:00:27 -030010195 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010196 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010197 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010198 }
Ma Ling27185ae2009-08-24 13:50:23 +080010199
Paulo Zanonie2debe92013-02-18 19:00:27 -030010200 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080010201
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010202 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10203 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010204 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010205 }
Imre Deake7281ea2013-05-08 13:14:08 +030010206 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010207 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080010208 }
Ma Ling27185ae2009-08-24 13:50:23 +080010209
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010210 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030010211 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010212 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070010213 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080010214 intel_dvo_init(dev);
10215
Zhenyu Wang103a1962009-11-27 11:44:36 +080010216 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080010217 intel_tv_init(dev);
10218
Chris Wilson4ef69c72010-09-09 15:14:28 +010010219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10220 encoder->base.possible_crtcs = encoder->crtc_mask;
10221 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020010222 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080010223 }
Chris Wilson47356eb2011-01-11 17:06:04 +000010224
Paulo Zanonidde86e22012-12-01 12:04:25 -020010225 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020010226
10227 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010228}
10229
Chris Wilsonddfe1562013-08-06 17:43:07 +010010230void intel_framebuffer_fini(struct intel_framebuffer *fb)
10231{
10232 drm_framebuffer_cleanup(&fb->base);
Daniel Vetter80075d42013-10-09 21:23:52 +020010233 WARN_ON(!fb->obj->framebuffer_references--);
Chris Wilsonddfe1562013-08-06 17:43:07 +010010234 drm_gem_object_unreference_unlocked(&fb->obj->base);
10235}
10236
Jesse Barnes79e53942008-11-07 14:24:08 -080010237static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10238{
10239 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080010240
Chris Wilsonddfe1562013-08-06 17:43:07 +010010241 intel_framebuffer_fini(intel_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080010242 kfree(intel_fb);
10243}
10244
10245static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000010246 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080010247 unsigned int *handle)
10248{
10249 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000010250 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080010251
Chris Wilson05394f32010-11-08 19:18:58 +000010252 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080010253}
10254
10255static const struct drm_framebuffer_funcs intel_fb_funcs = {
10256 .destroy = intel_user_framebuffer_destroy,
10257 .create_handle = intel_user_framebuffer_create_handle,
10258};
10259
Dave Airlie38651672010-03-30 05:34:13 +000010260int intel_framebuffer_init(struct drm_device *dev,
10261 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010262 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +000010263 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080010264{
Daniel Vetter53155c02013-10-09 21:55:33 +020010265 int aligned_height, tile_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010010266 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080010267 int ret;
10268
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010269 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10270
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010271 if (obj->tiling_mode == I915_TILING_Y) {
10272 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010010273 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010274 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010275
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010276 if (mode_cmd->pitches[0] & 63) {
10277 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10278 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010010279 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010280 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010281
Chris Wilsona35cdaa2013-06-25 17:26:45 +010010282 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10283 pitch_limit = 32*1024;
10284 } else if (INTEL_INFO(dev)->gen >= 4) {
10285 if (obj->tiling_mode)
10286 pitch_limit = 16*1024;
10287 else
10288 pitch_limit = 32*1024;
10289 } else if (INTEL_INFO(dev)->gen >= 3) {
10290 if (obj->tiling_mode)
10291 pitch_limit = 8*1024;
10292 else
10293 pitch_limit = 16*1024;
10294 } else
10295 /* XXX DSPC is limited to 4k tiled */
10296 pitch_limit = 8*1024;
10297
10298 if (mode_cmd->pitches[0] > pitch_limit) {
10299 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10300 obj->tiling_mode ? "tiled" : "linear",
10301 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010302 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010303 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010304
10305 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010306 mode_cmd->pitches[0] != obj->stride) {
10307 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10308 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010309 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010310 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010311
Ville Syrjälä57779d02012-10-31 17:50:14 +020010312 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010313 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020010314 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020010315 case DRM_FORMAT_RGB565:
10316 case DRM_FORMAT_XRGB8888:
10317 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020010318 break;
10319 case DRM_FORMAT_XRGB1555:
10320 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010321 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010322 DRM_DEBUG("unsupported pixel format: %s\n",
10323 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010324 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010325 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020010326 break;
10327 case DRM_FORMAT_XBGR8888:
10328 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020010329 case DRM_FORMAT_XRGB2101010:
10330 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020010331 case DRM_FORMAT_XBGR2101010:
10332 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010333 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010334 DRM_DEBUG("unsupported pixel format: %s\n",
10335 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010336 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010337 }
Jesse Barnesb5626742011-06-24 12:19:27 -070010338 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020010339 case DRM_FORMAT_YUYV:
10340 case DRM_FORMAT_UYVY:
10341 case DRM_FORMAT_YVYU:
10342 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010343 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010344 DRM_DEBUG("unsupported pixel format: %s\n",
10345 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010346 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010347 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010348 break;
10349 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010350 DRM_DEBUG("unsupported pixel format: %s\n",
10351 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010010352 return -EINVAL;
10353 }
10354
Ville Syrjälä90f9a332012-10-31 17:50:19 +020010355 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10356 if (mode_cmd->offsets[0] != 0)
10357 return -EINVAL;
10358
Daniel Vetter53155c02013-10-09 21:55:33 +020010359 tile_height = IS_GEN2(dev) ? 16 : 8;
10360 aligned_height = ALIGN(mode_cmd->height,
10361 obj->tiling_mode ? tile_height : 1);
10362 /* FIXME drm helper for size checks (especially planar formats)? */
10363 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10364 return -EINVAL;
10365
Daniel Vetterc7d73f62012-12-13 23:38:38 +010010366 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10367 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020010368 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010010369
Jesse Barnes79e53942008-11-07 14:24:08 -080010370 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10371 if (ret) {
10372 DRM_ERROR("framebuffer init failed %d\n", ret);
10373 return ret;
10374 }
10375
Jesse Barnes79e53942008-11-07 14:24:08 -080010376 return 0;
10377}
10378
Jesse Barnes79e53942008-11-07 14:24:08 -080010379static struct drm_framebuffer *
10380intel_user_framebuffer_create(struct drm_device *dev,
10381 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010382 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080010383{
Chris Wilson05394f32010-11-08 19:18:58 +000010384 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080010385
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010386 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10387 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000010388 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010010389 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080010390
Chris Wilsond2dff872011-04-19 08:36:26 +010010391 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080010392}
10393
Daniel Vetter4520f532013-10-09 09:18:51 +020010394#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020010395static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020010396{
10397}
10398#endif
10399
Jesse Barnes79e53942008-11-07 14:24:08 -080010400static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080010401 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020010402 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080010403};
10404
Jesse Barnese70236a2009-09-21 10:42:27 -070010405/* Set up chip specific display functions */
10406static void intel_init_display(struct drm_device *dev)
10407{
10408 struct drm_i915_private *dev_priv = dev->dev_private;
10409
Daniel Vetteree9300b2013-06-03 22:40:22 +020010410 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10411 dev_priv->display.find_dpll = g4x_find_best_dpll;
10412 else if (IS_VALLEYVIEW(dev))
10413 dev_priv->display.find_dpll = vlv_find_best_dpll;
10414 else if (IS_PINEVIEW(dev))
10415 dev_priv->display.find_dpll = pnv_find_best_dpll;
10416 else
10417 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10418
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010419 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010420 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030010421 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020010422 dev_priv->display.crtc_enable = haswell_crtc_enable;
10423 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -030010424 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030010425 dev_priv->display.update_plane = ironlake_update_plane;
10426 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010427 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070010428 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020010429 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10430 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010431 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -070010432 dev_priv->display.update_plane = ironlake_update_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070010433 } else if (IS_VALLEYVIEW(dev)) {
10434 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10435 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10436 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10437 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10438 dev_priv->display.off = i9xx_crtc_off;
10439 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070010440 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010441 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070010442 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020010443 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10444 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010445 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -070010446 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070010447 }
Jesse Barnese70236a2009-09-21 10:42:27 -070010448
Jesse Barnese70236a2009-09-21 10:42:27 -070010449 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070010450 if (IS_VALLEYVIEW(dev))
10451 dev_priv->display.get_display_clock_speed =
10452 valleyview_get_display_clock_speed;
10453 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070010454 dev_priv->display.get_display_clock_speed =
10455 i945_get_display_clock_speed;
10456 else if (IS_I915G(dev))
10457 dev_priv->display.get_display_clock_speed =
10458 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020010459 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070010460 dev_priv->display.get_display_clock_speed =
10461 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020010462 else if (IS_PINEVIEW(dev))
10463 dev_priv->display.get_display_clock_speed =
10464 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070010465 else if (IS_I915GM(dev))
10466 dev_priv->display.get_display_clock_speed =
10467 i915gm_get_display_clock_speed;
10468 else if (IS_I865G(dev))
10469 dev_priv->display.get_display_clock_speed =
10470 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020010471 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070010472 dev_priv->display.get_display_clock_speed =
10473 i855_get_display_clock_speed;
10474 else /* 852, 830 */
10475 dev_priv->display.get_display_clock_speed =
10476 i830_get_display_clock_speed;
10477
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080010478 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010010479 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070010480 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010481 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080010482 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070010483 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010484 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -070010485 } else if (IS_IVYBRIDGE(dev)) {
10486 /* FIXME: detect B0+ stepping and use auto training */
10487 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010488 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020010489 dev_priv->display.modeset_global_resources =
10490 ivb_modeset_global_resources;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030010491 } else if (IS_HASWELL(dev)) {
10492 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080010493 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020010494 dev_priv->display.modeset_global_resources =
10495 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020010496 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070010497 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080010498 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080010499 } else if (IS_VALLEYVIEW(dev)) {
10500 dev_priv->display.modeset_global_resources =
10501 valleyview_modeset_global_resources;
Jesse Barnese70236a2009-09-21 10:42:27 -070010502 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010503
10504 /* Default just returns -ENODEV to indicate unsupported */
10505 dev_priv->display.queue_flip = intel_default_queue_flip;
10506
10507 switch (INTEL_INFO(dev)->gen) {
10508 case 2:
10509 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10510 break;
10511
10512 case 3:
10513 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10514 break;
10515
10516 case 4:
10517 case 5:
10518 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10519 break;
10520
10521 case 6:
10522 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10523 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010524 case 7:
10525 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10526 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010527 }
Jesse Barnese70236a2009-09-21 10:42:27 -070010528}
10529
Jesse Barnesb690e962010-07-19 13:53:12 -070010530/*
10531 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10532 * resume, or other times. This quirk makes sure that's the case for
10533 * affected systems.
10534 */
Akshay Joshi0206e352011-08-16 15:34:10 -040010535static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070010536{
10537 struct drm_i915_private *dev_priv = dev->dev_private;
10538
10539 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010540 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070010541}
10542
Keith Packard435793d2011-07-12 14:56:22 -070010543/*
10544 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10545 */
10546static void quirk_ssc_force_disable(struct drm_device *dev)
10547{
10548 struct drm_i915_private *dev_priv = dev->dev_private;
10549 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010550 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070010551}
10552
Carsten Emde4dca20e2012-03-15 15:56:26 +010010553/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010010554 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10555 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010010556 */
10557static void quirk_invert_brightness(struct drm_device *dev)
10558{
10559 struct drm_i915_private *dev_priv = dev->dev_private;
10560 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010561 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070010562}
10563
Kamal Mostafae85843b2013-07-19 15:02:01 -070010564/*
10565 * Some machines (Dell XPS13) suffer broken backlight controls if
10566 * BLM_PCH_PWM_ENABLE is set.
10567 */
10568static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10569{
10570 struct drm_i915_private *dev_priv = dev->dev_private;
10571 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10572 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10573}
10574
Jesse Barnesb690e962010-07-19 13:53:12 -070010575struct intel_quirk {
10576 int device;
10577 int subsystem_vendor;
10578 int subsystem_device;
10579 void (*hook)(struct drm_device *dev);
10580};
10581
Egbert Eich5f85f1762012-10-14 15:46:38 +020010582/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10583struct intel_dmi_quirk {
10584 void (*hook)(struct drm_device *dev);
10585 const struct dmi_system_id (*dmi_id_list)[];
10586};
10587
10588static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10589{
10590 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10591 return 1;
10592}
10593
10594static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10595 {
10596 .dmi_id_list = &(const struct dmi_system_id[]) {
10597 {
10598 .callback = intel_dmi_reverse_brightness,
10599 .ident = "NCR Corporation",
10600 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10601 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10602 },
10603 },
10604 { } /* terminating entry */
10605 },
10606 .hook = quirk_invert_brightness,
10607 },
10608};
10609
Ben Widawskyc43b5632012-04-16 14:07:40 -070010610static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070010611 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040010612 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070010613
Jesse Barnesb690e962010-07-19 13:53:12 -070010614 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10615 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10616
Jesse Barnesb690e962010-07-19 13:53:12 -070010617 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10618 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10619
Chris Wilsona4945f92013-10-08 11:16:59 +010010620 /* 830 needs to leave pipe A & dpll A up */
Daniel Vetterdcdaed62012-08-12 21:19:34 +020010621 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -070010622
10623 /* Lenovo U160 cannot use SSC on LVDS */
10624 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020010625
10626 /* Sony Vaio Y cannot use SSC on LVDS */
10627 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010010628
Jani Nikulaee1452d2013-09-20 15:05:30 +030010629 /*
10630 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10631 * seem to use inverted backlight PWM.
10632 */
10633 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
Kamal Mostafae85843b2013-07-19 15:02:01 -070010634
10635 /* Dell XPS13 HD Sandy Bridge */
10636 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10637 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10638 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
Jesse Barnesb690e962010-07-19 13:53:12 -070010639};
10640
10641static void intel_init_quirks(struct drm_device *dev)
10642{
10643 struct pci_dev *d = dev->pdev;
10644 int i;
10645
10646 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10647 struct intel_quirk *q = &intel_quirks[i];
10648
10649 if (d->device == q->device &&
10650 (d->subsystem_vendor == q->subsystem_vendor ||
10651 q->subsystem_vendor == PCI_ANY_ID) &&
10652 (d->subsystem_device == q->subsystem_device ||
10653 q->subsystem_device == PCI_ANY_ID))
10654 q->hook(dev);
10655 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020010656 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10657 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10658 intel_dmi_quirks[i].hook(dev);
10659 }
Jesse Barnesb690e962010-07-19 13:53:12 -070010660}
10661
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010662/* Disable the VGA plane that we never use */
10663static void i915_disable_vga(struct drm_device *dev)
10664{
10665 struct drm_i915_private *dev_priv = dev->dev_private;
10666 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020010667 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010668
10669 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070010670 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010671 sr1 = inb(VGA_SR_DATA);
10672 outb(sr1 | 1<<5, VGA_SR_DATA);
10673 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10674 udelay(300);
10675
10676 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10677 POSTING_READ(vga_reg);
10678}
10679
Daniel Vetterf8175862012-04-10 15:50:11 +020010680void intel_modeset_init_hw(struct drm_device *dev)
10681{
Jesse Barnesf6071162013-10-01 10:41:38 -070010682 struct drm_i915_private *dev_priv = dev->dev_private;
10683
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030010684 intel_prepare_ddi(dev);
10685
Daniel Vetterf8175862012-04-10 15:50:11 +020010686 intel_init_clock_gating(dev);
10687
Jesse Barnesf6071162013-10-01 10:41:38 -070010688 /* Enable the CRI clock source so we can get at the display */
10689 if (IS_VALLEYVIEW(dev))
10690 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10691 DPLL_INTEGRATED_CRI_CLK_VLV);
10692
Jesse Barnes40e9cf62013-10-03 11:35:46 -070010693 intel_init_dpio(dev);
10694
Daniel Vetter79f5b2c2012-06-24 16:42:33 +020010695 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +020010696 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +020010697 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +020010698}
10699
Imre Deak7d708ee2013-04-17 14:04:50 +030010700void intel_modeset_suspend_hw(struct drm_device *dev)
10701{
10702 intel_suspend_hw(dev);
10703}
10704
Jesse Barnes79e53942008-11-07 14:24:08 -080010705void intel_modeset_init(struct drm_device *dev)
10706{
Jesse Barnes652c3932009-08-17 13:31:43 -070010707 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010708 int i, j, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080010709
10710 drm_mode_config_init(dev);
10711
10712 dev->mode_config.min_width = 0;
10713 dev->mode_config.min_height = 0;
10714
Dave Airlie019d96c2011-09-29 16:20:42 +010010715 dev->mode_config.preferred_depth = 24;
10716 dev->mode_config.prefer_shadow = 1;
10717
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020010718 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080010719
Jesse Barnesb690e962010-07-19 13:53:12 -070010720 intel_init_quirks(dev);
10721
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030010722 intel_init_pm(dev);
10723
Ben Widawskye3c74752013-04-05 13:12:39 -070010724 if (INTEL_INFO(dev)->num_pipes == 0)
10725 return;
10726
Jesse Barnese70236a2009-09-21 10:42:27 -070010727 intel_init_display(dev);
10728
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010729 if (IS_GEN2(dev)) {
10730 dev->mode_config.max_width = 2048;
10731 dev->mode_config.max_height = 2048;
10732 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070010733 dev->mode_config.max_width = 4096;
10734 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080010735 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010736 dev->mode_config.max_width = 8192;
10737 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080010738 }
Ben Widawsky5d4545a2013-01-17 12:45:15 -080010739 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080010740
Zhao Yakui28c97732009-10-09 11:39:41 +080010741 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010742 INTEL_INFO(dev)->num_pipes,
10743 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080010744
Damien Lespiau08e2a7d2013-07-11 20:10:54 +010010745 for_each_pipe(i) {
Jesse Barnes79e53942008-11-07 14:24:08 -080010746 intel_crtc_init(dev, i);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010747 for (j = 0; j < dev_priv->num_plane; j++) {
10748 ret = intel_plane_init(dev, i, j);
10749 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030010750 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10751 pipe_name(i), sprite_name(i, j), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010752 }
Jesse Barnes79e53942008-11-07 14:24:08 -080010753 }
10754
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010755 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010756 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010757
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010758 /* Just disable it once at startup */
10759 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010760 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000010761
10762 /* Just in case the BIOS is doing something questionable. */
10763 intel_disable_fbc(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010010764}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080010765
Daniel Vetter24929352012-07-02 20:28:59 +020010766static void
10767intel_connector_break_all_links(struct intel_connector *connector)
10768{
10769 connector->base.dpms = DRM_MODE_DPMS_OFF;
10770 connector->base.encoder = NULL;
10771 connector->encoder->connectors_active = false;
10772 connector->encoder->base.crtc = NULL;
10773}
10774
Daniel Vetter7fad7982012-07-04 17:51:47 +020010775static void intel_enable_pipe_a(struct drm_device *dev)
10776{
10777 struct intel_connector *connector;
10778 struct drm_connector *crt = NULL;
10779 struct intel_load_detect_pipe load_detect_temp;
10780
10781 /* We can't just switch on the pipe A, we need to set things up with a
10782 * proper mode and output configuration. As a gross hack, enable pipe A
10783 * by enabling the load detect pipe once. */
10784 list_for_each_entry(connector,
10785 &dev->mode_config.connector_list,
10786 base.head) {
10787 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10788 crt = &connector->base;
10789 break;
10790 }
10791 }
10792
10793 if (!crt)
10794 return;
10795
10796 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10797 intel_release_load_detect_pipe(crt, &load_detect_temp);
10798
10799
10800}
10801
Daniel Vetterfa555832012-10-10 23:14:00 +020010802static bool
10803intel_check_plane_mapping(struct intel_crtc *crtc)
10804{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010805 struct drm_device *dev = crtc->base.dev;
10806 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020010807 u32 reg, val;
10808
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010809 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020010810 return true;
10811
10812 reg = DSPCNTR(!crtc->plane);
10813 val = I915_READ(reg);
10814
10815 if ((val & DISPLAY_PLANE_ENABLE) &&
10816 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10817 return false;
10818
10819 return true;
10820}
10821
Daniel Vetter24929352012-07-02 20:28:59 +020010822static void intel_sanitize_crtc(struct intel_crtc *crtc)
10823{
10824 struct drm_device *dev = crtc->base.dev;
10825 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020010826 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020010827
Daniel Vetter24929352012-07-02 20:28:59 +020010828 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020010829 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020010830 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10831
10832 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020010833 * disable the crtc (and hence change the state) if it is wrong. Note
10834 * that gen4+ has a fixed plane -> pipe mapping. */
10835 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020010836 struct intel_connector *connector;
10837 bool plane;
10838
Daniel Vetter24929352012-07-02 20:28:59 +020010839 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10840 crtc->base.base.id);
10841
10842 /* Pipe has the wrong plane attached and the plane is active.
10843 * Temporarily change the plane mapping and disable everything
10844 * ... */
10845 plane = crtc->plane;
10846 crtc->plane = !plane;
10847 dev_priv->display.crtc_disable(&crtc->base);
10848 crtc->plane = plane;
10849
10850 /* ... and break all links. */
10851 list_for_each_entry(connector, &dev->mode_config.connector_list,
10852 base.head) {
10853 if (connector->encoder->base.crtc != &crtc->base)
10854 continue;
10855
10856 intel_connector_break_all_links(connector);
10857 }
10858
10859 WARN_ON(crtc->active);
10860 crtc->base.enabled = false;
10861 }
Daniel Vetter24929352012-07-02 20:28:59 +020010862
Daniel Vetter7fad7982012-07-04 17:51:47 +020010863 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10864 crtc->pipe == PIPE_A && !crtc->active) {
10865 /* BIOS forgot to enable pipe A, this mostly happens after
10866 * resume. Force-enable the pipe to fix this, the update_dpms
10867 * call below we restore the pipe to the right state, but leave
10868 * the required bits on. */
10869 intel_enable_pipe_a(dev);
10870 }
10871
Daniel Vetter24929352012-07-02 20:28:59 +020010872 /* Adjust the state of the output pipe according to whether we
10873 * have active connectors/encoders. */
10874 intel_crtc_update_dpms(&crtc->base);
10875
10876 if (crtc->active != crtc->base.enabled) {
10877 struct intel_encoder *encoder;
10878
10879 /* This can happen either due to bugs in the get_hw_state
10880 * functions or because the pipe is force-enabled due to the
10881 * pipe A quirk. */
10882 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10883 crtc->base.base.id,
10884 crtc->base.enabled ? "enabled" : "disabled",
10885 crtc->active ? "enabled" : "disabled");
10886
10887 crtc->base.enabled = crtc->active;
10888
10889 /* Because we only establish the connector -> encoder ->
10890 * crtc links if something is active, this means the
10891 * crtc is now deactivated. Break the links. connector
10892 * -> encoder links are only establish when things are
10893 * actually up, hence no need to break them. */
10894 WARN_ON(crtc->active);
10895
10896 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10897 WARN_ON(encoder->connectors_active);
10898 encoder->base.crtc = NULL;
10899 }
10900 }
10901}
10902
10903static void intel_sanitize_encoder(struct intel_encoder *encoder)
10904{
10905 struct intel_connector *connector;
10906 struct drm_device *dev = encoder->base.dev;
10907
10908 /* We need to check both for a crtc link (meaning that the
10909 * encoder is active and trying to read from a pipe) and the
10910 * pipe itself being active. */
10911 bool has_active_crtc = encoder->base.crtc &&
10912 to_intel_crtc(encoder->base.crtc)->active;
10913
10914 if (encoder->connectors_active && !has_active_crtc) {
10915 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10916 encoder->base.base.id,
10917 drm_get_encoder_name(&encoder->base));
10918
10919 /* Connector is active, but has no active pipe. This is
10920 * fallout from our resume register restoring. Disable
10921 * the encoder manually again. */
10922 if (encoder->base.crtc) {
10923 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10924 encoder->base.base.id,
10925 drm_get_encoder_name(&encoder->base));
10926 encoder->disable(encoder);
10927 }
10928
10929 /* Inconsistent output/port/pipe state happens presumably due to
10930 * a bug in one of the get_hw_state functions. Or someplace else
10931 * in our code, like the register restore mess on resume. Clamp
10932 * things to off as a safer default. */
10933 list_for_each_entry(connector,
10934 &dev->mode_config.connector_list,
10935 base.head) {
10936 if (connector->encoder != encoder)
10937 continue;
10938
10939 intel_connector_break_all_links(connector);
10940 }
10941 }
10942 /* Enabled encoders without active connectors will be fixed in
10943 * the crtc fixup. */
10944}
10945
Daniel Vetter44cec742013-01-25 17:53:21 +010010946void i915_redisable_vga(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010010947{
10948 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020010949 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010010950
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030010951 /* This function can be called both from intel_modeset_setup_hw_state or
10952 * at a very early point in our resume sequence, where the power well
10953 * structures are not yet restored. Since this function is at a very
10954 * paranoid "someone might have enabled VGA while we were not looking"
10955 * level, just check if the power well is enabled instead of trying to
10956 * follow the "don't touch the power well if we don't need it" policy
10957 * the rest of the driver uses. */
10958 if (HAS_POWER_WELL(dev) &&
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -030010959 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030010960 return;
10961
Ville Syrjäläe1553fa2013-10-04 20:32:25 +030010962 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010010963 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
Ville Syrjälä209d5212013-01-25 21:44:48 +020010964 i915_disable_vga(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010010965 }
10966}
10967
Daniel Vetter30e984d2013-06-05 13:34:17 +020010968static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020010969{
10970 struct drm_i915_private *dev_priv = dev->dev_private;
10971 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020010972 struct intel_crtc *crtc;
10973 struct intel_encoder *encoder;
10974 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020010975 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020010976
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010977 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10978 base.head) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010010979 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020010980
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010981 crtc->active = dev_priv->display.get_pipe_config(crtc,
10982 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020010983
10984 crtc->base.enabled = crtc->active;
Ville Syrjälä4c445e02013-10-09 17:24:58 +030010985 crtc->primary_enabled = crtc->active;
Daniel Vetter24929352012-07-02 20:28:59 +020010986
10987 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10988 crtc->base.base.id,
10989 crtc->active ? "enabled" : "disabled");
10990 }
10991
Daniel Vetter53589012013-06-05 13:34:16 +020010992 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010993 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -030010994 intel_ddi_setup_hw_pll_state(dev);
10995
Daniel Vetter53589012013-06-05 13:34:16 +020010996 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10997 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10998
10999 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11000 pll->active = 0;
11001 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11002 base.head) {
11003 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11004 pll->active++;
11005 }
11006 pll->refcount = pll->active;
11007
Daniel Vetter35c95372013-07-17 06:55:04 +020011008 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11009 pll->name, pll->refcount, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020011010 }
11011
Daniel Vetter24929352012-07-02 20:28:59 +020011012 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11013 base.head) {
11014 pipe = 0;
11015
11016 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070011017 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11018 encoder->base.crtc = &crtc->base;
Jesse Barnes510d5f22013-07-01 15:50:17 -070011019 if (encoder->get_config)
Jesse Barnes045ac3b2013-05-14 17:08:26 -070011020 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020011021 } else {
11022 encoder->base.crtc = NULL;
11023 }
11024
11025 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010011026 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020011027 encoder->base.base.id,
11028 drm_get_encoder_name(&encoder->base),
11029 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010011030 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020011031 }
11032
11033 list_for_each_entry(connector, &dev->mode_config.connector_list,
11034 base.head) {
11035 if (connector->get_hw_state(connector)) {
11036 connector->base.dpms = DRM_MODE_DPMS_ON;
11037 connector->encoder->connectors_active = true;
11038 connector->base.encoder = &connector->encoder->base;
11039 } else {
11040 connector->base.dpms = DRM_MODE_DPMS_OFF;
11041 connector->base.encoder = NULL;
11042 }
11043 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11044 connector->base.base.id,
11045 drm_get_connector_name(&connector->base),
11046 connector->base.encoder ? "enabled" : "disabled");
11047 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020011048}
11049
11050/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11051 * and i915 state tracking structures. */
11052void intel_modeset_setup_hw_state(struct drm_device *dev,
11053 bool force_restore)
11054{
11055 struct drm_i915_private *dev_priv = dev->dev_private;
11056 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020011057 struct intel_crtc *crtc;
11058 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020011059 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020011060
11061 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020011062
Jesse Barnesbabea612013-06-26 18:57:38 +030011063 /*
11064 * Now that we have the config, copy it to each CRTC struct
11065 * Note that this could go away if we move to using crtc_config
11066 * checking everywhere.
11067 */
11068 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11069 base.head) {
11070 if (crtc->active && i915_fastboot) {
11071 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11072
11073 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11074 crtc->base.base.id);
11075 drm_mode_debug_printmodeline(&crtc->base.mode);
11076 }
11077 }
11078
Daniel Vetter24929352012-07-02 20:28:59 +020011079 /* HW state is read out, now we need to sanitize this mess. */
11080 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11081 base.head) {
11082 intel_sanitize_encoder(encoder);
11083 }
11084
11085 for_each_pipe(pipe) {
11086 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11087 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020011088 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020011089 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011090
Daniel Vetter35c95372013-07-17 06:55:04 +020011091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11092 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11093
11094 if (!pll->on || pll->active)
11095 continue;
11096
11097 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11098
11099 pll->disable(dev_priv, pll);
11100 pll->on = false;
11101 }
11102
Ville Syrjälä243e6a42013-10-14 14:55:24 +030011103 if (IS_HASWELL(dev))
11104 ilk_wm_get_hw_state(dev);
11105
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011106 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030011107 i915_redisable_vga(dev);
11108
Daniel Vetterf30da182013-04-11 20:22:50 +020011109 /*
11110 * We need to use raw interfaces for restoring state to avoid
11111 * checking (bogus) intermediate states.
11112 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011113 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070011114 struct drm_crtc *crtc =
11115 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020011116
11117 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11118 crtc->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011119 }
11120 } else {
11121 intel_modeset_update_staged_output_state(dev);
11122 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011123
11124 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +020011125
11126 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010011127}
11128
11129void intel_modeset_gem_init(struct drm_device *dev)
11130{
Chris Wilson1833b132012-05-09 11:56:28 +010011131 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020011132
11133 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020011134
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011135 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -080011136}
11137
11138void intel_modeset_cleanup(struct drm_device *dev)
11139{
Jesse Barnes652c3932009-08-17 13:31:43 -070011140 struct drm_i915_private *dev_priv = dev->dev_private;
11141 struct drm_crtc *crtc;
Paulo Zanonid9255d52013-09-26 20:05:59 -030011142 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070011143
Daniel Vetterfd0c0642013-04-24 11:13:35 +020011144 /*
11145 * Interrupts and polling as the first thing to avoid creating havoc.
11146 * Too much stuff here (turning of rps, connectors, ...) would
11147 * experience fancy races otherwise.
11148 */
11149 drm_irq_uninstall(dev);
11150 cancel_work_sync(&dev_priv->hotplug_work);
11151 /*
11152 * Due to the hpd irq storm handling the hotplug work can re-arm the
11153 * poll handlers. Hence disable polling after hpd handling is shut down.
11154 */
Keith Packardf87ea762010-10-03 19:36:26 -070011155 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020011156
Jesse Barnes652c3932009-08-17 13:31:43 -070011157 mutex_lock(&dev->struct_mutex);
11158
Jesse Barnes723bfd72010-10-07 16:01:13 -070011159 intel_unregister_dsm_handler();
11160
Jesse Barnes652c3932009-08-17 13:31:43 -070011161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11162 /* Skip inactive CRTCs */
11163 if (!crtc->fb)
11164 continue;
11165
Daniel Vetter3dec0092010-08-20 21:40:52 +020011166 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070011167 }
11168
Chris Wilson973d04f2011-07-08 12:22:37 +010011169 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070011170
Daniel Vetter8090c6b2012-06-24 16:42:32 +020011171 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000011172
Daniel Vetter930ebb42012-06-29 23:32:16 +020011173 ironlake_teardown_rc6(dev);
11174
Kristian Høgsberg69341a52009-11-11 12:19:17 -050011175 mutex_unlock(&dev->struct_mutex);
11176
Chris Wilson1630fe72011-07-08 12:22:42 +010011177 /* flush any delayed tasks or pending work */
11178 flush_scheduled_work();
11179
Jani Nikuladc652f92013-04-12 15:18:38 +030011180 /* destroy backlight, if any, before the connectors */
11181 intel_panel_destroy_backlight(dev);
11182
Paulo Zanonid9255d52013-09-26 20:05:59 -030011183 /* destroy the sysfs files before encoders/connectors */
11184 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11185 drm_sysfs_connector_remove(connector);
11186
Jesse Barnes79e53942008-11-07 14:24:08 -080011187 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010011188
11189 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011190}
11191
Dave Airlie28d52042009-09-21 14:33:58 +100011192/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080011193 * Return which encoder is currently attached for connector.
11194 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010011195struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080011196{
Chris Wilsondf0e9242010-09-09 16:20:55 +010011197 return &intel_attached_encoder(connector)->base;
11198}
Jesse Barnes79e53942008-11-07 14:24:08 -080011199
Chris Wilsondf0e9242010-09-09 16:20:55 +010011200void intel_connector_attach_encoder(struct intel_connector *connector,
11201 struct intel_encoder *encoder)
11202{
11203 connector->encoder = encoder;
11204 drm_mode_connector_attach_encoder(&connector->base,
11205 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080011206}
Dave Airlie28d52042009-09-21 14:33:58 +100011207
11208/*
11209 * set vga decode state - true == enable VGA decode
11210 */
11211int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11212{
11213 struct drm_i915_private *dev_priv = dev->dev_private;
11214 u16 gmch_ctrl;
11215
11216 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11217 if (state)
11218 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11219 else
11220 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11221 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11222 return 0;
11223}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011224
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011225struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011226
11227 u32 power_well_driver;
11228
Chris Wilson63b66e52013-08-08 15:12:06 +020011229 int num_transcoders;
11230
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011231 struct intel_cursor_error_state {
11232 u32 control;
11233 u32 position;
11234 u32 base;
11235 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010011236 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011237
11238 struct intel_pipe_error_state {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011239 u32 source;
Damien Lespiau52331302012-08-15 19:23:25 +010011240 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011241
11242 struct intel_plane_error_state {
11243 u32 control;
11244 u32 stride;
11245 u32 size;
11246 u32 pos;
11247 u32 addr;
11248 u32 surface;
11249 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010011250 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020011251
11252 struct intel_transcoder_error_state {
11253 enum transcoder cpu_transcoder;
11254
11255 u32 conf;
11256
11257 u32 htotal;
11258 u32 hblank;
11259 u32 hsync;
11260 u32 vtotal;
11261 u32 vblank;
11262 u32 vsync;
11263 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011264};
11265
11266struct intel_display_error_state *
11267intel_display_capture_error_state(struct drm_device *dev)
11268{
Akshay Joshi0206e352011-08-16 15:34:10 -040011269 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011270 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020011271 int transcoders[] = {
11272 TRANSCODER_A,
11273 TRANSCODER_B,
11274 TRANSCODER_C,
11275 TRANSCODER_EDP,
11276 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011277 int i;
11278
Chris Wilson63b66e52013-08-08 15:12:06 +020011279 if (INTEL_INFO(dev)->num_pipes == 0)
11280 return NULL;
11281
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011282 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011283 if (error == NULL)
11284 return NULL;
11285
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011286 if (HAS_POWER_WELL(dev))
11287 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11288
Damien Lespiau52331302012-08-15 19:23:25 +010011289 for_each_pipe(i) {
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011290 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11291 continue;
11292
Paulo Zanonia18c4c32013-03-06 20:03:12 -030011293 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11294 error->cursor[i].control = I915_READ(CURCNTR(i));
11295 error->cursor[i].position = I915_READ(CURPOS(i));
11296 error->cursor[i].base = I915_READ(CURBASE(i));
11297 } else {
11298 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11299 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11300 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11301 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011302
11303 error->plane[i].control = I915_READ(DSPCNTR(i));
11304 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011305 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030011306 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011307 error->plane[i].pos = I915_READ(DSPPOS(i));
11308 }
Paulo Zanonica291362013-03-06 20:03:14 -030011309 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11310 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011311 if (INTEL_INFO(dev)->gen >= 4) {
11312 error->plane[i].surface = I915_READ(DSPSURF(i));
11313 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11314 }
11315
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011316 error->pipe[i].source = I915_READ(PIPESRC(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020011317 }
11318
11319 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11320 if (HAS_DDI(dev_priv->dev))
11321 error->num_transcoders++; /* Account for eDP. */
11322
11323 for (i = 0; i < error->num_transcoders; i++) {
11324 enum transcoder cpu_transcoder = transcoders[i];
11325
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011326 if (!intel_display_power_enabled(dev,
11327 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11328 continue;
11329
Chris Wilson63b66e52013-08-08 15:12:06 +020011330 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11331
11332 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11333 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11334 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11335 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11336 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11337 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11338 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011339 }
11340
11341 return error;
11342}
11343
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011344#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11345
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011346void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011347intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011348 struct drm_device *dev,
11349 struct intel_display_error_state *error)
11350{
11351 int i;
11352
Chris Wilson63b66e52013-08-08 15:12:06 +020011353 if (!error)
11354 return;
11355
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011356 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011357 if (HAS_POWER_WELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011358 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011359 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010011360 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011361 err_printf(m, "Pipe [%d]:\n", i);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011362 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011363
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011364 err_printf(m, "Plane [%d]:\n", i);
11365 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11366 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011367 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011368 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11369 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011370 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030011371 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011372 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011373 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011374 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11375 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011376 }
11377
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011378 err_printf(m, "Cursor [%d]:\n", i);
11379 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11380 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11381 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011382 }
Chris Wilson63b66e52013-08-08 15:12:06 +020011383
11384 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010011385 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020011386 transcoder_name(error->transcoder[i].cpu_transcoder));
11387 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11388 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11389 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11390 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11391 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11392 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11393 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11394 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011395}