blob: 9db009c55c88c00d8213bcfb699cd78621a27c61 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Daniel Vetter3dec0092010-08-20 21:40:52 +020044static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010045static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080046
Jesse Barnesf1f644d2013-06-27 00:39:25 +030047static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +030049static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
Jesse Barnesf1f644d2013-06-27 00:39:25 +030051
Damien Lespiaue7457a92013-08-08 22:28:59 +010052static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
Jesse Barnes79e53942008-11-07 14:24:08 -080056typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040057 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080058} intel_range_t;
59
60typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040061 int dot_limit;
62 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080063} intel_p2_t;
64
Ma Lingd4906092009-03-18 20:13:27 +080065typedef struct intel_limit intel_limit_t;
66struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040067 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080069};
Jesse Barnes79e53942008-11-07 14:24:08 -080070
Daniel Vetterd2acd212012-10-20 20:57:43 +020071int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
Chris Wilson021357a2010-09-07 20:54:59 +010081static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
Chris Wilson8b99e682010-10-13 09:59:17 +010084 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +010089}
90
Daniel Vetter5d536e22013-07-06 12:52:06 +020091static const intel_limit_t intel_limits_i8xx_dac = {
Akshay Joshi0206e352011-08-16 15:34:10 -040092 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +020093 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +020094 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -040095 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
Keith Packarde4b36692009-06-05 19:22:17 -0700102};
103
Daniel Vetter5d536e22013-07-06 12:52:06 +0200104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200106 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200107 .n = { .min = 2, .max = 16 },
Daniel Vetter5d536e22013-07-06 12:52:06 +0200108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
Keith Packarde4b36692009-06-05 19:22:17 -0700117static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400118 .dot = { .min = 25000, .max = 350000 },
Ville Syrjälä9c333712013-12-09 18:54:17 +0200119 .vco = { .min = 908000, .max = 1512000 },
Ville Syrjälä91dbe5f2013-12-09 18:54:14 +0200120 .n = { .min = 2, .max = 16 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700128};
Eric Anholt273e27c2011-03-30 13:01:10 -0700129
Keith Packarde4b36692009-06-05 19:22:17 -0700130static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
Patrik Jakobsson4f7dfb62013-02-13 22:20:22 +0100135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
Patrik Jakobsson53a7d2d2013-02-13 22:20:21 +0100148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
Keith Packarde4b36692009-06-05 19:22:17 -0700154};
155
Eric Anholt273e27c2011-03-30 13:01:10 -0700156
Keith Packarde4b36692009-06-05 19:22:17 -0700157static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800169 },
Keith Packarde4b36692009-06-05 19:22:17 -0700170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800196 },
Keith Packarde4b36692009-06-05 19:22:17 -0700197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800210 },
Keith Packarde4b36692009-06-05 19:22:17 -0700211};
212
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500213static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700216 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700219 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700226};
227
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500228static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
Keith Packarde4b36692009-06-05 19:22:17 -0700239};
240
Eric Anholt273e27c2011-03-30 13:01:10 -0700241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800246static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
Keith Packarde4b36692009-06-05 19:22:17 -0700257};
258
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800259static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800283};
284
Eric Anholt273e27c2011-03-30 13:01:10 -0700285/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400294 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400307 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800310};
311
Ville Syrjälädc730512013-09-24 21:26:30 +0300312static const intel_limit_t intel_limits_vlv = {
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
Daniel Vetter75e53982013-04-18 21:10:43 +0200320 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700321 .n = { .min = 1, .max = 7 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
Ville Syrjäläb99ab662013-09-24 21:26:26 +0300324 .p1 = { .min = 2, .max = 3 },
Ville Syrjälä5fdc9c492013-09-24 21:26:29 +0300325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700326};
327
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200332 if (WARN_ON(clock->n == 0 || clock->p == 0))
333 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300336}
337
Paulo Zanonie0638cd2013-09-24 13:52:54 -0300338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
Chris Wilson1b894b52010-12-14 20:04:54 +0000353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800355{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800356 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800357 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100360 if (intel_is_dual_link_lvds(dev)) {
Chris Wilson1b894b52010-12-14 20:04:54 +0000361 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000366 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200371 } else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800372 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800373
374 return limit;
375}
376
Ma Ling044c7c42009-03-18 20:13:23 +0800377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
Ma Ling044c7c42009-03-18 20:13:23 +0800380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100383 if (intel_is_dual_link_lvds(dev))
Keith Packarde4b36692009-06-05 19:22:17 -0700384 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800385 else
Keith Packarde4b36692009-06-05 19:22:17 -0700386 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700389 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700391 limit = &intel_limits_g4x_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800392 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700393 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800394
395 return limit;
396}
397
Chris Wilson1b894b52010-12-14 20:04:54 +0000398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
Eric Anholtbad720f2009-10-22 16:11:14 -0700403 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000404 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800405 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800406 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500407 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500409 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800410 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500411 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700412 } else if (IS_VALLEYVIEW(dev)) {
Ville Syrjälädc730512013-09-24 21:26:30 +0300413 limit = &intel_limits_vlv;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
417 else
418 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800419 } else {
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700421 limit = &intel_limits_i8xx_lvds;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
Keith Packarde4b36692009-06-05 19:22:17 -0700423 limit = &intel_limits_i8xx_dvo;
Daniel Vetter5d536e22013-07-06 12:52:06 +0200424 else
425 limit = &intel_limits_i8xx_dac;
Jesse Barnes79e53942008-11-07 14:24:08 -0800426 }
427 return limit;
428}
429
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500430/* m1 is reserved as 0 in Pineview, n is a ring counter */
431static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800432{
Shaohua Li21778322009-02-23 15:19:16 +0800433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200435 if (WARN_ON(clock->n == 0 || clock->p == 0))
436 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Shaohua Li21778322009-02-23 15:19:16 +0800439}
440
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200441static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442{
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444}
445
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200446static void i9xx_clock(int refclk, intel_clock_t *clock)
Shaohua Li21778322009-02-23 15:19:16 +0800447{
Daniel Vetter7429e9d2013-04-20 17:19:46 +0200448 clock->m = i9xx_dpll_compute_m(clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800449 clock->p = clock->p1 * clock->p2;
Ville Syrjäläed5ca772013-12-02 19:00:45 +0200450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451 return;
Ville Syrjäläfb03ac02013-10-14 14:50:30 +0300452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
Jesse Barnes79e53942008-11-07 14:24:08 -0800454}
455
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
Chris Wilson1b894b52010-12-14 20:04:54 +0000462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800465{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400469 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400471 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400473 INTELPllInvalid("m1 out of range\n");
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300474
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
478
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
484 }
485
Jesse Barnes79e53942008-11-07 14:24:08 -0800486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400487 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
490 */
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400492 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800493
494 return true;
495}
496
Ma Lingd4906092009-03-18 20:13:27 +0800497static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200498i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800501{
502 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800503 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800504 int err = target;
505
Daniel Vettera210b022012-11-26 17:22:08 +0100506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800507 /*
Daniel Vettera210b022012-11-26 17:22:08 +0100508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
Jesse Barnes79e53942008-11-07 14:24:08 -0800511 */
Daniel Vetter1974cad2012-11-26 17:22:09 +0100512 if (intel_is_dual_link_lvds(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800513 clock.p2 = limit->p2.p2_fast;
514 else
515 clock.p2 = limit->p2.p2_slow;
516 } else {
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
519 else
520 clock.p2 = limit->p2.p2_fast;
521 }
522
Akshay Joshi0206e352011-08-16 15:34:10 -0400523 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800524
Zhao Yakui42158662009-11-20 11:24:18 +0800525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526 clock.m1++) {
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterc0efc382013-06-03 20:56:24 +0200529 if (clock.m2 >= clock.m1)
Zhao Yakui42158662009-11-20 11:24:18 +0800530 break;
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800535 int this_err;
536
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200537 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000538 if (!intel_PLL_is_valid(dev, limit,
539 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800540 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800541 if (match_clock &&
542 clock.p != match_clock->p)
543 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800544
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
547 *best_clock = clock;
548 err = this_err;
549 }
550 }
551 }
552 }
553 }
554
555 return (err != target);
556}
557
Ma Lingd4906092009-03-18 20:13:27 +0800558static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200559pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200562{
563 struct drm_device *dev = crtc->dev;
564 intel_clock_t clock;
565 int err = target;
566
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
568 /*
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
572 */
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
575 else
576 clock.p2 = limit->p2.p2_slow;
577 } else {
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
580 else
581 clock.p2 = limit->p2.p2_fast;
582 }
583
584 memset(best_clock, 0, sizeof(*best_clock));
585
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587 clock.m1++) {
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
594 int this_err;
595
596 pineview_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 if (!intel_PLL_is_valid(dev, limit,
598 &clock))
599 continue;
600 if (match_clock &&
601 clock.p != match_clock->p)
602 continue;
603
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
606 *best_clock = clock;
607 err = this_err;
608 }
609 }
610 }
611 }
612 }
613
614 return (err != target);
615}
616
Ma Lingd4906092009-03-18 20:13:27 +0800617static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200618g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800621{
622 struct drm_device *dev = crtc->dev;
Ma Lingd4906092009-03-18 20:13:27 +0800623 intel_clock_t clock;
624 int max_n;
625 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800628 found = false;
629
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Daniel Vetter1974cad2012-11-26 17:22:09 +0100631 if (intel_is_dual_link_lvds(dev))
Ma Lingd4906092009-03-18 20:13:27 +0800632 clock.p2 = limit->p2.p2_fast;
633 else
634 clock.p2 = limit->p2.p2_slow;
635 } else {
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
638 else
639 clock.p2 = limit->p2.p2_fast;
640 }
641
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200644 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200646 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
653 int this_err;
654
Daniel Vetterac58c3f2013-06-01 17:16:17 +0200655 i9xx_clock(refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000656 if (!intel_PLL_is_valid(dev, limit,
657 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800658 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000659
660 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800661 if (this_err < err_most) {
662 *best_clock = clock;
663 err_most = this_err;
664 max_n = clock.n;
665 found = true;
666 }
667 }
668 }
669 }
670 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800671 return found;
672}
Ma Lingd4906092009-03-18 20:13:27 +0800673
Zhenyu Wang2c072452009-06-05 15:38:42 +0800674static bool
Daniel Vetteree9300b2013-06-03 22:40:22 +0200675vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700678{
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300679 struct drm_device *dev = crtc->dev;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300680 intel_clock_t clock;
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300681 unsigned int bestppm = 1000000;
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300684 bool found = false;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700685
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300686 target *= 5; /* fast clock */
687
688 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700689
690 /* based on hardware requirement, prefer smaller n to precision */
Ville Syrjälä27e639b2013-09-24 21:26:24 +0300691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Ville Syrjälä811bbf02013-09-24 21:26:25 +0300692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
Ville Syrjälä889059d2013-09-24 21:26:27 +0300693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
Ville Syrjäläc1a9ae42013-09-24 21:26:23 +0300694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300695 clock.p = clock.p1 * clock.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700696 /* based on hardware requirement, prefer bigger m1,m2 values */
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300698 unsigned int ppm, diff;
699
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701 refclk * clock.m1);
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300702
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300703 vlv_clock(refclk, &clock);
704
Ville Syrjäläf01b7962013-09-27 16:55:49 +0300705 if (!intel_PLL_is_valid(dev, limit,
706 &clock))
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300707 continue;
708
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
711
712 if (ppm < 100 && clock.p > best_clock->p) {
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300713 bestppm = 0;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300714 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300715 found = true;
Ville Syrjälä43b0ac52013-09-24 21:26:18 +0300716 }
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300717
Ville Syrjäläc6861222013-09-24 21:26:21 +0300718 if (bestppm >= 10 && ppm < bestppm - 10) {
Ville Syrjälä69e4f9002013-09-24 21:26:20 +0300719 bestppm = ppm;
Ville Syrjälä6b4bf1c2013-09-27 16:54:19 +0300720 *best_clock = clock;
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300721 found = true;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700722 }
723 }
724 }
725 }
726 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700727
Ville Syrjälä49e497e2013-09-24 21:26:31 +0300728 return found;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700729}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700730
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300731bool intel_crtc_active(struct drm_crtc *crtc)
732{
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
737 *
Damien Lespiau241bfc32013-09-25 16:45:37 +0100738 * We can ditch the adjusted_mode.crtc_clock check as soon
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300739 * as Haswell has gained clock readout/fastboot support.
740 *
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
743 */
744 return intel_crtc->active && crtc->fb &&
Damien Lespiau241bfc32013-09-25 16:45:37 +0100745 intel_crtc->config.adjusted_mode.crtc_clock;
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300746}
747
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200748enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749 enum pipe pipe)
750{
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753
Daniel Vetter3b117c82013-04-17 20:15:07 +0200754 return intel_crtc->config.cpu_transcoder;
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200755}
756
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200757static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
Paulo Zanonia928d532012-05-04 17:18:15 -0300758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300761
762 frame = I915_READ(frame_reg);
763
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
766}
767
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700768/**
769 * intel_wait_for_vblank - wait for vblank on a given pipe
770 * @dev: drm device
771 * @pipe: pipe to wait for
772 *
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * mode setting code.
775 */
776void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800777{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700778 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800779 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700780
Ville Syrjälä57e22f42013-11-06 13:56:28 -0200781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
Paulo Zanonia928d532012-05-04 17:18:15 -0300783 return;
784 }
785
Chris Wilson300387c2010-09-05 20:25:43 +0100786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
788 *
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
795 * vblanks...
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
798 */
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700802 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
805 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700806 DRM_DEBUG_KMS("vblank wait timed out\n");
807}
808
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300809static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
813 u32 line1, line2;
814 u32 line_mask;
815
816 if (IS_GEN2(dev))
817 line_mask = DSL_LINEMASK_GEN2;
818 else
819 line_mask = DSL_LINEMASK_GEN3;
820
821 line1 = I915_READ(reg) & line_mask;
822 mdelay(5);
823 line2 = I915_READ(reg) & line_mask;
824
825 return line1 == line2;
826}
827
Keith Packardab7ad7f2010-10-03 00:33:06 -0700828/*
829 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700830 * @dev: drm device
831 * @pipe: pipe to wait for
832 *
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
836 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700837 * On Gen4 and above:
838 * wait for the pipe register state bit to turn off
839 *
840 * Otherwise:
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100843 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700844 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100845void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700846{
847 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700850
Keith Packardab7ad7f2010-10-03 00:33:06 -0700851 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200852 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700853
Keith Packardab7ad7f2010-10-03 00:33:06 -0700854 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200857 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700858 } else {
Keith Packardab7ad7f2010-10-03 00:33:06 -0700859 /* Wait for the display line to settle */
Ville Syrjäläfbf49ea2013-10-11 14:21:31 +0300860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
Daniel Vetter284637d2012-07-09 09:51:57 +0200861 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -0700862 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800863}
864
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
Damien Lespiauc36346e2012-12-13 16:09:03 +0000877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
Jesse Barnesb24e7172011-01-04 15:09:30 -0800910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
Daniel Vetter55607e82013-06-16 21:42:39 +0200916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
Jesse Barnesb24e7172011-01-04 15:09:30 -0800930
Jani Nikula23538ef2013-08-27 15:12:22 +0300931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
Daniel Vetter55607e82013-06-16 21:42:39 +0200949struct intel_shared_dpll *
Daniel Vettere2b78262013-06-07 23:10:03 +0200950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -0800951{
Daniel Vettere2b78262013-06-07 23:10:03 +0200952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
Daniel Vettera43f6e02013-06-07 23:10:32 +0200954 if (crtc->config.shared_dpll < 0)
Daniel Vettere2b78262013-06-07 23:10:03 +0200955 return NULL;
956
Daniel Vettera43f6e02013-06-07 23:10:32 +0200957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
Daniel Vettere2b78262013-06-07 23:10:03 +0200958}
959
Jesse Barnesb24e7172011-01-04 15:09:30 -0800960/* For ILK+ */
Daniel Vetter55607e82013-06-16 21:42:39 +0200961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -0800964{
Jesse Barnes040484a2011-01-03 12:14:26 -0800965 bool cur_state;
Daniel Vetter53589012013-06-05 13:34:16 +0200966 struct intel_dpll_hw_state hw_state;
Jesse Barnes040484a2011-01-03 12:14:26 -0800967
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -0300968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
Chris Wilson92b27b02012-05-20 18:10:50 +0100973 if (WARN (!pll,
Daniel Vetter46edb022013-06-05 13:34:12 +0200974 "asserting DPLL %s with no DPLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100975 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100976
Daniel Vetter53589012013-06-05 13:34:16 +0200977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
Chris Wilson92b27b02012-05-20 18:10:50 +0100978 WARN(cur_state != state,
Daniel Vetter53589012013-06-05 13:34:16 +0200979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -0800981}
Jesse Barnes040484a2011-01-03 12:14:26 -0800982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -0200989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -0800991
Paulo Zanoniaffa9352012-11-23 15:30:39 -0200992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
Paulo Zanoniad80a812012-10-24 16:06:19 -0200994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300995 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -0200996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -0300997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02001037 if (HAS_DDI(dev_priv->dev))
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001038 return;
1039
Jesse Barnes040484a2011-01-03 12:14:26 -08001040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
Daniel Vetter55607e82013-06-16 21:42:39 +02001045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001047{
1048 int reg;
1049 u32 val;
Daniel Vetter55607e82013-06-16 21:42:39 +02001050 bool cur_state;
Jesse Barnes040484a2011-01-03 12:14:26 -08001051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
Daniel Vetter55607e82013-06-16 21:42:39 +02001054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
Jesse Barnes040484a2011-01-03 12:14:26 -08001058}
1059
Jesse Barnesea0760c2011-01-04 15:09:32 -08001060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001066 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001086 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001087}
1088
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001111{
1112 int reg;
1113 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001114 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001117
Daniel Vetter8e636782012-01-22 01:36:48 +01001118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
Paulo Zanonib97186f2013-05-03 12:15:36 -03001122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
Paulo Zanoni69310162013-01-29 16:35:19 -02001124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001133 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001134}
1135
Chris Wilson931872f2012-01-16 23:01:13 +00001136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001138{
1139 int reg;
1140 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001141 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001149}
1150
Chris Wilson931872f2012-01-16 23:01:13 +00001151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
Jesse Barnesb24e7172011-01-04 15:09:30 -08001154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
Ville Syrjälä653e1022013-06-04 13:49:05 +03001157 struct drm_device *dev = dev_priv->dev;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
Ville Syrjälä653e1022013-06-04 13:49:05 +03001162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
Adam Jackson28c057942011-10-07 14:38:42 -04001164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001169 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001170 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001171
Jesse Barnesb24e7172011-01-04 15:09:30 -08001172 /* Need to check both planes against the pipe */
Damien Lespiau08e2a7d2013-07-11 20:10:54 +01001173 for_each_pipe(i) {
Jesse Barnesb24e7172011-01-04 15:09:30 -08001174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001181 }
1182}
1183
Jesse Barnes19332d72013-03-28 09:55:38 -07001184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001187 struct drm_device *dev = dev_priv->dev;
Jesse Barnes19332d72013-03-28 09:55:38 -07001188 int reg, i;
1189 u32 val;
1190
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001201 val = I915_READ(reg);
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001202 WARN((val & SPRITE_ENABLE),
Ville Syrjälä06da8da2013-04-17 17:48:51 +03001203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
Ville Syrjälä20674ee2013-06-04 13:49:06 +03001204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
Jesse Barnes19332d72013-03-28 09:55:38 -07001211 }
1212}
1213
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001214static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
Jesse Barnes92f25842011-01-04 15:09:34 -08001215{
1216 u32 val;
1217 bool enabled;
1218
Paulo Zanoni89eff4b2014-01-08 11:12:28 -02001219 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001220
Jesse Barnes92f25842011-01-04 15:09:34 -08001221 val = I915_READ(PCH_DREF_CONTROL);
1222 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1223 DREF_SUPERSPREAD_SOURCE_MASK));
1224 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1225}
1226
Daniel Vetterab9412b2013-05-03 11:49:46 +02001227static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
Jesse Barnes92f25842011-01-04 15:09:34 -08001229{
1230 int reg;
1231 u32 val;
1232 bool enabled;
1233
Daniel Vetterab9412b2013-05-03 11:49:46 +02001234 reg = PCH_TRANSCONF(pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001235 val = I915_READ(reg);
1236 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001237 WARN(enabled,
1238 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001240}
1241
Keith Packard4e634382011-08-06 10:39:45 -07001242static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001244{
1245 if ((val & DP_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1250 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1251 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1252 return false;
1253 } else {
1254 if ((val & DP_PIPE_MASK) != (pipe << 30))
1255 return false;
1256 }
1257 return true;
1258}
1259
Keith Packard1519b992011-08-06 10:35:34 -07001260static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe, u32 val)
1262{
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001263 if ((val & SDVO_ENABLE) == 0)
Keith Packard1519b992011-08-06 10:35:34 -07001264 return false;
1265
1266 if (HAS_PCH_CPT(dev_priv->dev)) {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001267 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001268 return false;
1269 } else {
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001270 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
Keith Packard1519b992011-08-06 10:35:34 -07001271 return false;
1272 }
1273 return true;
1274}
1275
1276static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, u32 val)
1278{
1279 if ((val & LVDS_PORT_EN) == 0)
1280 return false;
1281
1282 if (HAS_PCH_CPT(dev_priv->dev)) {
1283 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1284 return false;
1285 } else {
1286 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1287 return false;
1288 }
1289 return true;
1290}
1291
1292static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, u32 val)
1294{
1295 if ((val & ADPA_DAC_ENABLE) == 0)
1296 return false;
1297 if (HAS_PCH_CPT(dev_priv->dev)) {
1298 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1299 return false;
1300 } else {
1301 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1302 return false;
1303 }
1304 return true;
1305}
1306
Jesse Barnes291906f2011-02-02 12:28:03 -08001307static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001308 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001309{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001310 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001311 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001312 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001313 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001314
Daniel Vetter75c5da22012-09-10 21:58:29 +02001315 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1316 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001317 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001318}
1319
1320static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, int reg)
1322{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001323 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001324 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001325 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001326 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001327
Paulo Zanonidc0fa712013-02-19 16:21:46 -03001328 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
Daniel Vetter75c5da22012-09-10 21:58:29 +02001329 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001330 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001331}
1332
1333static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1334 enum pipe pipe)
1335{
1336 int reg;
1337 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001338
Keith Packardf0575e92011-07-25 22:12:43 -07001339 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1340 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1341 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001342
1343 reg = PCH_ADPA;
1344 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001345 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001346 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001347 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001348
1349 reg = PCH_LVDS;
1350 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001351 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001352 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001353 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001354
Paulo Zanonie2debe92013-02-18 19:00:27 -03001355 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1356 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1357 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
Jesse Barnes291906f2011-02-02 12:28:03 -08001358}
1359
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001360static void intel_init_dpio(struct drm_device *dev)
1361{
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363
1364 if (!IS_VALLEYVIEW(dev))
1365 return;
1366
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001367 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
Jesse Barnes5382f5f352013-12-16 16:34:24 -08001368}
1369
1370static void intel_reset_dpio(struct drm_device *dev)
1371{
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373
1374 if (!IS_VALLEYVIEW(dev))
1375 return;
1376
Imre Deake5cbfbf2014-01-09 17:08:16 +02001377 /*
1378 * Enable the CRI clock source so we can get at the display and the
1379 * reference clock for VGA hotplug / manual detection.
1380 */
Imre Deak404faab2014-01-09 17:08:15 +02001381 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
Imre Deake5cbfbf2014-01-09 17:08:16 +02001382 DPLL_REFA_CLK_ENABLE_VLV |
Imre Deak404faab2014-01-09 17:08:15 +02001383 DPLL_INTEGRATED_CRI_CLK_VLV);
1384
Jesse Barnes40e9cf62013-10-03 11:35:46 -07001385 /*
1386 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1388 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389 * b. The other bits such as sfr settings / modesel may all be set
1390 * to 0.
1391 *
1392 * This should only be done on init and resume from S3 with both
1393 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1394 */
1395 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1396}
1397
Daniel Vetter426115c2013-07-11 22:13:42 +02001398static void vlv_enable_pll(struct intel_crtc *crtc)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001399{
Daniel Vetter426115c2013-07-11 22:13:42 +02001400 struct drm_device *dev = crtc->base.dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 int reg = DPLL(crtc->pipe);
1403 u32 dpll = crtc->config.dpll_hw_state.dpll;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001404
Daniel Vetter426115c2013-07-11 22:13:42 +02001405 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001406
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001407 /* No really, not for ILK+ */
Daniel Vetter87442f72013-06-06 00:52:17 +02001408 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1409
1410 /* PLL is protected by panel, make sure we can write it */
1411 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
Daniel Vetter426115c2013-07-11 22:13:42 +02001412 assert_panel_unlocked(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001413
Daniel Vetter426115c2013-07-11 22:13:42 +02001414 I915_WRITE(reg, dpll);
1415 POSTING_READ(reg);
1416 udelay(150);
1417
1418 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1419 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1420
1421 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1422 POSTING_READ(DPLL_MD(crtc->pipe));
Daniel Vetter87442f72013-06-06 00:52:17 +02001423
1424 /* We do this three times for luck */
Daniel Vetter426115c2013-07-11 22:13:42 +02001425 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001426 POSTING_READ(reg);
1427 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001428 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001429 POSTING_READ(reg);
1430 udelay(150); /* wait for warmup */
Daniel Vetter426115c2013-07-11 22:13:42 +02001431 I915_WRITE(reg, dpll);
Daniel Vetter87442f72013-06-06 00:52:17 +02001432 POSTING_READ(reg);
1433 udelay(150); /* wait for warmup */
1434}
1435
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001436static void i9xx_enable_pll(struct intel_crtc *crtc)
Daniel Vetter87442f72013-06-06 00:52:17 +02001437{
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001438 struct drm_device *dev = crtc->base.dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440 int reg = DPLL(crtc->pipe);
1441 u32 dpll = crtc->config.dpll_hw_state.dpll;
Daniel Vetter87442f72013-06-06 00:52:17 +02001442
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001443 assert_pipe_disabled(dev_priv, crtc->pipe);
Daniel Vetter87442f72013-06-06 00:52:17 +02001444
1445 /* No really, not for ILK+ */
1446 BUG_ON(dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001447
1448 /* PLL is protected by panel, make sure we can write it */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001449 if (IS_MOBILE(dev) && !IS_I830(dev))
1450 assert_panel_unlocked(dev_priv, crtc->pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001451
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001452 I915_WRITE(reg, dpll);
1453
1454 /* Wait for the clocks to stabilize. */
1455 POSTING_READ(reg);
1456 udelay(150);
1457
1458 if (INTEL_INFO(dev)->gen >= 4) {
1459 I915_WRITE(DPLL_MD(crtc->pipe),
1460 crtc->config.dpll_hw_state.dpll_md);
1461 } else {
1462 /* The pixel multiplier can only be updated once the
1463 * DPLL is enabled and the clocks are stable.
1464 *
1465 * So write it again.
1466 */
1467 I915_WRITE(reg, dpll);
1468 }
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001469
1470 /* We do this three times for luck */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001471 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001474 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02001477 I915_WRITE(reg, dpll);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480}
1481
1482/**
Daniel Vetter50b44a42013-06-05 13:34:33 +02001483 * i9xx_disable_pll - disable a PLL
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to disable
1486 *
1487 * Disable the PLL for @pipe, making sure the pipe is off first.
1488 *
1489 * Note! This is for pre-ILK only.
1490 */
Daniel Vetter50b44a42013-06-05 13:34:33 +02001491static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001492{
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
Daniel Vetter50b44a42013-06-05 13:34:33 +02001500 I915_WRITE(DPLL(pipe), 0);
1501 POSTING_READ(DPLL(pipe));
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001502}
1503
Jesse Barnesf6071162013-10-01 10:41:38 -07001504static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1505{
1506 u32 val = 0;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
Imre Deake5cbfbf2014-01-09 17:08:16 +02001511 /*
1512 * Leave integrated clock source and reference clock enabled for pipe B.
1513 * The latter is needed for VGA hotplug / manual detection.
1514 */
Jesse Barnesf6071162013-10-01 10:41:38 -07001515 if (pipe == PIPE_B)
Imre Deake5cbfbf2014-01-09 17:08:16 +02001516 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07001517 I915_WRITE(DPLL(pipe), val);
1518 POSTING_READ(DPLL(pipe));
1519}
1520
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001521void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1522 struct intel_digital_port *dport)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001523{
1524 u32 port_mask;
1525
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001526 switch (dport->port) {
1527 case PORT_B:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001528 port_mask = DPLL_PORTB_READY_MASK;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001529 break;
1530 case PORT_C:
Jesse Barnes89b667f2013-04-18 14:51:36 -07001531 port_mask = DPLL_PORTC_READY_MASK;
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001532 break;
1533 default:
1534 BUG();
1535 }
Jesse Barnes89b667f2013-04-18 14:51:36 -07001536
1537 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1538 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
Ville Syrjäläbe46ffd2013-11-29 13:21:49 +02001539 port_name(dport->port), I915_READ(DPLL(0)));
Jesse Barnes89b667f2013-04-18 14:51:36 -07001540}
1541
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001542/**
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001543 * ironlake_enable_shared_dpll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001544 * @dev_priv: i915 private structure
1545 * @pipe: pipe PLL to enable
1546 *
1547 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548 * drives the transcoder clock.
1549 */
Daniel Vettere2b78262013-06-07 23:10:03 +02001550static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001551{
Daniel Vettere2b78262013-06-07 23:10:03 +02001552 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1553 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes92f25842011-01-04 15:09:34 -08001554
Chris Wilson48da64a2012-05-13 20:16:12 +01001555 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001556 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001557 if (WARN_ON(pll == NULL))
Chris Wilson48da64a2012-05-13 20:16:12 +01001558 return;
1559
1560 if (WARN_ON(pll->refcount == 0))
1561 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001562
Daniel Vetter46edb022013-06-05 13:34:12 +02001563 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001565 crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001566
Daniel Vettercdbd2312013-06-05 13:34:03 +02001567 if (pll->active++) {
1568 WARN_ON(!pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02001569 assert_shared_dpll_enabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001570 return;
1571 }
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001572 WARN_ON(pll->on);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001573
Daniel Vetter46edb022013-06-05 13:34:12 +02001574 DRM_DEBUG_KMS("enabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001575 pll->enable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001576 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001577}
1578
Daniel Vettere2b78262013-06-07 23:10:03 +02001579static void intel_disable_shared_dpll(struct intel_crtc *crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001580{
Daniel Vettere2b78262013-06-07 23:10:03 +02001581 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1582 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001583
Jesse Barnes92f25842011-01-04 15:09:34 -08001584 /* PCH only available on ILK+ */
1585 BUG_ON(dev_priv->info->gen < 5);
Daniel Vetter87a875b2013-06-05 13:34:19 +02001586 if (WARN_ON(pll == NULL))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001587 return;
1588
Chris Wilson48da64a2012-05-13 20:16:12 +01001589 if (WARN_ON(pll->refcount == 0))
1590 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001591
Daniel Vetter46edb022013-06-05 13:34:12 +02001592 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593 pll->name, pll->active, pll->on,
Daniel Vettere2b78262013-06-07 23:10:03 +02001594 crtc->base.base.id);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001595
Chris Wilson48da64a2012-05-13 20:16:12 +01001596 if (WARN_ON(pll->active == 0)) {
Daniel Vettere9d69442013-06-05 13:34:15 +02001597 assert_shared_dpll_disabled(dev_priv, pll);
Chris Wilson48da64a2012-05-13 20:16:12 +01001598 return;
1599 }
1600
Daniel Vettere9d69442013-06-05 13:34:15 +02001601 assert_shared_dpll_enabled(dev_priv, pll);
Daniel Vetterf4a091c2013-06-10 17:28:22 +02001602 WARN_ON(!pll->on);
Daniel Vettercdbd2312013-06-05 13:34:03 +02001603 if (--pll->active)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001604 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001605
Daniel Vetter46edb022013-06-05 13:34:12 +02001606 DRM_DEBUG_KMS("disabling %s\n", pll->name);
Daniel Vettere7b903d2013-06-05 13:34:14 +02001607 pll->disable(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001608 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001609}
1610
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001611static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1612 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001613{
Daniel Vetter23670b322012-11-01 09:15:30 +01001614 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001615 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vettere2b78262013-06-07 23:10:03 +02001616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter23670b322012-11-01 09:15:30 +01001617 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001618
1619 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv->info->gen < 5);
1621
1622 /* Make sure PCH DPLL is enabled */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001623 assert_shared_dpll_enabled(dev_priv,
Daniel Vettere9d69442013-06-05 13:34:15 +02001624 intel_crtc_to_shared_dpll(intel_crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001625
1626 /* FDI must be feeding us bits for PCH ports */
1627 assert_fdi_tx_enabled(dev_priv, pipe);
1628 assert_fdi_rx_enabled(dev_priv, pipe);
1629
Daniel Vetter23670b322012-11-01 09:15:30 +01001630 if (HAS_PCH_CPT(dev)) {
1631 /* Workaround: Set the timing override bit before enabling the
1632 * pch transcoder. */
1633 reg = TRANS_CHICKEN2(pipe);
1634 val = I915_READ(reg);
1635 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1636 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001637 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001638
Daniel Vetterab9412b2013-05-03 11:49:46 +02001639 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001640 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001641 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001642
1643 if (HAS_PCH_IBX(dev_priv->dev)) {
1644 /*
1645 * make the BPC in transcoder be consistent with
1646 * that in pipeconf reg.
1647 */
Daniel Vetterdfd07d72012-12-17 11:21:38 +01001648 val &= ~PIPECONF_BPC_MASK;
1649 val |= pipeconf_val & PIPECONF_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001650 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001651
1652 val &= ~TRANS_INTERLACE_MASK;
1653 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001654 if (HAS_PCH_IBX(dev_priv->dev) &&
1655 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1656 val |= TRANS_LEGACY_INTERLACED_ILK;
1657 else
1658 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001659 else
1660 val |= TRANS_PROGRESSIVE;
1661
Jesse Barnes040484a2011-01-03 12:14:26 -08001662 I915_WRITE(reg, val | TRANS_ENABLE);
1663 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001664 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
Jesse Barnes040484a2011-01-03 12:14:26 -08001665}
1666
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001667static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001668 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001669{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001670 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001671
1672 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv->info->gen < 5);
1674
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001675 /* FDI must be feeding us bits for PCH ports */
Daniel Vetter1a240d42012-11-29 22:18:51 +01001676 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001677 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001678
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001679 /* Workaround: set timing override bit. */
1680 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001681 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001682 I915_WRITE(_TRANSA_CHICKEN2, val);
1683
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001684 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001685 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001686
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001687 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1688 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001689 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001690 else
1691 val |= TRANS_PROGRESSIVE;
1692
Daniel Vetterab9412b2013-05-03 11:49:46 +02001693 I915_WRITE(LPT_TRANSCONF, val);
1694 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
Paulo Zanoni937bb612012-10-31 18:12:47 -02001695 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001696}
1697
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001698static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1699 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001700{
Daniel Vetter23670b322012-11-01 09:15:30 +01001701 struct drm_device *dev = dev_priv->dev;
1702 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001703
1704 /* FDI relies on the transcoder */
1705 assert_fdi_tx_disabled(dev_priv, pipe);
1706 assert_fdi_rx_disabled(dev_priv, pipe);
1707
Jesse Barnes291906f2011-02-02 12:28:03 -08001708 /* Ports must be off as well */
1709 assert_pch_ports_disabled(dev_priv, pipe);
1710
Daniel Vetterab9412b2013-05-03 11:49:46 +02001711 reg = PCH_TRANSCONF(pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001712 val = I915_READ(reg);
1713 val &= ~TRANS_ENABLE;
1714 I915_WRITE(reg, val);
1715 /* wait for PCH transcoder off, transcoder state */
1716 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Ville Syrjälä4bb6f1f2013-04-17 17:48:50 +03001717 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
Daniel Vetter23670b322012-11-01 09:15:30 +01001718
1719 if (!HAS_PCH_IBX(dev)) {
1720 /* Workaround: Clear the timing override chicken bit again. */
1721 reg = TRANS_CHICKEN2(pipe);
1722 val = I915_READ(reg);
1723 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1724 I915_WRITE(reg, val);
1725 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001726}
1727
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001728static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001729{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001730 u32 val;
1731
Daniel Vetterab9412b2013-05-03 11:49:46 +02001732 val = I915_READ(LPT_TRANSCONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001733 val &= ~TRANS_ENABLE;
Daniel Vetterab9412b2013-05-03 11:49:46 +02001734 I915_WRITE(LPT_TRANSCONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001735 /* wait for PCH transcoder off, transcoder state */
Daniel Vetterab9412b2013-05-03 11:49:46 +02001736 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001737 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001738
1739 /* Workaround: clear timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001741 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001742 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001743}
1744
1745/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001746 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001747 * @dev_priv: i915 private structure
1748 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001749 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001750 *
1751 * Enable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753 *
1754 * @pipe should be %PIPE_A or %PIPE_B.
1755 *
1756 * Will wait until the pipe is actually running (i.e. first vblank) before
1757 * returning.
1758 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001759static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03001760 bool pch_port, bool dsi)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001761{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001764 enum pipe pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001765 int reg;
1766 u32 val;
1767
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001768 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001769 assert_cursor_disabled(dev_priv, pipe);
Daniel Vetter58c6eaa2013-04-11 16:29:09 +02001770 assert_sprites_disabled(dev_priv, pipe);
1771
Paulo Zanoni681e5812012-12-06 11:12:38 -02001772 if (HAS_PCH_LPT(dev_priv->dev))
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001773 pch_transcoder = TRANSCODER_A;
1774 else
1775 pch_transcoder = pipe;
1776
Jesse Barnesb24e7172011-01-04 15:09:30 -08001777 /*
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1780 * need the check.
1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
Jani Nikula23538ef2013-08-27 15:12:22 +03001783 if (dsi)
1784 assert_dsi_pll_enabled(dev_priv);
1785 else
1786 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001787 else {
1788 if (pch_port) {
1789 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
Daniel Vetter1a240d42012-11-29 22:18:51 +01001791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001793 }
1794 /* FIXME: assert CPU port conditions for SNB+ */
1795 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001796
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001797 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001798 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001799 if (val & PIPECONF_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001803 intel_wait_for_vblank(dev_priv->dev, pipe);
1804}
1805
1806/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001807 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001808 * @dev_priv: i915 private structure
1809 * @pipe: pipe to disable
1810 *
1811 * Disable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1813 *
1814 * @pipe should be %PIPE_A or %PIPE_B.
1815 *
1816 * Will wait until the pipe has shut down before returning.
1817 */
1818static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1819 enum pipe pipe)
1820{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001821 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1822 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001823 int reg;
1824 u32 val;
1825
1826 /*
1827 * Make sure planes won't keep trying to pump pixels to us,
1828 * or we might hang the display.
1829 */
1830 assert_planes_disabled(dev_priv, pipe);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03001831 assert_cursor_disabled(dev_priv, pipe);
Jesse Barnes19332d72013-03-28 09:55:38 -07001832 assert_sprites_disabled(dev_priv, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001833
1834 /* Don't disable pipe A or pipe A PLLs if needed */
1835 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1836 return;
1837
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001838 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001839 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001840 if ((val & PIPECONF_ENABLE) == 0)
1841 return;
1842
1843 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001844 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1845}
1846
Keith Packardd74362c2011-07-28 14:47:14 -07001847/*
1848 * Plane regs are double buffered, going from enabled->disabled needs a
1849 * trigger in order to latch. The display address reg provides this.
1850 */
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001851void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane)
Keith Packardd74362c2011-07-28 14:47:14 -07001853{
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001854 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855
1856 I915_WRITE(reg, I915_READ(reg));
1857 POSTING_READ(reg);
Keith Packardd74362c2011-07-28 14:47:14 -07001858}
1859
Jesse Barnesb24e7172011-01-04 15:09:30 -08001860/**
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001861 * intel_enable_primary_plane - enable the primary plane on a given pipe
Jesse Barnesb24e7172011-01-04 15:09:30 -08001862 * @dev_priv: i915 private structure
1863 * @plane: plane to enable
1864 * @pipe: pipe being fed
1865 *
1866 * Enable @plane on @pipe, making sure that @pipe is running first.
1867 */
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001868static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1869 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001870{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001871 struct intel_crtc *intel_crtc =
1872 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001873 int reg;
1874 u32 val;
1875
1876 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877 assert_pipe_enabled(dev_priv, pipe);
1878
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001879 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
Ville Syrjälä0037f712013-10-01 18:02:20 +03001880
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001881 intel_crtc->primary_enabled = true;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001882
Jesse Barnesb24e7172011-01-04 15:09:30 -08001883 reg = DSPCNTR(plane);
1884 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001885 if (val & DISPLAY_PLANE_ENABLE)
1886 return;
1887
1888 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001889 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001890 intel_wait_for_vblank(dev_priv->dev, pipe);
1891}
1892
Jesse Barnesb24e7172011-01-04 15:09:30 -08001893/**
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001894 * intel_disable_primary_plane - disable the primary plane
Jesse Barnesb24e7172011-01-04 15:09:30 -08001895 * @dev_priv: i915 private structure
1896 * @plane: plane to disable
1897 * @pipe: pipe consuming the data
1898 *
1899 * Disable @plane; should be an independent operation.
1900 */
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03001901static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1902 enum plane plane, enum pipe pipe)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001903{
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001904 struct intel_crtc *intel_crtc =
1905 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001906 int reg;
1907 u32 val;
1908
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001909 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
Ville Syrjälä0037f712013-10-01 18:02:20 +03001910
Ville Syrjälä4c445e02013-10-09 17:24:58 +03001911 intel_crtc->primary_enabled = false;
Ville Syrjälä939c2fe2013-10-01 18:02:10 +03001912
Jesse Barnesb24e7172011-01-04 15:09:30 -08001913 reg = DSPCNTR(plane);
1914 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001915 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1916 return;
1917
1918 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001919 intel_flush_primary_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001920 intel_wait_for_vblank(dev_priv->dev, pipe);
1921}
1922
Chris Wilson693db182013-03-05 14:52:39 +00001923static bool need_vtd_wa(struct drm_device *dev)
1924{
1925#ifdef CONFIG_INTEL_IOMMU
1926 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1927 return true;
1928#endif
1929 return false;
1930}
1931
Chris Wilson127bd2a2010-07-23 23:32:05 +01001932int
Chris Wilson48b956c2010-09-14 12:50:34 +01001933intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001934 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001935 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001936{
Chris Wilsonce453d82011-02-21 14:43:56 +00001937 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001938 u32 alignment;
1939 int ret;
1940
Chris Wilson05394f32010-11-08 19:18:58 +00001941 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001942 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001943 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1944 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001945 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001946 alignment = 4 * 1024;
1947 else
1948 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001949 break;
1950 case I915_TILING_X:
1951 /* pin() will align the object as required by fence */
1952 alignment = 0;
1953 break;
1954 case I915_TILING_Y:
Daniel Vetter80075d42013-10-09 21:23:52 +02001955 WARN(1, "Y tiled bo slipped through, driver bug!\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001956 return -EINVAL;
1957 default:
1958 BUG();
1959 }
1960
Chris Wilson693db182013-03-05 14:52:39 +00001961 /* Note that the w/a also requires 64 PTE of padding following the
1962 * bo. We currently fill all unused PTE with the shadow page and so
1963 * we should always have valid PTE following the scanout preventing
1964 * the VT-d warning.
1965 */
1966 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1967 alignment = 256 * 1024;
1968
Chris Wilsonce453d82011-02-21 14:43:56 +00001969 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001970 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001971 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001972 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001973
1974 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975 * fence, whereas 965+ only requires a fence if using
1976 * framebuffer compression. For simplicity, we always install
1977 * a fence as the cost is not that onerous.
1978 */
Chris Wilson06d98132012-04-17 15:31:24 +01001979 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001980 if (ret)
1981 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001982
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001983 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001984
Chris Wilsonce453d82011-02-21 14:43:56 +00001985 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001986 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001987
1988err_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01001989 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001990err_interruptible:
1991 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001992 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001993}
1994
Chris Wilson1690e1e2011-12-14 13:57:08 +01001995void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1996{
1997 i915_gem_object_unpin_fence(obj);
Chris Wilsoncc98b412013-08-09 12:25:09 +01001998 i915_gem_object_unpin_from_display_plane(obj);
Chris Wilson1690e1e2011-12-14 13:57:08 +01001999}
2000
Daniel Vetterc2c75132012-07-05 12:17:30 +02002001/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002 * is assumed to be a power-of-two. */
Chris Wilsonbc752862013-02-21 20:04:31 +00002003unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2004 unsigned int tiling_mode,
2005 unsigned int cpp,
2006 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002007{
Chris Wilsonbc752862013-02-21 20:04:31 +00002008 if (tiling_mode != I915_TILING_NONE) {
2009 unsigned int tile_rows, tiles;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002010
Chris Wilsonbc752862013-02-21 20:04:31 +00002011 tile_rows = *y / 8;
2012 *y %= 8;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002013
Chris Wilsonbc752862013-02-21 20:04:31 +00002014 tiles = *x / (512/cpp);
2015 *x %= 512/cpp;
2016
2017 return tile_rows * pitch * 8 + tiles * 4096;
2018 } else {
2019 unsigned int offset;
2020
2021 offset = *y * pitch + *x * cpp;
2022 *y = 0;
2023 *x = (offset & 4095) / cpp;
2024 return offset & -4096;
2025 }
Daniel Vetterc2c75132012-07-05 12:17:30 +02002026}
2027
Jesse Barnes17638cd2011-06-24 12:19:23 -07002028static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2029 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002030{
2031 struct drm_device *dev = crtc->dev;
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2034 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002035 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002036 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002037 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002038 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002039 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002040
2041 switch (plane) {
2042 case 0:
2043 case 1:
2044 break;
2045 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002046 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes81255562010-08-02 12:07:50 -07002047 return -EINVAL;
2048 }
2049
2050 intel_fb = to_intel_framebuffer(fb);
2051 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002052
Chris Wilson5eddb702010-09-11 13:48:45 +01002053 reg = DSPCNTR(plane);
2054 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002055 /* Mask out pixel format bits in case we change it */
2056 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002057 switch (fb->pixel_format) {
2058 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002059 dspcntr |= DISPPLANE_8BPP;
2060 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002061 case DRM_FORMAT_XRGB1555:
2062 case DRM_FORMAT_ARGB1555:
2063 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002064 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002065 case DRM_FORMAT_RGB565:
2066 dspcntr |= DISPPLANE_BGRX565;
2067 break;
2068 case DRM_FORMAT_XRGB8888:
2069 case DRM_FORMAT_ARGB8888:
2070 dspcntr |= DISPPLANE_BGRX888;
2071 break;
2072 case DRM_FORMAT_XBGR8888:
2073 case DRM_FORMAT_ABGR8888:
2074 dspcntr |= DISPPLANE_RGBX888;
2075 break;
2076 case DRM_FORMAT_XRGB2101010:
2077 case DRM_FORMAT_ARGB2101010:
2078 dspcntr |= DISPPLANE_BGRX101010;
2079 break;
2080 case DRM_FORMAT_XBGR2101010:
2081 case DRM_FORMAT_ABGR2101010:
2082 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002083 break;
2084 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002085 BUG();
Jesse Barnes81255562010-08-02 12:07:50 -07002086 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002087
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002088 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002089 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002090 dspcntr |= DISPPLANE_TILED;
2091 else
2092 dspcntr &= ~DISPPLANE_TILED;
2093 }
2094
Ville Syrjäläde1aa622013-06-07 10:47:01 +03002095 if (IS_G4X(dev))
2096 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
Chris Wilson5eddb702010-09-11 13:48:45 +01002098 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002099
Daniel Vettere506a0c2012-07-05 12:17:29 +02002100 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002101
Daniel Vetterc2c75132012-07-05 12:17:30 +02002102 if (INTEL_INFO(dev)->gen >= 4) {
2103 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002104 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2105 fb->bits_per_pixel / 8,
2106 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002107 linear_offset -= intel_crtc->dspaddr_offset;
2108 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002109 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002110 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002111
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002112 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2114 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002115 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002116 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002117 I915_MODIFY_DISPBASE(DSPSURF(plane),
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002118 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002119 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002120 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002121 } else
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002122 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002123 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002124
Jesse Barnes17638cd2011-06-24 12:19:23 -07002125 return 0;
2126}
2127
2128static int ironlake_update_plane(struct drm_crtc *crtc,
2129 struct drm_framebuffer *fb, int x, int y)
2130{
2131 struct drm_device *dev = crtc->dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134 struct intel_framebuffer *intel_fb;
2135 struct drm_i915_gem_object *obj;
2136 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002137 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002138 u32 dspcntr;
2139 u32 reg;
2140
2141 switch (plane) {
2142 case 0:
2143 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002144 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002145 break;
2146 default:
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002147 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
Jesse Barnes17638cd2011-06-24 12:19:23 -07002148 return -EINVAL;
2149 }
2150
2151 intel_fb = to_intel_framebuffer(fb);
2152 obj = intel_fb->obj;
2153
2154 reg = DSPCNTR(plane);
2155 dspcntr = I915_READ(reg);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002158 switch (fb->pixel_format) {
2159 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002160 dspcntr |= DISPPLANE_8BPP;
2161 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002162 case DRM_FORMAT_RGB565:
2163 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002164 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002165 case DRM_FORMAT_XRGB8888:
2166 case DRM_FORMAT_ARGB8888:
2167 dspcntr |= DISPPLANE_BGRX888;
2168 break;
2169 case DRM_FORMAT_XBGR8888:
2170 case DRM_FORMAT_ABGR8888:
2171 dspcntr |= DISPPLANE_RGBX888;
2172 break;
2173 case DRM_FORMAT_XRGB2101010:
2174 case DRM_FORMAT_ARGB2101010:
2175 dspcntr |= DISPPLANE_BGRX101010;
2176 break;
2177 case DRM_FORMAT_XBGR2101010:
2178 case DRM_FORMAT_ABGR2101010:
2179 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002180 break;
2181 default:
Daniel Vetterbaba1332013-03-27 00:45:00 +01002182 BUG();
Jesse Barnes17638cd2011-06-24 12:19:23 -07002183 }
2184
2185 if (obj->tiling_mode != I915_TILING_NONE)
2186 dspcntr |= DISPPLANE_TILED;
2187 else
2188 dspcntr &= ~DISPPLANE_TILED;
2189
Ville Syrjäläb42c6002013-11-03 13:47:27 +02002190 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03002191 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2192 else
2193 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002194
2195 I915_WRITE(reg, dspcntr);
2196
Daniel Vettere506a0c2012-07-05 12:17:29 +02002197 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002198 intel_crtc->dspaddr_offset =
Chris Wilsonbc752862013-02-21 20:04:31 +00002199 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2200 fb->bits_per_pixel / 8,
2201 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002202 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002203
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2206 fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002208 I915_MODIFY_DISPBASE(DSPSURF(plane),
Ben Widawskyf343c5f2013-07-05 14:41:04 -07002209 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Paulo Zanonib3dc6852013-11-02 21:07:33 -07002210 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212 } else {
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002216 POSTING_READ(reg);
2217
2218 return 0;
2219}
2220
2221/* Assume fb object is pinned & idle & fenced and just update base pointers */
2222static int
2223intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2225{
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002228
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002231 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002232
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002233 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002234}
2235
Ville Syrjälä96a02912013-02-18 19:08:49 +02002236void intel_display_handle_reset(struct drm_device *dev)
2237{
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct drm_crtc *crtc;
2240
2241 /*
2242 * Flips in the rings have been nuked by the reset,
2243 * so complete all pending flips so that user space
2244 * will get its events and not get stuck.
2245 *
2246 * Also update the base address of all primary
2247 * planes to the the last fb to make sure we're
2248 * showing the correct fb after a reset.
2249 *
2250 * Need to make two loops over the crtcs so that we
2251 * don't try to grab a crtc mutex before the
2252 * pending_flip_queue really got woken up.
2253 */
2254
2255 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257 enum plane plane = intel_crtc->plane;
2258
2259 intel_prepare_page_flip(dev, plane);
2260 intel_finish_page_flip_plane(dev, plane);
2261 }
2262
2263 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266 mutex_lock(&crtc->mutex);
Chris Wilson947fdaadf2013-11-27 12:01:32 +00002267 /*
2268 * FIXME: Once we have proper support for primary planes (and
2269 * disabling them without disabling the entire crtc) allow again
2270 * a NULL crtc->fb.
2271 */
2272 if (intel_crtc->active && crtc->fb)
Ville Syrjälä96a02912013-02-18 19:08:49 +02002273 dev_priv->display.update_plane(crtc, crtc->fb,
2274 crtc->x, crtc->y);
2275 mutex_unlock(&crtc->mutex);
2276 }
2277}
2278
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002279static int
Chris Wilson14667a42012-04-03 17:58:35 +01002280intel_finish_fb(struct drm_framebuffer *old_fb)
2281{
2282 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2283 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2284 bool was_interruptible = dev_priv->mm.interruptible;
2285 int ret;
2286
Chris Wilson14667a42012-04-03 17:58:35 +01002287 /* Big Hammer, we also need to ensure that any pending
2288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289 * current scanout is retired before unpinning the old
2290 * framebuffer.
2291 *
2292 * This should only fail upon a hung GPU, in which case we
2293 * can safely continue.
2294 */
2295 dev_priv->mm.interruptible = false;
2296 ret = i915_gem_object_finish_gpu(obj);
2297 dev_priv->mm.interruptible = was_interruptible;
2298
2299 return ret;
2300}
2301
Ville Syrjälä198598d2012-10-31 17:50:24 +02002302static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303{
2304 struct drm_device *dev = crtc->dev;
2305 struct drm_i915_master_private *master_priv;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307
2308 if (!dev->primary->master)
2309 return;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return;
2314
2315 switch (intel_crtc->pipe) {
2316 case 0:
2317 master_priv->sarea_priv->pipeA_x = x;
2318 master_priv->sarea_priv->pipeA_y = y;
2319 break;
2320 case 1:
2321 master_priv->sarea_priv->pipeB_x = x;
2322 master_priv->sarea_priv->pipeB_y = y;
2323 break;
2324 default:
2325 break;
2326 }
2327}
2328
Chris Wilson14667a42012-04-03 17:58:35 +01002329static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002330intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002331 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002332{
2333 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002334 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002336 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002337 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002338
2339 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002340 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002341 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002342 return 0;
2343 }
2344
Ben Widawsky7eb552a2013-03-13 14:05:41 -07002345 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03002346 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347 plane_name(intel_crtc->plane),
2348 INTEL_INFO(dev)->num_pipes);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002349 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002350 }
2351
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002352 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002353 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002354 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002355 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002356 if (ret != 0) {
2357 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002358 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002359 return ret;
2360 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002361
Damien Lespiaubb2043d2013-09-30 14:21:49 +01002362 /*
2363 * Update pipe size and adjust fitter if needed: the reason for this is
2364 * that in compute_mode_changes we check the native mode (not the pfit
2365 * mode) to see if we can flip rather than do a full mode set. In the
2366 * fastboot case, we'll flip, but if we don't update the pipesrc and
2367 * pfit state, we'll end up with a big fb scanned out into the wrong
2368 * sized surface.
2369 *
2370 * To fix this properly, we need to hoist the checks up into
2371 * compute_mode_changes (or above), check the actual pfit state and
2372 * whether the platform allows pfit disable with pipe active, and only
2373 * then update the pipesrc and pfit state, even on the flip path.
2374 */
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002375 if (i915_fastboot) {
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002376 const struct drm_display_mode *adjusted_mode =
2377 &intel_crtc->config.adjusted_mode;
2378
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002379 I915_WRITE(PIPESRC(intel_crtc->pipe),
Damien Lespiaud7bf63f2013-09-30 14:21:50 +01002380 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2381 (adjusted_mode->crtc_vdisplay - 1));
Chris Wilsonfd4daa92013-08-27 17:04:17 +01002382 if (!intel_crtc->config.pch_pfit.enabled &&
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002383 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2384 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2385 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2386 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2387 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2388 }
Jesse Barnes0637d602013-12-19 10:48:01 -08002389 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2390 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
Jesse Barnes4d6a3e62013-06-26 01:38:18 +03002391 }
2392
Daniel Vetter94352cf2012-07-05 22:51:56 +02002393 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002394 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002395 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002396 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002397 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002398 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002399 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002400
Daniel Vetter94352cf2012-07-05 22:51:56 +02002401 old_fb = crtc->fb;
2402 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002403 crtc->x = x;
2404 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002405
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002406 if (old_fb) {
Daniel Vetterd7697ee2013-06-02 17:23:01 +02002407 if (intel_crtc->active && old_fb != fb)
2408 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002409 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002410 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002411
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002412 intel_update_fbc(dev);
Rodrigo Vivi49065572013-07-11 18:45:05 -03002413 intel_edp_psr_update(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002414 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002415
Ville Syrjälä198598d2012-10-31 17:50:24 +02002416 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002417
2418 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002419}
2420
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002421static void intel_fdi_normal_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
2427 u32 reg, temp;
2428
2429 /* enable normal train */
2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002432 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002433 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2434 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002435 } else {
2436 temp &= ~FDI_LINK_TRAIN_NONE;
2437 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002438 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002439 I915_WRITE(reg, temp);
2440
2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
2443 if (HAS_PCH_CPT(dev)) {
2444 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2445 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2446 } else {
2447 temp &= ~FDI_LINK_TRAIN_NONE;
2448 temp |= FDI_LINK_TRAIN_NONE;
2449 }
2450 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2451
2452 /* wait one idle pattern time */
2453 POSTING_READ(reg);
2454 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002455
2456 /* IVB wants error correction enabled */
2457 if (IS_IVYBRIDGE(dev))
2458 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2459 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002460}
2461
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002462static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
Daniel Vetter1e833f42013-02-19 22:31:57 +01002463{
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01002464 return crtc->base.enabled && crtc->active &&
2465 crtc->config.has_pch_encoder;
Daniel Vetter1e833f42013-02-19 22:31:57 +01002466}
2467
Daniel Vetter01a415f2012-10-27 15:58:40 +02002468static void ivb_modeset_global_resources(struct drm_device *dev)
2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
Daniel Vetter1e833f42013-02-19 22:31:57 +01002477 /*
2478 * When everything is off disable fdi C so that we could enable fdi B
2479 * with all lanes. Note that we don't care about enabled pipes without
2480 * an enabled pch encoder.
2481 */
2482 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2483 !pipe_has_enabled_pch(pipe_C_crtc)) {
Daniel Vetter01a415f2012-10-27 15:58:40 +02002484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2486
2487 temp = I915_READ(SOUTH_CHICKEN1);
2488 temp &= ~FDI_BC_BIFURCATION_SELECT;
2489 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490 I915_WRITE(SOUTH_CHICKEN1, temp);
2491 }
2492}
2493
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002494/* The FDI link training functions for ILK/Ibexpeak. */
2495static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2496{
2497 struct drm_device *dev = crtc->dev;
2498 struct drm_i915_private *dev_priv = dev->dev_private;
2499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2500 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002501 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002502 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002503
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002504 /* FDI needs bits from pipe & plane first */
2505 assert_pipe_enabled(dev_priv, pipe);
2506 assert_plane_enabled(dev_priv, plane);
2507
Adam Jacksone1a44742010-06-25 15:32:14 -04002508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002514 I915_WRITE(reg, temp);
2515 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002516 udelay(150);
2517
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002518 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002519 reg = FDI_TX_CTL(pipe);
2520 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002521 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2522 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002525 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526
Chris Wilson5eddb702010-09-11 13:48:45 +01002527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2532
2533 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002534 udelay(150);
2535
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002536 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2538 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2539 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002540
Chris Wilson5eddb702010-09-11 13:48:45 +01002541 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002542 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002543 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546 if ((temp & FDI_RX_BIT_LOCK)) {
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002549 break;
2550 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002551 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002552 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002553 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002554
2555 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002560 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002561
Chris Wilson5eddb702010-09-11 13:48:45 +01002562 reg = FDI_RX_CTL(pipe);
2563 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002569 udelay(150);
2570
Chris Wilson5eddb702010-09-11 13:48:45 +01002571 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002572 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002573 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575
2576 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002577 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002578 DRM_DEBUG_KMS("FDI train 2 done.\n");
2579 break;
2580 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002581 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002582 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002583 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002584
2585 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002586
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002587}
2588
Akshay Joshi0206e352011-08-16 15:34:10 -04002589static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002590 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2591 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2593 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2594};
2595
2596/* The FDI link training functions for SNB/Cougarpoint. */
2597static void gen6_fdi_link_train(struct drm_crtc *crtc)
2598{
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002603 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002604
Adam Jacksone1a44742010-06-25 15:32:14 -04002605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002607 reg = FDI_RX_IMR(pipe);
2608 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002609 temp &= ~FDI_RX_SYMBOL_LOCK;
2610 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002614 udelay(150);
2615
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002616 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002617 reg = FDI_TX_CTL(pipe);
2618 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002619 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002621 temp &= ~FDI_LINK_TRAIN_NONE;
2622 temp |= FDI_LINK_TRAIN_PATTERN_1;
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 /* SNB-B */
2625 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002627
Daniel Vetterd74cf322012-10-26 10:58:13 +02002628 I915_WRITE(FDI_RX_MISC(pipe),
2629 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2630
Chris Wilson5eddb702010-09-11 13:48:45 +01002631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002633 if (HAS_PCH_CPT(dev)) {
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636 } else {
2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_1;
2639 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002643 udelay(150);
2644
Akshay Joshi0206e352011-08-16 15:34:10 -04002645 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002653 udelay(500);
2654
Sean Paulfa37d392012-03-02 12:53:39 -05002655 for (retry = 0; retry < 5; retry++) {
2656 reg = FDI_RX_IIR(pipe);
2657 temp = I915_READ(reg);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659 if (temp & FDI_RX_BIT_LOCK) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002665 }
Sean Paulfa37d392012-03-02 12:53:39 -05002666 if (retry < 5)
2667 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002668 }
2669 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002670 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002671
2672 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002675 temp &= ~FDI_LINK_TRAIN_NONE;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2;
2677 if (IS_GEN6(dev)) {
2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 /* SNB-B */
2680 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2681 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002682 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002683
Chris Wilson5eddb702010-09-11 13:48:45 +01002684 reg = FDI_RX_CTL(pipe);
2685 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002686 if (HAS_PCH_CPT(dev)) {
2687 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2689 } else {
2690 temp &= ~FDI_LINK_TRAIN_NONE;
2691 temp |= FDI_LINK_TRAIN_PATTERN_2;
2692 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002693 I915_WRITE(reg, temp);
2694
2695 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002696 udelay(150);
2697
Akshay Joshi0206e352011-08-16 15:34:10 -04002698 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002699 reg = FDI_TX_CTL(pipe);
2700 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002706 udelay(500);
2707
Sean Paulfa37d392012-03-02 12:53:39 -05002708 for (retry = 0; retry < 5; retry++) {
2709 reg = FDI_RX_IIR(pipe);
2710 temp = I915_READ(reg);
2711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2712 if (temp & FDI_RX_SYMBOL_LOCK) {
2713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2714 DRM_DEBUG_KMS("FDI train 2 done.\n");
2715 break;
2716 }
2717 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002718 }
Sean Paulfa37d392012-03-02 12:53:39 -05002719 if (retry < 5)
2720 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002721 }
2722 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002723 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002724
2725 DRM_DEBUG_KMS("FDI train done.\n");
2726}
2727
Jesse Barnes357555c2011-04-28 15:09:55 -07002728/* Manual link training for Ivy Bridge A0 parts */
2729static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2730{
2731 struct drm_device *dev = crtc->dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2734 int pipe = intel_crtc->pipe;
Jesse Barnes139ccd32013-08-19 11:04:55 -07002735 u32 reg, temp, i, j;
Jesse Barnes357555c2011-04-28 15:09:55 -07002736
2737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2738 for train result */
2739 reg = FDI_RX_IMR(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_RX_SYMBOL_LOCK;
2742 temp &= ~FDI_RX_BIT_LOCK;
2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
2746 udelay(150);
2747
Daniel Vetter01a415f2012-10-27 15:58:40 +02002748 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749 I915_READ(FDI_RX_IIR(pipe)));
2750
Jesse Barnes139ccd32013-08-19 11:04:55 -07002751 /* Try each vswing and preemphasis setting twice before moving on */
2752 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2753 /* disable first in case we need to retry */
Jesse Barnes357555c2011-04-28 15:09:55 -07002754 reg = FDI_TX_CTL(pipe);
2755 temp = I915_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07002756 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2757 temp &= ~FDI_TX_ENABLE;
2758 I915_WRITE(reg, temp);
2759
2760 reg = FDI_RX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 temp &= ~FDI_LINK_TRAIN_AUTO;
2763 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2764 temp &= ~FDI_RX_ENABLE;
2765 I915_WRITE(reg, temp);
2766
2767 /* enable CPU FDI TX and PCH FDI RX */
2768 reg = FDI_TX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2771 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2772 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
Jesse Barnes357555c2011-04-28 15:09:55 -07002773 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
Jesse Barnes139ccd32013-08-19 11:04:55 -07002774 temp |= snb_b_fdi_train_param[j/2];
2775 temp |= FDI_COMPOSITE_SYNC;
2776 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2777
2778 I915_WRITE(FDI_RX_MISC(pipe),
2779 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2780
2781 reg = FDI_RX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2784 temp |= FDI_COMPOSITE_SYNC;
2785 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2786
2787 POSTING_READ(reg);
2788 udelay(1); /* should be 0.5us */
2789
2790 for (i = 0; i < 4; i++) {
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2794
2795 if (temp & FDI_RX_BIT_LOCK ||
2796 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2799 i);
2800 break;
2801 }
2802 udelay(1); /* should be 0.5us */
2803 }
2804 if (i == 4) {
2805 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2806 continue;
2807 }
2808
2809 /* Train 2 */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2813 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2814 I915_WRITE(reg, temp);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
Jesse Barnes357555c2011-04-28 15:09:55 -07002820 I915_WRITE(reg, temp);
2821
2822 POSTING_READ(reg);
Jesse Barnes139ccd32013-08-19 11:04:55 -07002823 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07002824
Jesse Barnes139ccd32013-08-19 11:04:55 -07002825 for (i = 0; i < 4; i++) {
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
Jesse Barnes357555c2011-04-28 15:09:55 -07002829
Jesse Barnes139ccd32013-08-19 11:04:55 -07002830 if (temp & FDI_RX_SYMBOL_LOCK ||
2831 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2832 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2833 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2834 i);
2835 goto train_done;
2836 }
2837 udelay(2); /* should be 1.5us */
Jesse Barnes357555c2011-04-28 15:09:55 -07002838 }
Jesse Barnes139ccd32013-08-19 11:04:55 -07002839 if (i == 4)
2840 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
Jesse Barnes357555c2011-04-28 15:09:55 -07002841 }
Jesse Barnes357555c2011-04-28 15:09:55 -07002842
Jesse Barnes139ccd32013-08-19 11:04:55 -07002843train_done:
Jesse Barnes357555c2011-04-28 15:09:55 -07002844 DRM_DEBUG_KMS("FDI train done.\n");
2845}
2846
Daniel Vetter88cefb62012-08-12 19:27:14 +02002847static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002848{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002849 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002850 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002851 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002852 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002853
Jesse Barnesc64e3112010-09-10 11:27:03 -07002854
Jesse Barnes0e23b992010-09-10 11:10:00 -07002855 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002856 reg = FDI_RX_CTL(pipe);
2857 temp = I915_READ(reg);
Daniel Vetter627eb5a2013-04-29 19:33:42 +02002858 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2859 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Chris Wilson5eddb702010-09-11 13:48:45 +01002861 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002864 udelay(200);
2865
2866 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp | FDI_PCDCLK);
2869
2870 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002871 udelay(200);
2872
Paulo Zanoni20749732012-11-23 15:30:38 -02002873 /* Enable CPU FDI TX PLL, always on for Ironlake */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2877 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002878
Paulo Zanoni20749732012-11-23 15:30:38 -02002879 POSTING_READ(reg);
2880 udelay(100);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002881 }
2882}
2883
Daniel Vetter88cefb62012-08-12 19:27:14 +02002884static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2885{
2886 struct drm_device *dev = intel_crtc->base.dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 int pipe = intel_crtc->pipe;
2889 u32 reg, temp;
2890
2891 /* Switch from PCDclk to Rawclk */
2892 reg = FDI_RX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2895
2896 /* Disable CPU FDI TX PLL */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2900
2901 POSTING_READ(reg);
2902 udelay(100);
2903
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2907
2908 /* Wait for the clocks to turn off. */
2909 POSTING_READ(reg);
2910 udelay(100);
2911}
2912
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002913static void ironlake_fdi_disable(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918 int pipe = intel_crtc->pipe;
2919 u32 reg, temp;
2920
2921 /* disable CPU FDI tx and PCH FDI rx */
2922 reg = FDI_TX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2925 POSTING_READ(reg);
2926
2927 reg = FDI_RX_CTL(pipe);
2928 temp = I915_READ(reg);
2929 temp &= ~(0x7 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002930 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002931 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2932
2933 POSTING_READ(reg);
2934 udelay(100);
2935
2936 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002937 if (HAS_PCH_IBX(dev)) {
2938 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002939 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002940
2941 /* still set train pattern 1 */
2942 reg = FDI_TX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 temp &= ~FDI_LINK_TRAIN_NONE;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1;
2946 I915_WRITE(reg, temp);
2947
2948 reg = FDI_RX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 if (HAS_PCH_CPT(dev)) {
2951 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2953 } else {
2954 temp &= ~FDI_LINK_TRAIN_NONE;
2955 temp |= FDI_LINK_TRAIN_PATTERN_1;
2956 }
2957 /* BPC in FDI rx is consistent with that in PIPECONF */
2958 temp &= ~(0x07 << 16);
Daniel Vetterdfd07d72012-12-17 11:21:38 +01002959 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002960 I915_WRITE(reg, temp);
2961
2962 POSTING_READ(reg);
2963 udelay(100);
2964}
2965
Chris Wilson5bb61642012-09-27 21:25:58 +01002966static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä10d83732013-01-29 18:13:34 +02002970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5bb61642012-09-27 21:25:58 +01002971 unsigned long flags;
2972 bool pending;
2973
Ville Syrjälä10d83732013-01-29 18:13:34 +02002974 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2975 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
Chris Wilson5bb61642012-09-27 21:25:58 +01002976 return false;
2977
2978 spin_lock_irqsave(&dev->event_lock, flags);
2979 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2980 spin_unlock_irqrestore(&dev->event_lock, flags);
2981
2982 return pending;
2983}
2984
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002985static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2986{
Chris Wilson0f911282012-04-17 10:05:38 +01002987 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002988 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002989
2990 if (crtc->fb == NULL)
2991 return;
2992
Daniel Vetter2c10d572012-12-20 21:24:07 +01002993 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2994
Chris Wilson5bb61642012-09-27 21:25:58 +01002995 wait_event(dev_priv->pending_flip_queue,
2996 !intel_crtc_has_pending_flip(crtc));
2997
Chris Wilson0f911282012-04-17 10:05:38 +01002998 mutex_lock(&dev->struct_mutex);
2999 intel_finish_fb(crtc->fb);
3000 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003001}
3002
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003003/* Program iCLKIP clock to the desired frequency */
3004static void lpt_program_iclkip(struct drm_crtc *crtc)
3005{
3006 struct drm_device *dev = crtc->dev;
3007 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau241bfc32013-09-25 16:45:37 +01003008 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003009 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3010 u32 temp;
3011
Daniel Vetter09153002012-12-12 14:06:44 +01003012 mutex_lock(&dev_priv->dpio_lock);
3013
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003014 /* It is necessary to ungate the pixclk gate prior to programming
3015 * the divisors, and gate it back when it is done.
3016 */
3017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3018
3019 /* Disable SSCCTL */
3020 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003021 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3022 SBI_SSCCTL_DISABLE,
3023 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003024
3025 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003026 if (clock == 20000) {
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003027 auxdiv = 1;
3028 divsel = 0x41;
3029 phaseinc = 0x20;
3030 } else {
3031 /* The iCLK virtual clock root frequency is in MHz,
Damien Lespiau241bfc32013-09-25 16:45:37 +01003032 * but the adjusted_mode->crtc_clock in in KHz. To get the
3033 * divisors, it is necessary to divide one by another, so we
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003034 * convert the virtual clock precision to KHz here for higher
3035 * precision.
3036 */
3037 u32 iclk_virtual_root_freq = 172800 * 1000;
3038 u32 iclk_pi_range = 64;
3039 u32 desired_divisor, msb_divisor_value, pi_value;
3040
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003041 desired_divisor = (iclk_virtual_root_freq / clock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003042 msb_divisor_value = desired_divisor / iclk_pi_range;
3043 pi_value = desired_divisor % iclk_pi_range;
3044
3045 auxdiv = 0;
3046 divsel = msb_divisor_value - 2;
3047 phaseinc = pi_value;
3048 }
3049
3050 /* This should not happen with any sane values */
3051 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3052 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3053 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3054 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3055
3056 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
Ville Syrjälä12d7cee2013-09-04 18:25:19 +03003057 clock,
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003058 auxdiv,
3059 divsel,
3060 phasedir,
3061 phaseinc);
3062
3063 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003064 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003065 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3066 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3067 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3068 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3069 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3070 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003071 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003072
3073 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003074 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003075 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3076 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003077 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003078
3079 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003080 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003081 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003082 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003083
3084 /* Wait for initialization time */
3085 udelay(24);
3086
3087 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
Daniel Vetter09153002012-12-12 14:06:44 +01003088
3089 mutex_unlock(&dev_priv->dpio_lock);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003090}
3091
Daniel Vetter275f01b22013-05-03 11:49:47 +02003092static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3093 enum pipe pch_transcoder)
3094{
3095 struct drm_device *dev = crtc->base.dev;
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3098
3099 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3100 I915_READ(HTOTAL(cpu_transcoder)));
3101 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3102 I915_READ(HBLANK(cpu_transcoder)));
3103 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3104 I915_READ(HSYNC(cpu_transcoder)));
3105
3106 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3107 I915_READ(VTOTAL(cpu_transcoder)));
3108 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3109 I915_READ(VBLANK(cpu_transcoder)));
3110 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3111 I915_READ(VSYNC(cpu_transcoder)));
3112 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3113 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3114}
3115
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003116static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3117{
3118 struct drm_i915_private *dev_priv = dev->dev_private;
3119 uint32_t temp;
3120
3121 temp = I915_READ(SOUTH_CHICKEN1);
3122 if (temp & FDI_BC_BIFURCATION_SELECT)
3123 return;
3124
3125 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3126 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3127
3128 temp |= FDI_BC_BIFURCATION_SELECT;
3129 DRM_DEBUG_KMS("enabling fdi C rx\n");
3130 I915_WRITE(SOUTH_CHICKEN1, temp);
3131 POSTING_READ(SOUTH_CHICKEN1);
3132}
3133
3134static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3135{
3136 struct drm_device *dev = intel_crtc->base.dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139 switch (intel_crtc->pipe) {
3140 case PIPE_A:
3141 break;
3142 case PIPE_B:
3143 if (intel_crtc->config.fdi_lanes > 2)
3144 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3145 else
3146 cpt_enable_fdi_bc_bifurcation(dev);
3147
3148 break;
3149 case PIPE_C:
3150 cpt_enable_fdi_bc_bifurcation(dev);
3151
3152 break;
3153 default:
3154 BUG();
3155 }
3156}
3157
Jesse Barnesf67a5592011-01-05 10:31:48 -08003158/*
3159 * Enable PCH resources required for PCH ports:
3160 * - PCH PLLs
3161 * - FDI training & RX/TX
3162 * - update transcoder timings
3163 * - DP transcoding bits
3164 * - transcoder
3165 */
3166static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003167{
3168 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003172 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003173
Daniel Vetterab9412b2013-05-03 11:49:46 +02003174 assert_pch_transcoder_disabled(dev_priv, pipe);
Chris Wilsone7e164d2012-05-11 09:21:25 +01003175
Daniel Vetter1fbc0d72013-10-29 12:04:08 +01003176 if (IS_IVYBRIDGE(dev))
3177 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3178
Daniel Vettercd986ab2012-10-26 10:58:12 +02003179 /* Write the TU size bits before fdi link training, so that error
3180 * detection works. */
3181 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3182 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3183
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003184 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003185 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003186
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003187 /* We need to program the right clock selection before writing the pixel
3188 * mutliplier into the DPLL. */
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003189 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003190 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003191
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003192 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003193 temp |= TRANS_DPLL_ENABLE(pipe);
3194 sel = TRANS_DPLLB_SEL(pipe);
Daniel Vettera43f6e02013-06-07 23:10:32 +02003195 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003196 temp |= sel;
3197 else
3198 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003199 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003200 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003201
Daniel Vetter3ad8a202013-06-05 13:34:32 +02003202 /* XXX: pch pll's can be enabled any time before we enable the PCH
3203 * transcoder, and we actually should do this to not upset any PCH
3204 * transcoder that already use the clock when we share it.
3205 *
3206 * Note that enable_shared_dpll tries to do the right thing, but
3207 * get_shared_dpll unconditionally resets the pll - we need that to have
3208 * the right LVDS enable sequence. */
3209 ironlake_enable_shared_dpll(intel_crtc);
3210
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003211 /* set transcoder timing, panel must allow it */
3212 assert_panel_unlocked(dev_priv, pipe);
Daniel Vetter275f01b22013-05-03 11:49:47 +02003213 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003214
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003215 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003216
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003217 /* For PCH DP, enable TRANS_DP_CTL */
3218 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003219 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3220 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Daniel Vetterdfd07d72012-12-17 11:21:38 +01003221 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003222 reg = TRANS_DP_CTL(pipe);
3223 temp = I915_READ(reg);
3224 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003225 TRANS_DP_SYNC_MASK |
3226 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003227 temp |= (TRANS_DP_OUTPUT_ENABLE |
3228 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003229 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003230
3231 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003232 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003233 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003234 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003235
3236 switch (intel_trans_dp_port_sel(crtc)) {
3237 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003238 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003239 break;
3240 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003241 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003242 break;
3243 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003244 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003245 break;
3246 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003247 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003248 }
3249
Chris Wilson5eddb702010-09-11 13:48:45 +01003250 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003251 }
3252
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003253 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003254}
3255
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003256static void lpt_pch_enable(struct drm_crtc *crtc)
3257{
3258 struct drm_device *dev = crtc->dev;
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02003261 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003262
Daniel Vetterab9412b2013-05-03 11:49:46 +02003263 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003264
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003265 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003266
Paulo Zanoni0540e482012-10-31 18:12:40 -02003267 /* Set transcoder timing. */
Daniel Vetter275f01b22013-05-03 11:49:47 +02003268 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003269
Paulo Zanoni937bb612012-10-31 18:12:47 -02003270 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003271}
3272
Daniel Vettere2b78262013-06-07 23:10:03 +02003273static void intel_put_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003274{
Daniel Vettere2b78262013-06-07 23:10:03 +02003275 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003276
3277 if (pll == NULL)
3278 return;
3279
3280 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003281 WARN(1, "bad %s refcount\n", pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003282 return;
3283 }
3284
Daniel Vetterf4a091c2013-06-10 17:28:22 +02003285 if (--pll->refcount == 0) {
3286 WARN_ON(pll->on);
3287 WARN_ON(pll->active);
3288 }
3289
Daniel Vettera43f6e02013-06-07 23:10:32 +02003290 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003291}
3292
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003293static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003294{
Daniel Vettere2b78262013-06-07 23:10:03 +02003295 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3296 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3297 enum intel_dpll_id i;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003298
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003299 if (pll) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003300 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3301 crtc->base.base.id, pll->name);
Daniel Vettere2b78262013-06-07 23:10:03 +02003302 intel_put_shared_dpll(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003303 }
3304
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003305 if (HAS_PCH_IBX(dev_priv->dev)) {
3306 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
Daniel Vetterd94ab062013-07-04 12:01:16 +02003307 i = (enum intel_dpll_id) crtc->pipe;
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003308 pll = &dev_priv->shared_dplls[i];
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003309
Daniel Vetter46edb022013-06-05 13:34:12 +02003310 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3311 crtc->base.base.id, pll->name);
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003312
3313 goto found;
3314 }
3315
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003316 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3317 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003318
3319 /* Only want to check enabled timings first */
3320 if (pll->refcount == 0)
3321 continue;
3322
Daniel Vetterb89a1d32013-06-05 13:34:24 +02003323 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3324 sizeof(pll->hw_state)) == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003325 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
Daniel Vettere2b78262013-06-07 23:10:03 +02003326 crtc->base.base.id,
Daniel Vetter46edb022013-06-05 13:34:12 +02003327 pll->name, pll->refcount, pll->active);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003328
3329 goto found;
3330 }
3331 }
3332
3333 /* Ok no matching timings, maybe there's a free one? */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3335 pll = &dev_priv->shared_dplls[i];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003336 if (pll->refcount == 0) {
Daniel Vetter46edb022013-06-05 13:34:12 +02003337 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3338 crtc->base.base.id, pll->name);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003339 goto found;
3340 }
3341 }
3342
3343 return NULL;
3344
3345found:
Daniel Vettera43f6e02013-06-07 23:10:32 +02003346 crtc->config.shared_dpll = i;
Daniel Vetter46edb022013-06-05 13:34:12 +02003347 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3348 pipe_name(crtc->pipe));
Daniel Vetter66e985c2013-06-05 13:34:20 +02003349
Daniel Vettercdbd2312013-06-05 13:34:03 +02003350 if (pll->active == 0) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02003351 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3352 sizeof(pll->hw_state));
3353
Daniel Vetter46edb022013-06-05 13:34:12 +02003354 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003355 WARN_ON(pll->on);
Daniel Vettere9d69442013-06-05 13:34:15 +02003356 assert_shared_dpll_disabled(dev_priv, pll);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003357
Daniel Vetter15bdd4c2013-06-05 13:34:23 +02003358 pll->mode_set(dev_priv, pll);
Daniel Vettercdbd2312013-06-05 13:34:03 +02003359 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003360 pll->refcount++;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003361
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003362 return pll;
3363}
3364
Daniel Vettera1520312013-05-03 11:49:50 +02003365static void cpt_verify_modeset(struct drm_device *dev, int pipe)
Jesse Barnesd4270e52011-10-11 10:43:02 -07003366{
3367 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003368 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003369 u32 temp;
3370
3371 temp = I915_READ(dslreg);
3372 udelay(500);
3373 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003374 if (wait_for(I915_READ(dslreg) != temp, 5))
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03003375 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
Jesse Barnesd4270e52011-10-11 10:43:02 -07003376 }
3377}
3378
Jesse Barnesb074cec2013-04-25 12:55:02 -07003379static void ironlake_pfit_enable(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 int pipe = crtc->pipe;
3384
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003385 if (crtc->config.pch_pfit.enabled) {
Jesse Barnesb074cec2013-04-25 12:55:02 -07003386 /* Force use of hard-coded filter coefficients
3387 * as some pre-programmed values are broken,
3388 * e.g. x201.
3389 */
3390 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3391 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392 PF_PIPE_SEL_IVB(pipe));
3393 else
3394 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3395 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3396 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
Jesse Barnes040484a2011-01-03 12:14:26 -08003397 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003398}
3399
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003400static void intel_enable_planes(struct drm_crtc *crtc)
3401{
3402 struct drm_device *dev = crtc->dev;
3403 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3404 struct intel_plane *intel_plane;
3405
3406 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3407 if (intel_plane->pipe == pipe)
3408 intel_plane_restore(&intel_plane->base);
3409}
3410
3411static void intel_disable_planes(struct drm_crtc *crtc)
3412{
3413 struct drm_device *dev = crtc->dev;
3414 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3415 struct intel_plane *intel_plane;
3416
3417 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3418 if (intel_plane->pipe == pipe)
3419 intel_plane_disable(&intel_plane->base);
3420}
3421
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003422void hsw_enable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003423{
3424 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3425
3426 if (!crtc->config.ips_enabled)
3427 return;
3428
3429 /* We can only enable IPS after we enable a plane and wait for a vblank.
3430 * We guarantee that the plane is enabled by calling intel_enable_ips
3431 * only after intel_enable_plane. And intel_enable_plane already waits
3432 * for a vblank, so all we need to do here is to enable the IPS bit. */
3433 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003434 if (IS_BROADWELL(crtc->base.dev)) {
3435 mutex_lock(&dev_priv->rps.hw_lock);
3436 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3437 mutex_unlock(&dev_priv->rps.hw_lock);
3438 /* Quoting Art Runyan: "its not safe to expect any particular
3439 * value in IPS_CTL bit 31 after enabling IPS through the
Jesse Barnese59150d2014-01-07 13:30:45 -08003440 * mailbox." Moreover, the mailbox may return a bogus state,
3441 * so we need to just enable it and continue on.
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003442 */
3443 } else {
3444 I915_WRITE(IPS_CTL, IPS_ENABLE);
3445 /* The bit only becomes 1 in the next vblank, so this wait here
3446 * is essentially intel_wait_for_vblank. If we don't have this
3447 * and don't wait for vblanks until the end of crtc_enable, then
3448 * the HW state readout code will complain that the expected
3449 * IPS_CTL value is not the one we read. */
3450 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3451 DRM_ERROR("Timed out waiting for IPS enable\n");
3452 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003453}
3454
Ville Syrjälä20bc86732013-10-01 18:02:17 +03003455void hsw_disable_ips(struct intel_crtc *crtc)
Paulo Zanonid77e4532013-09-24 13:52:55 -03003456{
3457 struct drm_device *dev = crtc->base.dev;
3458 struct drm_i915_private *dev_priv = dev->dev_private;
3459
3460 if (!crtc->config.ips_enabled)
3461 return;
3462
3463 assert_plane_enabled(dev_priv, crtc->plane);
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003464 if (IS_BROADWELL(crtc->base.dev)) {
3465 mutex_lock(&dev_priv->rps.hw_lock);
3466 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3467 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnese59150d2014-01-07 13:30:45 -08003468 } else {
Ben Widawsky2a114cc2013-11-02 21:07:47 -07003469 I915_WRITE(IPS_CTL, 0);
Jesse Barnese59150d2014-01-07 13:30:45 -08003470 POSTING_READ(IPS_CTL);
3471 }
Paulo Zanonid77e4532013-09-24 13:52:55 -03003472
3473 /* We need to wait for a vblank before we can disable the plane. */
3474 intel_wait_for_vblank(dev, crtc->pipe);
3475}
3476
3477/** Loads the palette/gamma unit for the CRTC with the prepared values */
3478static void intel_crtc_load_lut(struct drm_crtc *crtc)
3479{
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 enum pipe pipe = intel_crtc->pipe;
3484 int palreg = PALETTE(pipe);
3485 int i;
3486 bool reenable_ips = false;
3487
3488 /* The clocks have to be on to load the palette. */
3489 if (!crtc->enabled || !intel_crtc->active)
3490 return;
3491
3492 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3494 assert_dsi_pll_enabled(dev_priv);
3495 else
3496 assert_pll_enabled(dev_priv, pipe);
3497 }
3498
3499 /* use legacy palette for Ironlake */
3500 if (HAS_PCH_SPLIT(dev))
3501 palreg = LGC_PALETTE(pipe);
3502
3503 /* Workaround : Do not read or write the pipe palette/gamma data while
3504 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3505 */
Paulo Zanoni41e6fc42014-01-08 17:26:31 -02003506 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
Paulo Zanonid77e4532013-09-24 13:52:55 -03003507 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3508 GAMMA_MODE_MODE_SPLIT)) {
3509 hsw_disable_ips(intel_crtc);
3510 reenable_ips = true;
3511 }
3512
3513 for (i = 0; i < 256; i++) {
3514 I915_WRITE(palreg + 4 * i,
3515 (intel_crtc->lut_r[i] << 16) |
3516 (intel_crtc->lut_g[i] << 8) |
3517 intel_crtc->lut_b[i]);
3518 }
3519
3520 if (reenable_ips)
3521 hsw_enable_ips(intel_crtc);
3522}
3523
Jesse Barnesf67a5592011-01-05 10:31:48 -08003524static void ironlake_crtc_enable(struct drm_crtc *crtc)
3525{
3526 struct drm_device *dev = crtc->dev;
3527 struct drm_i915_private *dev_priv = dev->dev_private;
3528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003529 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003530 int pipe = intel_crtc->pipe;
3531 int plane = intel_crtc->plane;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003532
Daniel Vetter08a48462012-07-02 11:43:47 +02003533 WARN_ON(!crtc->enabled);
3534
Jesse Barnesf67a5592011-01-05 10:31:48 -08003535 if (intel_crtc->active)
3536 return;
3537
3538 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003539
3540 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3541 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3542
Daniel Vetterf6736a12013-06-05 13:34:30 +02003543 for_each_encoder_on_crtc(dev, crtc, encoder)
Daniel Vetter952735e2013-06-05 13:34:27 +02003544 if (encoder->pre_enable)
3545 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003546
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003547 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003548 /* Note: FDI PLL enabling _must_ be done before we enable the
3549 * cpu pipes, hence this is separate from all the other fdi/pch
3550 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003551 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003552 } else {
3553 assert_fdi_tx_disabled(dev_priv, pipe);
3554 assert_fdi_rx_disabled(dev_priv, pipe);
3555 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003556
Jesse Barnesb074cec2013-04-25 12:55:02 -07003557 ironlake_pfit_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003558
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003559 /*
3560 * On ILK+ LUT must be loaded before the pipe is running but with
3561 * clocks enabled
3562 */
3563 intel_crtc_load_lut(crtc);
3564
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003565 intel_update_watermarks(crtc);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003566 intel_enable_pipe(dev_priv, pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03003567 intel_crtc->config.has_pch_encoder, false);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003568 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003569 intel_enable_planes(crtc);
Ville Syrjälä5c38d482013-06-04 13:49:00 +03003570 intel_crtc_update_cursor(crtc, true);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003571
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003572 if (intel_crtc->config.has_pch_encoder)
Jesse Barnesf67a5592011-01-05 10:31:48 -08003573 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003574
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003575 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003576 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003577 mutex_unlock(&dev->struct_mutex);
3578
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003579 for_each_encoder_on_crtc(dev, crtc, encoder)
3580 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003581
3582 if (HAS_PCH_CPT(dev))
Daniel Vettera1520312013-05-03 11:49:50 +02003583 cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003584
3585 /*
3586 * There seems to be a race in PCH platform hw (at least on some
3587 * outputs) where an enabled pipe still completes any pageflip right
3588 * away (as if the pipe is off) instead of waiting for vblank. As soon
3589 * as the first vblank happend, everything works as expected. Hence just
3590 * wait for one vblank before returning to avoid strange things
3591 * happening.
3592 */
3593 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003594}
3595
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003596/* IPS only exists on ULT machines and is tied to pipe A. */
3597static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3598{
Damien Lespiauf5adf942013-06-24 18:29:34 +01003599 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003600}
3601
Ville Syrjälädda9a662013-09-19 17:00:37 -03003602static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3603{
3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607 int pipe = intel_crtc->pipe;
3608 int plane = intel_crtc->plane;
3609
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003610 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003611 intel_enable_planes(crtc);
3612 intel_crtc_update_cursor(crtc, true);
3613
3614 hsw_enable_ips(intel_crtc);
3615
3616 mutex_lock(&dev->struct_mutex);
3617 intel_update_fbc(dev);
3618 mutex_unlock(&dev->struct_mutex);
3619}
3620
3621static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3622{
3623 struct drm_device *dev = crtc->dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 int pipe = intel_crtc->pipe;
3627 int plane = intel_crtc->plane;
3628
3629 intel_crtc_wait_for_pending_flips(crtc);
3630 drm_vblank_off(dev, pipe);
3631
3632 /* FBC must be disabled before disabling the plane on HSW. */
3633 if (dev_priv->fbc.plane == plane)
3634 intel_disable_fbc(dev);
3635
3636 hsw_disable_ips(intel_crtc);
3637
3638 intel_crtc_update_cursor(crtc, false);
3639 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003640 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003641}
3642
Paulo Zanonie4916942013-09-20 16:21:19 -03003643/*
3644 * This implements the workaround described in the "notes" section of the mode
3645 * set sequence documentation. When going from no pipes or single pipe to
3646 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3647 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3648 */
3649static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3650{
3651 struct drm_device *dev = crtc->base.dev;
3652 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3653
3654 /* We want to get the other_active_crtc only if there's only 1 other
3655 * active crtc. */
3656 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3657 if (!crtc_it->active || crtc_it == crtc)
3658 continue;
3659
3660 if (other_active_crtc)
3661 return;
3662
3663 other_active_crtc = crtc_it;
3664 }
3665 if (!other_active_crtc)
3666 return;
3667
3668 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3669 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3670}
3671
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003672static void haswell_crtc_enable(struct drm_crtc *crtc)
3673{
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct intel_encoder *encoder;
3678 int pipe = intel_crtc->pipe;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003679
3680 WARN_ON(!crtc->enabled);
3681
3682 if (intel_crtc->active)
3683 return;
3684
3685 intel_crtc->active = true;
Paulo Zanoni86642812013-04-12 17:57:57 -03003686
3687 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3688 if (intel_crtc->config.has_pch_encoder)
3689 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3690
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003691 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni04945642012-11-01 21:00:59 -02003692 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003693
3694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 if (encoder->pre_enable)
3696 encoder->pre_enable(encoder);
3697
Paulo Zanoni1f544382012-10-24 11:32:00 -02003698 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003699
Jesse Barnesb074cec2013-04-25 12:55:02 -07003700 ironlake_pfit_enable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003701
3702 /*
3703 * On ILK+ LUT must be loaded before the pipe is running but with
3704 * clocks enabled
3705 */
3706 intel_crtc_load_lut(crtc);
3707
Paulo Zanoni1f544382012-10-24 11:32:00 -02003708 intel_ddi_set_pipe_settings(crtc);
Damien Lespiau8228c252013-03-07 15:30:27 +00003709 intel_ddi_enable_transcoder_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003710
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03003711 intel_update_watermarks(crtc);
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003712 intel_enable_pipe(dev_priv, pipe,
Jani Nikula23538ef2013-08-27 15:12:22 +03003713 intel_crtc->config.has_pch_encoder, false);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03003714
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01003715 if (intel_crtc->config.has_pch_encoder)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003716 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003717
Jani Nikula8807e552013-08-30 19:40:32 +03003718 for_each_encoder_on_crtc(dev, crtc, encoder) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003719 encoder->enable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03003720 intel_opregion_notify_encoder(encoder, true);
3721 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003722
Paulo Zanonie4916942013-09-20 16:21:19 -03003723 /* If we change the relative order between pipe/planes enabling, we need
3724 * to change the workaround. */
3725 haswell_mode_set_planes_workaround(intel_crtc);
Ville Syrjälädda9a662013-09-19 17:00:37 -03003726 haswell_crtc_enable_planes(crtc);
3727
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003728 /*
3729 * There seems to be a race in PCH platform hw (at least on some
3730 * outputs) where an enabled pipe still completes any pageflip right
3731 * away (as if the pipe is off) instead of waiting for vblank. As soon
3732 * as the first vblank happend, everything works as expected. Hence just
3733 * wait for one vblank before returning to avoid strange things
3734 * happening.
3735 */
3736 intel_wait_for_vblank(dev, intel_crtc->pipe);
3737}
3738
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003739static void ironlake_pfit_disable(struct intel_crtc *crtc)
3740{
3741 struct drm_device *dev = crtc->base.dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 int pipe = crtc->pipe;
3744
3745 /* To avoid upsetting the power well on haswell only disable the pfit if
3746 * it's in use. The hw state code will make sure we get this right. */
Chris Wilsonfd4daa92013-08-27 17:04:17 +01003747 if (crtc->config.pch_pfit.enabled) {
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003748 I915_WRITE(PF_CTL(pipe), 0);
3749 I915_WRITE(PF_WIN_POS(pipe), 0);
3750 I915_WRITE(PF_WIN_SZ(pipe), 0);
3751 }
3752}
3753
Jesse Barnes6be4a602010-09-10 10:26:01 -07003754static void ironlake_crtc_disable(struct drm_crtc *crtc)
3755{
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003759 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003760 int pipe = intel_crtc->pipe;
3761 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003762 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003763
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003764
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003765 if (!intel_crtc->active)
3766 return;
3767
Daniel Vetterea9d7582012-07-10 10:42:52 +02003768 for_each_encoder_on_crtc(dev, crtc, encoder)
3769 encoder->disable(encoder);
3770
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003771 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003772 drm_vblank_off(dev, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003773
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07003774 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01003775 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003776
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003777 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03003778 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03003779 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03003780
Daniel Vetterd925c592013-06-05 13:34:04 +02003781 if (intel_crtc->config.has_pch_encoder)
3782 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3783
Jesse Barnesb24e7172011-01-04 15:09:30 -08003784 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003785
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003786 ironlake_pfit_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003787
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003788 for_each_encoder_on_crtc(dev, crtc, encoder)
3789 if (encoder->post_disable)
3790 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003791
Daniel Vetterd925c592013-06-05 13:34:04 +02003792 if (intel_crtc->config.has_pch_encoder) {
3793 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003794
Daniel Vetterd925c592013-06-05 13:34:04 +02003795 ironlake_disable_pch_transcoder(dev_priv, pipe);
3796 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003797
Daniel Vetterd925c592013-06-05 13:34:04 +02003798 if (HAS_PCH_CPT(dev)) {
3799 /* disable TRANS_DP_CTL */
3800 reg = TRANS_DP_CTL(pipe);
3801 temp = I915_READ(reg);
3802 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3803 TRANS_DP_PORT_SEL_MASK);
3804 temp |= TRANS_DP_PORT_SEL_NONE;
3805 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003806
Daniel Vetterd925c592013-06-05 13:34:04 +02003807 /* disable DPLL_SEL */
3808 temp = I915_READ(PCH_DPLL_SEL);
Daniel Vetter11887392013-06-05 13:34:09 +02003809 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
Daniel Vetterd925c592013-06-05 13:34:04 +02003810 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003811 }
Daniel Vetterd925c592013-06-05 13:34:04 +02003812
3813 /* disable PCH DPLL */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003814 intel_disable_shared_dpll(intel_crtc);
Daniel Vetterd925c592013-06-05 13:34:04 +02003815
3816 ironlake_fdi_pll_disable(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003817 }
3818
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003819 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003820 intel_update_watermarks(crtc);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003821
3822 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003823 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003824 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003825}
3826
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003827static void haswell_crtc_disable(struct drm_crtc *crtc)
3828{
3829 struct drm_device *dev = crtc->dev;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3832 struct intel_encoder *encoder;
3833 int pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02003834 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003835
3836 if (!intel_crtc->active)
3837 return;
3838
Ville Syrjälädda9a662013-09-19 17:00:37 -03003839 haswell_crtc_disable_planes(crtc);
3840
Jani Nikula8807e552013-08-30 19:40:32 +03003841 for_each_encoder_on_crtc(dev, crtc, encoder) {
3842 intel_opregion_notify_encoder(encoder, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003843 encoder->disable(encoder);
Jani Nikula8807e552013-08-30 19:40:32 +03003844 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003845
Paulo Zanoni86642812013-04-12 17:57:57 -03003846 if (intel_crtc->config.has_pch_encoder)
3847 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003848 intel_disable_pipe(dev_priv, pipe);
3849
Paulo Zanoniad80a812012-10-24 16:06:19 -02003850 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003851
Daniel Vetter3f8dce32013-05-08 10:36:30 +02003852 ironlake_pfit_disable(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003853
Paulo Zanoni1f544382012-10-24 11:32:00 -02003854 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003855
3856 for_each_encoder_on_crtc(dev, crtc, encoder)
3857 if (encoder->post_disable)
3858 encoder->post_disable(encoder);
3859
Daniel Vetter88adfff2013-03-28 10:42:01 +01003860 if (intel_crtc->config.has_pch_encoder) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003861 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni86642812013-04-12 17:57:57 -03003862 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003863 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003864 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003865
3866 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03003867 intel_update_watermarks(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003868
3869 mutex_lock(&dev->struct_mutex);
3870 intel_update_fbc(dev);
3871 mutex_unlock(&dev->struct_mutex);
3872}
3873
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003874static void ironlake_crtc_off(struct drm_crtc *crtc)
3875{
3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vettere72f9fb2013-06-05 13:34:06 +02003877 intel_put_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003878}
3879
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003880static void haswell_crtc_off(struct drm_crtc *crtc)
3881{
3882 intel_ddi_put_crtc_pll(crtc);
3883}
3884
Daniel Vetter02e792f2009-09-15 22:57:34 +02003885static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3886{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003887 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003888 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003889 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003890
Chris Wilson23f09ce2010-08-12 13:53:37 +01003891 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003892 dev_priv->mm.interruptible = false;
3893 (void) intel_overlay_switch_off(intel_crtc->overlay);
3894 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003895 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003896 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003897
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003898 /* Let userspace switch the overlay on again. In most cases userspace
3899 * has to recompute where to put it anyway.
3900 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003901}
3902
Egbert Eich61bc95c2013-03-04 09:24:38 -05003903/**
3904 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3905 * cursor plane briefly if not already running after enabling the display
3906 * plane.
3907 * This workaround avoids occasional blank screens when self refresh is
3908 * enabled.
3909 */
3910static void
3911g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3912{
3913 u32 cntl = I915_READ(CURCNTR(pipe));
3914
3915 if ((cntl & CURSOR_MODE) == 0) {
3916 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3917
3918 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3919 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3920 intel_wait_for_vblank(dev_priv->dev, pipe);
3921 I915_WRITE(CURCNTR(pipe), cntl);
3922 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3923 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3924 }
3925}
3926
Jesse Barnes2dd24552013-04-25 12:55:01 -07003927static void i9xx_pfit_enable(struct intel_crtc *crtc)
3928{
3929 struct drm_device *dev = crtc->base.dev;
3930 struct drm_i915_private *dev_priv = dev->dev_private;
3931 struct intel_crtc_config *pipe_config = &crtc->config;
3932
Daniel Vetter328d8e82013-05-08 10:36:31 +02003933 if (!crtc->config.gmch_pfit.control)
Jesse Barnes2dd24552013-04-25 12:55:01 -07003934 return;
3935
Daniel Vetterc0b03412013-05-28 12:05:54 +02003936 /*
3937 * The panel fitter should only be adjusted whilst the pipe is disabled,
3938 * according to register description and PRM.
3939 */
Jesse Barnes2dd24552013-04-25 12:55:01 -07003940 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3941 assert_pipe_disabled(dev_priv, crtc->pipe);
3942
Jesse Barnesb074cec2013-04-25 12:55:02 -07003943 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3944 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
Daniel Vetter5a80c452013-04-25 22:52:18 +02003945
3946 /* Border color in case we don't scale up to the full screen. Black by
3947 * default, change to something else for debugging. */
3948 I915_WRITE(BCLRPAT(crtc->pipe), 0);
Jesse Barnes2dd24552013-04-25 12:55:01 -07003949}
3950
Jesse Barnes586f49d2013-11-04 16:06:59 -08003951int valleyview_get_vco(struct drm_i915_private *dev_priv)
Jesse Barnes30a970c2013-11-04 13:48:12 -08003952{
Jesse Barnes586f49d2013-11-04 16:06:59 -08003953 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
Jesse Barnes30a970c2013-11-04 13:48:12 -08003954
Jesse Barnes586f49d2013-11-04 16:06:59 -08003955 /* Obtain SKU information */
3956 mutex_lock(&dev_priv->dpio_lock);
3957 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3958 CCK_FUSE_HPLL_FREQ_MASK;
3959 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes30a970c2013-11-04 13:48:12 -08003960
Jesse Barnes586f49d2013-11-04 16:06:59 -08003961 return vco_freq[hpll_freq];
Jesse Barnes30a970c2013-11-04 13:48:12 -08003962}
3963
3964/* Adjust CDclk dividers to allow high res or save power if possible */
3965static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3966{
3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968 u32 val, cmd;
3969
3970 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3971 cmd = 2;
3972 else if (cdclk == 266)
3973 cmd = 1;
3974 else
3975 cmd = 0;
3976
3977 mutex_lock(&dev_priv->rps.hw_lock);
3978 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3979 val &= ~DSPFREQGUAR_MASK;
3980 val |= (cmd << DSPFREQGUAR_SHIFT);
3981 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3982 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3983 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3984 50)) {
3985 DRM_ERROR("timed out waiting for CDclk change\n");
3986 }
3987 mutex_unlock(&dev_priv->rps.hw_lock);
3988
3989 if (cdclk == 400) {
3990 u32 divider, vco;
3991
3992 vco = valleyview_get_vco(dev_priv);
3993 divider = ((vco << 1) / cdclk) - 1;
3994
3995 mutex_lock(&dev_priv->dpio_lock);
3996 /* adjust cdclk divider */
3997 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3998 val &= ~0xf;
3999 val |= divider;
4000 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4001 mutex_unlock(&dev_priv->dpio_lock);
4002 }
4003
4004 mutex_lock(&dev_priv->dpio_lock);
4005 /* adjust self-refresh exit latency value */
4006 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4007 val &= ~0x7f;
4008
4009 /*
4010 * For high bandwidth configs, we set a higher latency in the bunit
4011 * so that the core display fetch happens in time to avoid underruns.
4012 */
4013 if (cdclk == 400)
4014 val |= 4500 / 250; /* 4.5 usec */
4015 else
4016 val |= 3000 / 250; /* 3.0 usec */
4017 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4018 mutex_unlock(&dev_priv->dpio_lock);
4019
4020 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4021 intel_i2c_reset(dev);
4022}
4023
4024static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4025{
4026 int cur_cdclk, vco;
4027 int divider;
4028
4029 vco = valleyview_get_vco(dev_priv);
4030
4031 mutex_lock(&dev_priv->dpio_lock);
4032 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4033 mutex_unlock(&dev_priv->dpio_lock);
4034
4035 divider &= 0xf;
4036
4037 cur_cdclk = (vco << 1) / (divider + 1);
4038
4039 return cur_cdclk;
4040}
4041
4042static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4043 int max_pixclk)
4044{
4045 int cur_cdclk;
4046
4047 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4048
4049 /*
4050 * Really only a few cases to deal with, as only 4 CDclks are supported:
4051 * 200MHz
4052 * 267MHz
4053 * 320MHz
4054 * 400MHz
4055 * So we check to see whether we're above 90% of the lower bin and
4056 * adjust if needed.
4057 */
4058 if (max_pixclk > 288000) {
4059 return 400;
4060 } else if (max_pixclk > 240000) {
4061 return 320;
4062 } else
4063 return 266;
4064 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4065}
4066
4067static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4068 unsigned modeset_pipes,
4069 struct intel_crtc_config *pipe_config)
4070{
4071 struct drm_device *dev = dev_priv->dev;
4072 struct intel_crtc *intel_crtc;
4073 int max_pixclk = 0;
4074
4075 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4076 base.head) {
4077 if (modeset_pipes & (1 << intel_crtc->pipe))
4078 max_pixclk = max(max_pixclk,
4079 pipe_config->adjusted_mode.crtc_clock);
4080 else if (intel_crtc->base.enabled)
4081 max_pixclk = max(max_pixclk,
4082 intel_crtc->config.adjusted_mode.crtc_clock);
4083 }
4084
4085 return max_pixclk;
4086}
4087
4088static void valleyview_modeset_global_pipes(struct drm_device *dev,
4089 unsigned *prepare_pipes,
4090 unsigned modeset_pipes,
4091 struct intel_crtc_config *pipe_config)
4092{
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 struct intel_crtc *intel_crtc;
4095 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4096 pipe_config);
4097 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4098
4099 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4100 return;
4101
4102 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4103 base.head)
4104 if (intel_crtc->base.enabled)
4105 *prepare_pipes |= (1 << intel_crtc->pipe);
4106}
4107
4108static void valleyview_modeset_global_resources(struct drm_device *dev)
4109{
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4112 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4113 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4114
4115 if (req_cdclk != cur_cdclk)
4116 valleyview_set_cdclk(dev, req_cdclk);
4117}
4118
Jesse Barnes89b667f2013-04-18 14:51:36 -07004119static void valleyview_crtc_enable(struct drm_crtc *crtc)
4120{
4121 struct drm_device *dev = crtc->dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4124 struct intel_encoder *encoder;
4125 int pipe = intel_crtc->pipe;
4126 int plane = intel_crtc->plane;
Jani Nikula23538ef2013-08-27 15:12:22 +03004127 bool is_dsi;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004128
4129 WARN_ON(!crtc->enabled);
4130
4131 if (intel_crtc->active)
4132 return;
4133
4134 intel_crtc->active = true;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004135
Jesse Barnes89b667f2013-04-18 14:51:36 -07004136 for_each_encoder_on_crtc(dev, crtc, encoder)
4137 if (encoder->pre_pll_enable)
4138 encoder->pre_pll_enable(encoder);
4139
Jani Nikula23538ef2013-08-27 15:12:22 +03004140 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4141
Jani Nikulae9fd1c02013-08-27 15:12:23 +03004142 if (!is_dsi)
4143 vlv_enable_pll(intel_crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004144
4145 for_each_encoder_on_crtc(dev, crtc, encoder)
4146 if (encoder->pre_enable)
4147 encoder->pre_enable(encoder);
4148
Jesse Barnes2dd24552013-04-25 12:55:01 -07004149 i9xx_pfit_enable(intel_crtc);
4150
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004151 intel_crtc_load_lut(crtc);
4152
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004153 intel_update_watermarks(crtc);
Jani Nikula23538ef2013-08-27 15:12:22 +03004154 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004155 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004156 intel_enable_planes(crtc);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004157 intel_crtc_update_cursor(crtc, true);
4158
Ville Syrjäläf440eb12013-06-04 13:49:01 +03004159 intel_update_fbc(dev);
Jani Nikula50049452013-07-30 12:20:32 +03004160
4161 for_each_encoder_on_crtc(dev, crtc, encoder)
4162 encoder->enable(encoder);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004163}
4164
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004165static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004166{
4167 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08004168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004170 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004171 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004172 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08004173
Daniel Vetter08a48462012-07-02 11:43:47 +02004174 WARN_ON(!crtc->enabled);
4175
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004176 if (intel_crtc->active)
4177 return;
4178
4179 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01004180
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02004181 for_each_encoder_on_crtc(dev, crtc, encoder)
Mika Kuoppala9d6d9f12013-02-08 16:35:38 +02004182 if (encoder->pre_enable)
4183 encoder->pre_enable(encoder);
4184
Daniel Vetterf6736a12013-06-05 13:34:30 +02004185 i9xx_enable_pll(intel_crtc);
4186
Jesse Barnes2dd24552013-04-25 12:55:01 -07004187 i9xx_pfit_enable(intel_crtc);
4188
Ville Syrjälä63cbb072013-06-04 13:48:59 +03004189 intel_crtc_load_lut(crtc);
4190
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004191 intel_update_watermarks(crtc);
Jani Nikula23538ef2013-08-27 15:12:22 +03004192 intel_enable_pipe(dev_priv, pipe, false, false);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004193 intel_enable_primary_plane(dev_priv, plane, pipe);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004194 intel_enable_planes(crtc);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03004195 /* The fixup needs to happen before cursor is enabled */
Egbert Eich61bc95c2013-03-04 09:24:38 -05004196 if (IS_G4X(dev))
4197 g4x_fixup_plane(dev_priv, pipe);
Ville Syrjälä22e407d2013-06-07 18:52:24 +03004198 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004199
4200 /* Give the overlay scaler a chance to enable if it's on this pipe */
4201 intel_crtc_dpms_overlay(intel_crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004202
Ville Syrjäläf440eb12013-06-04 13:49:01 +03004203 intel_update_fbc(dev);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004204
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02004205 for_each_encoder_on_crtc(dev, crtc, encoder)
4206 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004207}
4208
Daniel Vetter87476d62013-04-11 16:29:06 +02004209static void i9xx_pfit_disable(struct intel_crtc *crtc)
4210{
4211 struct drm_device *dev = crtc->base.dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter328d8e82013-05-08 10:36:31 +02004213
4214 if (!crtc->config.gmch_pfit.control)
4215 return;
Daniel Vetter87476d62013-04-11 16:29:06 +02004216
4217 assert_pipe_disabled(dev_priv, crtc->pipe);
4218
Daniel Vetter328d8e82013-05-08 10:36:31 +02004219 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4220 I915_READ(PFIT_CONTROL));
4221 I915_WRITE(PFIT_CONTROL, 0);
Daniel Vetter87476d62013-04-11 16:29:06 +02004222}
4223
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004224static void i9xx_crtc_disable(struct drm_crtc *crtc)
4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004229 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004230 int pipe = intel_crtc->pipe;
4231 int plane = intel_crtc->plane;
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02004232
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004233 if (!intel_crtc->active)
4234 return;
4235
Daniel Vetterea9d7582012-07-10 10:42:52 +02004236 for_each_encoder_on_crtc(dev, crtc, encoder)
4237 encoder->disable(encoder);
4238
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004239 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01004240 intel_crtc_wait_for_pending_flips(crtc);
4241 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004242
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07004243 if (dev_priv->fbc.plane == plane)
Chris Wilson973d04f2011-07-08 12:22:37 +01004244 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004245
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03004246 intel_crtc_dpms_overlay(intel_crtc, false);
4247 intel_crtc_update_cursor(crtc, false);
Ville Syrjäläbb53d4a2013-06-04 13:49:04 +03004248 intel_disable_planes(crtc);
Ville Syrjäläd1de00e2013-10-01 18:02:19 +03004249 intel_disable_primary_plane(dev_priv, plane, pipe);
Ville Syrjälä0d5b8c62013-06-04 13:49:02 +03004250
Jesse Barnesb24e7172011-01-04 15:09:30 -08004251 intel_disable_pipe(dev_priv, pipe);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004252
Daniel Vetter87476d62013-04-11 16:29:06 +02004253 i9xx_pfit_disable(intel_crtc);
Mika Kuoppala24a1f162013-02-08 16:35:37 +02004254
Jesse Barnes89b667f2013-04-18 14:51:36 -07004255 for_each_encoder_on_crtc(dev, crtc, encoder)
4256 if (encoder->post_disable)
4257 encoder->post_disable(encoder);
4258
Jesse Barnesf6071162013-10-01 10:41:38 -07004259 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4260 vlv_disable_pll(dev_priv, pipe);
4261 else if (!IS_VALLEYVIEW(dev))
Jani Nikulae9fd1c02013-08-27 15:12:23 +03004262 i9xx_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004263
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004264 intel_crtc->active = false;
Ville Syrjälä46ba6142013-09-10 11:40:40 +03004265 intel_update_watermarks(crtc);
Ville Syrjäläf37fcc22013-09-10 11:39:55 +03004266
Chris Wilson6b383a72010-09-13 13:54:26 +01004267 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07004268}
4269
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004270static void i9xx_crtc_off(struct drm_crtc *crtc)
4271{
4272}
4273
Daniel Vetter976f8a22012-07-08 22:34:21 +02004274static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4275 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004276{
4277 struct drm_device *dev = crtc->dev;
4278 struct drm_i915_master_private *master_priv;
4279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004281
4282 if (!dev->primary->master)
4283 return;
4284
4285 master_priv = dev->primary->master->driver_priv;
4286 if (!master_priv->sarea_priv)
4287 return;
4288
Jesse Barnes79e53942008-11-07 14:24:08 -08004289 switch (pipe) {
4290 case 0:
4291 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4292 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4293 break;
4294 case 1:
4295 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4296 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4297 break;
4298 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004299 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004300 break;
4301 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004302}
4303
Daniel Vetter976f8a22012-07-08 22:34:21 +02004304/**
4305 * Sets the power management mode of the pipe and plane.
4306 */
4307void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01004308{
Chris Wilsoncdd59982010-09-08 16:30:16 +01004309 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004310 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004311 struct intel_encoder *intel_encoder;
4312 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004313
Daniel Vetter976f8a22012-07-08 22:34:21 +02004314 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4315 enable |= intel_encoder->connectors_active;
4316
4317 if (enable)
4318 dev_priv->display.crtc_enable(crtc);
4319 else
4320 dev_priv->display.crtc_disable(crtc);
4321
4322 intel_crtc_update_sarea(crtc, enable);
4323}
4324
Daniel Vetter976f8a22012-07-08 22:34:21 +02004325static void intel_crtc_disable(struct drm_crtc *crtc)
4326{
4327 struct drm_device *dev = crtc->dev;
4328 struct drm_connector *connector;
4329 struct drm_i915_private *dev_priv = dev->dev_private;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08004330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004331
4332 /* crtc should still be enabled when we disable it. */
4333 WARN_ON(!crtc->enabled);
4334
4335 dev_priv->display.crtc_disable(crtc);
Paulo Zanonic77bf562013-05-03 12:15:40 -03004336 intel_crtc->eld_vld = false;
Daniel Vetter976f8a22012-07-08 22:34:21 +02004337 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004338 dev_priv->display.off(crtc);
4339
Chris Wilson931872f2012-01-16 23:01:13 +00004340 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
Jani Nikula93ce0ba2013-09-13 11:03:08 +03004341 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
Chris Wilson931872f2012-01-16 23:01:13 +00004342 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004343
4344 if (crtc->fb) {
4345 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01004346 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01004347 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02004348 crtc->fb = NULL;
4349 }
4350
4351 /* Update computed state. */
4352 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4353 if (!connector->encoder || !connector->encoder->crtc)
4354 continue;
4355
4356 if (connector->encoder->crtc != crtc)
4357 continue;
4358
4359 connector->dpms = DRM_MODE_DPMS_OFF;
4360 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01004361 }
4362}
4363
Chris Wilsonea5b2132010-08-04 13:50:23 +01004364void intel_encoder_destroy(struct drm_encoder *encoder)
4365{
Chris Wilson4ef69c72010-09-09 15:14:28 +01004366 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01004367
Chris Wilsonea5b2132010-08-04 13:50:23 +01004368 drm_encoder_cleanup(encoder);
4369 kfree(intel_encoder);
4370}
4371
Damien Lespiau92373292013-08-08 22:28:57 +01004372/* Simple dpms helper for encoders with just one connector, no cloning and only
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004373 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4374 * state of the entire output pipe. */
Damien Lespiau92373292013-08-08 22:28:57 +01004375static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004376{
4377 if (mode == DRM_MODE_DPMS_ON) {
4378 encoder->connectors_active = true;
4379
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004380 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004381 } else {
4382 encoder->connectors_active = false;
4383
Daniel Vetterb2cabb02012-07-01 22:42:24 +02004384 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004385 }
4386}
4387
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004388/* Cross check the actual hw state with our own modeset state tracking (and it's
4389 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02004390static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004391{
4392 if (connector->get_hw_state(connector)) {
4393 struct intel_encoder *encoder = connector->encoder;
4394 struct drm_crtc *crtc;
4395 bool encoder_enabled;
4396 enum pipe pipe;
4397
4398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4399 connector->base.base.id,
4400 drm_get_connector_name(&connector->base));
4401
4402 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4403 "wrong connector dpms state\n");
4404 WARN(connector->base.encoder != &encoder->base,
4405 "active connector not linked to encoder\n");
4406 WARN(!encoder->connectors_active,
4407 "encoder->connectors_active not set\n");
4408
4409 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4410 WARN(!encoder_enabled, "encoder not enabled\n");
4411 if (WARN_ON(!encoder->base.crtc))
4412 return;
4413
4414 crtc = encoder->base.crtc;
4415
4416 WARN(!crtc->enabled, "crtc not enabled\n");
4417 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4418 WARN(pipe != to_intel_crtc(crtc)->pipe,
4419 "encoder active on the wrong pipe\n");
4420 }
4421}
4422
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004423/* Even simpler default implementation, if there's really no special case to
4424 * consider. */
4425void intel_connector_dpms(struct drm_connector *connector, int mode)
4426{
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004427 /* All the simple cases only support two dpms states. */
4428 if (mode != DRM_MODE_DPMS_ON)
4429 mode = DRM_MODE_DPMS_OFF;
4430
4431 if (mode == connector->dpms)
4432 return;
4433
4434 connector->dpms = mode;
4435
4436 /* Only need to change hw state when actually enabled */
Chris Wilsonc9976dc2013-09-29 19:15:07 +01004437 if (connector->encoder)
4438 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02004439
Daniel Vetterb9805142012-08-31 17:37:33 +02004440 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02004441}
4442
Daniel Vetterf0947c32012-07-02 13:10:34 +02004443/* Simple connector->get_hw_state implementation for encoders that support only
4444 * one connector and no cloning and hence the encoder state determines the state
4445 * of the connector. */
4446bool intel_connector_get_hw_state(struct intel_connector *connector)
4447{
Daniel Vetter24929352012-07-02 20:28:59 +02004448 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02004449 struct intel_encoder *encoder = connector->encoder;
4450
4451 return encoder->get_hw_state(encoder, &pipe);
4452}
4453
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004454static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4455 struct intel_crtc_config *pipe_config)
4456{
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 struct intel_crtc *pipe_B_crtc =
4459 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4460
4461 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4462 pipe_name(pipe), pipe_config->fdi_lanes);
4463 if (pipe_config->fdi_lanes > 4) {
4464 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4465 pipe_name(pipe), pipe_config->fdi_lanes);
4466 return false;
4467 }
4468
Paulo Zanonibafb6552013-11-02 21:07:44 -07004469 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004470 if (pipe_config->fdi_lanes > 2) {
4471 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4472 pipe_config->fdi_lanes);
4473 return false;
4474 } else {
4475 return true;
4476 }
4477 }
4478
4479 if (INTEL_INFO(dev)->num_pipes == 2)
4480 return true;
4481
4482 /* Ivybridge 3 pipe is really complicated */
4483 switch (pipe) {
4484 case PIPE_A:
4485 return true;
4486 case PIPE_B:
4487 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4488 pipe_config->fdi_lanes > 2) {
4489 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4490 pipe_name(pipe), pipe_config->fdi_lanes);
4491 return false;
4492 }
4493 return true;
4494 case PIPE_C:
Daniel Vetter1e833f42013-02-19 22:31:57 +01004495 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004496 pipe_B_crtc->config.fdi_lanes <= 2) {
4497 if (pipe_config->fdi_lanes > 2) {
4498 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4499 pipe_name(pipe), pipe_config->fdi_lanes);
4500 return false;
4501 }
4502 } else {
4503 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4504 return false;
4505 }
4506 return true;
4507 default:
4508 BUG();
4509 }
4510}
4511
Daniel Vettere29c22c2013-02-21 00:00:16 +01004512#define RETRY 1
4513static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4514 struct intel_crtc_config *pipe_config)
Daniel Vetter877d48d2013-04-19 11:24:43 +02004515{
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004516 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004517 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetterff9a6752013-06-01 17:16:21 +02004518 int lane, link_bw, fdi_dotclock;
Daniel Vettere29c22c2013-02-21 00:00:16 +01004519 bool setup_ok, needs_recompute = false;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004520
Daniel Vettere29c22c2013-02-21 00:00:16 +01004521retry:
Daniel Vetter877d48d2013-04-19 11:24:43 +02004522 /* FDI is a binary signal running at ~2.7GHz, encoding
4523 * each output octet as 10 bits. The actual frequency
4524 * is stored as a divider into a 100MHz clock, and the
4525 * mode pixel clock is stored in units of 1KHz.
4526 * Hence the bw of each lane in terms of the mode signal
4527 * is:
4528 */
4529 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4530
Damien Lespiau241bfc32013-09-25 16:45:37 +01004531 fdi_dotclock = adjusted_mode->crtc_clock;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004532
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004533 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004534 pipe_config->pipe_bpp);
4535
4536 pipe_config->fdi_lanes = lane;
4537
Daniel Vetter2bd89a02013-06-01 17:16:19 +02004538 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
Daniel Vetter877d48d2013-04-19 11:24:43 +02004539 link_bw, &pipe_config->fdi_m_n);
Daniel Vetter1857e1d2013-04-29 19:34:16 +02004540
Daniel Vettere29c22c2013-02-21 00:00:16 +01004541 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4542 intel_crtc->pipe, pipe_config);
4543 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4544 pipe_config->pipe_bpp -= 2*3;
4545 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4546 pipe_config->pipe_bpp);
4547 needs_recompute = true;
4548 pipe_config->bw_constrained = true;
4549
4550 goto retry;
4551 }
4552
4553 if (needs_recompute)
4554 return RETRY;
4555
4556 return setup_ok ? 0 : -EINVAL;
Daniel Vetter877d48d2013-04-19 11:24:43 +02004557}
4558
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004559static void hsw_compute_ips_config(struct intel_crtc *crtc,
4560 struct intel_crtc_config *pipe_config)
4561{
Paulo Zanoni3c4ca582013-05-31 16:33:23 -03004562 pipe_config->ips_enabled = i915_enable_ips &&
4563 hsw_crtc_supports_ips(crtc) &&
Jesse Barnesb6dfdc92013-07-25 10:06:50 -07004564 pipe_config->pipe_bpp <= 24;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004565}
4566
Daniel Vettera43f6e02013-06-07 23:10:32 +02004567static int intel_crtc_compute_config(struct intel_crtc *crtc,
Daniel Vettere29c22c2013-02-21 00:00:16 +01004568 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08004569{
Daniel Vettera43f6e02013-06-07 23:10:32 +02004570 struct drm_device *dev = crtc->base.dev;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01004571 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Chris Wilson89749352010-09-12 18:25:19 +01004572
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004573 /* FIXME should check pixel clock limits on all platforms */
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004574 if (INTEL_INFO(dev)->gen < 4) {
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 int clock_limit =
4577 dev_priv->display.get_display_clock_speed(dev);
4578
4579 /*
4580 * Enable pixel doubling when the dot clock
4581 * is > 90% of the (display) core speed.
4582 *
Ville Syrjäläb397c962013-09-04 18:30:06 +03004583 * GDG double wide on either pipe,
4584 * otherwise pipe A only.
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004585 */
Ville Syrjäläb397c962013-09-04 18:30:06 +03004586 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
Damien Lespiau241bfc32013-09-25 16:45:37 +01004587 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004588 clock_limit *= 2;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03004589 pipe_config->double_wide = true;
Ville Syrjäläad3a4472013-09-04 18:30:04 +03004590 }
4591
Damien Lespiau241bfc32013-09-25 16:45:37 +01004592 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004593 return -EINVAL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004594 }
Chris Wilson89749352010-09-12 18:25:19 +01004595
Ville Syrjälä1d1d0e22013-09-04 18:30:05 +03004596 /*
4597 * Pipe horizontal size must be even in:
4598 * - DVO ganged mode
4599 * - LVDS dual channel mode
4600 * - Double wide pipe
4601 */
4602 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4603 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4604 pipe_config->pipe_src_w &= ~1;
4605
Damien Lespiau8693a822013-05-03 18:48:11 +01004606 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4607 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
Chris Wilson44f46b422012-06-21 13:19:59 +03004608 */
4609 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4610 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
Daniel Vettere29c22c2013-02-21 00:00:16 +01004611 return -EINVAL;
Chris Wilson44f46b422012-06-21 13:19:59 +03004612
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004613 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004614 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
Daniel Vetterbd080ee2013-04-17 20:01:39 +02004615 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
Daniel Vetter5d2d38d2013-03-27 00:45:01 +01004616 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4617 * for lvds. */
4618 pipe_config->pipe_bpp = 8*3;
4619 }
4620
Damien Lespiauf5adf942013-06-24 18:29:34 +01004621 if (HAS_IPS(dev))
Daniel Vettera43f6e02013-06-07 23:10:32 +02004622 hsw_compute_ips_config(crtc, pipe_config);
4623
4624 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4625 * clock survives for now. */
4626 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4627 pipe_config->shared_dpll = crtc->config.shared_dpll;
Paulo Zanoni42db64e2013-05-31 16:33:22 -03004628
Daniel Vetter877d48d2013-04-19 11:24:43 +02004629 if (pipe_config->has_pch_encoder)
Daniel Vettera43f6e02013-06-07 23:10:32 +02004630 return ironlake_fdi_compute_config(crtc, pipe_config);
Daniel Vetter877d48d2013-04-19 11:24:43 +02004631
Daniel Vettere29c22c2013-02-21 00:00:16 +01004632 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004633}
4634
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07004635static int valleyview_get_display_clock_speed(struct drm_device *dev)
4636{
4637 return 400000; /* FIXME */
4638}
4639
Jesse Barnese70236a2009-09-21 10:42:27 -07004640static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08004641{
Jesse Barnese70236a2009-09-21 10:42:27 -07004642 return 400000;
4643}
Jesse Barnes79e53942008-11-07 14:24:08 -08004644
Jesse Barnese70236a2009-09-21 10:42:27 -07004645static int i915_get_display_clock_speed(struct drm_device *dev)
4646{
4647 return 333000;
4648}
Jesse Barnes79e53942008-11-07 14:24:08 -08004649
Jesse Barnese70236a2009-09-21 10:42:27 -07004650static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4651{
4652 return 200000;
4653}
Jesse Barnes79e53942008-11-07 14:24:08 -08004654
Daniel Vetter257a7ff2013-07-26 08:35:42 +02004655static int pnv_get_display_clock_speed(struct drm_device *dev)
4656{
4657 u16 gcfgc = 0;
4658
4659 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4660
4661 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4662 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4663 return 267000;
4664 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4665 return 333000;
4666 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4667 return 444000;
4668 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4669 return 200000;
4670 default:
4671 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4672 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4673 return 133000;
4674 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4675 return 167000;
4676 }
4677}
4678
Jesse Barnese70236a2009-09-21 10:42:27 -07004679static int i915gm_get_display_clock_speed(struct drm_device *dev)
4680{
4681 u16 gcfgc = 0;
4682
4683 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4684
4685 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08004686 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07004687 else {
4688 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4689 case GC_DISPLAY_CLOCK_333_MHZ:
4690 return 333000;
4691 default:
4692 case GC_DISPLAY_CLOCK_190_200_MHZ:
4693 return 190000;
4694 }
4695 }
4696}
Jesse Barnes79e53942008-11-07 14:24:08 -08004697
Jesse Barnese70236a2009-09-21 10:42:27 -07004698static int i865_get_display_clock_speed(struct drm_device *dev)
4699{
4700 return 266000;
4701}
4702
4703static int i855_get_display_clock_speed(struct drm_device *dev)
4704{
4705 u16 hpllcc = 0;
4706 /* Assume that the hardware is in the high speed state. This
4707 * should be the default.
4708 */
4709 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4710 case GC_CLOCK_133_200:
4711 case GC_CLOCK_100_200:
4712 return 200000;
4713 case GC_CLOCK_166_250:
4714 return 250000;
4715 case GC_CLOCK_100_133:
4716 return 133000;
4717 }
4718
4719 /* Shouldn't happen */
4720 return 0;
4721}
4722
4723static int i830_get_display_clock_speed(struct drm_device *dev)
4724{
4725 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004726}
4727
Zhenyu Wang2c072452009-06-05 15:38:42 +08004728static void
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004729intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004730{
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004731 while (*num > DATA_LINK_M_N_MASK ||
4732 *den > DATA_LINK_M_N_MASK) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004733 *num >>= 1;
4734 *den >>= 1;
4735 }
4736}
4737
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004738static void compute_m_n(unsigned int m, unsigned int n,
4739 uint32_t *ret_m, uint32_t *ret_n)
4740{
4741 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4742 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4743 intel_reduce_m_n_ratio(ret_m, ret_n);
4744}
4745
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004746void
4747intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4748 int pixel_clock, int link_clock,
4749 struct intel_link_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004750{
Daniel Vettere69d0bc2012-11-29 15:59:36 +01004751 m_n->tu = 64;
Ville Syrjäläa65851a2013-04-23 15:03:34 +03004752
4753 compute_m_n(bits_per_pixel * pixel_clock,
4754 link_clock * nlanes * 8,
4755 &m_n->gmch_m, &m_n->gmch_n);
4756
4757 compute_m_n(pixel_clock, link_clock,
4758 &m_n->link_m, &m_n->link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004759}
4760
Chris Wilsona7615032011-01-12 17:04:08 +00004761static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4762{
Keith Packard72bbe582011-09-26 16:09:45 -07004763 if (i915_panel_use_ssc >= 0)
4764 return i915_panel_use_ssc != 0;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03004765 return dev_priv->vbt.lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004766 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004767}
4768
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004769static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4770{
4771 struct drm_device *dev = crtc->dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 int refclk;
4774
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004775 if (IS_VALLEYVIEW(dev)) {
Daniel Vetter9a0ea492013-09-16 11:29:34 +02004776 refclk = 100000;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004777 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004778 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02004779 refclk = dev_priv->vbt.lvds_ssc_freq;
4780 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004781 } else if (!IS_GEN2(dev)) {
4782 refclk = 96000;
4783 } else {
4784 refclk = 48000;
4785 }
4786
4787 return refclk;
4788}
4789
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004790static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004791{
Daniel Vetter7df00d72013-05-21 21:54:55 +02004792 return (1 << dpll->n) << 16 | dpll->m2;
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004793}
Daniel Vetterf47709a2013-03-28 10:42:02 +01004794
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004795static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4796{
4797 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004798}
4799
Daniel Vetterf47709a2013-03-28 10:42:02 +01004800static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
Jesse Barnesa7516a02011-12-15 12:30:37 -08004801 intel_clock_t *reduced_clock)
4802{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004803 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004804 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004805 int pipe = crtc->pipe;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004806 u32 fp, fp2 = 0;
4807
4808 if (IS_PINEVIEW(dev)) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004809 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004810 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004811 fp2 = pnv_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004812 } else {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004813 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004814 if (reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02004815 fp2 = i9xx_dpll_compute_fp(reduced_clock);
Jesse Barnesa7516a02011-12-15 12:30:37 -08004816 }
4817
4818 I915_WRITE(FP0(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004819 crtc->config.dpll_hw_state.fp0 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004820
Daniel Vetterf47709a2013-03-28 10:42:02 +01004821 crtc->lowfreq_avail = false;
4822 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Jesse Barnesa7516a02011-12-15 12:30:37 -08004823 reduced_clock && i915_powersave) {
4824 I915_WRITE(FP1(pipe), fp2);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004825 crtc->config.dpll_hw_state.fp1 = fp2;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004826 crtc->lowfreq_avail = true;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004827 } else {
4828 I915_WRITE(FP1(pipe), fp);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02004829 crtc->config.dpll_hw_state.fp1 = fp;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004830 }
4831}
4832
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004833static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4834 pipe)
Jesse Barnes89b667f2013-04-18 14:51:36 -07004835{
4836 u32 reg_val;
4837
4838 /*
4839 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4840 * and set it to a reasonable value instead.
4841 */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004842 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004843 reg_val &= 0xffffff00;
4844 reg_val |= 0x00000030;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004846
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004847 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004848 reg_val &= 0x8cffffff;
4849 reg_val = 0x8c000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004850 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004851
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004852 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004853 reg_val &= 0xffffff00;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004854 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004855
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004856 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004857 reg_val &= 0x00ffffff;
4858 reg_val |= 0xb0000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004859 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004860}
4861
Daniel Vetterb5518422013-05-03 11:49:48 +02004862static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4863 struct intel_link_m_n *m_n)
4864{
4865 struct drm_device *dev = crtc->base.dev;
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 int pipe = crtc->pipe;
4868
Daniel Vettere3b95f12013-05-03 11:49:49 +02004869 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4870 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4871 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4872 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004873}
4874
4875static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4876 struct intel_link_m_n *m_n)
4877{
4878 struct drm_device *dev = crtc->base.dev;
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 int pipe = crtc->pipe;
4881 enum transcoder transcoder = crtc->config.cpu_transcoder;
4882
4883 if (INTEL_INFO(dev)->gen >= 5) {
4884 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4885 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4886 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4887 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4888 } else {
Daniel Vettere3b95f12013-05-03 11:49:49 +02004889 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4890 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4891 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4892 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
Daniel Vetterb5518422013-05-03 11:49:48 +02004893 }
4894}
4895
Daniel Vetter03afc4a2013-04-02 23:42:31 +02004896static void intel_dp_set_m_n(struct intel_crtc *crtc)
4897{
4898 if (crtc->config.has_pch_encoder)
4899 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4900 else
4901 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4902}
4903
Daniel Vetterf47709a2013-03-28 10:42:02 +01004904static void vlv_update_pll(struct intel_crtc *crtc)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004905{
Daniel Vetterf47709a2013-03-28 10:42:02 +01004906 struct drm_device *dev = crtc->base.dev;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004907 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterf47709a2013-03-28 10:42:02 +01004908 int pipe = crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07004909 u32 dpll, mdiv;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004910 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Daniel Vetter198a037f2013-04-19 11:14:37 +02004911 u32 coreclk, reg_val, dpll_md;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004912
Daniel Vetter09153002012-12-12 14:06:44 +01004913 mutex_lock(&dev_priv->dpio_lock);
4914
Daniel Vetterf47709a2013-03-28 10:42:02 +01004915 bestn = crtc->config.dpll.n;
4916 bestm1 = crtc->config.dpll.m1;
4917 bestm2 = crtc->config.dpll.m2;
4918 bestp1 = crtc->config.dpll.p1;
4919 bestp2 = crtc->config.dpll.p2;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004920
Jesse Barnes89b667f2013-04-18 14:51:36 -07004921 /* See eDP HDMI DPIO driver vbios notes doc */
4922
4923 /* PLL B needs special handling */
4924 if (pipe)
Chon Ming Lee5e69f972013-09-05 20:41:49 +08004925 vlv_pllb_recal_opamp(dev_priv, pipe);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004926
4927 /* Set up Tx target for periodic Rcomp update */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004928 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004929
4930 /* Disable target IRef on PLL */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004931 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004932 reg_val &= 0x00ffffff;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004934
4935 /* Disable fast lock */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004936 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004937
4938 /* Set idtafcrecal before PLL is enabled */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004939 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4940 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4941 mdiv |= ((bestn << DPIO_N_SHIFT));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004942 mdiv |= (1 << DPIO_K_SHIFT);
Jesse Barnes7df50802013-05-02 10:48:09 -07004943
4944 /*
4945 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4946 * but we don't support that).
4947 * Note: don't use the DAC post divider as it seems unstable.
4948 */
4949 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004951
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004952 mdiv |= DPIO_ENABLE_CALIBRATION;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004954
Jesse Barnes89b667f2013-04-18 14:51:36 -07004955 /* Set HBR and RBR LPF coefficients */
Daniel Vetterff9a6752013-06-01 17:16:21 +02004956 if (crtc->config.port_clock == 162000 ||
Ville Syrjälä99750bd2013-06-14 14:02:52 +03004957 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
Jesse Barnes89b667f2013-04-18 14:51:36 -07004958 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Ville Syrjälä885b0122013-07-05 19:21:38 +03004960 0x009f0003);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004961 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004963 0x00d0000f);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004964
Jesse Barnes89b667f2013-04-18 14:51:36 -07004965 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4966 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4967 /* Use SSC source */
4968 if (!pipe)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004970 0x0df40000);
4971 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004973 0x0df70000);
4974 } else { /* HDMI or VGA */
4975 /* Use bend source */
4976 if (!pipe)
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004977 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004978 0x0df70000);
4979 else
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004980 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
Jesse Barnes89b667f2013-04-18 14:51:36 -07004981 0x0df40000);
4982 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004983
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004984 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
Jesse Barnes89b667f2013-04-18 14:51:36 -07004985 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4986 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4987 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4988 coreclk |= 0x01000000;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004990
Chon Ming Leeab3c7592013-11-07 10:43:30 +08004991 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
Jesse Barnes89b667f2013-04-18 14:51:36 -07004992
Imre Deake5cbfbf2014-01-09 17:08:16 +02004993 /*
4994 * Enable DPIO clock input. We should never disable the reference
4995 * clock for pipe B, since VGA hotplug / manual detection depends
4996 * on it.
4997 */
Jesse Barnes89b667f2013-04-18 14:51:36 -07004998 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4999 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
Jesse Barnesf6071162013-10-01 10:41:38 -07005000 /* We should never disable this, set it here for state tracking */
5001 if (pipe == PIPE_B)
Jesse Barnes89b667f2013-04-18 14:51:36 -07005002 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005003 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005004 crtc->config.dpll_hw_state.dpll = dpll;
5005
Daniel Vetteref1b4602013-06-01 17:17:04 +02005006 dpll_md = (crtc->config.pixel_multiplier - 1)
5007 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005008 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5009
Daniel Vetterf47709a2013-03-28 10:42:02 +01005010 if (crtc->config.has_dp_encoder)
5011 intel_dp_set_m_n(crtc);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305012
Daniel Vetter09153002012-12-12 14:06:44 +01005013 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07005014}
5015
Daniel Vetterf47709a2013-03-28 10:42:02 +01005016static void i9xx_update_pll(struct intel_crtc *crtc,
5017 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005018 int num_connectors)
5019{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005020 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005021 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005022 u32 dpll;
5023 bool is_sdvo;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005024 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005025
Daniel Vetterf47709a2013-03-28 10:42:02 +01005026 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305027
Daniel Vetterf47709a2013-03-28 10:42:02 +01005028 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5029 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005030
5031 dpll = DPLL_VGA_MODE_DIS;
5032
Daniel Vetterf47709a2013-03-28 10:42:02 +01005033 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005034 dpll |= DPLLB_MODE_LVDS;
5035 else
5036 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01005037
Daniel Vetteref1b4602013-06-01 17:17:04 +02005038 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
Daniel Vetter198a037f2013-04-19 11:14:37 +02005039 dpll |= (crtc->config.pixel_multiplier - 1)
5040 << SDVO_MULTIPLIER_SHIFT_HIRES;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005041 }
Daniel Vetter198a037f2013-04-19 11:14:37 +02005042
5043 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02005044 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter198a037f2013-04-19 11:14:37 +02005045
Daniel Vetterf47709a2013-03-28 10:42:02 +01005046 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
Daniel Vetter4a33e482013-07-06 12:52:05 +02005047 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005048
5049 /* compute bitmask from p1 value */
5050 if (IS_PINEVIEW(dev))
5051 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5052 else {
5053 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5054 if (IS_G4X(dev) && reduced_clock)
5055 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5056 }
5057 switch (clock->p2) {
5058 case 5:
5059 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5060 break;
5061 case 7:
5062 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5063 break;
5064 case 10:
5065 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5066 break;
5067 case 14:
5068 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5069 break;
5070 }
5071 if (INTEL_INFO(dev)->gen >= 4)
5072 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5073
Daniel Vetter09ede542013-04-30 14:01:45 +02005074 if (crtc->config.sdvo_tv_clock)
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005075 dpll |= PLL_REF_INPUT_TVCLKINBC;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005076 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005077 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5078 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5079 else
5080 dpll |= PLL_REF_INPUT_DREFCLK;
5081
5082 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005083 crtc->config.dpll_hw_state.dpll = dpll;
5084
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005085 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetteref1b4602013-06-01 17:17:04 +02005086 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5087 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005088 crtc->config.dpll_hw_state.dpll_md = dpll_md;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005089 }
Daniel Vetter66e3d5c2013-06-16 21:24:16 +02005090
5091 if (crtc->config.has_dp_encoder)
5092 intel_dp_set_m_n(crtc);
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005093}
5094
Daniel Vetterf47709a2013-03-28 10:42:02 +01005095static void i8xx_update_pll(struct intel_crtc *crtc,
Daniel Vetterf47709a2013-03-28 10:42:02 +01005096 intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005097 int num_connectors)
5098{
Daniel Vetterf47709a2013-03-28 10:42:02 +01005099 struct drm_device *dev = crtc->base.dev;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005100 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005101 u32 dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +01005102 struct dpll *clock = &crtc->config.dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005103
Daniel Vetterf47709a2013-03-28 10:42:02 +01005104 i9xx_update_pll_dividers(crtc, reduced_clock);
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305105
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005106 dpll = DPLL_VGA_MODE_DIS;
5107
Daniel Vetterf47709a2013-03-28 10:42:02 +01005108 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005109 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5110 } else {
5111 if (clock->p1 == 2)
5112 dpll |= PLL_P1_DIVIDE_BY_TWO;
5113 else
5114 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5115 if (clock->p2 == 4)
5116 dpll |= PLL_P2_DIVIDE_BY_4;
5117 }
5118
Daniel Vetter4a33e482013-07-06 12:52:05 +02005119 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5120 dpll |= DPLL_DVO_2X_MODE;
5121
Daniel Vetterf47709a2013-03-28 10:42:02 +01005122 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005123 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5124 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5125 else
5126 dpll |= PLL_REF_INPUT_DREFCLK;
5127
5128 dpll |= DPLL_VCO_ENABLE;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005129 crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005130}
5131
Daniel Vetter8a654f32013-06-01 17:16:22 +02005132static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005133{
5134 struct drm_device *dev = intel_crtc->base.dev;
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02005137 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Daniel Vetter8a654f32013-06-01 17:16:22 +02005138 struct drm_display_mode *adjusted_mode =
5139 &intel_crtc->config.adjusted_mode;
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005140 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5141
5142 /* We need to be careful not to changed the adjusted mode, for otherwise
5143 * the hw state checker will get angry at the mismatch. */
5144 crtc_vtotal = adjusted_mode->crtc_vtotal;
5145 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005146
5147 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5148 /* the chip adds 2 halflines automatically */
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005149 crtc_vtotal -= 1;
5150 crtc_vblank_end -= 1;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005151 vsyncshift = adjusted_mode->crtc_hsync_start
5152 - adjusted_mode->crtc_htotal / 2;
5153 } else {
5154 vsyncshift = 0;
5155 }
5156
5157 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005158 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005159
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005160 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005161 (adjusted_mode->crtc_hdisplay - 1) |
5162 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005163 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005164 (adjusted_mode->crtc_hblank_start - 1) |
5165 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005166 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005167 (adjusted_mode->crtc_hsync_start - 1) |
5168 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5169
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005170 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005171 (adjusted_mode->crtc_vdisplay - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005172 ((crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005173 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005174 (adjusted_mode->crtc_vblank_start - 1) |
Daniel Vetter4d8a62e2013-05-03 11:49:51 +02005175 ((crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02005176 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005177 (adjusted_mode->crtc_vsync_start - 1) |
5178 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5179
Paulo Zanonib5e508d2012-10-24 11:34:43 -02005180 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5181 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5182 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5183 * bits. */
5184 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5185 (pipe == PIPE_B || pipe == PIPE_C))
5186 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5187
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005188 /* pipesrc controls the size that is scaled from, which should
5189 * always be the user's requested size.
5190 */
5191 I915_WRITE(PIPESRC(pipe),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005192 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5193 (intel_crtc->config.pipe_src_h - 1));
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005194}
5195
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005196static void intel_get_pipe_timings(struct intel_crtc *crtc,
5197 struct intel_crtc_config *pipe_config)
5198{
5199 struct drm_device *dev = crtc->base.dev;
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5202 uint32_t tmp;
5203
5204 tmp = I915_READ(HTOTAL(cpu_transcoder));
5205 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5206 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5207 tmp = I915_READ(HBLANK(cpu_transcoder));
5208 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5209 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5210 tmp = I915_READ(HSYNC(cpu_transcoder));
5211 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5212 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5213
5214 tmp = I915_READ(VTOTAL(cpu_transcoder));
5215 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5216 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5217 tmp = I915_READ(VBLANK(cpu_transcoder));
5218 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5219 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5220 tmp = I915_READ(VSYNC(cpu_transcoder));
5221 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5222 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5223
5224 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5225 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5226 pipe_config->adjusted_mode.crtc_vtotal += 1;
5227 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5228 }
5229
5230 tmp = I915_READ(PIPESRC(crtc->pipe));
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005231 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5232 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5233
5234 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5235 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005236}
5237
Jesse Barnesbabea612013-06-26 18:57:38 +03005238static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5239 struct intel_crtc_config *pipe_config)
5240{
5241 struct drm_crtc *crtc = &intel_crtc->base;
5242
5243 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5244 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5245 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5246 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5247
5248 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5249 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5250 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5251 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5252
5253 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5254
Damien Lespiau241bfc32013-09-25 16:45:37 +01005255 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
Jesse Barnesbabea612013-06-26 18:57:38 +03005256 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5257}
5258
Daniel Vetter84b046f2013-02-19 18:48:54 +01005259static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5260{
5261 struct drm_device *dev = intel_crtc->base.dev;
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 uint32_t pipeconf;
5264
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005265 pipeconf = 0;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005266
Daniel Vetter67c72a12013-09-24 11:46:14 +02005267 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5268 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5269 pipeconf |= PIPECONF_ENABLE;
5270
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03005271 if (intel_crtc->config.double_wide)
5272 pipeconf |= PIPECONF_DOUBLE_WIDE;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005273
Daniel Vetterff9ce462013-04-24 14:57:17 +02005274 /* only g4x and later have fancy bpc/dither controls */
5275 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
Daniel Vetterff9ce462013-04-24 14:57:17 +02005276 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5277 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5278 pipeconf |= PIPECONF_DITHER_EN |
5279 PIPECONF_DITHER_TYPE_SP;
5280
5281 switch (intel_crtc->config.pipe_bpp) {
5282 case 18:
5283 pipeconf |= PIPECONF_6BPC;
5284 break;
5285 case 24:
5286 pipeconf |= PIPECONF_8BPC;
5287 break;
5288 case 30:
5289 pipeconf |= PIPECONF_10BPC;
5290 break;
5291 default:
5292 /* Case prevented by intel_choose_pipe_bpp_dither. */
5293 BUG();
Daniel Vetter84b046f2013-02-19 18:48:54 +01005294 }
5295 }
5296
5297 if (HAS_PIPE_CXSR(dev)) {
5298 if (intel_crtc->lowfreq_avail) {
5299 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5300 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301 } else {
5302 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Daniel Vetter84b046f2013-02-19 18:48:54 +01005303 }
5304 }
5305
Daniel Vetter84b046f2013-02-19 18:48:54 +01005306 if (!IS_GEN2(dev) &&
5307 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5308 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5309 else
5310 pipeconf |= PIPECONF_PROGRESSIVE;
5311
Daniel Vetter9f11a9e2013-06-13 00:54:58 +02005312 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5313 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä9c8e09b2013-04-02 16:10:09 +03005314
Daniel Vetter84b046f2013-02-19 18:48:54 +01005315 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5316 POSTING_READ(PIPECONF(intel_crtc->pipe));
5317}
5318
Eric Anholtf564048e2011-03-30 13:01:02 -07005319static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
Eric Anholtf564048e2011-03-30 13:01:02 -07005320 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005321 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005322{
5323 struct drm_device *dev = crtc->dev;
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5326 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07005327 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07005328 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005329 intel_clock_t clock, reduced_clock;
Daniel Vetter84b046f2013-02-19 18:48:54 +01005330 u32 dspcntr;
Daniel Vettera16af7212013-04-30 14:01:44 +02005331 bool ok, has_reduced_clock = false;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005332 bool is_lvds = false, is_dsi = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01005333 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005334 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005335 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005336
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005337 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005338 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005339 case INTEL_OUTPUT_LVDS:
5340 is_lvds = true;
5341 break;
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005342 case INTEL_OUTPUT_DSI:
5343 is_dsi = true;
5344 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005345 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005346
Eric Anholtc751ce42010-03-25 11:48:48 -07005347 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005348 }
5349
Jani Nikulaf2335332013-09-13 11:03:09 +03005350 if (is_dsi)
5351 goto skip_dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08005352
Jani Nikulaf2335332013-09-13 11:03:09 +03005353 if (!intel_crtc->config.clock_set) {
5354 refclk = i9xx_get_refclk(crtc, num_connectors);
5355
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005356 /*
5357 * Returns a set of divisors for the desired target clock with
5358 * the given refclk, or FALSE. The returned values represent
5359 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5360 * 2) / p1 / p2.
5361 */
5362 limit = intel_limit(crtc, refclk);
5363 ok = dev_priv->display.find_dpll(limit, crtc,
5364 intel_crtc->config.port_clock,
5365 refclk, NULL, &clock);
Jani Nikulaf2335332013-09-13 11:03:09 +03005366 if (!ok) {
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5368 return -EINVAL;
5369 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005370
Jani Nikulaf2335332013-09-13 11:03:09 +03005371 if (is_lvds && dev_priv->lvds_downclock_avail) {
5372 /*
5373 * Ensure we match the reduced clock's P to the target
5374 * clock. If the clocks don't match, we can't switch
5375 * the display clock by using the FP0/FP1. In such case
5376 * we will disable the LVDS downclock feature.
5377 */
5378 has_reduced_clock =
5379 dev_priv->display.find_dpll(limit, crtc,
5380 dev_priv->lvds_downclock,
5381 refclk, &clock,
5382 &reduced_clock);
5383 }
5384 /* Compat-code for transition, will disappear. */
Daniel Vetterf47709a2013-03-28 10:42:02 +01005385 intel_crtc->config.dpll.n = clock.n;
5386 intel_crtc->config.dpll.m1 = clock.m1;
5387 intel_crtc->config.dpll.m2 = clock.m2;
5388 intel_crtc->config.dpll.p1 = clock.p1;
5389 intel_crtc->config.dpll.p2 = clock.p2;
5390 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005391
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005392 if (IS_GEN2(dev)) {
Daniel Vetter8a654f32013-06-01 17:16:22 +02005393 i8xx_update_pll(intel_crtc,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05305394 has_reduced_clock ? &reduced_clock : NULL,
5395 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005396 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaf2335332013-09-13 11:03:09 +03005397 vlv_update_pll(intel_crtc);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005398 } else {
Daniel Vetterf47709a2013-03-28 10:42:02 +01005399 i9xx_update_pll(intel_crtc,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02005400 has_reduced_clock ? &reduced_clock : NULL,
Jesse Barnes89b667f2013-04-18 14:51:36 -07005401 num_connectors);
Jani Nikulae9fd1c02013-08-27 15:12:23 +03005402 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005403
Jani Nikulaf2335332013-09-13 11:03:09 +03005404skip_dpll:
Eric Anholtf564048e2011-03-30 13:01:02 -07005405 /* Set up the display plane register */
5406 dspcntr = DISPPLANE_GAMMA_ENABLE;
5407
Jesse Barnesda6ecc52013-03-08 10:46:00 -08005408 if (!IS_VALLEYVIEW(dev)) {
5409 if (pipe == 0)
5410 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5411 else
5412 dspcntr |= DISPPLANE_SEL_PIPE_B;
5413 }
Eric Anholtf564048e2011-03-30 13:01:02 -07005414
Daniel Vetter8a654f32013-06-01 17:16:22 +02005415 intel_set_pipe_timings(intel_crtc);
Eric Anholtf564048e2011-03-30 13:01:02 -07005416
5417 /* pipesrc and dspsize control the size that is scaled from,
5418 * which should always be the user's requested size.
5419 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005420 I915_WRITE(DSPSIZE(plane),
Ville Syrjälä37327ab2013-09-04 18:25:28 +03005421 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5422 (intel_crtc->config.pipe_src_w - 1));
Eric Anholt929c77f2011-03-30 13:01:04 -07005423 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07005424
Daniel Vetter84b046f2013-02-19 18:48:54 +01005425 i9xx_set_pipeconf(intel_crtc);
5426
Eric Anholtf564048e2011-03-30 13:01:02 -07005427 I915_WRITE(DSPCNTR(plane), dspcntr);
5428 POSTING_READ(DSPCNTR(plane));
5429
Daniel Vetter94352cf2012-07-05 22:51:56 +02005430 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07005431
Eric Anholtf564048e2011-03-30 13:01:02 -07005432 return ret;
5433}
5434
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005435static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5436 struct intel_crtc_config *pipe_config)
5437{
5438 struct drm_device *dev = crtc->base.dev;
5439 struct drm_i915_private *dev_priv = dev->dev_private;
5440 uint32_t tmp;
5441
Ville Syrjälädc9e7dec2014-01-10 14:06:45 +02005442 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5443 return;
5444
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005445 tmp = I915_READ(PFIT_CONTROL);
Daniel Vetter06922822013-07-11 13:35:40 +02005446 if (!(tmp & PFIT_ENABLE))
5447 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005448
Daniel Vetter06922822013-07-11 13:35:40 +02005449 /* Check whether the pfit is attached to our pipe. */
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005450 if (INTEL_INFO(dev)->gen < 4) {
5451 if (crtc->pipe != PIPE_B)
5452 return;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005453 } else {
5454 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5455 return;
5456 }
5457
Daniel Vetter06922822013-07-11 13:35:40 +02005458 pipe_config->gmch_pfit.control = tmp;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005459 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5460 if (INTEL_INFO(dev)->gen < 5)
5461 pipe_config->gmch_pfit.lvds_border_bits =
5462 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5463}
5464
Jesse Barnesacbec812013-09-20 11:29:32 -07005465static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5466 struct intel_crtc_config *pipe_config)
5467{
5468 struct drm_device *dev = crtc->base.dev;
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 int pipe = pipe_config->cpu_transcoder;
5471 intel_clock_t clock;
5472 u32 mdiv;
Chris Wilson662c6ec2013-09-25 14:24:01 -07005473 int refclk = 100000;
Jesse Barnesacbec812013-09-20 11:29:32 -07005474
5475 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08005476 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
Jesse Barnesacbec812013-09-20 11:29:32 -07005477 mutex_unlock(&dev_priv->dpio_lock);
5478
5479 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5480 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5481 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5482 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5483 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5484
Ville Syrjäläf6466282013-10-14 14:50:31 +03005485 vlv_clock(refclk, &clock);
Jesse Barnesacbec812013-09-20 11:29:32 -07005486
Ville Syrjäläf6466282013-10-14 14:50:31 +03005487 /* clock.dot is the fast clock */
5488 pipe_config->port_clock = clock.dot / 5;
Jesse Barnesacbec812013-09-20 11:29:32 -07005489}
5490
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005491static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5492 struct intel_crtc_config *pipe_config)
5493{
5494 struct drm_device *dev = crtc->base.dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 uint32_t tmp;
5497
Daniel Vettere143a212013-07-04 12:01:15 +02005498 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02005499 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02005500
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005501 tmp = I915_READ(PIPECONF(crtc->pipe));
5502 if (!(tmp & PIPECONF_ENABLE))
5503 return false;
5504
Ville Syrjälä42571ae2013-09-06 23:29:00 +03005505 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5506 switch (tmp & PIPECONF_BPC_MASK) {
5507 case PIPECONF_6BPC:
5508 pipe_config->pipe_bpp = 18;
5509 break;
5510 case PIPECONF_8BPC:
5511 pipe_config->pipe_bpp = 24;
5512 break;
5513 case PIPECONF_10BPC:
5514 pipe_config->pipe_bpp = 30;
5515 break;
5516 default:
5517 break;
5518 }
5519 }
5520
Ville Syrjälä282740f2013-09-04 18:30:03 +03005521 if (INTEL_INFO(dev)->gen < 4)
5522 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5523
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02005524 intel_get_pipe_timings(crtc, pipe_config);
5525
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02005526 i9xx_get_pfit_config(crtc, pipe_config);
5527
Daniel Vetter6c49f242013-06-06 12:45:25 +02005528 if (INTEL_INFO(dev)->gen >= 4) {
5529 tmp = I915_READ(DPLL_MD(crtc->pipe));
5530 pipe_config->pixel_multiplier =
5531 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5532 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005533 pipe_config->dpll_hw_state.dpll_md = tmp;
Daniel Vetter6c49f242013-06-06 12:45:25 +02005534 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5535 tmp = I915_READ(DPLL(crtc->pipe));
5536 pipe_config->pixel_multiplier =
5537 ((tmp & SDVO_MULTIPLIER_MASK)
5538 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5539 } else {
5540 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5541 * port and will be fixed up in the encoder->get_config
5542 * function. */
5543 pipe_config->pixel_multiplier = 1;
5544 }
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005545 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5546 if (!IS_VALLEYVIEW(dev)) {
5547 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5548 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
Ville Syrjälä165e9012013-06-26 17:44:15 +03005549 } else {
5550 /* Mask out read-only status bits. */
5551 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5552 DPLL_PORTC_READY_MASK |
5553 DPLL_PORTB_READY_MASK);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02005554 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02005555
Jesse Barnesacbec812013-09-20 11:29:32 -07005556 if (IS_VALLEYVIEW(dev))
5557 vlv_crtc_clock_get(crtc, pipe_config);
5558 else
5559 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä18442d02013-09-13 16:00:08 +03005560
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01005561 return true;
5562}
5563
Paulo Zanonidde86e22012-12-01 12:04:25 -02005564static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07005565{
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005568 struct intel_encoder *encoder;
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005569 u32 val, final;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005570 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005571 bool has_cpu_edp = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005572 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07005573 bool has_ck505 = false;
5574 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005575
5576 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07005577 list_for_each_entry(encoder, &mode_config->encoder_list,
5578 base.head) {
5579 switch (encoder->type) {
5580 case INTEL_OUTPUT_LVDS:
5581 has_panel = true;
5582 has_lvds = true;
5583 break;
5584 case INTEL_OUTPUT_EDP:
5585 has_panel = true;
Imre Deak2de69052013-05-08 13:14:04 +03005586 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
Keith Packard199e5d72011-09-22 12:01:57 -07005587 has_cpu_edp = true;
5588 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005589 }
5590 }
5591
Keith Packard99eb6a02011-09-26 14:29:12 -07005592 if (HAS_PCH_IBX(dev)) {
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005593 has_ck505 = dev_priv->vbt.display_clock_mode;
Keith Packard99eb6a02011-09-26 14:29:12 -07005594 can_ssc = has_ck505;
5595 } else {
5596 has_ck505 = false;
5597 can_ssc = true;
5598 }
5599
Imre Deak2de69052013-05-08 13:14:04 +03005600 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5601 has_panel, has_lvds, has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005602
5603 /* Ironlake: try to setup display ref clock before DPLL
5604 * enabling. This is only under driver's control after
5605 * PCH B stepping, previous chipset stepping should be
5606 * ignoring this setting.
5607 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005608 val = I915_READ(PCH_DREF_CONTROL);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005609
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005610 /* As we must carefully and slowly disable/enable each source in turn,
5611 * compute the final state we want first and check if we need to
5612 * make any changes at all.
5613 */
5614 final = val;
5615 final &= ~DREF_NONSPREAD_SOURCE_MASK;
Keith Packard99eb6a02011-09-26 14:29:12 -07005616 if (has_ck505)
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005617 final |= DREF_NONSPREAD_CK505_ENABLE;
Keith Packard99eb6a02011-09-26 14:29:12 -07005618 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005619 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5620
5621 final &= ~DREF_SSC_SOURCE_MASK;
5622 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5623 final &= ~DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005624
Keith Packard199e5d72011-09-22 12:01:57 -07005625 if (has_panel) {
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005626 final |= DREF_SSC_SOURCE_ENABLE;
5627
5628 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5629 final |= DREF_SSC1_ENABLE;
5630
5631 if (has_cpu_edp) {
5632 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5633 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5634 else
5635 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5636 } else
5637 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5638 } else {
5639 final |= DREF_SSC_SOURCE_DISABLE;
5640 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5641 }
5642
5643 if (final == val)
5644 return;
5645
5646 /* Always enable nonspread source */
5647 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5648
5649 if (has_ck505)
5650 val |= DREF_NONSPREAD_CK505_ENABLE;
5651 else
5652 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5653
5654 if (has_panel) {
5655 val &= ~DREF_SSC_SOURCE_MASK;
5656 val |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005657
Keith Packard199e5d72011-09-22 12:01:57 -07005658 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005659 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005660 DRM_DEBUG_KMS("Using SSC on panel\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005661 val |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02005662 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005663 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005664
5665 /* Get SSC going before enabling the outputs */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005666 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005667 POSTING_READ(PCH_DREF_CONTROL);
5668 udelay(200);
5669
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005670 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005671
5672 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005673 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005674 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005675 DRM_DEBUG_KMS("Using SSC on eDP\n");
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005676 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005677 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005678 else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005679 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005680 } else
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005681 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005682
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005683 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005684 POSTING_READ(PCH_DREF_CONTROL);
5685 udelay(200);
5686 } else {
5687 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5688
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005689 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Keith Packard199e5d72011-09-22 12:01:57 -07005690
5691 /* Turn off CPU output */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005692 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005693
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005694 I915_WRITE(PCH_DREF_CONTROL, val);
Keith Packard199e5d72011-09-22 12:01:57 -07005695 POSTING_READ(PCH_DREF_CONTROL);
5696 udelay(200);
5697
5698 /* Turn off the SSC source */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005699 val &= ~DREF_SSC_SOURCE_MASK;
5700 val |= DREF_SSC_SOURCE_DISABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005701
5702 /* Turn off SSC1 */
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005703 val &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07005704
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005705 I915_WRITE(PCH_DREF_CONTROL, val);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005706 POSTING_READ(PCH_DREF_CONTROL);
5707 udelay(200);
5708 }
Chris Wilson74cfd7a2013-03-26 16:33:04 -07005709
5710 BUG_ON(val != final);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005711}
5712
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005713static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
Paulo Zanonidde86e22012-12-01 12:04:25 -02005714{
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005715 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02005716
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005717 tmp = I915_READ(SOUTH_CHICKEN2);
5718 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5719 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005720
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005721 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5722 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5723 DRM_ERROR("FDI mPHY reset assert timeout\n");
Paulo Zanonidde86e22012-12-01 12:04:25 -02005724
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005725 tmp = I915_READ(SOUTH_CHICKEN2);
5726 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5727 I915_WRITE(SOUTH_CHICKEN2, tmp);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005728
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005729 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5730 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5731 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005732}
5733
5734/* WaMPhyProgramming:hsw */
5735static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5736{
5737 uint32_t tmp;
Paulo Zanonidde86e22012-12-01 12:04:25 -02005738
5739 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5740 tmp &= ~(0xFF << 24);
5741 tmp |= (0x12 << 24);
5742 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5743
Paulo Zanonidde86e22012-12-01 12:04:25 -02005744 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5745 tmp |= (1 << 11);
5746 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5747
5748 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5749 tmp |= (1 << 11);
5750 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5751
Paulo Zanonidde86e22012-12-01 12:04:25 -02005752 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5753 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5754 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5755
5756 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5757 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5758 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5759
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005760 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5761 tmp &= ~(7 << 13);
5762 tmp |= (5 << 13);
5763 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005764
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005765 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5766 tmp &= ~(7 << 13);
5767 tmp |= (5 << 13);
5768 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005769
5770 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5771 tmp &= ~0xFF;
5772 tmp |= 0x1C;
5773 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5774
5775 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5776 tmp &= ~0xFF;
5777 tmp |= 0x1C;
5778 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5779
5780 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5781 tmp &= ~(0xFF << 16);
5782 tmp |= (0x1C << 16);
5783 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5784
5785 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5786 tmp &= ~(0xFF << 16);
5787 tmp |= (0x1C << 16);
5788 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5789
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005790 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5791 tmp |= (1 << 27);
5792 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005793
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005794 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5795 tmp |= (1 << 27);
5796 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005797
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005798 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5799 tmp &= ~(0xF << 28);
5800 tmp |= (4 << 28);
5801 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005802
Paulo Zanoni0ff066a2013-07-12 14:19:36 -03005803 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5804 tmp &= ~(0xF << 28);
5805 tmp |= (4 << 28);
5806 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005807}
5808
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005809/* Implements 3 different sequences from BSpec chapter "Display iCLK
5810 * Programming" based on the parameters passed:
5811 * - Sequence to enable CLKOUT_DP
5812 * - Sequence to enable CLKOUT_DP without spread
5813 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5814 */
5815static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5816 bool with_fdi)
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005817{
5818 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005819 uint32_t reg, tmp;
5820
5821 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5822 with_spread = true;
5823 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5824 with_fdi, "LP PCH doesn't have FDI\n"))
5825 with_fdi = false;
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005826
5827 mutex_lock(&dev_priv->dpio_lock);
5828
5829 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5830 tmp &= ~SBI_SSCCTL_DISABLE;
5831 tmp |= SBI_SSCCTL_PATHALT;
5832 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5833
5834 udelay(24);
5835
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005836 if (with_spread) {
5837 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5838 tmp &= ~SBI_SSCCTL_PATHALT;
5839 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
Paulo Zanonif31f2d52013-07-18 18:51:11 -03005840
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005841 if (with_fdi) {
5842 lpt_reset_fdi_mphy(dev_priv);
5843 lpt_program_fdi_mphy(dev_priv);
5844 }
5845 }
Paulo Zanonidde86e22012-12-01 12:04:25 -02005846
Paulo Zanoni2fa86a12013-07-23 11:19:24 -03005847 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5848 SBI_GEN0 : SBI_DBUFF0;
5849 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5850 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5851 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
Daniel Vetterc00db242013-01-22 15:33:27 +01005852
5853 mutex_unlock(&dev_priv->dpio_lock);
Paulo Zanonidde86e22012-12-01 12:04:25 -02005854}
5855
Paulo Zanoni47701c32013-07-23 11:19:25 -03005856/* Sequence to disable CLKOUT_DP */
5857static void lpt_disable_clkout_dp(struct drm_device *dev)
5858{
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 uint32_t reg, tmp;
5861
5862 mutex_lock(&dev_priv->dpio_lock);
5863
5864 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5865 SBI_GEN0 : SBI_DBUFF0;
5866 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5867 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5868 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5869
5870 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5871 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5872 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5873 tmp |= SBI_SSCCTL_PATHALT;
5874 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5875 udelay(32);
5876 }
5877 tmp |= SBI_SSCCTL_DISABLE;
5878 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5879 }
5880
5881 mutex_unlock(&dev_priv->dpio_lock);
5882}
5883
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03005884static void lpt_init_pch_refclk(struct drm_device *dev)
5885{
5886 struct drm_mode_config *mode_config = &dev->mode_config;
5887 struct intel_encoder *encoder;
5888 bool has_vga = false;
5889
5890 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5891 switch (encoder->type) {
5892 case INTEL_OUTPUT_ANALOG:
5893 has_vga = true;
5894 break;
5895 }
5896 }
5897
Paulo Zanoni47701c32013-07-23 11:19:25 -03005898 if (has_vga)
5899 lpt_enable_clkout_dp(dev, true, true);
5900 else
5901 lpt_disable_clkout_dp(dev);
Paulo Zanonibf8fa3d2013-07-12 14:19:38 -03005902}
5903
Paulo Zanonidde86e22012-12-01 12:04:25 -02005904/*
5905 * Initialize reference clocks when the driver loads
5906 */
5907void intel_init_pch_refclk(struct drm_device *dev)
5908{
5909 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5910 ironlake_init_pch_refclk(dev);
5911 else if (HAS_PCH_LPT(dev))
5912 lpt_init_pch_refclk(dev);
5913}
5914
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005915static int ironlake_get_refclk(struct drm_crtc *crtc)
5916{
5917 struct drm_device *dev = crtc->dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005920 int num_connectors = 0;
5921 bool is_lvds = false;
5922
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005923 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005924 switch (encoder->type) {
5925 case INTEL_OUTPUT_LVDS:
5926 is_lvds = true;
5927 break;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005928 }
5929 num_connectors++;
5930 }
5931
5932 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005933 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03005934 dev_priv->vbt.lvds_ssc_freq);
Ville Syrjäläe91e9412013-12-09 18:54:16 +02005935 return dev_priv->vbt.lvds_ssc_freq;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005936 }
5937
5938 return 120000;
5939}
5940
Daniel Vetter6ff93602013-04-19 11:24:36 +02005941static void ironlake_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanonic8203562012-09-12 10:06:29 -03005942{
5943 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5945 int pipe = intel_crtc->pipe;
5946 uint32_t val;
5947
Daniel Vetter78114072013-06-13 00:54:57 +02005948 val = 0;
Paulo Zanonic8203562012-09-12 10:06:29 -03005949
Daniel Vetter965e0c42013-03-27 00:44:57 +01005950 switch (intel_crtc->config.pipe_bpp) {
Paulo Zanonic8203562012-09-12 10:06:29 -03005951 case 18:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005952 val |= PIPECONF_6BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005953 break;
5954 case 24:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005955 val |= PIPECONF_8BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005956 break;
5957 case 30:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005958 val |= PIPECONF_10BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005959 break;
5960 case 36:
Daniel Vetterdfd07d72012-12-17 11:21:38 +01005961 val |= PIPECONF_12BPC;
Paulo Zanonic8203562012-09-12 10:06:29 -03005962 break;
5963 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005964 /* Case prevented by intel_choose_pipe_bpp_dither. */
5965 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005966 }
5967
Daniel Vetterd8b32242013-04-25 17:54:44 +02005968 if (intel_crtc->config.dither)
Paulo Zanonic8203562012-09-12 10:06:29 -03005969 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5970
Daniel Vetter6ff93602013-04-19 11:24:36 +02005971 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanonic8203562012-09-12 10:06:29 -03005972 val |= PIPECONF_INTERLACED_ILK;
5973 else
5974 val |= PIPECONF_PROGRESSIVE;
5975
Daniel Vetter50f3b012013-03-27 00:44:56 +01005976 if (intel_crtc->config.limited_color_range)
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005977 val |= PIPECONF_COLOR_RANGE_SELECT;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +02005978
Paulo Zanonic8203562012-09-12 10:06:29 -03005979 I915_WRITE(PIPECONF(pipe), val);
5980 POSTING_READ(PIPECONF(pipe));
5981}
5982
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005983/*
5984 * Set up the pipe CSC unit.
5985 *
5986 * Currently only full range RGB to limited range RGB conversion
5987 * is supported, but eventually this should handle various
5988 * RGB<->YCbCr scenarios as well.
5989 */
Daniel Vetter50f3b012013-03-27 00:44:56 +01005990static void intel_set_pipe_csc(struct drm_crtc *crtc)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02005991{
5992 struct drm_device *dev = crtc->dev;
5993 struct drm_i915_private *dev_priv = dev->dev_private;
5994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5995 int pipe = intel_crtc->pipe;
5996 uint16_t coeff = 0x7800; /* 1.0 */
5997
5998 /*
5999 * TODO: Check what kind of values actually come out of the pipe
6000 * with these coeff/postoff values and adjust to get the best
6001 * accuracy. Perhaps we even need to take the bpc value into
6002 * consideration.
6003 */
6004
Daniel Vetter50f3b012013-03-27 00:44:56 +01006005 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006006 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6007
6008 /*
6009 * GY/GU and RY/RU should be the other way around according
6010 * to BSpec, but reality doesn't agree. Just set them up in
6011 * a way that results in the correct picture.
6012 */
6013 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6014 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6015
6016 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6017 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6018
6019 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6020 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6021
6022 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6023 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6024 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6025
6026 if (INTEL_INFO(dev)->gen > 6) {
6027 uint16_t postoff = 0;
6028
Daniel Vetter50f3b012013-03-27 00:44:56 +01006029 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006030 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6031
6032 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6033 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6034 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6035
6036 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6037 } else {
6038 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6039
Daniel Vetter50f3b012013-03-27 00:44:56 +01006040 if (intel_crtc->config.limited_color_range)
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02006041 mode |= CSC_BLACK_SCREEN_OFFSET;
6042
6043 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6044 }
6045}
6046
Daniel Vetter6ff93602013-04-19 11:24:36 +02006047static void haswell_set_pipeconf(struct drm_crtc *crtc)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006048{
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006049 struct drm_device *dev = crtc->dev;
6050 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006052 enum pipe pipe = intel_crtc->pipe;
Daniel Vetter3b117c82013-04-17 20:15:07 +02006053 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006054 uint32_t val;
6055
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006056 val = 0;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006057
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006058 if (IS_HASWELL(dev) && intel_crtc->config.dither)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006059 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6060
Daniel Vetter6ff93602013-04-19 11:24:36 +02006061 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006062 val |= PIPECONF_INTERLACED_ILK;
6063 else
6064 val |= PIPECONF_PROGRESSIVE;
6065
Paulo Zanoni702e7a52012-10-23 18:29:59 -02006066 I915_WRITE(PIPECONF(cpu_transcoder), val);
6067 POSTING_READ(PIPECONF(cpu_transcoder));
Daniel Vetter3eff4fa2013-06-13 00:54:59 +02006068
6069 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6070 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
Paulo Zanoni756f85c2013-11-02 21:07:38 -07006071
6072 if (IS_BROADWELL(dev)) {
6073 val = 0;
6074
6075 switch (intel_crtc->config.pipe_bpp) {
6076 case 18:
6077 val |= PIPEMISC_DITHER_6_BPC;
6078 break;
6079 case 24:
6080 val |= PIPEMISC_DITHER_8_BPC;
6081 break;
6082 case 30:
6083 val |= PIPEMISC_DITHER_10_BPC;
6084 break;
6085 case 36:
6086 val |= PIPEMISC_DITHER_12_BPC;
6087 break;
6088 default:
6089 /* Case prevented by pipe_config_set_bpp. */
6090 BUG();
6091 }
6092
6093 if (intel_crtc->config.dither)
6094 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6095
6096 I915_WRITE(PIPEMISC(pipe), val);
6097 }
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03006098}
6099
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006100static bool ironlake_compute_clocks(struct drm_crtc *crtc,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006101 intel_clock_t *clock,
6102 bool *has_reduced_clock,
6103 intel_clock_t *reduced_clock)
6104{
6105 struct drm_device *dev = crtc->dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 struct intel_encoder *intel_encoder;
6108 int refclk;
6109 const intel_limit_t *limit;
Daniel Vettera16af7212013-04-30 14:01:44 +02006110 bool ret, is_lvds = false;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006111
6112 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6113 switch (intel_encoder->type) {
6114 case INTEL_OUTPUT_LVDS:
6115 is_lvds = true;
6116 break;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006117 }
6118 }
6119
6120 refclk = ironlake_get_refclk(crtc);
6121
6122 /*
6123 * Returns a set of divisors for the desired target clock with the given
6124 * refclk, or FALSE. The returned values represent the clock equation:
6125 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6126 */
6127 limit = intel_limit(crtc, refclk);
Daniel Vetterff9a6752013-06-01 17:16:21 +02006128 ret = dev_priv->display.find_dpll(limit, crtc,
6129 to_intel_crtc(crtc)->config.port_clock,
Daniel Vetteree9300b2013-06-03 22:40:22 +02006130 refclk, NULL, clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006131 if (!ret)
6132 return false;
6133
6134 if (is_lvds && dev_priv->lvds_downclock_avail) {
6135 /*
6136 * Ensure we match the reduced clock's P to the target clock.
6137 * If the clocks don't match, we can't switch the display clock
6138 * by using the FP0/FP1. In such case we will disable the LVDS
6139 * downclock feature.
6140 */
Daniel Vetteree9300b2013-06-03 22:40:22 +02006141 *has_reduced_clock =
6142 dev_priv->display.find_dpll(limit, crtc,
6143 dev_priv->lvds_downclock,
6144 refclk, clock,
6145 reduced_clock);
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006146 }
6147
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006148 return true;
6149}
6150
Paulo Zanonid4b19312012-11-29 11:29:32 -02006151int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6152{
6153 /*
6154 * Account for spread spectrum to avoid
6155 * oversubscribing the link. Max center spread
6156 * is 2.5%; use 5% for safety's sake.
6157 */
6158 u32 bps = target_clock * bpp * 21 / 20;
6159 return bps / (link_bw * 8) + 1;
6160}
6161
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006162static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
Daniel Vetter6cf86a52013-04-02 23:38:10 +02006163{
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006164 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006165}
6166
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006167static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006168 u32 *fp,
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006169 intel_clock_t *reduced_clock, u32 *fp2)
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006170{
6171 struct drm_crtc *crtc = &intel_crtc->base;
6172 struct drm_device *dev = crtc->dev;
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct intel_encoder *intel_encoder;
6175 uint32_t dpll;
Daniel Vetter6cc5f342013-03-27 00:44:53 +01006176 int factor, num_connectors = 0;
Daniel Vetter09ede542013-04-30 14:01:45 +02006177 bool is_lvds = false, is_sdvo = false;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006178
6179 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6180 switch (intel_encoder->type) {
6181 case INTEL_OUTPUT_LVDS:
6182 is_lvds = true;
6183 break;
6184 case INTEL_OUTPUT_SDVO:
6185 case INTEL_OUTPUT_HDMI:
6186 is_sdvo = true;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006187 break;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006188 }
6189
6190 num_connectors++;
6191 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006192
Chris Wilsonc1858122010-12-03 21:35:48 +00006193 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07006194 factor = 21;
6195 if (is_lvds) {
6196 if ((intel_panel_use_ssc(dev_priv) &&
Ville Syrjäläe91e9412013-12-09 18:54:16 +02006197 dev_priv->vbt.lvds_ssc_freq == 100000) ||
Daniel Vetterf0b44052013-04-04 22:20:33 +02006198 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
Eric Anholt8febb292011-03-30 13:01:07 -07006199 factor = 25;
Daniel Vetter09ede542013-04-30 14:01:45 +02006200 } else if (intel_crtc->config.sdvo_tv_clock)
Eric Anholt8febb292011-03-30 13:01:07 -07006201 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00006202
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006203 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
Daniel Vetter7d0ac5b2013-04-04 22:20:32 +02006204 *fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00006205
Daniel Vetter9a7c7892013-04-04 22:20:34 +02006206 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6207 *fp2 |= FP_CB_TUNE;
6208
Chris Wilson5eddb702010-09-11 13:48:45 +01006209 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08006210
Eric Anholta07d6782011-03-30 13:01:08 -07006211 if (is_lvds)
6212 dpll |= DPLLB_MODE_LVDS;
6213 else
6214 dpll |= DPLLB_MODE_DAC_SERIAL;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006215
Daniel Vetteref1b4602013-06-01 17:17:04 +02006216 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6217 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Daniel Vetter198a037f2013-04-19 11:14:37 +02006218
6219 if (is_sdvo)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006220 dpll |= DPLL_SDVO_HIGH_SPEED;
Daniel Vetter9566e9a2013-04-19 11:14:36 +02006221 if (intel_crtc->config.has_dp_encoder)
Daniel Vetter4a33e482013-07-06 12:52:05 +02006222 dpll |= DPLL_SDVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08006223
Eric Anholta07d6782011-03-30 13:01:08 -07006224 /* compute bitmask from p1 value */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006225 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006226 /* also FPA1 */
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006227 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07006228
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006229 switch (intel_crtc->config.dpll.p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07006230 case 5:
6231 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6232 break;
6233 case 7:
6234 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6235 break;
6236 case 10:
6237 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6238 break;
6239 case 14:
6240 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6241 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006242 }
6243
Daniel Vetterb4c09f32013-04-30 14:01:42 +02006244 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05006245 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08006246 else
6247 dpll |= PLL_REF_INPUT_DREFCLK;
6248
Daniel Vetter959e16d2013-06-05 13:34:21 +02006249 return dpll | DPLL_VCO_ENABLE;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006250}
6251
Jesse Barnes79e53942008-11-07 14:24:08 -08006252static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
Jesse Barnes79e53942008-11-07 14:24:08 -08006253 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02006254 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08006255{
6256 struct drm_device *dev = crtc->dev;
6257 struct drm_i915_private *dev_priv = dev->dev_private;
6258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6259 int pipe = intel_crtc->pipe;
6260 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006261 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006262 intel_clock_t clock, reduced_clock;
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006263 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03006264 bool ok, has_reduced_clock = false;
Daniel Vetter8b470472013-03-28 10:41:59 +01006265 bool is_lvds = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03006266 struct intel_encoder *encoder;
Daniel Vettere2b78262013-06-07 23:10:03 +02006267 struct intel_shared_dpll *pll;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03006268 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006269
6270 for_each_encoder_on_crtc(dev, crtc, encoder) {
6271 switch (encoder->type) {
6272 case INTEL_OUTPUT_LVDS:
6273 is_lvds = true;
6274 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08006275 }
6276
6277 num_connectors++;
6278 }
6279
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006280 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6281 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6282
Daniel Vetterff9a6752013-06-01 17:16:21 +02006283 ok = ironlake_compute_clocks(crtc, &clock,
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03006284 &has_reduced_clock, &reduced_clock);
Daniel Vetteree9300b2013-06-03 22:40:22 +02006285 if (!ok && !intel_crtc->config.clock_set) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006286 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6287 return -EINVAL;
6288 }
Daniel Vetterf47709a2013-03-28 10:42:02 +01006289 /* Compat-code for transition, will disappear. */
6290 if (!intel_crtc->config.clock_set) {
6291 intel_crtc->config.dpll.n = clock.n;
6292 intel_crtc->config.dpll.m1 = clock.m1;
6293 intel_crtc->config.dpll.m2 = clock.m2;
6294 intel_crtc->config.dpll.p1 = clock.p1;
6295 intel_crtc->config.dpll.p2 = clock.p2;
6296 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006297
Paulo Zanoni5dc52982012-10-05 12:05:56 -03006298 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
Daniel Vetter8b470472013-03-28 10:41:59 +01006299 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006300 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006301 if (has_reduced_clock)
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006302 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006303
Daniel Vetter7429e9d2013-04-20 17:19:46 +02006304 dpll = ironlake_compute_dpll(intel_crtc,
Daniel Vettercbbab5b2013-04-19 11:14:31 +02006305 &fp, &reduced_clock,
6306 has_reduced_clock ? &fp2 : NULL);
6307
Daniel Vetter959e16d2013-06-05 13:34:21 +02006308 intel_crtc->config.dpll_hw_state.dpll = dpll;
Daniel Vetter66e985c2013-06-05 13:34:20 +02006309 intel_crtc->config.dpll_hw_state.fp0 = fp;
6310 if (has_reduced_clock)
6311 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6312 else
6313 intel_crtc->config.dpll_hw_state.fp1 = fp;
6314
Daniel Vetterb89a1d32013-06-05 13:34:24 +02006315 pll = intel_get_shared_dpll(intel_crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006316 if (pll == NULL) {
Ville Syrjälä84f44ce2013-04-17 17:48:49 +03006317 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6318 pipe_name(pipe));
Jesse Barnes4b645f12011-10-12 09:51:31 -07006319 return -EINVAL;
6320 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006321 } else
Daniel Vettere72f9fb2013-06-05 13:34:06 +02006322 intel_put_shared_dpll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006323
Daniel Vetter03afc4a2013-04-02 23:42:31 +02006324 if (intel_crtc->config.has_dp_encoder)
6325 intel_dp_set_m_n(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006326
Daniel Vetterbcd644e2013-06-05 13:34:22 +02006327 if (is_lvds && has_reduced_clock && i915_powersave)
6328 intel_crtc->lowfreq_avail = true;
6329 else
6330 intel_crtc->lowfreq_avail = false;
Daniel Vettere2b78262013-06-07 23:10:03 +02006331
Daniel Vetter8a654f32013-06-01 17:16:22 +02006332 intel_set_pipe_timings(intel_crtc);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02006333
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01006334 if (intel_crtc->config.has_pch_encoder) {
Daniel Vetterca3a0ff2013-02-14 16:54:22 +01006335 intel_cpu_transcoder_set_m_n(intel_crtc,
6336 &intel_crtc->config.fdi_m_n);
6337 }
Chris Wilson5eddb702010-09-11 13:48:45 +01006338
Daniel Vetter6ff93602013-04-19 11:24:36 +02006339 ironlake_set_pipeconf(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006340
Paulo Zanonia1f9e772012-09-12 10:06:32 -03006341 /* Set up the display plane register */
6342 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08006343 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08006344
Daniel Vetter94352cf2012-07-05 22:51:56 +02006345 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08006346
Daniel Vetter1857e1d2013-04-29 19:34:16 +02006347 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006348}
6349
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006350static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6351 struct intel_link_m_n *m_n)
Daniel Vetter72419202013-04-04 13:28:53 +02006352{
6353 struct drm_device *dev = crtc->base.dev;
6354 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006355 enum pipe pipe = crtc->pipe;
Daniel Vetter72419202013-04-04 13:28:53 +02006356
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006357 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6358 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6359 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6360 & ~TU_SIZE_MASK;
6361 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6362 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6363 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6364}
6365
6366static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6367 enum transcoder transcoder,
6368 struct intel_link_m_n *m_n)
6369{
6370 struct drm_device *dev = crtc->base.dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 enum pipe pipe = crtc->pipe;
6373
6374 if (INTEL_INFO(dev)->gen >= 5) {
6375 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6376 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6377 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6378 & ~TU_SIZE_MASK;
6379 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6380 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6381 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6382 } else {
6383 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6384 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6385 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6386 & ~TU_SIZE_MASK;
6387 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6388 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6389 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6390 }
6391}
6392
6393void intel_dp_get_m_n(struct intel_crtc *crtc,
6394 struct intel_crtc_config *pipe_config)
6395{
6396 if (crtc->config.has_pch_encoder)
6397 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6398 else
6399 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6400 &pipe_config->dp_m_n);
6401}
6402
Daniel Vetter72419202013-04-04 13:28:53 +02006403static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6404 struct intel_crtc_config *pipe_config)
6405{
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03006406 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6407 &pipe_config->fdi_m_n);
Daniel Vetter72419202013-04-04 13:28:53 +02006408}
6409
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006410static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6411 struct intel_crtc_config *pipe_config)
6412{
6413 struct drm_device *dev = crtc->base.dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 uint32_t tmp;
6416
6417 tmp = I915_READ(PF_CTL(crtc->pipe));
6418
6419 if (tmp & PF_ENABLE) {
Chris Wilsonfd4daa92013-08-27 17:04:17 +01006420 pipe_config->pch_pfit.enabled = true;
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006421 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6422 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
Daniel Vettercb8b2a32013-06-01 17:16:23 +02006423
6424 /* We currently do not free assignements of panel fitters on
6425 * ivb/hsw (since we don't use the higher upscaling modes which
6426 * differentiates them) so just WARN about this case for now. */
6427 if (IS_GEN7(dev)) {
6428 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6429 PF_PIPE_SEL_IVB(crtc->pipe));
6430 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006431 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006432}
6433
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006434static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6435 struct intel_crtc_config *pipe_config)
6436{
6437 struct drm_device *dev = crtc->base.dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 uint32_t tmp;
6440
Daniel Vettere143a212013-07-04 12:01:15 +02006441 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006442 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vettereccb1402013-05-22 00:50:22 +02006443
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006444 tmp = I915_READ(PIPECONF(crtc->pipe));
6445 if (!(tmp & PIPECONF_ENABLE))
6446 return false;
6447
Ville Syrjälä42571ae2013-09-06 23:29:00 +03006448 switch (tmp & PIPECONF_BPC_MASK) {
6449 case PIPECONF_6BPC:
6450 pipe_config->pipe_bpp = 18;
6451 break;
6452 case PIPECONF_8BPC:
6453 pipe_config->pipe_bpp = 24;
6454 break;
6455 case PIPECONF_10BPC:
6456 pipe_config->pipe_bpp = 30;
6457 break;
6458 case PIPECONF_12BPC:
6459 pipe_config->pipe_bpp = 36;
6460 break;
6461 default:
6462 break;
6463 }
6464
Daniel Vetterab9412b2013-05-03 11:49:46 +02006465 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
Daniel Vetter66e985c2013-06-05 13:34:20 +02006466 struct intel_shared_dpll *pll;
6467
Daniel Vetter88adfff2013-03-28 10:42:01 +01006468 pipe_config->has_pch_encoder = true;
6469
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006470 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6471 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6472 FDI_DP_PORT_WIDTH_SHIFT) + 1;
Daniel Vetter72419202013-04-04 13:28:53 +02006473
6474 ironlake_get_fdi_m_n_config(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02006475
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006476 if (HAS_PCH_IBX(dev_priv->dev)) {
Daniel Vetterd94ab062013-07-04 12:01:16 +02006477 pipe_config->shared_dpll =
6478 (enum intel_dpll_id) crtc->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02006479 } else {
6480 tmp = I915_READ(PCH_DPLL_SEL);
6481 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6482 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6483 else
6484 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6485 }
Daniel Vetter66e985c2013-06-05 13:34:20 +02006486
6487 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6488
6489 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6490 &pipe_config->dpll_hw_state));
Daniel Vetterc93f54c2013-06-27 19:47:19 +02006491
6492 tmp = pipe_config->dpll_hw_state.dpll;
6493 pipe_config->pixel_multiplier =
6494 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6495 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
Ville Syrjälä18442d02013-09-13 16:00:08 +03006496
6497 ironlake_pch_clock_get(crtc, pipe_config);
Daniel Vetter6c49f242013-06-06 12:45:25 +02006498 } else {
6499 pipe_config->pixel_multiplier = 1;
Daniel Vetter627eb5a2013-04-29 19:33:42 +02006500 }
6501
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02006502 intel_get_pipe_timings(crtc, pipe_config);
6503
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02006504 ironlake_get_pfit_config(crtc, pipe_config);
6505
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01006506 return true;
6507}
6508
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006509static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6510{
6511 struct drm_device *dev = dev_priv->dev;
6512 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6513 struct intel_crtc *crtc;
6514 unsigned long irqflags;
Paulo Zanonibd633a72013-08-19 13:18:08 -03006515 uint32_t val;
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006516
6517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
Paulo Zanoni798183c2013-12-06 20:29:01 -02006518 WARN(crtc->active, "CRTC for pipe %c enabled\n",
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006519 pipe_name(crtc->pipe));
6520
6521 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6522 WARN(plls->spll_refcount, "SPLL enabled\n");
6523 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6524 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6525 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6526 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6527 "CPU PWM1 enabled\n");
6528 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6529 "CPU PWM2 enabled\n");
6530 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6531 "PCH PWM1 enabled\n");
6532 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6533 "Utility pin enabled\n");
6534 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6535
6536 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6537 val = I915_READ(DEIMR);
Paulo Zanoni6806e632013-11-21 13:47:24 -02006538 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006539 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6540 val = I915_READ(SDEIMR);
Paulo Zanonibd633a72013-08-19 13:18:08 -03006541 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006542 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6543 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6544}
6545
6546/*
6547 * This function implements pieces of two sequences from BSpec:
6548 * - Sequence for display software to disable LCPLL
6549 * - Sequence for display software to allow package C8+
6550 * The steps implemented here are just the steps that actually touch the LCPLL
6551 * register. Callers should take care of disabling all the display engine
6552 * functions, doing the mode unset, fixing interrupts, etc.
6553 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03006554static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6555 bool switch_to_fclk, bool allow_power_down)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006556{
6557 uint32_t val;
6558
6559 assert_can_disable_lcpll(dev_priv);
6560
6561 val = I915_READ(LCPLL_CTL);
6562
6563 if (switch_to_fclk) {
6564 val |= LCPLL_CD_SOURCE_FCLK;
6565 I915_WRITE(LCPLL_CTL, val);
6566
6567 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6568 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6569 DRM_ERROR("Switching to FCLK failed\n");
6570
6571 val = I915_READ(LCPLL_CTL);
6572 }
6573
6574 val |= LCPLL_PLL_DISABLE;
6575 I915_WRITE(LCPLL_CTL, val);
6576 POSTING_READ(LCPLL_CTL);
6577
6578 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6579 DRM_ERROR("LCPLL still locked\n");
6580
6581 val = I915_READ(D_COMP);
6582 val |= D_COMP_COMP_DISABLE;
Paulo Zanoni515b2392013-09-10 19:36:37 -03006583 mutex_lock(&dev_priv->rps.hw_lock);
6584 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6585 DRM_ERROR("Failed to disable D_COMP\n");
6586 mutex_unlock(&dev_priv->rps.hw_lock);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006587 POSTING_READ(D_COMP);
6588 ndelay(100);
6589
6590 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6591 DRM_ERROR("D_COMP RCOMP still in progress\n");
6592
6593 if (allow_power_down) {
6594 val = I915_READ(LCPLL_CTL);
6595 val |= LCPLL_POWER_DOWN_ALLOW;
6596 I915_WRITE(LCPLL_CTL, val);
6597 POSTING_READ(LCPLL_CTL);
6598 }
6599}
6600
6601/*
6602 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6603 * source.
6604 */
Paulo Zanoni6ff58d52013-09-24 13:52:57 -03006605static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006606{
6607 uint32_t val;
6608
6609 val = I915_READ(LCPLL_CTL);
6610
6611 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6612 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6613 return;
6614
Paulo Zanoni215733f2013-08-19 13:18:07 -03006615 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6616 * we'll hang the machine! */
Deepak Sc8d9a592013-11-23 14:55:42 +05306617 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
Paulo Zanoni215733f2013-08-19 13:18:07 -03006618
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006619 if (val & LCPLL_POWER_DOWN_ALLOW) {
6620 val &= ~LCPLL_POWER_DOWN_ALLOW;
6621 I915_WRITE(LCPLL_CTL, val);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02006622 POSTING_READ(LCPLL_CTL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006623 }
6624
6625 val = I915_READ(D_COMP);
6626 val |= D_COMP_COMP_FORCE;
6627 val &= ~D_COMP_COMP_DISABLE;
Paulo Zanoni515b2392013-09-10 19:36:37 -03006628 mutex_lock(&dev_priv->rps.hw_lock);
6629 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6630 DRM_ERROR("Failed to enable D_COMP\n");
6631 mutex_unlock(&dev_priv->rps.hw_lock);
Daniel Vetter35d8f2e2013-08-21 23:38:08 +02006632 POSTING_READ(D_COMP);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006633
6634 val = I915_READ(LCPLL_CTL);
6635 val &= ~LCPLL_PLL_DISABLE;
6636 I915_WRITE(LCPLL_CTL, val);
6637
6638 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6639 DRM_ERROR("LCPLL not locked yet\n");
6640
6641 if (val & LCPLL_CD_SOURCE_FCLK) {
6642 val = I915_READ(LCPLL_CTL);
6643 val &= ~LCPLL_CD_SOURCE_FCLK;
6644 I915_WRITE(LCPLL_CTL, val);
6645
6646 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6647 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6648 DRM_ERROR("Switching back to LCPLL failed\n");
6649 }
Paulo Zanoni215733f2013-08-19 13:18:07 -03006650
Deepak Sc8d9a592013-11-23 14:55:42 +05306651 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
Paulo Zanonibe256dc2013-07-23 11:19:26 -03006652}
6653
Paulo Zanonic67a4702013-08-19 13:18:09 -03006654void hsw_enable_pc8_work(struct work_struct *__work)
6655{
6656 struct drm_i915_private *dev_priv =
6657 container_of(to_delayed_work(__work), struct drm_i915_private,
6658 pc8.enable_work);
6659 struct drm_device *dev = dev_priv->dev;
6660 uint32_t val;
6661
Paulo Zanoni7125ecb82013-11-21 13:47:15 -02006662 WARN_ON(!HAS_PC8(dev));
6663
Paulo Zanonic67a4702013-08-19 13:18:09 -03006664 if (dev_priv->pc8.enabled)
6665 return;
6666
6667 DRM_DEBUG_KMS("Enabling package C8+\n");
6668
6669 dev_priv->pc8.enabled = true;
6670
6671 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6672 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6673 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6674 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6675 }
6676
6677 lpt_disable_clkout_dp(dev);
6678 hsw_pc8_disable_interrupts(dev);
6679 hsw_disable_lcpll(dev_priv, true, true);
Paulo Zanoni8771a7f2013-11-21 13:47:28 -02006680
6681 intel_runtime_pm_put(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006682}
6683
6684static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6685{
6686 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6687 WARN(dev_priv->pc8.disable_count < 1,
6688 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6689
6690 dev_priv->pc8.disable_count--;
6691 if (dev_priv->pc8.disable_count != 0)
6692 return;
6693
6694 schedule_delayed_work(&dev_priv->pc8.enable_work,
Paulo Zanoni90058742013-08-19 13:18:11 -03006695 msecs_to_jiffies(i915_pc8_timeout));
Paulo Zanonic67a4702013-08-19 13:18:09 -03006696}
6697
6698static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6699{
6700 struct drm_device *dev = dev_priv->dev;
6701 uint32_t val;
6702
6703 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6704 WARN(dev_priv->pc8.disable_count < 0,
6705 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6706
6707 dev_priv->pc8.disable_count++;
6708 if (dev_priv->pc8.disable_count != 1)
6709 return;
6710
Paulo Zanoni7125ecb82013-11-21 13:47:15 -02006711 WARN_ON(!HAS_PC8(dev));
6712
Paulo Zanonic67a4702013-08-19 13:18:09 -03006713 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6714 if (!dev_priv->pc8.enabled)
6715 return;
6716
6717 DRM_DEBUG_KMS("Disabling package C8+\n");
6718
Paulo Zanoni8771a7f2013-11-21 13:47:28 -02006719 intel_runtime_pm_get(dev_priv);
6720
Paulo Zanonic67a4702013-08-19 13:18:09 -03006721 hsw_restore_lcpll(dev_priv);
6722 hsw_pc8_restore_interrupts(dev);
6723 lpt_init_pch_refclk(dev);
6724
6725 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6726 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6727 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6728 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6729 }
6730
6731 intel_prepare_ddi(dev);
6732 i915_gem_init_swizzling(dev);
6733 mutex_lock(&dev_priv->rps.hw_lock);
6734 gen6_update_ring_freq(dev);
6735 mutex_unlock(&dev_priv->rps.hw_lock);
6736 dev_priv->pc8.enabled = false;
6737}
6738
6739void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6740{
Chris Wilson7c6c2652013-11-18 18:32:37 -08006741 if (!HAS_PC8(dev_priv->dev))
6742 return;
6743
Paulo Zanonic67a4702013-08-19 13:18:09 -03006744 mutex_lock(&dev_priv->pc8.lock);
6745 __hsw_enable_package_c8(dev_priv);
6746 mutex_unlock(&dev_priv->pc8.lock);
6747}
6748
6749void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6750{
Chris Wilson7c6c2652013-11-18 18:32:37 -08006751 if (!HAS_PC8(dev_priv->dev))
6752 return;
6753
Paulo Zanonic67a4702013-08-19 13:18:09 -03006754 mutex_lock(&dev_priv->pc8.lock);
6755 __hsw_disable_package_c8(dev_priv);
6756 mutex_unlock(&dev_priv->pc8.lock);
6757}
6758
6759static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6760{
6761 struct drm_device *dev = dev_priv->dev;
6762 struct intel_crtc *crtc;
6763 uint32_t val;
6764
6765 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6766 if (crtc->base.enabled)
6767 return false;
6768
6769 /* This case is still possible since we have the i915.disable_power_well
6770 * parameter and also the KVMr or something else might be requesting the
6771 * power well. */
6772 val = I915_READ(HSW_PWR_WELL_DRIVER);
6773 if (val != 0) {
6774 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6775 return false;
6776 }
6777
6778 return true;
6779}
6780
6781/* Since we're called from modeset_global_resources there's no way to
6782 * symmetrically increase and decrease the refcount, so we use
6783 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6784 * or not.
6785 */
6786static void hsw_update_package_c8(struct drm_device *dev)
6787{
6788 struct drm_i915_private *dev_priv = dev->dev_private;
6789 bool allow;
6790
Chris Wilson7c6c2652013-11-18 18:32:37 -08006791 if (!HAS_PC8(dev_priv->dev))
6792 return;
6793
Paulo Zanonic67a4702013-08-19 13:18:09 -03006794 if (!i915_enable_pc8)
6795 return;
6796
6797 mutex_lock(&dev_priv->pc8.lock);
6798
6799 allow = hsw_can_enable_package_c8(dev_priv);
6800
6801 if (allow == dev_priv->pc8.requirements_met)
6802 goto done;
6803
6804 dev_priv->pc8.requirements_met = allow;
6805
6806 if (allow)
6807 __hsw_enable_package_c8(dev_priv);
6808 else
6809 __hsw_disable_package_c8(dev_priv);
6810
6811done:
6812 mutex_unlock(&dev_priv->pc8.lock);
6813}
6814
6815static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6816{
Chris Wilson7c6c2652013-11-18 18:32:37 -08006817 if (!HAS_PC8(dev_priv->dev))
6818 return;
6819
Chris Wilson34581222013-11-18 18:32:36 -08006820 mutex_lock(&dev_priv->pc8.lock);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006821 if (!dev_priv->pc8.gpu_idle) {
6822 dev_priv->pc8.gpu_idle = true;
Chris Wilson34581222013-11-18 18:32:36 -08006823 __hsw_enable_package_c8(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006824 }
Chris Wilson34581222013-11-18 18:32:36 -08006825 mutex_unlock(&dev_priv->pc8.lock);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006826}
6827
6828static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6829{
Chris Wilson7c6c2652013-11-18 18:32:37 -08006830 if (!HAS_PC8(dev_priv->dev))
6831 return;
6832
Chris Wilson34581222013-11-18 18:32:36 -08006833 mutex_lock(&dev_priv->pc8.lock);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006834 if (dev_priv->pc8.gpu_idle) {
6835 dev_priv->pc8.gpu_idle = false;
Chris Wilson34581222013-11-18 18:32:36 -08006836 __hsw_disable_package_c8(dev_priv);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006837 }
Chris Wilson34581222013-11-18 18:32:36 -08006838 mutex_unlock(&dev_priv->pc8.lock);
Daniel Vetter94352cf2012-07-05 22:51:56 +02006839}
Eric Anholtf564048e2011-03-30 13:01:02 -07006840
Imre Deak6efdf352013-10-16 17:25:52 +03006841#define for_each_power_domain(domain, mask) \
6842 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6843 if ((1 << (domain)) & (mask))
6844
6845static unsigned long get_pipe_power_domains(struct drm_device *dev,
6846 enum pipe pipe, bool pfit_enabled)
6847{
6848 unsigned long mask;
6849 enum transcoder transcoder;
6850
6851 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6852
6853 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6854 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6855 if (pfit_enabled)
6856 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6857
6858 return mask;
6859}
6860
Imre Deakbaa70702013-10-25 17:36:48 +03006861void intel_display_set_init_power(struct drm_device *dev, bool enable)
6862{
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6864
6865 if (dev_priv->power_domains.init_power_on == enable)
6866 return;
6867
6868 if (enable)
6869 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6870 else
6871 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6872
6873 dev_priv->power_domains.init_power_on = enable;
6874}
6875
Imre Deak4f074122013-10-16 17:25:51 +03006876static void modeset_update_power_wells(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08006877{
Imre Deak6efdf352013-10-16 17:25:52 +03006878 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
Jesse Barnes79e53942008-11-07 14:24:08 -08006879 struct intel_crtc *crtc;
6880
Imre Deak6efdf352013-10-16 17:25:52 +03006881 /*
6882 * First get all needed power domains, then put all unneeded, to avoid
6883 * any unnecessary toggling of the power wells.
6884 */
Jesse Barnes79e53942008-11-07 14:24:08 -08006885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Imre Deak6efdf352013-10-16 17:25:52 +03006886 enum intel_display_power_domain domain;
6887
Jesse Barnes79e53942008-11-07 14:24:08 -08006888 if (!crtc->base.enabled)
6889 continue;
6890
Imre Deak6efdf352013-10-16 17:25:52 +03006891 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6892 crtc->pipe,
6893 crtc->config.pch_pfit.enabled);
6894
6895 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6896 intel_display_power_get(dev, domain);
Jesse Barnes79e53942008-11-07 14:24:08 -08006897 }
6898
Imre Deak6efdf352013-10-16 17:25:52 +03006899 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6900 enum intel_display_power_domain domain;
6901
6902 for_each_power_domain(domain, crtc->enabled_power_domains)
6903 intel_display_power_put(dev, domain);
6904
6905 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6906 }
Imre Deakbaa70702013-10-25 17:36:48 +03006907
6908 intel_display_set_init_power(dev, false);
Imre Deak4f074122013-10-16 17:25:51 +03006909}
Paulo Zanonic67a4702013-08-19 13:18:09 -03006910
Imre Deak4f074122013-10-16 17:25:51 +03006911static void haswell_modeset_global_resources(struct drm_device *dev)
6912{
6913 modeset_update_power_wells(dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03006914 hsw_update_package_c8(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006915}
6916
6917static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6918 int x, int y,
6919 struct drm_framebuffer *fb)
6920{
6921 struct drm_device *dev = crtc->dev;
6922 struct drm_i915_private *dev_priv = dev->dev_private;
6923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924 int plane = intel_crtc->plane;
6925 int ret;
6926
Paulo Zanoni566b7342013-11-25 15:27:08 -02006927 if (!intel_ddi_pll_select(intel_crtc))
Chris Wilson560b85b2010-08-07 11:01:38 +01006928 return -EINVAL;
Paulo Zanoni566b7342013-11-25 15:27:08 -02006929 intel_ddi_pll_enable(intel_crtc);
Chris Wilson560b85b2010-08-07 11:01:38 +01006930
Chris Wilson560b85b2010-08-07 11:01:38 +01006931 if (intel_crtc->config.has_dp_encoder)
6932 intel_dp_set_m_n(intel_crtc);
6933
6934 intel_crtc->lowfreq_avail = false;
6935
6936 intel_set_pipe_timings(intel_crtc);
6937
6938 if (intel_crtc->config.has_pch_encoder) {
6939 intel_cpu_transcoder_set_m_n(intel_crtc,
6940 &intel_crtc->config.fdi_m_n);
6941 }
6942
6943 haswell_set_pipeconf(crtc);
6944
6945 intel_set_pipe_csc(crtc);
6946
6947 /* Set up the display plane register */
6948 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6949 POSTING_READ(DSPCNTR(plane));
6950
6951 ret = intel_pipe_set_base(crtc, x, y, fb);
6952
Chris Wilson560b85b2010-08-07 11:01:38 +01006953 return ret;
6954}
6955
6956static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6957 struct intel_crtc_config *pipe_config)
6958{
6959 struct drm_device *dev = crtc->base.dev;
6960 struct drm_i915_private *dev_priv = dev->dev_private;
6961 enum intel_display_power_domain pfit_domain;
6962 uint32_t tmp;
6963
6964 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6965 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6966
6967 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6968 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6969 enum pipe trans_edp_pipe;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006970 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
Chris Wilson6b383a72010-09-13 13:54:26 +01006971 default:
6972 WARN(1, "unknown pipe linked to edp transcoder\n");
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006973 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6974 case TRANS_DDI_EDP_INPUT_A_ON:
6975 trans_edp_pipe = PIPE_A;
6976 break;
6977 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6978 trans_edp_pipe = PIPE_B;
6979 break;
Chris Wilson560b85b2010-08-07 11:01:38 +01006980 case TRANS_DDI_EDP_INPUT_C_ONOFF:
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006981 trans_edp_pipe = PIPE_C;
6982 break;
6983 }
6984
Chris Wilson6b383a72010-09-13 13:54:26 +01006985 if (trans_edp_pipe == crtc->pipe)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006986 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6987 }
6988
6989 if (!intel_display_power_enabled(dev,
6990 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6991 return false;
6992
6993 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6994 if (!(tmp & PIPECONF_ENABLE))
6995 return false;
6996
6997 /*
6998 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6999 * DDI E. So just check whether this pipe is wired to DDI E and whether
7000 * the PCH transcoder is on.
7001 */
7002 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7003 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7004 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7005 pipe_config->has_pch_encoder = true;
7006
7007 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7008 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7009 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7010
7011 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7012 }
7013
Chris Wilson560b85b2010-08-07 11:01:38 +01007014 intel_get_pipe_timings(crtc, pipe_config);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007015
7016 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7017 if (intel_display_power_enabled(dev, pfit_domain))
Chris Wilson560b85b2010-08-07 11:01:38 +01007018 ironlake_get_pfit_config(crtc, pipe_config);
7019
Jesse Barnese59150d2014-01-07 13:30:45 -08007020 if (IS_HASWELL(dev))
7021 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7022 (I915_READ(IPS_CTL) & IPS_ENABLE);
Jesse Barnes79e53942008-11-07 14:24:08 -08007023
7024 pipe_config->pixel_multiplier = 1;
Eric Anholtf564048e2011-03-30 13:01:02 -07007025
7026 return true;
7027}
7028
7029static int intel_crtc_mode_set(struct drm_crtc *crtc,
7030 int x, int y,
7031 struct drm_framebuffer *fb)
7032{
Eric Anholt0b701d22011-03-30 13:01:03 -07007033 struct drm_device *dev = crtc->dev;
7034 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9256aa12012-10-31 19:26:13 +01007035 struct intel_encoder *encoder;
Eric Anholtf564048e2011-03-30 13:01:02 -07007036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007037 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
Eric Anholtf564048e2011-03-30 13:01:02 -07007038 int pipe = intel_crtc->pipe;
7039 int ret;
7040
Eric Anholt0b701d22011-03-30 13:01:03 -07007041 drm_vblank_pre_modeset(dev, pipe);
7042
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01007043 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7044
Jesse Barnes79e53942008-11-07 14:24:08 -08007045 drm_vblank_post_modeset(dev, pipe);
7046
Daniel Vetter9256aa12012-10-31 19:26:13 +01007047 if (ret != 0)
7048 return ret;
7049
7050 for_each_encoder_on_crtc(dev, crtc, encoder) {
7051 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7052 encoder->base.base.id,
7053 drm_get_encoder_name(&encoder->base),
7054 mode->base.id, mode->name);
Daniel Vetter36f2d1f2013-07-21 21:37:08 +02007055 encoder->mode_set(encoder);
Daniel Vetter9256aa12012-10-31 19:26:13 +01007056 }
7057
7058 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007059}
7060
Jani Nikula1a915102013-10-16 12:34:48 +03007061static struct {
7062 int clock;
7063 u32 config;
7064} hdmi_audio_clock[] = {
7065 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7066 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7067 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7068 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7069 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7070 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7071 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7072 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7073 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7074 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7075};
7076
7077/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7078static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7079{
7080 int i;
7081
7082 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7083 if (mode->clock == hdmi_audio_clock[i].clock)
7084 break;
7085 }
7086
7087 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7088 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7089 i = 1;
7090 }
7091
7092 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7093 hdmi_audio_clock[i].clock,
7094 hdmi_audio_clock[i].config);
7095
7096 return hdmi_audio_clock[i].config;
7097}
7098
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007099static bool intel_eld_uptodate(struct drm_connector *connector,
7100 int reg_eldv, uint32_t bits_eldv,
7101 int reg_elda, uint32_t bits_elda,
7102 int reg_edid)
7103{
7104 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7105 uint8_t *eld = connector->eld;
7106 uint32_t i;
7107
7108 i = I915_READ(reg_eldv);
7109 i &= bits_eldv;
7110
7111 if (!eld[0])
7112 return !i;
7113
7114 if (!i)
7115 return false;
7116
7117 i = I915_READ(reg_elda);
7118 i &= ~bits_elda;
7119 I915_WRITE(reg_elda, i);
7120
7121 for (i = 0; i < eld[2]; i++)
7122 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7123 return false;
7124
7125 return true;
7126}
7127
Wu Fengguange0dac652011-09-05 14:25:34 +08007128static void g4x_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007129 struct drm_crtc *crtc,
7130 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007131{
7132 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7133 uint8_t *eld = connector->eld;
7134 uint32_t eldv;
7135 uint32_t len;
7136 uint32_t i;
7137
7138 i = I915_READ(G4X_AUD_VID_DID);
7139
7140 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7141 eldv = G4X_ELDV_DEVCL_DEVBLC;
7142 else
7143 eldv = G4X_ELDV_DEVCTG;
7144
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007145 if (intel_eld_uptodate(connector,
7146 G4X_AUD_CNTL_ST, eldv,
7147 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7148 G4X_HDMIW_HDMIEDID))
7149 return;
7150
Wu Fengguange0dac652011-09-05 14:25:34 +08007151 i = I915_READ(G4X_AUD_CNTL_ST);
7152 i &= ~(eldv | G4X_ELD_ADDR);
7153 len = (i >> 9) & 0x1f; /* ELD buffer size */
7154 I915_WRITE(G4X_AUD_CNTL_ST, i);
7155
7156 if (!eld[0])
7157 return;
7158
7159 len = min_t(uint8_t, eld[2], len);
7160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7161 for (i = 0; i < len; i++)
7162 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7163
7164 i = I915_READ(G4X_AUD_CNTL_ST);
7165 i |= eldv;
7166 I915_WRITE(G4X_AUD_CNTL_ST, i);
7167}
7168
Wang Xingchao83358c852012-08-16 22:43:37 +08007169static void haswell_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007170 struct drm_crtc *crtc,
7171 struct drm_display_mode *mode)
Wang Xingchao83358c852012-08-16 22:43:37 +08007172{
7173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7174 uint8_t *eld = connector->eld;
7175 struct drm_device *dev = crtc->dev;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08007176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Wang Xingchao83358c852012-08-16 22:43:37 +08007177 uint32_t eldv;
7178 uint32_t i;
7179 int len;
7180 int pipe = to_intel_crtc(crtc)->pipe;
7181 int tmp;
7182
7183 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7184 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7185 int aud_config = HSW_AUD_CFG(pipe);
7186 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7187
7188
7189 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7190
7191 /* Audio output enable */
7192 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7193 tmp = I915_READ(aud_cntrl_st2);
7194 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7195 I915_WRITE(aud_cntrl_st2, tmp);
7196
7197 /* Wait for 1 vertical blank */
7198 intel_wait_for_vblank(dev, pipe);
7199
7200 /* Set ELD valid state */
7201 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007202 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007203 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7204 I915_WRITE(aud_cntrl_st2, tmp);
7205 tmp = I915_READ(aud_cntrl_st2);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007206 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007207
7208 /* Enable HDMI mode */
7209 tmp = I915_READ(aud_config);
Takashi Iwai7e7cb342013-09-10 07:30:36 +02007210 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
Wang Xingchao83358c852012-08-16 22:43:37 +08007211 /* clear N_programing_enable and N_value_index */
7212 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7213 I915_WRITE(aud_config, tmp);
7214
7215 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7216
7217 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
Wang Xingchao7b9f35a2013-01-22 23:25:25 +08007218 intel_crtc->eld_vld = true;
Wang Xingchao83358c852012-08-16 22:43:37 +08007219
7220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7221 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7222 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7223 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007224 } else {
7225 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7226 }
Wang Xingchao83358c852012-08-16 22:43:37 +08007227
7228 if (intel_eld_uptodate(connector,
7229 aud_cntrl_st2, eldv,
7230 aud_cntl_st, IBX_ELD_ADDRESS,
7231 hdmiw_hdmiedid))
7232 return;
7233
7234 i = I915_READ(aud_cntrl_st2);
7235 i &= ~eldv;
7236 I915_WRITE(aud_cntrl_st2, i);
7237
7238 if (!eld[0])
7239 return;
7240
7241 i = I915_READ(aud_cntl_st);
7242 i &= ~IBX_ELD_ADDRESS;
7243 I915_WRITE(aud_cntl_st, i);
7244 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7245 DRM_DEBUG_DRIVER("port num:%d\n", i);
7246
7247 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7248 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7249 for (i = 0; i < len; i++)
7250 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7251
7252 i = I915_READ(aud_cntrl_st2);
7253 i |= eldv;
7254 I915_WRITE(aud_cntrl_st2, i);
7255
7256}
7257
Wu Fengguange0dac652011-09-05 14:25:34 +08007258static void ironlake_write_eld(struct drm_connector *connector,
Jani Nikula34427052013-10-16 12:34:47 +03007259 struct drm_crtc *crtc,
7260 struct drm_display_mode *mode)
Wu Fengguange0dac652011-09-05 14:25:34 +08007261{
7262 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7263 uint8_t *eld = connector->eld;
7264 uint32_t eldv;
7265 uint32_t i;
7266 int len;
7267 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06007268 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08007269 int aud_cntl_st;
7270 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08007271 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08007272
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08007273 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007274 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7275 aud_config = IBX_AUD_CFG(pipe);
7276 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007277 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007278 } else if (IS_VALLEYVIEW(connector->dev)) {
7279 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7280 aud_config = VLV_AUD_CFG(pipe);
7281 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7282 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007283 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08007284 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7285 aud_config = CPT_AUD_CFG(pipe);
7286 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007287 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08007288 }
7289
Wang Xingchao9b138a82012-08-09 16:52:18 +08007290 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08007291
Mengdong Lin9ca2fe72013-11-01 00:17:03 -04007292 if (IS_VALLEYVIEW(connector->dev)) {
7293 struct intel_encoder *intel_encoder;
7294 struct intel_digital_port *intel_dig_port;
7295
7296 intel_encoder = intel_attached_encoder(connector);
7297 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7298 i = intel_dig_port->port;
7299 } else {
7300 i = I915_READ(aud_cntl_st);
7301 i = (i >> 29) & DIP_PORT_SEL_MASK;
7302 /* DIP_Port_Select, 0x1 = PortB */
7303 }
7304
Wu Fengguange0dac652011-09-05 14:25:34 +08007305 if (!i) {
7306 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7307 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007308 eldv = IBX_ELD_VALIDB;
7309 eldv |= IBX_ELD_VALIDB << 4;
7310 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08007311 } else {
Ville Syrjälä2582a852013-04-17 17:48:47 +03007312 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007313 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08007314 }
7315
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007316 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7317 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7318 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06007319 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
Jani Nikula1a915102013-10-16 12:34:48 +03007320 } else {
7321 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7322 }
Wu Fengguang3a9627f2011-12-09 20:42:19 +08007323
7324 if (intel_eld_uptodate(connector,
7325 aud_cntrl_st2, eldv,
7326 aud_cntl_st, IBX_ELD_ADDRESS,
7327 hdmiw_hdmiedid))
7328 return;
7329
Wu Fengguange0dac652011-09-05 14:25:34 +08007330 i = I915_READ(aud_cntrl_st2);
7331 i &= ~eldv;
7332 I915_WRITE(aud_cntrl_st2, i);
7333
7334 if (!eld[0])
7335 return;
7336
Wu Fengguange0dac652011-09-05 14:25:34 +08007337 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08007338 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08007339 I915_WRITE(aud_cntl_st, i);
7340
7341 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7342 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7343 for (i = 0; i < len; i++)
7344 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7345
7346 i = I915_READ(aud_cntrl_st2);
7347 i |= eldv;
7348 I915_WRITE(aud_cntrl_st2, i);
7349}
7350
7351void intel_write_eld(struct drm_encoder *encoder,
7352 struct drm_display_mode *mode)
7353{
7354 struct drm_crtc *crtc = encoder->crtc;
7355 struct drm_connector *connector;
7356 struct drm_device *dev = encoder->dev;
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358
7359 connector = drm_select_eld(encoder, mode);
7360 if (!connector)
7361 return;
7362
7363 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7364 connector->base.id,
7365 drm_get_connector_name(connector),
7366 connector->encoder->base.id,
7367 drm_get_encoder_name(connector->encoder));
7368
7369 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7370
7371 if (dev_priv->display.write_eld)
Jani Nikula34427052013-10-16 12:34:47 +03007372 dev_priv->display.write_eld(connector, crtc, mode);
Wu Fengguange0dac652011-09-05 14:25:34 +08007373}
7374
Jesse Barnes79e53942008-11-07 14:24:08 -08007375static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7376{
7377 struct drm_device *dev = crtc->dev;
7378 struct drm_i915_private *dev_priv = dev->dev_private;
7379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7380 bool visible = base != 0;
7381 u32 cntl;
7382
7383 if (intel_crtc->cursor_visible == visible)
7384 return;
7385
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007386 cntl = I915_READ(_CURACNTR);
Jesse Barnes79e53942008-11-07 14:24:08 -08007387 if (visible) {
7388 /* On these chipsets we can only modify the base whilst
7389 * the cursor is disabled.
7390 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007391 I915_WRITE(_CURABASE, base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007392
7393 cntl &= ~(CURSOR_FORMAT_MASK);
7394 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7395 cntl |= CURSOR_ENABLE |
7396 CURSOR_GAMMA_ENABLE |
7397 CURSOR_FORMAT_ARGB;
7398 } else
7399 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007400 I915_WRITE(_CURACNTR, cntl);
Jesse Barnes79e53942008-11-07 14:24:08 -08007401
7402 intel_crtc->cursor_visible = visible;
7403}
7404
7405static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7406{
7407 struct drm_device *dev = crtc->dev;
7408 struct drm_i915_private *dev_priv = dev->dev_private;
7409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410 int pipe = intel_crtc->pipe;
7411 bool visible = base != 0;
7412
7413 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08007414 uint32_t cntl = I915_READ(CURCNTR(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08007415 if (base) {
7416 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7417 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7418 cntl |= pipe << 28; /* Connect to correct pipe */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007419 } else {
Eric Anholtbad720f2009-10-22 16:11:14 -07007420 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
Zhenyu Wang2c072452009-06-05 15:38:42 +08007421 cntl |= CURSOR_MODE_DISABLE;
7422 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007423 I915_WRITE(CURCNTR(pipe), cntl);
Jesse Barnes79e53942008-11-07 14:24:08 -08007424
7425 intel_crtc->cursor_visible = visible;
7426 }
7427 /* and commit changes on next vblank */
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007428 POSTING_READ(CURCNTR(pipe));
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007429 I915_WRITE(CURBASE(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007430 POSTING_READ(CURBASE(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08007431}
7432
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007433static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7434{
7435 struct drm_device *dev = crtc->dev;
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438 int pipe = intel_crtc->pipe;
7439 bool visible = base != 0;
7440
7441 if (intel_crtc->cursor_visible != visible) {
7442 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7443 if (base) {
7444 cntl &= ~CURSOR_MODE;
7445 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7446 } else {
7447 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7448 cntl |= CURSOR_MODE_DISABLE;
7449 }
Ville Syrjälä6bbfa1c2013-11-02 21:07:39 -07007450 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Ville Syrjälä86d3efc2013-01-18 19:11:38 +02007451 cntl |= CURSOR_PIPE_CSC_ENABLE;
Paulo Zanoni1f5d76d2013-08-23 19:51:28 -03007452 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7453 }
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007454 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7455
7456 intel_crtc->cursor_visible = visible;
7457 }
7458 /* and commit changes on next vblank */
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007459 POSTING_READ(CURCNTR_IVB(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007460 I915_WRITE(CURBASE_IVB(pipe), base);
Daniel Vetterb2ea8ef2013-11-04 08:13:45 +01007461 POSTING_READ(CURBASE_IVB(pipe));
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007462}
7463
Jesse Barnes79e53942008-11-07 14:24:08 -08007464/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007465static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7466 bool on)
7467{
7468 struct drm_device *dev = crtc->dev;
7469 struct drm_i915_private *dev_priv = dev->dev_private;
7470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7471 int pipe = intel_crtc->pipe;
7472 int x = intel_crtc->cursor_x;
7473 int y = intel_crtc->cursor_y;
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007474 u32 base = 0, pos = 0;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007475 bool visible;
7476
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007477 if (on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007478 base = intel_crtc->cursor_addr;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007479
Ville Syrjäläd6e4db12013-09-04 18:25:31 +03007480 if (x >= intel_crtc->config.pipe_src_w)
7481 base = 0;
7482
7483 if (y >= intel_crtc->config.pipe_src_h)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007484 base = 0;
7485
7486 if (x < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007487 if (x + intel_crtc->cursor_width <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007488 base = 0;
7489
7490 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7491 x = -x;
7492 }
7493 pos |= x << CURSOR_X_SHIFT;
7494
7495 if (y < 0) {
Ville Syrjäläefc90642013-09-04 18:25:30 +03007496 if (y + intel_crtc->cursor_height <= 0)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007497 base = 0;
7498
7499 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7500 y = -y;
7501 }
7502 pos |= y << CURSOR_Y_SHIFT;
7503
7504 visible = base != 0;
7505 if (!visible && !intel_crtc->cursor_visible)
7506 return;
7507
Paulo Zanonib3dc6852013-11-02 21:07:33 -07007508 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07007509 I915_WRITE(CURPOS_IVB(pipe), pos);
7510 ivb_update_cursor(crtc, base);
7511 } else {
7512 I915_WRITE(CURPOS(pipe), pos);
7513 if (IS_845G(dev) || IS_I865G(dev))
7514 i845_update_cursor(crtc, base);
7515 else
7516 i9xx_update_cursor(crtc, base);
7517 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007518}
7519
Jesse Barnes79e53942008-11-07 14:24:08 -08007520static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00007521 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08007522 uint32_t handle,
7523 uint32_t width, uint32_t height)
7524{
7525 struct drm_device *dev = crtc->dev;
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00007528 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007529 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007530 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007531
Jesse Barnes79e53942008-11-07 14:24:08 -08007532 /* if we want to turn off the cursor ignore width and height */
7533 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007534 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007535 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00007536 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10007537 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007538 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08007539 }
7540
7541 /* Currently we only support 64x64 cursors */
7542 if (width != 64 || height != 64) {
7543 DRM_ERROR("we currently only support 64x64 cursors\n");
7544 return -EINVAL;
7545 }
7546
Chris Wilson05394f32010-11-08 19:18:58 +00007547 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00007548 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08007549 return -ENOENT;
7550
Chris Wilson05394f32010-11-08 19:18:58 +00007551 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007552 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10007553 ret = -ENOMEM;
7554 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08007555 }
7556
Dave Airlie71acb5e2008-12-30 20:31:46 +10007557 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007558 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05007559 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilson693db182013-03-05 14:52:39 +00007560 unsigned alignment;
7561
Chris Wilsond9e86c02010-11-10 16:40:20 +00007562 if (obj->tiling_mode) {
7563 DRM_ERROR("cursor cannot be tiled\n");
7564 ret = -EINVAL;
7565 goto fail_locked;
7566 }
7567
Chris Wilson693db182013-03-05 14:52:39 +00007568 /* Note that the w/a also requires 2 PTE of padding following
7569 * the bo. We currently fill all unused PTE with the shadow
7570 * page and so we should always have valid PTE following the
7571 * cursor preventing the VT-d warning.
7572 */
7573 alignment = 0;
7574 if (need_vtd_wa(dev))
7575 alignment = 64*1024;
7576
7577 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01007578 if (ret) {
7579 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01007580 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01007581 }
7582
Chris Wilsond9e86c02010-11-10 16:40:20 +00007583 ret = i915_gem_object_put_fence(obj);
7584 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01007585 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00007586 goto fail_unpin;
7587 }
7588
Ben Widawskyf343c5f2013-07-05 14:41:04 -07007589 addr = i915_gem_obj_ggtt_offset(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10007590 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01007591 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00007592 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01007593 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7594 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10007595 if (ret) {
7596 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007597 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10007598 }
Chris Wilson05394f32010-11-08 19:18:58 +00007599 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007600 }
7601
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007602 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04007603 I915_WRITE(CURSIZE, (height << 12) | width);
7604
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007605 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007606 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05007607 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00007608 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10007609 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7610 } else
Chris Wilsoncc98b412013-08-09 12:25:09 +01007611 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00007612 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007613 }
Jesse Barnes80824002009-09-10 15:28:06 -07007614
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007615 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007616
7617 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00007618 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01007619 intel_crtc->cursor_width = width;
7620 intel_crtc->cursor_height = height;
7621
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03007622 if (intel_crtc->active)
7623 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05007624
Jesse Barnes79e53942008-11-07 14:24:08 -08007625 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01007626fail_unpin:
Chris Wilsoncc98b412013-08-09 12:25:09 +01007627 i915_gem_object_unpin_from_display_plane(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05007628fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10007629 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00007630fail:
Chris Wilson05394f32010-11-08 19:18:58 +00007631 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10007632 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007633}
7634
7635static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7636{
Jesse Barnes79e53942008-11-07 14:24:08 -08007637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007638
Ville Syrjälä92e76c82013-10-21 19:01:58 +03007639 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7640 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
Jesse Barnes652c3932009-08-17 13:31:43 -07007641
Ville Syrjäläf2f5f772013-09-17 18:33:44 +03007642 if (intel_crtc->active)
7643 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08007644
7645 return 0;
7646}
7647
Jesse Barnes79e53942008-11-07 14:24:08 -08007648static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01007649 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08007650{
James Simmons72034252010-08-03 01:33:19 +01007651 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08007652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007653
James Simmons72034252010-08-03 01:33:19 +01007654 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007655 intel_crtc->lut_r[i] = red[i] >> 8;
7656 intel_crtc->lut_g[i] = green[i] >> 8;
7657 intel_crtc->lut_b[i] = blue[i] >> 8;
7658 }
7659
7660 intel_crtc_load_lut(crtc);
7661}
7662
Jesse Barnes79e53942008-11-07 14:24:08 -08007663/* VESA 640x480x72Hz mode to set on the pipe */
7664static struct drm_display_mode load_detect_mode = {
7665 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7667};
7668
Chris Wilsond2dff872011-04-19 08:36:26 +01007669static struct drm_framebuffer *
7670intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007671 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01007672 struct drm_i915_gem_object *obj)
7673{
7674 struct intel_framebuffer *intel_fb;
7675 int ret;
7676
7677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7678 if (!intel_fb) {
7679 drm_gem_object_unreference_unlocked(&obj->base);
7680 return ERR_PTR(-ENOMEM);
7681 }
7682
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007683 ret = i915_mutex_lock_interruptible(dev);
7684 if (ret)
7685 goto err;
7686
Chris Wilsond2dff872011-04-19 08:36:26 +01007687 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007688 mutex_unlock(&dev->struct_mutex);
7689 if (ret)
7690 goto err;
Chris Wilsond2dff872011-04-19 08:36:26 +01007691
7692 return &intel_fb->base;
Daniel Vetterdd4916c2013-10-09 21:23:51 +02007693err:
7694 drm_gem_object_unreference_unlocked(&obj->base);
7695 kfree(intel_fb);
7696
7697 return ERR_PTR(ret);
Chris Wilsond2dff872011-04-19 08:36:26 +01007698}
7699
7700static u32
7701intel_framebuffer_pitch_for_width(int width, int bpp)
7702{
7703 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7704 return ALIGN(pitch, 64);
7705}
7706
7707static u32
7708intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7709{
7710 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7711 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7712}
7713
7714static struct drm_framebuffer *
7715intel_framebuffer_create_for_mode(struct drm_device *dev,
7716 struct drm_display_mode *mode,
7717 int depth, int bpp)
7718{
7719 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00007720 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01007721
7722 obj = i915_gem_alloc_object(dev,
7723 intel_framebuffer_size_for_mode(mode, bpp));
7724 if (obj == NULL)
7725 return ERR_PTR(-ENOMEM);
7726
7727 mode_cmd.width = mode->hdisplay;
7728 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007729 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7730 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00007731 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01007732
7733 return intel_framebuffer_create(dev, &mode_cmd, obj);
7734}
7735
7736static struct drm_framebuffer *
7737mode_fits_in_fbdev(struct drm_device *dev,
7738 struct drm_display_mode *mode)
7739{
Daniel Vetter4520f532013-10-09 09:18:51 +02007740#ifdef CONFIG_DRM_I915_FBDEV
Chris Wilsond2dff872011-04-19 08:36:26 +01007741 struct drm_i915_private *dev_priv = dev->dev_private;
7742 struct drm_i915_gem_object *obj;
7743 struct drm_framebuffer *fb;
7744
7745 if (dev_priv->fbdev == NULL)
7746 return NULL;
7747
7748 obj = dev_priv->fbdev->ifb.obj;
7749 if (obj == NULL)
7750 return NULL;
7751
7752 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007753 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7754 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01007755 return NULL;
7756
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007757 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01007758 return NULL;
7759
7760 return fb;
Daniel Vetter4520f532013-10-09 09:18:51 +02007761#else
7762 return NULL;
7763#endif
Chris Wilsond2dff872011-04-19 08:36:26 +01007764}
7765
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007766bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01007767 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01007768 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08007769{
7770 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007771 struct intel_encoder *intel_encoder =
7772 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08007773 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007774 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08007775 struct drm_crtc *crtc = NULL;
7776 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02007777 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08007778 int i = -1;
7779
Chris Wilsond2dff872011-04-19 08:36:26 +01007780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7781 connector->base.id, drm_get_connector_name(connector),
7782 encoder->base.id, drm_get_encoder_name(encoder));
7783
Jesse Barnes79e53942008-11-07 14:24:08 -08007784 /*
7785 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01007786 *
Jesse Barnes79e53942008-11-07 14:24:08 -08007787 * - if the connector already has an assigned crtc, use it (but make
7788 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01007789 *
Jesse Barnes79e53942008-11-07 14:24:08 -08007790 * - try to find the first unused crtc that can drive this connector,
7791 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08007792 */
7793
7794 /* See if we already have a CRTC for this connector */
7795 if (encoder->crtc) {
7796 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01007797
Daniel Vetter7b240562012-12-12 00:35:33 +01007798 mutex_lock(&crtc->mutex);
7799
Daniel Vetter24218aa2012-08-12 19:27:11 +02007800 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01007801 old->load_detect_temp = false;
7802
7803 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02007804 if (connector->dpms != DRM_MODE_DPMS_ON)
7805 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01007806
Chris Wilson71731882011-04-19 23:10:58 +01007807 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08007808 }
7809
7810 /* Find an unused one (if possible) */
7811 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7812 i++;
7813 if (!(encoder->possible_crtcs & (1 << i)))
7814 continue;
7815 if (!possible_crtc->enabled) {
7816 crtc = possible_crtc;
7817 break;
7818 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007819 }
7820
7821 /*
7822 * If we didn't find an unused CRTC, don't use any.
7823 */
7824 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01007825 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7826 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007827 }
7828
Daniel Vetter7b240562012-12-12 00:35:33 +01007829 mutex_lock(&crtc->mutex);
Daniel Vetterfc303102012-07-09 10:40:58 +02007830 intel_encoder->new_crtc = to_intel_crtc(crtc);
7831 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007832
7833 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02007834 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01007835 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01007836 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08007837
Chris Wilson64927112011-04-20 07:25:26 +01007838 if (!mode)
7839 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08007840
Chris Wilsond2dff872011-04-19 08:36:26 +01007841 /* We need a framebuffer large enough to accommodate all accesses
7842 * that the plane may generate whilst we perform load detection.
7843 * We can not rely on the fbcon either being present (we get called
7844 * during its initialisation to detect all boot displays, or it may
7845 * not even exist) or that it is large enough to satisfy the
7846 * requested mode.
7847 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02007848 fb = mode_fits_in_fbdev(dev, mode);
7849 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01007850 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02007851 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7852 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01007853 } else
7854 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02007855 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01007856 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter7b240562012-12-12 00:35:33 +01007857 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00007858 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007859 }
Chris Wilsond2dff872011-04-19 08:36:26 +01007860
Chris Wilsonc0c36b942012-12-19 16:08:43 +00007861 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01007862 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01007863 if (old->release_fb)
7864 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter7b240562012-12-12 00:35:33 +01007865 mutex_unlock(&crtc->mutex);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00007866 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007867 }
Chris Wilson71731882011-04-19 23:10:58 +01007868
Jesse Barnes79e53942008-11-07 14:24:08 -08007869 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007870 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01007871 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08007872}
7873
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007874void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01007875 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08007876{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02007877 struct intel_encoder *intel_encoder =
7878 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01007879 struct drm_encoder *encoder = &intel_encoder->base;
Daniel Vetter7b240562012-12-12 00:35:33 +01007880 struct drm_crtc *crtc = encoder->crtc;
Jesse Barnes79e53942008-11-07 14:24:08 -08007881
Chris Wilsond2dff872011-04-19 08:36:26 +01007882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7883 connector->base.id, drm_get_connector_name(connector),
7884 encoder->base.id, drm_get_encoder_name(encoder));
7885
Chris Wilson8261b192011-04-19 23:18:09 +01007886 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02007887 to_intel_connector(connector)->new_encoder = NULL;
7888 intel_encoder->new_crtc = NULL;
7889 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01007890
Daniel Vetter36206362012-12-10 20:42:17 +01007891 if (old->release_fb) {
7892 drm_framebuffer_unregister_private(old->release_fb);
7893 drm_framebuffer_unreference(old->release_fb);
7894 }
Chris Wilsond2dff872011-04-19 08:36:26 +01007895
Daniel Vetter67c96402013-01-23 16:25:09 +00007896 mutex_unlock(&crtc->mutex);
Chris Wilson0622a532011-04-21 09:32:11 +01007897 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08007898 }
7899
Eric Anholtc751ce42010-03-25 11:48:48 -07007900 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02007901 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7902 connector->funcs->dpms(connector, old->dpms_mode);
Daniel Vetter7b240562012-12-12 00:35:33 +01007903
7904 mutex_unlock(&crtc->mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08007905}
7906
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007907static int i9xx_pll_refclk(struct drm_device *dev,
7908 const struct intel_crtc_config *pipe_config)
7909{
7910 struct drm_i915_private *dev_priv = dev->dev_private;
7911 u32 dpll = pipe_config->dpll_hw_state.dpll;
7912
7913 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
Ville Syrjäläe91e9412013-12-09 18:54:16 +02007914 return dev_priv->vbt.lvds_ssc_freq;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007915 else if (HAS_PCH_SPLIT(dev))
7916 return 120000;
7917 else if (!IS_GEN2(dev))
7918 return 96000;
7919 else
7920 return 48000;
7921}
7922
Jesse Barnes79e53942008-11-07 14:24:08 -08007923/* Returns the clock of the currently programmed mode of the given pipe. */
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007924static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7925 struct intel_crtc_config *pipe_config)
Jesse Barnes79e53942008-11-07 14:24:08 -08007926{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007927 struct drm_device *dev = crtc->base.dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08007928 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007929 int pipe = pipe_config->cpu_transcoder;
Ville Syrjälä293623f2013-09-13 16:18:46 +03007930 u32 dpll = pipe_config->dpll_hw_state.dpll;
Jesse Barnes79e53942008-11-07 14:24:08 -08007931 u32 fp;
7932 intel_clock_t clock;
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007933 int refclk = i9xx_pll_refclk(dev, pipe_config);
Jesse Barnes79e53942008-11-07 14:24:08 -08007934
7935 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Ville Syrjälä293623f2013-09-13 16:18:46 +03007936 fp = pipe_config->dpll_hw_state.fp0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007937 else
Ville Syrjälä293623f2013-09-13 16:18:46 +03007938 fp = pipe_config->dpll_hw_state.fp1;
Jesse Barnes79e53942008-11-07 14:24:08 -08007939
7940 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007941 if (IS_PINEVIEW(dev)) {
7942 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7943 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08007944 } else {
7945 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7946 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7947 }
7948
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007949 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007950 if (IS_PINEVIEW(dev))
7951 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7952 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08007953 else
7954 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08007955 DPLL_FPA01_P1_POST_DIV_SHIFT);
7956
7957 switch (dpll & DPLL_MODE_MASK) {
7958 case DPLLB_MODE_DAC_SERIAL:
7959 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7960 5 : 10;
7961 break;
7962 case DPLLB_MODE_LVDS:
7963 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7964 7 : 14;
7965 break;
7966 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08007967 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08007968 "mode\n", (int)(dpll & DPLL_MODE_MASK));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03007969 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08007970 }
7971
Daniel Vetterac58c3f2013-06-01 17:16:17 +02007972 if (IS_PINEVIEW(dev))
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007973 pineview_clock(refclk, &clock);
Daniel Vetterac58c3f2013-06-01 17:16:17 +02007974 else
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03007975 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08007976 } else {
Ville Syrjälä0fb58222014-01-10 14:06:46 +02007977 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02007978 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
Jesse Barnes79e53942008-11-07 14:24:08 -08007979
7980 if (is_lvds) {
7981 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7982 DPLL_FPA01_P1_POST_DIV_SHIFT);
Ville Syrjäläb1c560d2013-12-09 18:54:13 +02007983
7984 if (lvds & LVDS_CLKB_POWER_UP)
7985 clock.p2 = 7;
7986 else
7987 clock.p2 = 14;
Jesse Barnes79e53942008-11-07 14:24:08 -08007988 } else {
7989 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7990 clock.p1 = 2;
7991 else {
7992 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7993 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7994 }
7995 if (dpll & PLL_P2_DIVIDE_BY_4)
7996 clock.p2 = 4;
7997 else
7998 clock.p2 = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08007999 }
Ville Syrjäläda4a1ef2013-09-09 14:06:37 +03008000
8001 i9xx_clock(refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08008002 }
8003
Ville Syrjälä18442d02013-09-13 16:00:08 +03008004 /*
8005 * This value includes pixel_multiplier. We will use
Damien Lespiau241bfc32013-09-25 16:45:37 +01008006 * port_clock to compute adjusted_mode.crtc_clock in the
Ville Syrjälä18442d02013-09-13 16:00:08 +03008007 * encoder's get_config() function.
8008 */
8009 pipe_config->port_clock = clock.dot;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008010}
8011
Ville Syrjälä6878da02013-09-13 15:59:11 +03008012int intel_dotclock_calculate(int link_freq,
8013 const struct intel_link_m_n *m_n)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008014{
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008015 /*
8016 * The calculation for the data clock is:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008017 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008018 * But we want to avoid losing precison if possible, so:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008019 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008020 *
8021 * and the link clock is simpler:
Ville Syrjälä1041a022013-09-06 23:28:58 +03008022 * link_clock = (m * link_clock) / n
Jesse Barnes79e53942008-11-07 14:24:08 -08008023 */
8024
Ville Syrjälä6878da02013-09-13 15:59:11 +03008025 if (!m_n->link_n)
8026 return 0;
8027
8028 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8029}
8030
Ville Syrjälä18442d02013-09-13 16:00:08 +03008031static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8032 struct intel_crtc_config *pipe_config)
Ville Syrjälä6878da02013-09-13 15:59:11 +03008033{
8034 struct drm_device *dev = crtc->base.dev;
Ville Syrjälä18442d02013-09-13 16:00:08 +03008035
8036 /* read out port_clock from the DPLL */
8037 i9xx_crtc_clock_get(crtc, pipe_config);
Ville Syrjälä6878da02013-09-13 15:59:11 +03008038
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008039 /*
Ville Syrjälä18442d02013-09-13 16:00:08 +03008040 * This value does not include pixel_multiplier.
Damien Lespiau241bfc32013-09-25 16:45:37 +01008041 * We will check that port_clock and adjusted_mode.crtc_clock
Ville Syrjälä18442d02013-09-13 16:00:08 +03008042 * agree once we know their relationship in the encoder's
8043 * get_config() function.
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008044 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01008045 pipe_config->adjusted_mode.crtc_clock =
Ville Syrjälä18442d02013-09-13 16:00:08 +03008046 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8047 &pipe_config->fdi_m_n);
Jesse Barnes79e53942008-11-07 14:24:08 -08008048}
8049
8050/** Returns the currently programmed mode of the given pipe. */
8051struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8052 struct drm_crtc *crtc)
8053{
Jesse Barnes548f2452011-02-17 10:40:53 -08008054 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3b117c82013-04-17 20:15:07 +02008056 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008057 struct drm_display_mode *mode;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008058 struct intel_crtc_config pipe_config;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02008059 int htot = I915_READ(HTOTAL(cpu_transcoder));
8060 int hsync = I915_READ(HSYNC(cpu_transcoder));
8061 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8062 int vsync = I915_READ(VSYNC(cpu_transcoder));
Ville Syrjälä293623f2013-09-13 16:18:46 +03008063 enum pipe pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08008064
8065 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8066 if (!mode)
8067 return NULL;
8068
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008069 /*
8070 * Construct a pipe_config sufficient for getting the clock info
8071 * back out of crtc_clock_get.
8072 *
8073 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8074 * to use a real value here instead.
8075 */
Ville Syrjälä293623f2013-09-13 16:18:46 +03008076 pipe_config.cpu_transcoder = (enum transcoder) pipe;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008077 pipe_config.pixel_multiplier = 1;
Ville Syrjälä293623f2013-09-13 16:18:46 +03008078 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8079 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8080 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
Jesse Barnesf1f644d2013-06-27 00:39:25 +03008081 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8082
Ville Syrjälä773ae032013-09-23 17:48:20 +03008083 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
Jesse Barnes79e53942008-11-07 14:24:08 -08008084 mode->hdisplay = (htot & 0xffff) + 1;
8085 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8086 mode->hsync_start = (hsync & 0xffff) + 1;
8087 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8088 mode->vdisplay = (vtot & 0xffff) + 1;
8089 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8090 mode->vsync_start = (vsync & 0xffff) + 1;
8091 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8092
8093 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08008094
8095 return mode;
8096}
8097
Daniel Vetter3dec0092010-08-20 21:40:52 +02008098static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07008099{
8100 struct drm_device *dev = crtc->dev;
8101 drm_i915_private_t *dev_priv = dev->dev_private;
8102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8103 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008104 int dpll_reg = DPLL(pipe);
8105 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07008106
Eric Anholtbad720f2009-10-22 16:11:14 -07008107 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008108 return;
8109
8110 if (!dev_priv->lvds_downclock_avail)
8111 return;
8112
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008113 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008114 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08008115 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008116
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008117 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008118
8119 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8120 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008121 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08008122
Jesse Barnes652c3932009-08-17 13:31:43 -07008123 dpll = I915_READ(dpll_reg);
8124 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08008125 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008126 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008127}
8128
8129static void intel_decrease_pllclock(struct drm_crtc *crtc)
8130{
8131 struct drm_device *dev = crtc->dev;
8132 drm_i915_private_t *dev_priv = dev->dev_private;
8133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008134
Eric Anholtbad720f2009-10-22 16:11:14 -07008135 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07008136 return;
8137
8138 if (!dev_priv->lvds_downclock_avail)
8139 return;
8140
8141 /*
8142 * Since this is called by a timer, we should never get here in
8143 * the manual case.
8144 */
8145 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01008146 int pipe = intel_crtc->pipe;
8147 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02008148 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01008149
Zhao Yakui44d98a62009-10-09 11:39:40 +08008150 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008151
Sean Paul8ac5a6d2012-02-13 13:14:51 -05008152 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008153
Chris Wilson074b5e12012-05-02 12:07:06 +01008154 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07008155 dpll |= DISPLAY_RATE_SELECT_FPA1;
8156 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07008157 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07008158 dpll = I915_READ(dpll_reg);
8159 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08008160 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07008161 }
8162
8163}
8164
Chris Wilsonf047e392012-07-21 12:31:41 +01008165void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008166{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008167 struct drm_i915_private *dev_priv = dev->dev_private;
8168
8169 hsw_package_c8_gpu_busy(dev_priv);
8170 i915_update_gfx_val(dev_priv);
Chris Wilsonf047e392012-07-21 12:31:41 +01008171}
8172
8173void intel_mark_idle(struct drm_device *dev)
8174{
Paulo Zanonic67a4702013-08-19 13:18:09 -03008175 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson725a5b52013-01-08 11:02:57 +00008176 struct drm_crtc *crtc;
8177
Paulo Zanonic67a4702013-08-19 13:18:09 -03008178 hsw_package_c8_gpu_idle(dev_priv);
8179
Chris Wilson725a5b52013-01-08 11:02:57 +00008180 if (!i915_powersave)
8181 return;
8182
8183 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8184 if (!crtc->fb)
8185 continue;
8186
8187 intel_decrease_pllclock(crtc);
8188 }
Chris Wilsonb29c19b2013-09-25 17:34:56 +01008189
8190 if (dev_priv->info->gen >= 6)
8191 gen6_rps_idle(dev->dev_private);
Chris Wilsonf047e392012-07-21 12:31:41 +01008192}
8193
Chris Wilsonc65355b2013-06-06 16:53:41 -03008194void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8195 struct intel_ring_buffer *ring)
Chris Wilsonf047e392012-07-21 12:31:41 +01008196{
8197 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07008198 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07008199
8200 if (!i915_powersave)
8201 return;
8202
Jesse Barnes652c3932009-08-17 13:31:43 -07008203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07008204 if (!crtc->fb)
8205 continue;
8206
Chris Wilsonc65355b2013-06-06 16:53:41 -03008207 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8208 continue;
8209
8210 intel_increase_pllclock(crtc);
8211 if (ring && intel_fbc_enabled(dev))
8212 ring->fbc_dirty = true;
Jesse Barnes652c3932009-08-17 13:31:43 -07008213 }
Jesse Barnes652c3932009-08-17 13:31:43 -07008214}
8215
Jesse Barnes79e53942008-11-07 14:24:08 -08008216static void intel_crtc_destroy(struct drm_crtc *crtc)
8217{
8218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008219 struct drm_device *dev = crtc->dev;
8220 struct intel_unpin_work *work;
8221 unsigned long flags;
8222
8223 spin_lock_irqsave(&dev->event_lock, flags);
8224 work = intel_crtc->unpin_work;
8225 intel_crtc->unpin_work = NULL;
8226 spin_unlock_irqrestore(&dev->event_lock, flags);
8227
8228 if (work) {
8229 cancel_work_sync(&work->work);
8230 kfree(work);
8231 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008232
Mika Kuoppala40ccc722013-04-23 17:27:08 +03008233 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8234
Jesse Barnes79e53942008-11-07 14:24:08 -08008235 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02008236
Jesse Barnes79e53942008-11-07 14:24:08 -08008237 kfree(intel_crtc);
8238}
8239
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008240static void intel_unpin_work_fn(struct work_struct *__work)
8241{
8242 struct intel_unpin_work *work =
8243 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008244 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008245
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008246 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01008247 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00008248 drm_gem_object_unreference(&work->pending_flip_obj->base);
8249 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00008250
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008251 intel_update_fbc(dev);
8252 mutex_unlock(&dev->struct_mutex);
8253
8254 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8255 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8256
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008257 kfree(work);
8258}
8259
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008260static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01008261 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008262{
8263 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8265 struct intel_unpin_work *work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008266 unsigned long flags;
8267
8268 /* Ignore early vblank irqs */
8269 if (intel_crtc == NULL)
8270 return;
8271
8272 spin_lock_irqsave(&dev->event_lock, flags);
8273 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00008274
8275 /* Ensure we don't miss a work->pending update ... */
8276 smp_rmb();
8277
8278 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008279 spin_unlock_irqrestore(&dev->event_lock, flags);
8280 return;
8281 }
8282
Chris Wilsone7d841c2012-12-03 11:36:30 +00008283 /* and that the unpin work is consistent wrt ->pending. */
8284 smp_rmb();
8285
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008286 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008287
Rob Clark45a066e2012-10-08 14:50:40 -05008288 if (work->event)
8289 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008290
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01008291 drm_vblank_put(dev, intel_crtc->pipe);
8292
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008293 spin_unlock_irqrestore(&dev->event_lock, flags);
8294
Daniel Vetter2c10d572012-12-20 21:24:07 +01008295 wake_up_all(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008296
8297 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07008298
8299 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008300}
8301
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008302void intel_finish_page_flip(struct drm_device *dev, int pipe)
8303{
8304 drm_i915_private_t *dev_priv = dev->dev_private;
8305 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8306
Mario Kleiner49b14a52010-12-09 07:00:07 +01008307 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008308}
8309
8310void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8311{
8312 drm_i915_private_t *dev_priv = dev->dev_private;
8313 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8314
Mario Kleiner49b14a52010-12-09 07:00:07 +01008315 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07008316}
8317
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008318void intel_prepare_page_flip(struct drm_device *dev, int plane)
8319{
8320 drm_i915_private_t *dev_priv = dev->dev_private;
8321 struct intel_crtc *intel_crtc =
8322 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8323 unsigned long flags;
8324
Chris Wilsone7d841c2012-12-03 11:36:30 +00008325 /* NB: An MMIO update of the plane base pointer will also
8326 * generate a page-flip completion irq, i.e. every modeset
8327 * is also accompanied by a spurious intel_prepare_page_flip().
8328 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008329 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008330 if (intel_crtc->unpin_work)
8331 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008332 spin_unlock_irqrestore(&dev->event_lock, flags);
8333}
8334
Chris Wilsone7d841c2012-12-03 11:36:30 +00008335inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8336{
8337 /* Ensure that the work item is consistent when activating it ... */
8338 smp_wmb();
8339 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8340 /* and that it is marked active as soon as the irq could fire. */
8341 smp_wmb();
8342}
8343
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008344static int intel_gen2_queue_flip(struct drm_device *dev,
8345 struct drm_crtc *crtc,
8346 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008347 struct drm_i915_gem_object *obj,
8348 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008349{
8350 struct drm_i915_private *dev_priv = dev->dev_private;
8351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008352 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008353 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008354 int ret;
8355
Daniel Vetter6d90c952012-04-26 23:28:05 +02008356 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008357 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008358 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008359
Daniel Vetter6d90c952012-04-26 23:28:05 +02008360 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008361 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008362 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008363
8364 /* Can't queue multiple flips, so wait for the previous
8365 * one to finish before executing the next.
8366 */
8367 if (intel_crtc->plane)
8368 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8369 else
8370 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008371 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8372 intel_ring_emit(ring, MI_NOOP);
8373 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8374 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8375 intel_ring_emit(ring, fb->pitches[0]);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008376 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008377 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00008378
8379 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008380 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008381 return 0;
8382
8383err_unpin:
8384 intel_unpin_fb_obj(obj);
8385err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008386 return ret;
8387}
8388
8389static int intel_gen3_queue_flip(struct drm_device *dev,
8390 struct drm_crtc *crtc,
8391 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008392 struct drm_i915_gem_object *obj,
8393 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008394{
8395 struct drm_i915_private *dev_priv = dev->dev_private;
8396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008397 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008398 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008399 int ret;
8400
Daniel Vetter6d90c952012-04-26 23:28:05 +02008401 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008402 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008403 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008404
Daniel Vetter6d90c952012-04-26 23:28:05 +02008405 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008406 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008407 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008408
8409 if (intel_crtc->plane)
8410 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8411 else
8412 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008413 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8414 intel_ring_emit(ring, MI_NOOP);
8415 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8416 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8417 intel_ring_emit(ring, fb->pitches[0]);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008418 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008419 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008420
Chris Wilsone7d841c2012-12-03 11:36:30 +00008421 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008422 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008423 return 0;
8424
8425err_unpin:
8426 intel_unpin_fb_obj(obj);
8427err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008428 return ret;
8429}
8430
8431static int intel_gen4_queue_flip(struct drm_device *dev,
8432 struct drm_crtc *crtc,
8433 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008434 struct drm_i915_gem_object *obj,
8435 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008436{
8437 struct drm_i915_private *dev_priv = dev->dev_private;
8438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8439 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008440 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008441 int ret;
8442
Daniel Vetter6d90c952012-04-26 23:28:05 +02008443 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008444 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008445 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008446
Daniel Vetter6d90c952012-04-26 23:28:05 +02008447 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008448 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008449 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008450
8451 /* i965+ uses the linear or tiled offsets from the
8452 * Display Registers (which do not change across a page-flip)
8453 * so we need only reprogram the base address.
8454 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02008455 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8456 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8457 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02008458 intel_ring_emit(ring,
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008459 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
Daniel Vetterc2c75132012-07-05 12:17:30 +02008460 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008461
8462 /* XXX Enabling the panel-fitter across page-flip is so far
8463 * untested on non-native modes, so ignore it for now.
8464 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8465 */
8466 pf = 0;
8467 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008468 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008469
8470 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008471 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008472 return 0;
8473
8474err_unpin:
8475 intel_unpin_fb_obj(obj);
8476err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008477 return ret;
8478}
8479
8480static int intel_gen6_queue_flip(struct drm_device *dev,
8481 struct drm_crtc *crtc,
8482 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008483 struct drm_i915_gem_object *obj,
8484 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008485{
8486 struct drm_i915_private *dev_priv = dev->dev_private;
8487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02008488 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008489 uint32_t pf, pipesrc;
8490 int ret;
8491
Daniel Vetter6d90c952012-04-26 23:28:05 +02008492 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008493 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008494 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008495
Daniel Vetter6d90c952012-04-26 23:28:05 +02008496 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008497 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008498 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008499
Daniel Vetter6d90c952012-04-26 23:28:05 +02008500 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8501 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8502 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008503 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008504
Chris Wilson99d9acd2012-04-17 20:37:00 +01008505 /* Contrary to the suggestions in the documentation,
8506 * "Enable Panel Fitter" does not seem to be required when page
8507 * flipping with a non-native mode, and worse causes a normal
8508 * modeset to fail.
8509 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8510 */
8511 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008512 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02008513 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00008514
8515 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008516 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008517 return 0;
8518
8519err_unpin:
8520 intel_unpin_fb_obj(obj);
8521err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008522 return ret;
8523}
8524
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008525static int intel_gen7_queue_flip(struct drm_device *dev,
8526 struct drm_crtc *crtc,
8527 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008528 struct drm_i915_gem_object *obj,
8529 uint32_t flags)
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008530{
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilsonffe74d72013-08-26 20:58:12 +01008533 struct intel_ring_buffer *ring;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008534 uint32_t plane_bit = 0;
Chris Wilsonffe74d72013-08-26 20:58:12 +01008535 int len, ret;
8536
8537 ring = obj->ring;
Chris Wilson1c5fd082013-09-04 10:54:30 +01008538 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
Chris Wilsonffe74d72013-08-26 20:58:12 +01008539 ring = &dev_priv->ring[BCS];
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008540
8541 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8542 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008543 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008544
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008545 switch(intel_crtc->plane) {
8546 case PLANE_A:
8547 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8548 break;
8549 case PLANE_B:
8550 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8551 break;
8552 case PLANE_C:
8553 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8554 break;
8555 default:
8556 WARN_ONCE(1, "unknown plane in flip command\n");
8557 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03008558 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008559 }
8560
Chris Wilsonffe74d72013-08-26 20:58:12 +01008561 len = 4;
8562 if (ring->id == RCS)
8563 len += 6;
8564
8565 ret = intel_ring_begin(ring, len);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008566 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01008567 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008568
Chris Wilsonffe74d72013-08-26 20:58:12 +01008569 /* Unmask the flip-done completion message. Note that the bspec says that
8570 * we should do this for both the BCS and RCS, and that we must not unmask
8571 * more than one flip event at any time (or ensure that one flip message
8572 * can be sent by waiting for flip-done prior to queueing new flips).
8573 * Experimentation says that BCS works despite DERRMR masking all
8574 * flip-done completion events and that unmasking all planes at once
8575 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8576 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8577 */
8578 if (ring->id == RCS) {
8579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8580 intel_ring_emit(ring, DERRMR);
8581 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8582 DERRMR_PIPEB_PRI_FLIP_DONE |
8583 DERRMR_PIPEC_PRI_FLIP_DONE));
8584 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8585 intel_ring_emit(ring, DERRMR);
8586 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8587 }
8588
Daniel Vettercb05d8d2012-05-23 14:02:00 +02008589 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02008590 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Ben Widawskyf343c5f2013-07-05 14:41:04 -07008591 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008592 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00008593
8594 intel_mark_page_flip_active(intel_crtc);
Chris Wilson09246732013-08-10 22:16:32 +01008595 __intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01008596 return 0;
8597
8598err_unpin:
8599 intel_unpin_fb_obj(obj);
8600err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008601 return ret;
8602}
8603
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008604static int intel_default_queue_flip(struct drm_device *dev,
8605 struct drm_crtc *crtc,
8606 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008607 struct drm_i915_gem_object *obj,
8608 uint32_t flags)
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008609{
8610 return -ENODEV;
8611}
8612
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008613static int intel_crtc_page_flip(struct drm_crtc *crtc,
8614 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -07008615 struct drm_pending_vblank_event *event,
8616 uint32_t page_flip_flags)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008617{
8618 struct drm_device *dev = crtc->dev;
8619 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008620 struct drm_framebuffer *old_fb = crtc->fb;
8621 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008624 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01008625 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008626
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03008627 /* Can't change pixel format via MI display flips. */
8628 if (fb->pixel_format != crtc->fb->pixel_format)
8629 return -EINVAL;
8630
8631 /*
8632 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8633 * Note that pitch changes could also affect these register.
8634 */
8635 if (INTEL_INFO(dev)->gen > 3 &&
8636 (fb->offsets[0] != crtc->fb->offsets[0] ||
8637 fb->pitches[0] != crtc->fb->pitches[0]))
8638 return -EINVAL;
8639
Daniel Vetterb14c5672013-09-19 12:18:32 +02008640 work = kzalloc(sizeof(*work), GFP_KERNEL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008641 if (work == NULL)
8642 return -ENOMEM;
8643
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008644 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008645 work->crtc = crtc;
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008646 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008647 INIT_WORK(&work->work, intel_unpin_work_fn);
8648
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008649 ret = drm_vblank_get(dev, intel_crtc->pipe);
8650 if (ret)
8651 goto free_work;
8652
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008653 /* We borrow the event spin lock for protecting unpin_work */
8654 spin_lock_irqsave(&dev->event_lock, flags);
8655 if (intel_crtc->unpin_work) {
8656 spin_unlock_irqrestore(&dev->event_lock, flags);
8657 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008658 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01008659
8660 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008661 return -EBUSY;
8662 }
8663 intel_crtc->unpin_work = work;
8664 spin_unlock_irqrestore(&dev->event_lock, flags);
8665
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008666 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8667 flush_workqueue(dev_priv->wq);
8668
Chris Wilson79158102012-05-23 11:13:58 +01008669 ret = i915_mutex_lock_interruptible(dev);
8670 if (ret)
8671 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008672
Jesse Barnes75dfca82010-02-10 15:09:44 -08008673 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00008674 drm_gem_object_reference(&work->old_fb_obj->base);
8675 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008676
8677 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01008678
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008679 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008680
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01008681 work->enable_stall_check = true;
8682
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008683 atomic_inc(&intel_crtc->unpin_work_count);
Ville Syrjälä10d83732013-01-29 18:13:34 +02008684 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01008685
Keith Packarded8d1972013-07-22 18:49:58 -07008686 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008687 if (ret)
8688 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008689
Chris Wilson7782de32011-07-08 12:22:41 +01008690 intel_disable_fbc(dev);
Chris Wilsonc65355b2013-06-06 16:53:41 -03008691 intel_mark_fb_busy(obj, NULL);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008692 mutex_unlock(&dev->struct_mutex);
8693
Jesse Barnese5510fa2010-07-01 16:48:37 -07008694 trace_i915_flip_request(intel_crtc->plane, obj);
8695
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008696 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01008697
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008698cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00008699 atomic_dec(&intel_crtc->unpin_work_count);
Ville Syrjälä4a35f832013-02-22 16:53:38 +02008700 crtc->fb = old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00008701 drm_gem_object_unreference(&work->old_fb_obj->base);
8702 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01008703 mutex_unlock(&dev->struct_mutex);
8704
Chris Wilson79158102012-05-23 11:13:58 +01008705cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01008706 spin_lock_irqsave(&dev->event_lock, flags);
8707 intel_crtc->unpin_work = NULL;
8708 spin_unlock_irqrestore(&dev->event_lock, flags);
8709
Jesse Barnes7317c75e62011-08-29 09:45:28 -07008710 drm_vblank_put(dev, intel_crtc->pipe);
8711free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01008712 kfree(work);
8713
8714 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05008715}
8716
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008717static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008718 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8719 .load_lut = intel_crtc_load_lut,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008720};
8721
Daniel Vetter50f56112012-07-02 09:35:43 +02008722static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8723 struct drm_crtc *crtc)
8724{
8725 struct drm_device *dev;
8726 struct drm_crtc *tmp;
8727 int crtc_mask = 1;
8728
8729 WARN(!crtc, "checking null crtc?\n");
8730
8731 dev = crtc->dev;
8732
8733 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8734 if (tmp == crtc)
8735 break;
8736 crtc_mask <<= 1;
8737 }
8738
8739 if (encoder->possible_crtcs & crtc_mask)
8740 return true;
8741 return false;
8742}
8743
Daniel Vetter9a935852012-07-05 22:34:27 +02008744/**
8745 * intel_modeset_update_staged_output_state
8746 *
8747 * Updates the staged output configuration state, e.g. after we've read out the
8748 * current hw state.
8749 */
8750static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8751{
8752 struct intel_encoder *encoder;
8753 struct intel_connector *connector;
8754
8755 list_for_each_entry(connector, &dev->mode_config.connector_list,
8756 base.head) {
8757 connector->new_encoder =
8758 to_intel_encoder(connector->base.encoder);
8759 }
8760
8761 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8762 base.head) {
8763 encoder->new_crtc =
8764 to_intel_crtc(encoder->base.crtc);
8765 }
8766}
8767
8768/**
8769 * intel_modeset_commit_output_state
8770 *
8771 * This function copies the stage display pipe configuration to the real one.
8772 */
8773static void intel_modeset_commit_output_state(struct drm_device *dev)
8774{
8775 struct intel_encoder *encoder;
8776 struct intel_connector *connector;
8777
8778 list_for_each_entry(connector, &dev->mode_config.connector_list,
8779 base.head) {
8780 connector->base.encoder = &connector->new_encoder->base;
8781 }
8782
8783 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8784 base.head) {
8785 encoder->base.crtc = &encoder->new_crtc->base;
8786 }
8787}
8788
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008789static void
8790connected_sink_compute_bpp(struct intel_connector * connector,
8791 struct intel_crtc_config *pipe_config)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008792{
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008793 int bpp = pipe_config->pipe_bpp;
8794
8795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8796 connector->base.base.id,
8797 drm_get_connector_name(&connector->base));
8798
8799 /* Don't use an invalid EDID bpc value */
8800 if (connector->base.display_info.bpc &&
8801 connector->base.display_info.bpc * 3 < bpp) {
8802 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8803 bpp, connector->base.display_info.bpc*3);
8804 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8805 }
8806
8807 /* Clamp bpp to 8 on screens without EDID 1.4 */
8808 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8809 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8810 bpp);
8811 pipe_config->pipe_bpp = 24;
8812 }
8813}
8814
8815static int
8816compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8817 struct drm_framebuffer *fb,
8818 struct intel_crtc_config *pipe_config)
8819{
8820 struct drm_device *dev = crtc->base.dev;
8821 struct intel_connector *connector;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008822 int bpp;
8823
Daniel Vetterd42264b2013-03-28 16:38:08 +01008824 switch (fb->pixel_format) {
8825 case DRM_FORMAT_C8:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008826 bpp = 8*3; /* since we go through a colormap */
8827 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008828 case DRM_FORMAT_XRGB1555:
8829 case DRM_FORMAT_ARGB1555:
8830 /* checked in intel_framebuffer_init already */
8831 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8832 return -EINVAL;
8833 case DRM_FORMAT_RGB565:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008834 bpp = 6*3; /* min is 18bpp */
8835 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008836 case DRM_FORMAT_XBGR8888:
8837 case DRM_FORMAT_ABGR8888:
8838 /* checked in intel_framebuffer_init already */
8839 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8840 return -EINVAL;
8841 case DRM_FORMAT_XRGB8888:
8842 case DRM_FORMAT_ARGB8888:
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008843 bpp = 8*3;
8844 break;
Daniel Vetterd42264b2013-03-28 16:38:08 +01008845 case DRM_FORMAT_XRGB2101010:
8846 case DRM_FORMAT_ARGB2101010:
8847 case DRM_FORMAT_XBGR2101010:
8848 case DRM_FORMAT_ABGR2101010:
8849 /* checked in intel_framebuffer_init already */
8850 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
Daniel Vetterbaba1332013-03-27 00:45:00 +01008851 return -EINVAL;
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008852 bpp = 10*3;
8853 break;
Daniel Vetterbaba1332013-03-27 00:45:00 +01008854 /* TODO: gen4+ supports 16 bpc floating point, too. */
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008855 default:
8856 DRM_DEBUG_KMS("unsupported depth\n");
8857 return -EINVAL;
8858 }
8859
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008860 pipe_config->pipe_bpp = bpp;
8861
8862 /* Clamp display bpp to EDID value */
8863 list_for_each_entry(connector, &dev->mode_config.connector_list,
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008864 base.head) {
Daniel Vetter1b829e02013-06-02 13:26:24 +02008865 if (!connector->new_encoder ||
8866 connector->new_encoder->new_crtc != crtc)
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008867 continue;
8868
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008869 connected_sink_compute_bpp(connector, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008870 }
8871
8872 return bpp;
8873}
8874
Daniel Vetter644db712013-09-19 14:53:58 +02008875static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8876{
8877 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8878 "type: 0x%x flags: 0x%x\n",
Damien Lespiau13428302013-09-25 16:45:36 +01008879 mode->crtc_clock,
Daniel Vetter644db712013-09-19 14:53:58 +02008880 mode->crtc_hdisplay, mode->crtc_hsync_start,
8881 mode->crtc_hsync_end, mode->crtc_htotal,
8882 mode->crtc_vdisplay, mode->crtc_vsync_start,
8883 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8884}
8885
Daniel Vetterc0b03412013-05-28 12:05:54 +02008886static void intel_dump_pipe_config(struct intel_crtc *crtc,
8887 struct intel_crtc_config *pipe_config,
8888 const char *context)
8889{
8890 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8891 context, pipe_name(crtc->pipe));
8892
8893 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8894 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8895 pipe_config->pipe_bpp, pipe_config->dither);
8896 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8897 pipe_config->has_pch_encoder,
8898 pipe_config->fdi_lanes,
8899 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8900 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8901 pipe_config->fdi_m_n.tu);
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03008902 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8903 pipe_config->has_dp_encoder,
8904 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8905 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8906 pipe_config->dp_m_n.tu);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008907 DRM_DEBUG_KMS("requested mode:\n");
8908 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8909 DRM_DEBUG_KMS("adjusted mode:\n");
8910 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
Daniel Vetter644db712013-09-19 14:53:58 +02008911 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03008912 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03008913 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8914 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008915 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8916 pipe_config->gmch_pfit.control,
8917 pipe_config->gmch_pfit.pgm_ratios,
8918 pipe_config->gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01008919 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
Daniel Vetterc0b03412013-05-28 12:05:54 +02008920 pipe_config->pch_pfit.pos,
Chris Wilsonfd4daa92013-08-27 17:04:17 +01008921 pipe_config->pch_pfit.size,
8922 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
Paulo Zanoni42db64e2013-05-31 16:33:22 -03008923 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
Ville Syrjäläcf532bb2013-09-04 18:30:02 +03008924 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
Daniel Vetterc0b03412013-05-28 12:05:54 +02008925}
8926
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02008927static bool check_encoder_cloning(struct drm_crtc *crtc)
8928{
8929 int num_encoders = 0;
8930 bool uncloneable_encoders = false;
8931 struct intel_encoder *encoder;
8932
8933 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8934 base.head) {
8935 if (&encoder->new_crtc->base != crtc)
8936 continue;
8937
8938 num_encoders++;
8939 if (!encoder->cloneable)
8940 uncloneable_encoders = true;
8941 }
8942
8943 return !(num_encoders > 1 && uncloneable_encoders);
8944}
8945
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008946static struct intel_crtc_config *
8947intel_modeset_pipe_config(struct drm_crtc *crtc,
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008948 struct drm_framebuffer *fb,
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008949 struct drm_display_mode *mode)
Daniel Vetter7758a112012-07-08 19:40:39 +02008950{
8951 struct drm_device *dev = crtc->dev;
Daniel Vetter7758a112012-07-08 19:40:39 +02008952 struct intel_encoder *encoder;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008953 struct intel_crtc_config *pipe_config;
Daniel Vettere29c22c2013-02-21 00:00:16 +01008954 int plane_bpp, ret = -EINVAL;
8955 bool retry = true;
Daniel Vetter7758a112012-07-08 19:40:39 +02008956
Daniel Vetteraccfc0c2013-05-30 15:04:25 +02008957 if (!check_encoder_cloning(crtc)) {
8958 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8959 return ERR_PTR(-EINVAL);
8960 }
8961
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008962 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8963 if (!pipe_config)
Daniel Vetter7758a112012-07-08 19:40:39 +02008964 return ERR_PTR(-ENOMEM);
8965
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008966 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8967 drm_mode_copy(&pipe_config->requested_mode, mode);
Ville Syrjälä37327ab2013-09-04 18:25:28 +03008968
Daniel Vettere143a212013-07-04 12:01:15 +02008969 pipe_config->cpu_transcoder =
8970 (enum transcoder) to_intel_crtc(crtc)->pipe;
Daniel Vetterc0d43d62013-06-07 23:11:08 +02008971 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01008972
Imre Deak2960bc92013-07-30 13:36:32 +03008973 /*
8974 * Sanitize sync polarity flags based on requested ones. If neither
8975 * positive or negative polarity is requested, treat this as meaning
8976 * negative polarity.
8977 */
8978 if (!(pipe_config->adjusted_mode.flags &
8979 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8980 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8981
8982 if (!(pipe_config->adjusted_mode.flags &
8983 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8984 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8985
Daniel Vetter050f7ae2013-06-02 13:26:23 +02008986 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8987 * plane pixel format and any sink constraints into account. Returns the
8988 * source plane bpp so that dithering can be selected on mismatches
8989 * after encoders and crtc also have had their say. */
8990 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8991 fb, pipe_config);
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01008992 if (plane_bpp < 0)
8993 goto fail;
8994
Ville Syrjäläe41a56b2013-10-01 22:52:14 +03008995 /*
8996 * Determine the real pipe dimensions. Note that stereo modes can
8997 * increase the actual pipe size due to the frame doubling and
8998 * insertion of additional space for blanks between the frame. This
8999 * is stored in the crtc timings. We use the requested mode to do this
9000 * computation to clearly distinguish it from the adjusted mode, which
9001 * can be changed by the connectors in the below retry loop.
9002 */
9003 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9004 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9005 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9006
Daniel Vettere29c22c2013-02-21 00:00:16 +01009007encoder_retry:
Daniel Vetteref1b4602013-06-01 17:17:04 +02009008 /* Ensure the port clock defaults are reset when retrying. */
Daniel Vetterff9a6752013-06-01 17:16:21 +02009009 pipe_config->port_clock = 0;
Daniel Vetteref1b4602013-06-01 17:17:04 +02009010 pipe_config->pixel_multiplier = 1;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009011
Daniel Vetter135c81b2013-07-21 21:37:09 +02009012 /* Fill in default crtc timings, allow encoders to overwrite them. */
Damien Lespiau6ce70f52013-09-25 16:45:38 +01009013 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
Daniel Vetter135c81b2013-07-21 21:37:09 +02009014
Daniel Vetter7758a112012-07-08 19:40:39 +02009015 /* Pass our mode to the connectors and the CRTC to give them a chance to
9016 * adjust it according to limitations or connector properties, and also
9017 * a chance to reject the mode entirely.
9018 */
9019 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9020 base.head) {
9021
9022 if (&encoder->new_crtc->base != crtc)
9023 continue;
Daniel Vetter7ae89232013-03-27 00:44:52 +01009024
Daniel Vetterefea6e82013-07-21 21:36:59 +02009025 if (!(encoder->compute_config(encoder, pipe_config))) {
9026 DRM_DEBUG_KMS("Encoder config failure\n");
Daniel Vetter7758a112012-07-08 19:40:39 +02009027 goto fail;
9028 }
9029 }
9030
Daniel Vetterff9a6752013-06-01 17:16:21 +02009031 /* Set default port clock if not overwritten by the encoder. Needs to be
9032 * done afterwards in case the encoder adjusts the mode. */
9033 if (!pipe_config->port_clock)
Damien Lespiau241bfc32013-09-25 16:45:37 +01009034 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9035 * pipe_config->pixel_multiplier;
Daniel Vetterff9a6752013-06-01 17:16:21 +02009036
Daniel Vettera43f6e02013-06-07 23:10:32 +02009037 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009038 if (ret < 0) {
Daniel Vetter7758a112012-07-08 19:40:39 +02009039 DRM_DEBUG_KMS("CRTC fixup failed\n");
9040 goto fail;
9041 }
Daniel Vettere29c22c2013-02-21 00:00:16 +01009042
9043 if (ret == RETRY) {
9044 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9045 ret = -EINVAL;
9046 goto fail;
9047 }
9048
9049 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9050 retry = false;
9051 goto encoder_retry;
9052 }
9053
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009054 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9055 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9056 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9057
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009058 return pipe_config;
Daniel Vetter7758a112012-07-08 19:40:39 +02009059fail:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009060 kfree(pipe_config);
Daniel Vettere29c22c2013-02-21 00:00:16 +01009061 return ERR_PTR(ret);
Daniel Vetter7758a112012-07-08 19:40:39 +02009062}
9063
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009064/* Computes which crtcs are affected and sets the relevant bits in the mask. For
9065 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9066static void
9067intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9068 unsigned *prepare_pipes, unsigned *disable_pipes)
9069{
9070 struct intel_crtc *intel_crtc;
9071 struct drm_device *dev = crtc->dev;
9072 struct intel_encoder *encoder;
9073 struct intel_connector *connector;
9074 struct drm_crtc *tmp_crtc;
9075
9076 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9077
9078 /* Check which crtcs have changed outputs connected to them, these need
9079 * to be part of the prepare_pipes mask. We don't (yet) support global
9080 * modeset across multiple crtcs, so modeset_pipes will only have one
9081 * bit set at most. */
9082 list_for_each_entry(connector, &dev->mode_config.connector_list,
9083 base.head) {
9084 if (connector->base.encoder == &connector->new_encoder->base)
9085 continue;
9086
9087 if (connector->base.encoder) {
9088 tmp_crtc = connector->base.encoder->crtc;
9089
9090 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9091 }
9092
9093 if (connector->new_encoder)
9094 *prepare_pipes |=
9095 1 << connector->new_encoder->new_crtc->pipe;
9096 }
9097
9098 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9099 base.head) {
9100 if (encoder->base.crtc == &encoder->new_crtc->base)
9101 continue;
9102
9103 if (encoder->base.crtc) {
9104 tmp_crtc = encoder->base.crtc;
9105
9106 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9107 }
9108
9109 if (encoder->new_crtc)
9110 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9111 }
9112
9113 /* Check for any pipes that will be fully disabled ... */
9114 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9115 base.head) {
9116 bool used = false;
9117
9118 /* Don't try to disable disabled crtcs. */
9119 if (!intel_crtc->base.enabled)
9120 continue;
9121
9122 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9123 base.head) {
9124 if (encoder->new_crtc == intel_crtc)
9125 used = true;
9126 }
9127
9128 if (!used)
9129 *disable_pipes |= 1 << intel_crtc->pipe;
9130 }
9131
9132
9133 /* set_mode is also used to update properties on life display pipes. */
9134 intel_crtc = to_intel_crtc(crtc);
9135 if (crtc->enabled)
9136 *prepare_pipes |= 1 << intel_crtc->pipe;
9137
Daniel Vetterb6c51642013-04-12 18:48:43 +02009138 /*
9139 * For simplicity do a full modeset on any pipe where the output routing
9140 * changed. We could be more clever, but that would require us to be
9141 * more careful with calling the relevant encoder->mode_set functions.
9142 */
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009143 if (*prepare_pipes)
9144 *modeset_pipes = *prepare_pipes;
9145
9146 /* ... and mask these out. */
9147 *modeset_pipes &= ~(*disable_pipes);
9148 *prepare_pipes &= ~(*disable_pipes);
Daniel Vetterb6c51642013-04-12 18:48:43 +02009149
9150 /*
9151 * HACK: We don't (yet) fully support global modesets. intel_set_config
9152 * obies this rule, but the modeset restore mode of
9153 * intel_modeset_setup_hw_state does not.
9154 */
9155 *modeset_pipes &= 1 << intel_crtc->pipe;
9156 *prepare_pipes &= 1 << intel_crtc->pipe;
Daniel Vettere3641d32013-04-11 19:49:07 +02009157
9158 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9159 *modeset_pipes, *prepare_pipes, *disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009160}
9161
Daniel Vetterea9d7582012-07-10 10:42:52 +02009162static bool intel_crtc_in_use(struct drm_crtc *crtc)
9163{
9164 struct drm_encoder *encoder;
9165 struct drm_device *dev = crtc->dev;
9166
9167 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9168 if (encoder->crtc == crtc)
9169 return true;
9170
9171 return false;
9172}
9173
9174static void
9175intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9176{
9177 struct intel_encoder *intel_encoder;
9178 struct intel_crtc *intel_crtc;
9179 struct drm_connector *connector;
9180
9181 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9182 base.head) {
9183 if (!intel_encoder->base.crtc)
9184 continue;
9185
9186 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9187
9188 if (prepare_pipes & (1 << intel_crtc->pipe))
9189 intel_encoder->connectors_active = false;
9190 }
9191
9192 intel_modeset_commit_output_state(dev);
9193
9194 /* Update computed state. */
9195 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9196 base.head) {
9197 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9198 }
9199
9200 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9201 if (!connector->encoder || !connector->encoder->crtc)
9202 continue;
9203
9204 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9205
9206 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02009207 struct drm_property *dpms_property =
9208 dev->mode_config.dpms_property;
9209
Daniel Vetterea9d7582012-07-10 10:42:52 +02009210 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05009211 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02009212 dpms_property,
9213 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02009214
9215 intel_encoder = to_intel_encoder(connector->encoder);
9216 intel_encoder->connectors_active = true;
9217 }
9218 }
9219
9220}
9221
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009222static bool intel_fuzzy_clock_check(int clock1, int clock2)
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009223{
Ville Syrjälä3bd26262013-09-06 23:29:02 +03009224 int diff;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03009225
9226 if (clock1 == clock2)
9227 return true;
9228
9229 if (!clock1 || !clock2)
9230 return false;
9231
9232 diff = abs(clock1 - clock2);
9233
9234 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9235 return true;
9236
9237 return false;
9238}
9239
Daniel Vetter25c5b262012-07-08 22:08:04 +02009240#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9241 list_for_each_entry((intel_crtc), \
9242 &(dev)->mode_config.crtc_list, \
9243 base.head) \
Daniel Vetter0973f182013-04-19 11:25:33 +02009244 if (mask & (1 <<(intel_crtc)->pipe))
Daniel Vetter25c5b262012-07-08 22:08:04 +02009245
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009246static bool
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009247intel_pipe_config_compare(struct drm_device *dev,
9248 struct intel_crtc_config *current_config,
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009249 struct intel_crtc_config *pipe_config)
9250{
Daniel Vetter66e985c2013-06-05 13:34:20 +02009251#define PIPE_CONF_CHECK_X(name) \
9252 if (current_config->name != pipe_config->name) { \
9253 DRM_ERROR("mismatch in " #name " " \
9254 "(expected 0x%08x, found 0x%08x)\n", \
9255 current_config->name, \
9256 pipe_config->name); \
9257 return false; \
9258 }
9259
Daniel Vetter08a24032013-04-19 11:25:34 +02009260#define PIPE_CONF_CHECK_I(name) \
9261 if (current_config->name != pipe_config->name) { \
9262 DRM_ERROR("mismatch in " #name " " \
9263 "(expected %i, found %i)\n", \
9264 current_config->name, \
9265 pipe_config->name); \
9266 return false; \
Daniel Vetter88adfff2013-03-28 10:42:01 +01009267 }
9268
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009269#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9270 if ((current_config->name ^ pipe_config->name) & (mask)) { \
Jesse Barnes6f024882013-07-01 10:19:09 -07009271 DRM_ERROR("mismatch in " #name "(" #mask ") " \
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009272 "(expected %i, found %i)\n", \
9273 current_config->name & (mask), \
9274 pipe_config->name & (mask)); \
9275 return false; \
9276 }
9277
Ville Syrjälä5e550652013-09-06 23:29:07 +03009278#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9279 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9280 DRM_ERROR("mismatch in " #name " " \
9281 "(expected %i, found %i)\n", \
9282 current_config->name, \
9283 pipe_config->name); \
9284 return false; \
9285 }
9286
Daniel Vetterbb760062013-06-06 14:55:52 +02009287#define PIPE_CONF_QUIRK(quirk) \
9288 ((current_config->quirks | pipe_config->quirks) & (quirk))
9289
Daniel Vettereccb1402013-05-22 00:50:22 +02009290 PIPE_CONF_CHECK_I(cpu_transcoder);
9291
Daniel Vetter08a24032013-04-19 11:25:34 +02009292 PIPE_CONF_CHECK_I(has_pch_encoder);
9293 PIPE_CONF_CHECK_I(fdi_lanes);
Daniel Vetter72419202013-04-04 13:28:53 +02009294 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9295 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9296 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9297 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9298 PIPE_CONF_CHECK_I(fdi_m_n.tu);
Daniel Vetter08a24032013-04-19 11:25:34 +02009299
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03009300 PIPE_CONF_CHECK_I(has_dp_encoder);
9301 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9302 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9303 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9304 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9305 PIPE_CONF_CHECK_I(dp_m_n.tu);
9306
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009307 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9308 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9309 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9310 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9311 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9312 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9313
9314 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9315 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9316 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9317 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9318 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9319 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9320
Daniel Vetterc93f54c2013-06-27 19:47:19 +02009321 PIPE_CONF_CHECK_I(pixel_multiplier);
Daniel Vetter6c49f242013-06-06 12:45:25 +02009322
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009323 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9324 DRM_MODE_FLAG_INTERLACE);
9325
Daniel Vetterbb760062013-06-06 14:55:52 +02009326 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9327 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9328 DRM_MODE_FLAG_PHSYNC);
9329 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9330 DRM_MODE_FLAG_NHSYNC);
9331 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9332 DRM_MODE_FLAG_PVSYNC);
9333 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9334 DRM_MODE_FLAG_NVSYNC);
9335 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009336
Ville Syrjälä37327ab2013-09-04 18:25:28 +03009337 PIPE_CONF_CHECK_I(pipe_src_w);
9338 PIPE_CONF_CHECK_I(pipe_src_h);
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009339
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009340 PIPE_CONF_CHECK_I(gmch_pfit.control);
9341 /* pfit ratios are autocomputed by the hw on gen4+ */
9342 if (INTEL_INFO(dev)->gen < 4)
9343 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9344 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
Chris Wilsonfd4daa92013-08-27 17:04:17 +01009345 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9346 if (current_config->pch_pfit.enabled) {
9347 PIPE_CONF_CHECK_I(pch_pfit.pos);
9348 PIPE_CONF_CHECK_I(pch_pfit.size);
9349 }
Daniel Vetter2fa2fe92013-05-07 23:34:16 +02009350
Jesse Barnese59150d2014-01-07 13:30:45 -08009351 /* BDW+ don't expose a synchronous way to read the state */
9352 if (IS_HASWELL(dev))
9353 PIPE_CONF_CHECK_I(ips_enabled);
Paulo Zanoni42db64e2013-05-31 16:33:22 -03009354
Ville Syrjälä282740f2013-09-04 18:30:03 +03009355 PIPE_CONF_CHECK_I(double_wide);
9356
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009357 PIPE_CONF_CHECK_I(shared_dpll);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009358 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
Daniel Vetter8bcc2792013-06-05 13:34:28 +02009359 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009360 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9361 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
Daniel Vetterc0d43d62013-06-07 23:11:08 +02009362
Ville Syrjälä42571ae2013-09-06 23:29:00 +03009363 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9364 PIPE_CONF_CHECK_I(pipe_bpp);
9365
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009366 if (!IS_HASWELL(dev)) {
Damien Lespiau241bfc32013-09-25 16:45:37 +01009367 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
Ville Syrjäläd71b8d42013-09-06 23:29:08 +03009368 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9369 }
Ville Syrjälä5e550652013-09-06 23:29:07 +03009370
Daniel Vetter66e985c2013-06-05 13:34:20 +02009371#undef PIPE_CONF_CHECK_X
Daniel Vetter08a24032013-04-19 11:25:34 +02009372#undef PIPE_CONF_CHECK_I
Daniel Vetter1bd1bd82013-04-29 21:56:12 +02009373#undef PIPE_CONF_CHECK_FLAGS
Ville Syrjälä5e550652013-09-06 23:29:07 +03009374#undef PIPE_CONF_CHECK_CLOCK_FUZZY
Daniel Vetterbb760062013-06-06 14:55:52 +02009375#undef PIPE_CONF_QUIRK
Daniel Vetter627eb5a2013-04-29 19:33:42 +02009376
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009377 return true;
9378}
9379
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009380static void
9381check_connector_state(struct drm_device *dev)
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009382{
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009383 struct intel_connector *connector;
9384
9385 list_for_each_entry(connector, &dev->mode_config.connector_list,
9386 base.head) {
9387 /* This also checks the encoder/connector hw state with the
9388 * ->get_hw_state callbacks. */
9389 intel_connector_check_state(connector);
9390
9391 WARN(&connector->new_encoder->base != connector->base.encoder,
9392 "connector's staged encoder doesn't match current encoder\n");
9393 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009394}
9395
9396static void
9397check_encoder_state(struct drm_device *dev)
9398{
9399 struct intel_encoder *encoder;
9400 struct intel_connector *connector;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009401
9402 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9403 base.head) {
9404 bool enabled = false;
9405 bool active = false;
9406 enum pipe pipe, tracked_pipe;
9407
9408 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9409 encoder->base.base.id,
9410 drm_get_encoder_name(&encoder->base));
9411
9412 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9413 "encoder's stage crtc doesn't match current crtc\n");
9414 WARN(encoder->connectors_active && !encoder->base.crtc,
9415 "encoder's active_connectors set, but no crtc\n");
9416
9417 list_for_each_entry(connector, &dev->mode_config.connector_list,
9418 base.head) {
9419 if (connector->base.encoder != &encoder->base)
9420 continue;
9421 enabled = true;
9422 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9423 active = true;
9424 }
9425 WARN(!!encoder->base.crtc != enabled,
9426 "encoder's enabled state mismatch "
9427 "(expected %i, found %i)\n",
9428 !!encoder->base.crtc, enabled);
9429 WARN(active && !encoder->base.crtc,
9430 "active encoder with no crtc\n");
9431
9432 WARN(encoder->connectors_active != active,
9433 "encoder's computed active state doesn't match tracked active state "
9434 "(expected %i, found %i)\n", active, encoder->connectors_active);
9435
9436 active = encoder->get_hw_state(encoder, &pipe);
9437 WARN(active != encoder->connectors_active,
9438 "encoder's hw state doesn't match sw tracking "
9439 "(expected %i, found %i)\n",
9440 encoder->connectors_active, active);
9441
9442 if (!encoder->base.crtc)
9443 continue;
9444
9445 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9446 WARN(active && pipe != tracked_pipe,
9447 "active encoder's pipe doesn't match"
9448 "(expected %i, found %i)\n",
9449 tracked_pipe, pipe);
9450
9451 }
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009452}
9453
9454static void
9455check_crtc_state(struct drm_device *dev)
9456{
9457 drm_i915_private_t *dev_priv = dev->dev_private;
9458 struct intel_crtc *crtc;
9459 struct intel_encoder *encoder;
9460 struct intel_crtc_config pipe_config;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009461
9462 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9463 base.head) {
9464 bool enabled = false;
9465 bool active = false;
9466
Jesse Barnes045ac3b2013-05-14 17:08:26 -07009467 memset(&pipe_config, 0, sizeof(pipe_config));
9468
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009469 DRM_DEBUG_KMS("[CRTC:%d]\n",
9470 crtc->base.base.id);
9471
9472 WARN(crtc->active && !crtc->base.enabled,
9473 "active crtc, but not enabled in sw tracking\n");
9474
9475 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9476 base.head) {
9477 if (encoder->base.crtc != &crtc->base)
9478 continue;
9479 enabled = true;
9480 if (encoder->connectors_active)
9481 active = true;
9482 }
Daniel Vetter6c49f242013-06-06 12:45:25 +02009483
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009484 WARN(active != crtc->active,
9485 "crtc's computed active state doesn't match tracked active state "
9486 "(expected %i, found %i)\n", active, crtc->active);
9487 WARN(enabled != crtc->base.enabled,
9488 "crtc's computed enabled state doesn't match tracked enabled state "
9489 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9490
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009491 active = dev_priv->display.get_pipe_config(crtc,
9492 &pipe_config);
Daniel Vetterd62cf622013-05-29 10:41:29 +02009493
9494 /* hw state is inconsistent with the pipe A quirk */
9495 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9496 active = crtc->active;
9497
Daniel Vetter6c49f242013-06-06 12:45:25 +02009498 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9499 base.head) {
Ville Syrjälä3eaba512013-08-05 17:57:48 +03009500 enum pipe pipe;
Daniel Vetter6c49f242013-06-06 12:45:25 +02009501 if (encoder->base.crtc != &crtc->base)
9502 continue;
Daniel Vetter1d37b682013-11-18 09:00:59 +01009503 if (encoder->get_hw_state(encoder, &pipe))
Daniel Vetter6c49f242013-06-06 12:45:25 +02009504 encoder->get_config(encoder, &pipe_config);
9505 }
9506
Daniel Vetter0e8ffe12013-03-28 10:42:00 +01009507 WARN(crtc->active != active,
9508 "crtc active state doesn't match with hw state "
9509 "(expected %i, found %i)\n", crtc->active, active);
9510
Daniel Vetterc0b03412013-05-28 12:05:54 +02009511 if (active &&
9512 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9513 WARN(1, "pipe state doesn't match!\n");
9514 intel_dump_pipe_config(crtc, &pipe_config,
9515 "[hw state]");
9516 intel_dump_pipe_config(crtc, &crtc->config,
9517 "[sw state]");
9518 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009519 }
9520}
9521
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009522static void
9523check_shared_dpll_state(struct drm_device *dev)
9524{
9525 drm_i915_private_t *dev_priv = dev->dev_private;
9526 struct intel_crtc *crtc;
9527 struct intel_dpll_hw_state dpll_hw_state;
9528 int i;
Daniel Vetter53589012013-06-05 13:34:16 +02009529
9530 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9531 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9532 int enabled_crtcs = 0, active_crtcs = 0;
9533 bool active;
9534
9535 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9536
9537 DRM_DEBUG_KMS("%s\n", pll->name);
9538
9539 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9540
9541 WARN(pll->active > pll->refcount,
9542 "more active pll users than references: %i vs %i\n",
9543 pll->active, pll->refcount);
9544 WARN(pll->active && !pll->on,
9545 "pll in active use but not on in sw tracking\n");
Daniel Vetter35c95372013-07-17 06:55:04 +02009546 WARN(pll->on && !pll->active,
9547 "pll in on but not on in use in sw tracking\n");
Daniel Vetter53589012013-06-05 13:34:16 +02009548 WARN(pll->on != active,
9549 "pll on state mismatch (expected %i, found %i)\n",
9550 pll->on, active);
9551
9552 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9553 base.head) {
9554 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9555 enabled_crtcs++;
9556 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9557 active_crtcs++;
9558 }
9559 WARN(pll->active != active_crtcs,
9560 "pll active crtcs mismatch (expected %i, found %i)\n",
9561 pll->active, active_crtcs);
9562 WARN(pll->refcount != enabled_crtcs,
9563 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9564 pll->refcount, enabled_crtcs);
Daniel Vetter66e985c2013-06-05 13:34:20 +02009565
9566 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9567 sizeof(dpll_hw_state)),
9568 "pll hw state mismatch\n");
Daniel Vetter53589012013-06-05 13:34:16 +02009569 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009570}
9571
Daniel Vetter91d1b4b2013-06-05 13:34:18 +02009572void
9573intel_modeset_check_state(struct drm_device *dev)
9574{
9575 check_connector_state(dev);
9576 check_encoder_state(dev);
9577 check_crtc_state(dev);
9578 check_shared_dpll_state(dev);
9579}
9580
Ville Syrjälä18442d02013-09-13 16:00:08 +03009581void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9582 int dotclock)
9583{
9584 /*
9585 * FDI already provided one idea for the dotclock.
9586 * Yell if the encoder disagrees.
9587 */
Damien Lespiau241bfc32013-09-25 16:45:37 +01009588 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
Ville Syrjälä18442d02013-09-13 16:00:08 +03009589 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +01009590 pipe_config->adjusted_mode.crtc_clock, dotclock);
Ville Syrjälä18442d02013-09-13 16:00:08 +03009591}
9592
Daniel Vetterf30da182013-04-11 20:22:50 +02009593static int __intel_set_mode(struct drm_crtc *crtc,
9594 struct drm_display_mode *mode,
9595 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02009596{
9597 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02009598 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009599 struct drm_display_mode *saved_mode, *saved_hwmode;
9600 struct intel_crtc_config *pipe_config = NULL;
Daniel Vetter25c5b262012-07-08 22:08:04 +02009601 struct intel_crtc *intel_crtc;
9602 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009603 int ret = 0;
Daniel Vettera6778b32012-07-02 09:56:42 +02009604
Daniel Vettera1e22652013-09-21 00:35:38 +02009605 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009606 if (!saved_mode)
9607 return -ENOMEM;
Tim Gardner3ac18232012-12-07 07:54:26 -07009608 saved_hwmode = saved_mode + 1;
Daniel Vettera6778b32012-07-02 09:56:42 +02009609
Daniel Vettere2e1ed42012-07-08 21:14:38 +02009610 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02009611 &prepare_pipes, &disable_pipes);
9612
Tim Gardner3ac18232012-12-07 07:54:26 -07009613 *saved_hwmode = crtc->hwmode;
9614 *saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009615
Daniel Vetter25c5b262012-07-08 22:08:04 +02009616 /* Hack: Because we don't (yet) support global modeset on multiple
9617 * crtcs, we don't keep track of the new mode for more than one crtc.
9618 * Hence simply check whether any bit is set in modeset_pipes in all the
9619 * pieces of code that are not yet converted to deal with mutliple crtcs
9620 * changing their mode at the same time. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009621 if (modeset_pipes) {
Daniel Vetter4e53c2e2013-03-27 00:44:58 +01009622 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009623 if (IS_ERR(pipe_config)) {
9624 ret = PTR_ERR(pipe_config);
9625 pipe_config = NULL;
9626
Tim Gardner3ac18232012-12-07 07:54:26 -07009627 goto out;
Daniel Vetter25c5b262012-07-08 22:08:04 +02009628 }
Daniel Vetterc0b03412013-05-28 12:05:54 +02009629 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9630 "[modeset]");
Daniel Vettera6778b32012-07-02 09:56:42 +02009631 }
9632
Jesse Barnes30a970c2013-11-04 13:48:12 -08009633 /*
9634 * See if the config requires any additional preparation, e.g.
9635 * to adjust global state with pipes off. We need to do this
9636 * here so we can get the modeset_pipe updated config for the new
9637 * mode set on this crtc. For other crtcs we need to use the
9638 * adjusted_mode bits in the crtc directly.
9639 */
Ville Syrjäläc164f832013-11-05 22:34:12 +02009640 if (IS_VALLEYVIEW(dev)) {
Jesse Barnes30a970c2013-11-04 13:48:12 -08009641 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9642 modeset_pipes, pipe_config);
9643
Ville Syrjäläc164f832013-11-05 22:34:12 +02009644 /* may have added more to prepare_pipes than we should */
9645 prepare_pipes &= ~disable_pipes;
9646 }
9647
Daniel Vetter460da9162013-03-27 00:44:51 +01009648 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9649 intel_crtc_disable(&intel_crtc->base);
9650
Daniel Vetterea9d7582012-07-10 10:42:52 +02009651 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9652 if (intel_crtc->base.enabled)
9653 dev_priv->display.crtc_disable(&intel_crtc->base);
9654 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009655
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02009656 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9657 * to set it here already despite that we pass it down the callchain.
9658 */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009659 if (modeset_pipes) {
Daniel Vetter25c5b262012-07-08 22:08:04 +02009660 crtc->mode = *mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009661 /* mode_set/enable/disable functions rely on a correct pipe
9662 * config. */
9663 to_intel_crtc(crtc)->config = *pipe_config;
9664 }
Daniel Vetter7758a112012-07-08 19:40:39 +02009665
Daniel Vetterea9d7582012-07-10 10:42:52 +02009666 /* Only after disabling all output pipelines that will be changed can we
9667 * update the the output configuration. */
9668 intel_modeset_update_state(dev, prepare_pipes);
9669
Daniel Vetter47fab732012-10-26 10:58:18 +02009670 if (dev_priv->display.modeset_global_resources)
9671 dev_priv->display.modeset_global_resources(dev);
9672
Daniel Vettera6778b32012-07-02 09:56:42 +02009673 /* Set up the DPLL and any encoders state that needs to adjust or depend
9674 * on the DPLL.
9675 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009676 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009677 ret = intel_crtc_mode_set(&intel_crtc->base,
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009678 x, y, fb);
9679 if (ret)
9680 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02009681 }
9682
9683 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02009684 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9685 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02009686
Daniel Vetter25c5b262012-07-08 22:08:04 +02009687 if (modeset_pipes) {
9688 /* Store real post-adjustment hardware mode. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009689 crtc->hwmode = pipe_config->adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009690
Daniel Vetter25c5b262012-07-08 22:08:04 +02009691 /* Calculate and store various constants which
9692 * are later needed by vblank and swap-completion
9693 * timestamping. They are derived from true hwmode.
9694 */
9695 drm_calc_timestamping_constants(crtc);
9696 }
Daniel Vettera6778b32012-07-02 09:56:42 +02009697
9698 /* FIXME: add subpixel order */
9699done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009700 if (ret && crtc->enabled) {
Tim Gardner3ac18232012-12-07 07:54:26 -07009701 crtc->hwmode = *saved_hwmode;
9702 crtc->mode = *saved_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02009703 }
9704
Tim Gardner3ac18232012-12-07 07:54:26 -07009705out:
Daniel Vetterb8cecdf2013-03-27 00:44:50 +01009706 kfree(pipe_config);
Tim Gardner3ac18232012-12-07 07:54:26 -07009707 kfree(saved_mode);
Daniel Vettera6778b32012-07-02 09:56:42 +02009708 return ret;
9709}
9710
Damien Lespiaue7457a92013-08-08 22:28:59 +01009711static int intel_set_mode(struct drm_crtc *crtc,
9712 struct drm_display_mode *mode,
9713 int x, int y, struct drm_framebuffer *fb)
Daniel Vetterf30da182013-04-11 20:22:50 +02009714{
9715 int ret;
9716
9717 ret = __intel_set_mode(crtc, mode, x, y, fb);
9718
9719 if (ret == 0)
9720 intel_modeset_check_state(crtc->dev);
9721
9722 return ret;
9723}
9724
Chris Wilsonc0c36b942012-12-19 16:08:43 +00009725void intel_crtc_restore_mode(struct drm_crtc *crtc)
9726{
9727 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9728}
9729
Daniel Vetter25c5b262012-07-08 22:08:04 +02009730#undef for_each_intel_crtc_masked
9731
Daniel Vetterd9e55602012-07-04 22:16:09 +02009732static void intel_set_config_free(struct intel_set_config *config)
9733{
9734 if (!config)
9735 return;
9736
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009737 kfree(config->save_connector_encoders);
9738 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02009739 kfree(config);
9740}
9741
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009742static int intel_set_config_save_state(struct drm_device *dev,
9743 struct intel_set_config *config)
9744{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009745 struct drm_encoder *encoder;
9746 struct drm_connector *connector;
9747 int count;
9748
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009749 config->save_encoder_crtcs =
9750 kcalloc(dev->mode_config.num_encoder,
9751 sizeof(struct drm_crtc *), GFP_KERNEL);
9752 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009753 return -ENOMEM;
9754
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009755 config->save_connector_encoders =
9756 kcalloc(dev->mode_config.num_connector,
9757 sizeof(struct drm_encoder *), GFP_KERNEL);
9758 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009759 return -ENOMEM;
9760
9761 /* Copy data. Note that driver private data is not affected.
9762 * Should anything bad happen only the expected state is
9763 * restored, not the drivers personal bookkeeping.
9764 */
9765 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009766 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009767 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009768 }
9769
9770 count = 0;
9771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02009772 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009773 }
9774
9775 return 0;
9776}
9777
9778static void intel_set_config_restore_state(struct drm_device *dev,
9779 struct intel_set_config *config)
9780{
Daniel Vetter9a935852012-07-05 22:34:27 +02009781 struct intel_encoder *encoder;
9782 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009783 int count;
9784
9785 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02009786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9787 encoder->new_crtc =
9788 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009789 }
9790
9791 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02009792 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9793 connector->new_encoder =
9794 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009795 }
9796}
9797
Imre Deake3de42b2013-05-03 19:44:07 +02009798static bool
Chris Wilson2e57f472013-07-17 12:14:40 +01009799is_crtc_connector_off(struct drm_mode_set *set)
Imre Deake3de42b2013-05-03 19:44:07 +02009800{
9801 int i;
9802
Chris Wilson2e57f472013-07-17 12:14:40 +01009803 if (set->num_connectors == 0)
9804 return false;
9805
9806 if (WARN_ON(set->connectors == NULL))
9807 return false;
9808
9809 for (i = 0; i < set->num_connectors; i++)
9810 if (set->connectors[i]->encoder &&
9811 set->connectors[i]->encoder->crtc == set->crtc &&
9812 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
Imre Deake3de42b2013-05-03 19:44:07 +02009813 return true;
9814
9815 return false;
9816}
9817
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009818static void
9819intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9820 struct intel_set_config *config)
9821{
9822
9823 /* We should be able to check here if the fb has the same properties
9824 * and then just flip_or_move it */
Chris Wilson2e57f472013-07-17 12:14:40 +01009825 if (is_crtc_connector_off(set)) {
9826 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009827 } else if (set->crtc->fb != set->fb) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009828 /* If we have no fb then treat it as a full mode set */
9829 if (set->crtc->fb == NULL) {
Jesse Barnes319d9822013-06-26 01:38:19 +03009830 struct intel_crtc *intel_crtc =
9831 to_intel_crtc(set->crtc);
9832
9833 if (intel_crtc->active && i915_fastboot) {
9834 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9835 config->fb_changed = true;
9836 } else {
9837 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9838 config->mode_changed = true;
9839 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009840 } else if (set->fb == NULL) {
9841 config->mode_changed = true;
Daniel Vetter72f49012013-03-28 16:01:35 +01009842 } else if (set->fb->pixel_format !=
9843 set->crtc->fb->pixel_format) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009844 config->mode_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009845 } else {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009846 config->fb_changed = true;
Imre Deake3de42b2013-05-03 19:44:07 +02009847 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009848 }
9849
Daniel Vetter835c5872012-07-10 18:11:08 +02009850 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009851 config->fb_changed = true;
9852
9853 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9854 DRM_DEBUG_KMS("modes are different, full mode set\n");
9855 drm_mode_debug_printmodeline(&set->crtc->mode);
9856 drm_mode_debug_printmodeline(set->mode);
9857 config->mode_changed = true;
9858 }
Chris Wilsona1d95702013-08-13 18:48:47 +01009859
9860 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9861 set->crtc->base.id, config->mode_changed, config->fb_changed);
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009862}
9863
Daniel Vetter2e431052012-07-04 22:42:15 +02009864static int
Daniel Vetter9a935852012-07-05 22:34:27 +02009865intel_modeset_stage_output_state(struct drm_device *dev,
9866 struct drm_mode_set *set,
9867 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02009868{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02009869 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02009870 struct intel_connector *connector;
9871 struct intel_encoder *encoder;
Paulo Zanonif3f08572013-08-12 14:56:53 -03009872 int ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02009873
Damien Lespiau9abdda72013-02-13 13:29:23 +00009874 /* The upper layers ensure that we either disable a crtc or have a list
Daniel Vetter9a935852012-07-05 22:34:27 +02009875 * of connectors. For paranoia, double-check this. */
9876 WARN_ON(!set->fb && (set->num_connectors != 0));
9877 WARN_ON(set->fb && (set->num_connectors == 0));
9878
Daniel Vetter9a935852012-07-05 22:34:27 +02009879 list_for_each_entry(connector, &dev->mode_config.connector_list,
9880 base.head) {
9881 /* Otherwise traverse passed in connector list and get encoders
9882 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02009883 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009884 if (set->connectors[ro] == &connector->base) {
9885 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02009886 break;
9887 }
9888 }
9889
Daniel Vetter9a935852012-07-05 22:34:27 +02009890 /* If we disable the crtc, disable all its connectors. Also, if
9891 * the connector is on the changing crtc but not on the new
9892 * connector list, disable it. */
9893 if ((!set->fb || ro == set->num_connectors) &&
9894 connector->base.encoder &&
9895 connector->base.encoder->crtc == set->crtc) {
9896 connector->new_encoder = NULL;
9897
9898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9899 connector->base.base.id,
9900 drm_get_connector_name(&connector->base));
9901 }
9902
9903
9904 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02009905 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009906 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02009907 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009908 }
9909 /* connector->new_encoder is now updated for all connectors. */
9910
9911 /* Update crtc of enabled connectors. */
Daniel Vetter9a935852012-07-05 22:34:27 +02009912 list_for_each_entry(connector, &dev->mode_config.connector_list,
9913 base.head) {
9914 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02009915 continue;
9916
Daniel Vetter9a935852012-07-05 22:34:27 +02009917 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02009918
9919 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02009920 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02009921 new_crtc = set->crtc;
9922 }
9923
9924 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02009925 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9926 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009927 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02009928 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009929 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9930
9931 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9932 connector->base.base.id,
9933 drm_get_connector_name(&connector->base),
9934 new_crtc->base.id);
9935 }
9936
9937 /* Check for any encoders that needs to be disabled. */
9938 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9939 base.head) {
Paulo Zanoni5a65f352014-01-07 14:55:53 -02009940 int num_connectors = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02009941 list_for_each_entry(connector,
9942 &dev->mode_config.connector_list,
9943 base.head) {
9944 if (connector->new_encoder == encoder) {
9945 WARN_ON(!connector->new_encoder->new_crtc);
Paulo Zanoni5a65f352014-01-07 14:55:53 -02009946 num_connectors++;
Daniel Vetter9a935852012-07-05 22:34:27 +02009947 }
9948 }
Paulo Zanoni5a65f352014-01-07 14:55:53 -02009949
9950 if (num_connectors == 0)
9951 encoder->new_crtc = NULL;
9952 else if (num_connectors > 1)
9953 return -EINVAL;
9954
Daniel Vetter9a935852012-07-05 22:34:27 +02009955 /* Only now check for crtc changes so we don't miss encoders
9956 * that will be disabled. */
9957 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02009958 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02009959 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02009960 }
9961 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009962 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02009963
Daniel Vetter2e431052012-07-04 22:42:15 +02009964 return 0;
9965}
9966
9967static int intel_crtc_set_config(struct drm_mode_set *set)
9968{
9969 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02009970 struct drm_mode_set save_set;
9971 struct intel_set_config *config;
9972 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02009973
Daniel Vetter8d3e3752012-07-05 16:09:09 +02009974 BUG_ON(!set);
9975 BUG_ON(!set->crtc);
9976 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02009977
Daniel Vetter7e53f3a2013-01-21 10:52:17 +01009978 /* Enforce sane interface api - has been abused by the fb helper. */
9979 BUG_ON(!set->mode && set->fb);
9980 BUG_ON(set->fb && set->num_connectors == 0);
Daniel Vetter431e50f2012-07-10 17:53:42 +02009981
Daniel Vetter2e431052012-07-04 22:42:15 +02009982 if (set->fb) {
9983 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9984 set->crtc->base.id, set->fb->base.id,
9985 (int)set->num_connectors, set->x, set->y);
9986 } else {
9987 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02009988 }
9989
9990 dev = set->crtc->dev;
9991
9992 ret = -ENOMEM;
9993 config = kzalloc(sizeof(*config), GFP_KERNEL);
9994 if (!config)
9995 goto out_config;
9996
9997 ret = intel_set_config_save_state(dev, config);
9998 if (ret)
9999 goto out_config;
10000
10001 save_set.crtc = set->crtc;
10002 save_set.mode = &set->crtc->mode;
10003 save_set.x = set->crtc->x;
10004 save_set.y = set->crtc->y;
10005 save_set.fb = set->crtc->fb;
10006
10007 /* Compute whether we need a full modeset, only an fb base update or no
10008 * change at all. In the future we might also check whether only the
10009 * mode changed, e.g. for LVDS where we only change the panel fitter in
10010 * such cases. */
10011 intel_set_config_compute_mode_changes(set, config);
10012
Daniel Vetter9a935852012-07-05 22:34:27 +020010013 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +020010014 if (ret)
10015 goto fail;
10016
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010017 if (config->mode_changed) {
Chris Wilsonc0c36b942012-12-19 16:08:43 +000010018 ret = intel_set_mode(set->crtc, set->mode,
10019 set->x, set->y, set->fb);
Daniel Vetter5e2b5842012-07-04 22:41:29 +020010020 } else if (config->fb_changed) {
Ville Syrjälä4878cae2013-02-18 19:08:48 +020010021 intel_crtc_wait_for_pending_flips(set->crtc);
10022
Daniel Vetter4f660f42012-07-02 09:47:37 +020010023 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +020010024 set->x, set->y, set->fb);
Jesse Barnes7ca51a32014-01-07 13:50:49 -080010025 /*
10026 * In the fastboot case this may be our only check of the
10027 * state after boot. It would be better to only do it on
10028 * the first update, but we don't have a nice way of doing that
10029 * (and really, set_config isn't used much for high freq page
10030 * flipping, so increasing its cost here shouldn't be a big
10031 * deal).
10032 */
10033 if (i915_fastboot && ret == 0)
10034 intel_modeset_check_state(set->crtc->dev);
Daniel Vetter50f56112012-07-02 09:35:43 +020010035 }
10036
Chris Wilson2d05eae2013-05-03 17:36:25 +010010037 if (ret) {
Daniel Vetterbf67dfe2013-06-25 11:06:52 +020010038 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10039 set->crtc->base.id, ret);
Daniel Vetter50f56112012-07-02 09:35:43 +020010040fail:
Chris Wilson2d05eae2013-05-03 17:36:25 +010010041 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010042
Chris Wilson2d05eae2013-05-03 17:36:25 +010010043 /* Try to restore the config */
10044 if (config->mode_changed &&
10045 intel_set_mode(save_set.crtc, save_set.mode,
10046 save_set.x, save_set.y, save_set.fb))
10047 DRM_ERROR("failed to restore config after modeset failure\n");
10048 }
Daniel Vetter50f56112012-07-02 09:35:43 +020010049
Daniel Vetterd9e55602012-07-04 22:16:09 +020010050out_config:
10051 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +020010052 return ret;
10053}
10054
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010055static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010056 .cursor_set = intel_crtc_cursor_set,
10057 .cursor_move = intel_crtc_cursor_move,
10058 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +020010059 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +010010060 .destroy = intel_crtc_destroy,
10061 .page_flip = intel_crtc_page_flip,
10062};
10063
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010064static void intel_cpu_pll_init(struct drm_device *dev)
10065{
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010066 if (HAS_DDI(dev))
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010067 intel_ddi_pll_init(dev);
10068}
10069
Daniel Vetter53589012013-06-05 13:34:16 +020010070static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10071 struct intel_shared_dpll *pll,
10072 struct intel_dpll_hw_state *hw_state)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010073{
Daniel Vetter53589012013-06-05 13:34:16 +020010074 uint32_t val;
10075
10076 val = I915_READ(PCH_DPLL(pll->id));
Daniel Vetter66e985c2013-06-05 13:34:20 +020010077 hw_state->dpll = val;
10078 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10079 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
Daniel Vetter53589012013-06-05 13:34:16 +020010080
10081 return val & DPLL_VCO_ENABLE;
10082}
10083
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010084static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10085 struct intel_shared_dpll *pll)
10086{
10087 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10088 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10089}
10090
Daniel Vettere7b903d2013-06-05 13:34:14 +020010091static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10092 struct intel_shared_dpll *pll)
10093{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010094 /* PCH refclock must be enabled first */
Paulo Zanoni89eff4b2014-01-08 11:12:28 -020010095 ibx_assert_pch_refclk_enabled(dev_priv);
Daniel Vettere7b903d2013-06-05 13:34:14 +020010096
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010097 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10098
10099 /* Wait for the clocks to stabilize. */
10100 POSTING_READ(PCH_DPLL(pll->id));
10101 udelay(150);
10102
10103 /* The pixel multiplier can only be updated once the
10104 * DPLL is enabled and the clocks are stable.
10105 *
10106 * So write it again.
10107 */
10108 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10109 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010110 udelay(200);
10111}
10112
10113static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10114 struct intel_shared_dpll *pll)
10115{
10116 struct drm_device *dev = dev_priv->dev;
10117 struct intel_crtc *crtc;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010118
10119 /* Make sure no transcoder isn't still depending on us. */
10120 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10121 if (intel_crtc_to_shared_dpll(crtc) == pll)
10122 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10123 }
10124
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010125 I915_WRITE(PCH_DPLL(pll->id), 0);
10126 POSTING_READ(PCH_DPLL(pll->id));
Daniel Vettere7b903d2013-06-05 13:34:14 +020010127 udelay(200);
10128}
10129
Daniel Vetter46edb022013-06-05 13:34:12 +020010130static char *ibx_pch_dpll_names[] = {
10131 "PCH DPLL A",
10132 "PCH DPLL B",
10133};
10134
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010135static void ibx_pch_dpll_init(struct drm_device *dev)
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010136{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010137 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010138 int i;
10139
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010140 dev_priv->num_shared_dpll = 2;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010141
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
Daniel Vetter46edb022013-06-05 13:34:12 +020010143 dev_priv->shared_dplls[i].id = i;
10144 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
Daniel Vetter15bdd4c2013-06-05 13:34:23 +020010145 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
Daniel Vettere7b903d2013-06-05 13:34:14 +020010146 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10147 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
Daniel Vetter53589012013-06-05 13:34:16 +020010148 dev_priv->shared_dplls[i].get_hw_state =
10149 ibx_pch_dpll_get_hw_state;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010150 }
10151}
10152
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010153static void intel_shared_dpll_init(struct drm_device *dev)
10154{
Daniel Vettere7b903d2013-06-05 13:34:14 +020010155 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010156
10157 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10158 ibx_pch_dpll_init(dev);
10159 else
10160 dev_priv->num_shared_dpll = 0;
10161
10162 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
Daniel Vetter7c74ade2013-06-05 13:34:11 +020010163}
10164
Hannes Ederb358d0a2008-12-18 21:18:47 +010010165static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -080010166{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010167 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -080010168 struct intel_crtc *intel_crtc;
10169 int i;
10170
Daniel Vetter955382f2013-09-19 14:05:45 +020010171 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
Jesse Barnes79e53942008-11-07 14:24:08 -080010172 if (intel_crtc == NULL)
10173 return;
10174
10175 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10176
10177 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -080010178 for (i = 0; i < 256; i++) {
10179 intel_crtc->lut_r[i] = i;
10180 intel_crtc->lut_g[i] = i;
10181 intel_crtc->lut_b[i] = i;
10182 }
10183
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +020010184 /*
10185 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10186 * is hooked to plane B. Hence we want plane A feeding pipe B.
10187 */
Jesse Barnes80824002009-09-10 15:28:06 -070010188 intel_crtc->pipe = pipe;
10189 intel_crtc->plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +010010190 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
Zhao Yakui28c97732009-10-09 11:39:41 +080010191 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +010010192 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -070010193 }
10194
Jesse Barnes22fd0fa2009-12-02 13:42:53 -080010195 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10196 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10197 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10198 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10199
Jesse Barnes79e53942008-11-07 14:24:08 -080010200 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -080010201}
10202
Jesse Barnes752aa882013-10-31 18:55:49 +020010203enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10204{
10205 struct drm_encoder *encoder = connector->base.encoder;
10206
10207 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10208
10209 if (!encoder)
10210 return INVALID_PIPE;
10211
10212 return to_intel_crtc(encoder->crtc)->pipe;
10213}
10214
Carl Worth08d7b3d2009-04-29 14:43:54 -070010215int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +000010216 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -070010217{
Carl Worth08d7b3d2009-04-29 14:43:54 -070010218 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +020010219 struct drm_mode_object *drmmode_obj;
10220 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010221
Daniel Vetter1cff8f62012-04-24 09:55:08 +020010222 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10223 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010224
Daniel Vetterc05422d2009-08-11 16:05:30 +020010225 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10226 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -070010227
Daniel Vetterc05422d2009-08-11 16:05:30 +020010228 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -070010229 DRM_ERROR("no such CRTC id\n");
Ville Syrjälä3f2c2052013-10-17 13:35:03 +030010230 return -ENOENT;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010231 }
10232
Daniel Vetterc05422d2009-08-11 16:05:30 +020010233 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10234 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010235
Daniel Vetterc05422d2009-08-11 16:05:30 +020010236 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -070010237}
10238
Daniel Vetter66a92782012-07-12 20:08:18 +020010239static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080010240{
Daniel Vetter66a92782012-07-12 20:08:18 +020010241 struct drm_device *dev = encoder->base.dev;
10242 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -080010243 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -080010244 int entry = 0;
10245
Daniel Vetter66a92782012-07-12 20:08:18 +020010246 list_for_each_entry(source_encoder,
10247 &dev->mode_config.encoder_list, base.head) {
10248
10249 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -080010250 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +020010251
10252 /* Intel hw has only one MUX where enocoders could be cloned. */
10253 if (encoder->cloneable && source_encoder->cloneable)
10254 index_mask |= (1 << entry);
10255
Jesse Barnes79e53942008-11-07 14:24:08 -080010256 entry++;
10257 }
Chris Wilson4ef69c72010-09-09 15:14:28 +010010258
Jesse Barnes79e53942008-11-07 14:24:08 -080010259 return index_mask;
10260}
10261
Chris Wilson4d302442010-12-14 19:21:29 +000010262static bool has_edp_a(struct drm_device *dev)
10263{
10264 struct drm_i915_private *dev_priv = dev->dev_private;
10265
10266 if (!IS_MOBILE(dev))
10267 return false;
10268
10269 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10270 return false;
10271
10272 if (IS_GEN5(dev) &&
10273 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10274 return false;
10275
10276 return true;
10277}
10278
Damien Lespiauba0fbca2014-01-08 14:18:23 +000010279const char *intel_output_name(int output)
10280{
10281 static const char *names[] = {
10282 [INTEL_OUTPUT_UNUSED] = "Unused",
10283 [INTEL_OUTPUT_ANALOG] = "Analog",
10284 [INTEL_OUTPUT_DVO] = "DVO",
10285 [INTEL_OUTPUT_SDVO] = "SDVO",
10286 [INTEL_OUTPUT_LVDS] = "LVDS",
10287 [INTEL_OUTPUT_TVOUT] = "TV",
10288 [INTEL_OUTPUT_HDMI] = "HDMI",
10289 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10290 [INTEL_OUTPUT_EDP] = "eDP",
10291 [INTEL_OUTPUT_DSI] = "DSI",
10292 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10293 };
10294
10295 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10296 return "Invalid";
10297
10298 return names[output];
10299}
10300
Jesse Barnes79e53942008-11-07 14:24:08 -080010301static void intel_setup_outputs(struct drm_device *dev)
10302{
Eric Anholt725e30a2009-01-22 13:01:02 -080010303 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +010010304 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010305 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -080010306
Daniel Vetterc9093352013-06-06 22:22:47 +020010307 intel_lvds_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010308
Paulo Zanonic40c0f52013-04-12 18:16:53 -030010309 if (!IS_ULT(dev))
Paulo Zanoni79935fc2012-11-20 13:27:40 -020010310 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010311
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010312 if (HAS_DDI(dev)) {
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -030010313 int found;
10314
10315 /* Haswell uses DDI functions to detect digital outputs */
10316 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10317 /* DDI A only supports eDP */
10318 if (found)
10319 intel_ddi_init(dev, PORT_A);
10320
10321 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10322 * register */
10323 found = I915_READ(SFUSE_STRAP);
10324
10325 if (found & SFUSE_STRAP_DDIB_DETECTED)
10326 intel_ddi_init(dev, PORT_B);
10327 if (found & SFUSE_STRAP_DDIC_DETECTED)
10328 intel_ddi_init(dev, PORT_C);
10329 if (found & SFUSE_STRAP_DDID_DETECTED)
10330 intel_ddi_init(dev, PORT_D);
10331 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010332 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +020010333 dpd_is_edp = intel_dpd_is_edp(dev);
10334
10335 if (has_edp_a(dev))
10336 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -040010337
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010338 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +080010339 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +010010340 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010341 if (!found)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010342 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010343 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010344 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010345 }
10346
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010347 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010348 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010349
Paulo Zanonidc0fa712013-02-19 16:21:46 -030010350 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
Paulo Zanonie2debe92013-02-18 19:00:27 -030010351 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +080010352
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010353 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010354 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080010355
Daniel Vetter270b3042012-10-27 15:52:05 +020010356 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010357 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -070010358 } else if (IS_VALLEYVIEW(dev)) {
Artem Bityutskiy585a94b2013-10-16 18:10:41 +030010359 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10360 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10361 PORT_B);
10362 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10363 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10364 }
10365
Jesse Barnes6f6005a2013-08-09 09:34:35 -070010366 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10367 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10368 PORT_C);
10369 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10370 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10371 PORT_C);
10372 }
Gajanan Bhat19c03922012-09-27 19:13:07 +053010373
Jani Nikula3cfca972013-08-27 15:12:26 +030010374 intel_dsi_init(dev);
Zhenyu Wang103a1962009-11-27 11:44:36 +080010375 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +080010376 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -080010377
Paulo Zanonie2debe92013-02-18 19:00:27 -030010378 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010379 DRM_DEBUG_KMS("probing SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010380 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010381 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10382 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010383 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010384 }
Ma Ling27185ae2009-08-24 13:50:23 +080010385
Imre Deake7281ea2013-05-08 13:14:08 +030010386 if (!found && SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010387 intel_dp_init(dev, DP_B, PORT_B);
Eric Anholt725e30a2009-01-22 13:01:02 -080010388 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -040010389
10390 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -040010391
Paulo Zanonie2debe92013-02-18 19:00:27 -030010392 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010393 DRM_DEBUG_KMS("probing SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010394 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010395 }
Ma Ling27185ae2009-08-24 13:50:23 +080010396
Paulo Zanonie2debe92013-02-18 19:00:27 -030010397 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
Ma Ling27185ae2009-08-24 13:50:23 +080010398
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010399 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10400 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Paulo Zanonie2debe92013-02-18 19:00:27 -030010401 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010402 }
Imre Deake7281ea2013-05-08 13:14:08 +030010403 if (SUPPORTS_INTEGRATED_DP(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010404 intel_dp_init(dev, DP_C, PORT_C);
Eric Anholt725e30a2009-01-22 13:01:02 -080010405 }
Ma Ling27185ae2009-08-24 13:50:23 +080010406
Jesse Barnesb01f2c32009-12-11 11:07:17 -080010407 if (SUPPORTS_INTEGRATED_DP(dev) &&
Imre Deake7281ea2013-05-08 13:14:08 +030010408 (I915_READ(DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -030010409 intel_dp_init(dev, DP_D, PORT_D);
Eric Anholtbad720f2009-10-22 16:11:14 -070010410 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080010411 intel_dvo_init(dev);
10412
Zhenyu Wang103a1962009-11-27 11:44:36 +080010413 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -080010414 intel_tv_init(dev);
10415
Chris Wilson4ef69c72010-09-09 15:14:28 +010010416 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10417 encoder->base.possible_crtcs = encoder->crtc_mask;
10418 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +020010419 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -080010420 }
Chris Wilson47356eb2011-01-11 17:06:04 +000010421
Paulo Zanonidde86e22012-12-01 12:04:25 -020010422 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +020010423
10424 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010425}
10426
Chris Wilsonddfe1562013-08-06 17:43:07 +010010427void intel_framebuffer_fini(struct intel_framebuffer *fb)
10428{
10429 drm_framebuffer_cleanup(&fb->base);
Daniel Vetter80075d42013-10-09 21:23:52 +020010430 WARN_ON(!fb->obj->framebuffer_references--);
Chris Wilsonddfe1562013-08-06 17:43:07 +010010431 drm_gem_object_unreference_unlocked(&fb->obj->base);
10432}
10433
Jesse Barnes79e53942008-11-07 14:24:08 -080010434static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10435{
10436 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080010437
Chris Wilsonddfe1562013-08-06 17:43:07 +010010438 intel_framebuffer_fini(intel_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -080010439 kfree(intel_fb);
10440}
10441
10442static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +000010443 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -080010444 unsigned int *handle)
10445{
10446 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +000010447 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080010448
Chris Wilson05394f32010-11-08 19:18:58 +000010449 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -080010450}
10451
10452static const struct drm_framebuffer_funcs intel_fb_funcs = {
10453 .destroy = intel_user_framebuffer_destroy,
10454 .create_handle = intel_user_framebuffer_create_handle,
10455};
10456
Dave Airlie38651672010-03-30 05:34:13 +000010457int intel_framebuffer_init(struct drm_device *dev,
10458 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010459 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +000010460 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -080010461{
Daniel Vetter53155c02013-10-09 21:55:33 +020010462 int aligned_height, tile_height;
Chris Wilsona35cdaa2013-06-25 17:26:45 +010010463 int pitch_limit;
Jesse Barnes79e53942008-11-07 14:24:08 -080010464 int ret;
10465
Daniel Vetterdd4916c2013-10-09 21:23:51 +020010466 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10467
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010468 if (obj->tiling_mode == I915_TILING_Y) {
10469 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +010010470 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010471 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010472
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010473 if (mode_cmd->pitches[0] & 63) {
10474 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10475 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +010010476 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010477 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010478
Chris Wilsona35cdaa2013-06-25 17:26:45 +010010479 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10480 pitch_limit = 32*1024;
10481 } else if (INTEL_INFO(dev)->gen >= 4) {
10482 if (obj->tiling_mode)
10483 pitch_limit = 16*1024;
10484 else
10485 pitch_limit = 32*1024;
10486 } else if (INTEL_INFO(dev)->gen >= 3) {
10487 if (obj->tiling_mode)
10488 pitch_limit = 8*1024;
10489 else
10490 pitch_limit = 16*1024;
10491 } else
10492 /* XXX DSPC is limited to 4k tiled */
10493 pitch_limit = 8*1024;
10494
10495 if (mode_cmd->pitches[0] > pitch_limit) {
10496 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10497 obj->tiling_mode ? "tiled" : "linear",
10498 mode_cmd->pitches[0], pitch_limit);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010499 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010500 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010501
10502 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010503 mode_cmd->pitches[0] != obj->stride) {
10504 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10505 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010506 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010507 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +020010508
Ville Syrjälä57779d02012-10-31 17:50:14 +020010509 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010510 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +020010511 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +020010512 case DRM_FORMAT_RGB565:
10513 case DRM_FORMAT_XRGB8888:
10514 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +020010515 break;
10516 case DRM_FORMAT_XRGB1555:
10517 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010518 if (INTEL_INFO(dev)->gen > 3) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010519 DRM_DEBUG("unsupported pixel format: %s\n",
10520 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010521 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010522 }
Ville Syrjälä57779d02012-10-31 17:50:14 +020010523 break;
10524 case DRM_FORMAT_XBGR8888:
10525 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +020010526 case DRM_FORMAT_XRGB2101010:
10527 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +020010528 case DRM_FORMAT_XBGR2101010:
10529 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010530 if (INTEL_INFO(dev)->gen < 4) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010531 DRM_DEBUG("unsupported pixel format: %s\n",
10532 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010533 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010534 }
Jesse Barnesb5626742011-06-24 12:19:27 -070010535 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +020010536 case DRM_FORMAT_YUYV:
10537 case DRM_FORMAT_UYVY:
10538 case DRM_FORMAT_YVYU:
10539 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010540 if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010541 DRM_DEBUG("unsupported pixel format: %s\n",
10542 drm_get_format_name(mode_cmd->pixel_format));
Ville Syrjälä57779d02012-10-31 17:50:14 +020010543 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +000010544 }
Chris Wilson57cd6502010-08-08 12:34:44 +010010545 break;
10546 default:
Ville Syrjälä4ee62c72013-06-07 15:43:05 +000010547 DRM_DEBUG("unsupported pixel format: %s\n",
10548 drm_get_format_name(mode_cmd->pixel_format));
Chris Wilson57cd6502010-08-08 12:34:44 +010010549 return -EINVAL;
10550 }
10551
Ville Syrjälä90f9a332012-10-31 17:50:19 +020010552 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10553 if (mode_cmd->offsets[0] != 0)
10554 return -EINVAL;
10555
Daniel Vetter53155c02013-10-09 21:55:33 +020010556 tile_height = IS_GEN2(dev) ? 16 : 8;
10557 aligned_height = ALIGN(mode_cmd->height,
10558 obj->tiling_mode ? tile_height : 1);
10559 /* FIXME drm helper for size checks (especially planar formats)? */
10560 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10561 return -EINVAL;
10562
Daniel Vetterc7d73f62012-12-13 23:38:38 +010010563 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10564 intel_fb->obj = obj;
Daniel Vetter80075d42013-10-09 21:23:52 +020010565 intel_fb->obj->framebuffer_references++;
Daniel Vetterc7d73f62012-12-13 23:38:38 +010010566
Jesse Barnes79e53942008-11-07 14:24:08 -080010567 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10568 if (ret) {
10569 DRM_ERROR("framebuffer init failed %d\n", ret);
10570 return ret;
10571 }
10572
Jesse Barnes79e53942008-11-07 14:24:08 -080010573 return 0;
10574}
10575
Jesse Barnes79e53942008-11-07 14:24:08 -080010576static struct drm_framebuffer *
10577intel_user_framebuffer_create(struct drm_device *dev,
10578 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010579 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -080010580{
Chris Wilson05394f32010-11-08 19:18:58 +000010581 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -080010582
Jesse Barnes308e5bc2011-11-14 14:51:28 -080010583 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10584 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +000010585 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +010010586 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -080010587
Chris Wilsond2dff872011-04-19 08:36:26 +010010588 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -080010589}
10590
Daniel Vetter4520f532013-10-09 09:18:51 +020010591#ifndef CONFIG_DRM_I915_FBDEV
Daniel Vetter0632fef2013-10-08 17:44:49 +020010592static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +020010593{
10594}
10595#endif
10596
Jesse Barnes79e53942008-11-07 14:24:08 -080010597static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -080010598 .fb_create = intel_user_framebuffer_create,
Daniel Vetter0632fef2013-10-08 17:44:49 +020010599 .output_poll_changed = intel_fbdev_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -080010600};
10601
Jesse Barnese70236a2009-09-21 10:42:27 -070010602/* Set up chip specific display functions */
10603static void intel_init_display(struct drm_device *dev)
10604{
10605 struct drm_i915_private *dev_priv = dev->dev_private;
10606
Daniel Vetteree9300b2013-06-03 22:40:22 +020010607 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10608 dev_priv->display.find_dpll = g4x_find_best_dpll;
10609 else if (IS_VALLEYVIEW(dev))
10610 dev_priv->display.find_dpll = vlv_find_best_dpll;
10611 else if (IS_PINEVIEW(dev))
10612 dev_priv->display.find_dpll = pnv_find_best_dpll;
10613 else
10614 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10615
Paulo Zanoniaffa9352012-11-23 15:30:39 -020010616 if (HAS_DDI(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010617 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030010618 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -020010619 dev_priv->display.crtc_enable = haswell_crtc_enable;
10620 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -030010621 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -030010622 dev_priv->display.update_plane = ironlake_update_plane;
10623 } else if (HAS_PCH_SPLIT(dev)) {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010624 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070010625 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020010626 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10627 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010628 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -070010629 dev_priv->display.update_plane = ironlake_update_plane;
Jesse Barnes89b667f2013-04-18 14:51:36 -070010630 } else if (IS_VALLEYVIEW(dev)) {
10631 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10632 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10633 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10634 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10635 dev_priv->display.off = i9xx_crtc_off;
10636 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070010637 } else {
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010010638 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
Eric Anholtf564048e2011-03-30 13:01:02 -070010639 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +020010640 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10641 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010642 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -070010643 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -070010644 }
Jesse Barnese70236a2009-09-21 10:42:27 -070010645
Jesse Barnese70236a2009-09-21 10:42:27 -070010646 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -070010647 if (IS_VALLEYVIEW(dev))
10648 dev_priv->display.get_display_clock_speed =
10649 valleyview_get_display_clock_speed;
10650 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -070010651 dev_priv->display.get_display_clock_speed =
10652 i945_get_display_clock_speed;
10653 else if (IS_I915G(dev))
10654 dev_priv->display.get_display_clock_speed =
10655 i915_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020010656 else if (IS_I945GM(dev) || IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070010657 dev_priv->display.get_display_clock_speed =
10658 i9xx_misc_get_display_clock_speed;
Daniel Vetter257a7ff2013-07-26 08:35:42 +020010659 else if (IS_PINEVIEW(dev))
10660 dev_priv->display.get_display_clock_speed =
10661 pnv_get_display_clock_speed;
Jesse Barnese70236a2009-09-21 10:42:27 -070010662 else if (IS_I915GM(dev))
10663 dev_priv->display.get_display_clock_speed =
10664 i915gm_get_display_clock_speed;
10665 else if (IS_I865G(dev))
10666 dev_priv->display.get_display_clock_speed =
10667 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +020010668 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -070010669 dev_priv->display.get_display_clock_speed =
10670 i855_get_display_clock_speed;
10671 else /* 852, 830 */
10672 dev_priv->display.get_display_clock_speed =
10673 i830_get_display_clock_speed;
10674
Zhenyu Wang7f8a8562010-04-01 13:07:53 +080010675 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +010010676 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070010677 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010678 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +080010679 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -070010680 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010681 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -070010682 } else if (IS_IVYBRIDGE(dev)) {
10683 /* FIXME: detect B0+ stepping and use auto training */
10684 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +080010685 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +020010686 dev_priv->display.modeset_global_resources =
10687 ivb_modeset_global_resources;
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070010688 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -030010689 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +080010690 dev_priv->display.write_eld = haswell_write_eld;
Daniel Vetterd6dd9eb2013-01-29 16:35:20 -020010691 dev_priv->display.modeset_global_resources =
10692 haswell_modeset_global_resources;
Paulo Zanonia0e63c22012-12-06 11:12:39 -020010693 }
Jesse Barnes6067aae2011-04-28 15:04:31 -070010694 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +080010695 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnes30a970c2013-11-04 13:48:12 -080010696 } else if (IS_VALLEYVIEW(dev)) {
10697 dev_priv->display.modeset_global_resources =
10698 valleyview_modeset_global_resources;
Mengdong Lin9ca2fe72013-11-01 00:17:03 -040010699 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -070010700 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010701
10702 /* Default just returns -ENODEV to indicate unsupported */
10703 dev_priv->display.queue_flip = intel_default_queue_flip;
10704
10705 switch (INTEL_INFO(dev)->gen) {
10706 case 2:
10707 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10708 break;
10709
10710 case 3:
10711 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10712 break;
10713
10714 case 4:
10715 case 5:
10716 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10717 break;
10718
10719 case 6:
10720 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10721 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010722 case 7:
Ben Widawsky4e0bbc32013-11-02 21:07:07 -070010723 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
Jesse Barnes7c9017e2011-06-16 12:18:54 -070010724 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10725 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -070010726 }
Jani Nikula7bd688c2013-11-08 16:48:56 +020010727
10728 intel_panel_init_backlight_funcs(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070010729}
10730
Jesse Barnesb690e962010-07-19 13:53:12 -070010731/*
10732 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10733 * resume, or other times. This quirk makes sure that's the case for
10734 * affected systems.
10735 */
Akshay Joshi0206e352011-08-16 15:34:10 -040010736static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -070010737{
10738 struct drm_i915_private *dev_priv = dev->dev_private;
10739
10740 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010741 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070010742}
10743
Keith Packard435793d2011-07-12 14:56:22 -070010744/*
10745 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10746 */
10747static void quirk_ssc_force_disable(struct drm_device *dev)
10748{
10749 struct drm_i915_private *dev_priv = dev->dev_private;
10750 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010751 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -070010752}
10753
Carsten Emde4dca20e2012-03-15 15:56:26 +010010754/*
Carsten Emde5a15ab52012-03-15 15:56:27 +010010755 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10756 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +010010757 */
10758static void quirk_invert_brightness(struct drm_device *dev)
10759{
10760 struct drm_i915_private *dev_priv = dev->dev_private;
10761 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +020010762 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -070010763}
10764
10765struct intel_quirk {
10766 int device;
10767 int subsystem_vendor;
10768 int subsystem_device;
10769 void (*hook)(struct drm_device *dev);
10770};
10771
Egbert Eich5f85f1762012-10-14 15:46:38 +020010772/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10773struct intel_dmi_quirk {
10774 void (*hook)(struct drm_device *dev);
10775 const struct dmi_system_id (*dmi_id_list)[];
10776};
10777
10778static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10779{
10780 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10781 return 1;
10782}
10783
10784static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10785 {
10786 .dmi_id_list = &(const struct dmi_system_id[]) {
10787 {
10788 .callback = intel_dmi_reverse_brightness,
10789 .ident = "NCR Corporation",
10790 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10791 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10792 },
10793 },
10794 { } /* terminating entry */
10795 },
10796 .hook = quirk_invert_brightness,
10797 },
10798};
10799
Ben Widawskyc43b5632012-04-16 14:07:40 -070010800static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -070010801 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -040010802 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -070010803
Jesse Barnesb690e962010-07-19 13:53:12 -070010804 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10805 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10806
Jesse Barnesb690e962010-07-19 13:53:12 -070010807 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10808 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10809
Chris Wilsona4945f92013-10-08 11:16:59 +010010810 /* 830 needs to leave pipe A & dpll A up */
Daniel Vetterdcdaed62012-08-12 21:19:34 +020010811 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -070010812
10813 /* Lenovo U160 cannot use SSC on LVDS */
10814 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +020010815
10816 /* Sony Vaio Y cannot use SSC on LVDS */
10817 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +010010818
Jani Nikulaee1452d2013-09-20 15:05:30 +030010819 /*
10820 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10821 * seem to use inverted backlight PWM.
10822 */
10823 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -070010824};
10825
10826static void intel_init_quirks(struct drm_device *dev)
10827{
10828 struct pci_dev *d = dev->pdev;
10829 int i;
10830
10831 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10832 struct intel_quirk *q = &intel_quirks[i];
10833
10834 if (d->device == q->device &&
10835 (d->subsystem_vendor == q->subsystem_vendor ||
10836 q->subsystem_vendor == PCI_ANY_ID) &&
10837 (d->subsystem_device == q->subsystem_device ||
10838 q->subsystem_device == PCI_ANY_ID))
10839 q->hook(dev);
10840 }
Egbert Eich5f85f1762012-10-14 15:46:38 +020010841 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10842 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10843 intel_dmi_quirks[i].hook(dev);
10844 }
Jesse Barnesb690e962010-07-19 13:53:12 -070010845}
10846
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010847/* Disable the VGA plane that we never use */
10848static void i915_disable_vga(struct drm_device *dev)
10849{
10850 struct drm_i915_private *dev_priv = dev->dev_private;
10851 u8 sr1;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020010852 u32 vga_reg = i915_vgacntrl_reg(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010853
10854 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -070010855 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010856 sr1 = inb(VGA_SR_DATA);
10857 outb(sr1 | 1<<5, VGA_SR_DATA);
10858 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10859 udelay(300);
10860
10861 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10862 POSTING_READ(vga_reg);
10863}
10864
Daniel Vetterf8175862012-04-10 15:50:11 +020010865void intel_modeset_init_hw(struct drm_device *dev)
10866{
Eugeni Dodonova8f78b52012-06-28 15:55:35 -030010867 intel_prepare_ddi(dev);
10868
Daniel Vetterf8175862012-04-10 15:50:11 +020010869 intel_init_clock_gating(dev);
10870
Jesse Barnes5382f5f352013-12-16 16:34:24 -080010871 intel_reset_dpio(dev);
Jesse Barnes40e9cf62013-10-03 11:35:46 -070010872
Daniel Vetter79f5b2c2012-06-24 16:42:33 +020010873 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +020010874 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +020010875 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +020010876}
10877
Imre Deak7d708ee2013-04-17 14:04:50 +030010878void intel_modeset_suspend_hw(struct drm_device *dev)
10879{
10880 intel_suspend_hw(dev);
10881}
10882
Jesse Barnes79e53942008-11-07 14:24:08 -080010883void intel_modeset_init(struct drm_device *dev)
10884{
Jesse Barnes652c3932009-08-17 13:31:43 -070010885 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010886 int i, j, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -080010887
10888 drm_mode_config_init(dev);
10889
10890 dev->mode_config.min_width = 0;
10891 dev->mode_config.min_height = 0;
10892
Dave Airlie019d96c2011-09-29 16:20:42 +010010893 dev->mode_config.preferred_depth = 24;
10894 dev->mode_config.prefer_shadow = 1;
10895
Laurent Pincharte6ecefa2012-05-17 13:27:23 +020010896 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -080010897
Jesse Barnesb690e962010-07-19 13:53:12 -070010898 intel_init_quirks(dev);
10899
Eugeni Dodonov1fa61102012-04-18 15:29:26 -030010900 intel_init_pm(dev);
10901
Ben Widawskye3c74752013-04-05 13:12:39 -070010902 if (INTEL_INFO(dev)->num_pipes == 0)
10903 return;
10904
Jesse Barnese70236a2009-09-21 10:42:27 -070010905 intel_init_display(dev);
10906
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010907 if (IS_GEN2(dev)) {
10908 dev->mode_config.max_width = 2048;
10909 dev->mode_config.max_height = 2048;
10910 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -070010911 dev->mode_config.max_width = 4096;
10912 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -080010913 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +010010914 dev->mode_config.max_width = 8192;
10915 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -080010916 }
Ben Widawsky5d4545a2013-01-17 12:45:15 -080010917 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
Jesse Barnes79e53942008-11-07 14:24:08 -080010918
Zhao Yakui28c97732009-10-09 11:39:41 +080010919 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010920 INTEL_INFO(dev)->num_pipes,
10921 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -080010922
Damien Lespiau08e2a7d2013-07-11 20:10:54 +010010923 for_each_pipe(i) {
Jesse Barnes79e53942008-11-07 14:24:08 -080010924 intel_crtc_init(dev, i);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010925 for (j = 0; j < dev_priv->num_plane; j++) {
10926 ret = intel_plane_init(dev, i, j);
10927 if (ret)
Ville Syrjälä06da8da2013-04-17 17:48:51 +030010928 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10929 pipe_name(i), sprite_name(i, j), ret);
Jesse Barnes7f1f3852013-04-02 11:22:20 -070010930 }
Jesse Barnes79e53942008-11-07 14:24:08 -080010931 }
10932
Jesse Barnesf42bb702013-12-16 16:34:23 -080010933 intel_init_dpio(dev);
Jesse Barnes5382f5f352013-12-16 16:34:24 -080010934 intel_reset_dpio(dev);
Jesse Barnesf42bb702013-12-16 16:34:23 -080010935
Paulo Zanoni79f689a2012-10-05 12:05:52 -030010936 intel_cpu_pll_init(dev);
Daniel Vettere72f9fb2013-06-05 13:34:06 +020010937 intel_shared_dpll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +010010938
Jesse Barnes9cce37f2010-08-13 15:11:26 -070010939 /* Just disable it once at startup */
10940 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080010941 intel_setup_outputs(dev);
Chris Wilson11be49e2012-11-15 11:32:20 +000010942
10943 /* Just in case the BIOS is doing something questionable. */
10944 intel_disable_fbc(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010010945}
Jesse Barnesd5bb0812011-01-05 12:01:26 -080010946
Daniel Vetter24929352012-07-02 20:28:59 +020010947static void
10948intel_connector_break_all_links(struct intel_connector *connector)
10949{
10950 connector->base.dpms = DRM_MODE_DPMS_OFF;
10951 connector->base.encoder = NULL;
10952 connector->encoder->connectors_active = false;
10953 connector->encoder->base.crtc = NULL;
10954}
10955
Daniel Vetter7fad7982012-07-04 17:51:47 +020010956static void intel_enable_pipe_a(struct drm_device *dev)
10957{
10958 struct intel_connector *connector;
10959 struct drm_connector *crt = NULL;
10960 struct intel_load_detect_pipe load_detect_temp;
10961
10962 /* We can't just switch on the pipe A, we need to set things up with a
10963 * proper mode and output configuration. As a gross hack, enable pipe A
10964 * by enabling the load detect pipe once. */
10965 list_for_each_entry(connector,
10966 &dev->mode_config.connector_list,
10967 base.head) {
10968 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10969 crt = &connector->base;
10970 break;
10971 }
10972 }
10973
10974 if (!crt)
10975 return;
10976
10977 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10978 intel_release_load_detect_pipe(crt, &load_detect_temp);
10979
10980
10981}
10982
Daniel Vetterfa555832012-10-10 23:14:00 +020010983static bool
10984intel_check_plane_mapping(struct intel_crtc *crtc)
10985{
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010986 struct drm_device *dev = crtc->base.dev;
10987 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020010988 u32 reg, val;
10989
Ben Widawsky7eb552a2013-03-13 14:05:41 -070010990 if (INTEL_INFO(dev)->num_pipes == 1)
Daniel Vetterfa555832012-10-10 23:14:00 +020010991 return true;
10992
10993 reg = DSPCNTR(!crtc->plane);
10994 val = I915_READ(reg);
10995
10996 if ((val & DISPLAY_PLANE_ENABLE) &&
10997 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10998 return false;
10999
11000 return true;
11001}
11002
Daniel Vetter24929352012-07-02 20:28:59 +020011003static void intel_sanitize_crtc(struct intel_crtc *crtc)
11004{
11005 struct drm_device *dev = crtc->base.dev;
11006 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +020011007 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +020011008
Daniel Vetter24929352012-07-02 20:28:59 +020011009 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vetter3b117c82013-04-17 20:15:07 +020011010 reg = PIPECONF(crtc->config.cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +020011011 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11012
11013 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +020011014 * disable the crtc (and hence change the state) if it is wrong. Note
11015 * that gen4+ has a fixed plane -> pipe mapping. */
11016 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +020011017 struct intel_connector *connector;
11018 bool plane;
11019
Daniel Vetter24929352012-07-02 20:28:59 +020011020 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11021 crtc->base.base.id);
11022
11023 /* Pipe has the wrong plane attached and the plane is active.
11024 * Temporarily change the plane mapping and disable everything
11025 * ... */
11026 plane = crtc->plane;
11027 crtc->plane = !plane;
11028 dev_priv->display.crtc_disable(&crtc->base);
11029 crtc->plane = plane;
11030
11031 /* ... and break all links. */
11032 list_for_each_entry(connector, &dev->mode_config.connector_list,
11033 base.head) {
11034 if (connector->encoder->base.crtc != &crtc->base)
11035 continue;
11036
11037 intel_connector_break_all_links(connector);
11038 }
11039
11040 WARN_ON(crtc->active);
11041 crtc->base.enabled = false;
11042 }
Daniel Vetter24929352012-07-02 20:28:59 +020011043
Daniel Vetter7fad7982012-07-04 17:51:47 +020011044 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11045 crtc->pipe == PIPE_A && !crtc->active) {
11046 /* BIOS forgot to enable pipe A, this mostly happens after
11047 * resume. Force-enable the pipe to fix this, the update_dpms
11048 * call below we restore the pipe to the right state, but leave
11049 * the required bits on. */
11050 intel_enable_pipe_a(dev);
11051 }
11052
Daniel Vetter24929352012-07-02 20:28:59 +020011053 /* Adjust the state of the output pipe according to whether we
11054 * have active connectors/encoders. */
11055 intel_crtc_update_dpms(&crtc->base);
11056
11057 if (crtc->active != crtc->base.enabled) {
11058 struct intel_encoder *encoder;
11059
11060 /* This can happen either due to bugs in the get_hw_state
11061 * functions or because the pipe is force-enabled due to the
11062 * pipe A quirk. */
11063 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11064 crtc->base.base.id,
11065 crtc->base.enabled ? "enabled" : "disabled",
11066 crtc->active ? "enabled" : "disabled");
11067
11068 crtc->base.enabled = crtc->active;
11069
11070 /* Because we only establish the connector -> encoder ->
11071 * crtc links if something is active, this means the
11072 * crtc is now deactivated. Break the links. connector
11073 * -> encoder links are only establish when things are
11074 * actually up, hence no need to break them. */
11075 WARN_ON(crtc->active);
11076
11077 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11078 WARN_ON(encoder->connectors_active);
11079 encoder->base.crtc = NULL;
11080 }
11081 }
11082}
11083
11084static void intel_sanitize_encoder(struct intel_encoder *encoder)
11085{
11086 struct intel_connector *connector;
11087 struct drm_device *dev = encoder->base.dev;
11088
11089 /* We need to check both for a crtc link (meaning that the
11090 * encoder is active and trying to read from a pipe) and the
11091 * pipe itself being active. */
11092 bool has_active_crtc = encoder->base.crtc &&
11093 to_intel_crtc(encoder->base.crtc)->active;
11094
11095 if (encoder->connectors_active && !has_active_crtc) {
11096 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11097 encoder->base.base.id,
11098 drm_get_encoder_name(&encoder->base));
11099
11100 /* Connector is active, but has no active pipe. This is
11101 * fallout from our resume register restoring. Disable
11102 * the encoder manually again. */
11103 if (encoder->base.crtc) {
11104 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11105 encoder->base.base.id,
11106 drm_get_encoder_name(&encoder->base));
11107 encoder->disable(encoder);
11108 }
11109
11110 /* Inconsistent output/port/pipe state happens presumably due to
11111 * a bug in one of the get_hw_state functions. Or someplace else
11112 * in our code, like the register restore mess on resume. Clamp
11113 * things to off as a safer default. */
11114 list_for_each_entry(connector,
11115 &dev->mode_config.connector_list,
11116 base.head) {
11117 if (connector->encoder != encoder)
11118 continue;
11119
11120 intel_connector_break_all_links(connector);
11121 }
11122 }
11123 /* Enabled encoders without active connectors will be fixed in
11124 * the crtc fixup. */
11125}
11126
Daniel Vetter44cec742013-01-25 17:53:21 +010011127void i915_redisable_vga(struct drm_device *dev)
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011128{
11129 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +020011130 u32 vga_reg = i915_vgacntrl_reg(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011131
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030011132 /* This function can be called both from intel_modeset_setup_hw_state or
11133 * at a very early point in our resume sequence, where the power well
11134 * structures are not yet restored. Since this function is at a very
11135 * paranoid "someone might have enabled VGA while we were not looking"
11136 * level, just check if the power well is enabled instead of trying to
11137 * follow the "don't touch the power well if we don't need it" policy
11138 * the rest of the driver uses. */
Jesse Barnesf9e711e2013-11-25 17:15:32 +020011139 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
Paulo Zanoni6aedd1f2013-08-02 16:22:25 -030011140 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
Paulo Zanoni8dc8a272013-08-02 16:22:24 -030011141 return;
11142
Ville Syrjäläe1553fa2013-10-04 20:32:25 +030011143 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011144 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
Ville Syrjälä209d5212013-01-25 21:44:48 +020011145 i915_disable_vga(dev);
Krzysztof Mazur0fde9012012-12-19 11:03:41 +010011146 }
11147}
11148
Daniel Vetter30e984d2013-06-05 13:34:17 +020011149static void intel_modeset_readout_hw_state(struct drm_device *dev)
Daniel Vetter24929352012-07-02 20:28:59 +020011150{
11151 struct drm_i915_private *dev_priv = dev->dev_private;
11152 enum pipe pipe;
Daniel Vetter24929352012-07-02 20:28:59 +020011153 struct intel_crtc *crtc;
11154 struct intel_encoder *encoder;
11155 struct intel_connector *connector;
Daniel Vetter53589012013-06-05 13:34:16 +020011156 int i;
Daniel Vetter24929352012-07-02 20:28:59 +020011157
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011158 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11159 base.head) {
Daniel Vetter88adfff2013-03-28 10:42:01 +010011160 memset(&crtc->config, 0, sizeof(crtc->config));
Daniel Vetter3b117c82013-04-17 20:15:07 +020011161
Daniel Vetter0e8ffe12013-03-28 10:42:00 +010011162 crtc->active = dev_priv->display.get_pipe_config(crtc,
11163 &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020011164
11165 crtc->base.enabled = crtc->active;
Ville Syrjälä4c445e02013-10-09 17:24:58 +030011166 crtc->primary_enabled = crtc->active;
Daniel Vetter24929352012-07-02 20:28:59 +020011167
11168 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11169 crtc->base.base.id,
11170 crtc->active ? "enabled" : "disabled");
11171 }
11172
Daniel Vetter53589012013-06-05 13:34:16 +020011173 /* FIXME: Smash this into the new shared dpll infrastructure. */
Paulo Zanoniaffa9352012-11-23 15:30:39 -020011174 if (HAS_DDI(dev))
Paulo Zanoni6441ab52012-10-05 12:05:58 -030011175 intel_ddi_setup_hw_pll_state(dev);
11176
Daniel Vetter53589012013-06-05 13:34:16 +020011177 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11178 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11179
11180 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11181 pll->active = 0;
11182 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11183 base.head) {
11184 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11185 pll->active++;
11186 }
11187 pll->refcount = pll->active;
11188
Daniel Vetter35c95372013-07-17 06:55:04 +020011189 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11190 pll->name, pll->refcount, pll->on);
Daniel Vetter53589012013-06-05 13:34:16 +020011191 }
11192
Daniel Vetter24929352012-07-02 20:28:59 +020011193 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11194 base.head) {
11195 pipe = 0;
11196
11197 if (encoder->get_hw_state(encoder, &pipe)) {
Jesse Barnes045ac3b2013-05-14 17:08:26 -070011198 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11199 encoder->base.crtc = &crtc->base;
Daniel Vetter1d37b682013-11-18 09:00:59 +010011200 encoder->get_config(encoder, &crtc->config);
Daniel Vetter24929352012-07-02 20:28:59 +020011201 } else {
11202 encoder->base.crtc = NULL;
11203 }
11204
11205 encoder->connectors_active = false;
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010011206 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
Daniel Vetter24929352012-07-02 20:28:59 +020011207 encoder->base.base.id,
11208 drm_get_encoder_name(&encoder->base),
11209 encoder->base.crtc ? "enabled" : "disabled",
Damien Lespiau6f2bcce2013-10-16 12:29:54 +010011210 pipe_name(pipe));
Daniel Vetter24929352012-07-02 20:28:59 +020011211 }
11212
11213 list_for_each_entry(connector, &dev->mode_config.connector_list,
11214 base.head) {
11215 if (connector->get_hw_state(connector)) {
11216 connector->base.dpms = DRM_MODE_DPMS_ON;
11217 connector->encoder->connectors_active = true;
11218 connector->base.encoder = &connector->encoder->base;
11219 } else {
11220 connector->base.dpms = DRM_MODE_DPMS_OFF;
11221 connector->base.encoder = NULL;
11222 }
11223 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11224 connector->base.base.id,
11225 drm_get_connector_name(&connector->base),
11226 connector->base.encoder ? "enabled" : "disabled");
11227 }
Daniel Vetter30e984d2013-06-05 13:34:17 +020011228}
11229
11230/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11231 * and i915 state tracking structures. */
11232void intel_modeset_setup_hw_state(struct drm_device *dev,
11233 bool force_restore)
11234{
11235 struct drm_i915_private *dev_priv = dev->dev_private;
11236 enum pipe pipe;
Daniel Vetter30e984d2013-06-05 13:34:17 +020011237 struct intel_crtc *crtc;
11238 struct intel_encoder *encoder;
Daniel Vetter35c95372013-07-17 06:55:04 +020011239 int i;
Daniel Vetter30e984d2013-06-05 13:34:17 +020011240
11241 intel_modeset_readout_hw_state(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020011242
Jesse Barnesbabea612013-06-26 18:57:38 +030011243 /*
11244 * Now that we have the config, copy it to each CRTC struct
11245 * Note that this could go away if we move to using crtc_config
11246 * checking everywhere.
11247 */
11248 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11249 base.head) {
11250 if (crtc->active && i915_fastboot) {
11251 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11252
11253 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11254 crtc->base.base.id);
11255 drm_mode_debug_printmodeline(&crtc->base.mode);
11256 }
11257 }
11258
Daniel Vetter24929352012-07-02 20:28:59 +020011259 /* HW state is read out, now we need to sanitize this mess. */
11260 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11261 base.head) {
11262 intel_sanitize_encoder(encoder);
11263 }
11264
11265 for_each_pipe(pipe) {
11266 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11267 intel_sanitize_crtc(crtc);
Daniel Vetterc0b03412013-05-28 12:05:54 +020011268 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
Daniel Vetter24929352012-07-02 20:28:59 +020011269 }
Daniel Vetter9a935852012-07-05 22:34:27 +020011270
Daniel Vetter35c95372013-07-17 06:55:04 +020011271 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11272 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11273
11274 if (!pll->on || pll->active)
11275 continue;
11276
11277 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11278
11279 pll->disable(dev_priv, pll);
11280 pll->on = false;
11281 }
11282
Ville Syrjälä96f90c52013-12-05 15:51:38 +020011283 if (HAS_PCH_SPLIT(dev))
Ville Syrjälä243e6a42013-10-14 14:55:24 +030011284 ilk_wm_get_hw_state(dev);
11285
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011286 if (force_restore) {
Ville Syrjälä7d0bc1e2013-09-16 17:38:33 +030011287 i915_redisable_vga(dev);
11288
Daniel Vetterf30da182013-04-11 20:22:50 +020011289 /*
11290 * We need to use raw interfaces for restoring state to avoid
11291 * checking (bogus) intermediate states.
11292 */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011293 for_each_pipe(pipe) {
Jesse Barnesb5644d02013-03-26 13:25:27 -070011294 struct drm_crtc *crtc =
11295 dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetterf30da182013-04-11 20:22:50 +020011296
11297 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11298 crtc->fb);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011299 }
11300 } else {
11301 intel_modeset_update_staged_output_state(dev);
11302 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +020011303
11304 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +020011305
11306 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +010011307}
11308
11309void intel_modeset_gem_init(struct drm_device *dev)
11310{
Chris Wilson1833b132012-05-09 11:56:28 +010011311 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +020011312
11313 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +020011314
Daniel Vetter45e2b5f2012-11-23 18:16:34 +010011315 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -080011316}
11317
11318void intel_modeset_cleanup(struct drm_device *dev)
11319{
Jesse Barnes652c3932009-08-17 13:31:43 -070011320 struct drm_i915_private *dev_priv = dev->dev_private;
11321 struct drm_crtc *crtc;
Paulo Zanonid9255d52013-09-26 20:05:59 -030011322 struct drm_connector *connector;
Jesse Barnes652c3932009-08-17 13:31:43 -070011323
Daniel Vetterfd0c0642013-04-24 11:13:35 +020011324 /*
11325 * Interrupts and polling as the first thing to avoid creating havoc.
11326 * Too much stuff here (turning of rps, connectors, ...) would
11327 * experience fancy races otherwise.
11328 */
11329 drm_irq_uninstall(dev);
11330 cancel_work_sync(&dev_priv->hotplug_work);
11331 /*
11332 * Due to the hpd irq storm handling the hotplug work can re-arm the
11333 * poll handlers. Hence disable polling after hpd handling is shut down.
11334 */
Keith Packardf87ea762010-10-03 19:36:26 -070011335 drm_kms_helper_poll_fini(dev);
Daniel Vetterfd0c0642013-04-24 11:13:35 +020011336
Jesse Barnes652c3932009-08-17 13:31:43 -070011337 mutex_lock(&dev->struct_mutex);
11338
Jesse Barnes723bfd72010-10-07 16:01:13 -070011339 intel_unregister_dsm_handler();
11340
Jesse Barnes652c3932009-08-17 13:31:43 -070011341 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11342 /* Skip inactive CRTCs */
11343 if (!crtc->fb)
11344 continue;
11345
Daniel Vetter3dec0092010-08-20 21:40:52 +020011346 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -070011347 }
11348
Chris Wilson973d04f2011-07-08 12:22:37 +010011349 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -070011350
Daniel Vetter8090c6b2012-06-24 16:42:32 +020011351 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +000011352
Daniel Vetter930ebb42012-06-29 23:32:16 +020011353 ironlake_teardown_rc6(dev);
11354
Kristian Høgsberg69341a52009-11-11 12:19:17 -050011355 mutex_unlock(&dev->struct_mutex);
11356
Chris Wilson1630fe72011-07-08 12:22:42 +010011357 /* flush any delayed tasks or pending work */
11358 flush_scheduled_work();
11359
Jani Nikuladb31af12013-11-08 16:48:53 +020011360 /* destroy the backlight and sysfs files before encoders/connectors */
11361 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11362 intel_panel_destroy_backlight(connector);
Paulo Zanonid9255d52013-09-26 20:05:59 -030011363 drm_sysfs_connector_remove(connector);
Jani Nikuladb31af12013-11-08 16:48:53 +020011364 }
Paulo Zanonid9255d52013-09-26 20:05:59 -030011365
Jesse Barnes79e53942008-11-07 14:24:08 -080011366 drm_mode_config_cleanup(dev);
Daniel Vetter4d7bb012012-12-18 15:24:37 +010011367
11368 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -080011369}
11370
Dave Airlie28d52042009-09-21 14:33:58 +100011371/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +080011372 * Return which encoder is currently attached for connector.
11373 */
Chris Wilsondf0e9242010-09-09 16:20:55 +010011374struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -080011375{
Chris Wilsondf0e9242010-09-09 16:20:55 +010011376 return &intel_attached_encoder(connector)->base;
11377}
Jesse Barnes79e53942008-11-07 14:24:08 -080011378
Chris Wilsondf0e9242010-09-09 16:20:55 +010011379void intel_connector_attach_encoder(struct intel_connector *connector,
11380 struct intel_encoder *encoder)
11381{
11382 connector->encoder = encoder;
11383 drm_mode_connector_attach_encoder(&connector->base,
11384 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -080011385}
Dave Airlie28d52042009-09-21 14:33:58 +100011386
11387/*
11388 * set vga decode state - true == enable VGA decode
11389 */
11390int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11391{
11392 struct drm_i915_private *dev_priv = dev->dev_private;
11393 u16 gmch_ctrl;
11394
11395 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11396 if (state)
11397 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11398 else
11399 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11400 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11401 return 0;
11402}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011403
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011404struct intel_display_error_state {
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011405
11406 u32 power_well_driver;
11407
Chris Wilson63b66e52013-08-08 15:12:06 +020011408 int num_transcoders;
11409
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011410 struct intel_cursor_error_state {
11411 u32 control;
11412 u32 position;
11413 u32 base;
11414 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +010011415 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011416
11417 struct intel_pipe_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020011418 bool power_domain_on;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011419 u32 source;
Damien Lespiau52331302012-08-15 19:23:25 +010011420 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011421
11422 struct intel_plane_error_state {
11423 u32 control;
11424 u32 stride;
11425 u32 size;
11426 u32 pos;
11427 u32 addr;
11428 u32 surface;
11429 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +010011430 } plane[I915_MAX_PIPES];
Chris Wilson63b66e52013-08-08 15:12:06 +020011431
11432 struct intel_transcoder_error_state {
Imre Deakddf9c532013-11-27 22:02:02 +020011433 bool power_domain_on;
Chris Wilson63b66e52013-08-08 15:12:06 +020011434 enum transcoder cpu_transcoder;
11435
11436 u32 conf;
11437
11438 u32 htotal;
11439 u32 hblank;
11440 u32 hsync;
11441 u32 vtotal;
11442 u32 vblank;
11443 u32 vsync;
11444 } transcoder[4];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011445};
11446
11447struct intel_display_error_state *
11448intel_display_capture_error_state(struct drm_device *dev)
11449{
Akshay Joshi0206e352011-08-16 15:34:10 -040011450 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011451 struct intel_display_error_state *error;
Chris Wilson63b66e52013-08-08 15:12:06 +020011452 int transcoders[] = {
11453 TRANSCODER_A,
11454 TRANSCODER_B,
11455 TRANSCODER_C,
11456 TRANSCODER_EDP,
11457 };
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011458 int i;
11459
Chris Wilson63b66e52013-08-08 15:12:06 +020011460 if (INTEL_INFO(dev)->num_pipes == 0)
11461 return NULL;
11462
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011463 error = kzalloc(sizeof(*error), GFP_ATOMIC);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011464 if (error == NULL)
11465 return NULL;
11466
Imre Deak190be112013-11-25 17:15:31 +020011467 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011468 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11469
Damien Lespiau52331302012-08-15 19:23:25 +010011470 for_each_pipe(i) {
Imre Deakddf9c532013-11-27 22:02:02 +020011471 error->pipe[i].power_domain_on =
11472 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11473 if (!error->pipe[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011474 continue;
11475
Paulo Zanonia18c4c32013-03-06 20:03:12 -030011476 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11477 error->cursor[i].control = I915_READ(CURCNTR(i));
11478 error->cursor[i].position = I915_READ(CURPOS(i));
11479 error->cursor[i].base = I915_READ(CURBASE(i));
11480 } else {
11481 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11482 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11483 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11484 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011485
11486 error->plane[i].control = I915_READ(DSPCNTR(i));
11487 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011488 if (INTEL_INFO(dev)->gen <= 3) {
Paulo Zanoni51889b32013-03-06 20:03:13 -030011489 error->plane[i].size = I915_READ(DSPSIZE(i));
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011490 error->plane[i].pos = I915_READ(DSPPOS(i));
11491 }
Paulo Zanonica291362013-03-06 20:03:14 -030011492 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11493 error->plane[i].addr = I915_READ(DSPADDR(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011494 if (INTEL_INFO(dev)->gen >= 4) {
11495 error->plane[i].surface = I915_READ(DSPSURF(i));
11496 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11497 }
11498
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011499 error->pipe[i].source = I915_READ(PIPESRC(i));
Chris Wilson63b66e52013-08-08 15:12:06 +020011500 }
11501
11502 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11503 if (HAS_DDI(dev_priv->dev))
11504 error->num_transcoders++; /* Account for eDP. */
11505
11506 for (i = 0; i < error->num_transcoders; i++) {
11507 enum transcoder cpu_transcoder = transcoders[i];
11508
Imre Deakddf9c532013-11-27 22:02:02 +020011509 error->transcoder[i].power_domain_on =
Paulo Zanoni38cc1da2013-12-20 15:09:41 -020011510 intel_display_power_enabled_sw(dev,
11511 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020011512 if (!error->transcoder[i].power_domain_on)
Paulo Zanoni9d1cb912013-11-01 13:32:08 -020011513 continue;
11514
Chris Wilson63b66e52013-08-08 15:12:06 +020011515 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11516
11517 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11518 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11519 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11520 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11521 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11522 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11523 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011524 }
11525
11526 return error;
11527}
11528
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011529#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11530
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011531void
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011532intel_display_print_error_state(struct drm_i915_error_state_buf *m,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011533 struct drm_device *dev,
11534 struct intel_display_error_state *error)
11535{
11536 int i;
11537
Chris Wilson63b66e52013-08-08 15:12:06 +020011538 if (!error)
11539 return;
11540
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011541 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
Imre Deak190be112013-11-25 17:15:31 +020011542 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011543 err_printf(m, "PWR_WELL_CTL2: %08x\n",
Paulo Zanoniff57f1b2013-05-03 12:15:37 -030011544 error->power_well_driver);
Damien Lespiau52331302012-08-15 19:23:25 +010011545 for_each_pipe(i) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011546 err_printf(m, "Pipe [%d]:\n", i);
Imre Deakddf9c532013-11-27 22:02:02 +020011547 err_printf(m, " Power: %s\n",
11548 error->pipe[i].power_domain_on ? "on" : "off");
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011549 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011550
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011551 err_printf(m, "Plane [%d]:\n", i);
11552 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11553 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011554 if (INTEL_INFO(dev)->gen <= 3) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011555 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11556 err_printf(m, " POS: %08x\n", error->plane[i].pos);
Paulo Zanoni80ca3782013-03-22 14:20:57 -030011557 }
Paulo Zanoni4b71a572013-03-22 14:19:21 -030011558 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011559 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011560 if (INTEL_INFO(dev)->gen >= 4) {
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011561 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11562 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011563 }
11564
Mika Kuoppalaedc3d882013-05-23 13:55:35 +030011565 err_printf(m, "Cursor [%d]:\n", i);
11566 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11567 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11568 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011569 }
Chris Wilson63b66e52013-08-08 15:12:06 +020011570
11571 for (i = 0; i < error->num_transcoders; i++) {
Chris Wilson1cf84bb2013-10-21 09:10:33 +010011572 err_printf(m, "CPU transcoder: %c\n",
Chris Wilson63b66e52013-08-08 15:12:06 +020011573 transcoder_name(error->transcoder[i].cpu_transcoder));
Imre Deakddf9c532013-11-27 22:02:02 +020011574 err_printf(m, " Power: %s\n",
11575 error->transcoder[i].power_domain_on ? "on" : "off");
Chris Wilson63b66e52013-08-08 15:12:06 +020011576 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11577 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11578 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11579 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11580 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11581 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11582 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11583 }
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +000011584}