Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 31 | #include <linux/notifier.h> |
| 32 | #include <linux/reboot.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 34 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drm_crtc.h> |
| 36 | #include <drm/drm_crtc_helper.h> |
| 37 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 41 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 43 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 44 | /* Compliance test status bits */ |
| 45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 |
| 46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) |
| 49 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 50 | struct dp_link_dpll { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 51 | int clock; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 52 | struct dpll dpll; |
| 53 | }; |
| 54 | |
| 55 | static const struct dp_link_dpll gen4_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 56 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 58 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 60 | }; |
| 61 | |
| 62 | static const struct dp_link_dpll pch_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 63 | { 162000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 65 | { 270000, |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 67 | }; |
| 68 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 70 | { 162000, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 72 | { 270000, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 74 | }; |
| 75 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 76 | /* |
| 77 | * CHV supports eDP 1.4 that have more link rates. |
| 78 | * Below only provides the fixed rate but exclude variable rate. |
| 79 | */ |
| 80 | static const struct dp_link_dpll chv_dpll[] = { |
| 81 | /* |
| 82 | * CHV requires to program fractional division for m2. |
| 83 | * m2 is stored in fixed point format using formula below |
| 84 | * (m2_int << 22) | m2_fraction |
| 85 | */ |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 92 | }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 93 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
| 95 | 324000, 432000, 540000 }; |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 97 | 324000, 432000, 540000 }; |
| 98 | static const int default_rates[] = { 162000, 270000, 540000 }; |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 99 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 100 | /** |
| 101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 102 | * @intel_dp: DP struct |
| 103 | * |
| 104 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 105 | * will return true, and false otherwise. |
| 106 | */ |
| 107 | static bool is_edp(struct intel_dp *intel_dp) |
| 108 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 110 | |
| 111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 112 | } |
| 113 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 115 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 117 | |
| 118 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 119 | } |
| 120 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 122 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 124 | } |
| 125 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 131 | enum pipe pipe); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 133 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 134 | static int |
| 135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 136 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 138 | |
| 139 | switch (max_link_bw) { |
| 140 | case DP_LINK_BW_1_62: |
| 141 | case DP_LINK_BW_2_7: |
Ville Syrjälä | 1db10e2 | 2015-03-12 17:10:32 +0200 | [diff] [blame] | 142 | case DP_LINK_BW_5_4: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 143 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 144 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 146 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 147 | max_link_bw = DP_LINK_BW_1_62; |
| 148 | break; |
| 149 | } |
| 150 | return max_link_bw; |
| 151 | } |
| 152 | |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 154 | { |
| 155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 156 | u8 source_max, sink_max; |
| 157 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 158 | source_max = intel_dig_port->max_lanes; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 160 | |
| 161 | return min(source_max, sink_max); |
| 162 | } |
| 163 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 164 | /* |
| 165 | * The units on the numbers in the next two are... bizarre. Examples will |
| 166 | * make it clearer; this one parallels an example in the eDP spec. |
| 167 | * |
| 168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 169 | * |
| 170 | * 270000 * 1 * 8 / 10 == 216000 |
| 171 | * |
| 172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 175 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 176 | * |
| 177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 178 | * get the result in decakilobits instead of kilobits. |
| 179 | */ |
| 180 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 181 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 183 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 184 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 189 | { |
| 190 | return (max_link_clock * max_lanes * 8) / 10; |
| 191 | } |
| 192 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 193 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 194 | intel_dp_mode_valid(struct drm_connector *connector, |
| 195 | struct drm_display_mode *mode) |
| 196 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 197 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 198 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 199 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 200 | int target_clock = mode->clock; |
| 201 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Mika Kahola | 799487f | 2016-02-02 15:16:38 +0200 | [diff] [blame] | 202 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 203 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 204 | if (is_edp(intel_dp) && fixed_mode) { |
| 205 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 206 | return MODE_PANEL; |
| 207 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 208 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 209 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 210 | |
| 211 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 212 | } |
| 213 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 214 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 215 | max_lanes = intel_dp_max_lane_count(intel_dp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 216 | |
| 217 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 218 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 219 | |
Mika Kahola | 799487f | 2016-02-02 15:16:38 +0200 | [diff] [blame] | 220 | if (mode_rate > max_rate || target_clock > max_dotclk) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 221 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 222 | |
| 223 | if (mode->clock < 10000) |
| 224 | return MODE_CLOCK_LOW; |
| 225 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 226 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 227 | return MODE_H_ILLEGAL; |
| 228 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 229 | return MODE_OK; |
| 230 | } |
| 231 | |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 232 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 233 | { |
| 234 | int i; |
| 235 | uint32_t v = 0; |
| 236 | |
| 237 | if (src_bytes > 4) |
| 238 | src_bytes = 4; |
| 239 | for (i = 0; i < src_bytes; i++) |
| 240 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 241 | return v; |
| 242 | } |
| 243 | |
Damien Lespiau | c2af70e | 2015-02-10 19:32:23 +0000 | [diff] [blame] | 244 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 245 | { |
| 246 | int i; |
| 247 | if (dst_bytes > 4) |
| 248 | dst_bytes = 4; |
| 249 | for (i = 0; i < dst_bytes; i++) |
| 250 | dst[i] = src >> ((3-i) * 8); |
| 251 | } |
| 252 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 253 | static void |
| 254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 255 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 256 | static void |
| 257 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 258 | struct intel_dp *intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 259 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 260 | static void pps_lock(struct intel_dp *intel_dp) |
| 261 | { |
| 262 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 263 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 264 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 265 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 266 | enum intel_display_power_domain power_domain; |
| 267 | |
| 268 | /* |
| 269 | * See vlv_power_sequencer_reset() why we need |
| 270 | * a power domain reference here. |
| 271 | */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 272 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 273 | intel_display_power_get(dev_priv, power_domain); |
| 274 | |
| 275 | mutex_lock(&dev_priv->pps_mutex); |
| 276 | } |
| 277 | |
| 278 | static void pps_unlock(struct intel_dp *intel_dp) |
| 279 | { |
| 280 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 281 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 282 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 283 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 284 | enum intel_display_power_domain power_domain; |
| 285 | |
| 286 | mutex_unlock(&dev_priv->pps_mutex); |
| 287 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 288 | power_domain = intel_display_port_aux_power_domain(encoder); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 289 | intel_display_power_put(dev_priv, power_domain); |
| 290 | } |
| 291 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 292 | static void |
| 293 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 294 | { |
| 295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 296 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 297 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 298 | enum pipe pipe = intel_dp->pps_pipe; |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 299 | bool pll_enabled, release_cl_override = false; |
| 300 | enum dpio_phy phy = DPIO_PHY(pipe); |
| 301 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 302 | uint32_t DP; |
| 303 | |
| 304 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, |
| 305 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", |
| 306 | pipe_name(pipe), port_name(intel_dig_port->port))) |
| 307 | return; |
| 308 | |
| 309 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", |
| 310 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 311 | |
| 312 | /* Preserve the BIOS-computed detected bit. This is |
| 313 | * supposed to be read-only. |
| 314 | */ |
| 315 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
| 316 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 317 | DP |= DP_PORT_WIDTH(1); |
| 318 | DP |= DP_LINK_TRAIN_PAT_1; |
| 319 | |
| 320 | if (IS_CHERRYVIEW(dev)) |
| 321 | DP |= DP_PIPE_SELECT_CHV(pipe); |
| 322 | else if (pipe == PIPE_B) |
| 323 | DP |= DP_PIPEB_SELECT; |
| 324 | |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 325 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
| 326 | |
| 327 | /* |
| 328 | * The DPLL for the pipe must be enabled for this to work. |
| 329 | * So enable temporarily it if it's not already enabled. |
| 330 | */ |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 331 | if (!pll_enabled) { |
| 332 | release_cl_override = IS_CHERRYVIEW(dev) && |
| 333 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
| 334 | |
Tvrtko Ursulin | 3f36b93 | 2016-01-19 15:25:17 +0000 | [diff] [blame] | 335 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
| 336 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 337 | DRM_ERROR("Failed to force on pll for pipe %c!\n", |
| 338 | pipe_name(pipe)); |
| 339 | return; |
| 340 | } |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 341 | } |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 342 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 343 | /* |
| 344 | * Similar magic as in intel_dp_enable_port(). |
| 345 | * We _must_ do this port enable + disable trick |
| 346 | * to make this power seqeuencer lock onto the port. |
| 347 | * Otherwise even VDD force bit won't work. |
| 348 | */ |
| 349 | I915_WRITE(intel_dp->output_reg, DP); |
| 350 | POSTING_READ(intel_dp->output_reg); |
| 351 | |
| 352 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); |
| 353 | POSTING_READ(intel_dp->output_reg); |
| 354 | |
| 355 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 356 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 357 | |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 358 | if (!pll_enabled) { |
Ville Syrjälä | d288f65 | 2014-10-28 13:20:22 +0200 | [diff] [blame] | 359 | vlv_force_pll_off(dev, pipe); |
Ville Syrjälä | 0047eed | 2015-07-10 10:56:24 +0300 | [diff] [blame] | 360 | |
| 361 | if (release_cl_override) |
| 362 | chv_phy_powergate_ch(dev_priv, phy, ch, false); |
| 363 | } |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 364 | } |
| 365 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 366 | static enum pipe |
| 367 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 368 | { |
| 369 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 370 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 371 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 372 | struct intel_encoder *encoder; |
| 373 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 374 | enum pipe pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 375 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 376 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 377 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 378 | /* We should never land here with regular DP ports */ |
| 379 | WARN_ON(!is_edp(intel_dp)); |
| 380 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 381 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 382 | return intel_dp->pps_pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 383 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 384 | /* |
| 385 | * We don't have power sequencer currently. |
| 386 | * Pick one that's not used by other ports. |
| 387 | */ |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 388 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 389 | struct intel_dp *tmp; |
| 390 | |
| 391 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 392 | continue; |
| 393 | |
| 394 | tmp = enc_to_intel_dp(&encoder->base); |
| 395 | |
| 396 | if (tmp->pps_pipe != INVALID_PIPE) |
| 397 | pipes &= ~(1 << tmp->pps_pipe); |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * Didn't find one. This should not happen since there |
| 402 | * are two power sequencers and up to two eDP ports. |
| 403 | */ |
| 404 | if (WARN_ON(pipes == 0)) |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 405 | pipe = PIPE_A; |
| 406 | else |
| 407 | pipe = ffs(pipes) - 1; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 408 | |
Ville Syrjälä | a8c3344 | 2014-10-16 21:29:59 +0300 | [diff] [blame] | 409 | vlv_steal_power_sequencer(dev, pipe); |
| 410 | intel_dp->pps_pipe = pipe; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 411 | |
| 412 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", |
| 413 | pipe_name(intel_dp->pps_pipe), |
| 414 | port_name(intel_dig_port->port)); |
| 415 | |
| 416 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 417 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 418 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 419 | |
Ville Syrjälä | 961a0db | 2014-10-16 21:29:42 +0300 | [diff] [blame] | 420 | /* |
| 421 | * Even vdd force doesn't work until we've made |
| 422 | * the power sequencer lock in on the port. |
| 423 | */ |
| 424 | vlv_power_sequencer_kick(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 425 | |
| 426 | return intel_dp->pps_pipe; |
| 427 | } |
| 428 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 429 | static int |
| 430 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) |
| 431 | { |
| 432 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 433 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 434 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 435 | |
| 436 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 437 | |
| 438 | /* We should never land here with regular DP ports */ |
| 439 | WARN_ON(!is_edp(intel_dp)); |
| 440 | |
| 441 | /* |
| 442 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance |
| 443 | * mapping needs to be retrieved from VBT, for now just hard-code to |
| 444 | * use instance #0 always. |
| 445 | */ |
| 446 | if (!intel_dp->pps_reset) |
| 447 | return 0; |
| 448 | |
| 449 | intel_dp->pps_reset = false; |
| 450 | |
| 451 | /* |
| 452 | * Only the HW needs to be reprogrammed, the SW state is fixed and |
| 453 | * has been setup during connector init. |
| 454 | */ |
| 455 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 456 | |
| 457 | return 0; |
| 458 | } |
| 459 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 460 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
| 461 | enum pipe pipe); |
| 462 | |
| 463 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, |
| 464 | enum pipe pipe) |
| 465 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 466 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, |
| 470 | enum pipe pipe) |
| 471 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 472 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, |
| 476 | enum pipe pipe) |
| 477 | { |
| 478 | return true; |
| 479 | } |
| 480 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 481 | static enum pipe |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 482 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
| 483 | enum port port, |
| 484 | vlv_pipe_check pipe_check) |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 485 | { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 486 | enum pipe pipe; |
| 487 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 488 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 489 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 490 | PANEL_PORT_SELECT_MASK; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 491 | |
| 492 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) |
| 493 | continue; |
| 494 | |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 495 | if (!pipe_check(dev_priv, pipe)) |
| 496 | continue; |
| 497 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 498 | return pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 499 | } |
| 500 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 501 | return INVALID_PIPE; |
| 502 | } |
| 503 | |
| 504 | static void |
| 505 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 506 | { |
| 507 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 508 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 509 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 510 | enum port port = intel_dig_port->port; |
| 511 | |
| 512 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 513 | |
| 514 | /* try to find a pipe with this port selected */ |
Ville Syrjälä | 6491ab2 | 2014-08-18 22:16:06 +0300 | [diff] [blame] | 515 | /* first pick one where the panel is on */ |
| 516 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 517 | vlv_pipe_has_pp_on); |
| 518 | /* didn't find one? pick one where vdd is on */ |
| 519 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 520 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 521 | vlv_pipe_has_vdd_on); |
| 522 | /* didn't find one? pick one with just the correct port */ |
| 523 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 524 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 525 | vlv_pipe_any); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 526 | |
| 527 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 528 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 529 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", |
| 530 | port_name(port)); |
| 531 | return; |
| 532 | } |
| 533 | |
| 534 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
| 535 | port_name(port), pipe_name(intel_dp->pps_pipe)); |
| 536 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 537 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 538 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 539 | } |
| 540 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 541 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 542 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 543 | struct drm_device *dev = &dev_priv->drm; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 544 | struct intel_encoder *encoder; |
| 545 | |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 546 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 547 | !IS_BROXTON(dev))) |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 548 | return; |
| 549 | |
| 550 | /* |
| 551 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 552 | * mutex when power_domain functions are called while holding pps_mutex. |
| 553 | * That also means that in order to use pps_pipe the code needs to |
| 554 | * hold both a power domain reference and pps_mutex, and the power domain |
| 555 | * reference get/put must be done while _not_ holding pps_mutex. |
| 556 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 557 | * should use them always. |
| 558 | */ |
| 559 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 560 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 561 | struct intel_dp *intel_dp; |
| 562 | |
| 563 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 564 | continue; |
| 565 | |
| 566 | intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 7859799 | 2016-06-16 16:37:20 +0300 | [diff] [blame] | 567 | if (IS_BROXTON(dev)) |
| 568 | intel_dp->pps_reset = true; |
| 569 | else |
| 570 | intel_dp->pps_pipe = INVALID_PIPE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 571 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 572 | } |
| 573 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 574 | struct pps_registers { |
| 575 | i915_reg_t pp_ctrl; |
| 576 | i915_reg_t pp_stat; |
| 577 | i915_reg_t pp_on; |
| 578 | i915_reg_t pp_off; |
| 579 | i915_reg_t pp_div; |
| 580 | }; |
| 581 | |
| 582 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, |
| 583 | struct intel_dp *intel_dp, |
| 584 | struct pps_registers *regs) |
| 585 | { |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 586 | int pps_idx = 0; |
| 587 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 588 | memset(regs, 0, sizeof(*regs)); |
| 589 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 590 | if (IS_BROXTON(dev_priv)) |
| 591 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
| 592 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
| 593 | pps_idx = vlv_power_sequencer_pipe(intel_dp); |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 594 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 595 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
| 596 | regs->pp_stat = PP_STATUS(pps_idx); |
| 597 | regs->pp_on = PP_ON_DELAYS(pps_idx); |
| 598 | regs->pp_off = PP_OFF_DELAYS(pps_idx); |
| 599 | if (!IS_BROXTON(dev_priv)) |
| 600 | regs->pp_div = PP_DIVISOR(pps_idx); |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 601 | } |
| 602 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 603 | static i915_reg_t |
| 604 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 605 | { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 606 | struct pps_registers regs; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 607 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 608 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
| 609 | ®s); |
| 610 | |
| 611 | return regs.pp_ctrl; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 612 | } |
| 613 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 614 | static i915_reg_t |
| 615 | _pp_stat_reg(struct intel_dp *intel_dp) |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 616 | { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 617 | struct pps_registers regs; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 618 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 619 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
| 620 | ®s); |
| 621 | |
| 622 | return regs.pp_stat; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 623 | } |
| 624 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 625 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 626 | This function only applicable when panel PM state is not to be tracked */ |
| 627 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 628 | void *unused) |
| 629 | { |
| 630 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), |
| 631 | edp_notifier); |
| 632 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 633 | struct drm_i915_private *dev_priv = to_i915(dev); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 634 | |
| 635 | if (!is_edp(intel_dp) || code != SYS_RESTART) |
| 636 | return 0; |
| 637 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 638 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 639 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 640 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 641 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 642 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 643 | u32 pp_div; |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 644 | |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 645 | pp_ctrl_reg = PP_CONTROL(pipe); |
| 646 | pp_div_reg = PP_DIVISOR(pipe); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 647 | pp_div = I915_READ(pp_div_reg); |
| 648 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
| 649 | |
| 650 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 651 | I915_WRITE(pp_div_reg, pp_div | 0x1F); |
| 652 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 653 | msleep(intel_dp->panel_power_cycle_delay); |
| 654 | } |
| 655 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 656 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 657 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 658 | return 0; |
| 659 | } |
| 660 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 661 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 662 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 663 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 664 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 665 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 666 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 667 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 668 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 669 | intel_dp->pps_pipe == INVALID_PIPE) |
| 670 | return false; |
| 671 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 672 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 673 | } |
| 674 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 675 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 676 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 677 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 678 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 679 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 680 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 681 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 682 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
Ville Syrjälä | 9a42356 | 2014-10-16 21:29:48 +0300 | [diff] [blame] | 683 | intel_dp->pps_pipe == INVALID_PIPE) |
| 684 | return false; |
| 685 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 686 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 687 | } |
| 688 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 689 | static void |
| 690 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 691 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 692 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 693 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 694 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 695 | if (!is_edp(intel_dp)) |
| 696 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 697 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 698 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 699 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 700 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 701 | I915_READ(_pp_stat_reg(intel_dp)), |
| 702 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 703 | } |
| 704 | } |
| 705 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 706 | static uint32_t |
| 707 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 708 | { |
| 709 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 710 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 711 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 712 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 713 | uint32_t status; |
| 714 | bool done; |
| 715 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 716 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 717 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 718 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 719 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 720 | else |
Imre Deak | 713a6b6 | 2016-06-28 13:37:33 +0300 | [diff] [blame] | 721 | done = wait_for(C, 10) == 0; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 722 | if (!done) |
| 723 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 724 | has_aux_irq); |
| 725 | #undef C |
| 726 | |
| 727 | return status; |
| 728 | } |
| 729 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 730 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 731 | { |
| 732 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 733 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 734 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 735 | if (index) |
| 736 | return 0; |
| 737 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 738 | /* |
| 739 | * The clock divider is based off the hrawclk, and would like to run at |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 740 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 741 | */ |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 742 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 743 | } |
| 744 | |
| 745 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 746 | { |
| 747 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 748 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 749 | |
| 750 | if (index) |
| 751 | return 0; |
| 752 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 753 | /* |
| 754 | * The clock divider is based off the cdclk or PCH rawclk, and would |
| 755 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| 756 | * divide by 2000 and use that |
| 757 | */ |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 758 | if (intel_dig_port->port == PORT_A) |
Ville Syrjälä | fce18c4 | 2015-11-30 16:23:46 +0200 | [diff] [blame] | 759 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 760 | else |
| 761 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 765 | { |
| 766 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 767 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 768 | |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 769 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 770 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 771 | switch (index) { |
| 772 | case 0: return 63; |
| 773 | case 1: return 72; |
| 774 | default: return 0; |
| 775 | } |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 776 | } |
Ville Syrjälä | a457f54 | 2016-03-02 17:22:17 +0200 | [diff] [blame] | 777 | |
| 778 | return ilk_get_aux_clock_divider(intel_dp, index); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 779 | } |
| 780 | |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 781 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 782 | { |
| 783 | /* |
| 784 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 785 | * derive the clock from CDCLK automatically). We still implement the |
| 786 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 787 | */ |
| 788 | return index ? 0 : 1; |
| 789 | } |
| 790 | |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 791 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 792 | bool has_aux_irq, |
| 793 | int send_bytes, |
| 794 | uint32_t aux_clock_divider) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 795 | { |
| 796 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 797 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 798 | uint32_t precharge, timeout; |
| 799 | |
| 800 | if (IS_GEN6(dev)) |
| 801 | precharge = 3; |
| 802 | else |
| 803 | precharge = 5; |
| 804 | |
Ville Syrjälä | f3c6a3a | 2015-11-11 20:34:10 +0200 | [diff] [blame] | 805 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 806 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 807 | else |
| 808 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 809 | |
| 810 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 811 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 812 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 813 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 814 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 815 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 816 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 817 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 818 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 819 | } |
| 820 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 821 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 822 | bool has_aux_irq, |
| 823 | int send_bytes, |
| 824 | uint32_t unused) |
| 825 | { |
| 826 | return DP_AUX_CH_CTL_SEND_BUSY | |
| 827 | DP_AUX_CH_CTL_DONE | |
| 828 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
| 829 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 830 | DP_AUX_CH_CTL_TIME_OUT_1600us | |
| 831 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
| 832 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
Daniel Vetter | d4dcbdc | 2016-05-18 18:47:15 +0200 | [diff] [blame] | 833 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 834 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
| 835 | } |
| 836 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 837 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 838 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Daniel Vetter | bd9f74a | 2014-10-02 09:45:35 +0200 | [diff] [blame] | 839 | const uint8_t *send, int send_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 840 | uint8_t *recv, int recv_size) |
| 841 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 842 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 843 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 844 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 845 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 846 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 847 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 848 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 849 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 850 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 851 | bool vdd; |
| 852 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 853 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 854 | |
Ville Syrjälä | 72c3500 | 2014-08-18 22:16:00 +0300 | [diff] [blame] | 855 | /* |
| 856 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 857 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 858 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 859 | * ourselves. |
| 860 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 861 | vdd = edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 862 | |
| 863 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 864 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 865 | * deep sleep states. |
| 866 | */ |
| 867 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 868 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 869 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 870 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 871 | /* Try to wait for any previous AUX channel activity */ |
| 872 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 873 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 874 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 875 | break; |
| 876 | msleep(1); |
| 877 | } |
| 878 | |
| 879 | if (try == 3) { |
Mika Kuoppala | 02196c7 | 2015-08-06 16:48:58 +0300 | [diff] [blame] | 880 | static u32 last_status = -1; |
| 881 | const u32 status = I915_READ(ch_ctl); |
| 882 | |
| 883 | if (status != last_status) { |
| 884 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 885 | status); |
| 886 | last_status = status; |
| 887 | } |
| 888 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 889 | ret = -EBUSY; |
| 890 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 891 | } |
| 892 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 893 | /* Only 5 data registers! */ |
| 894 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 895 | ret = -E2BIG; |
| 896 | goto out; |
| 897 | } |
| 898 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 899 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 900 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 901 | has_aux_irq, |
| 902 | send_bytes, |
| 903 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 904 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 905 | /* Must try at least 3 times according to DP spec */ |
| 906 | for (try = 0; try < 5; try++) { |
| 907 | /* Load the send data into the aux channel data registers */ |
| 908 | for (i = 0; i < send_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 909 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 910 | intel_dp_pack_aux(send + i, |
| 911 | send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 912 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 913 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 914 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 915 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 916 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 917 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 918 | /* Clear done status and any errors */ |
| 919 | I915_WRITE(ch_ctl, |
| 920 | status | |
| 921 | DP_AUX_CH_CTL_DONE | |
| 922 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 923 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 924 | |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 925 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 926 | continue; |
Todd Previte | 74ebf29 | 2015-04-15 08:38:41 -0700 | [diff] [blame] | 927 | |
| 928 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 929 | * 400us delay required for errors and timeouts |
| 930 | * Timeout errors from the HW already meet this |
| 931 | * requirement so skip to next iteration |
| 932 | */ |
| 933 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
| 934 | usleep_range(400, 500); |
| 935 | continue; |
| 936 | } |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 937 | if (status & DP_AUX_CH_CTL_DONE) |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 938 | goto done; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 939 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 940 | } |
| 941 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 942 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 943 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 944 | ret = -EBUSY; |
| 945 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 946 | } |
| 947 | |
Jim Bride | e058c94 | 2015-05-27 10:21:48 -0700 | [diff] [blame] | 948 | done: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 949 | /* Check for timeout or receive error. |
| 950 | * Timeouts occur when the sink is not connected |
| 951 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 952 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 953 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 954 | ret = -EIO; |
| 955 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 956 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 957 | |
| 958 | /* Timeouts occur when the device isn't connected, so they're |
| 959 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 960 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 961 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 962 | ret = -ETIMEDOUT; |
| 963 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 964 | } |
| 965 | |
| 966 | /* Unload any bytes sent back from the other side */ |
| 967 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 968 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Rodrigo Vivi | 14e0188 | 2015-12-10 11:12:27 -0800 | [diff] [blame] | 969 | |
| 970 | /* |
| 971 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 972 | * We have no idea of what happened so we return -EBUSY so |
| 973 | * drm layer takes care for the necessary retries. |
| 974 | */ |
| 975 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 976 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", |
| 977 | recv_bytes); |
| 978 | /* |
| 979 | * FIXME: This patch was created on top of a series that |
| 980 | * organize the retries at drm level. There EBUSY should |
| 981 | * also take care for 1ms wait before retrying. |
| 982 | * That aux retries re-org is still needed and after that is |
| 983 | * merged we remove this sleep from here. |
| 984 | */ |
| 985 | usleep_range(1000, 1500); |
| 986 | ret = -EBUSY; |
| 987 | goto out; |
| 988 | } |
| 989 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 990 | if (recv_bytes > recv_size) |
| 991 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 992 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 993 | for (i = 0; i < recv_bytes; i += 4) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 994 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
Rodrigo Vivi | a4f1289 | 2014-11-14 08:52:27 -0800 | [diff] [blame] | 995 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 996 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 997 | ret = recv_bytes; |
| 998 | out: |
| 999 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 1000 | |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 1001 | if (vdd) |
| 1002 | edp_panel_vdd_off(intel_dp, false); |
| 1003 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1004 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1005 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1006 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1007 | } |
| 1008 | |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1009 | #define BARE_ADDRESS_SIZE 3 |
| 1010 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1011 | static ssize_t |
| 1012 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1013 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1014 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 1015 | uint8_t txbuf[20], rxbuf[20]; |
| 1016 | size_t txsize, rxsize; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1017 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1018 | |
Ville Syrjälä | d2d9cbb | 2015-03-19 11:44:06 +0200 | [diff] [blame] | 1019 | txbuf[0] = (msg->request << 4) | |
| 1020 | ((msg->address >> 16) & 0xf); |
| 1021 | txbuf[1] = (msg->address >> 8) & 0xff; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1022 | txbuf[2] = msg->address & 0xff; |
| 1023 | txbuf[3] = msg->size - 1; |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 1024 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1025 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 1026 | case DP_AUX_NATIVE_WRITE: |
| 1027 | case DP_AUX_I2C_WRITE: |
Ville Syrjälä | c1e74122 | 2015-08-27 17:23:27 +0300 | [diff] [blame] | 1028 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1029 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 1030 | rxsize = 2; /* 0 or 1 data bytes */ |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1031 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1032 | if (WARN_ON(txsize > 20)) |
| 1033 | return -E2BIG; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1034 | |
Ville Syrjälä | dd788090 | 2016-07-28 17:55:04 +0300 | [diff] [blame] | 1035 | WARN_ON(!msg->buffer != !msg->size); |
| 1036 | |
Imre Deak | d81a67c | 2016-01-29 14:52:26 +0200 | [diff] [blame] | 1037 | if (msg->buffer) |
| 1038 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1039 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1040 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1041 | if (ret > 0) { |
| 1042 | msg->reply = rxbuf[0] >> 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1043 | |
Jani Nikula | a1ddefd | 2015-03-17 17:18:54 +0200 | [diff] [blame] | 1044 | if (ret > 1) { |
| 1045 | /* Number of bytes written in a short write. */ |
| 1046 | ret = clamp_t(int, rxbuf[1], 0, msg->size); |
| 1047 | } else { |
| 1048 | /* Return payload size. */ |
| 1049 | ret = msg->size; |
| 1050 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1051 | } |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1052 | break; |
| 1053 | |
| 1054 | case DP_AUX_NATIVE_READ: |
| 1055 | case DP_AUX_I2C_READ: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 1056 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1057 | rxsize = msg->size + 1; |
| 1058 | |
| 1059 | if (WARN_ON(rxsize > 20)) |
| 1060 | return -E2BIG; |
| 1061 | |
| 1062 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 1063 | if (ret > 0) { |
| 1064 | msg->reply = rxbuf[0] >> 4; |
| 1065 | /* |
| 1066 | * Assume happy day, and copy the data. The caller is |
| 1067 | * expected to check msg->reply before touching it. |
| 1068 | * |
| 1069 | * Return payload size. |
| 1070 | */ |
| 1071 | ret--; |
| 1072 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 1073 | } |
| 1074 | break; |
| 1075 | |
| 1076 | default: |
| 1077 | ret = -EINVAL; |
| 1078 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1079 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 1080 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1081 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1082 | } |
| 1083 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1084 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1085 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1086 | { |
| 1087 | switch (port) { |
| 1088 | case PORT_B: |
| 1089 | case PORT_C: |
| 1090 | case PORT_D: |
| 1091 | return DP_AUX_CH_CTL(port); |
| 1092 | default: |
| 1093 | MISSING_CASE(port); |
| 1094 | return DP_AUX_CH_CTL(PORT_B); |
| 1095 | } |
| 1096 | } |
| 1097 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1098 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1099 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1100 | { |
| 1101 | switch (port) { |
| 1102 | case PORT_B: |
| 1103 | case PORT_C: |
| 1104 | case PORT_D: |
| 1105 | return DP_AUX_CH_DATA(port, index); |
| 1106 | default: |
| 1107 | MISSING_CASE(port); |
| 1108 | return DP_AUX_CH_DATA(PORT_B, index); |
| 1109 | } |
| 1110 | } |
| 1111 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1112 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1113 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1114 | { |
| 1115 | switch (port) { |
| 1116 | case PORT_A: |
| 1117 | return DP_AUX_CH_CTL(port); |
| 1118 | case PORT_B: |
| 1119 | case PORT_C: |
| 1120 | case PORT_D: |
| 1121 | return PCH_DP_AUX_CH_CTL(port); |
| 1122 | default: |
| 1123 | MISSING_CASE(port); |
| 1124 | return DP_AUX_CH_CTL(PORT_A); |
| 1125 | } |
| 1126 | } |
| 1127 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1128 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1129 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1130 | { |
| 1131 | switch (port) { |
| 1132 | case PORT_A: |
| 1133 | return DP_AUX_CH_DATA(port, index); |
| 1134 | case PORT_B: |
| 1135 | case PORT_C: |
| 1136 | case PORT_D: |
| 1137 | return PCH_DP_AUX_CH_DATA(port, index); |
| 1138 | default: |
| 1139 | MISSING_CASE(port); |
| 1140 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1141 | } |
| 1142 | } |
| 1143 | |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1144 | /* |
| 1145 | * On SKL we don't have Aux for port E so we rely |
| 1146 | * on VBT to set a proper alternate aux channel. |
| 1147 | */ |
| 1148 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) |
| 1149 | { |
| 1150 | const struct ddi_vbt_port_info *info = |
| 1151 | &dev_priv->vbt.ddi_port_info[PORT_E]; |
| 1152 | |
| 1153 | switch (info->alternate_aux_channel) { |
| 1154 | case DP_AUX_A: |
| 1155 | return PORT_A; |
| 1156 | case DP_AUX_B: |
| 1157 | return PORT_B; |
| 1158 | case DP_AUX_C: |
| 1159 | return PORT_C; |
| 1160 | case DP_AUX_D: |
| 1161 | return PORT_D; |
| 1162 | default: |
| 1163 | MISSING_CASE(info->alternate_aux_channel); |
| 1164 | return PORT_A; |
| 1165 | } |
| 1166 | } |
| 1167 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1168 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1169 | enum port port) |
Ville Syrjälä | da00bdc | 2015-11-11 20:34:13 +0200 | [diff] [blame] | 1170 | { |
| 1171 | if (port == PORT_E) |
| 1172 | port = skl_porte_aux_port(dev_priv); |
| 1173 | |
| 1174 | switch (port) { |
| 1175 | case PORT_A: |
| 1176 | case PORT_B: |
| 1177 | case PORT_C: |
| 1178 | case PORT_D: |
| 1179 | return DP_AUX_CH_CTL(port); |
| 1180 | default: |
| 1181 | MISSING_CASE(port); |
| 1182 | return DP_AUX_CH_CTL(PORT_A); |
| 1183 | } |
| 1184 | } |
| 1185 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1186 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1187 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1188 | { |
| 1189 | if (port == PORT_E) |
| 1190 | port = skl_porte_aux_port(dev_priv); |
| 1191 | |
| 1192 | switch (port) { |
| 1193 | case PORT_A: |
| 1194 | case PORT_B: |
| 1195 | case PORT_C: |
| 1196 | case PORT_D: |
| 1197 | return DP_AUX_CH_DATA(port, index); |
| 1198 | default: |
| 1199 | MISSING_CASE(port); |
| 1200 | return DP_AUX_CH_DATA(PORT_A, index); |
| 1201 | } |
| 1202 | } |
| 1203 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1204 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
| 1205 | enum port port) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1206 | { |
| 1207 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1208 | return skl_aux_ctl_reg(dev_priv, port); |
| 1209 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1210 | return ilk_aux_ctl_reg(dev_priv, port); |
| 1211 | else |
| 1212 | return g4x_aux_ctl_reg(dev_priv, port); |
| 1213 | } |
| 1214 | |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1215 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
| 1216 | enum port port, int index) |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1217 | { |
| 1218 | if (INTEL_INFO(dev_priv)->gen >= 9) |
| 1219 | return skl_aux_data_reg(dev_priv, port, index); |
| 1220 | else if (HAS_PCH_SPLIT(dev_priv)) |
| 1221 | return ilk_aux_data_reg(dev_priv, port, index); |
| 1222 | else |
| 1223 | return g4x_aux_data_reg(dev_priv, port, index); |
| 1224 | } |
| 1225 | |
| 1226 | static void intel_aux_reg_init(struct intel_dp *intel_dp) |
| 1227 | { |
| 1228 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
| 1229 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1230 | int i; |
| 1231 | |
| 1232 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); |
| 1233 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) |
| 1234 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); |
| 1235 | } |
| 1236 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1237 | static void |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1238 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1239 | { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1240 | kfree(intel_dp->aux.name); |
| 1241 | } |
| 1242 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1243 | static void |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1244 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1245 | { |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 1246 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1247 | enum port port = intel_dig_port->port; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1248 | |
Ville Syrjälä | 330e20e | 2015-11-11 20:34:14 +0200 | [diff] [blame] | 1249 | intel_aux_reg_init(intel_dp); |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1250 | drm_dp_aux_init(&intel_dp->aux); |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 1251 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 1252 | /* Failure to allocate our preferred name is not critical */ |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 1253 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1254 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1255 | } |
| 1256 | |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1257 | static int |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1258 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1259 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1260 | if (intel_dp->num_sink_rates) { |
| 1261 | *sink_rates = intel_dp->sink_rates; |
| 1262 | return intel_dp->num_sink_rates; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1263 | } |
Ville Syrjälä | 12f6a2e | 2015-03-12 17:10:30 +0200 | [diff] [blame] | 1264 | |
| 1265 | *sink_rates = default_rates; |
| 1266 | |
| 1267 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; |
Sonika Jindal | fc0f8e2 | 2015-03-05 10:03:58 +0530 | [diff] [blame] | 1268 | } |
| 1269 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1270 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1271 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1272 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1273 | struct drm_device *dev = dig_port->base.base.dev; |
| 1274 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1275 | /* WaDisableHBR2:skl */ |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 1276 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1277 | return false; |
| 1278 | |
| 1279 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || |
| 1280 | (INTEL_INFO(dev)->gen >= 9)) |
| 1281 | return true; |
| 1282 | else |
| 1283 | return false; |
| 1284 | } |
| 1285 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1286 | static int |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1287 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1288 | { |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1289 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1290 | struct drm_device *dev = dig_port->base.base.dev; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1291 | int size; |
| 1292 | |
Sonika Jindal | 64987fc | 2015-05-26 17:50:13 +0530 | [diff] [blame] | 1293 | if (IS_BROXTON(dev)) { |
| 1294 | *source_rates = bxt_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1295 | size = ARRAY_SIZE(bxt_rates); |
Rodrigo Vivi | ef11bdb | 2015-10-28 04:16:45 -0700 | [diff] [blame] | 1296 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
Sonika Jindal | 637a9c6 | 2015-05-07 09:52:08 +0530 | [diff] [blame] | 1297 | *source_rates = skl_rates; |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1298 | size = ARRAY_SIZE(skl_rates); |
| 1299 | } else { |
| 1300 | *source_rates = default_rates; |
| 1301 | size = ARRAY_SIZE(default_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1302 | } |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1303 | |
Thulasimani,Sivakumar | ed63baa | 2015-08-18 15:30:37 +0530 | [diff] [blame] | 1304 | /* This depends on the fact that 5.4 is last value in the array */ |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1305 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1306 | size--; |
Ville Syrjälä | 636280b | 2015-03-12 17:10:29 +0200 | [diff] [blame] | 1307 | |
Thulasimani,Sivakumar | af7080f | 2015-08-18 11:07:59 +0530 | [diff] [blame] | 1308 | return size; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1309 | } |
| 1310 | |
Daniel Vetter | 0e50338 | 2014-07-04 11:26:04 -0300 | [diff] [blame] | 1311 | static void |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1312 | intel_dp_set_clock(struct intel_encoder *encoder, |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1313 | struct intel_crtc_state *pipe_config) |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1314 | { |
| 1315 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1316 | const struct dp_link_dpll *divisor = NULL; |
| 1317 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1318 | |
| 1319 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1320 | divisor = gen4_dpll; |
| 1321 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1322 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1323 | divisor = pch_dpll; |
| 1324 | count = ARRAY_SIZE(pch_dpll); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 1325 | } else if (IS_CHERRYVIEW(dev)) { |
| 1326 | divisor = chv_dpll; |
| 1327 | count = ARRAY_SIZE(chv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1328 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 1329 | divisor = vlv_dpll; |
| 1330 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1331 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1332 | |
| 1333 | if (divisor && count) { |
| 1334 | for (i = 0; i < count; i++) { |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1335 | if (pipe_config->port_clock == divisor[i].clock) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 1336 | pipe_config->dpll = divisor[i].dpll; |
| 1337 | pipe_config->clock_set = true; |
| 1338 | break; |
| 1339 | } |
| 1340 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1341 | } |
| 1342 | } |
| 1343 | |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1344 | static int intersect_rates(const int *source_rates, int source_len, |
| 1345 | const int *sink_rates, int sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1346 | int *common_rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1347 | { |
| 1348 | int i = 0, j = 0, k = 0; |
| 1349 | |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1350 | while (i < source_len && j < sink_len) { |
| 1351 | if (source_rates[i] == sink_rates[j]) { |
Ville Syrjälä | e6bda3e | 2015-03-12 17:10:37 +0200 | [diff] [blame] | 1352 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
| 1353 | return k; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1354 | common_rates[k] = source_rates[i]; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1355 | ++k; |
| 1356 | ++i; |
| 1357 | ++j; |
| 1358 | } else if (source_rates[i] < sink_rates[j]) { |
| 1359 | ++i; |
| 1360 | } else { |
| 1361 | ++j; |
| 1362 | } |
| 1363 | } |
| 1364 | return k; |
| 1365 | } |
| 1366 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1367 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
| 1368 | int *common_rates) |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1369 | { |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1370 | const int *source_rates, *sink_rates; |
| 1371 | int source_len, sink_len; |
| 1372 | |
| 1373 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1374 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1375 | |
| 1376 | return intersect_rates(source_rates, source_len, |
| 1377 | sink_rates, sink_len, |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1378 | common_rates); |
Ville Syrjälä | 2ecae76 | 2015-03-12 17:10:33 +0200 | [diff] [blame] | 1379 | } |
| 1380 | |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1381 | static void snprintf_int_array(char *str, size_t len, |
| 1382 | const int *array, int nelem) |
| 1383 | { |
| 1384 | int i; |
| 1385 | |
| 1386 | str[0] = '\0'; |
| 1387 | |
| 1388 | for (i = 0; i < nelem; i++) { |
Jani Nikula | b2f505b | 2015-05-18 16:01:45 +0300 | [diff] [blame] | 1389 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1390 | if (r >= len) |
| 1391 | return; |
| 1392 | str += r; |
| 1393 | len -= r; |
| 1394 | } |
| 1395 | } |
| 1396 | |
| 1397 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1398 | { |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1399 | const int *source_rates, *sink_rates; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1400 | int source_len, sink_len, common_len; |
| 1401 | int common_rates[DP_MAX_SUPPORTED_RATES]; |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1402 | char str[128]; /* FIXME: too big for stack? */ |
| 1403 | |
| 1404 | if ((drm_debug & DRM_UT_KMS) == 0) |
| 1405 | return; |
| 1406 | |
Ander Conselvan de Oliveira | e588fa1 | 2015-10-23 13:01:50 +0300 | [diff] [blame] | 1407 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1408 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
| 1409 | DRM_DEBUG_KMS("source rates: %s\n", str); |
| 1410 | |
| 1411 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); |
| 1412 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); |
| 1413 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
| 1414 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1415 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
| 1416 | snprintf_int_array(str, sizeof(str), common_rates, common_len); |
| 1417 | DRM_DEBUG_KMS("common rates: %s\n", str); |
Ville Syrjälä | 0336400e | 2015-03-12 17:10:39 +0200 | [diff] [blame] | 1418 | } |
| 1419 | |
Ville Syrjälä | f4896f1 | 2015-03-12 17:10:27 +0200 | [diff] [blame] | 1420 | static int rate_to_index(int find, const int *rates) |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1421 | { |
| 1422 | int i = 0; |
| 1423 | |
| 1424 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) |
| 1425 | if (find == rates[i]) |
| 1426 | break; |
| 1427 | |
| 1428 | return i; |
| 1429 | } |
| 1430 | |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1431 | int |
| 1432 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1433 | { |
| 1434 | int rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1435 | int len; |
| 1436 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1437 | len = intel_dp_common_rates(intel_dp, rates); |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1438 | if (WARN_ON(len <= 0)) |
| 1439 | return 162000; |
| 1440 | |
Ville Syrjälä | 1354f73 | 2016-07-28 17:50:45 +0300 | [diff] [blame] | 1441 | return rates[len - 1]; |
Ville Syrjälä | 50fec21 | 2015-03-12 17:10:34 +0200 | [diff] [blame] | 1442 | } |
| 1443 | |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1444 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1445 | { |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1446 | return rate_to_index(rate, intel_dp->sink_rates); |
Ville Syrjälä | ed4e9c1 | 2015-03-12 17:10:36 +0200 | [diff] [blame] | 1447 | } |
| 1448 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 1449 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1450 | uint8_t *link_bw, uint8_t *rate_select) |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1451 | { |
| 1452 | if (intel_dp->num_sink_rates) { |
| 1453 | *link_bw = 0; |
| 1454 | *rate_select = |
| 1455 | intel_dp_rate_select(intel_dp, port_clock); |
| 1456 | } else { |
| 1457 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1458 | *rate_select = 0; |
| 1459 | } |
| 1460 | } |
| 1461 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 1462 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1463 | intel_dp_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 1464 | struct intel_crtc_state *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1465 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1466 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1467 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 1468 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1469 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1470 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ander Conselvan de Oliveira | 84556d5 | 2015-03-20 16:18:10 +0200 | [diff] [blame] | 1471 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1472 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1473 | int lane_count, clock; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1474 | int min_lane_count = 1; |
Paulo Zanoni | eeb6324 | 2014-05-06 14:56:50 +0300 | [diff] [blame] | 1475 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 1476 | /* Conveniently, the link BW constants become indices with a shift...*/ |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1477 | int min_clock = 0; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1478 | int max_clock; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1479 | int bpp, mode_rate; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1480 | int link_avail, link_clock; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1481 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
| 1482 | int common_len; |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1483 | uint8_t link_bw, rate_select; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1484 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1485 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1486 | |
| 1487 | /* No common link rates between source and sink */ |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1488 | WARN_ON(common_len <= 0); |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1489 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1490 | max_clock = common_len - 1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1491 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1492 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 1493 | pipe_config->has_pch_encoder = true; |
| 1494 | |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1495 | pipe_config->has_drrs = false; |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 1496 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1497 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 1498 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 1499 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 1500 | adjusted_mode); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1501 | |
| 1502 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1503 | int ret; |
Maarten Lankhorst | e435d6e | 2015-07-13 16:30:15 +0200 | [diff] [blame] | 1504 | ret = skl_update_scaler_crtc(pipe_config); |
Chandra Konduru | a1b2278 | 2015-04-07 15:28:45 -0700 | [diff] [blame] | 1505 | if (ret) |
| 1506 | return ret; |
| 1507 | } |
| 1508 | |
Matt Roper | b5667627 | 2015-11-04 09:05:27 -0800 | [diff] [blame] | 1509 | if (HAS_GMCH_DISPLAY(dev)) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 1510 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 1511 | intel_connector->panel.fitting_mode); |
| 1512 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 1513 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 1514 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 1515 | } |
| 1516 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 1517 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 1518 | return false; |
| 1519 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1520 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1521 | "max bw %d pixel clock %iKHz\n", |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1522 | max_lane_count, common_rates[max_clock], |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1523 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 1524 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1525 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 1526 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 1527 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1528 | if (is_edp(intel_dp)) { |
Thulasimani,Sivakumar | 22ce562 | 2015-07-31 11:05:27 +0530 | [diff] [blame] | 1529 | |
| 1530 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 1531 | if (intel_connector->base.display_info.bpc == 0 && |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1532 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1533 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 1534 | dev_priv->vbt.edp.bpp); |
| 1535 | bpp = dev_priv->vbt.edp.bpp; |
Jani Nikula | 56071a2 | 2014-05-06 14:56:52 +0300 | [diff] [blame] | 1536 | } |
| 1537 | |
Jani Nikula | 344c5bb | 2014-09-09 11:25:13 +0300 | [diff] [blame] | 1538 | /* |
| 1539 | * Use the maximum clock and number of lanes the eDP panel |
| 1540 | * advertizes being capable of. The panels are generally |
| 1541 | * designed to support only a single clock and lane |
| 1542 | * configuration, and typically these values correspond to the |
| 1543 | * native resolution of the panel. |
| 1544 | */ |
| 1545 | min_lane_count = max_lane_count; |
| 1546 | min_clock = max_clock; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 1547 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1548 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1549 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1550 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 1551 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1552 | |
Dave Airlie | c693099 | 2014-07-14 11:04:39 +1000 | [diff] [blame] | 1553 | for (clock = min_clock; clock <= max_clock; clock++) { |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1554 | for (lane_count = min_lane_count; |
| 1555 | lane_count <= max_lane_count; |
| 1556 | lane_count <<= 1) { |
| 1557 | |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1558 | link_clock = common_rates[clock]; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1559 | link_avail = intel_dp_max_data_rate(link_clock, |
| 1560 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 1561 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1562 | if (mode_rate <= link_avail) { |
| 1563 | goto found; |
| 1564 | } |
| 1565 | } |
| 1566 | } |
| 1567 | } |
| 1568 | |
| 1569 | return false; |
| 1570 | |
| 1571 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1572 | if (intel_dp->color_range_auto) { |
| 1573 | /* |
| 1574 | * See: |
| 1575 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 1576 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 1577 | */ |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1578 | pipe_config->limited_color_range = |
| 1579 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; |
| 1580 | } else { |
| 1581 | pipe_config->limited_color_range = |
| 1582 | intel_dp->limited_color_range; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 1583 | } |
| 1584 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1585 | pipe_config->lane_count = lane_count; |
Sonika Jindal | a8f3ef6 | 2015-03-05 10:02:30 +0530 | [diff] [blame] | 1586 | |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 1587 | pipe_config->pipe_bpp = bpp; |
Ville Syrjälä | 94ca719 | 2015-03-13 19:40:31 +0200 | [diff] [blame] | 1588 | pipe_config->port_clock = common_rates[clock]; |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 1589 | |
Ville Syrjälä | 04a60f9 | 2015-07-06 15:10:06 +0300 | [diff] [blame] | 1590 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
| 1591 | &link_bw, &rate_select); |
| 1592 | |
| 1593 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", |
| 1594 | link_bw, rate_select, pipe_config->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 1595 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1596 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 1597 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1598 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1599 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1600 | adjusted_mode->crtc_clock, |
| 1601 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 1602 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1603 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1604 | if (intel_connector->panel.downclock_mode != NULL && |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 1605 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
Vandana Kannan | f769cd2 | 2014-08-05 07:51:22 -0700 | [diff] [blame] | 1606 | pipe_config->has_drrs = true; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 1607 | intel_link_compute_m_n(bpp, lane_count, |
| 1608 | intel_connector->panel.downclock_mode->clock, |
| 1609 | pipe_config->port_clock, |
| 1610 | &pipe_config->dp_m2_n2); |
| 1611 | } |
| 1612 | |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1613 | /* |
| 1614 | * DPLL0 VCO may need to be adjusted to get the correct |
| 1615 | * clock for eDP. This will affect cdclk as well. |
| 1616 | */ |
| 1617 | if (is_edp(intel_dp) && |
| 1618 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { |
| 1619 | int vco; |
| 1620 | |
| 1621 | switch (pipe_config->port_clock / 2) { |
| 1622 | case 108000: |
| 1623 | case 216000: |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 1624 | vco = 8640000; |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1625 | break; |
| 1626 | default: |
Ville Syrjälä | 63911d7 | 2016-05-13 23:41:32 +0300 | [diff] [blame] | 1627 | vco = 8100000; |
Ville Syrjälä | 14d41b3 | 2016-05-13 23:41:22 +0300 | [diff] [blame] | 1628 | break; |
| 1629 | } |
| 1630 | |
| 1631 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; |
| 1632 | } |
| 1633 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1634 | if (!HAS_DDI(dev)) |
Ville Syrjälä | 840b32b | 2015-08-11 20:21:46 +0300 | [diff] [blame] | 1635 | intel_dp_set_clock(encoder, pipe_config); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 1636 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 1637 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1638 | } |
| 1639 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1640 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 1641 | const struct intel_crtc_state *pipe_config) |
| 1642 | { |
| 1643 | intel_dp->link_rate = pipe_config->port_clock; |
| 1644 | intel_dp->lane_count = pipe_config->lane_count; |
Ville Syrjälä | 64ee2fd | 2016-07-28 17:50:39 +0300 | [diff] [blame] | 1645 | intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1646 | } |
| 1647 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 1648 | static void intel_dp_prepare(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1649 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1650 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1651 | struct drm_i915_private *dev_priv = to_i915(dev); |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1652 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1653 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 1654 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 1655 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1656 | |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 1657 | intel_dp_set_link_params(intel_dp, crtc->config); |
| 1658 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1659 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1660 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1661 | * |
| 1662 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1663 | * SNB CPU |
| 1664 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1665 | * CPT PCH |
| 1666 | * |
| 1667 | * IBX PCH and CPU are the same for almost everything, |
| 1668 | * except that the CPU DP PLL is configured in this |
| 1669 | * register |
| 1670 | * |
| 1671 | * CPT PCH is quite different, having many bits moved |
| 1672 | * to the TRANS_DP_CTL register instead. That |
| 1673 | * configuration happens (oddly) in ironlake_pch_enable |
| 1674 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 1675 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1676 | /* Preserve the BIOS-computed detected bit. This is |
| 1677 | * supposed to be read-only. |
| 1678 | */ |
| 1679 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1680 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1681 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1682 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 1683 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1684 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1685 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1686 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1687 | if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1688 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1689 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1690 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1691 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1692 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 1693 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1694 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1695 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1696 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 1697 | intel_dp->DP |= crtc->pipe << 29; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1698 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1699 | u32 trans_dp; |
| 1700 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1701 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Ville Syrjälä | e3ef447 | 2015-05-05 17:17:31 +0300 | [diff] [blame] | 1702 | |
| 1703 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1704 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 1705 | trans_dp |= TRANS_DP_ENH_FRAMING; |
| 1706 | else |
| 1707 | trans_dp &= ~TRANS_DP_ENH_FRAMING; |
| 1708 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1709 | } else { |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1710 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 1711 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 1712 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1713 | |
| 1714 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1715 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 1716 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1717 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 1718 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 1719 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 1720 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1721 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 1722 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1723 | if (IS_CHERRYVIEW(dev)) |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 1724 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 1725 | else if (crtc->pipe == PIPE_B) |
| 1726 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1727 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1728 | } |
| 1729 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1730 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1731 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1732 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1733 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1734 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1735 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1736 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1737 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1738 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 1739 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
| 1740 | struct intel_dp *intel_dp); |
| 1741 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1742 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1743 | u32 mask, |
| 1744 | u32 value) |
| 1745 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1746 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1747 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1748 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1749 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1750 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1751 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 1752 | intel_pps_verify_state(dev_priv, intel_dp); |
| 1753 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1754 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1755 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1756 | |
| 1757 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1758 | mask, value, |
| 1759 | I915_READ(pp_stat_reg), |
| 1760 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1761 | |
Chris Wilson | 9036ff0 | 2016-06-30 15:33:09 +0100 | [diff] [blame] | 1762 | if (intel_wait_for_register(dev_priv, |
| 1763 | pp_stat_reg, mask, value, |
| 1764 | 5000)) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1765 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1766 | I915_READ(pp_stat_reg), |
| 1767 | I915_READ(pp_ctrl_reg)); |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1768 | |
| 1769 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1770 | } |
| 1771 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1772 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1773 | { |
| 1774 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1775 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1776 | } |
| 1777 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1778 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1779 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1780 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1781 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1782 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1783 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1784 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1785 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1786 | ktime_t panel_power_on_time; |
| 1787 | s64 panel_power_off_duration; |
| 1788 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1789 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1790 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1791 | /* take the difference of currrent time and panel power off time |
| 1792 | * and then make panel wait for t11_t12 if needed. */ |
| 1793 | panel_power_on_time = ktime_get_boottime(); |
| 1794 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| 1795 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1796 | /* When we disable the VDD override bit last we have to do the manual |
| 1797 | * wait. */ |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1798 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| 1799 | wait_remaining_ms_from_jiffies(jiffies, |
| 1800 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1801 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1802 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1803 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1804 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1805 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1806 | { |
| 1807 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1808 | intel_dp->backlight_on_delay); |
| 1809 | } |
| 1810 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1811 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1812 | { |
| 1813 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1814 | intel_dp->backlight_off_delay); |
| 1815 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1816 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1817 | /* Read the current pp_control value, unlocking the register if it |
| 1818 | * is locked |
| 1819 | */ |
| 1820 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1821 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1822 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1823 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1824 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1825 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1826 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1827 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1828 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1829 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 1830 | if (!IS_BROXTON(dev)) { |
| 1831 | control &= ~PANEL_UNLOCK_MASK; |
| 1832 | control |= PANEL_UNLOCK_REGS; |
| 1833 | } |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1834 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1835 | } |
| 1836 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1837 | /* |
| 1838 | * Must be paired with edp_panel_vdd_off(). |
| 1839 | * Must hold pps_mutex around the whole on/off sequence. |
| 1840 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1841 | */ |
Ville Syrjälä | 1e0560e | 2014-08-19 13:24:25 +0300 | [diff] [blame] | 1842 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1843 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1844 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1845 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1846 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1847 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1848 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1849 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1850 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1851 | bool need_to_disable = !intel_dp->want_panel_vdd; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1852 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1853 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1854 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1855 | if (!is_edp(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1856 | return false; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1857 | |
Egbert Eich | 2c623c1 | 2014-11-25 12:54:57 +0100 | [diff] [blame] | 1858 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1859 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1860 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1861 | if (edp_have_panel_vdd(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1862 | return need_to_disable; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1863 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1864 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1865 | intel_display_power_get(dev_priv, power_domain); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1866 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1867 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
| 1868 | port_name(intel_dig_port->port)); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1869 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1870 | if (!edp_have_panel_power(intel_dp)) |
| 1871 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1872 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1873 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1874 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1875 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1876 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1877 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1878 | |
| 1879 | I915_WRITE(pp_ctrl_reg, pp); |
| 1880 | POSTING_READ(pp_ctrl_reg); |
| 1881 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1882 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1883 | /* |
| 1884 | * If the panel wasn't on, delay before accessing aux channel |
| 1885 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1886 | if (!edp_have_panel_power(intel_dp)) { |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1887 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
| 1888 | port_name(intel_dig_port->port)); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1889 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1890 | } |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1891 | |
| 1892 | return need_to_disable; |
| 1893 | } |
| 1894 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1895 | /* |
| 1896 | * Must be paired with intel_edp_panel_vdd_off() or |
| 1897 | * intel_edp_panel_off(). |
| 1898 | * Nested calls to these functions are not allowed since |
| 1899 | * we drop the lock. Caller must use some higher level |
| 1900 | * locking to prevent nested calls from other threads. |
| 1901 | */ |
Daniel Vetter | b80d6c7 | 2014-03-19 15:54:37 +0100 | [diff] [blame] | 1902 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1903 | { |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1904 | bool vdd; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1905 | |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1906 | if (!is_edp(intel_dp)) |
| 1907 | return; |
| 1908 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1909 | pps_lock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1910 | vdd = edp_panel_vdd_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1911 | pps_unlock(intel_dp); |
Ville Syrjälä | c695b6b | 2014-08-18 22:16:03 +0300 | [diff] [blame] | 1912 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1913 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1914 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1915 | } |
| 1916 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1917 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1918 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1919 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1920 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1921 | struct intel_digital_port *intel_dig_port = |
| 1922 | dp_to_dig_port(intel_dp); |
| 1923 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1924 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1925 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 1926 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1927 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1928 | lockdep_assert_held(&dev_priv->pps_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1929 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1930 | WARN_ON(intel_dp->want_panel_vdd); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1931 | |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1932 | if (!edp_have_panel_vdd(intel_dp)) |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1933 | return; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1934 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1935 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
| 1936 | port_name(intel_dig_port->port)); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1937 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1938 | pp = ironlake_get_pp_control(intel_dp); |
| 1939 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1940 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1941 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1942 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1943 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1944 | I915_WRITE(pp_ctrl_reg, pp); |
| 1945 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 1946 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1947 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1948 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1949 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1950 | |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1951 | if ((pp & POWER_TARGET_ON) == 0) |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 1952 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1953 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 1954 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Ville Syrjälä | be2c919 | 2014-08-18 22:16:01 +0300 | [diff] [blame] | 1955 | intel_display_power_put(dev_priv, power_domain); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1956 | } |
| 1957 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1958 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1959 | { |
| 1960 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1961 | struct intel_dp, panel_vdd_work); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1962 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1963 | pps_lock(intel_dp); |
Ville Syrjälä | 15e899a | 2014-08-18 22:16:02 +0300 | [diff] [blame] | 1964 | if (!intel_dp->want_panel_vdd) |
| 1965 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 1966 | pps_unlock(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1967 | } |
| 1968 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 1969 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 1970 | { |
| 1971 | unsigned long delay; |
| 1972 | |
| 1973 | /* |
| 1974 | * Queue the timer to fire a long time from now (relative to the power |
| 1975 | * down delay) to keep the panel power up across a sequence of |
| 1976 | * operations. |
| 1977 | */ |
| 1978 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); |
| 1979 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 1980 | } |
| 1981 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 1982 | /* |
| 1983 | * Must be paired with edp_panel_vdd_on(). |
| 1984 | * Must hold pps_mutex around the whole on/off sequence. |
| 1985 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 1986 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1987 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1988 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1989 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 1990 | |
| 1991 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 1992 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1993 | if (!is_edp(intel_dp)) |
| 1994 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1995 | |
Rob Clark | e2c719b | 2014-12-15 13:56:32 -0500 | [diff] [blame] | 1996 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 1997 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1998 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1999 | intel_dp->want_panel_vdd = false; |
| 2000 | |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2001 | if (sync) |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2002 | edp_panel_vdd_off_sync(intel_dp); |
Imre Deak | aba8689 | 2014-07-30 15:57:31 +0300 | [diff] [blame] | 2003 | else |
| 2004 | edp_panel_vdd_schedule_off(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2005 | } |
| 2006 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2007 | static void edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2008 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2009 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2010 | struct drm_i915_private *dev_priv = to_i915(dev); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2011 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2012 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2013 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2014 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2015 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2016 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2017 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2018 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2019 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
| 2020 | port_name(dp_to_dig_port(intel_dp)->port)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2021 | |
Ville Syrjälä | e7a89ac | 2014-10-16 21:30:07 +0300 | [diff] [blame] | 2022 | if (WARN(edp_have_panel_power(intel_dp), |
| 2023 | "eDP port %c panel power already on\n", |
| 2024 | port_name(dp_to_dig_port(intel_dp)->port))) |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2025 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2026 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2027 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2028 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2029 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2030 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2031 | if (IS_GEN5(dev)) { |
| 2032 | /* ILK workaround: disable reset around power sequence */ |
| 2033 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2034 | I915_WRITE(pp_ctrl_reg, pp); |
| 2035 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2036 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2037 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 2038 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2039 | if (!IS_GEN5(dev)) |
| 2040 | pp |= PANEL_POWER_RESET; |
| 2041 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2042 | I915_WRITE(pp_ctrl_reg, pp); |
| 2043 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2044 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2045 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2046 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2047 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2048 | if (IS_GEN5(dev)) { |
| 2049 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2050 | I915_WRITE(pp_ctrl_reg, pp); |
| 2051 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 2052 | } |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2053 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2054 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2055 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 2056 | { |
| 2057 | if (!is_edp(intel_dp)) |
| 2058 | return; |
| 2059 | |
| 2060 | pps_lock(intel_dp); |
| 2061 | edp_panel_on(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2062 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2063 | } |
| 2064 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2065 | |
| 2066 | static void edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2067 | { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2068 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2069 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2070 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2071 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2072 | enum intel_display_power_domain power_domain; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2073 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2074 | i915_reg_t pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2075 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2076 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2077 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 2078 | if (!is_edp(intel_dp)) |
| 2079 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2080 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2081 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
| 2082 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 2083 | |
Ville Syrjälä | 3936fcf | 2014-10-16 21:30:02 +0300 | [diff] [blame] | 2084 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
| 2085 | port_name(dp_to_dig_port(intel_dp)->port)); |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2086 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2087 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 2088 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 2089 | * panels get very unhappy and cease to work. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 2090 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 2091 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2092 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2093 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2094 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2095 | intel_dp->want_panel_vdd = false; |
| 2096 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2097 | I915_WRITE(pp_ctrl_reg, pp); |
| 2098 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2099 | |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 2100 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2101 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 2102 | |
| 2103 | /* We got a reference when we enabled the VDD. */ |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 2104 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 2105 | intel_display_power_put(dev_priv, power_domain); |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2106 | } |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2107 | |
Ville Syrjälä | 9f0fb5b | 2014-10-16 21:27:32 +0300 | [diff] [blame] | 2108 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 2109 | { |
| 2110 | if (!is_edp(intel_dp)) |
| 2111 | return; |
| 2112 | |
| 2113 | pps_lock(intel_dp); |
| 2114 | edp_panel_off(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2115 | pps_unlock(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 2116 | } |
| 2117 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2118 | /* Enable backlight in the panel power control. */ |
| 2119 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2120 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2121 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2122 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2123 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2124 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2125 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2126 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2127 | /* |
| 2128 | * If we enable the backlight right away following a panel power |
| 2129 | * on, we may see slight flicker as the panel syncs with the eDP |
| 2130 | * link. So delay a bit to make sure the image is solid before |
| 2131 | * allowing it to appear. |
| 2132 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2133 | wait_backlight_on(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2134 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2135 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2136 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2137 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2138 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2139 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2140 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2141 | |
| 2142 | I915_WRITE(pp_ctrl_reg, pp); |
| 2143 | POSTING_READ(pp_ctrl_reg); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2144 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2145 | pps_unlock(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2146 | } |
| 2147 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2148 | /* Enable backlight PWM and backlight PP control. */ |
| 2149 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 2150 | { |
| 2151 | if (!is_edp(intel_dp)) |
| 2152 | return; |
| 2153 | |
| 2154 | DRM_DEBUG_KMS("\n"); |
| 2155 | |
| 2156 | intel_panel_enable_backlight(intel_dp->attached_connector); |
| 2157 | _intel_edp_backlight_on(intel_dp); |
| 2158 | } |
| 2159 | |
| 2160 | /* Disable backlight in the panel power control. */ |
| 2161 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2162 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2163 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2164 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2165 | u32 pp; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2166 | i915_reg_t pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2167 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2168 | if (!is_edp(intel_dp)) |
| 2169 | return; |
| 2170 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2171 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2172 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2173 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2174 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2175 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 2176 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 2177 | |
| 2178 | I915_WRITE(pp_ctrl_reg, pp); |
| 2179 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2180 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2181 | pps_unlock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2182 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2183 | intel_dp->last_backlight_off = jiffies; |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2184 | edp_wait_backlight_off(intel_dp); |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2185 | } |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2186 | |
Jani Nikula | 1250d10 | 2014-08-12 17:11:39 +0300 | [diff] [blame] | 2187 | /* Disable backlight PP control and backlight PWM. */ |
| 2188 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 2189 | { |
| 2190 | if (!is_edp(intel_dp)) |
| 2191 | return; |
| 2192 | |
| 2193 | DRM_DEBUG_KMS("\n"); |
| 2194 | |
| 2195 | _intel_edp_backlight_off(intel_dp); |
Jesse Barnes | f7d2323 | 2014-03-31 11:13:56 -0700 | [diff] [blame] | 2196 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2197 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2198 | |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2199 | /* |
| 2200 | * Hook for controlling the panel power control backlight through the bl_power |
| 2201 | * sysfs attribute. Take care to handle multiple calls. |
| 2202 | */ |
| 2203 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 2204 | bool enable) |
| 2205 | { |
| 2206 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2207 | bool is_enabled; |
| 2208 | |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2209 | pps_lock(intel_dp); |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 2210 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2211 | pps_unlock(intel_dp); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2212 | |
| 2213 | if (is_enabled == enable) |
| 2214 | return; |
| 2215 | |
Jani Nikula | 23ba937 | 2014-08-27 14:08:43 +0300 | [diff] [blame] | 2216 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
| 2217 | enable ? "enable" : "disable"); |
Jani Nikula | 73580fb7 | 2014-08-12 17:11:41 +0300 | [diff] [blame] | 2218 | |
| 2219 | if (enable) |
| 2220 | _intel_edp_backlight_on(intel_dp); |
| 2221 | else |
| 2222 | _intel_edp_backlight_off(intel_dp); |
| 2223 | } |
| 2224 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2225 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
| 2226 | { |
| 2227 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2228 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 2229 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; |
| 2230 | |
| 2231 | I915_STATE_WARN(cur_state != state, |
| 2232 | "DP port %c state assertion failure (expected %s, current %s)\n", |
| 2233 | port_name(dig_port->port), |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2234 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2235 | } |
| 2236 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) |
| 2237 | |
| 2238 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) |
| 2239 | { |
| 2240 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; |
| 2241 | |
| 2242 | I915_STATE_WARN(cur_state != state, |
| 2243 | "eDP PLL state assertion failure (expected %s, current %s)\n", |
Jani Nikula | 87ad321 | 2016-01-14 12:53:34 +0200 | [diff] [blame] | 2244 | onoff(state), onoff(cur_state)); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2245 | } |
| 2246 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) |
| 2247 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) |
| 2248 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2249 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2250 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2251 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2252 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2253 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2254 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2255 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2256 | assert_dp_port_disabled(intel_dp); |
| 2257 | assert_edp_pll_disabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2258 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2259 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
| 2260 | crtc->config->port_clock); |
| 2261 | |
| 2262 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; |
| 2263 | |
| 2264 | if (crtc->config->port_clock == 162000) |
| 2265 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
| 2266 | else |
| 2267 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 2268 | |
| 2269 | I915_WRITE(DP_A, intel_dp->DP); |
| 2270 | POSTING_READ(DP_A); |
| 2271 | udelay(500); |
| 2272 | |
Ville Syrjälä | 6b23f3e | 2016-04-01 21:53:19 +0300 | [diff] [blame] | 2273 | /* |
| 2274 | * [DevILK] Work around required when enabling DP PLL |
| 2275 | * while a pipe is enabled going to FDI: |
| 2276 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI |
| 2277 | * 2. Program DP PLL enable |
| 2278 | */ |
| 2279 | if (IS_GEN5(dev_priv)) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 2280 | intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); |
Ville Syrjälä | 6b23f3e | 2016-04-01 21:53:19 +0300 | [diff] [blame] | 2281 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2282 | intel_dp->DP |= DP_PLL_ENABLE; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2283 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2284 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 2285 | POSTING_READ(DP_A); |
| 2286 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2287 | } |
| 2288 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2289 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2290 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2291 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2292 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
| 2293 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2294 | |
Ville Syrjälä | 64e1077 | 2015-10-29 21:26:01 +0200 | [diff] [blame] | 2295 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 2296 | assert_dp_port_disabled(intel_dp); |
| 2297 | assert_edp_pll_enabled(dev_priv); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2298 | |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2299 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
| 2300 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2301 | intel_dp->DP &= ~DP_PLL_ENABLE; |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2302 | |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2303 | I915_WRITE(DP_A, intel_dp->DP); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 2304 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2305 | udelay(200); |
| 2306 | } |
| 2307 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2308 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2309 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2310 | { |
| 2311 | int ret, i; |
| 2312 | |
| 2313 | /* Should have a valid DPCD by this point */ |
| 2314 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 2315 | return; |
| 2316 | |
| 2317 | if (mode != DRM_MODE_DPMS_ON) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2318 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2319 | DP_SET_POWER_D3); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2320 | } else { |
| 2321 | /* |
| 2322 | * When turning on, we need to retry for 1ms to give the sink |
| 2323 | * time to wake up. |
| 2324 | */ |
| 2325 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2326 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 2327 | DP_SET_POWER_D0); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2328 | if (ret == 1) |
| 2329 | break; |
| 2330 | msleep(1); |
| 2331 | } |
| 2332 | } |
Jani Nikula | f9cac72 | 2014-09-02 16:33:52 +0300 | [diff] [blame] | 2333 | |
| 2334 | if (ret != 1) |
| 2335 | DRM_DEBUG_KMS("failed to %s sink power state\n", |
| 2336 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 2337 | } |
| 2338 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2339 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 2340 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2341 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2342 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2343 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2344 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2345 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2346 | enum intel_display_power_domain power_domain; |
| 2347 | u32 tmp; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2348 | bool ret; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2349 | |
| 2350 | power_domain = intel_display_port_power_domain(encoder); |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2351 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2352 | return false; |
| 2353 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2354 | ret = false; |
| 2355 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 2356 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2357 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2358 | if (!(tmp & DP_PORT_EN)) |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2359 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2360 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2361 | if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2362 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2363 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2364 | enum pipe p; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2365 | |
Ville Syrjälä | adc289d | 2015-05-05 17:17:30 +0300 | [diff] [blame] | 2366 | for_each_pipe(dev_priv, p) { |
| 2367 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); |
| 2368 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { |
| 2369 | *pipe = p; |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2370 | ret = true; |
| 2371 | |
| 2372 | goto out; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2373 | } |
| 2374 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2375 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2376 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 2377 | i915_mmio_reg_offset(intel_dp->output_reg)); |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2378 | } else if (IS_CHERRYVIEW(dev)) { |
| 2379 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
| 2380 | } else { |
| 2381 | *pipe = PORT_TO_PIPE(tmp); |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 2382 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2383 | |
Imre Deak | 6fa9a5e | 2016-02-12 18:55:18 +0200 | [diff] [blame] | 2384 | ret = true; |
| 2385 | |
| 2386 | out: |
| 2387 | intel_display_power_put(dev_priv, power_domain); |
| 2388 | |
| 2389 | return ret; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2390 | } |
| 2391 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2392 | static void intel_dp_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 2393 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2394 | { |
| 2395 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2396 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2397 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2398 | struct drm_i915_private *dev_priv = to_i915(dev); |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2399 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 2400 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2401 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2402 | tmp = I915_READ(intel_dp->output_reg); |
Jani Nikula | 9fcb170 | 2015-05-05 16:32:12 +0300 | [diff] [blame] | 2403 | |
| 2404 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 2405 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2406 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2407 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 2408 | |
| 2409 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2410 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2411 | else |
| 2412 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2413 | |
Ville Syrjälä | b81e34c | 2015-07-06 15:10:03 +0300 | [diff] [blame] | 2414 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2415 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2416 | else |
| 2417 | flags |= DRM_MODE_FLAG_NVSYNC; |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2418 | } else { |
| 2419 | if (tmp & DP_SYNC_HS_HIGH) |
| 2420 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 2421 | else |
| 2422 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 2423 | |
| 2424 | if (tmp & DP_SYNC_VS_HIGH) |
| 2425 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 2426 | else |
| 2427 | flags |= DRM_MODE_FLAG_NVSYNC; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 2428 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2429 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 2430 | pipe_config->base.adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2431 | |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2432 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2433 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
Ville Syrjälä | 8c875fc | 2014-09-12 15:46:29 +0300 | [diff] [blame] | 2434 | pipe_config->limited_color_range = true; |
| 2435 | |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 2436 | pipe_config->lane_count = |
| 2437 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; |
| 2438 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 2439 | intel_dp_get_m_n(crtc, pipe_config); |
| 2440 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2441 | if (port == PORT_A) { |
Ville Syrjälä | b377e0d | 2015-10-29 21:25:59 +0200 | [diff] [blame] | 2442 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 2443 | pipe_config->port_clock = 162000; |
| 2444 | else |
| 2445 | pipe_config->port_clock = 270000; |
| 2446 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 2447 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 2448 | pipe_config->base.adjusted_mode.crtc_clock = |
| 2449 | intel_dotclock_calculate(pipe_config->port_clock, |
| 2450 | &pipe_config->dp_m_n); |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 2451 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2452 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
| 2453 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2454 | /* |
| 2455 | * This is a big fat ugly hack. |
| 2456 | * |
| 2457 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 2458 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 2459 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 2460 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 2461 | * max, not what it tells us to use. |
| 2462 | * |
| 2463 | * Note: This will still be broken if the eDP panel is not lit |
| 2464 | * up by the BIOS, and thus we can't get the mode at module |
| 2465 | * load. |
| 2466 | */ |
| 2467 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 2468 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 2469 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 2470 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 2471 | } |
| 2472 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2473 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2474 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2475 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2476 | struct drm_device *dev = encoder->base.dev; |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2477 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 2478 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2479 | if (crtc->config->has_audio) |
Jani Nikula | 495a5bb | 2014-10-27 16:26:55 +0200 | [diff] [blame] | 2480 | intel_audio_codec_disable(encoder); |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2481 | |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2482 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
| 2483 | intel_psr_disable(intel_dp); |
| 2484 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 2485 | /* Make sure the panel is off before trying to change the mode. But also |
| 2486 | * ensure that we have vdd while we switch off the panel. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 2487 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2488 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 2489 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2490 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2491 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2492 | /* disable the port before the pipe on g4x */ |
| 2493 | if (INTEL_INFO(dev)->gen < 5) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 2494 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2495 | } |
| 2496 | |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2497 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2498 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2499 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 2500 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2501 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2502 | intel_dp_link_down(intel_dp); |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2503 | |
| 2504 | /* Only ilk+ has port A */ |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 2505 | if (port == PORT_A) |
| 2506 | ironlake_edp_pll_off(intel_dp); |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 2507 | } |
| 2508 | |
| 2509 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 2510 | { |
| 2511 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2512 | |
| 2513 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2514 | } |
| 2515 | |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2516 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 2517 | { |
| 2518 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2519 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2520 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2521 | |
| 2522 | intel_dp_link_down(intel_dp); |
| 2523 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2524 | mutex_lock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2525 | |
Ville Syrjälä | a8f327f | 2015-07-09 20:14:11 +0300 | [diff] [blame] | 2526 | /* Assert data lane reset */ |
| 2527 | chv_data_lane_soft_reset(encoder, true); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2528 | |
Ville Syrjälä | a580516 | 2015-05-26 20:42:30 +0300 | [diff] [blame] | 2529 | mutex_unlock(&dev_priv->sb_lock); |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 2530 | } |
| 2531 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2532 | static void |
| 2533 | _intel_dp_set_link_train(struct intel_dp *intel_dp, |
| 2534 | uint32_t *DP, |
| 2535 | uint8_t dp_train_pat) |
| 2536 | { |
| 2537 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2538 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2539 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2540 | enum port port = intel_dig_port->port; |
| 2541 | |
| 2542 | if (HAS_DDI(dev)) { |
| 2543 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
| 2544 | |
| 2545 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2546 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2547 | else |
| 2548 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2549 | |
| 2550 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2551 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2552 | case DP_TRAINING_PATTERN_DISABLE: |
| 2553 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2554 | |
| 2555 | break; |
| 2556 | case DP_TRAINING_PATTERN_1: |
| 2557 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2558 | break; |
| 2559 | case DP_TRAINING_PATTERN_2: |
| 2560 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2561 | break; |
| 2562 | case DP_TRAINING_PATTERN_3: |
| 2563 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2564 | break; |
| 2565 | } |
| 2566 | I915_WRITE(DP_TP_CTL(port), temp); |
| 2567 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 2568 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
| 2569 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2570 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 2571 | |
| 2572 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2573 | case DP_TRAINING_PATTERN_DISABLE: |
| 2574 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
| 2575 | break; |
| 2576 | case DP_TRAINING_PATTERN_1: |
| 2577 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
| 2578 | break; |
| 2579 | case DP_TRAINING_PATTERN_2: |
| 2580 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2581 | break; |
| 2582 | case DP_TRAINING_PATTERN_3: |
| 2583 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2584 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
| 2585 | break; |
| 2586 | } |
| 2587 | |
| 2588 | } else { |
| 2589 | if (IS_CHERRYVIEW(dev)) |
| 2590 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 2591 | else |
| 2592 | *DP &= ~DP_LINK_TRAIN_MASK; |
| 2593 | |
| 2594 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2595 | case DP_TRAINING_PATTERN_DISABLE: |
| 2596 | *DP |= DP_LINK_TRAIN_OFF; |
| 2597 | break; |
| 2598 | case DP_TRAINING_PATTERN_1: |
| 2599 | *DP |= DP_LINK_TRAIN_PAT_1; |
| 2600 | break; |
| 2601 | case DP_TRAINING_PATTERN_2: |
| 2602 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2603 | break; |
| 2604 | case DP_TRAINING_PATTERN_3: |
| 2605 | if (IS_CHERRYVIEW(dev)) { |
| 2606 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
| 2607 | } else { |
| 2608 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 2609 | *DP |= DP_LINK_TRAIN_PAT_2; |
| 2610 | } |
| 2611 | break; |
| 2612 | } |
| 2613 | } |
| 2614 | } |
| 2615 | |
| 2616 | static void intel_dp_enable_port(struct intel_dp *intel_dp) |
| 2617 | { |
| 2618 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2619 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2620 | struct intel_crtc *crtc = |
| 2621 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2622 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2623 | /* enable with pattern 1 (as per spec) */ |
| 2624 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
| 2625 | DP_TRAINING_PATTERN_1); |
| 2626 | |
| 2627 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2628 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2629 | |
| 2630 | /* |
| 2631 | * Magic for VLV/CHV. We _must_ first set up the register |
| 2632 | * without actually enabling the port, and then do another |
| 2633 | * write to enable the port. Otherwise link training will |
| 2634 | * fail when the power sequencer is freshly used for this port. |
| 2635 | */ |
| 2636 | intel_dp->DP |= DP_PORT_EN; |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 2637 | if (crtc->config->has_audio) |
| 2638 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Ville Syrjälä | 7b713f5 | 2014-10-16 21:27:35 +0300 | [diff] [blame] | 2639 | |
| 2640 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 2641 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2642 | } |
| 2643 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2644 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2645 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2646 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2647 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2648 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2649 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2650 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2651 | enum pipe pipe = crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2652 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 2653 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 2654 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2655 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2656 | pps_lock(intel_dp); |
| 2657 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2658 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2659 | vlv_init_panel_power_sequencer(intel_dp); |
| 2660 | |
Ville Syrjälä | 7b13b58 | 2014-08-18 22:16:08 +0300 | [diff] [blame] | 2661 | intel_dp_enable_port(intel_dp); |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2662 | |
| 2663 | edp_panel_vdd_on(intel_dp); |
| 2664 | edp_panel_on(intel_dp); |
| 2665 | edp_panel_vdd_off(intel_dp, true); |
| 2666 | |
| 2667 | pps_unlock(intel_dp); |
| 2668 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2669 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2670 | unsigned int lane_mask = 0x0; |
| 2671 | |
| 2672 | if (IS_CHERRYVIEW(dev)) |
| 2673 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); |
| 2674 | |
Ville Syrjälä | 9b6de0a | 2015-04-10 18:21:31 +0300 | [diff] [blame] | 2675 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 2676 | lane_mask); |
Ville Syrjälä | e0fce78 | 2015-07-08 23:45:54 +0300 | [diff] [blame] | 2677 | } |
Ville Syrjälä | 61234fa | 2014-10-16 21:27:34 +0300 | [diff] [blame] | 2678 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2679 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 2680 | intel_dp_start_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2681 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2682 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 2683 | if (crtc->config->has_audio) { |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2684 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2685 | pipe_name(pipe)); |
Jani Nikula | c1dec79 | 2014-10-27 16:26:56 +0200 | [diff] [blame] | 2686 | intel_audio_codec_enable(encoder); |
| 2687 | } |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2688 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2689 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2690 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 2691 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2692 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2693 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2694 | intel_enable_dp(encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2695 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2696 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2697 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2698 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 2699 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 2700 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2701 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 2702 | intel_edp_backlight_on(intel_dp); |
Rodrigo Vivi | b32c6f4 | 2014-11-20 03:44:37 -0800 | [diff] [blame] | 2703 | intel_psr_enable(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2704 | } |
| 2705 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2706 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2707 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2708 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | d6fbdd1 | 2015-10-29 21:25:58 +0200 | [diff] [blame] | 2709 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2710 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2711 | intel_dp_prepare(encoder); |
| 2712 | |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 2713 | /* Only ilk+ has port A */ |
Ville Syrjälä | abfce94 | 2015-10-29 21:26:03 +0200 | [diff] [blame] | 2714 | if (port == PORT_A) |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2715 | ironlake_edp_pll_on(intel_dp); |
| 2716 | } |
| 2717 | |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2718 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 2719 | { |
| 2720 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2721 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2722 | enum pipe pipe = intel_dp->pps_pipe; |
Imre Deak | 44cb734 | 2016-08-10 14:07:29 +0300 | [diff] [blame^] | 2723 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2724 | |
| 2725 | edp_panel_vdd_off_sync(intel_dp); |
| 2726 | |
| 2727 | /* |
| 2728 | * VLV seems to get confused when multiple power seqeuencers |
| 2729 | * have the same port selected (even if only one has power/vdd |
| 2730 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 2731 | * CHV on the other hand doesn't seem to mind having the same port |
| 2732 | * selected in multiple power seqeuencers, but let's clear the |
| 2733 | * port select always when logically disconnecting a power sequencer |
| 2734 | * from a port. |
| 2735 | */ |
| 2736 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", |
| 2737 | pipe_name(pipe), port_name(intel_dig_port->port)); |
| 2738 | I915_WRITE(pp_on_reg, 0); |
| 2739 | POSTING_READ(pp_on_reg); |
| 2740 | |
| 2741 | intel_dp->pps_pipe = INVALID_PIPE; |
| 2742 | } |
| 2743 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2744 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
| 2745 | enum pipe pipe) |
| 2746 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2747 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2748 | struct intel_encoder *encoder; |
| 2749 | |
| 2750 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2751 | |
Ville Syrjälä | ac3c12e | 2014-10-16 21:29:56 +0300 | [diff] [blame] | 2752 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
| 2753 | return; |
| 2754 | |
Jani Nikula | 19c8054 | 2015-12-16 12:48:16 +0200 | [diff] [blame] | 2755 | for_each_intel_encoder(dev, encoder) { |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2756 | struct intel_dp *intel_dp; |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2757 | enum port port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2758 | |
| 2759 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 2760 | continue; |
| 2761 | |
| 2762 | intel_dp = enc_to_intel_dp(&encoder->base); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2763 | port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2764 | |
| 2765 | if (intel_dp->pps_pipe != pipe) |
| 2766 | continue; |
| 2767 | |
| 2768 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 2769 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2770 | |
Maarten Lankhorst | e02f9a0 | 2015-08-05 12:37:08 +0200 | [diff] [blame] | 2771 | WARN(encoder->base.crtc, |
Ville Syrjälä | 034e43c | 2014-10-16 21:27:28 +0300 | [diff] [blame] | 2772 | "stealing pipe %c power sequencer from active eDP port %c\n", |
| 2773 | pipe_name(pipe), port_name(port)); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2774 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2775 | /* make sure vdd is off before we steal it */ |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2776 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2777 | } |
| 2778 | } |
| 2779 | |
| 2780 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) |
| 2781 | { |
| 2782 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2783 | struct intel_encoder *encoder = &intel_dig_port->base; |
| 2784 | struct drm_device *dev = encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2785 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2786 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2787 | |
| 2788 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 2789 | |
Ville Syrjälä | 093e3f1 | 2014-10-16 21:27:33 +0300 | [diff] [blame] | 2790 | if (!is_edp(intel_dp)) |
| 2791 | return; |
| 2792 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2793 | if (intel_dp->pps_pipe == crtc->pipe) |
| 2794 | return; |
| 2795 | |
| 2796 | /* |
| 2797 | * If another power sequencer was being used on this |
| 2798 | * port previously make sure to turn off vdd there while |
| 2799 | * we still have control of it. |
| 2800 | */ |
| 2801 | if (intel_dp->pps_pipe != INVALID_PIPE) |
Ville Syrjälä | 83b8459 | 2014-10-16 21:29:51 +0300 | [diff] [blame] | 2802 | vlv_detach_power_sequencer(intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2803 | |
| 2804 | /* |
| 2805 | * We may be stealing the power |
| 2806 | * sequencer from another port. |
| 2807 | */ |
| 2808 | vlv_steal_power_sequencer(dev, crtc->pipe); |
| 2809 | |
| 2810 | /* now it's all ours */ |
| 2811 | intel_dp->pps_pipe = crtc->pipe; |
| 2812 | |
| 2813 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", |
| 2814 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); |
| 2815 | |
| 2816 | /* init power sequencer on this pipe and port */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 2817 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 2818 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 2819 | } |
| 2820 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2821 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 2822 | { |
Ander Conselvan de Oliveira | 5f68c27 | 2016-04-27 15:44:24 +0300 | [diff] [blame] | 2823 | vlv_phy_pre_encoder_enable(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2824 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 2825 | intel_enable_dp(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2826 | } |
| 2827 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 2828 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 2829 | { |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 2830 | intel_dp_prepare(encoder); |
| 2831 | |
Ander Conselvan de Oliveira | 6da2e61 | 2016-04-27 15:44:23 +0300 | [diff] [blame] | 2832 | vlv_phy_pre_pll_enable(encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2833 | } |
| 2834 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2835 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2836 | { |
Ander Conselvan de Oliveira | e7d2a717 | 2016-04-27 15:44:20 +0300 | [diff] [blame] | 2837 | chv_phy_pre_encoder_enable(encoder); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2838 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2839 | intel_enable_dp(encoder); |
Ville Syrjälä | b0b3384 | 2015-07-08 23:45:55 +0300 | [diff] [blame] | 2840 | |
| 2841 | /* Second common lane will stay alive on its own now */ |
Ander Conselvan de Oliveira | e7d2a717 | 2016-04-27 15:44:20 +0300 | [diff] [blame] | 2842 | chv_phy_release_cl2_override(encoder); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2843 | } |
| 2844 | |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2845 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
| 2846 | { |
Ville Syrjälä | 625695f | 2014-06-28 02:04:02 +0300 | [diff] [blame] | 2847 | intel_dp_prepare(encoder); |
| 2848 | |
Ander Conselvan de Oliveira | 419b1b7 | 2016-04-27 15:44:19 +0300 | [diff] [blame] | 2849 | chv_phy_pre_pll_enable(encoder); |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 2850 | } |
| 2851 | |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 2852 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
| 2853 | { |
Ander Conselvan de Oliveira | 204970b | 2016-04-27 15:44:21 +0300 | [diff] [blame] | 2854 | chv_phy_post_pll_disable(encoder); |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 2855 | } |
| 2856 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2857 | /* |
| 2858 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 2859 | * link status information |
| 2860 | */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2861 | bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2862 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2863 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 2864 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
| 2865 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2866 | } |
| 2867 | |
Paulo Zanoni | 1100244 | 2014-06-13 18:45:41 -0300 | [diff] [blame] | 2868 | /* These are source-specific values. */ |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2869 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2870 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2871 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2872 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 2873 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2874 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2875 | |
Vandana Kannan | 9314726 | 2014-11-18 15:45:29 +0530 | [diff] [blame] | 2876 | if (IS_BROXTON(dev)) |
| 2877 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
| 2878 | else if (INTEL_INFO(dev)->gen >= 9) { |
Jani Nikula | 06411f0 | 2016-03-24 17:50:21 +0200 | [diff] [blame] | 2879 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 2880 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 2881 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2882 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2883 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2884 | else if (IS_GEN7(dev) && port == PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2885 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2886 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2887 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2888 | else |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2889 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2890 | } |
| 2891 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 2892 | uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2893 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 2894 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2895 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2896 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2897 | |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 2898 | if (INTEL_INFO(dev)->gen >= 9) { |
| 2899 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2900 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2901 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2902 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2903 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2904 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2905 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Sonika Jindal | 7ad14a2 | 2015-02-25 10:29:12 +0530 | [diff] [blame] | 2906 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
| 2907 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Damien Lespiau | 5a9d1f1 | 2013-12-03 13:56:26 +0000 | [diff] [blame] | 2908 | default: |
| 2909 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
| 2910 | } |
| 2911 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2912 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2913 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2914 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2915 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2916 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2917 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2918 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2919 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2920 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2921 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2922 | } |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 2923 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2924 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2925 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2926 | return DP_TRAIN_PRE_EMPH_LEVEL_3; |
| 2927 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2928 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2929 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2930 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2931 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2932 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2933 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2934 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2935 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2936 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2937 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2938 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2939 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2940 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2941 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2942 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2943 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2944 | } |
| 2945 | } else { |
| 2946 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2947 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
| 2948 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2949 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
| 2950 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
| 2951 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
| 2952 | return DP_TRAIN_PRE_EMPH_LEVEL_1; |
| 2953 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2954 | default: |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2955 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2956 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2957 | } |
| 2958 | } |
| 2959 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 2960 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2961 | { |
Ander Conselvan de Oliveira | 53d9872 | 2016-04-27 15:44:22 +0300 | [diff] [blame] | 2962 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2963 | unsigned long demph_reg_value, preemph_reg_value, |
| 2964 | uniqtranscale_reg_value; |
| 2965 | uint8_t train_set = intel_dp->train_set[0]; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2966 | |
| 2967 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2968 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2969 | preemph_reg_value = 0x0004000; |
| 2970 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2971 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2972 | demph_reg_value = 0x2B405555; |
| 2973 | uniqtranscale_reg_value = 0x552AB83A; |
| 2974 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2975 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2976 | demph_reg_value = 0x2B404040; |
| 2977 | uniqtranscale_reg_value = 0x5548B83A; |
| 2978 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2979 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2980 | demph_reg_value = 0x2B245555; |
| 2981 | uniqtranscale_reg_value = 0x5560B83A; |
| 2982 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2983 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2984 | demph_reg_value = 0x2B405555; |
| 2985 | uniqtranscale_reg_value = 0x5598DA3A; |
| 2986 | break; |
| 2987 | default: |
| 2988 | return 0; |
| 2989 | } |
| 2990 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2991 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2992 | preemph_reg_value = 0x0002000; |
| 2993 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2994 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2995 | demph_reg_value = 0x2B404040; |
| 2996 | uniqtranscale_reg_value = 0x5552B83A; |
| 2997 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 2998 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2999 | demph_reg_value = 0x2B404848; |
| 3000 | uniqtranscale_reg_value = 0x5580B83A; |
| 3001 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3002 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3003 | demph_reg_value = 0x2B404040; |
| 3004 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3005 | break; |
| 3006 | default: |
| 3007 | return 0; |
| 3008 | } |
| 3009 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3010 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3011 | preemph_reg_value = 0x0000000; |
| 3012 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3013 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3014 | demph_reg_value = 0x2B305555; |
| 3015 | uniqtranscale_reg_value = 0x5570B83A; |
| 3016 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3017 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3018 | demph_reg_value = 0x2B2B4040; |
| 3019 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3020 | break; |
| 3021 | default: |
| 3022 | return 0; |
| 3023 | } |
| 3024 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3025 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3026 | preemph_reg_value = 0x0006000; |
| 3027 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3028 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3029 | demph_reg_value = 0x1B405555; |
| 3030 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 3031 | break; |
| 3032 | default: |
| 3033 | return 0; |
| 3034 | } |
| 3035 | break; |
| 3036 | default: |
| 3037 | return 0; |
| 3038 | } |
| 3039 | |
Ander Conselvan de Oliveira | 53d9872 | 2016-04-27 15:44:22 +0300 | [diff] [blame] | 3040 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
| 3041 | uniqtranscale_reg_value, 0); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3042 | |
| 3043 | return 0; |
| 3044 | } |
| 3045 | |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3046 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3047 | { |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3048 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 3049 | u32 deemph_reg_value, margin_reg_value; |
| 3050 | bool uniq_trans_scale = false; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3051 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3052 | |
| 3053 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3054 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3055 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3056 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3057 | deemph_reg_value = 128; |
| 3058 | margin_reg_value = 52; |
| 3059 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3060 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3061 | deemph_reg_value = 128; |
| 3062 | margin_reg_value = 77; |
| 3063 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3064 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3065 | deemph_reg_value = 128; |
| 3066 | margin_reg_value = 102; |
| 3067 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3068 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3069 | deemph_reg_value = 128; |
| 3070 | margin_reg_value = 154; |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3071 | uniq_trans_scale = true; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3072 | break; |
| 3073 | default: |
| 3074 | return 0; |
| 3075 | } |
| 3076 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3077 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3078 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3079 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3080 | deemph_reg_value = 85; |
| 3081 | margin_reg_value = 78; |
| 3082 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3083 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3084 | deemph_reg_value = 85; |
| 3085 | margin_reg_value = 116; |
| 3086 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3087 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3088 | deemph_reg_value = 85; |
| 3089 | margin_reg_value = 154; |
| 3090 | break; |
| 3091 | default: |
| 3092 | return 0; |
| 3093 | } |
| 3094 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3095 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3096 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3097 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3098 | deemph_reg_value = 64; |
| 3099 | margin_reg_value = 104; |
| 3100 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3101 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3102 | deemph_reg_value = 64; |
| 3103 | margin_reg_value = 154; |
| 3104 | break; |
| 3105 | default: |
| 3106 | return 0; |
| 3107 | } |
| 3108 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3109 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3110 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3111 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3112 | deemph_reg_value = 43; |
| 3113 | margin_reg_value = 154; |
| 3114 | break; |
| 3115 | default: |
| 3116 | return 0; |
| 3117 | } |
| 3118 | break; |
| 3119 | default: |
| 3120 | return 0; |
| 3121 | } |
| 3122 | |
Ander Conselvan de Oliveira | b7fa22d | 2016-04-27 15:44:17 +0300 | [diff] [blame] | 3123 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
| 3124 | margin_reg_value, uniq_trans_scale); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3125 | |
| 3126 | return 0; |
| 3127 | } |
| 3128 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3129 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3130 | gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3131 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3132 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3133 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3134 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3136 | default: |
| 3137 | signal_levels |= DP_VOLTAGE_0_4; |
| 3138 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3140 | signal_levels |= DP_VOLTAGE_0_6; |
| 3141 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3142 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3143 | signal_levels |= DP_VOLTAGE_0_8; |
| 3144 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3145 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3146 | signal_levels |= DP_VOLTAGE_1_2; |
| 3147 | break; |
| 3148 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 3149 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3150 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3151 | default: |
| 3152 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 3153 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3154 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3155 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 3156 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3157 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3158 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 3159 | break; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3160 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3161 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 3162 | break; |
| 3163 | } |
| 3164 | return signal_levels; |
| 3165 | } |
| 3166 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3167 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 3168 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3169 | gen6_edp_signal_levels(uint8_t train_set) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3170 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3171 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3172 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3173 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3175 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3176 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3177 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3178 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3179 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
| 3180 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3181 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3182 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
| 3183 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3184 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
| 3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3187 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3188 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 3189 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3190 | "0x%x\n", signal_levels); |
| 3191 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3192 | } |
| 3193 | } |
| 3194 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3195 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 3196 | static uint32_t |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3197 | gen7_edp_signal_levels(uint8_t train_set) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3198 | { |
| 3199 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 3200 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 3201 | switch (signal_levels) { |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3202 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3203 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3205 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3206 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3207 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 3208 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3210 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3211 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3212 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 3213 | |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3215 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
Sonika Jindal | bd60018 | 2014-08-08 16:23:41 +0530 | [diff] [blame] | 3216 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 3217 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 3218 | |
| 3219 | default: |
| 3220 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 3221 | "0x%x\n", signal_levels); |
| 3222 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 3223 | } |
| 3224 | } |
| 3225 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3226 | void |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3227 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3228 | { |
| 3229 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3230 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3231 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3232 | struct drm_i915_private *dev_priv = to_i915(dev); |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3233 | uint32_t signal_levels, mask = 0; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3234 | uint8_t train_set = intel_dp->train_set[0]; |
| 3235 | |
David Weinehall | f8896f5 | 2015-06-25 11:11:03 +0300 | [diff] [blame] | 3236 | if (HAS_DDI(dev)) { |
| 3237 | signal_levels = ddi_signal_levels(intel_dp); |
| 3238 | |
| 3239 | if (IS_BROXTON(dev)) |
| 3240 | signal_levels = 0; |
| 3241 | else |
| 3242 | mask = DDI_BUF_EMP_MASK; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 3243 | } else if (IS_CHERRYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3244 | signal_levels = chv_signal_levels(intel_dp); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 3245 | } else if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3246 | signal_levels = vlv_signal_levels(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3247 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3248 | signal_levels = gen7_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3249 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3250 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3251 | signal_levels = gen6_edp_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3252 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 3253 | } else { |
Daniel Vetter | 5829975c | 2015-04-16 11:36:52 +0200 | [diff] [blame] | 3254 | signal_levels = gen4_signal_levels(train_set); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3255 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 3256 | } |
| 3257 | |
Vandana Kannan | 96fb9f9 | 2014-11-18 15:45:27 +0530 | [diff] [blame] | 3258 | if (mask) |
| 3259 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 3260 | |
| 3261 | DRM_DEBUG_KMS("Using vswing level %d\n", |
| 3262 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); |
| 3263 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", |
| 3264 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 3265 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3266 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3267 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
Ander Conselvan de Oliveira | b905a91 | 2015-10-23 13:01:47 +0300 | [diff] [blame] | 3268 | |
| 3269 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 3270 | POSTING_READ(intel_dp->output_reg); |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 3271 | } |
| 3272 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3273 | void |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3274 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 3275 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3276 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 3277 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 90a6b7b | 2015-07-06 16:39:15 +0300 | [diff] [blame] | 3278 | struct drm_i915_private *dev_priv = |
| 3279 | to_i915(intel_dig_port->base.base.dev); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3280 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3281 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 3282 | |
Ander Conselvan de Oliveira | f4eb692 | 2015-10-23 13:01:44 +0300 | [diff] [blame] | 3283 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3284 | POSTING_READ(intel_dp->output_reg); |
Ander Conselvan de Oliveira | e9c176d | 2015-10-23 13:01:45 +0300 | [diff] [blame] | 3285 | } |
| 3286 | |
Ander Conselvan de Oliveira | 94223d0 | 2015-10-23 13:01:48 +0300 | [diff] [blame] | 3287 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3288 | { |
| 3289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3290 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3291 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3292 | enum port port = intel_dig_port->port; |
| 3293 | uint32_t val; |
| 3294 | |
| 3295 | if (!HAS_DDI(dev)) |
| 3296 | return; |
| 3297 | |
| 3298 | val = I915_READ(DP_TP_CTL(port)); |
| 3299 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 3300 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 3301 | I915_WRITE(DP_TP_CTL(port), val); |
| 3302 | |
| 3303 | /* |
| 3304 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 3305 | * we need to set idle transmission mode is to work around a HW issue |
| 3306 | * where we enable the pipe while not in idle link-training mode. |
| 3307 | * In this case there is requirement to wait for a minimum number of |
| 3308 | * idle patterns to be sent. |
| 3309 | */ |
| 3310 | if (port == PORT_A) |
| 3311 | return; |
| 3312 | |
Chris Wilson | a767017 | 2016-06-30 15:33:10 +0100 | [diff] [blame] | 3313 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
| 3314 | DP_TP_STATUS_IDLE_DONE, |
| 3315 | DP_TP_STATUS_IDLE_DONE, |
| 3316 | 1)) |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3317 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 3318 | } |
| 3319 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3320 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3321 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3322 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3323 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3324 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3325 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3326 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 3327 | struct drm_i915_private *dev_priv = to_i915(dev); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3328 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3329 | |
Daniel Vetter | bc76e320 | 2014-05-20 22:46:50 +0200 | [diff] [blame] | 3330 | if (WARN_ON(HAS_DDI(dev))) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3331 | return; |
| 3332 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 3333 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3334 | return; |
| 3335 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3336 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3337 | |
Ville Syrjälä | 39e5fa8 | 2015-05-05 17:17:29 +0300 | [diff] [blame] | 3338 | if ((IS_GEN7(dev) && port == PORT_A) || |
| 3339 | (HAS_PCH_CPT(dev) && port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3340 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3341 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3342 | } else { |
Ville Syrjälä | aad3d14 | 2014-06-28 02:04:25 +0300 | [diff] [blame] | 3343 | if (IS_CHERRYVIEW(dev)) |
| 3344 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
| 3345 | else |
| 3346 | DP &= ~DP_LINK_TRAIN_MASK; |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3347 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3348 | } |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3349 | I915_WRITE(intel_dp->output_reg, DP); |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 3350 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3351 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3352 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 3353 | I915_WRITE(intel_dp->output_reg, DP); |
| 3354 | POSTING_READ(intel_dp->output_reg); |
| 3355 | |
| 3356 | /* |
| 3357 | * HW workaround for IBX, we need to move the port |
| 3358 | * to transcoder A after disabling it to allow the |
| 3359 | * matching HDMI port to be enabled on transcoder A. |
| 3360 | */ |
| 3361 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3362 | /* |
| 3363 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 3364 | * doing the workaround. Sweep them under the rug. |
| 3365 | */ |
| 3366 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3367 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
| 3368 | |
Ville Syrjälä | 1612c8b | 2015-05-05 17:17:34 +0300 | [diff] [blame] | 3369 | /* always enable with pattern 1 (as per spec) */ |
| 3370 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); |
| 3371 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; |
| 3372 | I915_WRITE(intel_dp->output_reg, DP); |
| 3373 | POSTING_READ(intel_dp->output_reg); |
| 3374 | |
| 3375 | DP &= ~DP_PORT_EN; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3376 | I915_WRITE(intel_dp->output_reg, DP); |
Daniel Vetter | 0ca0968 | 2014-11-24 16:54:11 +0100 | [diff] [blame] | 3377 | POSTING_READ(intel_dp->output_reg); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3378 | |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 3379 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
Ville Syrjälä | 0c241d5 | 2015-10-30 19:23:22 +0200 | [diff] [blame] | 3380 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
| 3381 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3382 | } |
| 3383 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 3384 | msleep(intel_dp->panel_power_down_delay); |
Ville Syrjälä | 6fec766 | 2015-11-10 16:16:17 +0200 | [diff] [blame] | 3385 | |
| 3386 | intel_dp->DP = DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3387 | } |
| 3388 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3389 | static bool |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 3390 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3391 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3392 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3393 | sizeof(intel_dp->dpcd)) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3394 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3395 | |
Andy Shevchenko | a8e9815 | 2014-09-01 14:12:01 +0300 | [diff] [blame] | 3396 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3397 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 3398 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
| 3399 | } |
| 3400 | |
| 3401 | static bool |
| 3402 | intel_edp_init_dpcd(struct intel_dp *intel_dp) |
| 3403 | { |
| 3404 | struct drm_i915_private *dev_priv = |
| 3405 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
| 3406 | |
| 3407 | /* this function is meant to be called only once */ |
| 3408 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); |
| 3409 | |
| 3410 | if (!intel_dp_read_dpcd(intel_dp)) |
| 3411 | return false; |
| 3412 | |
| 3413 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 3414 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 3415 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 3416 | |
| 3417 | /* Check if the panel supports PSR */ |
| 3418 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3419 | intel_dp->psr_dpcd, |
| 3420 | sizeof(intel_dp->psr_dpcd)); |
| 3421 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3422 | dev_priv->psr.sink_support = true; |
| 3423 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
| 3424 | } |
| 3425 | |
| 3426 | if (INTEL_GEN(dev_priv) >= 9 && |
| 3427 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { |
| 3428 | uint8_t frame_sync_cap; |
| 3429 | |
| 3430 | dev_priv->psr.sink_support = true; |
| 3431 | drm_dp_dpcd_read(&intel_dp->aux, |
| 3432 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, |
| 3433 | &frame_sync_cap, 1); |
| 3434 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
| 3435 | /* PSR2 needs frame sync as well */ |
| 3436 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; |
| 3437 | DRM_DEBUG_KMS("PSR2 %s on sink", |
| 3438 | dev_priv->psr.psr2_support ? "supported" : "not supported"); |
| 3439 | } |
| 3440 | |
| 3441 | /* Read the eDP Display control capabilities registers */ |
| 3442 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && |
| 3443 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, |
| 3444 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == |
| 3445 | sizeof(intel_dp->edp_dpcd))) |
| 3446 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
| 3447 | intel_dp->edp_dpcd); |
| 3448 | |
| 3449 | /* Intermediate frequency support */ |
| 3450 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
| 3451 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
| 3452 | int i; |
| 3453 | |
| 3454 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
| 3455 | sink_rates, sizeof(sink_rates)); |
| 3456 | |
| 3457 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
| 3458 | int val = le16_to_cpu(sink_rates[i]); |
| 3459 | |
| 3460 | if (val == 0) |
| 3461 | break; |
| 3462 | |
| 3463 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
| 3464 | intel_dp->sink_rates[i] = (val * 200) / 10; |
| 3465 | } |
| 3466 | intel_dp->num_sink_rates = i; |
| 3467 | } |
| 3468 | |
| 3469 | return true; |
| 3470 | } |
| 3471 | |
| 3472 | |
| 3473 | static bool |
| 3474 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
| 3475 | { |
| 3476 | if (!intel_dp_read_dpcd(intel_dp)) |
| 3477 | return false; |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3478 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3479 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, |
| 3480 | &intel_dp->sink_count, 1) < 0) |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3481 | return false; |
| 3482 | |
| 3483 | /* |
| 3484 | * Sink count can change between short pulse hpd hence |
| 3485 | * a member variable in intel_dp will track any changes |
| 3486 | * between short pulse interrupts. |
| 3487 | */ |
| 3488 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); |
| 3489 | |
| 3490 | /* |
| 3491 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that |
| 3492 | * a dongle is present but no display. Unless we require to know |
| 3493 | * if a dongle is present or not, we don't need to update |
| 3494 | * downstream port information. So, an early return here saves |
| 3495 | * time from performing other operations which are not required. |
| 3496 | */ |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 3497 | if (!is_edp(intel_dp) && !intel_dp->sink_count) |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3498 | return false; |
| 3499 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3500 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3501 | DP_DWN_STRM_PORT_PRESENT)) |
| 3502 | return true; /* native DP sink */ |
| 3503 | |
| 3504 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3505 | return true; /* no per-port downstream info */ |
| 3506 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3507 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3508 | intel_dp->downstream_ports, |
| 3509 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3510 | return false; /* downstream port status fetch failed */ |
| 3511 | |
| 3512 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3513 | } |
| 3514 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3515 | static void |
| 3516 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3517 | { |
| 3518 | u8 buf[3]; |
| 3519 | |
| 3520 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3521 | return; |
| 3522 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3523 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3524 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3525 | buf[0], buf[1], buf[2]); |
| 3526 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3527 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3528 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3529 | buf[0], buf[1], buf[2]); |
| 3530 | } |
| 3531 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3532 | static bool |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3533 | intel_dp_can_mst(struct intel_dp *intel_dp) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3534 | { |
| 3535 | u8 buf[1]; |
| 3536 | |
Nathan Schulte | 7cc9613 | 2016-03-15 10:14:05 -0500 | [diff] [blame] | 3537 | if (!i915.enable_dp_mst) |
| 3538 | return false; |
| 3539 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3540 | if (!intel_dp->can_mst) |
| 3541 | return false; |
| 3542 | |
| 3543 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
| 3544 | return false; |
| 3545 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3546 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
| 3547 | return false; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3548 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 3549 | return buf[0] & DP_MST_CAP; |
| 3550 | } |
| 3551 | |
| 3552 | static void |
| 3553 | intel_dp_configure_mst(struct intel_dp *intel_dp) |
| 3554 | { |
| 3555 | if (!i915.enable_dp_mst) |
| 3556 | return; |
| 3557 | |
| 3558 | if (!intel_dp->can_mst) |
| 3559 | return; |
| 3560 | |
| 3561 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); |
| 3562 | |
| 3563 | if (intel_dp->is_mst) |
| 3564 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
| 3565 | else |
| 3566 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
| 3567 | |
| 3568 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 3569 | intel_dp->is_mst); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3570 | } |
| 3571 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3572 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3573 | { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3574 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3575 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3576 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3577 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3578 | int ret = 0; |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3579 | int count = 0; |
| 3580 | int attempts = 10; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3581 | |
| 3582 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3583 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3584 | ret = -EIO; |
| 3585 | goto out; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3586 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3587 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3588 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3589 | buf & ~DP_TEST_SINK_START) < 0) { |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3590 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3591 | ret = -EIO; |
| 3592 | goto out; |
| 3593 | } |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3594 | |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3595 | do { |
| 3596 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3597 | |
| 3598 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
| 3599 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3600 | ret = -EIO; |
| 3601 | goto out; |
| 3602 | } |
| 3603 | count = buf & DP_TEST_COUNT_MASK; |
| 3604 | } while (--attempts && count); |
| 3605 | |
| 3606 | if (attempts == 0) { |
Rodrigo Vivi | dc5a903 | 2016-01-29 14:44:59 -0800 | [diff] [blame] | 3607 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
Rodrigo Vivi | c629784 | 2015-11-05 10:50:20 -0800 | [diff] [blame] | 3608 | ret = -ETIMEDOUT; |
| 3609 | } |
| 3610 | |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3611 | out: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3612 | hsw_enable_ips(intel_crtc); |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3613 | return ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3614 | } |
| 3615 | |
| 3616 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) |
| 3617 | { |
| 3618 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3619 | struct drm_device *dev = dig_port->base.base.dev; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3620 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3621 | u8 buf; |
Rodrigo Vivi | e5a1cab | 2015-07-23 16:35:48 -0700 | [diff] [blame] | 3622 | int ret; |
| 3623 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3624 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
| 3625 | return -EIO; |
| 3626 | |
| 3627 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
| 3628 | return -ENOTTY; |
| 3629 | |
| 3630 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
| 3631 | return -EIO; |
| 3632 | |
Rodrigo Vivi | 6d8175d | 2015-11-05 10:50:22 -0800 | [diff] [blame] | 3633 | if (buf & DP_TEST_SINK_START) { |
| 3634 | ret = intel_dp_sink_crc_stop(intel_dp); |
| 3635 | if (ret) |
| 3636 | return ret; |
| 3637 | } |
| 3638 | |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3639 | hsw_disable_ips(intel_crtc); |
| 3640 | |
| 3641 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3642 | buf | DP_TEST_SINK_START) < 0) { |
| 3643 | hsw_enable_ips(intel_crtc); |
| 3644 | return -EIO; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3645 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3646 | |
Rodrigo Vivi | d72f9d9 | 2015-11-05 10:50:19 -0800 | [diff] [blame] | 3647 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3648 | return 0; |
| 3649 | } |
| 3650 | |
| 3651 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3652 | { |
| 3653 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3654 | struct drm_device *dev = dig_port->base.base.dev; |
| 3655 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 3656 | u8 buf; |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3657 | int count, ret; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3658 | int attempts = 6; |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3659 | |
| 3660 | ret = intel_dp_sink_crc_start(intel_dp); |
| 3661 | if (ret) |
| 3662 | return ret; |
| 3663 | |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3664 | do { |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3665 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3666 | |
Rodrigo Vivi | 1dda5f9 | 2014-10-01 07:32:37 -0700 | [diff] [blame] | 3667 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3668 | DP_TEST_SINK_MISC, &buf) < 0) { |
| 3669 | ret = -EIO; |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3670 | goto stop; |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3671 | } |
Rodrigo Vivi | 621d4c7 | 2015-07-23 16:35:49 -0700 | [diff] [blame] | 3672 | count = buf & DP_TEST_COUNT_MASK; |
Rodrigo Vivi | aabc95d | 2015-07-23 16:35:50 -0700 | [diff] [blame] | 3673 | |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3674 | } while (--attempts && count == 0); |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3675 | |
| 3676 | if (attempts == 0) { |
Rodrigo Vivi | 7e38eef | 2015-11-05 10:50:21 -0800 | [diff] [blame] | 3677 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
| 3678 | ret = -ETIMEDOUT; |
| 3679 | goto stop; |
| 3680 | } |
| 3681 | |
| 3682 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { |
| 3683 | ret = -EIO; |
| 3684 | goto stop; |
Rodrigo Vivi | ad9dc91 | 2014-09-16 19:18:12 -0400 | [diff] [blame] | 3685 | } |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3686 | |
Rodrigo Vivi | afe0d67 | 2015-07-23 16:35:45 -0700 | [diff] [blame] | 3687 | stop: |
Rodrigo Vivi | 082dcc7 | 2015-07-30 16:26:39 -0700 | [diff] [blame] | 3688 | intel_dp_sink_crc_stop(intel_dp); |
Paulo Zanoni | 4373f0f | 2015-05-25 18:52:29 -0300 | [diff] [blame] | 3689 | return ret; |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3690 | } |
| 3691 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3692 | static bool |
| 3693 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3694 | { |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3695 | return drm_dp_dpcd_read(&intel_dp->aux, |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3696 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3697 | sink_irq_vector, 1) == 1; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3698 | } |
| 3699 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3700 | static bool |
| 3701 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3702 | { |
| 3703 | int ret; |
| 3704 | |
Lyude | 9f085eb | 2016-04-13 10:58:33 -0400 | [diff] [blame] | 3705 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3706 | DP_SINK_COUNT_ESI, |
| 3707 | sink_irq_vector, 14); |
| 3708 | if (ret != 14) |
| 3709 | return false; |
| 3710 | |
| 3711 | return true; |
| 3712 | } |
| 3713 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3714 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3715 | { |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3716 | uint8_t test_result = DP_TEST_ACK; |
| 3717 | return test_result; |
| 3718 | } |
| 3719 | |
| 3720 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 3721 | { |
| 3722 | uint8_t test_result = DP_TEST_NAK; |
| 3723 | return test_result; |
| 3724 | } |
| 3725 | |
| 3726 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 3727 | { |
| 3728 | uint8_t test_result = DP_TEST_NAK; |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3729 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 3730 | struct drm_connector *connector = &intel_connector->base; |
| 3731 | |
| 3732 | if (intel_connector->detect_edid == NULL || |
Daniel Vetter | ac6f2e2 | 2015-05-08 16:15:41 +0200 | [diff] [blame] | 3733 | connector->edid_corrupt || |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3734 | intel_dp->aux.i2c_defer_count > 6) { |
| 3735 | /* Check EDID read for NACKs, DEFERs and corruption |
| 3736 | * (DP CTS 1.2 Core r1.1) |
| 3737 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 3738 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 3739 | * 4.2.2.6 : EDID corruption detected |
| 3740 | * Use failsafe mode for all cases |
| 3741 | */ |
| 3742 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 3743 | intel_dp->aux.i2c_defer_count > 0) |
| 3744 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", |
| 3745 | intel_dp->aux.i2c_nack_count, |
| 3746 | intel_dp->aux.i2c_defer_count); |
| 3747 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; |
| 3748 | } else { |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3749 | struct edid *block = intel_connector->detect_edid; |
| 3750 | |
| 3751 | /* We have to write the checksum |
| 3752 | * of the last block read |
| 3753 | */ |
| 3754 | block += intel_connector->detect_edid->extensions; |
| 3755 | |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3756 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
| 3757 | DP_TEST_EDID_CHECKSUM, |
Thulasimani,Sivakumar | f79b468e | 2015-08-07 15:14:30 +0530 | [diff] [blame] | 3758 | &block->checksum, |
Dan Carpenter | 5a1cc65 | 2015-05-12 21:07:37 +0300 | [diff] [blame] | 3759 | 1)) |
Todd Previte | 559be30 | 2015-05-04 07:48:20 -0700 | [diff] [blame] | 3760 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
| 3761 | |
| 3762 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; |
| 3763 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; |
| 3764 | } |
| 3765 | |
| 3766 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 3767 | intel_dp->compliance_test_active = 1; |
| 3768 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3769 | return test_result; |
| 3770 | } |
| 3771 | |
| 3772 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
| 3773 | { |
| 3774 | uint8_t test_result = DP_TEST_NAK; |
| 3775 | return test_result; |
| 3776 | } |
| 3777 | |
| 3778 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3779 | { |
| 3780 | uint8_t response = DP_TEST_NAK; |
| 3781 | uint8_t rxdata = 0; |
| 3782 | int status = 0; |
| 3783 | |
Todd Previte | c5d5ab7 | 2015-04-15 08:38:38 -0700 | [diff] [blame] | 3784 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
| 3785 | if (status <= 0) { |
| 3786 | DRM_DEBUG_KMS("Could not read test request from sink\n"); |
| 3787 | goto update_status; |
| 3788 | } |
| 3789 | |
| 3790 | switch (rxdata) { |
| 3791 | case DP_TEST_LINK_TRAINING: |
| 3792 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); |
| 3793 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; |
| 3794 | response = intel_dp_autotest_link_training(intel_dp); |
| 3795 | break; |
| 3796 | case DP_TEST_LINK_VIDEO_PATTERN: |
| 3797 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); |
| 3798 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; |
| 3799 | response = intel_dp_autotest_video_pattern(intel_dp); |
| 3800 | break; |
| 3801 | case DP_TEST_LINK_EDID_READ: |
| 3802 | DRM_DEBUG_KMS("EDID test requested\n"); |
| 3803 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; |
| 3804 | response = intel_dp_autotest_edid(intel_dp); |
| 3805 | break; |
| 3806 | case DP_TEST_LINK_PHY_TEST_PATTERN: |
| 3807 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); |
| 3808 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; |
| 3809 | response = intel_dp_autotest_phy_pattern(intel_dp); |
| 3810 | break; |
| 3811 | default: |
| 3812 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); |
| 3813 | break; |
| 3814 | } |
| 3815 | |
| 3816 | update_status: |
| 3817 | status = drm_dp_dpcd_write(&intel_dp->aux, |
| 3818 | DP_TEST_RESPONSE, |
| 3819 | &response, 1); |
| 3820 | if (status <= 0) |
| 3821 | DRM_DEBUG_KMS("Could not write test response to sink\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3822 | } |
| 3823 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3824 | static int |
| 3825 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
| 3826 | { |
| 3827 | bool bret; |
| 3828 | |
| 3829 | if (intel_dp->is_mst) { |
| 3830 | u8 esi[16] = { 0 }; |
| 3831 | int ret = 0; |
| 3832 | int retry; |
| 3833 | bool handled; |
| 3834 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 3835 | go_again: |
| 3836 | if (bret == true) { |
| 3837 | |
| 3838 | /* check link status - esi[10] = 0x200c */ |
Ville Syrjälä | 19e0b4c | 2016-08-05 19:05:42 +0300 | [diff] [blame] | 3839 | if (intel_dp->active_mst_links && |
Ville Syrjälä | 901c2da | 2015-08-17 18:05:12 +0300 | [diff] [blame] | 3840 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3841 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
| 3842 | intel_dp_start_link_train(intel_dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3843 | intel_dp_stop_link_train(intel_dp); |
| 3844 | } |
| 3845 | |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 3846 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3847 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
| 3848 | |
| 3849 | if (handled) { |
| 3850 | for (retry = 0; retry < 3; retry++) { |
| 3851 | int wret; |
| 3852 | wret = drm_dp_dpcd_write(&intel_dp->aux, |
| 3853 | DP_SINK_COUNT_ESI+1, |
| 3854 | &esi[1], 3); |
| 3855 | if (wret == 3) { |
| 3856 | break; |
| 3857 | } |
| 3858 | } |
| 3859 | |
| 3860 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
| 3861 | if (bret == true) { |
Andy Shevchenko | 6f34cc3 | 2015-01-15 13:45:09 +0200 | [diff] [blame] | 3862 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 3863 | goto go_again; |
| 3864 | } |
| 3865 | } else |
| 3866 | ret = 0; |
| 3867 | |
| 3868 | return ret; |
| 3869 | } else { |
| 3870 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3871 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
| 3872 | intel_dp->is_mst = false; |
| 3873 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
| 3874 | /* send a hotplug event */ |
| 3875 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); |
| 3876 | } |
| 3877 | } |
| 3878 | return -EINVAL; |
| 3879 | } |
| 3880 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 3881 | static void |
| 3882 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
| 3883 | { |
| 3884 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 3885 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 3886 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 3887 | |
| 3888 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
| 3889 | |
| 3890 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 3891 | DRM_ERROR("Failed to get link status\n"); |
| 3892 | return; |
| 3893 | } |
| 3894 | |
| 3895 | if (!intel_encoder->base.crtc) |
| 3896 | return; |
| 3897 | |
| 3898 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
| 3899 | return; |
| 3900 | |
| 3901 | /* if link training is requested we should perform it always */ |
| 3902 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || |
| 3903 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { |
| 3904 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 3905 | intel_encoder->base.name); |
| 3906 | intel_dp_start_link_train(intel_dp); |
| 3907 | intel_dp_stop_link_train(intel_dp); |
| 3908 | } |
| 3909 | } |
| 3910 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3911 | /* |
| 3912 | * According to DP spec |
| 3913 | * 5.1.2: |
| 3914 | * 1. Read DPCD |
| 3915 | * 2. Configure link according to Receiver Capabilities |
| 3916 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 3917 | * 4. Check link status on receipt of hot-plug interrupt |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 3918 | * |
| 3919 | * intel_dp_short_pulse - handles short pulse interrupts |
| 3920 | * when full detection is not required. |
| 3921 | * Returns %true if short pulse is handled and full detection |
| 3922 | * is NOT required and %false otherwise. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3923 | */ |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 3924 | static bool |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 3925 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3926 | { |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 3927 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 3928 | u8 sink_irq_vector = 0; |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 3929 | u8 old_sink_count = intel_dp->sink_count; |
| 3930 | bool ret; |
Dave Airlie | 5b215bc | 2014-08-05 10:40:20 +1000 | [diff] [blame] | 3931 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 3932 | /* |
| 3933 | * Clearing compliance test variables to allow capturing |
| 3934 | * of values for next automated test request. |
| 3935 | */ |
| 3936 | intel_dp->compliance_test_active = 0; |
| 3937 | intel_dp->compliance_test_type = 0; |
| 3938 | intel_dp->compliance_test_data = 0; |
| 3939 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 3940 | /* |
| 3941 | * Now read the DPCD to see if it's actually running |
| 3942 | * If the current value of sink count doesn't match with |
| 3943 | * the value that was stored earlier or dpcd read failed |
| 3944 | * we need to do full detection |
| 3945 | */ |
| 3946 | ret = intel_dp_get_dpcd(intel_dp); |
| 3947 | |
| 3948 | if ((old_sink_count != intel_dp->sink_count) || !ret) { |
| 3949 | /* No need to proceed if we are going to do full detect */ |
| 3950 | return false; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 3951 | } |
| 3952 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3953 | /* Try to read the source of the interrupt */ |
| 3954 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 3955 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
| 3956 | sink_irq_vector != 0) { |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3957 | /* Clear interrupt source */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3958 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 3959 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3960 | sink_irq_vector); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3961 | |
| 3962 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 3963 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3964 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 3965 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 3966 | } |
| 3967 | |
Shubhangi Shrivastava | 5c9114d | 2016-03-30 18:05:24 +0530 | [diff] [blame] | 3968 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 3969 | intel_dp_check_link_status(intel_dp); |
| 3970 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 3971 | |
| 3972 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3973 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3974 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3975 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3976 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3977 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 3978 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3979 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3980 | uint8_t type; |
| 3981 | |
| 3982 | if (!intel_dp_get_dpcd(intel_dp)) |
| 3983 | return connector_status_disconnected; |
| 3984 | |
Shubhangi Shrivastava | 1034ce7 | 2016-04-12 12:23:54 +0530 | [diff] [blame] | 3985 | if (is_edp(intel_dp)) |
| 3986 | return connector_status_connected; |
| 3987 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3988 | /* if there's no downstream port, we're done */ |
| 3989 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3990 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3991 | |
| 3992 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 3993 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 3994 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3995 | |
Shubhangi Shrivastava | 30d9aa4 | 2016-03-30 18:05:25 +0530 | [diff] [blame] | 3996 | return intel_dp->sink_count ? |
| 3997 | connector_status_connected : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3998 | } |
| 3999 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 4000 | if (intel_dp_can_mst(intel_dp)) |
| 4001 | return connector_status_connected; |
| 4002 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4003 | /* If no HPD, poke DDC gently */ |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4004 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4005 | return connector_status_connected; |
| 4006 | |
| 4007 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 4008 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 4009 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 4010 | if (type == DP_DS_PORT_TYPE_VGA || |
| 4011 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 4012 | return connector_status_unknown; |
| 4013 | } else { |
| 4014 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 4015 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 4016 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 4017 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 4018 | return connector_status_unknown; |
| 4019 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 4020 | |
| 4021 | /* Anything else is out of spec, warn and ignore */ |
| 4022 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 4023 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 4024 | } |
| 4025 | |
| 4026 | static enum drm_connector_status |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4027 | edp_detect(struct intel_dp *intel_dp) |
| 4028 | { |
| 4029 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 4030 | enum drm_connector_status status; |
| 4031 | |
| 4032 | status = intel_panel_detect(dev); |
| 4033 | if (status == connector_status_unknown) |
| 4034 | status = connector_status_connected; |
| 4035 | |
| 4036 | return status; |
| 4037 | } |
| 4038 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4039 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4040 | struct intel_digital_port *port) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4041 | { |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4042 | u32 bit; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 4043 | |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4044 | switch (port->port) { |
| 4045 | case PORT_A: |
| 4046 | return true; |
| 4047 | case PORT_B: |
| 4048 | bit = SDE_PORTB_HOTPLUG; |
| 4049 | break; |
| 4050 | case PORT_C: |
| 4051 | bit = SDE_PORTC_HOTPLUG; |
| 4052 | break; |
| 4053 | case PORT_D: |
| 4054 | bit = SDE_PORTD_HOTPLUG; |
| 4055 | break; |
| 4056 | default: |
| 4057 | MISSING_CASE(port->port); |
| 4058 | return false; |
| 4059 | } |
| 4060 | |
| 4061 | return I915_READ(SDEISR) & bit; |
| 4062 | } |
| 4063 | |
| 4064 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4065 | struct intel_digital_port *port) |
| 4066 | { |
| 4067 | u32 bit; |
| 4068 | |
| 4069 | switch (port->port) { |
| 4070 | case PORT_A: |
| 4071 | return true; |
| 4072 | case PORT_B: |
| 4073 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 4074 | break; |
| 4075 | case PORT_C: |
| 4076 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 4077 | break; |
| 4078 | case PORT_D: |
| 4079 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 4080 | break; |
Jani Nikula | a78695d | 2015-09-18 15:54:50 +0300 | [diff] [blame] | 4081 | case PORT_E: |
| 4082 | bit = SDE_PORTE_HOTPLUG_SPT; |
| 4083 | break; |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4084 | default: |
| 4085 | MISSING_CASE(port->port); |
| 4086 | return false; |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4087 | } |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 4088 | |
Jani Nikula | b93433c | 2015-08-20 10:47:36 +0300 | [diff] [blame] | 4089 | return I915_READ(SDEISR) & bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4090 | } |
| 4091 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4092 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4093 | struct intel_digital_port *port) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4094 | { |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4095 | u32 bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4096 | |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4097 | switch (port->port) { |
| 4098 | case PORT_B: |
| 4099 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 4100 | break; |
| 4101 | case PORT_C: |
| 4102 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 4103 | break; |
| 4104 | case PORT_D: |
| 4105 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 4106 | break; |
| 4107 | default: |
| 4108 | MISSING_CASE(port->port); |
| 4109 | return false; |
| 4110 | } |
| 4111 | |
| 4112 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
| 4113 | } |
| 4114 | |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4115 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
| 4116 | struct intel_digital_port *port) |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4117 | { |
| 4118 | u32 bit; |
| 4119 | |
| 4120 | switch (port->port) { |
| 4121 | case PORT_B: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4122 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4123 | break; |
| 4124 | case PORT_C: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4125 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4126 | break; |
| 4127 | case PORT_D: |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4128 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
Jani Nikula | 9642c81 | 2015-08-20 10:47:41 +0300 | [diff] [blame] | 4129 | break; |
| 4130 | default: |
| 4131 | MISSING_CASE(port->port); |
| 4132 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4133 | } |
| 4134 | |
Jani Nikula | 1d24598 | 2015-08-20 10:47:37 +0300 | [diff] [blame] | 4135 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
Dave Airlie | 2a592be | 2014-09-01 16:58:12 +1000 | [diff] [blame] | 4136 | } |
| 4137 | |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4138 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4139 | struct intel_digital_port *intel_dig_port) |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4140 | { |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4141 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4142 | enum port port; |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4143 | u32 bit; |
| 4144 | |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4145 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
| 4146 | switch (port) { |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4147 | case PORT_A: |
| 4148 | bit = BXT_DE_PORT_HP_DDIA; |
| 4149 | break; |
| 4150 | case PORT_B: |
| 4151 | bit = BXT_DE_PORT_HP_DDIB; |
| 4152 | break; |
| 4153 | case PORT_C: |
| 4154 | bit = BXT_DE_PORT_HP_DDIC; |
| 4155 | break; |
| 4156 | default: |
Sonika Jindal | e2ec35a | 2015-09-11 16:58:32 +0530 | [diff] [blame] | 4157 | MISSING_CASE(port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4158 | return false; |
| 4159 | } |
| 4160 | |
| 4161 | return I915_READ(GEN8_DE_PORT_ISR) & bit; |
| 4162 | } |
| 4163 | |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4164 | /* |
| 4165 | * intel_digital_port_connected - is the specified port connected? |
| 4166 | * @dev_priv: i915 private structure |
| 4167 | * @port: the port to test |
| 4168 | * |
| 4169 | * Return %true if @port is connected, %false otherwise. |
| 4170 | */ |
Sonika Jindal | 237ed86 | 2015-09-15 09:44:20 +0530 | [diff] [blame] | 4171 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4172 | struct intel_digital_port *port) |
| 4173 | { |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4174 | if (HAS_PCH_IBX(dev_priv)) |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4175 | return ibx_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 22824fa | 2016-02-11 16:44:28 +0200 | [diff] [blame] | 4176 | else if (HAS_PCH_SPLIT(dev_priv)) |
Jani Nikula | 0df53b7 | 2015-08-20 10:47:40 +0300 | [diff] [blame] | 4177 | return cpt_digital_port_connected(dev_priv, port); |
Jani Nikula | e464bfd | 2015-08-20 10:47:42 +0300 | [diff] [blame] | 4178 | else if (IS_BROXTON(dev_priv)) |
| 4179 | return bxt_digital_port_connected(dev_priv, port); |
Ville Syrjälä | 0780cd3 | 2016-02-10 19:59:05 +0200 | [diff] [blame] | 4180 | else if (IS_GM45(dev_priv)) |
| 4181 | return gm45_digital_port_connected(dev_priv, port); |
Jani Nikula | 7e66bcf | 2015-08-20 10:47:39 +0300 | [diff] [blame] | 4182 | else |
| 4183 | return g4x_digital_port_connected(dev_priv, port); |
| 4184 | } |
| 4185 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4186 | static struct edid * |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4187 | intel_dp_get_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4188 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4189 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4190 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4191 | /* use cached edid if we have one */ |
| 4192 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4193 | /* invalid edid */ |
| 4194 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4195 | return NULL; |
| 4196 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 4197 | return drm_edid_duplicate(intel_connector->edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4198 | } else |
| 4199 | return drm_get_edid(&intel_connector->base, |
| 4200 | &intel_dp->aux.ddc); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4201 | } |
| 4202 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4203 | static void |
| 4204 | intel_dp_set_edid(struct intel_dp *intel_dp) |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4205 | { |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4206 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4207 | struct edid *edid; |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 4208 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4209 | intel_dp_unset_edid(intel_dp); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4210 | edid = intel_dp_get_edid(intel_dp); |
| 4211 | intel_connector->detect_edid = edid; |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4212 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4213 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) |
| 4214 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; |
| 4215 | else |
| 4216 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 4217 | } |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 4218 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4219 | static void |
| 4220 | intel_dp_unset_edid(struct intel_dp *intel_dp) |
| 4221 | { |
| 4222 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 4223 | |
| 4224 | kfree(intel_connector->detect_edid); |
| 4225 | intel_connector->detect_edid = NULL; |
| 4226 | |
| 4227 | intel_dp->has_audio = false; |
| 4228 | } |
| 4229 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4230 | static void |
| 4231 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4232 | { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4233 | struct drm_connector *connector = &intel_connector->base; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4234 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 4235 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4236 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 4237 | struct drm_device *dev = connector->dev; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4238 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4239 | enum intel_display_power_domain power_domain; |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4240 | u8 sink_irq_vector = 0; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4241 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4242 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4243 | intel_display_power_get(to_i915(dev), power_domain); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4244 | |
Chris Wilson | d410b56 | 2014-09-02 20:03:59 +0100 | [diff] [blame] | 4245 | /* Can't disconnect eDP, but you can close the lid... */ |
| 4246 | if (is_edp(intel_dp)) |
| 4247 | status = edp_detect(intel_dp); |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4248 | else if (intel_digital_port_connected(to_i915(dev), |
| 4249 | dp_to_dig_port(intel_dp))) |
| 4250 | status = intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4251 | else |
Ander Conselvan de Oliveira | c555a81 | 2015-11-18 17:19:30 +0200 | [diff] [blame] | 4252 | status = connector_status_disconnected; |
| 4253 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4254 | if (status != connector_status_connected) { |
| 4255 | intel_dp->compliance_test_active = 0; |
| 4256 | intel_dp->compliance_test_type = 0; |
| 4257 | intel_dp->compliance_test_data = 0; |
| 4258 | |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4259 | if (intel_dp->is_mst) { |
| 4260 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4261 | intel_dp->is_mst, |
| 4262 | intel_dp->mst_mgr.mst_state); |
| 4263 | intel_dp->is_mst = false; |
| 4264 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4265 | intel_dp->is_mst); |
| 4266 | } |
| 4267 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4268 | goto out; |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4269 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4270 | |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4271 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4272 | intel_encoder->type = INTEL_OUTPUT_DP; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4273 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 4274 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
| 4275 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
| 4276 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
| 4277 | |
| 4278 | intel_dp_print_rates(intel_dp); |
| 4279 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 4280 | intel_dp_probe_oui(intel_dp); |
| 4281 | |
Ville Syrjälä | c4e3170 | 2016-07-29 16:51:16 +0300 | [diff] [blame] | 4282 | intel_dp_configure_mst(intel_dp); |
| 4283 | |
| 4284 | if (intel_dp->is_mst) { |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4285 | /* |
| 4286 | * If we are in MST mode then this connector |
| 4287 | * won't appear connected or have anything |
| 4288 | * with EDID on it |
| 4289 | */ |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4290 | status = connector_status_disconnected; |
| 4291 | goto out; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4292 | } else if (connector->status == connector_status_connected) { |
| 4293 | /* |
| 4294 | * If display was connected already and is still connected |
| 4295 | * check links status, there has been known issues of |
| 4296 | * link loss triggerring long pulse!!!! |
| 4297 | */ |
| 4298 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
| 4299 | intel_dp_check_link_status(intel_dp); |
| 4300 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
| 4301 | goto out; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4302 | } |
| 4303 | |
Shubhangi Shrivastava | 4df6960 | 2015-10-28 15:30:36 +0530 | [diff] [blame] | 4304 | /* |
| 4305 | * Clearing NACK and defer counts to get their exact values |
| 4306 | * while reading EDID which are required by Compliance tests |
| 4307 | * 4.2.2.4 and 4.2.2.5 |
| 4308 | */ |
| 4309 | intel_dp->aux.i2c_nack_count = 0; |
| 4310 | intel_dp->aux.i2c_defer_count = 0; |
| 4311 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4312 | intel_dp_set_edid(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 4313 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4314 | status = connector_status_connected; |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4315 | intel_dp->detect_done = true; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4316 | |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4317 | /* Try to read the source of the interrupt */ |
| 4318 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
Ville Syrjälä | 65fbb4e | 2016-07-28 17:50:47 +0300 | [diff] [blame] | 4319 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
| 4320 | sink_irq_vector != 0) { |
Todd Previte | 09b1eb1 | 2015-04-20 15:27:34 -0700 | [diff] [blame] | 4321 | /* Clear interrupt source */ |
| 4322 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 4323 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 4324 | sink_irq_vector); |
| 4325 | |
| 4326 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 4327 | intel_dp_handle_test_request(intel_dp); |
| 4328 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 4329 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 4330 | } |
| 4331 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 4332 | out: |
jim.bride@linux.intel.com | 0e505a0 | 2016-04-11 10:11:24 -0700 | [diff] [blame] | 4333 | if ((status != connector_status_connected) && |
| 4334 | (intel_dp->is_mst == false)) |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4335 | intel_dp_unset_edid(intel_dp); |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4336 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4337 | intel_display_power_put(to_i915(dev), power_domain); |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4338 | return; |
| 4339 | } |
| 4340 | |
| 4341 | static enum drm_connector_status |
| 4342 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 4343 | { |
| 4344 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4345 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4346 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4347 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4348 | |
| 4349 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4350 | connector->base.id, connector->name); |
| 4351 | |
| 4352 | if (intel_dp->is_mst) { |
| 4353 | /* MST devices are disconnected from a monitor POV */ |
| 4354 | intel_dp_unset_edid(intel_dp); |
| 4355 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4356 | intel_encoder->type = INTEL_OUTPUT_DP; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4357 | return connector_status_disconnected; |
| 4358 | } |
| 4359 | |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4360 | /* If full detect is not performed yet, do a full detect */ |
| 4361 | if (!intel_dp->detect_done) |
| 4362 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4363 | |
| 4364 | intel_dp->detect_done = false; |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4365 | |
Ville Syrjälä | 1b7f2c8 | 2016-07-18 13:15:14 +0300 | [diff] [blame] | 4366 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
Shubhangi Shrivastava | f21a219 | 2016-03-30 18:05:22 +0530 | [diff] [blame] | 4367 | return connector_status_connected; |
| 4368 | else |
| 4369 | return connector_status_disconnected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4370 | } |
| 4371 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4372 | static void |
| 4373 | intel_dp_force(struct drm_connector *connector) |
| 4374 | { |
| 4375 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 4376 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4377 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4378 | enum intel_display_power_domain power_domain; |
| 4379 | |
| 4380 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4381 | connector->base.id, connector->name); |
| 4382 | intel_dp_unset_edid(intel_dp); |
| 4383 | |
| 4384 | if (connector->status != connector_status_connected) |
| 4385 | return; |
| 4386 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4387 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
| 4388 | intel_display_power_get(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4389 | |
| 4390 | intel_dp_set_edid(intel_dp); |
| 4391 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4392 | intel_display_power_put(dev_priv, power_domain); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4393 | |
| 4394 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4395 | intel_encoder->type = INTEL_OUTPUT_DP; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4396 | } |
| 4397 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4398 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 4399 | { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4400 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4401 | struct edid *edid; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4402 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4403 | edid = intel_connector->detect_edid; |
| 4404 | if (edid) { |
| 4405 | int ret = intel_connector_update_modes(connector, edid); |
| 4406 | if (ret) |
| 4407 | return ret; |
| 4408 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4409 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4410 | /* if eDP has no EDID, fall back to fixed mode */ |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4411 | if (is_edp(intel_attached_dp(connector)) && |
| 4412 | intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4413 | struct drm_display_mode *mode; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4414 | |
| 4415 | mode = drm_mode_duplicate(connector->dev, |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4416 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 4417 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4418 | drm_mode_probed_add(connector, mode); |
| 4419 | return 1; |
| 4420 | } |
| 4421 | } |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4422 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4423 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4424 | } |
| 4425 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4426 | static bool |
| 4427 | intel_dp_detect_audio(struct drm_connector *connector) |
| 4428 | { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4429 | bool has_audio = false; |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4430 | struct edid *edid; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4431 | |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4432 | edid = to_intel_connector(connector)->detect_edid; |
| 4433 | if (edid) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4434 | has_audio = drm_detect_monitor_audio(edid); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 4435 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4436 | return has_audio; |
| 4437 | } |
| 4438 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4439 | static int |
| 4440 | intel_dp_set_property(struct drm_connector *connector, |
| 4441 | struct drm_property *property, |
| 4442 | uint64_t val) |
| 4443 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4444 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4445 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4446 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 4447 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4448 | int ret; |
| 4449 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4450 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4451 | if (ret) |
| 4452 | return ret; |
| 4453 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4454 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4455 | int i = val; |
| 4456 | bool has_audio; |
| 4457 | |
| 4458 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4459 | return 0; |
| 4460 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4461 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4462 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4463 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4464 | has_audio = intel_dp_detect_audio(connector); |
| 4465 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 4466 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4467 | |
| 4468 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4469 | return 0; |
| 4470 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 4471 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4472 | goto done; |
| 4473 | } |
| 4474 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4475 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4476 | bool old_auto = intel_dp->color_range_auto; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4477 | bool old_range = intel_dp->limited_color_range; |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4478 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4479 | switch (val) { |
| 4480 | case INTEL_BROADCAST_RGB_AUTO: |
| 4481 | intel_dp->color_range_auto = true; |
| 4482 | break; |
| 4483 | case INTEL_BROADCAST_RGB_FULL: |
| 4484 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4485 | intel_dp->limited_color_range = false; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4486 | break; |
| 4487 | case INTEL_BROADCAST_RGB_LIMITED: |
| 4488 | intel_dp->color_range_auto = false; |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4489 | intel_dp->limited_color_range = true; |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4490 | break; |
| 4491 | default: |
| 4492 | return -EINVAL; |
| 4493 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4494 | |
| 4495 | if (old_auto == intel_dp->color_range_auto && |
Ville Syrjälä | 0f2a2a7 | 2015-07-06 15:10:00 +0300 | [diff] [blame] | 4496 | old_range == intel_dp->limited_color_range) |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 4497 | return 0; |
| 4498 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4499 | goto done; |
| 4500 | } |
| 4501 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4502 | if (is_edp(intel_dp) && |
| 4503 | property == connector->dev->mode_config.scaling_mode_property) { |
| 4504 | if (val == DRM_MODE_SCALE_NONE) { |
| 4505 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 4506 | return -EINVAL; |
| 4507 | } |
Ville Syrjälä | 234126c | 2016-04-12 22:14:38 +0300 | [diff] [blame] | 4508 | if (HAS_GMCH_DISPLAY(dev_priv) && |
| 4509 | val == DRM_MODE_SCALE_CENTER) { |
| 4510 | DRM_DEBUG_KMS("centering not supported\n"); |
| 4511 | return -EINVAL; |
| 4512 | } |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4513 | |
| 4514 | if (intel_connector->panel.fitting_mode == val) { |
| 4515 | /* the eDP scaling property is not changed */ |
| 4516 | return 0; |
| 4517 | } |
| 4518 | intel_connector->panel.fitting_mode = val; |
| 4519 | |
| 4520 | goto done; |
| 4521 | } |
| 4522 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4523 | return -EINVAL; |
| 4524 | |
| 4525 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 4526 | if (intel_encoder->base.crtc) |
| 4527 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4528 | |
| 4529 | return 0; |
| 4530 | } |
| 4531 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4532 | static int |
| 4533 | intel_dp_connector_register(struct drm_connector *connector) |
| 4534 | { |
| 4535 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Chris Wilson | 1ebaa0b | 2016-06-24 14:00:15 +0100 | [diff] [blame] | 4536 | int ret; |
| 4537 | |
| 4538 | ret = intel_connector_register(connector); |
| 4539 | if (ret) |
| 4540 | return ret; |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4541 | |
| 4542 | i915_debugfs_connector_add(connector); |
| 4543 | |
| 4544 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
| 4545 | intel_dp->aux.name, connector->kdev->kobj.name); |
| 4546 | |
| 4547 | intel_dp->aux.dev = connector->kdev; |
| 4548 | return drm_dp_aux_register(&intel_dp->aux); |
| 4549 | } |
| 4550 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4551 | static void |
Chris Wilson | c191eca | 2016-06-17 11:40:33 +0100 | [diff] [blame] | 4552 | intel_dp_connector_unregister(struct drm_connector *connector) |
| 4553 | { |
| 4554 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); |
| 4555 | intel_connector_unregister(connector); |
| 4556 | } |
| 4557 | |
| 4558 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4559 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4560 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4561 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4562 | |
Chris Wilson | 10e972d | 2014-09-04 21:43:45 +0100 | [diff] [blame] | 4563 | kfree(intel_connector->detect_edid); |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4564 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 4565 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 4566 | kfree(intel_connector->edid); |
| 4567 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 4568 | /* Can't call is_edp() since the encoder may have been destroyed |
| 4569 | * already. */ |
| 4570 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 4571 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 4572 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4573 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 4574 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4575 | } |
| 4576 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4577 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4578 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4579 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 4580 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4581 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4582 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4583 | if (is_edp(intel_dp)) { |
| 4584 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4585 | /* |
| 4586 | * vdd might still be enabled do to the delayed vdd off. |
| 4587 | * Make sure vdd is actually turned off here. |
| 4588 | */ |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4589 | pps_lock(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4590 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4591 | pps_unlock(intel_dp); |
| 4592 | |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 4593 | if (intel_dp->edp_notifier.notifier_call) { |
| 4594 | unregister_reboot_notifier(&intel_dp->edp_notifier); |
| 4595 | intel_dp->edp_notifier.notifier_call = NULL; |
| 4596 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 4597 | } |
Chris Wilson | 9968188 | 2016-06-20 09:29:17 +0100 | [diff] [blame] | 4598 | |
| 4599 | intel_dp_aux_fini(intel_dp); |
| 4600 | |
Imre Deak | c8bd0e4 | 2014-12-12 17:57:38 +0200 | [diff] [blame] | 4601 | drm_encoder_cleanup(encoder); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 4602 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4603 | } |
| 4604 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4605 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4606 | { |
| 4607 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
| 4608 | |
| 4609 | if (!is_edp(intel_dp)) |
| 4610 | return; |
| 4611 | |
Ville Syrjälä | 951468f | 2014-09-04 14:55:31 +0300 | [diff] [blame] | 4612 | /* |
| 4613 | * vdd might still be enabled do to the delayed vdd off. |
| 4614 | * Make sure vdd is actually turned off here. |
| 4615 | */ |
Ville Syrjälä | afa4e53 | 2014-11-25 15:43:48 +0200 | [diff] [blame] | 4616 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4617 | pps_lock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4618 | edp_panel_vdd_off_sync(intel_dp); |
Ville Syrjälä | 773538e8 | 2014-09-04 14:54:56 +0300 | [diff] [blame] | 4619 | pps_unlock(intel_dp); |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 4620 | } |
| 4621 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4622 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
| 4623 | { |
| 4624 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 4625 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4626 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4627 | enum intel_display_power_domain power_domain; |
| 4628 | |
| 4629 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4630 | |
| 4631 | if (!edp_have_panel_vdd(intel_dp)) |
| 4632 | return; |
| 4633 | |
| 4634 | /* |
| 4635 | * The VDD bit needs a power domain reference, so if the bit is |
| 4636 | * already enabled when we boot or resume, grab this reference and |
| 4637 | * schedule a vdd off, so we don't hold on to the reference |
| 4638 | * indefinitely. |
| 4639 | */ |
| 4640 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4641 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4642 | intel_display_power_get(dev_priv, power_domain); |
| 4643 | |
| 4644 | edp_panel_vdd_schedule_off(intel_dp); |
| 4645 | } |
| 4646 | |
Imre Deak | bf93ba6 | 2016-04-18 10:04:21 +0300 | [diff] [blame] | 4647 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4648 | { |
Ville Syrjälä | 64989ca4 | 2016-05-13 20:53:56 +0300 | [diff] [blame] | 4649 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
| 4650 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 4651 | |
| 4652 | if (!HAS_DDI(dev_priv)) |
| 4653 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4654 | |
| 4655 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
| 4656 | return; |
| 4657 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4658 | pps_lock(intel_dp); |
| 4659 | |
| 4660 | /* |
| 4661 | * Read out the current power sequencer assignment, |
| 4662 | * in case the BIOS did something with it. |
| 4663 | */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4664 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 4665 | vlv_initial_power_sequencer_setup(intel_dp); |
| 4666 | |
| 4667 | intel_edp_panel_vdd_sanitize(intel_dp); |
| 4668 | |
| 4669 | pps_unlock(intel_dp); |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4670 | } |
| 4671 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4672 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 4673 | .dpms = drm_atomic_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4674 | .detect = intel_dp_detect, |
Chris Wilson | beb6060 | 2014-09-02 20:04:00 +0100 | [diff] [blame] | 4675 | .force = intel_dp_force, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4676 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4677 | .set_property = intel_dp_set_property, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 4678 | .atomic_get_property = intel_connector_atomic_get_property, |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 4679 | .late_register = intel_dp_connector_register, |
Chris Wilson | c191eca | 2016-06-17 11:40:33 +0100 | [diff] [blame] | 4680 | .early_unregister = intel_dp_connector_unregister, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 4681 | .destroy = intel_dp_connector_destroy, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 4682 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 4683 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4684 | }; |
| 4685 | |
| 4686 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 4687 | .get_modes = intel_dp_get_modes, |
| 4688 | .mode_valid = intel_dp_mode_valid, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4689 | }; |
| 4690 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4691 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Imre Deak | 6d93c0c | 2014-07-31 14:03:36 +0300 | [diff] [blame] | 4692 | .reset = intel_dp_encoder_reset, |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 4693 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4694 | }; |
| 4695 | |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4696 | enum irqreturn |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4697 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
| 4698 | { |
| 4699 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4700 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4701 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4702 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4703 | enum intel_display_power_domain power_domain; |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4704 | enum irqreturn ret = IRQ_NONE; |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4705 | |
Takashi Iwai | 2540058 | 2015-11-19 12:09:56 +0100 | [diff] [blame] | 4706 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
| 4707 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 4708 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4709 | |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4710 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
| 4711 | /* |
| 4712 | * vdd off can generate a long pulse on eDP which |
| 4713 | * would require vdd on to handle it, and thus we |
| 4714 | * would end up in an endless cycle of |
| 4715 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." |
| 4716 | */ |
| 4717 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", |
| 4718 | port_name(intel_dig_port->port)); |
Ville Syrjälä | a8b3d52 | 2015-02-10 14:11:46 +0200 | [diff] [blame] | 4719 | return IRQ_HANDLED; |
Ville Syrjälä | 7a7f84c | 2014-10-16 20:46:10 +0300 | [diff] [blame] | 4720 | } |
| 4721 | |
Ville Syrjälä | 26fbb77 | 2014-08-11 18:37:37 +0300 | [diff] [blame] | 4722 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
| 4723 | port_name(intel_dig_port->port), |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4724 | long_hpd ? "long" : "short"); |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4725 | |
Ville Syrjälä | 25f78f5 | 2015-11-16 15:01:04 +0100 | [diff] [blame] | 4726 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4727 | intel_display_power_get(dev_priv, power_domain); |
| 4728 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4729 | if (long_hpd) { |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4730 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4731 | if (intel_dp->is_mst) |
| 4732 | ret = IRQ_HANDLED; |
| 4733 | goto put_power; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4734 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4735 | } else { |
| 4736 | if (intel_dp->is_mst) { |
Shubhangi Shrivastava | 7d23e3c | 2016-03-30 18:05:23 +0530 | [diff] [blame] | 4737 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
| 4738 | /* |
| 4739 | * If we were in MST mode, and device is not |
| 4740 | * there, get out of MST mode |
| 4741 | */ |
| 4742 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", |
| 4743 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); |
| 4744 | intel_dp->is_mst = false; |
| 4745 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4746 | intel_dp->is_mst); |
| 4747 | goto put_power; |
| 4748 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4749 | } |
| 4750 | |
Shubhangi Shrivastava | 39ff747 | 2016-03-30 18:05:26 +0530 | [diff] [blame] | 4751 | if (!intel_dp->is_mst) { |
| 4752 | if (!intel_dp_short_pulse(intel_dp)) { |
| 4753 | intel_dp_long_pulse(intel_dp->attached_connector); |
| 4754 | goto put_power; |
| 4755 | } |
| 4756 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4757 | } |
Daniel Vetter | b2c5c18 | 2015-01-23 06:00:31 +0100 | [diff] [blame] | 4758 | |
| 4759 | ret = IRQ_HANDLED; |
| 4760 | |
Imre Deak | 1c767b3 | 2014-08-18 14:42:42 +0300 | [diff] [blame] | 4761 | put_power: |
| 4762 | intel_display_power_put(dev_priv, power_domain); |
| 4763 | |
| 4764 | return ret; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 4765 | } |
| 4766 | |
Rodrigo Vivi | 477ec32 | 2015-08-06 15:51:39 +0800 | [diff] [blame] | 4767 | /* check the VBT to see whether the eDP is on another port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 4768 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4769 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4770 | struct drm_i915_private *dev_priv = to_i915(dev); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4771 | |
Ville Syrjälä | 53ce81a | 2015-09-11 21:04:38 +0300 | [diff] [blame] | 4772 | /* |
| 4773 | * eDP not supported on g4x. so bail out early just |
| 4774 | * for a bit extra safety in case the VBT is bonkers. |
| 4775 | */ |
| 4776 | if (INTEL_INFO(dev)->gen < 5) |
| 4777 | return false; |
| 4778 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 4779 | if (port == PORT_A) |
| 4780 | return true; |
| 4781 | |
Jani Nikula | 951d9ef | 2016-03-16 12:43:31 +0200 | [diff] [blame] | 4782 | return intel_bios_is_port_edp(dev_priv, port); |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 4783 | } |
| 4784 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 4785 | void |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4786 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 4787 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4788 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 4789 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 4790 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 4791 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 4792 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4793 | |
| 4794 | if (is_edp(intel_dp)) { |
| 4795 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 4796 | drm_object_attach_property( |
| 4797 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4798 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 4799 | DRM_MODE_SCALE_ASPECT); |
| 4800 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 4801 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4802 | } |
| 4803 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4804 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 4805 | { |
Abhay Kumar | d28d473 | 2016-01-22 17:39:04 -0800 | [diff] [blame] | 4806 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4807 | intel_dp->last_power_on = jiffies; |
| 4808 | intel_dp->last_backlight_off = jiffies; |
| 4809 | } |
| 4810 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4811 | static void |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4812 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
| 4813 | struct intel_dp *intel_dp, struct edp_power_seq *seq) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4814 | { |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4815 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4816 | struct pps_registers regs; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4817 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4818 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4819 | |
| 4820 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 4821 | * the very first thing. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4822 | pp_ctl = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4823 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4824 | pp_on = I915_READ(regs.pp_on); |
| 4825 | pp_off = I915_READ(regs.pp_off); |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4826 | if (!IS_BROXTON(dev_priv)) { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4827 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
| 4828 | pp_div = I915_READ(regs.pp_div); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4829 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4830 | |
| 4831 | /* Pull timing values out of registers */ |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4832 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 4833 | PANEL_POWER_UP_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4834 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4835 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 4836 | PANEL_LIGHT_ON_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4837 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4838 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 4839 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4840 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4841 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 4842 | PANEL_POWER_DOWN_DELAY_SHIFT; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4843 | |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4844 | if (IS_BROXTON(dev_priv)) { |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4845 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
| 4846 | BXT_POWER_CYCLE_DELAY_SHIFT; |
| 4847 | if (tmp > 0) |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4848 | seq->t11_t12 = (tmp - 1) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4849 | else |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4850 | seq->t11_t12 = 0; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4851 | } else { |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4852 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4853 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4854 | } |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4855 | } |
| 4856 | |
| 4857 | static void |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4858 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) |
| 4859 | { |
| 4860 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 4861 | state_name, |
| 4862 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); |
| 4863 | } |
| 4864 | |
| 4865 | static void |
| 4866 | intel_pps_verify_state(struct drm_i915_private *dev_priv, |
| 4867 | struct intel_dp *intel_dp) |
| 4868 | { |
| 4869 | struct edp_power_seq hw; |
| 4870 | struct edp_power_seq *sw = &intel_dp->pps_delays; |
| 4871 | |
| 4872 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); |
| 4873 | |
| 4874 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || |
| 4875 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { |
| 4876 | DRM_ERROR("PPS state mismatch\n"); |
| 4877 | intel_pps_dump_state("sw", sw); |
| 4878 | intel_pps_dump_state("hw", &hw); |
| 4879 | } |
| 4880 | } |
| 4881 | |
| 4882 | static void |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4883 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 4884 | struct intel_dp *intel_dp) |
| 4885 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4886 | struct drm_i915_private *dev_priv = to_i915(dev); |
Imre Deak | 5464861 | 2016-06-16 16:37:22 +0300 | [diff] [blame] | 4887 | struct edp_power_seq cur, vbt, spec, |
| 4888 | *final = &intel_dp->pps_delays; |
| 4889 | |
| 4890 | lockdep_assert_held(&dev_priv->pps_mutex); |
| 4891 | |
| 4892 | /* already initialized? */ |
| 4893 | if (final->t11_t12 != 0) |
| 4894 | return; |
| 4895 | |
| 4896 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4897 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4898 | intel_pps_dump_state("cur", &cur); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4899 | |
Jani Nikula | 6aa23e6 | 2016-03-24 17:50:20 +0200 | [diff] [blame] | 4900 | vbt = dev_priv->vbt.edp.pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4901 | |
| 4902 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 4903 | * our hw here, which are all in 100usec. */ |
| 4904 | spec.t1_t3 = 210 * 10; |
| 4905 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 4906 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 4907 | spec.t10 = 500 * 10; |
| 4908 | /* This one is special and actually in units of 100ms, but zero |
| 4909 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 4910 | * table multiplies it with 1000 to make it in units of 100usec, |
| 4911 | * too. */ |
| 4912 | spec.t11_t12 = (510 + 100) * 10; |
| 4913 | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4914 | intel_pps_dump_state("vbt", &vbt); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4915 | |
| 4916 | /* Use the max of the register settings and vbt. If both are |
| 4917 | * unset, fall back to the spec limits. */ |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4918 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4919 | spec.field : \ |
| 4920 | max(cur.field, vbt.field)) |
| 4921 | assign_final(t1_t3); |
| 4922 | assign_final(t8); |
| 4923 | assign_final(t9); |
| 4924 | assign_final(t10); |
| 4925 | assign_final(t11_t12); |
| 4926 | #undef assign_final |
| 4927 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4928 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4929 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 4930 | intel_dp->backlight_on_delay = get_delay(t8); |
| 4931 | intel_dp->backlight_off_delay = get_delay(t9); |
| 4932 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 4933 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 4934 | #undef get_delay |
| 4935 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 4936 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 4937 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 4938 | intel_dp->panel_power_cycle_delay); |
| 4939 | |
| 4940 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 4941 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4942 | |
| 4943 | /* |
| 4944 | * We override the HW backlight delays to 1 because we do manual waits |
| 4945 | * on them. For T8, even BSpec recommends doing it. For T9, if we |
| 4946 | * don't do this, we'll end up waiting for the backlight off delay |
| 4947 | * twice: once when we do the manual sleep, and once when we disable |
| 4948 | * the panel and wait for the PP_STATUS bit to become zero. |
| 4949 | */ |
| 4950 | final->t8 = 1; |
| 4951 | final->t9 = 1; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 4952 | } |
| 4953 | |
| 4954 | static void |
| 4955 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4956 | struct intel_dp *intel_dp) |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 4957 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 4958 | struct drm_i915_private *dev_priv = to_i915(dev); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4959 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
Ville Syrjälä | e7dc33f | 2016-03-02 17:22:13 +0200 | [diff] [blame] | 4960 | int div = dev_priv->rawclk_freq / 1000; |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4961 | struct pps_registers regs; |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 4962 | enum port port = dp_to_dig_port(intel_dp)->port; |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 4963 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4964 | |
Ville Syrjälä | e39b999 | 2014-09-04 14:53:14 +0300 | [diff] [blame] | 4965 | lockdep_assert_held(&dev_priv->pps_mutex); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4966 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4967 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4968 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 4969 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Imre Deak | de9c1b6 | 2016-06-16 20:01:46 +0300 | [diff] [blame] | 4970 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 4971 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 4972 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4973 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 4974 | * formula. */ |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4975 | if (IS_BROXTON(dev)) { |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4976 | pp_div = I915_READ(regs.pp_ctrl); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 4977 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
| 4978 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) |
| 4979 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
| 4980 | } else { |
| 4981 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
| 4982 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
| 4983 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 4984 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4985 | |
| 4986 | /* Haswell doesn't have any port selection bits for the panel |
| 4987 | * power sequencer any more. */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 4988 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 4989 | port_sel = PANEL_PORT_SELECT_VLV(port); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 4990 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
Ville Syrjälä | ad933b5 | 2014-08-18 22:15:56 +0300 | [diff] [blame] | 4991 | if (port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 4992 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4993 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 4994 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 4995 | } |
| 4996 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 4997 | pp_on |= port_sel; |
| 4998 | |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 4999 | I915_WRITE(regs.pp_on, pp_on); |
| 5000 | I915_WRITE(regs.pp_off, pp_off); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5001 | if (IS_BROXTON(dev)) |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5002 | I915_WRITE(regs.pp_ctrl, pp_div); |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5003 | else |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5004 | I915_WRITE(regs.pp_div, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5005 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 5006 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5007 | I915_READ(regs.pp_on), |
| 5008 | I915_READ(regs.pp_off), |
Vandana Kannan | b0a08be | 2015-06-18 11:00:55 +0530 | [diff] [blame] | 5009 | IS_BROXTON(dev) ? |
Imre Deak | 8e8232d | 2016-06-16 16:37:21 +0300 | [diff] [blame] | 5010 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
| 5011 | I915_READ(regs.pp_div)); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 5012 | } |
| 5013 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5014 | /** |
| 5015 | * intel_dp_set_drrs_state - program registers for RR switch to take effect |
| 5016 | * @dev: DRM device |
| 5017 | * @refresh_rate: RR to be programmed |
| 5018 | * |
| 5019 | * This function gets called when refresh rate (RR) has to be changed from |
| 5020 | * one frequency to another. Switches can be between high and low RR |
| 5021 | * supported by the panel or to any other RR based on media playback (in |
| 5022 | * this case, RR value needs to be passed from user space). |
| 5023 | * |
| 5024 | * The caller of this function needs to take a lock on dev_priv->drrs. |
| 5025 | */ |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5026 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5027 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5028 | struct drm_i915_private *dev_priv = to_i915(dev); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5029 | struct intel_encoder *encoder; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5030 | struct intel_digital_port *dig_port = NULL; |
| 5031 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 5032 | struct intel_crtc_state *config = NULL; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5033 | struct intel_crtc *intel_crtc = NULL; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5034 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5035 | |
| 5036 | if (refresh_rate <= 0) { |
| 5037 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 5038 | return; |
| 5039 | } |
| 5040 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5041 | if (intel_dp == NULL) { |
| 5042 | DRM_DEBUG_KMS("DRRS not supported.\n"); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5043 | return; |
| 5044 | } |
| 5045 | |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5046 | /* |
Rodrigo Vivi | e4d59f6 | 2014-11-20 02:22:08 -0800 | [diff] [blame] | 5047 | * FIXME: This needs proper synchronization with psr state for some |
| 5048 | * platforms that cannot have PSR and DRRS enabled at the same time. |
Daniel Vetter | 1fcc9d1 | 2014-07-11 10:30:10 -0700 | [diff] [blame] | 5049 | */ |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5050 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5051 | dig_port = dp_to_dig_port(intel_dp); |
| 5052 | encoder = &dig_port->base; |
Ander Conselvan de Oliveira | 723f9aa | 2015-03-20 16:18:18 +0200 | [diff] [blame] | 5053 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5054 | |
| 5055 | if (!intel_crtc) { |
| 5056 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 5057 | return; |
| 5058 | } |
| 5059 | |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 5060 | config = intel_crtc->config; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5061 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5062 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5063 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 5064 | return; |
| 5065 | } |
| 5066 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5067 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
| 5068 | refresh_rate) |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5069 | index = DRRS_LOW_RR; |
| 5070 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5071 | if (index == dev_priv->drrs.refresh_rate_type) { |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5072 | DRM_DEBUG_KMS( |
| 5073 | "DRRS requested for previously set RR...ignoring\n"); |
| 5074 | return; |
| 5075 | } |
| 5076 | |
| 5077 | if (!intel_crtc->active) { |
| 5078 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 5079 | return; |
| 5080 | } |
| 5081 | |
Durgadoss R | 44395bf | 2015-02-13 15:33:02 +0530 | [diff] [blame] | 5082 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5083 | switch (index) { |
| 5084 | case DRRS_HIGH_RR: |
| 5085 | intel_dp_set_m_n(intel_crtc, M1_N1); |
| 5086 | break; |
| 5087 | case DRRS_LOW_RR: |
| 5088 | intel_dp_set_m_n(intel_crtc, M2_N2); |
| 5089 | break; |
| 5090 | case DRRS_MAX_RR: |
| 5091 | default: |
| 5092 | DRM_ERROR("Unsupported refreshrate type\n"); |
| 5093 | } |
| 5094 | } else if (INTEL_INFO(dev)->gen > 6) { |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 5095 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5096 | u32 val; |
Vandana Kannan | a4c30b1 | 2015-02-13 15:33:00 +0530 | [diff] [blame] | 5097 | |
Ville Syrjälä | 649636e | 2015-09-22 19:50:01 +0300 | [diff] [blame] | 5098 | val = I915_READ(reg); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5099 | if (index > DRRS_HIGH_RR) { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5100 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5101 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5102 | else |
| 5103 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5104 | } else { |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5105 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
Vandana Kannan | 6fa7aec | 2015-02-13 15:33:01 +0530 | [diff] [blame] | 5106 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
| 5107 | else |
| 5108 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5109 | } |
| 5110 | I915_WRITE(reg, val); |
| 5111 | } |
| 5112 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5113 | dev_priv->drrs.refresh_rate_type = index; |
| 5114 | |
| 5115 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 5116 | } |
| 5117 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5118 | /** |
| 5119 | * intel_edp_drrs_enable - init drrs struct if supported |
| 5120 | * @intel_dp: DP struct |
| 5121 | * |
| 5122 | * Initializes frontbuffer_bits and drrs.dp |
| 5123 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5124 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
| 5125 | { |
| 5126 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5127 | struct drm_i915_private *dev_priv = to_i915(dev); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5128 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5129 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5131 | |
| 5132 | if (!intel_crtc->config->has_drrs) { |
| 5133 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
| 5134 | return; |
| 5135 | } |
| 5136 | |
| 5137 | mutex_lock(&dev_priv->drrs.mutex); |
| 5138 | if (WARN_ON(dev_priv->drrs.dp)) { |
| 5139 | DRM_ERROR("DRRS already enabled\n"); |
| 5140 | goto unlock; |
| 5141 | } |
| 5142 | |
| 5143 | dev_priv->drrs.busy_frontbuffer_bits = 0; |
| 5144 | |
| 5145 | dev_priv->drrs.dp = intel_dp; |
| 5146 | |
| 5147 | unlock: |
| 5148 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5149 | } |
| 5150 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5151 | /** |
| 5152 | * intel_edp_drrs_disable - Disable DRRS |
| 5153 | * @intel_dp: DP struct |
| 5154 | * |
| 5155 | */ |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5156 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
| 5157 | { |
| 5158 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5159 | struct drm_i915_private *dev_priv = to_i915(dev); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5160 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5161 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 5162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5163 | |
| 5164 | if (!intel_crtc->config->has_drrs) |
| 5165 | return; |
| 5166 | |
| 5167 | mutex_lock(&dev_priv->drrs.mutex); |
| 5168 | if (!dev_priv->drrs.dp) { |
| 5169 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5170 | return; |
| 5171 | } |
| 5172 | |
| 5173 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 5174 | intel_dp_set_drrs_state(&dev_priv->drm, |
| 5175 | intel_dp->attached_connector->panel. |
| 5176 | fixed_mode->vrefresh); |
Vandana Kannan | c395578 | 2015-01-22 15:17:40 +0530 | [diff] [blame] | 5177 | |
| 5178 | dev_priv->drrs.dp = NULL; |
| 5179 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5180 | |
| 5181 | cancel_delayed_work_sync(&dev_priv->drrs.work); |
| 5182 | } |
| 5183 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5184 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
| 5185 | { |
| 5186 | struct drm_i915_private *dev_priv = |
| 5187 | container_of(work, typeof(*dev_priv), drrs.work.work); |
| 5188 | struct intel_dp *intel_dp; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5189 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5190 | mutex_lock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5191 | |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5192 | intel_dp = dev_priv->drrs.dp; |
| 5193 | |
| 5194 | if (!intel_dp) |
| 5195 | goto unlock; |
| 5196 | |
| 5197 | /* |
| 5198 | * The delayed work can race with an invalidate hence we need to |
| 5199 | * recheck. |
| 5200 | */ |
| 5201 | |
| 5202 | if (dev_priv->drrs.busy_frontbuffer_bits) |
| 5203 | goto unlock; |
| 5204 | |
| 5205 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 5206 | intel_dp_set_drrs_state(&dev_priv->drm, |
| 5207 | intel_dp->attached_connector->panel. |
| 5208 | downclock_mode->vrefresh); |
Vandana Kannan | 4e9ac94 | 2015-01-22 15:14:45 +0530 | [diff] [blame] | 5209 | |
| 5210 | unlock: |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5211 | mutex_unlock(&dev_priv->drrs.mutex); |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5212 | } |
| 5213 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5214 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5215 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5216 | * @dev_priv: i915 device |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5217 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5218 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5219 | * This function gets called everytime rendering on the given planes start. |
| 5220 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5221 | * |
| 5222 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5223 | */ |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5224 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
| 5225 | unsigned int frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5226 | { |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5227 | struct drm_crtc *crtc; |
| 5228 | enum pipe pipe; |
| 5229 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5230 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5231 | return; |
| 5232 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5233 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5234 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5235 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5236 | if (!dev_priv->drrs.dp) { |
| 5237 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5238 | return; |
| 5239 | } |
| 5240 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5241 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5242 | pipe = to_intel_crtc(crtc)->pipe; |
| 5243 | |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5244 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
| 5245 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; |
| 5246 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5247 | /* invalidate means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5248 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 5249 | intel_dp_set_drrs_state(&dev_priv->drm, |
| 5250 | dev_priv->drrs.dp->attached_connector->panel. |
| 5251 | fixed_mode->vrefresh); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5252 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5253 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5254 | } |
| 5255 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5256 | /** |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5257 | * intel_edp_drrs_flush - Restart Idleness DRRS |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5258 | * @dev_priv: i915 device |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5259 | * @frontbuffer_bits: frontbuffer plane tracking bits |
| 5260 | * |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5261 | * This function gets called every time rendering on the given planes has |
| 5262 | * completed or flip on a crtc is completed. So DRRS should be upclocked |
| 5263 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, |
| 5264 | * if no other planes are dirty. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5265 | * |
| 5266 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. |
| 5267 | */ |
Chris Wilson | 5748b6a | 2016-08-04 16:32:38 +0100 | [diff] [blame] | 5268 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
| 5269 | unsigned int frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5270 | { |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5271 | struct drm_crtc *crtc; |
| 5272 | enum pipe pipe; |
| 5273 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5274 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5275 | return; |
| 5276 | |
Daniel Vetter | 88f933a | 2015-04-09 16:44:16 +0200 | [diff] [blame] | 5277 | cancel_delayed_work(&dev_priv->drrs.work); |
Ramalingam C | 3954e73 | 2015-03-03 12:11:46 +0530 | [diff] [blame] | 5278 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5279 | mutex_lock(&dev_priv->drrs.mutex); |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5280 | if (!dev_priv->drrs.dp) { |
| 5281 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5282 | return; |
| 5283 | } |
| 5284 | |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5285 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
| 5286 | pipe = to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5287 | |
| 5288 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5289 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
| 5290 | |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5291 | /* flush means busy screen hence upclock */ |
Daniel Vetter | c1d038c | 2015-06-18 10:30:25 +0200 | [diff] [blame] | 5292 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 5293 | intel_dp_set_drrs_state(&dev_priv->drm, |
| 5294 | dev_priv->drrs.dp->attached_connector->panel. |
| 5295 | fixed_mode->vrefresh); |
Ramalingam C | 0ddfd20 | 2015-06-15 20:50:05 +0530 | [diff] [blame] | 5296 | |
| 5297 | /* |
| 5298 | * flush also means no more activity hence schedule downclock, if all |
| 5299 | * other fbs are quiescent too |
| 5300 | */ |
| 5301 | if (!dev_priv->drrs.busy_frontbuffer_bits) |
Vandana Kannan | a93fad0 | 2015-01-10 02:25:59 +0530 | [diff] [blame] | 5302 | schedule_delayed_work(&dev_priv->drrs.work, |
| 5303 | msecs_to_jiffies(1000)); |
| 5304 | mutex_unlock(&dev_priv->drrs.mutex); |
| 5305 | } |
| 5306 | |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5307 | /** |
| 5308 | * DOC: Display Refresh Rate Switching (DRRS) |
| 5309 | * |
| 5310 | * Display Refresh Rate Switching (DRRS) is a power conservation feature |
| 5311 | * which enables swtching between low and high refresh rates, |
| 5312 | * dynamically, based on the usage scenario. This feature is applicable |
| 5313 | * for internal panels. |
| 5314 | * |
| 5315 | * Indication that the panel supports DRRS is given by the panel EDID, which |
| 5316 | * would list multiple refresh rates for one resolution. |
| 5317 | * |
| 5318 | * DRRS is of 2 types - static and seamless. |
| 5319 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset |
| 5320 | * (may appear as a blink on screen) and is used in dock-undock scenario. |
| 5321 | * Seamless DRRS involves changing RR without any visual effect to the user |
| 5322 | * and can be used during normal system usage. This is done by programming |
| 5323 | * certain registers. |
| 5324 | * |
| 5325 | * Support for static/seamless DRRS may be indicated in the VBT based on |
| 5326 | * inputs from the panel spec. |
| 5327 | * |
| 5328 | * DRRS saves power by switching to low RR based on usage scenarios. |
| 5329 | * |
Daniel Vetter | 2e7a570 | 2016-06-01 23:40:36 +0200 | [diff] [blame] | 5330 | * The implementation is based on frontbuffer tracking implementation. When |
| 5331 | * there is a disturbance on the screen triggered by user activity or a periodic |
| 5332 | * system activity, DRRS is disabled (RR is changed to high RR). When there is |
| 5333 | * no movement on screen, after a timeout of 1 second, a switch to low RR is |
| 5334 | * made. |
| 5335 | * |
| 5336 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() |
| 5337 | * and intel_edp_drrs_flush() are called. |
Vandana Kannan | b33a281 | 2015-02-13 15:33:03 +0530 | [diff] [blame] | 5338 | * |
| 5339 | * DRRS can be further extended to support other internal panels and also |
| 5340 | * the scenario of video playback wherein RR is set based on the rate |
| 5341 | * requested by userspace. |
| 5342 | */ |
| 5343 | |
| 5344 | /** |
| 5345 | * intel_dp_drrs_init - Init basic DRRS work and mutex. |
| 5346 | * @intel_connector: eDP connector |
| 5347 | * @fixed_mode: preferred mode of panel |
| 5348 | * |
| 5349 | * This function is called only once at driver load to initialize basic |
| 5350 | * DRRS stuff. |
| 5351 | * |
| 5352 | * Returns: |
| 5353 | * Downclock mode if panel supports it, else return NULL. |
| 5354 | * DRRS support is determined by the presence of downclock mode (apart |
| 5355 | * from VBT setting). |
| 5356 | */ |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5357 | static struct drm_display_mode * |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5358 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
| 5359 | struct drm_display_mode *fixed_mode) |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5360 | { |
| 5361 | struct drm_connector *connector = &intel_connector->base; |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5362 | struct drm_device *dev = connector->dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5363 | struct drm_i915_private *dev_priv = to_i915(dev); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5364 | struct drm_display_mode *downclock_mode = NULL; |
| 5365 | |
Daniel Vetter | 9da7d69 | 2015-04-09 16:44:15 +0200 | [diff] [blame] | 5366 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
| 5367 | mutex_init(&dev_priv->drrs.mutex); |
| 5368 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5369 | if (INTEL_INFO(dev)->gen <= 6) { |
| 5370 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 5371 | return NULL; |
| 5372 | } |
| 5373 | |
| 5374 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5375 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5376 | return NULL; |
| 5377 | } |
| 5378 | |
| 5379 | downclock_mode = intel_find_panel_downclock |
| 5380 | (dev, fixed_mode, connector); |
| 5381 | |
| 5382 | if (!downclock_mode) { |
Ramalingam C | a1d2634 | 2015-02-23 17:38:33 +0530 | [diff] [blame] | 5383 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5384 | return NULL; |
| 5385 | } |
| 5386 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5387 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 5388 | |
Vandana Kannan | 96178ee | 2015-01-10 02:25:56 +0530 | [diff] [blame] | 5389 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
Damien Lespiau | 4079b8d | 2014-08-05 10:39:42 +0100 | [diff] [blame] | 5390 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5391 | return downclock_mode; |
| 5392 | } |
| 5393 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5394 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5395 | struct intel_connector *intel_connector) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5396 | { |
| 5397 | struct drm_connector *connector = &intel_connector->base; |
| 5398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5399 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5400 | struct drm_device *dev = intel_encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5401 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5402 | struct drm_display_mode *fixed_mode = NULL; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5403 | struct drm_display_mode *downclock_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5404 | bool has_dpcd; |
| 5405 | struct drm_display_mode *scan; |
| 5406 | struct edid *edid; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5407 | enum pipe pipe = INVALID_PIPE; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5408 | |
| 5409 | if (!is_edp(intel_dp)) |
| 5410 | return true; |
| 5411 | |
Imre Deak | 97a824e1 | 2016-06-21 11:51:47 +0300 | [diff] [blame] | 5412 | /* |
| 5413 | * On IBX/CPT we may get here with LVDS already registered. Since the |
| 5414 | * driver uses the only internal power sequencer available for both |
| 5415 | * eDP and LVDS bail out early in this case to prevent interfering |
| 5416 | * with an already powered-on LVDS power sequencer. |
| 5417 | */ |
| 5418 | if (intel_get_lvds_encoder(dev)) { |
| 5419 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
| 5420 | DRM_INFO("LVDS was detected, not registering eDP\n"); |
| 5421 | |
| 5422 | return false; |
| 5423 | } |
| 5424 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5425 | pps_lock(intel_dp); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5426 | |
| 5427 | intel_dp_init_panel_power_timestamps(intel_dp); |
| 5428 | |
| 5429 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
| 5430 | vlv_initial_power_sequencer_setup(intel_dp); |
| 5431 | } else { |
| 5432 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
| 5433 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
| 5434 | } |
| 5435 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5436 | intel_edp_panel_vdd_sanitize(intel_dp); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5437 | |
Ville Syrjälä | 49e6bc5 | 2014-10-28 16:15:52 +0200 | [diff] [blame] | 5438 | pps_unlock(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 5439 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5440 | /* Cache DPCD and EDID for edp. */ |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 5441 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5442 | |
Ville Syrjälä | fe5a66f | 2016-07-29 16:52:39 +0300 | [diff] [blame] | 5443 | if (!has_dpcd) { |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5444 | /* if this fails, presume the device is a ghost */ |
| 5445 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5446 | goto out_vdd_off; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5447 | } |
| 5448 | |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5449 | mutex_lock(&dev->mode_config.mutex); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5450 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5451 | if (edid) { |
| 5452 | if (drm_add_edid_modes(connector, edid)) { |
| 5453 | drm_mode_connector_update_edid_property(connector, |
| 5454 | edid); |
| 5455 | drm_edid_to_eld(connector, edid); |
| 5456 | } else { |
| 5457 | kfree(edid); |
| 5458 | edid = ERR_PTR(-EINVAL); |
| 5459 | } |
| 5460 | } else { |
| 5461 | edid = ERR_PTR(-ENOENT); |
| 5462 | } |
| 5463 | intel_connector->edid = edid; |
| 5464 | |
| 5465 | /* prefer fixed mode from EDID if available */ |
| 5466 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 5467 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 5468 | fixed_mode = drm_mode_duplicate(dev, scan); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5469 | downclock_mode = intel_dp_drrs_init( |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5470 | intel_connector, fixed_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5471 | break; |
| 5472 | } |
| 5473 | } |
| 5474 | |
| 5475 | /* fallback to VBT if available for eDP */ |
| 5476 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 5477 | fixed_mode = drm_mode_duplicate(dev, |
| 5478 | dev_priv->vbt.lfp_lvds_vbt_mode); |
Ville Syrjälä | df45724 | 2016-05-31 12:08:34 +0300 | [diff] [blame] | 5479 | if (fixed_mode) { |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5480 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
Ville Syrjälä | df45724 | 2016-05-31 12:08:34 +0300 | [diff] [blame] | 5481 | connector->display_info.width_mm = fixed_mode->width_mm; |
| 5482 | connector->display_info.height_mm = fixed_mode->height_mm; |
| 5483 | } |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5484 | } |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 5485 | mutex_unlock(&dev->mode_config.mutex); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5486 | |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5487 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5488 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
| 5489 | register_reboot_notifier(&intel_dp->edp_notifier); |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5490 | |
| 5491 | /* |
| 5492 | * Figure out the current pipe for the initial backlight setup. |
| 5493 | * If the current pipe isn't valid, try the PPS pipe, and if that |
| 5494 | * fails just assume pipe A. |
| 5495 | */ |
| 5496 | if (IS_CHERRYVIEW(dev)) |
| 5497 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
| 5498 | else |
| 5499 | pipe = PORT_TO_PIPE(intel_dp->DP); |
| 5500 | |
| 5501 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5502 | pipe = intel_dp->pps_pipe; |
| 5503 | |
| 5504 | if (pipe != PIPE_A && pipe != PIPE_B) |
| 5505 | pipe = PIPE_A; |
| 5506 | |
| 5507 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", |
| 5508 | pipe_name(pipe)); |
Clint Taylor | 01527b3 | 2014-07-07 13:01:46 -0700 | [diff] [blame] | 5509 | } |
| 5510 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 5511 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Jani Nikula | 5507fae | 2015-09-14 14:03:48 +0300 | [diff] [blame] | 5512 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
Ville Syrjälä | 6517d27 | 2014-11-07 11:16:02 +0200 | [diff] [blame] | 5513 | intel_panel_setup_backlight(connector, pipe); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5514 | |
| 5515 | return true; |
Imre Deak | b4d06ed | 2016-06-21 11:51:49 +0300 | [diff] [blame] | 5516 | |
| 5517 | out_vdd_off: |
| 5518 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 5519 | /* |
| 5520 | * vdd might still be enabled do to the delayed vdd off. |
| 5521 | * Make sure vdd is actually turned off here. |
| 5522 | */ |
| 5523 | pps_lock(intel_dp); |
| 5524 | edp_panel_vdd_off_sync(intel_dp); |
| 5525 | pps_unlock(intel_dp); |
| 5526 | |
| 5527 | return false; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 5528 | } |
| 5529 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5530 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5531 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 5532 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5533 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5534 | struct drm_connector *connector = &intel_connector->base; |
| 5535 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 5536 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 5537 | struct drm_device *dev = intel_encoder->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5538 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5539 | enum port port = intel_dig_port->port; |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 5540 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5541 | |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5542 | if (WARN(intel_dig_port->max_lanes < 1, |
| 5543 | "Not enough lanes (%d) for DP on port %c\n", |
| 5544 | intel_dig_port->max_lanes, port_name(port))) |
| 5545 | return false; |
| 5546 | |
Ville Syrjälä | a4a5d2f | 2014-09-04 14:54:20 +0300 | [diff] [blame] | 5547 | intel_dp->pps_pipe = INVALID_PIPE; |
| 5548 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5549 | /* intel_dp vfuncs */ |
Damien Lespiau | b6b5e38 | 2014-01-20 16:00:59 +0000 | [diff] [blame] | 5550 | if (INTEL_INFO(dev)->gen >= 9) |
| 5551 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5552 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 5553 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 5554 | else if (HAS_PCH_SPLIT(dev)) |
| 5555 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 5556 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5557 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 5558 | |
Damien Lespiau | b9ca5fa | 2014-01-20 16:01:00 +0000 | [diff] [blame] | 5559 | if (INTEL_INFO(dev)->gen >= 9) |
| 5560 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 5561 | else |
Ville Syrjälä | 6ffb1be | 2016-03-02 17:22:14 +0200 | [diff] [blame] | 5562 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 5563 | |
Ander Conselvan de Oliveira | ad64217 | 2015-10-23 13:01:49 +0300 | [diff] [blame] | 5564 | if (HAS_DDI(dev)) |
| 5565 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
| 5566 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 5567 | /* Preserve the current hw state. */ |
| 5568 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 5569 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 5570 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5571 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 5572 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 5573 | else |
| 5574 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5575 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 5576 | /* |
| 5577 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 5578 | * for DP the encoder type can be set by the caller to |
| 5579 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 5580 | */ |
| 5581 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 5582 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 5583 | |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5584 | /* eDP only on port B and/or C on vlv/chv */ |
Wayne Boyer | 666a453 | 2015-12-09 12:29:35 -0800 | [diff] [blame] | 5585 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
| 5586 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
Ville Syrjälä | c17ed5b | 2014-10-16 21:27:27 +0300 | [diff] [blame] | 5587 | return false; |
| 5588 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 5589 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 5590 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 5591 | port_name(port)); |
| 5592 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 5593 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5594 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 5595 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5596 | connector->interlace_allowed = true; |
| 5597 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 5598 | |
Chris Wilson | 7a418e3 | 2016-06-24 14:00:14 +0100 | [diff] [blame] | 5599 | intel_dp_aux_init(intel_dp, intel_connector); |
| 5600 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 5601 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 5602 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 5603 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 5604 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5605 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 5606 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 5607 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 5608 | else |
| 5609 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
| 5610 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 5611 | /* Set up the hotplug pin. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5612 | switch (port) { |
| 5613 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5614 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5615 | break; |
| 5616 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5617 | intel_encoder->hpd_pin = HPD_PORT_B; |
Jani Nikula | e87a005 | 2015-10-20 15:22:02 +0300 | [diff] [blame] | 5618 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
Sonika Jindal | cf1d588 | 2015-08-10 10:35:36 +0530 | [diff] [blame] | 5619 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5620 | break; |
| 5621 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5622 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5623 | break; |
| 5624 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 5625 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5626 | break; |
Xiong Zhang | 26951ca | 2015-08-17 15:55:50 +0800 | [diff] [blame] | 5627 | case PORT_E: |
| 5628 | intel_encoder->hpd_pin = HPD_PORT_E; |
| 5629 | break; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 5630 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 5631 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 5632 | } |
| 5633 | |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5634 | /* init MST on ports that can support it */ |
Ville Syrjälä | f8e58dd | 2016-06-22 21:56:59 +0300 | [diff] [blame] | 5635 | if (HAS_DP_MST(dev) && !is_edp(intel_dp) && |
Jani Nikula | 0c9b371 | 2015-05-18 17:10:01 +0300 | [diff] [blame] | 5636 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
| 5637 | intel_dp_mst_encoder_init(intel_dig_port, |
| 5638 | intel_connector->base.base.id); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5639 | |
Ville Syrjälä | 36b5f42 | 2014-10-16 21:27:30 +0300 | [diff] [blame] | 5640 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5641 | intel_dp_aux_fini(intel_dp); |
| 5642 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
| 5643 | goto fail; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 5644 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 5645 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 5646 | intel_dp_add_properties(intel_dp, connector); |
| 5647 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5648 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 5649 | * 0xd. Failure to do so will result in spurious interrupts being |
| 5650 | * generated on the port when a cable is not attached. |
| 5651 | */ |
| 5652 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 5653 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 5654 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 5655 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 5656 | |
| 5657 | return true; |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5658 | |
| 5659 | fail: |
Ville Syrjälä | a121f4e | 2015-11-11 20:34:11 +0200 | [diff] [blame] | 5660 | drm_connector_cleanup(connector); |
| 5661 | |
| 5662 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 5663 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5664 | |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5665 | bool intel_dp_init(struct drm_device *dev, |
| 5666 | i915_reg_t output_reg, |
| 5667 | enum port port) |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5668 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5669 | struct drm_i915_private *dev_priv = to_i915(dev); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5670 | struct intel_digital_port *intel_dig_port; |
| 5671 | struct intel_encoder *intel_encoder; |
| 5672 | struct drm_encoder *encoder; |
| 5673 | struct intel_connector *intel_connector; |
| 5674 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 5675 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5676 | if (!intel_dig_port) |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5677 | return false; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5678 | |
Ander Conselvan de Oliveira | 08d9bc9 | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 5679 | intel_connector = intel_connector_alloc(); |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5680 | if (!intel_connector) |
| 5681 | goto err_connector_alloc; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5682 | |
| 5683 | intel_encoder = &intel_dig_port->base; |
| 5684 | encoder = &intel_encoder->base; |
| 5685 | |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5686 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Ville Syrjälä | 580d8ed | 2016-05-27 20:59:24 +0300 | [diff] [blame] | 5687 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5688 | goto err_encoder_init; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5689 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 5690 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5691 | intel_encoder->disable = intel_disable_dp; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 5692 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 5693 | intel_encoder->get_config = intel_dp_get_config; |
Imre Deak | 07f9cd0 | 2014-08-18 14:42:45 +0300 | [diff] [blame] | 5694 | intel_encoder->suspend = intel_dp_encoder_suspend; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5695 | if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 9197c88 | 2014-04-09 13:29:05 +0300 | [diff] [blame] | 5696 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5697 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 5698 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame] | 5699 | intel_encoder->post_disable = chv_post_disable_dp; |
Ville Syrjälä | d6db995 | 2015-07-08 23:45:49 +0300 | [diff] [blame] | 5700 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 5701 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5702 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5703 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 5704 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 5705 | intel_encoder->post_disable = vlv_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5706 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 5707 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 5708 | intel_encoder->enable = g4x_enable_dp; |
Ville Syrjälä | 08aff3f | 2014-08-18 22:16:09 +0300 | [diff] [blame] | 5709 | if (INTEL_INFO(dev)->gen >= 5) |
| 5710 | intel_encoder->post_disable = ilk_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 5711 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5712 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 5713 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5714 | intel_dig_port->dp.output_reg = output_reg; |
Ville Syrjälä | ccb1a83 | 2015-12-08 19:59:38 +0200 | [diff] [blame] | 5715 | intel_dig_port->max_lanes = 4; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5716 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 5717 | intel_encoder->type = INTEL_OUTPUT_DP; |
Ville Syrjälä | 882ec38 | 2014-04-28 14:07:43 +0300 | [diff] [blame] | 5718 | if (IS_CHERRYVIEW(dev)) { |
| 5719 | if (port == PORT_D) |
| 5720 | intel_encoder->crtc_mask = 1 << 2; |
| 5721 | else |
| 5722 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 5723 | } else { |
| 5724 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 5725 | } |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 5726 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5727 | |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5728 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5729 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
Dave Airlie | 13cf550 | 2014-06-18 11:29:35 +1000 | [diff] [blame] | 5730 | |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5731 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
| 5732 | goto err_init_connector; |
| 5733 | |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5734 | return true; |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5735 | |
| 5736 | err_init_connector: |
| 5737 | drm_encoder_cleanup(encoder); |
Sudip Mukherjee | 893da0c | 2015-10-08 19:28:00 +0530 | [diff] [blame] | 5738 | err_encoder_init: |
Sudip Mukherjee | 11aee0f | 2015-10-08 19:27:59 +0530 | [diff] [blame] | 5739 | kfree(intel_connector); |
| 5740 | err_connector_alloc: |
| 5741 | kfree(intel_dig_port); |
Chris Wilson | 457c52d | 2016-06-01 08:27:50 +0100 | [diff] [blame] | 5742 | return false; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 5743 | } |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5744 | |
| 5745 | void intel_dp_mst_suspend(struct drm_device *dev) |
| 5746 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5747 | struct drm_i915_private *dev_priv = to_i915(dev); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5748 | int i; |
| 5749 | |
| 5750 | /* disable MST */ |
| 5751 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5752 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5753 | |
| 5754 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5755 | continue; |
| 5756 | |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5757 | if (intel_dig_port->dp.is_mst) |
| 5758 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5759 | } |
| 5760 | } |
| 5761 | |
| 5762 | void intel_dp_mst_resume(struct drm_device *dev) |
| 5763 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 5764 | struct drm_i915_private *dev_priv = to_i915(dev); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5765 | int i; |
| 5766 | |
| 5767 | for (i = 0; i < I915_MAX_PORTS; i++) { |
Jani Nikula | 5fcece8 | 2015-05-27 15:03:42 +0300 | [diff] [blame] | 5768 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5769 | int ret; |
| 5770 | |
| 5771 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5772 | continue; |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5773 | |
Ville Syrjälä | 5aa5696 | 2016-06-22 21:57:00 +0300 | [diff] [blame] | 5774 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
| 5775 | if (ret) |
| 5776 | intel_dp_check_mst_status(&intel_dig_port->dp); |
Dave Airlie | 0e32b39 | 2014-05-02 14:02:48 +1000 | [diff] [blame] | 5777 | } |
| 5778 | } |