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Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010033#include <linux/circ_buf.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drmP.h>
35#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010037#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Egbert Eiche5868a32013-02-28 04:17:12 -050040static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010050 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050051 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
65static const u32 hpd_status_gen4[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
Egbert Eiche5868a32013-02-28 04:17:12 -050074static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
Zhenyu Wang036a4a72009-06-08 14:40:19 +080083/* For display hotplug interrupt */
Chris Wilson995b6762010-08-20 13:23:26 +010084static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -050085ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +080086{
Daniel Vetter4bc9d432013-06-27 13:44:58 +020087 assert_spin_locked(&dev_priv->irq_lock);
88
Paulo Zanonic67a4702013-08-19 13:18:09 -030089 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
Chris Wilson1ec14ad2010-12-04 11:30:53 +000095 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +000098 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +080099 }
100}
101
Paulo Zanoni0ff98002013-02-22 17:05:31 -0300102static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800104{
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200105 assert_spin_locked(&dev_priv->irq_lock);
106
Paulo Zanonic67a4702013-08-19 13:18:09 -0300107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000116 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800117 }
118}
119
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
Paulo Zanonic67a4702013-08-19 13:18:09 -0300132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
Paulo Zanoni605cd252013-08-06 18:57:15 -0300166 uint32_t new_val;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300167
168 assert_spin_locked(&dev_priv->irq_lock);
169
Paulo Zanonic67a4702013-08-19 13:18:09 -0300170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
Paulo Zanoni605cd252013-08-06 18:57:15 -0300178 new_val = dev_priv->pm_irq_mask;
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
Paulo Zanoni605cd252013-08-06 18:57:15 -0300182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300185 POSTING_READ(GEN6_PMIMR);
186 }
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
Paulo Zanoni86642812013-04-12 17:57:57 -0300199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200205 assert_spin_locked(&dev_priv->irq_lock);
206
Paulo Zanoni86642812013-04-12 17:57:57 -0300207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
Daniel Vetterfee884e2013-07-04 23:35:21 +0200223 assert_spin_locked(&dev_priv->irq_lock);
224
Paulo Zanoni86642812013-04-12 17:57:57 -0300225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
235static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
237{
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
241
242 if (enable)
243 ironlake_enable_display_irq(dev_priv, bit);
244 else
245 ironlake_disable_display_irq(dev_priv, bit);
246}
247
248static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
Daniel Vetter7336df62013-07-09 22:59:16 +0200249 enum pipe pipe, bool enable)
Paulo Zanoni86642812013-04-12 17:57:57 -0300250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni86642812013-04-12 17:57:57 -0300252 if (enable) {
Daniel Vetter7336df62013-07-09 22:59:16 +0200253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
254
Paulo Zanoni86642812013-04-12 17:57:57 -0300255 if (!ivb_can_enable_err_int(dev))
256 return;
257
Paulo Zanoni86642812013-04-12 17:57:57 -0300258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
259 } else {
Daniel Vetter7336df62013-07-09 22:59:16 +0200260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
261
262 /* Change the state _after_ we've read out the current one. */
Paulo Zanoni86642812013-04-12 17:57:57 -0300263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
Daniel Vetter7336df62013-07-09 22:59:16 +0200264
265 if (!was_enabled &&
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
268 pipe_name(pipe));
269 }
Paulo Zanoni86642812013-04-12 17:57:57 -0300270 }
271}
272
Daniel Vetterfee884e2013-07-04 23:35:21 +0200273/**
274 * ibx_display_interrupt_update - update SDEIMR
275 * @dev_priv: driver private
276 * @interrupt_mask: mask of interrupt bits to update
277 * @enabled_irq_mask: mask of interrupt bits to enable
278 */
279static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
280 uint32_t interrupt_mask,
281 uint32_t enabled_irq_mask)
282{
283 uint32_t sdeimr = I915_READ(SDEIMR);
284 sdeimr &= ~interrupt_mask;
285 sdeimr |= (~enabled_irq_mask & interrupt_mask);
286
287 assert_spin_locked(&dev_priv->irq_lock);
288
Paulo Zanonic67a4702013-08-19 13:18:09 -0300289 if (dev_priv->pc8.irqs_disabled &&
290 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
291 WARN(1, "IRQs disabled\n");
292 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
293 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
294 interrupt_mask);
295 return;
296 }
297
Daniel Vetterfee884e2013-07-04 23:35:21 +0200298 I915_WRITE(SDEIMR, sdeimr);
299 POSTING_READ(SDEIMR);
300}
301#define ibx_enable_display_interrupt(dev_priv, bits) \
302 ibx_display_interrupt_update((dev_priv), (bits), (bits))
303#define ibx_disable_display_interrupt(dev_priv, bits) \
304 ibx_display_interrupt_update((dev_priv), (bits), 0)
305
Daniel Vetterde280752013-07-04 23:35:24 +0200306static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
307 enum transcoder pch_transcoder,
Paulo Zanoni86642812013-04-12 17:57:57 -0300308 bool enable)
309{
Paulo Zanoni86642812013-04-12 17:57:57 -0300310 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterde280752013-07-04 23:35:24 +0200311 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
312 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
Paulo Zanoni86642812013-04-12 17:57:57 -0300313
314 if (enable)
Daniel Vetterfee884e2013-07-04 23:35:21 +0200315 ibx_enable_display_interrupt(dev_priv, bit);
Paulo Zanoni86642812013-04-12 17:57:57 -0300316 else
Daniel Vetterfee884e2013-07-04 23:35:21 +0200317 ibx_disable_display_interrupt(dev_priv, bit);
Paulo Zanoni86642812013-04-12 17:57:57 -0300318}
319
320static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
321 enum transcoder pch_transcoder,
322 bool enable)
323{
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (enable) {
Daniel Vetter1dd246f2013-07-10 08:30:23 +0200327 I915_WRITE(SERR_INT,
328 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
329
Paulo Zanoni86642812013-04-12 17:57:57 -0300330 if (!cpt_can_enable_serr_int(dev))
331 return;
332
Daniel Vetterfee884e2013-07-04 23:35:21 +0200333 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
Paulo Zanoni86642812013-04-12 17:57:57 -0300334 } else {
Daniel Vetter1dd246f2013-07-10 08:30:23 +0200335 uint32_t tmp = I915_READ(SERR_INT);
336 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
337
338 /* Change the state _after_ we've read out the current one. */
Daniel Vetterfee884e2013-07-04 23:35:21 +0200339 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
Daniel Vetter1dd246f2013-07-10 08:30:23 +0200340
341 if (!was_enabled &&
342 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
343 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
344 transcoder_name(pch_transcoder));
345 }
Paulo Zanoni86642812013-04-12 17:57:57 -0300346 }
Paulo Zanoni86642812013-04-12 17:57:57 -0300347}
348
349/**
350 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
351 * @dev: drm device
352 * @pipe: pipe
353 * @enable: true if we want to report FIFO underrun errors, false otherwise
354 *
355 * This function makes us disable or enable CPU fifo underruns for a specific
356 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
357 * reporting for one pipe may also disable all the other CPU error interruts for
358 * the other pipes, due to the fact that there's just one interrupt mask/enable
359 * bit for all the pipes.
360 *
361 * Returns the previous state of underrun reporting.
362 */
363bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
364 enum pipe pipe, bool enable)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
369 unsigned long flags;
370 bool ret;
371
372 spin_lock_irqsave(&dev_priv->irq_lock, flags);
373
374 ret = !intel_crtc->cpu_fifo_underrun_disabled;
375
376 if (enable == ret)
377 goto done;
378
379 intel_crtc->cpu_fifo_underrun_disabled = !enable;
380
381 if (IS_GEN5(dev) || IS_GEN6(dev))
382 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
383 else if (IS_GEN7(dev))
Daniel Vetter7336df62013-07-09 22:59:16 +0200384 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
Paulo Zanoni86642812013-04-12 17:57:57 -0300385
386done:
387 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
388 return ret;
389}
390
391/**
392 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
393 * @dev: drm device
394 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
395 * @enable: true if we want to report FIFO underrun errors, false otherwise
396 *
397 * This function makes us disable or enable PCH fifo underruns for a specific
398 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
399 * underrun reporting for one transcoder may also disable all the other PCH
400 * error interruts for the other transcoders, due to the fact that there's just
401 * one interrupt mask/enable bit for all the transcoders.
402 *
403 * Returns the previous state of underrun reporting.
404 */
405bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
406 enum transcoder pch_transcoder,
407 bool enable)
408{
409 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterde280752013-07-04 23:35:24 +0200410 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni86642812013-04-12 17:57:57 -0300412 unsigned long flags;
413 bool ret;
414
Daniel Vetterde280752013-07-04 23:35:24 +0200415 /*
416 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
417 * has only one pch transcoder A that all pipes can use. To avoid racy
418 * pch transcoder -> pipe lookups from interrupt code simply store the
419 * underrun statistics in crtc A. Since we never expose this anywhere
420 * nor use it outside of the fifo underrun code here using the "wrong"
421 * crtc on LPT won't cause issues.
422 */
Paulo Zanoni86642812013-04-12 17:57:57 -0300423
424 spin_lock_irqsave(&dev_priv->irq_lock, flags);
425
426 ret = !intel_crtc->pch_fifo_underrun_disabled;
427
428 if (enable == ret)
429 goto done;
430
431 intel_crtc->pch_fifo_underrun_disabled = !enable;
432
433 if (HAS_PCH_IBX(dev))
Daniel Vetterde280752013-07-04 23:35:24 +0200434 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
Paulo Zanoni86642812013-04-12 17:57:57 -0300435 else
436 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
437
438done:
439 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
440 return ret;
441}
442
443
Keith Packard7c463582008-11-04 02:03:27 -0800444void
445i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
446{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200447 u32 reg = PIPESTAT(pipe);
448 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800449
Daniel Vetterb79480b2013-06-27 17:52:10 +0200450 assert_spin_locked(&dev_priv->irq_lock);
451
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200452 if ((pipestat & mask) == mask)
453 return;
454
455 /* Enable the interrupt, clear any pending status */
456 pipestat |= mask | (mask >> 16);
457 I915_WRITE(reg, pipestat);
458 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800459}
460
461void
462i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
463{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
Keith Packard7c463582008-11-04 02:03:27 -0800466
Daniel Vetterb79480b2013-06-27 17:52:10 +0200467 assert_spin_locked(&dev_priv->irq_lock);
468
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200469 if ((pipestat & mask) == 0)
470 return;
471
472 pipestat &= ~mask;
473 I915_WRITE(reg, pipestat);
474 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800475}
476
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000477/**
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300478 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
Zhao Yakui01c66882009-10-28 05:10:00 +0000479 */
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300480static void i915_enable_asle_pipestat(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000481{
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000482 drm_i915_private_t *dev_priv = dev->dev_private;
483 unsigned long irqflags;
484
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300485 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
486 return;
487
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000488 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000489
Jani Nikulaf8987802013-04-29 13:02:53 +0300490 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
491 if (INTEL_INFO(dev)->gen >= 4)
492 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000493
494 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Zhao Yakui01c66882009-10-28 05:10:00 +0000495}
496
497/**
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700498 * i915_pipe_enabled - check if a pipe is enabled
499 * @dev: DRM device
500 * @pipe: pipe to check
501 *
502 * Reading certain registers when the pipe is disabled can hang the chip.
503 * Use this routine to make sure the PLL is running and the pipe is active
504 * before reading such registers if unsure.
505 */
506static int
507i915_pipe_enabled(struct drm_device *dev, int pipe)
508{
509 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -0200510
Daniel Vettera01025a2013-05-22 00:50:23 +0200511 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
512 /* Locking is horribly broken here, but whatever. */
513 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni71f8ba62013-05-03 12:15:39 -0300515
Daniel Vettera01025a2013-05-22 00:50:23 +0200516 return intel_crtc->active;
517 } else {
518 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
519 }
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700520}
521
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +0300522static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
523{
524 /* Gen2 doesn't have a hardware frame counter */
525 return 0;
526}
527
Keith Packard42f52ef2008-10-18 19:39:29 -0700528/* Called from drm generic code, passed a 'crtc', which
529 * we use as a pipe index
530 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700531static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700532{
533 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
534 unsigned long high_frame;
535 unsigned long low_frame;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300536 u32 high1, high2, low, pixel, vbl_start;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700537
538 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800539 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800540 "pipe %c\n", pipe_name(pipe));
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700541 return 0;
542 }
543
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300544 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
545 struct intel_crtc *intel_crtc =
546 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
547 const struct drm_display_mode *mode =
548 &intel_crtc->config.adjusted_mode;
549
550 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
551 } else {
552 enum transcoder cpu_transcoder =
553 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
554 u32 htotal;
555
556 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
557 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
558
559 vbl_start *= htotal;
560 }
561
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800562 high_frame = PIPEFRAME(pipe);
563 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100564
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700565 /*
566 * High & low register fields aren't synchronized, so make sure
567 * we get a low value that's stable across two reads of the high
568 * register.
569 */
570 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100571 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300572 low = I915_READ(low_frame);
Chris Wilson5eddb702010-09-11 13:48:45 +0100573 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700574 } while (high1 != high2);
575
Chris Wilson5eddb702010-09-11 13:48:45 +0100576 high1 >>= PIPE_FRAME_HIGH_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300577 pixel = low & PIPE_PIXEL_MASK;
Chris Wilson5eddb702010-09-11 13:48:45 +0100578 low >>= PIPE_FRAME_LOW_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300579
580 /*
581 * The frame counter increments at beginning of active.
582 * Cook up a vblank counter by also checking the pixel
583 * counter against vblank start.
584 */
585 return ((high1 << 8) | low) + (pixel >= vbl_start);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700586}
587
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700588static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800589{
590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800591 int reg = PIPE_FRMCOUNT_GM45(pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800592
593 if (!i915_pipe_enabled(dev, pipe)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +0800594 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800595 "pipe %c\n", pipe_name(pipe));
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800596 return 0;
597 }
598
599 return I915_READ(reg);
600}
601
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300602static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
Ville Syrjälä54ddcbd2013-09-23 13:02:07 +0300603{
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 uint32_t status;
606
607 if (IS_VALLEYVIEW(dev)) {
608 status = pipe == PIPE_A ?
609 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
610 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
611
612 return I915_READ(VLV_ISR) & status;
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300613 } else if (IS_GEN2(dev)) {
614 status = pipe == PIPE_A ?
615 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
616 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
617
618 return I915_READ16(ISR) & status;
619 } else if (INTEL_INFO(dev)->gen < 5) {
Ville Syrjälä54ddcbd2013-09-23 13:02:07 +0300620 status = pipe == PIPE_A ?
621 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
622 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
623
624 return I915_READ(ISR) & status;
625 } else if (INTEL_INFO(dev)->gen < 7) {
626 status = pipe == PIPE_A ?
627 DE_PIPEA_VBLANK :
628 DE_PIPEB_VBLANK;
629
630 return I915_READ(DEISR) & status;
631 } else {
632 switch (pipe) {
633 default:
634 case PIPE_A:
635 status = DE_PIPEA_VBLANK_IVB;
636 break;
637 case PIPE_B:
638 status = DE_PIPEB_VBLANK_IVB;
639 break;
640 case PIPE_C:
641 status = DE_PIPEC_VBLANK_IVB;
642 break;
643 }
644
645 return I915_READ(DEISR) & status;
646 }
647}
648
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700649static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100650 int *vpos, int *hpos)
651{
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300656 int position;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100657 int vbl_start, vbl_end, htotal, vtotal;
658 bool in_vbl = true;
659 int ret = 0;
660
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300661 if (!intel_crtc->active) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100662 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800663 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100664 return 0;
665 }
666
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300667 htotal = mode->crtc_htotal;
668 vtotal = mode->crtc_vtotal;
669 vbl_start = mode->crtc_vblank_start;
670 vbl_end = mode->crtc_vblank_end;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100671
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300672 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
673
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300674 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100675 /* No obvious pixelcount register. Only query vertical
676 * scanout position from Display scan line register.
677 */
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300678 if (IS_GEN2(dev))
679 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
680 else
681 position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
Ville Syrjälä54ddcbd2013-09-23 13:02:07 +0300682
683 /*
684 * The scanline counter increments at the leading edge
685 * of hsync, ie. it completely misses the active portion
686 * of the line. Fix up the counter at both edges of vblank
687 * to get a more accurate picture whether we're in vblank
688 * or not.
689 */
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300690 in_vbl = intel_pipe_in_vblank(dev, pipe);
Ville Syrjälä54ddcbd2013-09-23 13:02:07 +0300691 if ((in_vbl && position == vbl_start - 1) ||
692 (!in_vbl && position == vbl_end - 1))
693 position = (position + 1) % vtotal;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100694 } else {
695 /* Have access to pixelcount since start of frame.
696 * We can split this into vertical and horizontal
697 * scanout position.
698 */
699 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
700
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300701 /* convert to pixel counts */
702 vbl_start *= htotal;
703 vbl_end *= htotal;
704 vtotal *= htotal;
705 }
706
707 in_vbl = position >= vbl_start && position < vbl_end;
708
709 /*
710 * While in vblank, position will be negative
711 * counting up towards 0 at vbl_end. And outside
712 * vblank, position will be positive counting
713 * up since vbl_end.
714 */
715 if (position >= vbl_start)
716 position -= vbl_end;
717 else
718 position += vtotal - vbl_end;
719
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300720 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300721 *vpos = position;
722 *hpos = 0;
723 } else {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100724 *vpos = position / htotal;
725 *hpos = position - (*vpos * htotal);
726 }
727
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100728 /* In vblank? */
729 if (in_vbl)
730 ret |= DRM_SCANOUTPOS_INVBL;
731
732 return ret;
733}
734
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700735static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100736 int *max_error,
737 struct timeval *vblank_time,
738 unsigned flags)
739{
Chris Wilson4041b852011-01-22 10:07:56 +0000740 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100741
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700742 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000743 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100744 return -EINVAL;
745 }
746
747 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000748 crtc = intel_get_crtc_for_pipe(dev, pipe);
749 if (crtc == NULL) {
750 DRM_ERROR("Invalid crtc %d\n", pipe);
751 return -EINVAL;
752 }
753
754 if (!crtc->enabled) {
755 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
756 return -EBUSY;
757 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100758
759 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000760 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
761 vblank_time, flags,
762 crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100763}
764
Jani Nikula67c347f2013-09-17 14:26:34 +0300765static bool intel_hpd_irq_event(struct drm_device *dev,
766 struct drm_connector *connector)
Egbert Eich321a1b32013-04-11 16:00:26 +0200767{
768 enum drm_connector_status old_status;
769
770 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
771 old_status = connector->status;
772
773 connector->status = connector->funcs->detect(connector, false);
Jani Nikula67c347f2013-09-17 14:26:34 +0300774 if (old_status == connector->status)
775 return false;
776
777 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
Egbert Eich321a1b32013-04-11 16:00:26 +0200778 connector->base.id,
779 drm_get_connector_name(connector),
Jani Nikula67c347f2013-09-17 14:26:34 +0300780 drm_get_connector_status_name(old_status),
781 drm_get_connector_status_name(connector->status));
782
783 return true;
Egbert Eich321a1b32013-04-11 16:00:26 +0200784}
785
Jesse Barnes5ca58282009-03-31 14:11:15 -0700786/*
787 * Handle hotplug events outside the interrupt handler proper.
788 */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200789#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
790
Jesse Barnes5ca58282009-03-31 14:11:15 -0700791static void i915_hotplug_work_func(struct work_struct *work)
792{
793 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
794 hotplug_work);
795 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700796 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200797 struct intel_connector *intel_connector;
798 struct intel_encoder *intel_encoder;
799 struct drm_connector *connector;
800 unsigned long irqflags;
801 bool hpd_disabled = false;
Egbert Eich321a1b32013-04-11 16:00:26 +0200802 bool changed = false;
Egbert Eich142e2392013-04-11 15:57:57 +0200803 u32 hpd_event_bits;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700804
Daniel Vetter52d7ece2012-12-01 21:03:22 +0100805 /* HPD irq before everything is fully set up. */
806 if (!dev_priv->enable_hotplug_processing)
807 return;
808
Keith Packarda65e34c2011-07-25 10:04:56 -0700809 mutex_lock(&mode_config->mutex);
Jesse Barnese67189ab2011-02-11 14:44:51 -0800810 DRM_DEBUG_KMS("running encoder hotplug functions\n");
811
Egbert Eichcd569ae2013-04-16 13:36:57 +0200812 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Egbert Eich142e2392013-04-11 15:57:57 +0200813
814 hpd_event_bits = dev_priv->hpd_event_bits;
815 dev_priv->hpd_event_bits = 0;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200816 list_for_each_entry(connector, &mode_config->connector_list, head) {
817 intel_connector = to_intel_connector(connector);
818 intel_encoder = intel_connector->encoder;
819 if (intel_encoder->hpd_pin > HPD_NONE &&
820 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
821 connector->polled == DRM_CONNECTOR_POLL_HPD) {
822 DRM_INFO("HPD interrupt storm detected on connector %s: "
823 "switching from hotplug detection to polling\n",
824 drm_get_connector_name(connector));
825 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
826 connector->polled = DRM_CONNECTOR_POLL_CONNECT
827 | DRM_CONNECTOR_POLL_DISCONNECT;
828 hpd_disabled = true;
829 }
Egbert Eich142e2392013-04-11 15:57:57 +0200830 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
831 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
832 drm_get_connector_name(connector), intel_encoder->hpd_pin);
833 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200834 }
835 /* if there were no outputs to poll, poll was disabled,
836 * therefore make sure it's enabled when disabling HPD on
837 * some connectors */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200838 if (hpd_disabled) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200839 drm_kms_helper_poll_enable(dev);
Egbert Eichac4c16c2013-04-16 13:36:58 +0200840 mod_timer(&dev_priv->hotplug_reenable_timer,
841 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
842 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200843
844 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
845
Egbert Eich321a1b32013-04-11 16:00:26 +0200846 list_for_each_entry(connector, &mode_config->connector_list, head) {
847 intel_connector = to_intel_connector(connector);
848 intel_encoder = intel_connector->encoder;
849 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
850 if (intel_encoder->hot_plug)
851 intel_encoder->hot_plug(intel_encoder);
852 if (intel_hpd_irq_event(dev, connector))
853 changed = true;
854 }
855 }
Keith Packard40ee3382011-07-28 15:31:19 -0700856 mutex_unlock(&mode_config->mutex);
857
Egbert Eich321a1b32013-04-11 16:00:26 +0200858 if (changed)
859 drm_kms_helper_hotplug_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700860}
861
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200862static void ironlake_rps_change_irq_handler(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800863{
864 drm_i915_private_t *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000865 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200866 u8 new_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200867
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200868 spin_lock(&mchdev_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800869
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200870 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
871
Daniel Vetter20e4d402012-08-08 23:35:39 +0200872 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200873
Jesse Barnes7648fa92010-05-20 14:28:11 -0700874 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000875 busy_up = I915_READ(RCPREVBSYTUPAVG);
876 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800877 max_avg = I915_READ(RCBMAXAVG);
878 min_avg = I915_READ(RCBMINAVG);
879
880 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000881 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200882 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
883 new_delay = dev_priv->ips.cur_delay - 1;
884 if (new_delay < dev_priv->ips.max_delay)
885 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000886 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200887 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
888 new_delay = dev_priv->ips.cur_delay + 1;
889 if (new_delay > dev_priv->ips.min_delay)
890 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800891 }
892
Jesse Barnes7648fa92010-05-20 14:28:11 -0700893 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200894 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800895
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200896 spin_unlock(&mchdev_lock);
Daniel Vetter92703882012-08-09 16:46:01 +0200897
Jesse Barnesf97108d2010-01-29 11:27:07 -0800898 return;
899}
900
Chris Wilson549f7362010-10-19 11:19:32 +0100901static void notify_ring(struct drm_device *dev,
902 struct intel_ring_buffer *ring)
903{
Chris Wilson475553d2011-01-20 09:52:56 +0000904 if (ring->obj == NULL)
905 return;
906
Chris Wilson814e9b52013-09-23 17:33:19 -0300907 trace_i915_gem_request_complete(ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000908
Chris Wilson549f7362010-10-19 11:19:32 +0100909 wake_up_all(&ring->irq_queue);
Mika Kuoppala10cd45b2013-07-03 17:22:08 +0300910 i915_queue_hangcheck(dev);
Chris Wilson549f7362010-10-19 11:19:32 +0100911}
912
Ben Widawsky4912d042011-04-25 11:25:20 -0700913static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800914{
Ben Widawsky4912d042011-04-25 11:25:20 -0700915 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200916 rps.work);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300917 u32 pm_iir;
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100918 int new_delay, adj;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800919
Daniel Vetter59cdb632013-07-04 23:35:28 +0200920 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200921 pm_iir = dev_priv->rps.pm_iir;
922 dev_priv->rps.pm_iir = 0;
Ben Widawsky48484052013-05-28 19:22:27 -0700923 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300924 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
Daniel Vetter59cdb632013-07-04 23:35:28 +0200925 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawsky4912d042011-04-25 11:25:20 -0700926
Paulo Zanoni60611c12013-08-15 11:50:01 -0300927 /* Make sure we didn't queue anything we're not going to process. */
928 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
929
Ben Widawsky48484052013-05-28 19:22:27 -0700930 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800931 return;
932
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700933 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +0100934
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100935 adj = dev_priv->rps.last_adj;
Ville Syrjälä74250342013-06-25 21:38:11 +0300936 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100937 if (adj > 0)
938 adj *= 2;
939 else
940 adj = 1;
941 new_delay = dev_priv->rps.cur_delay + adj;
Ville Syrjälä74250342013-06-25 21:38:11 +0300942
943 /*
944 * For better performance, jump directly
945 * to RPe if we're below it.
946 */
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100947 if (new_delay < dev_priv->rps.rpe_delay)
Ville Syrjälä74250342013-06-25 21:38:11 +0300948 new_delay = dev_priv->rps.rpe_delay;
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100949 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
950 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
951 new_delay = dev_priv->rps.rpe_delay;
952 else
953 new_delay = dev_priv->rps.min_delay;
954 adj = 0;
955 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
956 if (adj < 0)
957 adj *= 2;
958 else
959 adj = -1;
960 new_delay = dev_priv->rps.cur_delay + adj;
961 } else { /* unknown event */
962 new_delay = dev_priv->rps.cur_delay;
963 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800964
Ben Widawsky79249632012-09-07 19:43:42 -0700965 /* sysfs frequency interfaces may have snuck in while servicing the
966 * interrupt
967 */
Chris Wilsondd75fdc2013-09-25 17:34:57 +0100968 if (new_delay < (int)dev_priv->rps.min_delay)
969 new_delay = dev_priv->rps.min_delay;
970 if (new_delay > (int)dev_priv->rps.max_delay)
971 new_delay = dev_priv->rps.max_delay;
972 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
973
974 if (IS_VALLEYVIEW(dev_priv->dev))
975 valleyview_set_rps(dev_priv->dev, new_delay);
976 else
977 gen6_set_rps(dev_priv->dev, new_delay);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800978
Jesse Barnes4fc688c2012-11-02 11:14:01 -0700979 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800980}
981
Ben Widawskye3689192012-05-25 16:56:22 -0700982
983/**
984 * ivybridge_parity_work - Workqueue called when a parity error interrupt
985 * occurred.
986 * @work: workqueue struct
987 *
988 * Doesn't actually do anything except notify userspace. As a consequence of
989 * this event, userspace should try to remap the bad rows since statistically
990 * it is likely the same row is more likely to go bad again.
991 */
992static void ivybridge_parity_work(struct work_struct *work)
993{
994 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
Daniel Vettera4da4fa2012-11-02 19:55:07 +0100995 l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -0700996 u32 error_status, row, bank, subbank;
Ben Widawsky35a85ac2013-09-19 11:13:41 -0700997 char *parity_event[6];
Ben Widawskye3689192012-05-25 16:56:22 -0700998 uint32_t misccpctl;
999 unsigned long flags;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001000 uint8_t slice = 0;
Ben Widawskye3689192012-05-25 16:56:22 -07001001
1002 /* We must turn off DOP level clock gating to access the L3 registers.
1003 * In order to prevent a get/put style interface, acquire struct mutex
1004 * any time we access those registers.
1005 */
1006 mutex_lock(&dev_priv->dev->struct_mutex);
1007
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001008 /* If we've screwed up tracking, just let the interrupt fire again */
1009 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1010 goto out;
1011
Ben Widawskye3689192012-05-25 16:56:22 -07001012 misccpctl = I915_READ(GEN7_MISCCPCTL);
1013 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1014 POSTING_READ(GEN7_MISCCPCTL);
1015
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001016 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1017 u32 reg;
Ben Widawskye3689192012-05-25 16:56:22 -07001018
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001019 slice--;
1020 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1021 break;
1022
1023 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1024
1025 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1026
1027 error_status = I915_READ(reg);
1028 row = GEN7_PARITY_ERROR_ROW(error_status);
1029 bank = GEN7_PARITY_ERROR_BANK(error_status);
1030 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1031
1032 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1033 POSTING_READ(reg);
1034
1035 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1036 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1037 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1038 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1039 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1040 parity_event[5] = NULL;
1041
1042 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
1043 KOBJ_CHANGE, parity_event);
1044
1045 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1046 slice, row, bank, subbank);
1047
1048 kfree(parity_event[4]);
1049 kfree(parity_event[3]);
1050 kfree(parity_event[2]);
1051 kfree(parity_event[1]);
1052 }
Ben Widawskye3689192012-05-25 16:56:22 -07001053
1054 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1055
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001056out:
1057 WARN_ON(dev_priv->l3_parity.which_slice);
Ben Widawskye3689192012-05-25 16:56:22 -07001058 spin_lock_irqsave(&dev_priv->irq_lock, flags);
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001059 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
Ben Widawskye3689192012-05-25 16:56:22 -07001060 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1061
1062 mutex_unlock(&dev_priv->dev->struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001063}
1064
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001065static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
Ben Widawskye3689192012-05-25 16:56:22 -07001066{
1067 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Ben Widawskye3689192012-05-25 16:56:22 -07001068
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001069 if (!HAS_L3_DPF(dev))
Ben Widawskye3689192012-05-25 16:56:22 -07001070 return;
1071
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001072 spin_lock(&dev_priv->irq_lock);
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001073 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001074 spin_unlock(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001075
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001076 iir &= GT_PARITY_ERROR(dev);
1077 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1078 dev_priv->l3_parity.which_slice |= 1 << 1;
1079
1080 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1081 dev_priv->l3_parity.which_slice |= 1 << 0;
1082
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001083 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001084}
1085
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001086static void ilk_gt_irq_handler(struct drm_device *dev,
1087 struct drm_i915_private *dev_priv,
1088 u32 gt_iir)
1089{
1090 if (gt_iir &
1091 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1092 notify_ring(dev, &dev_priv->ring[RCS]);
1093 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1094 notify_ring(dev, &dev_priv->ring[VCS]);
1095}
1096
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001097static void snb_gt_irq_handler(struct drm_device *dev,
1098 struct drm_i915_private *dev_priv,
1099 u32 gt_iir)
1100{
1101
Ben Widawskycc609d52013-05-28 19:22:29 -07001102 if (gt_iir &
1103 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001104 notify_ring(dev, &dev_priv->ring[RCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001105 if (gt_iir & GT_BSD_USER_INTERRUPT)
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001106 notify_ring(dev, &dev_priv->ring[VCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001107 if (gt_iir & GT_BLT_USER_INTERRUPT)
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001108 notify_ring(dev, &dev_priv->ring[BCS]);
1109
Ben Widawskycc609d52013-05-28 19:22:29 -07001110 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1111 GT_BSD_CS_ERROR_INTERRUPT |
1112 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001113 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1114 i915_handle_error(dev, false);
1115 }
Ben Widawskye3689192012-05-25 16:56:22 -07001116
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001117 if (gt_iir & GT_PARITY_ERROR(dev))
1118 ivybridge_parity_error_irq_handler(dev, gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001119}
1120
Egbert Eichb543fb02013-04-16 13:36:54 +02001121#define HPD_STORM_DETECT_PERIOD 1000
1122#define HPD_STORM_THRESHOLD 5
1123
Daniel Vetter10a504d2013-06-27 17:52:12 +02001124static inline void intel_hpd_irq_handler(struct drm_device *dev,
Daniel Vetter22062db2013-06-27 17:52:11 +02001125 u32 hotplug_trigger,
1126 const u32 *hpd)
Egbert Eichb543fb02013-04-16 13:36:54 +02001127{
1128 drm_i915_private_t *dev_priv = dev->dev_private;
Egbert Eichb543fb02013-04-16 13:36:54 +02001129 int i;
Daniel Vetter10a504d2013-06-27 17:52:12 +02001130 bool storm_detected = false;
Egbert Eichb543fb02013-04-16 13:36:54 +02001131
Daniel Vetter91d131d2013-06-27 17:52:14 +02001132 if (!hotplug_trigger)
1133 return;
1134
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001135 spin_lock(&dev_priv->irq_lock);
Egbert Eichb543fb02013-04-16 13:36:54 +02001136 for (i = 1; i < HPD_NUM_PINS; i++) {
Egbert Eich821450c2013-04-16 13:36:55 +02001137
Egbert Eichb8f102e2013-07-26 14:14:24 +02001138 WARN(((hpd[i] & hotplug_trigger) &&
1139 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1140 "Received HPD interrupt although disabled\n");
1141
Egbert Eichb543fb02013-04-16 13:36:54 +02001142 if (!(hpd[i] & hotplug_trigger) ||
1143 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1144 continue;
1145
Jani Nikulabc5ead8c2013-05-07 15:10:29 +03001146 dev_priv->hpd_event_bits |= (1 << i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001147 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1148 dev_priv->hpd_stats[i].hpd_last_jiffies
1149 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1150 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1151 dev_priv->hpd_stats[i].hpd_cnt = 0;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001152 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001153 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1154 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
Egbert Eich142e2392013-04-11 15:57:57 +02001155 dev_priv->hpd_event_bits &= ~(1 << i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001156 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
Daniel Vetter10a504d2013-06-27 17:52:12 +02001157 storm_detected = true;
Egbert Eichb543fb02013-04-16 13:36:54 +02001158 } else {
1159 dev_priv->hpd_stats[i].hpd_cnt++;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001160 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1161 dev_priv->hpd_stats[i].hpd_cnt);
Egbert Eichb543fb02013-04-16 13:36:54 +02001162 }
1163 }
1164
Daniel Vetter10a504d2013-06-27 17:52:12 +02001165 if (storm_detected)
1166 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001167 spin_unlock(&dev_priv->irq_lock);
Daniel Vetter5876fa02013-06-27 17:52:13 +02001168
Daniel Vetter645416f2013-09-02 16:22:25 +02001169 /*
1170 * Our hotplug handler can grab modeset locks (by calling down into the
1171 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1172 * queue for otherwise the flush_work in the pageflip code will
1173 * deadlock.
1174 */
1175 schedule_work(&dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02001176}
1177
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001178static void gmbus_irq_handler(struct drm_device *dev)
1179{
Daniel Vetter28c70f12012-12-01 13:53:45 +01001180 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1181
Daniel Vetter28c70f12012-12-01 13:53:45 +01001182 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001183}
1184
Daniel Vetterce99c252012-12-01 13:53:47 +01001185static void dp_aux_irq_handler(struct drm_device *dev)
1186{
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001187 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1188
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001189 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +01001190}
1191
Shuang He8bf1e9f2013-10-15 18:55:27 +01001192#if defined(CONFIG_DEBUG_FS)
Daniel Vettereba94eb2013-10-16 22:55:46 +02001193static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe,
1194 uint32_t crc0, uint32_t crc1,
1195 uint32_t crc2, uint32_t crc3,
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001196 uint32_t crc4)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001197{
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1200 struct intel_pipe_crc_entry *entry;
Damien Lespiauac2300d2013-10-15 18:55:30 +01001201 int head, tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001202
Damien Lespiau0c912c72013-10-15 18:55:37 +01001203 if (!pipe_crc->entries) {
1204 DRM_ERROR("spurious interrupt\n");
1205 return;
1206 }
1207
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001208 head = atomic_read(&pipe_crc->head);
1209 tail = atomic_read(&pipe_crc->tail);
1210
1211 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1212 DRM_ERROR("CRC buffer overflowing\n");
1213 return;
1214 }
1215
1216 entry = &pipe_crc->entries[head];
Shuang He8bf1e9f2013-10-15 18:55:27 +01001217
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001218 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
Daniel Vettereba94eb2013-10-16 22:55:46 +02001219 entry->crc[0] = crc0;
1220 entry->crc[1] = crc1;
1221 entry->crc[2] = crc2;
1222 entry->crc[3] = crc3;
1223 entry->crc[4] = crc4;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001224
1225 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1226 atomic_set(&pipe_crc->head, head);
Damien Lespiau07144422013-10-15 18:55:40 +01001227
1228 wake_up_interruptible(&pipe_crc->wq);
Shuang He8bf1e9f2013-10-15 18:55:27 +01001229}
Daniel Vettereba94eb2013-10-16 22:55:46 +02001230
1231static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1232{
1233 struct drm_i915_private *dev_priv = dev->dev_private;
1234
1235 display_pipe_crc_update(dev, pipe,
1236 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1237 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1238 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1239 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001240 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
Daniel Vettereba94eb2013-10-16 22:55:46 +02001241}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001242
1243static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
1244{
1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247 display_pipe_crc_update(dev, pipe,
1248 I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),
1249 I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
1250 I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
1251 I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001252 I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)));
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001253}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001254#else
Daniel Vetterf8c168f2013-10-16 11:49:58 +02001255static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001256static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001257#endif
1258
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001259/* The RPS events need forcewake, so we add them to a work queue and mask their
1260 * IMR bits until the work is done. Other interrupts can be processed without
1261 * the work queue. */
1262static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
Ben Widawskybaf02a12013-05-28 19:22:24 -07001263{
Daniel Vetter41a05a32013-07-04 23:35:26 +02001264 if (pm_iir & GEN6_PM_RPS_EVENTS) {
Daniel Vetter59cdb632013-07-04 23:35:28 +02001265 spin_lock(&dev_priv->irq_lock);
Daniel Vetter41a05a32013-07-04 23:35:26 +02001266 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
Paulo Zanoni4d3b3d52013-08-09 17:04:36 -03001267 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
Daniel Vetter59cdb632013-07-04 23:35:28 +02001268 spin_unlock(&dev_priv->irq_lock);
Daniel Vetter2adbee62013-07-04 23:35:27 +02001269
1270 queue_work(dev_priv->wq, &dev_priv->rps.work);
Ben Widawskybaf02a12013-05-28 19:22:24 -07001271 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001272
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001273 if (HAS_VEBOX(dev_priv->dev)) {
1274 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1275 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
Ben Widawsky12638c52013-05-28 19:22:31 -07001276
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001277 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1278 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1279 i915_handle_error(dev_priv->dev, false);
1280 }
Ben Widawsky12638c52013-05-28 19:22:31 -07001281 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001282}
1283
Daniel Vetterff1f5252012-10-02 15:10:55 +02001284static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001285{
1286 struct drm_device *dev = (struct drm_device *) arg;
1287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1288 u32 iir, gt_iir, pm_iir;
1289 irqreturn_t ret = IRQ_NONE;
1290 unsigned long irqflags;
1291 int pipe;
1292 u32 pipe_stats[I915_MAX_PIPES];
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001293
1294 atomic_inc(&dev_priv->irq_received);
1295
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001296 while (true) {
1297 iir = I915_READ(VLV_IIR);
1298 gt_iir = I915_READ(GTIIR);
1299 pm_iir = I915_READ(GEN6_PMIIR);
1300
1301 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1302 goto out;
1303
1304 ret = IRQ_HANDLED;
1305
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001306 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001307
1308 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1309 for_each_pipe(pipe) {
1310 int reg = PIPESTAT(pipe);
1311 pipe_stats[pipe] = I915_READ(reg);
1312
1313 /*
1314 * Clear the PIPE*STAT regs before the IIR
1315 */
1316 if (pipe_stats[pipe] & 0x8000ffff) {
1317 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1318 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1319 pipe_name(pipe));
1320 I915_WRITE(reg, pipe_stats[pipe]);
1321 }
1322 }
1323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1324
Jesse Barnes31acc7f2012-06-20 10:53:11 -07001325 for_each_pipe(pipe) {
1326 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1327 drm_handle_vblank(dev, pipe);
1328
1329 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1330 intel_prepare_page_flip(dev, pipe);
1331 intel_finish_page_flip(dev, pipe);
1332 }
1333 }
1334
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001335 /* Consume port. Then clear IIR or we'll miss events */
1336 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1337 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +02001338 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001339
1340 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1341 hotplug_status);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001342
1343 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1344
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001345 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1346 I915_READ(PORT_HOTPLUG_STAT);
1347 }
1348
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001349 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1350 gmbus_irq_handler(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001351
Paulo Zanoni60611c12013-08-15 11:50:01 -03001352 if (pm_iir)
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001353 gen6_rps_irq_handler(dev_priv, pm_iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001354
1355 I915_WRITE(GTIIR, gt_iir);
1356 I915_WRITE(GEN6_PMIIR, pm_iir);
1357 I915_WRITE(VLV_IIR, iir);
1358 }
1359
1360out:
1361 return ret;
1362}
1363
Adam Jackson23e81d62012-06-06 15:45:44 -04001364static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -08001365{
1366 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001367 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001368 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Jesse Barnes776ad802011-01-04 15:09:39 -08001369
Daniel Vetter91d131d2013-06-27 17:52:14 +02001370 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1371
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001372 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1373 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1374 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -08001375 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001376 port_name(port));
1377 }
Jesse Barnes776ad802011-01-04 15:09:39 -08001378
Daniel Vetterce99c252012-12-01 13:53:47 +01001379 if (pch_iir & SDE_AUX_MASK)
1380 dp_aux_irq_handler(dev);
1381
Jesse Barnes776ad802011-01-04 15:09:39 -08001382 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001383 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -08001384
1385 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1386 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1387
1388 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1389 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1390
1391 if (pch_iir & SDE_POISON)
1392 DRM_ERROR("PCH poison interrupt\n");
1393
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001394 if (pch_iir & SDE_FDI_MASK)
1395 for_each_pipe(pipe)
1396 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1397 pipe_name(pipe),
1398 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08001399
1400 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1401 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1402
1403 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1404 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1405
Jesse Barnes776ad802011-01-04 15:09:39 -08001406 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Paulo Zanoni86642812013-04-12 17:57:57 -03001407 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1408 false))
1409 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1410
1411 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1412 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1413 false))
1414 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1415}
1416
1417static void ivb_err_int_handler(struct drm_device *dev)
1418{
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 u32 err_int = I915_READ(GEN7_ERR_INT);
1421
Paulo Zanonide032bf2013-04-12 17:57:58 -03001422 if (err_int & ERR_INT_POISON)
1423 DRM_ERROR("Poison interrupt\n");
1424
Paulo Zanoni86642812013-04-12 17:57:57 -03001425 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1426 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1427 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1428
1429 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1430 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1431 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1432
1433 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1434 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1435 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1436
Shuang He8bf1e9f2013-10-15 18:55:27 +01001437 if (err_int & ERR_INT_PIPE_CRC_DONE_A)
1438 ivb_pipe_crc_update(dev, PIPE_A);
1439
1440 if (err_int & ERR_INT_PIPE_CRC_DONE_B)
1441 ivb_pipe_crc_update(dev, PIPE_B);
1442
1443 if (err_int & ERR_INT_PIPE_CRC_DONE_C)
1444 ivb_pipe_crc_update(dev, PIPE_C);
1445
Paulo Zanoni86642812013-04-12 17:57:57 -03001446 I915_WRITE(GEN7_ERR_INT, err_int);
1447}
1448
1449static void cpt_serr_int_handler(struct drm_device *dev)
1450{
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 u32 serr_int = I915_READ(SERR_INT);
1453
Paulo Zanonide032bf2013-04-12 17:57:58 -03001454 if (serr_int & SERR_INT_POISON)
1455 DRM_ERROR("PCH poison interrupt\n");
1456
Paulo Zanoni86642812013-04-12 17:57:57 -03001457 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1458 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1459 false))
1460 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1461
1462 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1463 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1464 false))
1465 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1466
1467 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1468 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1469 false))
1470 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1471
1472 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08001473}
1474
Adam Jackson23e81d62012-06-06 15:45:44 -04001475static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1476{
1477 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1478 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001479 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Adam Jackson23e81d62012-06-06 15:45:44 -04001480
Daniel Vetter91d131d2013-06-27 17:52:14 +02001481 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1482
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001483 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1484 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1485 SDE_AUDIO_POWER_SHIFT_CPT);
1486 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1487 port_name(port));
1488 }
Adam Jackson23e81d62012-06-06 15:45:44 -04001489
1490 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +01001491 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001492
1493 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001494 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001495
1496 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1497 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1498
1499 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1500 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1501
1502 if (pch_iir & SDE_FDI_MASK_CPT)
1503 for_each_pipe(pipe)
1504 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1505 pipe_name(pipe),
1506 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03001507
1508 if (pch_iir & SDE_ERROR_CPT)
1509 cpt_serr_int_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001510}
1511
Paulo Zanonic008bc62013-07-12 16:35:10 -03001512static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (de_iir & DE_AUX_CHANNEL_A)
1517 dp_aux_irq_handler(dev);
1518
1519 if (de_iir & DE_GSE)
1520 intel_opregion_asle_intr(dev);
1521
1522 if (de_iir & DE_PIPEA_VBLANK)
1523 drm_handle_vblank(dev, 0);
1524
1525 if (de_iir & DE_PIPEB_VBLANK)
1526 drm_handle_vblank(dev, 1);
1527
1528 if (de_iir & DE_POISON)
1529 DRM_ERROR("Poison interrupt\n");
1530
1531 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1532 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1533 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1534
1535 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1536 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1537 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1538
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001539 if (de_iir & DE_PIPEA_CRC_DONE)
1540 ilk_pipe_crc_update(dev, PIPE_A);
1541
1542 if (de_iir & DE_PIPEB_CRC_DONE)
1543 ilk_pipe_crc_update(dev, PIPE_B);
1544
Paulo Zanonic008bc62013-07-12 16:35:10 -03001545 if (de_iir & DE_PLANEA_FLIP_DONE) {
1546 intel_prepare_page_flip(dev, 0);
1547 intel_finish_page_flip_plane(dev, 0);
1548 }
1549
1550 if (de_iir & DE_PLANEB_FLIP_DONE) {
1551 intel_prepare_page_flip(dev, 1);
1552 intel_finish_page_flip_plane(dev, 1);
1553 }
1554
1555 /* check event from PCH */
1556 if (de_iir & DE_PCH_EVENT) {
1557 u32 pch_iir = I915_READ(SDEIIR);
1558
1559 if (HAS_PCH_CPT(dev))
1560 cpt_irq_handler(dev, pch_iir);
1561 else
1562 ibx_irq_handler(dev, pch_iir);
1563
1564 /* should clear PCH hotplug event before clear CPU irq */
1565 I915_WRITE(SDEIIR, pch_iir);
1566 }
1567
1568 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1569 ironlake_rps_change_irq_handler(dev);
1570}
1571
Paulo Zanoni9719fb92013-07-12 16:35:11 -03001572static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1573{
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int i;
1576
1577 if (de_iir & DE_ERR_INT_IVB)
1578 ivb_err_int_handler(dev);
1579
1580 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1581 dp_aux_irq_handler(dev);
1582
1583 if (de_iir & DE_GSE_IVB)
1584 intel_opregion_asle_intr(dev);
1585
1586 for (i = 0; i < 3; i++) {
1587 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1588 drm_handle_vblank(dev, i);
1589 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1590 intel_prepare_page_flip(dev, i);
1591 intel_finish_page_flip_plane(dev, i);
1592 }
1593 }
1594
1595 /* check event from PCH */
1596 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1597 u32 pch_iir = I915_READ(SDEIIR);
1598
1599 cpt_irq_handler(dev, pch_iir);
1600
1601 /* clear PCH hotplug event before clear CPU irq */
1602 I915_WRITE(SDEIIR, pch_iir);
1603 }
1604}
1605
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001606static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001607{
1608 struct drm_device *dev = (struct drm_device *) arg;
1609 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001610 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01001611 irqreturn_t ret = IRQ_NONE;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001612
1613 atomic_inc(&dev_priv->irq_received);
1614
Paulo Zanoni86642812013-04-12 17:57:57 -03001615 /* We get interrupts on unclaimed registers, so check for this before we
1616 * do any I915_{READ,WRITE}. */
Chris Wilson907b28c2013-07-19 20:36:52 +01001617 intel_uncore_check_errors(dev);
Paulo Zanoni86642812013-04-12 17:57:57 -03001618
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001619 /* disable master interrupt before clearing iir */
1620 de_ier = I915_READ(DEIER);
1621 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Paulo Zanoni23a78512013-07-12 16:35:14 -03001622 POSTING_READ(DEIER);
Chris Wilson0e434062012-05-09 21:45:44 +01001623
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001624 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1625 * interrupts will will be stored on its back queue, and then we'll be
1626 * able to process them after we restore SDEIER (as soon as we restore
1627 * it, we'll get an interrupt if SDEIIR still has something to process
1628 * due to its back queue). */
Ben Widawskyab5c6082013-04-05 13:12:41 -07001629 if (!HAS_PCH_NOP(dev)) {
1630 sde_ier = I915_READ(SDEIER);
1631 I915_WRITE(SDEIER, 0);
1632 POSTING_READ(SDEIER);
1633 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03001634
Chris Wilson0e434062012-05-09 21:45:44 +01001635 gt_iir = I915_READ(GTIIR);
1636 if (gt_iir) {
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03001637 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001638 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03001639 else
1640 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01001641 I915_WRITE(GTIIR, gt_iir);
1642 ret = IRQ_HANDLED;
1643 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001644
1645 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01001646 if (de_iir) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001647 if (INTEL_INFO(dev)->gen >= 7)
1648 ivb_display_irq_handler(dev, de_iir);
1649 else
1650 ilk_display_irq_handler(dev, de_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01001651 I915_WRITE(DEIIR, de_iir);
1652 ret = IRQ_HANDLED;
1653 }
1654
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001655 if (INTEL_INFO(dev)->gen >= 6) {
1656 u32 pm_iir = I915_READ(GEN6_PMIIR);
1657 if (pm_iir) {
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001658 gen6_rps_irq_handler(dev_priv, pm_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001659 I915_WRITE(GEN6_PMIIR, pm_iir);
1660 ret = IRQ_HANDLED;
1661 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001662 }
1663
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001664 I915_WRITE(DEIER, de_ier);
1665 POSTING_READ(DEIER);
Ben Widawskyab5c6082013-04-05 13:12:41 -07001666 if (!HAS_PCH_NOP(dev)) {
1667 I915_WRITE(SDEIER, sde_ier);
1668 POSTING_READ(SDEIER);
1669 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001670
1671 return ret;
1672}
1673
Daniel Vetter17e1df02013-09-08 21:57:13 +02001674static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1675 bool reset_completed)
1676{
1677 struct intel_ring_buffer *ring;
1678 int i;
1679
1680 /*
1681 * Notify all waiters for GPU completion events that reset state has
1682 * been changed, and that they need to restart their wait after
1683 * checking for potential errors (and bail out to drop locks if there is
1684 * a gpu reset pending so that i915_error_work_func can acquire them).
1685 */
1686
1687 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1688 for_each_ring(ring, dev_priv, i)
1689 wake_up_all(&ring->irq_queue);
1690
1691 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1692 wake_up_all(&dev_priv->pending_flip_queue);
1693
1694 /*
1695 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1696 * reset state is cleared.
1697 */
1698 if (reset_completed)
1699 wake_up_all(&dev_priv->gpu_error.reset_queue);
1700}
1701
Jesse Barnes8a905232009-07-11 16:48:03 -04001702/**
1703 * i915_error_work_func - do process context error handling work
1704 * @work: work struct
1705 *
1706 * Fire an error uevent so userspace can see that a hang or error
1707 * was detected.
1708 */
1709static void i915_error_work_func(struct work_struct *work)
1710{
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001711 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1712 work);
1713 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1714 gpu_error);
Jesse Barnes8a905232009-07-11 16:48:03 -04001715 struct drm_device *dev = dev_priv->dev;
Ben Widawskycce723e2013-07-19 09:16:42 -07001716 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1717 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1718 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
Daniel Vetter17e1df02013-09-08 21:57:13 +02001719 int ret;
Jesse Barnes8a905232009-07-11 16:48:03 -04001720
Ben Gamarif316a422009-09-14 17:48:46 -04001721 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04001722
Daniel Vetter7db0ba22012-12-06 16:23:37 +01001723 /*
1724 * Note that there's only one work item which does gpu resets, so we
1725 * need not worry about concurrent gpu resets potentially incrementing
1726 * error->reset_counter twice. We only need to take care of another
1727 * racing irq/hangcheck declaring the gpu dead for a second time. A
1728 * quick check for that is good enough: schedule_work ensures the
1729 * correct ordering between hang detection and this work item, and since
1730 * the reset in-progress bit is only ever set by code outside of this
1731 * work we don't need to worry about any other races.
1732 */
1733 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +01001734 DRM_DEBUG_DRIVER("resetting chip\n");
Daniel Vetter7db0ba22012-12-06 16:23:37 +01001735 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1736 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001737
Daniel Vetter17e1df02013-09-08 21:57:13 +02001738 /*
1739 * All state reset _must_ be completed before we update the
1740 * reset counter, for otherwise waiters might miss the reset
1741 * pending state and not properly drop locks, resulting in
1742 * deadlocks with the reset work.
1743 */
Daniel Vetterf69061b2012-12-06 09:01:42 +01001744 ret = i915_reset(dev);
1745
Daniel Vetter17e1df02013-09-08 21:57:13 +02001746 intel_display_handle_reset(dev);
1747
Daniel Vetterf69061b2012-12-06 09:01:42 +01001748 if (ret == 0) {
1749 /*
1750 * After all the gem state is reset, increment the reset
1751 * counter and wake up everyone waiting for the reset to
1752 * complete.
1753 *
1754 * Since unlock operations are a one-sided barrier only,
1755 * we need to insert a barrier here to order any seqno
1756 * updates before
1757 * the counter increment.
1758 */
1759 smp_mb__before_atomic_inc();
1760 atomic_inc(&dev_priv->gpu_error.reset_counter);
1761
1762 kobject_uevent_env(&dev->primary->kdev.kobj,
1763 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001764 } else {
1765 atomic_set(&error->reset_counter, I915_WEDGED);
Ben Gamarif316a422009-09-14 17:48:46 -04001766 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001767
Daniel Vetter17e1df02013-09-08 21:57:13 +02001768 /*
1769 * Note: The wake_up also serves as a memory barrier so that
1770 * waiters see the update value of the reset counter atomic_t.
1771 */
1772 i915_error_wake_up(dev_priv, true);
Ben Gamarif316a422009-09-14 17:48:46 -04001773 }
Jesse Barnes8a905232009-07-11 16:48:03 -04001774}
1775
Chris Wilson35aed2e2010-05-27 13:18:12 +01001776static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04001777{
1778 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07001779 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04001780 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07001781 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04001782
Chris Wilson35aed2e2010-05-27 13:18:12 +01001783 if (!eir)
1784 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04001785
Joe Perchesa70491c2012-03-18 13:00:11 -07001786 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04001787
Ben Widawskybd9854f2012-08-23 15:18:09 -07001788 i915_get_extra_instdone(dev, instdone);
1789
Jesse Barnes8a905232009-07-11 16:48:03 -04001790 if (IS_G4X(dev)) {
1791 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1792 u32 ipeir = I915_READ(IPEIR_I965);
1793
Joe Perchesa70491c2012-03-18 13:00:11 -07001794 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1795 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07001796 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1797 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07001798 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001799 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001800 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001801 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001802 }
1803 if (eir & GM45_ERROR_PAGE_TABLE) {
1804 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001805 pr_err("page table error\n");
1806 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001807 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001808 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001809 }
1810 }
1811
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001812 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001813 if (eir & I915_ERROR_PAGE_TABLE) {
1814 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07001815 pr_err("page table error\n");
1816 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04001817 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001818 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04001819 }
1820 }
1821
1822 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001823 pr_err("memory refresh error:\n");
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001824 for_each_pipe(pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07001825 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001826 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04001827 /* pipestat has already been acked */
1828 }
1829 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07001830 pr_err("instruction error\n");
1831 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07001832 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1833 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001834 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04001835 u32 ipeir = I915_READ(IPEIR);
1836
Joe Perchesa70491c2012-03-18 13:00:11 -07001837 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1838 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07001839 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04001840 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001841 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001842 } else {
1843 u32 ipeir = I915_READ(IPEIR_I965);
1844
Joe Perchesa70491c2012-03-18 13:00:11 -07001845 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1846 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07001847 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07001848 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04001849 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001850 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04001851 }
1852 }
1853
1854 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00001855 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04001856 eir = I915_READ(EIR);
1857 if (eir) {
1858 /*
1859 * some errors might have become stuck,
1860 * mask them.
1861 */
1862 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1863 I915_WRITE(EMR, I915_READ(EMR) | eir);
1864 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1865 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01001866}
1867
1868/**
1869 * i915_handle_error - handle an error interrupt
1870 * @dev: drm device
1871 *
1872 * Do some basic checking of regsiter state at error interrupt time and
1873 * dump it to the syslog. Also call i915_capture_error_state() to make
1874 * sure we get a record and make it available in debugfs. Fire a uevent
1875 * so userspace knows something bad happened (should trigger collection
1876 * of a ring dump etc.).
1877 */
Chris Wilson527f9e92010-11-11 01:16:58 +00001878void i915_handle_error(struct drm_device *dev, bool wedged)
Chris Wilson35aed2e2010-05-27 13:18:12 +01001879{
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881
1882 i915_capture_error_state(dev);
1883 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04001884
Ben Gamariba1234d2009-09-14 17:48:47 -04001885 if (wedged) {
Daniel Vetterf69061b2012-12-06 09:01:42 +01001886 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1887 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04001888
Ben Gamari11ed50e2009-09-14 17:48:45 -04001889 /*
Daniel Vetter17e1df02013-09-08 21:57:13 +02001890 * Wakeup waiting processes so that the reset work function
1891 * i915_error_work_func doesn't deadlock trying to grab various
1892 * locks. By bumping the reset counter first, the woken
1893 * processes will see a reset in progress and back off,
1894 * releasing their locks and then wait for the reset completion.
1895 * We must do this for _all_ gpu waiters that might hold locks
1896 * that the reset work needs to acquire.
1897 *
1898 * Note: The wake_up serves as the required memory barrier to
1899 * ensure that the waiters see the updated value of the reset
1900 * counter atomic_t.
Ben Gamari11ed50e2009-09-14 17:48:45 -04001901 */
Daniel Vetter17e1df02013-09-08 21:57:13 +02001902 i915_error_wake_up(dev_priv, false);
Ben Gamari11ed50e2009-09-14 17:48:45 -04001903 }
1904
Daniel Vetter122f46b2013-09-04 17:36:14 +02001905 /*
1906 * Our reset work can grab modeset locks (since it needs to reset the
1907 * state of outstanding pagelips). Hence it must not be run on our own
1908 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1909 * code will deadlock.
1910 */
1911 schedule_work(&dev_priv->gpu_error.work);
Jesse Barnes8a905232009-07-11 16:48:03 -04001912}
1913
Ville Syrjälä21ad8332013-02-19 15:16:39 +02001914static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001915{
1916 drm_i915_private_t *dev_priv = dev->dev_private;
1917 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00001919 struct drm_i915_gem_object *obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001920 struct intel_unpin_work *work;
1921 unsigned long flags;
1922 bool stall_detected;
1923
1924 /* Ignore early vblank irqs */
1925 if (intel_crtc == NULL)
1926 return;
1927
1928 spin_lock_irqsave(&dev->event_lock, flags);
1929 work = intel_crtc->unpin_work;
1930
Chris Wilsone7d841c2012-12-03 11:36:30 +00001931 if (work == NULL ||
1932 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1933 !work->enable_stall_check) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001934 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1935 spin_unlock_irqrestore(&dev->event_lock, flags);
1936 return;
1937 }
1938
1939 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
Chris Wilson05394f32010-11-08 19:18:58 +00001940 obj = work->pending_flip_obj;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001941 if (INTEL_INFO(dev)->gen >= 4) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001942 int dspsurf = DSPSURF(intel_crtc->plane);
Armin Reese446f2542012-03-30 16:20:16 -07001943 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
Ben Widawskyf343c5f2013-07-05 14:41:04 -07001944 i915_gem_obj_ggtt_offset(obj);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001945 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001946 int dspaddr = DSPADDR(intel_crtc->plane);
Ben Widawskyf343c5f2013-07-05 14:41:04 -07001947 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
Ville Syrjälä01f2c772011-12-20 00:06:49 +02001948 crtc->y * crtc->fb->pitches[0] +
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001949 crtc->x * crtc->fb->bits_per_pixel/8);
1950 }
1951
1952 spin_unlock_irqrestore(&dev->event_lock, flags);
1953
1954 if (stall_detected) {
1955 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1956 intel_prepare_page_flip(dev, intel_crtc->plane);
1957 }
1958}
1959
Keith Packard42f52ef2008-10-18 19:39:29 -07001960/* Called from drm generic code, passed 'crtc' which
1961 * we use as a pipe index
1962 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001963static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001964{
1965 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07001966 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001967
Chris Wilson5eddb702010-09-11 13:48:45 +01001968 if (!i915_pipe_enabled(dev, pipe))
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08001969 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001970
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001971 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07001972 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08001973 i915_enable_pipestat(dev_priv, pipe,
1974 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Keith Packarde9d21d72008-10-16 11:31:38 -07001975 else
Keith Packard7c463582008-11-04 02:03:27 -08001976 i915_enable_pipestat(dev_priv, pipe,
1977 PIPE_VBLANK_INTERRUPT_ENABLE);
Chris Wilson8692d00e2011-02-05 10:08:21 +00001978
1979 /* maintain vblank delivery even in deep C-states */
1980 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02001981 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00001983
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001984 return 0;
1985}
1986
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001987static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07001988{
1989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1990 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03001991 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1992 DE_PIPE_VBLANK_ILK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07001993
1994 if (!i915_pipe_enabled(dev, pipe))
1995 return -EINVAL;
1996
1997 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03001998 ironlake_enable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001999 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2000
2001 return 0;
2002}
2003
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002004static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2005{
2006 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2007 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002008 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002009
2010 if (!i915_pipe_enabled(dev, pipe))
2011 return -EINVAL;
2012
2013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002014 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002015 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002016 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002017 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002018 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002019 I915_WRITE(VLV_IMR, imr);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002020 i915_enable_pipestat(dev_priv, pipe,
2021 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002022 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2023
2024 return 0;
2025}
2026
Keith Packard42f52ef2008-10-18 19:39:29 -07002027/* Called from drm generic code, passed 'crtc' which
2028 * we use as a pipe index
2029 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002030static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002031{
2032 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002033 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002034
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002035 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002036 if (dev_priv->info->gen == 3)
Daniel Vetter6b26c862012-04-24 14:04:12 +02002037 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
Chris Wilson8692d00e2011-02-05 10:08:21 +00002038
Jesse Barnesf796cf82011-04-07 13:58:17 -07002039 i915_disable_pipestat(dev_priv, pipe,
2040 PIPE_VBLANK_INTERRUPT_ENABLE |
2041 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2042 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2043}
2044
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002045static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002046{
2047 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2048 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002049 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2050 DE_PIPE_VBLANK_ILK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002051
2052 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002053 ironlake_disable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002054 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2055}
2056
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002057static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2058{
2059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2060 unsigned long irqflags;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002061 u32 imr;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002062
2063 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002064 i915_disable_pipestat(dev_priv, pipe,
2065 PIPE_START_VBLANK_INTERRUPT_ENABLE);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002066 imr = I915_READ(VLV_IMR);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002067 if (pipe == 0)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002068 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002069 else
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002070 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002071 I915_WRITE(VLV_IMR, imr);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002072 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2073}
2074
Chris Wilson893eead2010-10-27 14:44:35 +01002075static u32
2076ring_last_seqno(struct intel_ring_buffer *ring)
Zou Nan hai852835f2010-05-21 09:08:56 +08002077{
Chris Wilson893eead2010-10-27 14:44:35 +01002078 return list_entry(ring->request_list.prev,
2079 struct drm_i915_gem_request, list)->seqno;
2080}
2081
Chris Wilson9107e9d2013-06-10 11:20:20 +01002082static bool
2083ring_idle(struct intel_ring_buffer *ring, u32 seqno)
Chris Wilson893eead2010-10-27 14:44:35 +01002084{
Chris Wilson9107e9d2013-06-10 11:20:20 +01002085 return (list_empty(&ring->request_list) ||
2086 i915_seqno_passed(seqno, ring_last_seqno(ring)));
Ben Gamarif65d9422009-09-14 17:48:44 -04002087}
2088
Chris Wilson6274f212013-06-10 11:20:21 +01002089static struct intel_ring_buffer *
2090semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
Chris Wilsona24a11e2013-03-14 17:52:05 +02002091{
2092 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Chris Wilson6274f212013-06-10 11:20:21 +01002093 u32 cmd, ipehr, acthd, acthd_min;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002094
2095 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2096 if ((ipehr & ~(0x3 << 16)) !=
2097 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
Chris Wilson6274f212013-06-10 11:20:21 +01002098 return NULL;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002099
2100 /* ACTHD is likely pointing to the dword after the actual command,
2101 * so scan backwards until we find the MBOX.
2102 */
Chris Wilson6274f212013-06-10 11:20:21 +01002103 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002104 acthd_min = max((int)acthd - 3 * 4, 0);
2105 do {
2106 cmd = ioread32(ring->virtual_start + acthd);
2107 if (cmd == ipehr)
2108 break;
2109
2110 acthd -= 4;
2111 if (acthd < acthd_min)
Chris Wilson6274f212013-06-10 11:20:21 +01002112 return NULL;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002113 } while (1);
2114
Chris Wilson6274f212013-06-10 11:20:21 +01002115 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2116 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
Chris Wilsona24a11e2013-03-14 17:52:05 +02002117}
2118
Chris Wilson6274f212013-06-10 11:20:21 +01002119static int semaphore_passed(struct intel_ring_buffer *ring)
2120{
2121 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2122 struct intel_ring_buffer *signaller;
2123 u32 seqno, ctl;
2124
2125 ring->hangcheck.deadlock = true;
2126
2127 signaller = semaphore_waits_for(ring, &seqno);
2128 if (signaller == NULL || signaller->hangcheck.deadlock)
2129 return -1;
2130
2131 /* cursory check for an unkickable deadlock */
2132 ctl = I915_READ_CTL(signaller);
2133 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2134 return -1;
2135
2136 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2137}
2138
2139static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2140{
2141 struct intel_ring_buffer *ring;
2142 int i;
2143
2144 for_each_ring(ring, dev_priv, i)
2145 ring->hangcheck.deadlock = false;
2146}
2147
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002148static enum intel_ring_hangcheck_action
2149ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002150{
2151 struct drm_device *dev = ring->dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002153 u32 tmp;
2154
Chris Wilson6274f212013-06-10 11:20:21 +01002155 if (ring->hangcheck.acthd != acthd)
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002156 return HANGCHECK_ACTIVE;
Chris Wilson6274f212013-06-10 11:20:21 +01002157
Chris Wilson9107e9d2013-06-10 11:20:20 +01002158 if (IS_GEN2(dev))
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002159 return HANGCHECK_HUNG;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002160
2161 /* Is the chip hanging on a WAIT_FOR_EVENT?
2162 * If so we can simply poke the RB_WAIT bit
2163 * and break the hang. This should work on
2164 * all but the second generation chipsets.
2165 */
2166 tmp = I915_READ_CTL(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002167 if (tmp & RING_WAIT) {
2168 DRM_ERROR("Kicking stuck wait on %s\n",
2169 ring->name);
Chris Wilson09e14bf2013-10-10 09:37:19 +01002170 i915_handle_error(dev, false);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002171 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002172 return HANGCHECK_KICK;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002173 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002174
Chris Wilson6274f212013-06-10 11:20:21 +01002175 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2176 switch (semaphore_passed(ring)) {
2177 default:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002178 return HANGCHECK_HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002179 case 1:
2180 DRM_ERROR("Kicking stuck semaphore on %s\n",
2181 ring->name);
Chris Wilson09e14bf2013-10-10 09:37:19 +01002182 i915_handle_error(dev, false);
Chris Wilson6274f212013-06-10 11:20:21 +01002183 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002184 return HANGCHECK_KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002185 case 0:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002186 return HANGCHECK_WAIT;
Chris Wilson6274f212013-06-10 11:20:21 +01002187 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002188 }
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002189
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002190 return HANGCHECK_HUNG;
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002191}
2192
Ben Gamarif65d9422009-09-14 17:48:44 -04002193/**
2194 * This is called when the chip hasn't reported back with completed
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002195 * batchbuffers in a long time. We keep track per ring seqno progress and
2196 * if there are no progress, hangcheck score for that ring is increased.
2197 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2198 * we kick the ring. If we see no progress on three subsequent calls
2199 * we assume chip is wedged and try to fix it by resetting the chip.
Ben Gamarif65d9422009-09-14 17:48:44 -04002200 */
Damien Lespiaua658b5d2013-08-08 22:28:56 +01002201static void i915_hangcheck_elapsed(unsigned long data)
Ben Gamarif65d9422009-09-14 17:48:44 -04002202{
2203 struct drm_device *dev = (struct drm_device *)data;
2204 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonb4519512012-05-11 14:29:30 +01002205 struct intel_ring_buffer *ring;
Chris Wilsonb4519512012-05-11 14:29:30 +01002206 int i;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002207 int busy_count = 0, rings_hung = 0;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002208 bool stuck[I915_NUM_RINGS] = { 0 };
2209#define BUSY 1
2210#define KICK 5
2211#define HUNG 20
2212#define FIRE 30
Chris Wilson893eead2010-10-27 14:44:35 +01002213
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07002214 if (!i915_enable_hangcheck)
2215 return;
2216
Chris Wilsonb4519512012-05-11 14:29:30 +01002217 for_each_ring(ring, dev_priv, i) {
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002218 u32 seqno, acthd;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002219 bool busy = true;
Chris Wilsonb4519512012-05-11 14:29:30 +01002220
Chris Wilson6274f212013-06-10 11:20:21 +01002221 semaphore_clear_deadlocks(dev_priv);
2222
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002223 seqno = ring->get_seqno(ring, false);
2224 acthd = intel_ring_get_active_head(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01002225
Chris Wilson9107e9d2013-06-10 11:20:20 +01002226 if (ring->hangcheck.seqno == seqno) {
2227 if (ring_idle(ring, seqno)) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002228 ring->hangcheck.action = HANGCHECK_IDLE;
2229
Chris Wilson9107e9d2013-06-10 11:20:20 +01002230 if (waitqueue_active(&ring->irq_queue)) {
2231 /* Issue a wake-up to catch stuck h/w. */
Chris Wilson094f9a52013-09-25 17:34:55 +01002232 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2233 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2234 ring->name);
2235 wake_up_all(&ring->irq_queue);
2236 }
2237 /* Safeguard against driver failure */
2238 ring->hangcheck.score += BUSY;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002239 } else
2240 busy = false;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002241 } else {
Chris Wilson6274f212013-06-10 11:20:21 +01002242 /* We always increment the hangcheck score
2243 * if the ring is busy and still processing
2244 * the same request, so that no single request
2245 * can run indefinitely (such as a chain of
2246 * batches). The only time we do not increment
2247 * the hangcheck score on this ring, if this
2248 * ring is in a legitimate wait for another
2249 * ring. In that case the waiting ring is a
2250 * victim and we want to be sure we catch the
2251 * right culprit. Then every time we do kick
2252 * the ring, add a small increment to the
2253 * score so that we can catch a batch that is
2254 * being repeatedly kicked and so responsible
2255 * for stalling the machine.
2256 */
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002257 ring->hangcheck.action = ring_stuck(ring,
2258 acthd);
2259
2260 switch (ring->hangcheck.action) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002261 case HANGCHECK_IDLE:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002262 case HANGCHECK_WAIT:
Chris Wilson6274f212013-06-10 11:20:21 +01002263 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002264 case HANGCHECK_ACTIVE:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002265 ring->hangcheck.score += BUSY;
Chris Wilson6274f212013-06-10 11:20:21 +01002266 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002267 case HANGCHECK_KICK:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002268 ring->hangcheck.score += KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002269 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002270 case HANGCHECK_HUNG:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002271 ring->hangcheck.score += HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002272 stuck[i] = true;
2273 break;
2274 }
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002275 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002276 } else {
Mika Kuoppalada661462013-09-06 16:03:28 +03002277 ring->hangcheck.action = HANGCHECK_ACTIVE;
2278
Chris Wilson9107e9d2013-06-10 11:20:20 +01002279 /* Gradually reduce the count so that we catch DoS
2280 * attempts across multiple batches.
2281 */
2282 if (ring->hangcheck.score > 0)
2283 ring->hangcheck.score--;
Chris Wilsond1e61e72012-04-10 17:00:41 +01002284 }
2285
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002286 ring->hangcheck.seqno = seqno;
2287 ring->hangcheck.acthd = acthd;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002288 busy_count += busy;
Chris Wilson893eead2010-10-27 14:44:35 +01002289 }
Eric Anholtb9201c12010-01-08 14:25:16 -08002290
Mika Kuoppala92cab732013-05-24 17:16:07 +03002291 for_each_ring(ring, dev_priv, i) {
Chris Wilson9107e9d2013-06-10 11:20:20 +01002292 if (ring->hangcheck.score > FIRE) {
Daniel Vetterb8d88d12013-08-28 10:57:59 +02002293 DRM_INFO("%s on %s\n",
2294 stuck[i] ? "stuck" : "no progress",
2295 ring->name);
Chris Wilsona43adf02013-06-10 11:20:22 +01002296 rings_hung++;
Mika Kuoppala92cab732013-05-24 17:16:07 +03002297 }
2298 }
2299
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002300 if (rings_hung)
2301 return i915_handle_error(dev, true);
Ben Gamarif65d9422009-09-14 17:48:44 -04002302
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002303 if (busy_count)
2304 /* Reset timer case chip hangs without another request
2305 * being added */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002306 i915_queue_hangcheck(dev);
2307}
2308
2309void i915_queue_hangcheck(struct drm_device *dev)
2310{
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 if (!i915_enable_hangcheck)
2313 return;
2314
2315 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2316 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04002317}
2318
Paulo Zanoni91738a92013-06-05 14:21:51 -03002319static void ibx_irq_preinstall(struct drm_device *dev)
2320{
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323 if (HAS_PCH_NOP(dev))
2324 return;
2325
2326 /* south display irq */
2327 I915_WRITE(SDEIMR, 0xffffffff);
2328 /*
2329 * SDEIER is also touched by the interrupt handler to work around missed
2330 * PCH interrupts. Hence we can't update it after the interrupt handler
2331 * is enabled - instead we unconditionally enable all PCH interrupt
2332 * sources here, but then only unmask them as needed with SDEIMR.
2333 */
2334 I915_WRITE(SDEIER, 0xffffffff);
2335 POSTING_READ(SDEIER);
2336}
2337
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02002338static void gen5_gt_irq_preinstall(struct drm_device *dev)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341
2342 /* and GT */
2343 I915_WRITE(GTIMR, 0xffffffff);
2344 I915_WRITE(GTIER, 0x0);
2345 POSTING_READ(GTIER);
2346
2347 if (INTEL_INFO(dev)->gen >= 6) {
2348 /* and PM */
2349 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2350 I915_WRITE(GEN6_PMIER, 0x0);
2351 POSTING_READ(GEN6_PMIER);
2352 }
2353}
2354
Linus Torvalds1da177e2005-04-16 15:20:36 -07002355/* drm_dma.h hooks
2356*/
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002357static void ironlake_irq_preinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002358{
2359 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2360
Jesse Barnes46979952011-04-07 13:53:55 -07002361 atomic_set(&dev_priv->irq_received, 0);
2362
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002363 I915_WRITE(HWSTAM, 0xeffe);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01002364
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002365 I915_WRITE(DEIMR, 0xffffffff);
2366 I915_WRITE(DEIER, 0x0);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002367 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002368
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02002369 gen5_gt_irq_preinstall(dev);
Zhenyu Wangc6501562009-11-03 18:57:21 +00002370
Paulo Zanoni91738a92013-06-05 14:21:51 -03002371 ibx_irq_preinstall(dev);
Ben Widawsky7d991632013-05-28 19:22:25 -07002372}
2373
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002374static void valleyview_irq_preinstall(struct drm_device *dev)
2375{
2376 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2377 int pipe;
2378
2379 atomic_set(&dev_priv->irq_received, 0);
2380
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002381 /* VLV magic */
2382 I915_WRITE(VLV_IMR, 0);
2383 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2384 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2385 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2386
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002387 /* and GT */
2388 I915_WRITE(GTIIR, I915_READ(GTIIR));
2389 I915_WRITE(GTIIR, I915_READ(GTIIR));
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02002390
2391 gen5_gt_irq_preinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002392
2393 I915_WRITE(DPINVGTT, 0xff);
2394
2395 I915_WRITE(PORT_HOTPLUG_EN, 0);
2396 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2397 for_each_pipe(pipe)
2398 I915_WRITE(PIPESTAT(pipe), 0xffff);
2399 I915_WRITE(VLV_IIR, 0xffffffff);
2400 I915_WRITE(VLV_IMR, 0xffffffff);
2401 I915_WRITE(VLV_IER, 0x0);
2402 POSTING_READ(VLV_IER);
2403}
2404
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002405static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07002406{
2407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002408 struct drm_mode_config *mode_config = &dev->mode_config;
2409 struct intel_encoder *intel_encoder;
Daniel Vetterfee884e2013-07-04 23:35:21 +02002410 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
Keith Packard7fe0b972011-09-19 13:31:02 -07002411
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002412 if (HAS_PCH_IBX(dev)) {
Daniel Vetterfee884e2013-07-04 23:35:21 +02002413 hotplug_irqs = SDE_HOTPLUG_MASK;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002414 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
Egbert Eichcd569ae2013-04-16 13:36:57 +02002415 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02002416 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002417 } else {
Daniel Vetterfee884e2013-07-04 23:35:21 +02002418 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002419 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
Egbert Eichcd569ae2013-04-16 13:36:57 +02002420 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02002421 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002422 }
2423
Daniel Vetterfee884e2013-07-04 23:35:21 +02002424 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002425
2426 /*
2427 * Enable digital hotplug on the PCH, and configure the DP short pulse
2428 * duration to 2ms (which is the minimum in the Display Port spec)
2429 *
2430 * This register is the same on all known PCH chips.
2431 */
Keith Packard7fe0b972011-09-19 13:31:02 -07002432 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2433 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2434 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2435 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2436 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2437 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2438}
2439
Paulo Zanonid46da432013-02-08 17:35:15 -02002440static void ibx_irq_postinstall(struct drm_device *dev)
2441{
2442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01002443 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02002444
Daniel Vetter692a04c2013-05-29 21:43:05 +02002445 if (HAS_PCH_NOP(dev))
2446 return;
2447
Paulo Zanoni86642812013-04-12 17:57:57 -03002448 if (HAS_PCH_IBX(dev)) {
2449 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
Paulo Zanonide032bf2013-04-12 17:57:58 -03002450 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
Paulo Zanoni86642812013-04-12 17:57:57 -03002451 } else {
2452 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2453
2454 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2455 }
Ben Widawskyab5c6082013-04-05 13:12:41 -07002456
Paulo Zanonid46da432013-02-08 17:35:15 -02002457 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2458 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02002459}
2460
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002461static void gen5_gt_irq_postinstall(struct drm_device *dev)
2462{
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 u32 pm_irqs, gt_irqs;
2465
2466 pm_irqs = gt_irqs = 0;
2467
2468 dev_priv->gt_irq_mask = ~0;
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002469 if (HAS_L3_DPF(dev)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002470 /* L3 parity interrupt is always unmasked. */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07002471 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2472 gt_irqs |= GT_PARITY_ERROR(dev);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002473 }
2474
2475 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2476 if (IS_GEN5(dev)) {
2477 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2478 ILK_BSD_USER_INTERRUPT;
2479 } else {
2480 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2481 }
2482
2483 I915_WRITE(GTIIR, I915_READ(GTIIR));
2484 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2485 I915_WRITE(GTIER, gt_irqs);
2486 POSTING_READ(GTIER);
2487
2488 if (INTEL_INFO(dev)->gen >= 6) {
2489 pm_irqs |= GEN6_PM_RPS_EVENTS;
2490
2491 if (HAS_VEBOX(dev))
2492 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2493
Paulo Zanoni605cd252013-08-06 18:57:15 -03002494 dev_priv->pm_irq_mask = 0xffffffff;
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002495 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
Paulo Zanoni605cd252013-08-06 18:57:15 -03002496 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002497 I915_WRITE(GEN6_PMIER, pm_irqs);
2498 POSTING_READ(GEN6_PMIER);
2499 }
2500}
2501
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002502static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002503{
Daniel Vetter4bc9d432013-06-27 13:44:58 +02002504 unsigned long irqflags;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002505 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03002506 u32 display_mask, extra_mask;
2507
2508 if (INTEL_INFO(dev)->gen >= 7) {
2509 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2510 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2511 DE_PLANEB_FLIP_DONE_IVB |
2512 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2513 DE_ERR_INT_IVB);
2514 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2515 DE_PIPEA_VBLANK_IVB);
2516
2517 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2518 } else {
2519 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2520 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002521 DE_AUX_CHANNEL_A |
2522 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2523 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2524 DE_POISON);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03002525 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2526 }
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002527
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002528 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002529
2530 /* should always can generate irq */
2531 I915_WRITE(DEIIR, I915_READ(DEIIR));
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002532 I915_WRITE(DEIMR, dev_priv->irq_mask);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03002533 I915_WRITE(DEIER, display_mask | extra_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002534 POSTING_READ(DEIER);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002535
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002536 gen5_gt_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002537
Paulo Zanonid46da432013-02-08 17:35:15 -02002538 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07002539
Jesse Barnesf97108d2010-01-29 11:27:07 -08002540 if (IS_IRONLAKE_M(dev)) {
Daniel Vetter6005ce42013-06-27 13:44:59 +02002541 /* Enable PCU event interrupts
2542 *
2543 * spinlocking not required here for correctness since interrupt
Daniel Vetter4bc9d432013-06-27 13:44:58 +02002544 * setup is guaranteed to run in single-threaded context. But we
2545 * need it to make the assert_spin_locked happy. */
2546 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf97108d2010-01-29 11:27:07 -08002547 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
Daniel Vetter4bc9d432013-06-27 13:44:58 +02002548 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Jesse Barnesf97108d2010-01-29 11:27:07 -08002549 }
2550
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002551 return 0;
2552}
2553
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002554static int valleyview_irq_postinstall(struct drm_device *dev)
2555{
2556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002557 u32 enable_mask;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002558 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
Daniel Vetterb79480b2013-06-27 17:52:10 +02002559 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002560
2561 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002562 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2563 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2564 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002565 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2566
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002567 /*
2568 *Leave vblank interrupts masked initially. enable/disable will
2569 * toggle them based on usage.
2570 */
2571 dev_priv->irq_mask = (~enable_mask) |
2572 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2573 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002574
Daniel Vetter20afbda2012-12-11 14:05:07 +01002575 I915_WRITE(PORT_HOTPLUG_EN, 0);
2576 POSTING_READ(PORT_HOTPLUG_EN);
2577
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002578 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2579 I915_WRITE(VLV_IER, enable_mask);
2580 I915_WRITE(VLV_IIR, 0xffffffff);
2581 I915_WRITE(PIPESTAT(0), 0xffff);
2582 I915_WRITE(PIPESTAT(1), 0xffff);
2583 POSTING_READ(VLV_IER);
2584
Daniel Vetterb79480b2013-06-27 17:52:10 +02002585 /* Interrupt setup is already guaranteed to be single-threaded, this is
2586 * just to make the assert_spin_locked check happy. */
2587 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002588 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01002589 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002590 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
Daniel Vetterb79480b2013-06-27 17:52:10 +02002591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002592
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002593 I915_WRITE(VLV_IIR, 0xffffffff);
2594 I915_WRITE(VLV_IIR, 0xffffffff);
2595
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02002596 gen5_gt_irq_postinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002597
2598 /* ack & enable invalid PTE error interrupts */
2599#if 0 /* FIXME: add support to irq handler for checking these bits */
2600 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2601 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2602#endif
2603
2604 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01002605
2606 return 0;
2607}
2608
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002609static void valleyview_irq_uninstall(struct drm_device *dev)
2610{
2611 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2612 int pipe;
2613
2614 if (!dev_priv)
2615 return;
2616
Egbert Eichac4c16c2013-04-16 13:36:58 +02002617 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2618
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002619 for_each_pipe(pipe)
2620 I915_WRITE(PIPESTAT(pipe), 0xffff);
2621
2622 I915_WRITE(HWSTAM, 0xffffffff);
2623 I915_WRITE(PORT_HOTPLUG_EN, 0);
2624 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2625 for_each_pipe(pipe)
2626 I915_WRITE(PIPESTAT(pipe), 0xffff);
2627 I915_WRITE(VLV_IIR, 0xffffffff);
2628 I915_WRITE(VLV_IMR, 0xffffffff);
2629 I915_WRITE(VLV_IER, 0x0);
2630 POSTING_READ(VLV_IER);
2631}
2632
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002633static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002634{
2635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07002636
2637 if (!dev_priv)
2638 return;
2639
Egbert Eichac4c16c2013-04-16 13:36:58 +02002640 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2641
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002642 I915_WRITE(HWSTAM, 0xffffffff);
2643
2644 I915_WRITE(DEIMR, 0xffffffff);
2645 I915_WRITE(DEIER, 0x0);
2646 I915_WRITE(DEIIR, I915_READ(DEIIR));
Paulo Zanoni86642812013-04-12 17:57:57 -03002647 if (IS_GEN7(dev))
2648 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002649
2650 I915_WRITE(GTIMR, 0xffffffff);
2651 I915_WRITE(GTIER, 0x0);
2652 I915_WRITE(GTIIR, I915_READ(GTIIR));
Keith Packard192aac1f2011-09-20 10:12:44 -07002653
Ben Widawskyab5c6082013-04-05 13:12:41 -07002654 if (HAS_PCH_NOP(dev))
2655 return;
2656
Keith Packard192aac1f2011-09-20 10:12:44 -07002657 I915_WRITE(SDEIMR, 0xffffffff);
2658 I915_WRITE(SDEIER, 0x0);
2659 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
Paulo Zanoni86642812013-04-12 17:57:57 -03002660 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2661 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
Zhenyu Wang036a4a72009-06-08 14:40:19 +08002662}
2663
Chris Wilsonc2798b12012-04-22 21:13:57 +01002664static void i8xx_irq_preinstall(struct drm_device * dev)
2665{
2666 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2667 int pipe;
2668
2669 atomic_set(&dev_priv->irq_received, 0);
2670
2671 for_each_pipe(pipe)
2672 I915_WRITE(PIPESTAT(pipe), 0);
2673 I915_WRITE16(IMR, 0xffff);
2674 I915_WRITE16(IER, 0x0);
2675 POSTING_READ16(IER);
2676}
2677
2678static int i8xx_irq_postinstall(struct drm_device *dev)
2679{
2680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2681
Chris Wilsonc2798b12012-04-22 21:13:57 +01002682 I915_WRITE16(EMR,
2683 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2684
2685 /* Unmask the interrupts that we always want on. */
2686 dev_priv->irq_mask =
2687 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2688 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2689 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2690 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2691 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2692 I915_WRITE16(IMR, dev_priv->irq_mask);
2693
2694 I915_WRITE16(IER,
2695 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2696 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2697 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2698 I915_USER_INTERRUPT);
2699 POSTING_READ16(IER);
2700
2701 return 0;
2702}
2703
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002704/*
2705 * Returns true when a page flip has completed.
2706 */
2707static bool i8xx_handle_vblank(struct drm_device *dev,
2708 int pipe, u16 iir)
2709{
2710 drm_i915_private_t *dev_priv = dev->dev_private;
2711 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2712
2713 if (!drm_handle_vblank(dev, pipe))
2714 return false;
2715
2716 if ((iir & flip_pending) == 0)
2717 return false;
2718
2719 intel_prepare_page_flip(dev, pipe);
2720
2721 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2722 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2723 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2724 * the flip is completed (no longer pending). Since this doesn't raise
2725 * an interrupt per se, we watch for the change at vblank.
2726 */
2727 if (I915_READ16(ISR) & flip_pending)
2728 return false;
2729
2730 intel_finish_page_flip(dev, pipe);
2731
2732 return true;
2733}
2734
Daniel Vetterff1f5252012-10-02 15:10:55 +02002735static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01002736{
2737 struct drm_device *dev = (struct drm_device *) arg;
2738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002739 u16 iir, new_iir;
2740 u32 pipe_stats[2];
2741 unsigned long irqflags;
Chris Wilsonc2798b12012-04-22 21:13:57 +01002742 int pipe;
2743 u16 flip_mask =
2744 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2745 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2746
2747 atomic_inc(&dev_priv->irq_received);
2748
2749 iir = I915_READ16(IIR);
2750 if (iir == 0)
2751 return IRQ_NONE;
2752
2753 while (iir & ~flip_mask) {
2754 /* Can't rely on pipestat interrupt bit in iir as it might
2755 * have been cleared after the pipestat interrupt was received.
2756 * It doesn't set the bit in iir again, but it still produces
2757 * interrupts (for non-MSI).
2758 */
2759 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2760 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2761 i915_handle_error(dev, false);
2762
2763 for_each_pipe(pipe) {
2764 int reg = PIPESTAT(pipe);
2765 pipe_stats[pipe] = I915_READ(reg);
2766
2767 /*
2768 * Clear the PIPE*STAT regs before the IIR
2769 */
2770 if (pipe_stats[pipe] & 0x8000ffff) {
2771 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2772 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2773 pipe_name(pipe));
2774 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002775 }
2776 }
2777 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2778
2779 I915_WRITE16(IIR, iir & ~flip_mask);
2780 new_iir = I915_READ16(IIR); /* Flush posted writes */
2781
Daniel Vetterd05c6172012-04-26 23:28:09 +02002782 i915_update_dri1_breadcrumb(dev);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002783
2784 if (iir & I915_USER_INTERRUPT)
2785 notify_ring(dev, &dev_priv->ring[RCS]);
2786
2787 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002788 i8xx_handle_vblank(dev, 0, iir))
2789 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002790
2791 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002792 i8xx_handle_vblank(dev, 1, iir))
2793 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
Chris Wilsonc2798b12012-04-22 21:13:57 +01002794
2795 iir = new_iir;
2796 }
2797
2798 return IRQ_HANDLED;
2799}
2800
2801static void i8xx_irq_uninstall(struct drm_device * dev)
2802{
2803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2804 int pipe;
2805
Chris Wilsonc2798b12012-04-22 21:13:57 +01002806 for_each_pipe(pipe) {
2807 /* Clear enable bits; then clear status bits */
2808 I915_WRITE(PIPESTAT(pipe), 0);
2809 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2810 }
2811 I915_WRITE16(IMR, 0xffff);
2812 I915_WRITE16(IER, 0x0);
2813 I915_WRITE16(IIR, I915_READ16(IIR));
2814}
2815
Chris Wilsona266c7d2012-04-24 22:59:44 +01002816static void i915_irq_preinstall(struct drm_device * dev)
2817{
2818 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2819 int pipe;
2820
2821 atomic_set(&dev_priv->irq_received, 0);
2822
2823 if (I915_HAS_HOTPLUG(dev)) {
2824 I915_WRITE(PORT_HOTPLUG_EN, 0);
2825 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2826 }
2827
Chris Wilson00d98eb2012-04-24 22:59:48 +01002828 I915_WRITE16(HWSTAM, 0xeffe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002829 for_each_pipe(pipe)
2830 I915_WRITE(PIPESTAT(pipe), 0);
2831 I915_WRITE(IMR, 0xffffffff);
2832 I915_WRITE(IER, 0x0);
2833 POSTING_READ(IER);
2834}
2835
2836static int i915_irq_postinstall(struct drm_device *dev)
2837{
2838 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01002839 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002840
Chris Wilson38bde182012-04-24 22:59:50 +01002841 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2842
2843 /* Unmask the interrupts that we always want on. */
2844 dev_priv->irq_mask =
2845 ~(I915_ASLE_INTERRUPT |
2846 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2847 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2848 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2849 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2850 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2851
2852 enable_mask =
2853 I915_ASLE_INTERRUPT |
2854 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2855 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2856 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2857 I915_USER_INTERRUPT;
2858
Chris Wilsona266c7d2012-04-24 22:59:44 +01002859 if (I915_HAS_HOTPLUG(dev)) {
Daniel Vetter20afbda2012-12-11 14:05:07 +01002860 I915_WRITE(PORT_HOTPLUG_EN, 0);
2861 POSTING_READ(PORT_HOTPLUG_EN);
2862
Chris Wilsona266c7d2012-04-24 22:59:44 +01002863 /* Enable in IER... */
2864 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2865 /* and unmask in IMR */
2866 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2867 }
2868
Chris Wilsona266c7d2012-04-24 22:59:44 +01002869 I915_WRITE(IMR, dev_priv->irq_mask);
2870 I915_WRITE(IER, enable_mask);
2871 POSTING_READ(IER);
2872
Jani Nikulaf49e38d2013-04-29 13:02:54 +03002873 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01002874
2875 return 0;
2876}
2877
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002878/*
2879 * Returns true when a page flip has completed.
2880 */
2881static bool i915_handle_vblank(struct drm_device *dev,
2882 int plane, int pipe, u32 iir)
2883{
2884 drm_i915_private_t *dev_priv = dev->dev_private;
2885 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2886
2887 if (!drm_handle_vblank(dev, pipe))
2888 return false;
2889
2890 if ((iir & flip_pending) == 0)
2891 return false;
2892
2893 intel_prepare_page_flip(dev, plane);
2894
2895 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2896 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2897 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2898 * the flip is completed (no longer pending). Since this doesn't raise
2899 * an interrupt per se, we watch for the change at vblank.
2900 */
2901 if (I915_READ(ISR) & flip_pending)
2902 return false;
2903
2904 intel_finish_page_flip(dev, pipe);
2905
2906 return true;
2907}
2908
Daniel Vetterff1f5252012-10-02 15:10:55 +02002909static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01002910{
2911 struct drm_device *dev = (struct drm_device *) arg;
2912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01002913 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01002914 unsigned long irqflags;
Chris Wilson38bde182012-04-24 22:59:50 +01002915 u32 flip_mask =
2916 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2917 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01002918 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002919
2920 atomic_inc(&dev_priv->irq_received);
2921
2922 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01002923 do {
2924 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01002925 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002926
2927 /* Can't rely on pipestat interrupt bit in iir as it might
2928 * have been cleared after the pipestat interrupt was received.
2929 * It doesn't set the bit in iir again, but it still produces
2930 * interrupts (for non-MSI).
2931 */
2932 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2933 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2934 i915_handle_error(dev, false);
2935
2936 for_each_pipe(pipe) {
2937 int reg = PIPESTAT(pipe);
2938 pipe_stats[pipe] = I915_READ(reg);
2939
Chris Wilson38bde182012-04-24 22:59:50 +01002940 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01002941 if (pipe_stats[pipe] & 0x8000ffff) {
2942 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2943 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2944 pipe_name(pipe));
2945 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01002946 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002947 }
2948 }
2949 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2950
2951 if (!irq_received)
2952 break;
2953
Chris Wilsona266c7d2012-04-24 22:59:44 +01002954 /* Consume port. Then clear IIR or we'll miss events */
2955 if ((I915_HAS_HOTPLUG(dev)) &&
2956 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2957 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +02002958 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Chris Wilsona266c7d2012-04-24 22:59:44 +01002959
2960 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2961 hotplug_status);
Daniel Vetter91d131d2013-06-27 17:52:14 +02002962
2963 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2964
Chris Wilsona266c7d2012-04-24 22:59:44 +01002965 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
Chris Wilson38bde182012-04-24 22:59:50 +01002966 POSTING_READ(PORT_HOTPLUG_STAT);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002967 }
2968
Chris Wilson38bde182012-04-24 22:59:50 +01002969 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002970 new_iir = I915_READ(IIR); /* Flush posted writes */
2971
Chris Wilsona266c7d2012-04-24 22:59:44 +01002972 if (iir & I915_USER_INTERRUPT)
2973 notify_ring(dev, &dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002974
Chris Wilsona266c7d2012-04-24 22:59:44 +01002975 for_each_pipe(pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01002976 int plane = pipe;
2977 if (IS_MOBILE(dev))
2978 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02002979
Ville Syrjälä90a72f82013-02-19 23:16:44 +02002980 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2981 i915_handle_vblank(dev, plane, pipe, iir))
2982 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01002983
2984 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2985 blc_event = true;
2986 }
2987
Chris Wilsona266c7d2012-04-24 22:59:44 +01002988 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2989 intel_opregion_asle_intr(dev);
2990
2991 /* With MSI, interrupts are only generated when iir
2992 * transitions from zero to nonzero. If another bit got
2993 * set while we were handling the existing iir bits, then
2994 * we would never get another interrupt.
2995 *
2996 * This is fine on non-MSI as well, as if we hit this path
2997 * we avoid exiting the interrupt handler only to generate
2998 * another one.
2999 *
3000 * Note that for MSI this could cause a stray interrupt report
3001 * if an interrupt landed in the time between writing IIR and
3002 * the posting read. This should be rare enough to never
3003 * trigger the 99% of 100,000 interrupts test for disabling
3004 * stray interrupts.
3005 */
Chris Wilson38bde182012-04-24 22:59:50 +01003006 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003007 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01003008 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003009
Daniel Vetterd05c6172012-04-26 23:28:09 +02003010 i915_update_dri1_breadcrumb(dev);
Chris Wilson8291ee92012-04-24 22:59:47 +01003011
Chris Wilsona266c7d2012-04-24 22:59:44 +01003012 return ret;
3013}
3014
3015static void i915_irq_uninstall(struct drm_device * dev)
3016{
3017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3018 int pipe;
3019
Egbert Eichac4c16c2013-04-16 13:36:58 +02003020 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3021
Chris Wilsona266c7d2012-04-24 22:59:44 +01003022 if (I915_HAS_HOTPLUG(dev)) {
3023 I915_WRITE(PORT_HOTPLUG_EN, 0);
3024 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3025 }
3026
Chris Wilson00d98eb2012-04-24 22:59:48 +01003027 I915_WRITE16(HWSTAM, 0xffff);
Chris Wilson55b39752012-04-24 22:59:49 +01003028 for_each_pipe(pipe) {
3029 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003030 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01003031 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3032 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003033 I915_WRITE(IMR, 0xffffffff);
3034 I915_WRITE(IER, 0x0);
3035
Chris Wilsona266c7d2012-04-24 22:59:44 +01003036 I915_WRITE(IIR, I915_READ(IIR));
3037}
3038
3039static void i965_irq_preinstall(struct drm_device * dev)
3040{
3041 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3042 int pipe;
3043
3044 atomic_set(&dev_priv->irq_received, 0);
3045
Chris Wilsonadca4732012-05-11 18:01:31 +01003046 I915_WRITE(PORT_HOTPLUG_EN, 0);
3047 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01003048
3049 I915_WRITE(HWSTAM, 0xeffe);
3050 for_each_pipe(pipe)
3051 I915_WRITE(PIPESTAT(pipe), 0);
3052 I915_WRITE(IMR, 0xffffffff);
3053 I915_WRITE(IER, 0x0);
3054 POSTING_READ(IER);
3055}
3056
3057static int i965_irq_postinstall(struct drm_device *dev)
3058{
3059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003060 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003061 u32 error_mask;
Daniel Vetterb79480b2013-06-27 17:52:10 +02003062 unsigned long irqflags;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003063
Chris Wilsona266c7d2012-04-24 22:59:44 +01003064 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003065 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01003066 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003067 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3068 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3069 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3070 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3071 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3072
3073 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003074 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3075 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01003076 enable_mask |= I915_USER_INTERRUPT;
3077
3078 if (IS_G4X(dev))
3079 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003080
Daniel Vetterb79480b2013-06-27 17:52:10 +02003081 /* Interrupt setup is already guaranteed to be single-threaded, this is
3082 * just to make the assert_spin_locked check happy. */
3083 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01003084 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
Daniel Vetterb79480b2013-06-27 17:52:10 +02003085 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003086
Chris Wilsona266c7d2012-04-24 22:59:44 +01003087 /*
3088 * Enable some error detection, note the instruction error mask
3089 * bit is reserved, so we leave it masked.
3090 */
3091 if (IS_G4X(dev)) {
3092 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3093 GM45_ERROR_MEM_PRIV |
3094 GM45_ERROR_CP_PRIV |
3095 I915_ERROR_MEMORY_REFRESH);
3096 } else {
3097 error_mask = ~(I915_ERROR_PAGE_TABLE |
3098 I915_ERROR_MEMORY_REFRESH);
3099 }
3100 I915_WRITE(EMR, error_mask);
3101
3102 I915_WRITE(IMR, dev_priv->irq_mask);
3103 I915_WRITE(IER, enable_mask);
3104 POSTING_READ(IER);
3105
Daniel Vetter20afbda2012-12-11 14:05:07 +01003106 I915_WRITE(PORT_HOTPLUG_EN, 0);
3107 POSTING_READ(PORT_HOTPLUG_EN);
3108
Jani Nikulaf49e38d2013-04-29 13:02:54 +03003109 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003110
3111 return 0;
3112}
3113
Egbert Eichbac56d52013-02-25 12:06:51 -05003114static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01003115{
3116 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Egbert Eiche5868a32013-02-28 04:17:12 -05003117 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +02003118 struct intel_encoder *intel_encoder;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003119 u32 hotplug_en;
3120
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02003121 assert_spin_locked(&dev_priv->irq_lock);
3122
Egbert Eichbac56d52013-02-25 12:06:51 -05003123 if (I915_HAS_HOTPLUG(dev)) {
3124 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3125 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3126 /* Note HDMI and DP share hotplug bits */
Egbert Eiche5868a32013-02-28 04:17:12 -05003127 /* enable bits are the same for all generations */
Egbert Eichcd569ae2013-04-16 13:36:57 +02003128 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3129 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3130 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
Egbert Eichbac56d52013-02-25 12:06:51 -05003131 /* Programming the CRT detection parameters tends
3132 to generate a spurious hotplug event about three
3133 seconds later. So just do it once.
3134 */
3135 if (IS_G4X(dev))
3136 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
Daniel Vetter85fc95b2013-03-27 15:47:11 +01003137 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
Egbert Eichbac56d52013-02-25 12:06:51 -05003138 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003139
Egbert Eichbac56d52013-02-25 12:06:51 -05003140 /* Ignore TV since it's buggy */
3141 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3142 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01003143}
3144
Daniel Vetterff1f5252012-10-02 15:10:55 +02003145static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003146{
3147 struct drm_device *dev = (struct drm_device *) arg;
3148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003149 u32 iir, new_iir;
3150 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01003151 unsigned long irqflags;
3152 int irq_received;
3153 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003154 u32 flip_mask =
3155 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3156 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003157
3158 atomic_inc(&dev_priv->irq_received);
3159
3160 iir = I915_READ(IIR);
3161
Chris Wilsona266c7d2012-04-24 22:59:44 +01003162 for (;;) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01003163 bool blc_event = false;
3164
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003165 irq_received = (iir & ~flip_mask) != 0;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003166
3167 /* Can't rely on pipestat interrupt bit in iir as it might
3168 * have been cleared after the pipestat interrupt was received.
3169 * It doesn't set the bit in iir again, but it still produces
3170 * interrupts (for non-MSI).
3171 */
3172 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3173 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3174 i915_handle_error(dev, false);
3175
3176 for_each_pipe(pipe) {
3177 int reg = PIPESTAT(pipe);
3178 pipe_stats[pipe] = I915_READ(reg);
3179
3180 /*
3181 * Clear the PIPE*STAT regs before the IIR
3182 */
3183 if (pipe_stats[pipe] & 0x8000ffff) {
3184 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3185 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3186 pipe_name(pipe));
3187 I915_WRITE(reg, pipe_stats[pipe]);
3188 irq_received = 1;
3189 }
3190 }
3191 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3192
3193 if (!irq_received)
3194 break;
3195
3196 ret = IRQ_HANDLED;
3197
3198 /* Consume port. Then clear IIR or we'll miss events */
Chris Wilsonadca4732012-05-11 18:01:31 +01003199 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003200 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
Egbert Eichb543fb02013-04-16 13:36:54 +02003201 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3202 HOTPLUG_INT_STATUS_G4X :
Daniel Vetter4f7fd702013-06-24 21:33:28 +02003203 HOTPLUG_INT_STATUS_I915);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003204
3205 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3206 hotplug_status);
Daniel Vetter91d131d2013-06-27 17:52:14 +02003207
3208 intel_hpd_irq_handler(dev, hotplug_trigger,
3209 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3210
Chris Wilsona266c7d2012-04-24 22:59:44 +01003211 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3212 I915_READ(PORT_HOTPLUG_STAT);
3213 }
3214
Ville Syrjälä21ad8332013-02-19 15:16:39 +02003215 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003216 new_iir = I915_READ(IIR); /* Flush posted writes */
3217
Chris Wilsona266c7d2012-04-24 22:59:44 +01003218 if (iir & I915_USER_INTERRUPT)
3219 notify_ring(dev, &dev_priv->ring[RCS]);
3220 if (iir & I915_BSD_USER_INTERRUPT)
3221 notify_ring(dev, &dev_priv->ring[VCS]);
3222
Chris Wilsona266c7d2012-04-24 22:59:44 +01003223 for_each_pipe(pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01003224 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003225 i915_handle_vblank(dev, pipe, pipe, iir))
3226 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003227
3228 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3229 blc_event = true;
3230 }
3231
3232
3233 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3234 intel_opregion_asle_intr(dev);
3235
Daniel Vetter515ac2b2012-12-01 13:53:44 +01003236 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3237 gmbus_irq_handler(dev);
3238
Chris Wilsona266c7d2012-04-24 22:59:44 +01003239 /* With MSI, interrupts are only generated when iir
3240 * transitions from zero to nonzero. If another bit got
3241 * set while we were handling the existing iir bits, then
3242 * we would never get another interrupt.
3243 *
3244 * This is fine on non-MSI as well, as if we hit this path
3245 * we avoid exiting the interrupt handler only to generate
3246 * another one.
3247 *
3248 * Note that for MSI this could cause a stray interrupt report
3249 * if an interrupt landed in the time between writing IIR and
3250 * the posting read. This should be rare enough to never
3251 * trigger the 99% of 100,000 interrupts test for disabling
3252 * stray interrupts.
3253 */
3254 iir = new_iir;
3255 }
3256
Daniel Vetterd05c6172012-04-26 23:28:09 +02003257 i915_update_dri1_breadcrumb(dev);
Chris Wilson2c8ba292012-04-24 22:59:46 +01003258
Chris Wilsona266c7d2012-04-24 22:59:44 +01003259 return ret;
3260}
3261
3262static void i965_irq_uninstall(struct drm_device * dev)
3263{
3264 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3265 int pipe;
3266
3267 if (!dev_priv)
3268 return;
3269
Egbert Eichac4c16c2013-04-16 13:36:58 +02003270 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3271
Chris Wilsonadca4732012-05-11 18:01:31 +01003272 I915_WRITE(PORT_HOTPLUG_EN, 0);
3273 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01003274
3275 I915_WRITE(HWSTAM, 0xffffffff);
3276 for_each_pipe(pipe)
3277 I915_WRITE(PIPESTAT(pipe), 0);
3278 I915_WRITE(IMR, 0xffffffff);
3279 I915_WRITE(IER, 0x0);
3280
3281 for_each_pipe(pipe)
3282 I915_WRITE(PIPESTAT(pipe),
3283 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3284 I915_WRITE(IIR, I915_READ(IIR));
3285}
3286
Egbert Eichac4c16c2013-04-16 13:36:58 +02003287static void i915_reenable_hotplug_timer_func(unsigned long data)
3288{
3289 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3290 struct drm_device *dev = dev_priv->dev;
3291 struct drm_mode_config *mode_config = &dev->mode_config;
3292 unsigned long irqflags;
3293 int i;
3294
3295 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3296 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3297 struct drm_connector *connector;
3298
3299 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3300 continue;
3301
3302 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3303
3304 list_for_each_entry(connector, &mode_config->connector_list, head) {
3305 struct intel_connector *intel_connector = to_intel_connector(connector);
3306
3307 if (intel_connector->encoder->hpd_pin == i) {
3308 if (connector->polled != intel_connector->polled)
3309 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3310 drm_get_connector_name(connector));
3311 connector->polled = intel_connector->polled;
3312 if (!connector->polled)
3313 connector->polled = DRM_CONNECTOR_POLL_HPD;
3314 }
3315 }
3316 }
3317 if (dev_priv->display.hpd_irq_setup)
3318 dev_priv->display.hpd_irq_setup(dev);
3319 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3320}
3321
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003322void intel_irq_init(struct drm_device *dev)
3323{
Chris Wilson8b2e3262012-04-24 22:59:41 +01003324 struct drm_i915_private *dev_priv = dev->dev_private;
3325
3326 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Daniel Vetter99584db2012-11-14 17:14:04 +01003327 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02003328 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01003329 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01003330
Daniel Vetter99584db2012-11-14 17:14:04 +01003331 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3332 i915_hangcheck_elapsed,
Daniel Vetter61bac782012-12-01 21:03:21 +01003333 (unsigned long) dev);
Egbert Eichac4c16c2013-04-16 13:36:58 +02003334 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3335 (unsigned long) dev_priv);
Daniel Vetter61bac782012-12-01 21:03:21 +01003336
Tomas Janousek97a19a22012-12-08 13:48:13 +01003337 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01003338
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +03003339 if (IS_GEN2(dev)) {
3340 dev->max_vblank_count = 0;
3341 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3342 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003343 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3344 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
Ville Syrjälä391f75e2013-09-25 19:55:26 +03003345 } else {
3346 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3347 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003348 }
3349
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +03003350 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Keith Packardc3613de2011-08-12 17:05:54 -07003351 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +03003352 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3353 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003354
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003355 if (IS_VALLEYVIEW(dev)) {
3356 dev->driver->irq_handler = valleyview_irq_handler;
3357 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3358 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3359 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3360 dev->driver->enable_vblank = valleyview_enable_vblank;
3361 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05003362 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003363 } else if (HAS_PCH_SPLIT(dev)) {
3364 dev->driver->irq_handler = ironlake_irq_handler;
3365 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3366 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3367 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3368 dev->driver->enable_vblank = ironlake_enable_vblank;
3369 dev->driver->disable_vblank = ironlake_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003370 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003371 } else {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003372 if (INTEL_INFO(dev)->gen == 2) {
3373 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3374 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3375 dev->driver->irq_handler = i8xx_irq_handler;
3376 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003377 } else if (INTEL_INFO(dev)->gen == 3) {
3378 dev->driver->irq_preinstall = i915_irq_preinstall;
3379 dev->driver->irq_postinstall = i915_irq_postinstall;
3380 dev->driver->irq_uninstall = i915_irq_uninstall;
3381 dev->driver->irq_handler = i915_irq_handler;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003382 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003383 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003384 dev->driver->irq_preinstall = i965_irq_preinstall;
3385 dev->driver->irq_postinstall = i965_irq_postinstall;
3386 dev->driver->irq_uninstall = i965_irq_uninstall;
3387 dev->driver->irq_handler = i965_irq_handler;
Egbert Eichbac56d52013-02-25 12:06:51 -05003388 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003389 }
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003390 dev->driver->enable_vblank = i915_enable_vblank;
3391 dev->driver->disable_vblank = i915_disable_vblank;
3392 }
3393}
Daniel Vetter20afbda2012-12-11 14:05:07 +01003394
3395void intel_hpd_init(struct drm_device *dev)
3396{
3397 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eich821450c2013-04-16 13:36:55 +02003398 struct drm_mode_config *mode_config = &dev->mode_config;
3399 struct drm_connector *connector;
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02003400 unsigned long irqflags;
Egbert Eich821450c2013-04-16 13:36:55 +02003401 int i;
Daniel Vetter20afbda2012-12-11 14:05:07 +01003402
Egbert Eich821450c2013-04-16 13:36:55 +02003403 for (i = 1; i < HPD_NUM_PINS; i++) {
3404 dev_priv->hpd_stats[i].hpd_cnt = 0;
3405 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3406 }
3407 list_for_each_entry(connector, &mode_config->connector_list, head) {
3408 struct intel_connector *intel_connector = to_intel_connector(connector);
3409 connector->polled = intel_connector->polled;
3410 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3411 connector->polled = DRM_CONNECTOR_POLL_HPD;
3412 }
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02003413
3414 /* Interrupt setup is already guaranteed to be single-threaded, this is
3415 * just to make the assert_spin_locked checks happy. */
3416 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003417 if (dev_priv->display.hpd_irq_setup)
3418 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02003419 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003420}
Paulo Zanonic67a4702013-08-19 13:18:09 -03003421
3422/* Disable interrupts so we can allow Package C8+. */
3423void hsw_pc8_disable_interrupts(struct drm_device *dev)
3424{
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 unsigned long irqflags;
3427
3428 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3429
3430 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3431 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3432 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3433 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3434 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3435
3436 ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3437 ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3438 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3439 snb_disable_pm_irq(dev_priv, 0xffffffff);
3440
3441 dev_priv->pc8.irqs_disabled = true;
3442
3443 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3444}
3445
3446/* Restore interrupts so we can recover from Package C8+. */
3447void hsw_pc8_restore_interrupts(struct drm_device *dev)
3448{
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 unsigned long irqflags;
3451 uint32_t val, expected;
3452
3453 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3454
3455 val = I915_READ(DEIMR);
3456 expected = ~DE_PCH_EVENT_IVB;
3457 WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3458
3459 val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3460 expected = ~SDE_HOTPLUG_MASK_CPT;
3461 WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3462 val, expected);
3463
3464 val = I915_READ(GTIMR);
3465 expected = 0xffffffff;
3466 WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3467
3468 val = I915_READ(GEN6_PMIMR);
3469 expected = 0xffffffff;
3470 WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3471 expected);
3472
3473 dev_priv->pc8.irqs_disabled = false;
3474
3475 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3476 ibx_enable_display_interrupt(dev_priv,
3477 ~dev_priv->pc8.regsave.sdeimr &
3478 ~SDE_HOTPLUG_MASK_CPT);
3479 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3480 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3481 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3482
3483 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3484}