Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 30 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 31 | #include <linux/sysrq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 33 | #include <linux/circ_buf.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 34 | #include <drm/drmP.h> |
| 35 | #include <drm/i915_drm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 37 | #include "i915_trace.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 40 | static const u32 hpd_ibx[] = { |
| 41 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
| 42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, |
| 43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, |
| 44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, |
| 45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG |
| 46 | }; |
| 47 | |
| 48 | static const u32 hpd_cpt[] = { |
| 49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
Daniel Vetter | 73c352a | 2013-03-26 22:38:43 +0100 | [diff] [blame] | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
| 52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, |
| 53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT |
| 54 | }; |
| 55 | |
| 56 | static const u32 hpd_mask_i915[] = { |
| 57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
| 58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, |
| 59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, |
| 60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, |
| 61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, |
| 62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN |
| 63 | }; |
| 64 | |
| 65 | static const u32 hpd_status_gen4[] = { |
| 66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, |
| 68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, |
| 69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 72 | }; |
| 73 | |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
| 75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
| 76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, |
| 77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, |
| 78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, |
| 79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, |
| 80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS |
| 81 | }; |
| 82 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 83 | /* For display hotplug interrupt */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 84 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 85 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 86 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 87 | assert_spin_locked(&dev_priv->irq_lock); |
| 88 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 89 | if (dev_priv->pc8.irqs_disabled) { |
| 90 | WARN(1, "IRQs disabled\n"); |
| 91 | dev_priv->pc8.regsave.deimr &= ~mask; |
| 92 | return; |
| 93 | } |
| 94 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 95 | if ((dev_priv->irq_mask & mask) != 0) { |
| 96 | dev_priv->irq_mask &= ~mask; |
| 97 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 98 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 99 | } |
| 100 | } |
| 101 | |
Paulo Zanoni | 0ff9800 | 2013-02-22 17:05:31 -0300 | [diff] [blame] | 102 | static void |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 103 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 104 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 105 | assert_spin_locked(&dev_priv->irq_lock); |
| 106 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 107 | if (dev_priv->pc8.irqs_disabled) { |
| 108 | WARN(1, "IRQs disabled\n"); |
| 109 | dev_priv->pc8.regsave.deimr |= mask; |
| 110 | return; |
| 111 | } |
| 112 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 113 | if ((dev_priv->irq_mask & mask) != mask) { |
| 114 | dev_priv->irq_mask |= mask; |
| 115 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 116 | POSTING_READ(DEIMR); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 120 | /** |
| 121 | * ilk_update_gt_irq - update GTIMR |
| 122 | * @dev_priv: driver private |
| 123 | * @interrupt_mask: mask of interrupt bits to update |
| 124 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 125 | */ |
| 126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, |
| 127 | uint32_t interrupt_mask, |
| 128 | uint32_t enabled_irq_mask) |
| 129 | { |
| 130 | assert_spin_locked(&dev_priv->irq_lock); |
| 131 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 132 | if (dev_priv->pc8.irqs_disabled) { |
| 133 | WARN(1, "IRQs disabled\n"); |
| 134 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; |
| 135 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & |
| 136 | interrupt_mask); |
| 137 | return; |
| 138 | } |
| 139 | |
Paulo Zanoni | 43eaea1 | 2013-08-06 18:57:12 -0300 | [diff] [blame] | 140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
| 141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); |
| 142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 143 | POSTING_READ(GTIMR); |
| 144 | } |
| 145 | |
| 146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 147 | { |
| 148 | ilk_update_gt_irq(dev_priv, mask, mask); |
| 149 | } |
| 150 | |
| 151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 152 | { |
| 153 | ilk_update_gt_irq(dev_priv, mask, 0); |
| 154 | } |
| 155 | |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 156 | /** |
| 157 | * snb_update_pm_irq - update GEN6_PMIMR |
| 158 | * @dev_priv: driver private |
| 159 | * @interrupt_mask: mask of interrupt bits to update |
| 160 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 161 | */ |
| 162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
| 163 | uint32_t interrupt_mask, |
| 164 | uint32_t enabled_irq_mask) |
| 165 | { |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 166 | uint32_t new_val; |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 167 | |
| 168 | assert_spin_locked(&dev_priv->irq_lock); |
| 169 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 170 | if (dev_priv->pc8.irqs_disabled) { |
| 171 | WARN(1, "IRQs disabled\n"); |
| 172 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; |
| 173 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & |
| 174 | interrupt_mask); |
| 175 | return; |
| 176 | } |
| 177 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 178 | new_val = dev_priv->pm_irq_mask; |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 179 | new_val &= ~interrupt_mask; |
| 180 | new_val |= (~enabled_irq_mask & interrupt_mask); |
| 181 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 182 | if (new_val != dev_priv->pm_irq_mask) { |
| 183 | dev_priv->pm_irq_mask = new_val; |
| 184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
Paulo Zanoni | f52ecbc | 2013-08-06 18:57:14 -0300 | [diff] [blame] | 185 | POSTING_READ(GEN6_PMIMR); |
| 186 | } |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 190 | { |
| 191 | snb_update_pm_irq(dev_priv, mask, mask); |
| 192 | } |
| 193 | |
| 194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
| 195 | { |
| 196 | snb_update_pm_irq(dev_priv, mask, 0); |
| 197 | } |
| 198 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
| 200 | { |
| 201 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 202 | struct intel_crtc *crtc; |
| 203 | enum pipe pipe; |
| 204 | |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 205 | assert_spin_locked(&dev_priv->irq_lock); |
| 206 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 207 | for_each_pipe(pipe) { |
| 208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 209 | |
| 210 | if (crtc->cpu_fifo_underrun_disabled) |
| 211 | return false; |
| 212 | } |
| 213 | |
| 214 | return true; |
| 215 | } |
| 216 | |
| 217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) |
| 218 | { |
| 219 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 220 | enum pipe pipe; |
| 221 | struct intel_crtc *crtc; |
| 222 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 223 | assert_spin_locked(&dev_priv->irq_lock); |
| 224 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 225 | for_each_pipe(pipe) { |
| 226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 227 | |
| 228 | if (crtc->pch_fifo_underrun_disabled) |
| 229 | return false; |
| 230 | } |
| 231 | |
| 232 | return true; |
| 233 | } |
| 234 | |
| 235 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
| 236 | enum pipe pipe, bool enable) |
| 237 | { |
| 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 239 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : |
| 240 | DE_PIPEB_FIFO_UNDERRUN; |
| 241 | |
| 242 | if (enable) |
| 243 | ironlake_enable_display_irq(dev_priv, bit); |
| 244 | else |
| 245 | ironlake_disable_display_irq(dev_priv, bit); |
| 246 | } |
| 247 | |
| 248 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 249 | enum pipe pipe, bool enable) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 250 | { |
| 251 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 252 | if (enable) { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 253 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
| 254 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 255 | if (!ivb_can_enable_err_int(dev)) |
| 256 | return; |
| 257 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 258 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| 259 | } else { |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 260 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
| 261 | |
| 262 | /* Change the state _after_ we've read out the current one. */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 263 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 264 | |
| 265 | if (!was_enabled && |
| 266 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { |
| 267 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", |
| 268 | pipe_name(pipe)); |
| 269 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 270 | } |
| 271 | } |
| 272 | |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 273 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
| 274 | enum pipe pipe, bool enable) |
| 275 | { |
| 276 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 277 | |
| 278 | assert_spin_locked(&dev_priv->irq_lock); |
| 279 | |
| 280 | if (enable) |
| 281 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; |
| 282 | else |
| 283 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; |
| 284 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 285 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
| 286 | } |
| 287 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 288 | /** |
| 289 | * ibx_display_interrupt_update - update SDEIMR |
| 290 | * @dev_priv: driver private |
| 291 | * @interrupt_mask: mask of interrupt bits to update |
| 292 | * @enabled_irq_mask: mask of interrupt bits to enable |
| 293 | */ |
| 294 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
| 295 | uint32_t interrupt_mask, |
| 296 | uint32_t enabled_irq_mask) |
| 297 | { |
| 298 | uint32_t sdeimr = I915_READ(SDEIMR); |
| 299 | sdeimr &= ~interrupt_mask; |
| 300 | sdeimr |= (~enabled_irq_mask & interrupt_mask); |
| 301 | |
| 302 | assert_spin_locked(&dev_priv->irq_lock); |
| 303 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 304 | if (dev_priv->pc8.irqs_disabled && |
| 305 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { |
| 306 | WARN(1, "IRQs disabled\n"); |
| 307 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; |
| 308 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & |
| 309 | interrupt_mask); |
| 310 | return; |
| 311 | } |
| 312 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 313 | I915_WRITE(SDEIMR, sdeimr); |
| 314 | POSTING_READ(SDEIMR); |
| 315 | } |
| 316 | #define ibx_enable_display_interrupt(dev_priv, bits) \ |
| 317 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) |
| 318 | #define ibx_disable_display_interrupt(dev_priv, bits) \ |
| 319 | ibx_display_interrupt_update((dev_priv), (bits), 0) |
| 320 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 321 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
| 322 | enum transcoder pch_transcoder, |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 323 | bool enable) |
| 324 | { |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 326 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
| 327 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 328 | |
| 329 | if (enable) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 330 | ibx_enable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 331 | else |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 332 | ibx_disable_display_interrupt(dev_priv, bit); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, |
| 336 | enum transcoder pch_transcoder, |
| 337 | bool enable) |
| 338 | { |
| 339 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 340 | |
| 341 | if (enable) { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 342 | I915_WRITE(SERR_INT, |
| 343 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); |
| 344 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 345 | if (!cpt_can_enable_serr_int(dev)) |
| 346 | return; |
| 347 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 348 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 349 | } else { |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 350 | uint32_t tmp = I915_READ(SERR_INT); |
| 351 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); |
| 352 | |
| 353 | /* Change the state _after_ we've read out the current one. */ |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 354 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
Daniel Vetter | 1dd246f | 2013-07-10 08:30:23 +0200 | [diff] [blame] | 355 | |
| 356 | if (!was_enabled && |
| 357 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { |
| 358 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", |
| 359 | transcoder_name(pch_transcoder)); |
| 360 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 361 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | /** |
| 365 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 366 | * @dev: drm device |
| 367 | * @pipe: pipe |
| 368 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 369 | * |
| 370 | * This function makes us disable or enable CPU fifo underruns for a specific |
| 371 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun |
| 372 | * reporting for one pipe may also disable all the other CPU error interruts for |
| 373 | * the other pipes, due to the fact that there's just one interrupt mask/enable |
| 374 | * bit for all the pipes. |
| 375 | * |
| 376 | * Returns the previous state of underrun reporting. |
| 377 | */ |
| 378 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
| 379 | enum pipe pipe, bool enable) |
| 380 | { |
| 381 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 382 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 384 | unsigned long flags; |
| 385 | bool ret; |
| 386 | |
| 387 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 388 | |
| 389 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
| 390 | |
| 391 | if (enable == ret) |
| 392 | goto done; |
| 393 | |
| 394 | intel_crtc->cpu_fifo_underrun_disabled = !enable; |
| 395 | |
| 396 | if (IS_GEN5(dev) || IS_GEN6(dev)) |
| 397 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
| 398 | else if (IS_GEN7(dev)) |
Daniel Vetter | 7336df6 | 2013-07-09 22:59:16 +0200 | [diff] [blame] | 399 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 400 | else if (IS_GEN8(dev)) |
| 401 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 402 | |
| 403 | done: |
| 404 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 405 | return ret; |
| 406 | } |
| 407 | |
| 408 | /** |
| 409 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages |
| 410 | * @dev: drm device |
| 411 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) |
| 412 | * @enable: true if we want to report FIFO underrun errors, false otherwise |
| 413 | * |
| 414 | * This function makes us disable or enable PCH fifo underruns for a specific |
| 415 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO |
| 416 | * underrun reporting for one transcoder may also disable all the other PCH |
| 417 | * error interruts for the other transcoders, due to the fact that there's just |
| 418 | * one interrupt mask/enable bit for all the transcoders. |
| 419 | * |
| 420 | * Returns the previous state of underrun reporting. |
| 421 | */ |
| 422 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| 423 | enum transcoder pch_transcoder, |
| 424 | bool enable) |
| 425 | { |
| 426 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 427 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
| 428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 429 | unsigned long flags; |
| 430 | bool ret; |
| 431 | |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 432 | /* |
| 433 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT |
| 434 | * has only one pch transcoder A that all pipes can use. To avoid racy |
| 435 | * pch transcoder -> pipe lookups from interrupt code simply store the |
| 436 | * underrun statistics in crtc A. Since we never expose this anywhere |
| 437 | * nor use it outside of the fifo underrun code here using the "wrong" |
| 438 | * crtc on LPT won't cause issues. |
| 439 | */ |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 440 | |
| 441 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
| 442 | |
| 443 | ret = !intel_crtc->pch_fifo_underrun_disabled; |
| 444 | |
| 445 | if (enable == ret) |
| 446 | goto done; |
| 447 | |
| 448 | intel_crtc->pch_fifo_underrun_disabled = !enable; |
| 449 | |
| 450 | if (HAS_PCH_IBX(dev)) |
Daniel Vetter | de28075 | 2013-07-04 23:35:24 +0200 | [diff] [blame] | 451 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 452 | else |
| 453 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
| 454 | |
| 455 | done: |
| 456 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 457 | return ret; |
| 458 | } |
| 459 | |
| 460 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 461 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 462 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 463 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 464 | u32 reg = PIPESTAT(pipe); |
| 465 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 466 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 467 | assert_spin_locked(&dev_priv->irq_lock); |
| 468 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 469 | if ((pipestat & mask) == mask) |
| 470 | return; |
| 471 | |
| 472 | /* Enable the interrupt, clear any pending status */ |
| 473 | pipestat |= mask | (mask >> 16); |
| 474 | I915_WRITE(reg, pipestat); |
| 475 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | void |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 479 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 480 | { |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 481 | u32 reg = PIPESTAT(pipe); |
| 482 | u32 pipestat = I915_READ(reg) & 0x7fff0000; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 483 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 484 | assert_spin_locked(&dev_priv->irq_lock); |
| 485 | |
Ville Syrjälä | 46c06a3 | 2013-02-20 21:16:18 +0200 | [diff] [blame] | 486 | if ((pipestat & mask) == 0) |
| 487 | return; |
| 488 | |
| 489 | pipestat &= ~mask; |
| 490 | I915_WRITE(reg, pipestat); |
| 491 | POSTING_READ(reg); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 492 | } |
| 493 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 494 | /** |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 495 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 496 | */ |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 497 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 498 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 499 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 500 | unsigned long irqflags; |
| 501 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 502 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
| 503 | return; |
| 504 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 505 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 506 | |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 507 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); |
Jani Nikula | f898780 | 2013-04-29 13:02:53 +0300 | [diff] [blame] | 508 | if (INTEL_INFO(dev)->gen >= 4) |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 509 | i915_enable_pipestat(dev_priv, PIPE_A, |
| 510 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 511 | |
| 512 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Zhao Yakui | 01c6688 | 2009-10-28 05:10:00 +0000 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 516 | * i915_pipe_enabled - check if a pipe is enabled |
| 517 | * @dev: DRM device |
| 518 | * @pipe: pipe to check |
| 519 | * |
| 520 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 521 | * Use this routine to make sure the PLL is running and the pipe is active |
| 522 | * before reading such registers if unsure. |
| 523 | */ |
| 524 | static int |
| 525 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 526 | { |
| 527 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 528 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 529 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 530 | /* Locking is horribly broken here, but whatever. */ |
| 531 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 71f8ba6 | 2013-05-03 12:15:39 -0300 | [diff] [blame] | 533 | |
Daniel Vetter | a01025a | 2013-05-22 00:50:23 +0200 | [diff] [blame] | 534 | return intel_crtc->active; |
| 535 | } else { |
| 536 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
| 537 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 538 | } |
| 539 | |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 540 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
| 541 | { |
| 542 | /* Gen2 doesn't have a hardware frame counter */ |
| 543 | return 0; |
| 544 | } |
| 545 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 546 | /* Called from drm generic code, passed a 'crtc', which |
| 547 | * we use as a pipe index |
| 548 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 549 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 550 | { |
| 551 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 552 | unsigned long high_frame; |
| 553 | unsigned long low_frame; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 554 | u32 high1, high2, low, pixel, vbl_start; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 555 | |
| 556 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 557 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 558 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 559 | return 0; |
| 560 | } |
| 561 | |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 562 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 563 | struct intel_crtc *intel_crtc = |
| 564 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 565 | const struct drm_display_mode *mode = |
| 566 | &intel_crtc->config.adjusted_mode; |
| 567 | |
| 568 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; |
| 569 | } else { |
| 570 | enum transcoder cpu_transcoder = |
| 571 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); |
| 572 | u32 htotal; |
| 573 | |
| 574 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; |
| 575 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; |
| 576 | |
| 577 | vbl_start *= htotal; |
| 578 | } |
| 579 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 580 | high_frame = PIPEFRAME(pipe); |
| 581 | low_frame = PIPEFRAMEPIXEL(pipe); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 582 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 583 | /* |
| 584 | * High & low register fields aren't synchronized, so make sure |
| 585 | * we get a low value that's stable across two reads of the high |
| 586 | * register. |
| 587 | */ |
| 588 | do { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 589 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 590 | low = I915_READ(low_frame); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 591 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 592 | } while (high1 != high2); |
| 593 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 594 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 595 | pixel = low & PIPE_PIXEL_MASK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 596 | low >>= PIPE_FRAME_LOW_SHIFT; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 597 | |
| 598 | /* |
| 599 | * The frame counter increments at beginning of active. |
| 600 | * Cook up a vblank counter by also checking the pixel |
| 601 | * counter against vblank start. |
| 602 | */ |
| 603 | return ((high1 << 8) | low) + (pixel >= vbl_start); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 604 | } |
| 605 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 606 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 607 | { |
| 608 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 609 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 610 | |
| 611 | if (!i915_pipe_enabled(dev, pipe)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 612 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 613 | "pipe %c\n", pipe_name(pipe)); |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | return I915_READ(reg); |
| 618 | } |
| 619 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 620 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
| 621 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 622 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 623 | |
| 624 | static bool intel_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 625 | { |
| 626 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 627 | uint32_t status; |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 628 | int reg; |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 629 | |
| 630 | if (IS_VALLEYVIEW(dev)) { |
| 631 | status = pipe == PIPE_A ? |
| 632 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : |
| 633 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 634 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 635 | reg = VLV_ISR; |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 636 | } else if (IS_GEN2(dev)) { |
| 637 | status = pipe == PIPE_A ? |
| 638 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : |
| 639 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 640 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 641 | reg = ISR; |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 642 | } else if (INTEL_INFO(dev)->gen < 5) { |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 643 | status = pipe == PIPE_A ? |
| 644 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : |
| 645 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 646 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 647 | reg = ISR; |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 648 | } else if (INTEL_INFO(dev)->gen < 7) { |
| 649 | status = pipe == PIPE_A ? |
| 650 | DE_PIPEA_VBLANK : |
| 651 | DE_PIPEB_VBLANK; |
| 652 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 653 | reg = DEISR; |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 654 | } else { |
| 655 | switch (pipe) { |
| 656 | default: |
| 657 | case PIPE_A: |
| 658 | status = DE_PIPEA_VBLANK_IVB; |
| 659 | break; |
| 660 | case PIPE_B: |
| 661 | status = DE_PIPEB_VBLANK_IVB; |
| 662 | break; |
| 663 | case PIPE_C: |
| 664 | status = DE_PIPEC_VBLANK_IVB; |
| 665 | break; |
| 666 | } |
| 667 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 668 | reg = DEISR; |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 669 | } |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 670 | |
| 671 | if (IS_GEN2(dev)) |
| 672 | return __raw_i915_read16(dev_priv, reg) & status; |
| 673 | else |
| 674 | return __raw_i915_read32(dev_priv, reg) & status; |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 675 | } |
| 676 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 677 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 678 | int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 679 | { |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 680 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 681 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 682 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 683 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 684 | int position; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 685 | int vbl_start, vbl_end, htotal, vtotal; |
| 686 | bool in_vbl = true; |
| 687 | int ret = 0; |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 688 | unsigned long irqflags; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 689 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 690 | if (!intel_crtc->active) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 691 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 692 | "pipe %c\n", pipe_name(pipe)); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 693 | return 0; |
| 694 | } |
| 695 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 696 | htotal = mode->crtc_htotal; |
| 697 | vtotal = mode->crtc_vtotal; |
| 698 | vbl_start = mode->crtc_vblank_start; |
| 699 | vbl_end = mode->crtc_vblank_end; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 700 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 701 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
| 702 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 703 | /* |
| 704 | * Lock uncore.lock, as we will do multiple timing critical raw |
| 705 | * register reads, potentially with preemption disabled, so the |
| 706 | * following code must not block on uncore.lock. |
| 707 | */ |
| 708 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 709 | |
| 710 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
| 711 | |
| 712 | /* Get optional system timestamp before query. */ |
| 713 | if (stime) |
| 714 | *stime = ktime_get(); |
| 715 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 716 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 717 | /* No obvious pixelcount register. Only query vertical |
| 718 | * scanout position from Display scan line register. |
| 719 | */ |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 720 | if (IS_GEN2(dev)) |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 721 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 722 | else |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 723 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 724 | |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 725 | /* |
| 726 | * The scanline counter increments at the leading edge |
| 727 | * of hsync, ie. it completely misses the active portion |
| 728 | * of the line. Fix up the counter at both edges of vblank |
| 729 | * to get a more accurate picture whether we're in vblank |
| 730 | * or not. |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 731 | */ |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 732 | in_vbl = intel_pipe_in_vblank_locked(dev, pipe); |
Ville Syrjälä | 54ddcbd | 2013-09-23 13:02:07 +0300 | [diff] [blame] | 733 | if ((in_vbl && position == vbl_start - 1) || |
| 734 | (!in_vbl && position == vbl_end - 1)) |
| 735 | position = (position + 1) % vtotal; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 736 | } else { |
| 737 | /* Have access to pixelcount since start of frame. |
| 738 | * We can split this into vertical and horizontal |
| 739 | * scanout position. |
| 740 | */ |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 741 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 742 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 743 | /* convert to pixel counts */ |
| 744 | vbl_start *= htotal; |
| 745 | vbl_end *= htotal; |
| 746 | vtotal *= htotal; |
| 747 | } |
| 748 | |
Mario Kleiner | ad3543e | 2013-10-30 05:13:08 +0100 | [diff] [blame] | 749 | /* Get optional system timestamp after query. */ |
| 750 | if (etime) |
| 751 | *etime = ktime_get(); |
| 752 | |
| 753 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
| 754 | |
| 755 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 756 | |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 757 | in_vbl = position >= vbl_start && position < vbl_end; |
| 758 | |
| 759 | /* |
| 760 | * While in vblank, position will be negative |
| 761 | * counting up towards 0 at vbl_end. And outside |
| 762 | * vblank, position will be positive counting |
| 763 | * up since vbl_end. |
| 764 | */ |
| 765 | if (position >= vbl_start) |
| 766 | position -= vbl_end; |
| 767 | else |
| 768 | position += vtotal - vbl_end; |
| 769 | |
Ville Syrjälä | 7c06b08 | 2013-10-11 21:52:43 +0300 | [diff] [blame] | 770 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 3aa18df | 2013-10-11 19:10:32 +0300 | [diff] [blame] | 771 | *vpos = position; |
| 772 | *hpos = 0; |
| 773 | } else { |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 774 | *vpos = position / htotal; |
| 775 | *hpos = position - (*vpos * htotal); |
| 776 | } |
| 777 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 778 | /* In vblank? */ |
| 779 | if (in_vbl) |
| 780 | ret |= DRM_SCANOUTPOS_INVBL; |
| 781 | |
| 782 | return ret; |
| 783 | } |
| 784 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 785 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 786 | int *max_error, |
| 787 | struct timeval *vblank_time, |
| 788 | unsigned flags) |
| 789 | { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 790 | struct drm_crtc *crtc; |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 791 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 792 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 793 | DRM_ERROR("Invalid crtc %d\n", pipe); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 794 | return -EINVAL; |
| 795 | } |
| 796 | |
| 797 | /* Get drm_crtc to timestamp: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 798 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
| 799 | if (crtc == NULL) { |
| 800 | DRM_ERROR("Invalid crtc %d\n", pipe); |
| 801 | return -EINVAL; |
| 802 | } |
| 803 | |
| 804 | if (!crtc->enabled) { |
| 805 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
| 806 | return -EBUSY; |
| 807 | } |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 808 | |
| 809 | /* Helper routine in DRM core does all the work: */ |
Chris Wilson | 4041b85 | 2011-01-22 10:07:56 +0000 | [diff] [blame] | 810 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
| 811 | vblank_time, flags, |
| 812 | crtc); |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 813 | } |
| 814 | |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 815 | static bool intel_hpd_irq_event(struct drm_device *dev, |
| 816 | struct drm_connector *connector) |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 817 | { |
| 818 | enum drm_connector_status old_status; |
| 819 | |
| 820 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 821 | old_status = connector->status; |
| 822 | |
| 823 | connector->status = connector->funcs->detect(connector, false); |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 824 | if (old_status == connector->status) |
| 825 | return false; |
| 826 | |
| 827 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 828 | connector->base.id, |
| 829 | drm_get_connector_name(connector), |
Jani Nikula | 67c347f | 2013-09-17 14:26:34 +0300 | [diff] [blame] | 830 | drm_get_connector_status_name(old_status), |
| 831 | drm_get_connector_status_name(connector->status)); |
| 832 | |
| 833 | return true; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 834 | } |
| 835 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 836 | /* |
| 837 | * Handle hotplug events outside the interrupt handler proper. |
| 838 | */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 839 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
| 840 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 841 | static void i915_hotplug_work_func(struct work_struct *work) |
| 842 | { |
| 843 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 844 | hotplug_work); |
| 845 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame] | 846 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 847 | struct intel_connector *intel_connector; |
| 848 | struct intel_encoder *intel_encoder; |
| 849 | struct drm_connector *connector; |
| 850 | unsigned long irqflags; |
| 851 | bool hpd_disabled = false; |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 852 | bool changed = false; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 853 | u32 hpd_event_bits; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 854 | |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 855 | /* HPD irq before everything is fully set up. */ |
| 856 | if (!dev_priv->enable_hotplug_processing) |
| 857 | return; |
| 858 | |
Keith Packard | a65e34c | 2011-07-25 10:04:56 -0700 | [diff] [blame] | 859 | mutex_lock(&mode_config->mutex); |
Jesse Barnes | e67189ab | 2011-02-11 14:44:51 -0800 | [diff] [blame] | 860 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
| 861 | |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 862 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 863 | |
| 864 | hpd_event_bits = dev_priv->hpd_event_bits; |
| 865 | dev_priv->hpd_event_bits = 0; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 866 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 867 | intel_connector = to_intel_connector(connector); |
| 868 | intel_encoder = intel_connector->encoder; |
| 869 | if (intel_encoder->hpd_pin > HPD_NONE && |
| 870 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && |
| 871 | connector->polled == DRM_CONNECTOR_POLL_HPD) { |
| 872 | DRM_INFO("HPD interrupt storm detected on connector %s: " |
| 873 | "switching from hotplug detection to polling\n", |
| 874 | drm_get_connector_name(connector)); |
| 875 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; |
| 876 | connector->polled = DRM_CONNECTOR_POLL_CONNECT |
| 877 | | DRM_CONNECTOR_POLL_DISCONNECT; |
| 878 | hpd_disabled = true; |
| 879 | } |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 880 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 881 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", |
| 882 | drm_get_connector_name(connector), intel_encoder->hpd_pin); |
| 883 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 884 | } |
| 885 | /* if there were no outputs to poll, poll was disabled, |
| 886 | * therefore make sure it's enabled when disabling HPD on |
| 887 | * some connectors */ |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 888 | if (hpd_disabled) { |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 889 | drm_kms_helper_poll_enable(dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 890 | mod_timer(&dev_priv->hotplug_reenable_timer, |
| 891 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); |
| 892 | } |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 893 | |
| 894 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 895 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 896 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 897 | intel_connector = to_intel_connector(connector); |
| 898 | intel_encoder = intel_connector->encoder; |
| 899 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
| 900 | if (intel_encoder->hot_plug) |
| 901 | intel_encoder->hot_plug(intel_encoder); |
| 902 | if (intel_hpd_irq_event(dev, connector)) |
| 903 | changed = true; |
| 904 | } |
| 905 | } |
Keith Packard | 40ee338 | 2011-07-28 15:31:19 -0700 | [diff] [blame] | 906 | mutex_unlock(&mode_config->mutex); |
| 907 | |
Egbert Eich | 321a1b3 | 2013-04-11 16:00:26 +0200 | [diff] [blame] | 908 | if (changed) |
| 909 | drm_kms_helper_hotplug_event(dev); |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 910 | } |
| 911 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 912 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 913 | { |
| 914 | drm_i915_private_t *dev_priv = dev->dev_private; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 915 | u32 busy_up, busy_down, max_avg, min_avg; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 916 | u8 new_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 917 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 918 | spin_lock(&mchdev_lock); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 919 | |
Daniel Vetter | 73edd18f | 2012-08-08 23:35:37 +0200 | [diff] [blame] | 920 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
| 921 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 922 | new_delay = dev_priv->ips.cur_delay; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 923 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 924 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 925 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
| 926 | busy_down = I915_READ(RCPREVBSYTDNAVG); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 927 | max_avg = I915_READ(RCBMAXAVG); |
| 928 | min_avg = I915_READ(RCBMINAVG); |
| 929 | |
| 930 | /* Handle RCS change request from hw */ |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 931 | if (busy_up > max_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 932 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
| 933 | new_delay = dev_priv->ips.cur_delay - 1; |
| 934 | if (new_delay < dev_priv->ips.max_delay) |
| 935 | new_delay = dev_priv->ips.max_delay; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 936 | } else if (busy_down < min_avg) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 937 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
| 938 | new_delay = dev_priv->ips.cur_delay + 1; |
| 939 | if (new_delay > dev_priv->ips.min_delay) |
| 940 | new_delay = dev_priv->ips.min_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 941 | } |
| 942 | |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 943 | if (ironlake_set_drps(dev, new_delay)) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 944 | dev_priv->ips.cur_delay = new_delay; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 945 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 946 | spin_unlock(&mchdev_lock); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 947 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 948 | return; |
| 949 | } |
| 950 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 951 | static void notify_ring(struct drm_device *dev, |
| 952 | struct intel_ring_buffer *ring) |
| 953 | { |
Chris Wilson | 475553d | 2011-01-20 09:52:56 +0000 | [diff] [blame] | 954 | if (ring->obj == NULL) |
| 955 | return; |
| 956 | |
Chris Wilson | 814e9b5 | 2013-09-23 17:33:19 -0300 | [diff] [blame] | 957 | trace_i915_gem_request_complete(ring); |
Chris Wilson | 9862e60 | 2011-01-04 22:22:17 +0000 | [diff] [blame] | 958 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 959 | wake_up_all(&ring->irq_queue); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 960 | i915_queue_hangcheck(dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 961 | } |
| 962 | |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 963 | static void gen6_pm_rps_work(struct work_struct *work) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 964 | { |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 965 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 966 | rps.work); |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 967 | u32 pm_iir; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 968 | int new_delay, adj; |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 969 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 970 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 971 | pm_iir = dev_priv->rps.pm_iir; |
| 972 | dev_priv->rps.pm_iir = 0; |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 973 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
Paulo Zanoni | edbfdb4 | 2013-08-06 18:57:13 -0300 | [diff] [blame] | 974 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 975 | spin_unlock_irq(&dev_priv->irq_lock); |
Ben Widawsky | 4912d04 | 2011-04-25 11:25:20 -0700 | [diff] [blame] | 976 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 977 | /* Make sure we didn't queue anything we're not going to process. */ |
| 978 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); |
| 979 | |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 980 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 981 | return; |
| 982 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 983 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 984 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 985 | adj = dev_priv->rps.last_adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 986 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 987 | if (adj > 0) |
| 988 | adj *= 2; |
| 989 | else |
| 990 | adj = 1; |
| 991 | new_delay = dev_priv->rps.cur_delay + adj; |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 992 | |
| 993 | /* |
| 994 | * For better performance, jump directly |
| 995 | * to RPe if we're below it. |
| 996 | */ |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 997 | if (new_delay < dev_priv->rps.rpe_delay) |
Ville Syrjälä | 7425034 | 2013-06-25 21:38:11 +0300 | [diff] [blame] | 998 | new_delay = dev_priv->rps.rpe_delay; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 999 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
| 1000 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) |
| 1001 | new_delay = dev_priv->rps.rpe_delay; |
| 1002 | else |
| 1003 | new_delay = dev_priv->rps.min_delay; |
| 1004 | adj = 0; |
| 1005 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { |
| 1006 | if (adj < 0) |
| 1007 | adj *= 2; |
| 1008 | else |
| 1009 | adj = -1; |
| 1010 | new_delay = dev_priv->rps.cur_delay + adj; |
| 1011 | } else { /* unknown event */ |
| 1012 | new_delay = dev_priv->rps.cur_delay; |
| 1013 | } |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1014 | |
Ben Widawsky | 7924963 | 2012-09-07 19:43:42 -0700 | [diff] [blame] | 1015 | /* sysfs frequency interfaces may have snuck in while servicing the |
| 1016 | * interrupt |
| 1017 | */ |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 1018 | if (new_delay < (int)dev_priv->rps.min_delay) |
| 1019 | new_delay = dev_priv->rps.min_delay; |
| 1020 | if (new_delay > (int)dev_priv->rps.max_delay) |
| 1021 | new_delay = dev_priv->rps.max_delay; |
| 1022 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; |
| 1023 | |
| 1024 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 1025 | valleyview_set_rps(dev_priv->dev, new_delay); |
| 1026 | else |
| 1027 | gen6_set_rps(dev_priv->dev, new_delay); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1028 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 1029 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 1030 | } |
| 1031 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1032 | |
| 1033 | /** |
| 1034 | * ivybridge_parity_work - Workqueue called when a parity error interrupt |
| 1035 | * occurred. |
| 1036 | * @work: workqueue struct |
| 1037 | * |
| 1038 | * Doesn't actually do anything except notify userspace. As a consequence of |
| 1039 | * this event, userspace should try to remap the bad rows since statistically |
| 1040 | * it is likely the same row is more likely to go bad again. |
| 1041 | */ |
| 1042 | static void ivybridge_parity_work(struct work_struct *work) |
| 1043 | { |
| 1044 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1045 | l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1046 | u32 error_status, row, bank, subbank; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1047 | char *parity_event[6]; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1048 | uint32_t misccpctl; |
| 1049 | unsigned long flags; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1050 | uint8_t slice = 0; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1051 | |
| 1052 | /* We must turn off DOP level clock gating to access the L3 registers. |
| 1053 | * In order to prevent a get/put style interface, acquire struct mutex |
| 1054 | * any time we access those registers. |
| 1055 | */ |
| 1056 | mutex_lock(&dev_priv->dev->struct_mutex); |
| 1057 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1058 | /* If we've screwed up tracking, just let the interrupt fire again */ |
| 1059 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) |
| 1060 | goto out; |
| 1061 | |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1062 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
| 1063 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); |
| 1064 | POSTING_READ(GEN7_MISCCPCTL); |
| 1065 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1066 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
| 1067 | u32 reg; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1068 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1069 | slice--; |
| 1070 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) |
| 1071 | break; |
| 1072 | |
| 1073 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
| 1074 | |
| 1075 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
| 1076 | |
| 1077 | error_status = I915_READ(reg); |
| 1078 | row = GEN7_PARITY_ERROR_ROW(error_status); |
| 1079 | bank = GEN7_PARITY_ERROR_BANK(error_status); |
| 1080 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); |
| 1081 | |
| 1082 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); |
| 1083 | POSTING_READ(reg); |
| 1084 | |
| 1085 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; |
| 1086 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); |
| 1087 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); |
| 1088 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); |
| 1089 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); |
| 1090 | parity_event[5] = NULL; |
| 1091 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1092 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1093 | KOBJ_CHANGE, parity_event); |
| 1094 | |
| 1095 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
| 1096 | slice, row, bank, subbank); |
| 1097 | |
| 1098 | kfree(parity_event[4]); |
| 1099 | kfree(parity_event[3]); |
| 1100 | kfree(parity_event[2]); |
| 1101 | kfree(parity_event[1]); |
| 1102 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1103 | |
| 1104 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
| 1105 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1106 | out: |
| 1107 | WARN_ON(dev_priv->l3_parity.which_slice); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1108 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1109 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1110 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
| 1111 | |
| 1112 | mutex_unlock(&dev_priv->dev->struct_mutex); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1113 | } |
| 1114 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1115 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1116 | { |
| 1117 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1118 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 1119 | if (!HAS_L3_DPF(dev)) |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1120 | return; |
| 1121 | |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1122 | spin_lock(&dev_priv->irq_lock); |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1123 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1124 | spin_unlock(&dev_priv->irq_lock); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1125 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1126 | iir &= GT_PARITY_ERROR(dev); |
| 1127 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
| 1128 | dev_priv->l3_parity.which_slice |= 1 << 1; |
| 1129 | |
| 1130 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) |
| 1131 | dev_priv->l3_parity.which_slice |= 1 << 0; |
| 1132 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1133 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1134 | } |
| 1135 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1136 | static void ilk_gt_irq_handler(struct drm_device *dev, |
| 1137 | struct drm_i915_private *dev_priv, |
| 1138 | u32 gt_iir) |
| 1139 | { |
| 1140 | if (gt_iir & |
| 1141 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
| 1142 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1143 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
| 1144 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 1145 | } |
| 1146 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1147 | static void snb_gt_irq_handler(struct drm_device *dev, |
| 1148 | struct drm_i915_private *dev_priv, |
| 1149 | u32 gt_iir) |
| 1150 | { |
| 1151 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1152 | if (gt_iir & |
| 1153 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1154 | notify_ring(dev, &dev_priv->ring[RCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1155 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1156 | notify_ring(dev, &dev_priv->ring[VCS]); |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1157 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1158 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 1159 | |
Ben Widawsky | cc609d5 | 2013-05-28 19:22:29 -0700 | [diff] [blame] | 1160 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
| 1161 | GT_BSD_CS_ERROR_INTERRUPT | |
| 1162 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1163 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
| 1164 | i915_handle_error(dev, false); |
| 1165 | } |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1166 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1167 | if (gt_iir & GT_PARITY_ERROR(dev)) |
| 1168 | ivybridge_parity_error_irq_handler(dev, gt_iir); |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1169 | } |
| 1170 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1171 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
| 1172 | struct drm_i915_private *dev_priv, |
| 1173 | u32 master_ctl) |
| 1174 | { |
| 1175 | u32 rcs, bcs, vcs; |
| 1176 | uint32_t tmp = 0; |
| 1177 | irqreturn_t ret = IRQ_NONE; |
| 1178 | |
| 1179 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { |
| 1180 | tmp = I915_READ(GEN8_GT_IIR(0)); |
| 1181 | if (tmp) { |
| 1182 | ret = IRQ_HANDLED; |
| 1183 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; |
| 1184 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; |
| 1185 | if (rcs & GT_RENDER_USER_INTERRUPT) |
| 1186 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 1187 | if (bcs & GT_RENDER_USER_INTERRUPT) |
| 1188 | notify_ring(dev, &dev_priv->ring[BCS]); |
| 1189 | I915_WRITE(GEN8_GT_IIR(0), tmp); |
| 1190 | } else |
| 1191 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); |
| 1192 | } |
| 1193 | |
| 1194 | if (master_ctl & GEN8_GT_VCS1_IRQ) { |
| 1195 | tmp = I915_READ(GEN8_GT_IIR(1)); |
| 1196 | if (tmp) { |
| 1197 | ret = IRQ_HANDLED; |
| 1198 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; |
| 1199 | if (vcs & GT_RENDER_USER_INTERRUPT) |
| 1200 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 1201 | I915_WRITE(GEN8_GT_IIR(1), tmp); |
| 1202 | } else |
| 1203 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
| 1204 | } |
| 1205 | |
| 1206 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
| 1207 | tmp = I915_READ(GEN8_GT_IIR(3)); |
| 1208 | if (tmp) { |
| 1209 | ret = IRQ_HANDLED; |
| 1210 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; |
| 1211 | if (vcs & GT_RENDER_USER_INTERRUPT) |
| 1212 | notify_ring(dev, &dev_priv->ring[VECS]); |
| 1213 | I915_WRITE(GEN8_GT_IIR(3), tmp); |
| 1214 | } else |
| 1215 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); |
| 1216 | } |
| 1217 | |
| 1218 | return ret; |
| 1219 | } |
| 1220 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1221 | #define HPD_STORM_DETECT_PERIOD 1000 |
| 1222 | #define HPD_STORM_THRESHOLD 5 |
| 1223 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1224 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
Daniel Vetter | 22062db | 2013-06-27 17:52:11 +0200 | [diff] [blame] | 1225 | u32 hotplug_trigger, |
| 1226 | const u32 *hpd) |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1227 | { |
| 1228 | drm_i915_private_t *dev_priv = dev->dev_private; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1229 | int i; |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1230 | bool storm_detected = false; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1231 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1232 | if (!hotplug_trigger) |
| 1233 | return; |
| 1234 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1235 | spin_lock(&dev_priv->irq_lock); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1236 | for (i = 1; i < HPD_NUM_PINS; i++) { |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 1237 | |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1238 | WARN(((hpd[i] & hotplug_trigger) && |
| 1239 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), |
| 1240 | "Received HPD interrupt although disabled\n"); |
| 1241 | |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1242 | if (!(hpd[i] & hotplug_trigger) || |
| 1243 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
| 1244 | continue; |
| 1245 | |
Jani Nikula | bc5ead8c | 2013-05-07 15:10:29 +0300 | [diff] [blame] | 1246 | dev_priv->hpd_event_bits |= (1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1247 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
| 1248 | dev_priv->hpd_stats[i].hpd_last_jiffies |
| 1249 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { |
| 1250 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; |
| 1251 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1252 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1253 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
| 1254 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1255 | dev_priv->hpd_event_bits &= ~(1 << i); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1256 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1257 | storm_detected = true; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1258 | } else { |
| 1259 | dev_priv->hpd_stats[i].hpd_cnt++; |
Egbert Eich | b8f102e | 2013-07-26 14:14:24 +0200 | [diff] [blame] | 1260 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
| 1261 | dev_priv->hpd_stats[i].hpd_cnt); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1262 | } |
| 1263 | } |
| 1264 | |
Daniel Vetter | 10a504d | 2013-06-27 17:52:12 +0200 | [diff] [blame] | 1265 | if (storm_detected) |
| 1266 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 1267 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 5876fa0 | 2013-06-27 17:52:13 +0200 | [diff] [blame] | 1268 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1269 | /* |
| 1270 | * Our hotplug handler can grab modeset locks (by calling down into the |
| 1271 | * fb helpers). Hence it must not be run on our own dev-priv->wq work |
| 1272 | * queue for otherwise the flush_work in the pageflip code will |
| 1273 | * deadlock. |
| 1274 | */ |
| 1275 | schedule_work(&dev_priv->hotplug_work); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1276 | } |
| 1277 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1278 | static void gmbus_irq_handler(struct drm_device *dev) |
| 1279 | { |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1280 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1281 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1282 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1283 | } |
| 1284 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1285 | static void dp_aux_irq_handler(struct drm_device *dev) |
| 1286 | { |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1287 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1288 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1289 | wake_up_all(&dev_priv->gmbus_wait_queue); |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1290 | } |
| 1291 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1292 | #if defined(CONFIG_DEBUG_FS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1293 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1294 | uint32_t crc0, uint32_t crc1, |
| 1295 | uint32_t crc2, uint32_t crc3, |
| 1296 | uint32_t crc4) |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1297 | { |
| 1298 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1299 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
| 1300 | struct intel_pipe_crc_entry *entry; |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1301 | int head, tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1302 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1303 | spin_lock(&pipe_crc->lock); |
| 1304 | |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1305 | if (!pipe_crc->entries) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1306 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0c912c7 | 2013-10-15 18:55:37 +0100 | [diff] [blame] | 1307 | DRM_ERROR("spurious interrupt\n"); |
| 1308 | return; |
| 1309 | } |
| 1310 | |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1311 | head = pipe_crc->head; |
| 1312 | tail = pipe_crc->tail; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1313 | |
| 1314 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1315 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1316 | DRM_ERROR("CRC buffer overflowing\n"); |
| 1317 | return; |
| 1318 | } |
| 1319 | |
| 1320 | entry = &pipe_crc->entries[head]; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1321 | |
Daniel Vetter | 8bc5e95 | 2013-10-16 22:55:49 +0200 | [diff] [blame] | 1322 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
Daniel Vetter | eba94eb | 2013-10-16 22:55:46 +0200 | [diff] [blame] | 1323 | entry->crc[0] = crc0; |
| 1324 | entry->crc[1] = crc1; |
| 1325 | entry->crc[2] = crc2; |
| 1326 | entry->crc[3] = crc3; |
| 1327 | entry->crc[4] = crc4; |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1328 | |
| 1329 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1330 | pipe_crc->head = head; |
| 1331 | |
| 1332 | spin_unlock(&pipe_crc->lock); |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1333 | |
| 1334 | wake_up_interruptible(&pipe_crc->wq); |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1335 | } |
| 1336 | #else |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1337 | static inline void |
| 1338 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
| 1339 | uint32_t crc0, uint32_t crc1, |
| 1340 | uint32_t crc2, uint32_t crc3, |
| 1341 | uint32_t crc4) {} |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1342 | #endif |
| 1343 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1344 | |
| 1345 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 1346 | { |
| 1347 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1348 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1349 | display_pipe_crc_irq_handler(dev, pipe, |
| 1350 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1351 | 0, 0, 0, 0); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1352 | } |
| 1353 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1354 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Chris Wilson | fc6826d | 2012-04-15 11:56:03 +0100 | [diff] [blame] | 1355 | { |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1356 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1357 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1358 | display_pipe_crc_irq_handler(dev, pipe, |
| 1359 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
| 1360 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), |
| 1361 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), |
| 1362 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), |
| 1363 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1364 | } |
| 1365 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1366 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 1367 | { |
| 1368 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 0b5c5ed | 2013-10-16 22:55:53 +0200 | [diff] [blame] | 1369 | uint32_t res1, res2; |
| 1370 | |
| 1371 | if (INTEL_INFO(dev)->gen >= 3) |
| 1372 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
| 1373 | else |
| 1374 | res1 = 0; |
| 1375 | |
| 1376 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
| 1377 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
| 1378 | else |
| 1379 | res2 = 0; |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1380 | |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1381 | display_pipe_crc_irq_handler(dev, pipe, |
| 1382 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
| 1383 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), |
| 1384 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), |
| 1385 | res1, res2); |
Daniel Vetter | 41a05a3 | 2013-07-04 23:35:26 +0200 | [diff] [blame] | 1386 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1387 | |
| 1388 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
| 1389 | * IMR bits until the work is done. Other interrupts can be processed without |
| 1390 | * the work queue. */ |
| 1391 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) |
| 1392 | { |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1393 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
Ben Widawsky | 4848405 | 2013-05-28 19:22:27 -0700 | [diff] [blame] | 1394 | spin_lock(&dev_priv->irq_lock); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1395 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
Paulo Zanoni | 4d3b3d5 | 2013-08-09 17:04:36 -0300 | [diff] [blame] | 1396 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 1397 | spin_unlock(&dev_priv->irq_lock); |
Daniel Vetter | 2adbee6 | 2013-07-04 23:35:27 +0200 | [diff] [blame] | 1398 | |
| 1399 | queue_work(dev_priv->wq, &dev_priv->rps.work); |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1400 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1401 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1402 | if (HAS_VEBOX(dev_priv->dev)) { |
| 1403 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
| 1404 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1405 | |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1406 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
| 1407 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); |
| 1408 | i915_handle_error(dev_priv->dev, false); |
| 1409 | } |
Ben Widawsky | 12638c5 | 2013-05-28 19:22:31 -0700 | [diff] [blame] | 1410 | } |
Ben Widawsky | baf02a1 | 2013-05-28 19:22:24 -0700 | [diff] [blame] | 1411 | } |
| 1412 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 1413 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1414 | { |
| 1415 | struct drm_device *dev = (struct drm_device *) arg; |
| 1416 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1417 | u32 iir, gt_iir, pm_iir; |
| 1418 | irqreturn_t ret = IRQ_NONE; |
| 1419 | unsigned long irqflags; |
| 1420 | int pipe; |
| 1421 | u32 pipe_stats[I915_MAX_PIPES]; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1422 | |
| 1423 | atomic_inc(&dev_priv->irq_received); |
| 1424 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1425 | while (true) { |
| 1426 | iir = I915_READ(VLV_IIR); |
| 1427 | gt_iir = I915_READ(GTIIR); |
| 1428 | pm_iir = I915_READ(GEN6_PMIIR); |
| 1429 | |
| 1430 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) |
| 1431 | goto out; |
| 1432 | |
| 1433 | ret = IRQ_HANDLED; |
| 1434 | |
Daniel Vetter | e7b4c6b | 2012-03-30 20:24:35 +0200 | [diff] [blame] | 1435 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1436 | |
| 1437 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 1438 | for_each_pipe(pipe) { |
| 1439 | int reg = PIPESTAT(pipe); |
| 1440 | pipe_stats[pipe] = I915_READ(reg); |
| 1441 | |
| 1442 | /* |
| 1443 | * Clear the PIPE*STAT regs before the IIR |
| 1444 | */ |
| 1445 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 1446 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 1447 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 1448 | pipe_name(pipe)); |
| 1449 | I915_WRITE(reg, pipe_stats[pipe]); |
| 1450 | } |
| 1451 | } |
| 1452 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 1453 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1454 | for_each_pipe(pipe) { |
Jesse Barnes | 7b5562d | 2013-11-05 15:48:01 -0800 | [diff] [blame] | 1455 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1456 | drm_handle_vblank(dev, pipe); |
| 1457 | |
| 1458 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { |
| 1459 | intel_prepare_page_flip(dev, pipe); |
| 1460 | intel_finish_page_flip(dev, pipe); |
| 1461 | } |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 1462 | |
| 1463 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1464 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 1465 | } |
| 1466 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1467 | /* Consume port. Then clear IIR or we'll miss events */ |
| 1468 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
| 1469 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1470 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1471 | |
| 1472 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 1473 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1474 | |
| 1475 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 1476 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1477 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 1478 | I915_READ(PORT_HOTPLUG_STAT); |
| 1479 | } |
| 1480 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1481 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 1482 | gmbus_irq_handler(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1483 | |
Paulo Zanoni | 60611c1 | 2013-08-15 11:50:01 -0300 | [diff] [blame] | 1484 | if (pm_iir) |
Daniel Vetter | d0ecd7e | 2013-07-04 23:35:25 +0200 | [diff] [blame] | 1485 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 1486 | |
| 1487 | I915_WRITE(GTIIR, gt_iir); |
| 1488 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1489 | I915_WRITE(VLV_IIR, iir); |
| 1490 | } |
| 1491 | |
| 1492 | out: |
| 1493 | return ret; |
| 1494 | } |
| 1495 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1496 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1497 | { |
| 1498 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1499 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1500 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1501 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1502 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
| 1503 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1504 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
| 1505 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> |
| 1506 | SDE_AUDIO_POWER_SHIFT); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1507 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1508 | port_name(port)); |
| 1509 | } |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1510 | |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1511 | if (pch_iir & SDE_AUX_MASK) |
| 1512 | dp_aux_irq_handler(dev); |
| 1513 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1514 | if (pch_iir & SDE_GMBUS) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1515 | gmbus_irq_handler(dev); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1516 | |
| 1517 | if (pch_iir & SDE_AUDIO_HDCP_MASK) |
| 1518 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); |
| 1519 | |
| 1520 | if (pch_iir & SDE_AUDIO_TRANS_MASK) |
| 1521 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); |
| 1522 | |
| 1523 | if (pch_iir & SDE_POISON) |
| 1524 | DRM_ERROR("PCH poison interrupt\n"); |
| 1525 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1526 | if (pch_iir & SDE_FDI_MASK) |
| 1527 | for_each_pipe(pipe) |
| 1528 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1529 | pipe_name(pipe), |
| 1530 | I915_READ(FDI_RX_IIR(pipe))); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1531 | |
| 1532 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) |
| 1533 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); |
| 1534 | |
| 1535 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) |
| 1536 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); |
| 1537 | |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1538 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1539 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1540 | false)) |
| 1541 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1542 | |
| 1543 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) |
| 1544 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1545 | false)) |
| 1546 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1547 | } |
| 1548 | |
| 1549 | static void ivb_err_int_handler(struct drm_device *dev) |
| 1550 | { |
| 1551 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1552 | u32 err_int = I915_READ(GEN7_ERR_INT); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1553 | enum pipe pipe; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1554 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1555 | if (err_int & ERR_INT_POISON) |
| 1556 | DRM_ERROR("Poison interrupt\n"); |
| 1557 | |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1558 | for_each_pipe(pipe) { |
| 1559 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { |
| 1560 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, |
| 1561 | false)) |
| 1562 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", |
| 1563 | pipe_name(pipe)); |
| 1564 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1565 | |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1566 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
| 1567 | if (IS_IVYBRIDGE(dev)) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1568 | ivb_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1569 | else |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 1570 | hsw_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5a69b89 | 2013-10-16 22:55:52 +0200 | [diff] [blame] | 1571 | } |
| 1572 | } |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1573 | |
| 1574 | I915_WRITE(GEN7_ERR_INT, err_int); |
| 1575 | } |
| 1576 | |
| 1577 | static void cpt_serr_int_handler(struct drm_device *dev) |
| 1578 | { |
| 1579 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1580 | u32 serr_int = I915_READ(SERR_INT); |
| 1581 | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 1582 | if (serr_int & SERR_INT_POISON) |
| 1583 | DRM_ERROR("PCH poison interrupt\n"); |
| 1584 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1585 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
| 1586 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
| 1587 | false)) |
| 1588 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); |
| 1589 | |
| 1590 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) |
| 1591 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, |
| 1592 | false)) |
| 1593 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); |
| 1594 | |
| 1595 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) |
| 1596 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, |
| 1597 | false)) |
| 1598 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); |
| 1599 | |
| 1600 | I915_WRITE(SERR_INT, serr_int); |
Jesse Barnes | 776ad80 | 2011-01-04 15:09:39 -0800 | [diff] [blame] | 1601 | } |
| 1602 | |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1603 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
| 1604 | { |
| 1605 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 1606 | int pipe; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1607 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1608 | |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 1609 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
| 1610 | |
Ville Syrjälä | cfc33bf | 2013-04-17 17:48:48 +0300 | [diff] [blame] | 1611 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
| 1612 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> |
| 1613 | SDE_AUDIO_POWER_SHIFT_CPT); |
| 1614 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", |
| 1615 | port_name(port)); |
| 1616 | } |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1617 | |
| 1618 | if (pch_iir & SDE_AUX_MASK_CPT) |
Daniel Vetter | ce99c25 | 2012-12-01 13:53:47 +0100 | [diff] [blame] | 1619 | dp_aux_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1620 | |
| 1621 | if (pch_iir & SDE_GMBUS_CPT) |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 1622 | gmbus_irq_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1623 | |
| 1624 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) |
| 1625 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); |
| 1626 | |
| 1627 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) |
| 1628 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); |
| 1629 | |
| 1630 | if (pch_iir & SDE_FDI_MASK_CPT) |
| 1631 | for_each_pipe(pipe) |
| 1632 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
| 1633 | pipe_name(pipe), |
| 1634 | I915_READ(FDI_RX_IIR(pipe))); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1635 | |
| 1636 | if (pch_iir & SDE_ERROR_CPT) |
| 1637 | cpt_serr_int_handler(dev); |
Adam Jackson | 23e81d6 | 2012-06-06 15:45:44 -0400 | [diff] [blame] | 1638 | } |
| 1639 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1640 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1641 | { |
| 1642 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1643 | enum pipe pipe; |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1644 | |
| 1645 | if (de_iir & DE_AUX_CHANNEL_A) |
| 1646 | dp_aux_irq_handler(dev); |
| 1647 | |
| 1648 | if (de_iir & DE_GSE) |
| 1649 | intel_opregion_asle_intr(dev); |
| 1650 | |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1651 | if (de_iir & DE_POISON) |
| 1652 | DRM_ERROR("Poison interrupt\n"); |
| 1653 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1654 | for_each_pipe(pipe) { |
| 1655 | if (de_iir & DE_PIPE_VBLANK(pipe)) |
| 1656 | drm_handle_vblank(dev, pipe); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1657 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1658 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
| 1659 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) |
| 1660 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", |
| 1661 | pipe_name(pipe)); |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1662 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1663 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
| 1664 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1665 | |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1666 | /* plane/pipes map 1:1 on ilk+ */ |
| 1667 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { |
| 1668 | intel_prepare_page_flip(dev, pipe); |
| 1669 | intel_finish_page_flip_plane(dev, pipe); |
| 1670 | } |
Paulo Zanoni | c008bc6 | 2013-07-12 16:35:10 -0300 | [diff] [blame] | 1671 | } |
| 1672 | |
| 1673 | /* check event from PCH */ |
| 1674 | if (de_iir & DE_PCH_EVENT) { |
| 1675 | u32 pch_iir = I915_READ(SDEIIR); |
| 1676 | |
| 1677 | if (HAS_PCH_CPT(dev)) |
| 1678 | cpt_irq_handler(dev, pch_iir); |
| 1679 | else |
| 1680 | ibx_irq_handler(dev, pch_iir); |
| 1681 | |
| 1682 | /* should clear PCH hotplug event before clear CPU irq */ |
| 1683 | I915_WRITE(SDEIIR, pch_iir); |
| 1684 | } |
| 1685 | |
| 1686 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) |
| 1687 | ironlake_rps_change_irq_handler(dev); |
| 1688 | } |
| 1689 | |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1690 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| 1691 | { |
| 1692 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1693 | enum pipe i; |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1694 | |
| 1695 | if (de_iir & DE_ERR_INT_IVB) |
| 1696 | ivb_err_int_handler(dev); |
| 1697 | |
| 1698 | if (de_iir & DE_AUX_CHANNEL_A_IVB) |
| 1699 | dp_aux_irq_handler(dev); |
| 1700 | |
| 1701 | if (de_iir & DE_GSE_IVB) |
| 1702 | intel_opregion_asle_intr(dev); |
| 1703 | |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 1704 | for_each_pipe(i) { |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1705 | if (de_iir & (DE_PIPE_VBLANK_IVB(i))) |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1706 | drm_handle_vblank(dev, i); |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 1707 | |
| 1708 | /* plane/pipes map 1:1 on ilk+ */ |
| 1709 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { |
Paulo Zanoni | 9719fb9 | 2013-07-12 16:35:11 -0300 | [diff] [blame] | 1710 | intel_prepare_page_flip(dev, i); |
| 1711 | intel_finish_page_flip_plane(dev, i); |
| 1712 | } |
| 1713 | } |
| 1714 | |
| 1715 | /* check event from PCH */ |
| 1716 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { |
| 1717 | u32 pch_iir = I915_READ(SDEIIR); |
| 1718 | |
| 1719 | cpt_irq_handler(dev, pch_iir); |
| 1720 | |
| 1721 | /* clear PCH hotplug event before clear CPU irq */ |
| 1722 | I915_WRITE(SDEIIR, pch_iir); |
| 1723 | } |
| 1724 | } |
| 1725 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1726 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1727 | { |
| 1728 | struct drm_device *dev = (struct drm_device *) arg; |
| 1729 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1730 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1731 | irqreturn_t ret = IRQ_NONE; |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1732 | |
| 1733 | atomic_inc(&dev_priv->irq_received); |
| 1734 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1735 | /* We get interrupts on unclaimed registers, so check for this before we |
| 1736 | * do any I915_{READ,WRITE}. */ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1737 | intel_uncore_check_errors(dev); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 1738 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1739 | /* disable master interrupt before clearing iir */ |
| 1740 | de_ier = I915_READ(DEIER); |
| 1741 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
Paulo Zanoni | 23a7851 | 2013-07-12 16:35:14 -0300 | [diff] [blame] | 1742 | POSTING_READ(DEIER); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1743 | |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1744 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
| 1745 | * interrupts will will be stored on its back queue, and then we'll be |
| 1746 | * able to process them after we restore SDEIER (as soon as we restore |
| 1747 | * it, we'll get an interrupt if SDEIIR still has something to process |
| 1748 | * due to its back queue). */ |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1749 | if (!HAS_PCH_NOP(dev)) { |
| 1750 | sde_ier = I915_READ(SDEIER); |
| 1751 | I915_WRITE(SDEIER, 0); |
| 1752 | POSTING_READ(SDEIER); |
| 1753 | } |
Paulo Zanoni | 44498ae | 2013-02-22 17:05:28 -0300 | [diff] [blame] | 1754 | |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1755 | gt_iir = I915_READ(GTIIR); |
| 1756 | if (gt_iir) { |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1757 | if (INTEL_INFO(dev)->gen >= 6) |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1758 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
Paulo Zanoni | d8fc8a4 | 2013-07-19 18:57:55 -0300 | [diff] [blame] | 1759 | else |
| 1760 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1761 | I915_WRITE(GTIIR, gt_iir); |
| 1762 | ret = IRQ_HANDLED; |
| 1763 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1764 | |
| 1765 | de_iir = I915_READ(DEIIR); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1766 | if (de_iir) { |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1767 | if (INTEL_INFO(dev)->gen >= 7) |
| 1768 | ivb_display_irq_handler(dev, de_iir); |
| 1769 | else |
| 1770 | ilk_display_irq_handler(dev, de_iir); |
Chris Wilson | 0e43406 | 2012-05-09 21:45:44 +0100 | [diff] [blame] | 1771 | I915_WRITE(DEIIR, de_iir); |
| 1772 | ret = IRQ_HANDLED; |
| 1773 | } |
| 1774 | |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1775 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1776 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
| 1777 | if (pm_iir) { |
Paulo Zanoni | 1403c0d | 2013-08-15 11:51:32 -0300 | [diff] [blame] | 1778 | gen6_rps_irq_handler(dev_priv, pm_iir); |
Paulo Zanoni | f1af8fc | 2013-07-12 19:56:30 -0300 | [diff] [blame] | 1779 | I915_WRITE(GEN6_PMIIR, pm_iir); |
| 1780 | ret = IRQ_HANDLED; |
| 1781 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1782 | } |
| 1783 | |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1784 | I915_WRITE(DEIER, de_ier); |
| 1785 | POSTING_READ(DEIER); |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 1786 | if (!HAS_PCH_NOP(dev)) { |
| 1787 | I915_WRITE(SDEIER, sde_ier); |
| 1788 | POSTING_READ(SDEIER); |
| 1789 | } |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 1790 | |
| 1791 | return ret; |
| 1792 | } |
| 1793 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1794 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
| 1795 | { |
| 1796 | struct drm_device *dev = arg; |
| 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1798 | u32 master_ctl; |
| 1799 | irqreturn_t ret = IRQ_NONE; |
| 1800 | uint32_t tmp = 0; |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1801 | enum pipe pipe; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1802 | |
| 1803 | atomic_inc(&dev_priv->irq_received); |
| 1804 | |
| 1805 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
| 1806 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
| 1807 | if (!master_ctl) |
| 1808 | return IRQ_NONE; |
| 1809 | |
| 1810 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 1811 | POSTING_READ(GEN8_MASTER_IRQ); |
| 1812 | |
| 1813 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); |
| 1814 | |
| 1815 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
| 1816 | tmp = I915_READ(GEN8_DE_MISC_IIR); |
| 1817 | if (tmp & GEN8_DE_MISC_GSE) |
| 1818 | intel_opregion_asle_intr(dev); |
| 1819 | else if (tmp) |
| 1820 | DRM_ERROR("Unexpected DE Misc interrupt\n"); |
| 1821 | else |
| 1822 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); |
| 1823 | |
| 1824 | if (tmp) { |
| 1825 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); |
| 1826 | ret = IRQ_HANDLED; |
| 1827 | } |
| 1828 | } |
| 1829 | |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 1830 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
| 1831 | tmp = I915_READ(GEN8_DE_PORT_IIR); |
| 1832 | if (tmp & GEN8_AUX_CHANNEL_A) |
| 1833 | dp_aux_irq_handler(dev); |
| 1834 | else if (tmp) |
| 1835 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
| 1836 | else |
| 1837 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); |
| 1838 | |
| 1839 | if (tmp) { |
| 1840 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
| 1841 | ret = IRQ_HANDLED; |
| 1842 | } |
| 1843 | } |
| 1844 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1845 | for_each_pipe(pipe) { |
| 1846 | uint32_t pipe_iir; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1847 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1848 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
| 1849 | continue; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1850 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1851 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
| 1852 | if (pipe_iir & GEN8_PIPE_VBLANK) |
| 1853 | drm_handle_vblank(dev, pipe); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1854 | |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1855 | if (pipe_iir & GEN8_PIPE_FLIP_DONE) { |
| 1856 | intel_prepare_page_flip(dev, pipe); |
| 1857 | intel_finish_page_flip_plane(dev, pipe); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1858 | } |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1859 | |
Daniel Vetter | 0fbe787 | 2013-11-07 11:05:44 +0100 | [diff] [blame] | 1860 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
| 1861 | hsw_pipe_crc_irq_handler(dev, pipe); |
| 1862 | |
Daniel Vetter | 38d83c96 | 2013-11-07 11:05:46 +0100 | [diff] [blame] | 1863 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
| 1864 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, |
| 1865 | false)) |
| 1866 | DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", |
| 1867 | pipe_name(pipe)); |
| 1868 | } |
| 1869 | |
Daniel Vetter | 30100f2 | 2013-11-07 14:49:24 +0100 | [diff] [blame] | 1870 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
| 1871 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
| 1872 | pipe_name(pipe), |
| 1873 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); |
| 1874 | } |
Daniel Vetter | c42664c | 2013-11-07 11:05:40 +0100 | [diff] [blame] | 1875 | |
| 1876 | if (pipe_iir) { |
| 1877 | ret = IRQ_HANDLED; |
| 1878 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); |
| 1879 | } else |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1880 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
| 1881 | } |
| 1882 | |
Daniel Vetter | 92d03a8 | 2013-11-07 11:05:43 +0100 | [diff] [blame] | 1883 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
| 1884 | /* |
| 1885 | * FIXME(BDW): Assume for now that the new interrupt handling |
| 1886 | * scheme also closed the SDE interrupt handling race we've seen |
| 1887 | * on older pch-split platforms. But this needs testing. |
| 1888 | */ |
| 1889 | u32 pch_iir = I915_READ(SDEIIR); |
| 1890 | |
| 1891 | cpt_irq_handler(dev, pch_iir); |
| 1892 | |
| 1893 | if (pch_iir) { |
| 1894 | I915_WRITE(SDEIIR, pch_iir); |
| 1895 | ret = IRQ_HANDLED; |
| 1896 | } |
| 1897 | } |
| 1898 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1899 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
| 1900 | POSTING_READ(GEN8_MASTER_IRQ); |
| 1901 | |
| 1902 | return ret; |
| 1903 | } |
| 1904 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 1905 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
| 1906 | bool reset_completed) |
| 1907 | { |
| 1908 | struct intel_ring_buffer *ring; |
| 1909 | int i; |
| 1910 | |
| 1911 | /* |
| 1912 | * Notify all waiters for GPU completion events that reset state has |
| 1913 | * been changed, and that they need to restart their wait after |
| 1914 | * checking for potential errors (and bail out to drop locks if there is |
| 1915 | * a gpu reset pending so that i915_error_work_func can acquire them). |
| 1916 | */ |
| 1917 | |
| 1918 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ |
| 1919 | for_each_ring(ring, dev_priv, i) |
| 1920 | wake_up_all(&ring->irq_queue); |
| 1921 | |
| 1922 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ |
| 1923 | wake_up_all(&dev_priv->pending_flip_queue); |
| 1924 | |
| 1925 | /* |
| 1926 | * Signal tasks blocked in i915_gem_wait_for_error that the pending |
| 1927 | * reset state is cleared. |
| 1928 | */ |
| 1929 | if (reset_completed) |
| 1930 | wake_up_all(&dev_priv->gpu_error.reset_queue); |
| 1931 | } |
| 1932 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1933 | /** |
| 1934 | * i915_error_work_func - do process context error handling work |
| 1935 | * @work: work struct |
| 1936 | * |
| 1937 | * Fire an error uevent so userspace can see that a hang or error |
| 1938 | * was detected. |
| 1939 | */ |
| 1940 | static void i915_error_work_func(struct work_struct *work) |
| 1941 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1942 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
| 1943 | work); |
| 1944 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, |
| 1945 | gpu_error); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1946 | struct drm_device *dev = dev_priv->dev; |
Ben Widawsky | cce723e | 2013-07-19 09:16:42 -0700 | [diff] [blame] | 1947 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
| 1948 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; |
| 1949 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 1950 | int ret; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1951 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1952 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 1953 | |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1954 | /* |
| 1955 | * Note that there's only one work item which does gpu resets, so we |
| 1956 | * need not worry about concurrent gpu resets potentially incrementing |
| 1957 | * error->reset_counter twice. We only need to take care of another |
| 1958 | * racing irq/hangcheck declaring the gpu dead for a second time. A |
| 1959 | * quick check for that is good enough: schedule_work ensures the |
| 1960 | * correct ordering between hang detection and this work item, and since |
| 1961 | * the reset in-progress bit is only ever set by code outside of this |
| 1962 | * work we don't need to worry about any other races. |
| 1963 | */ |
| 1964 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { |
Chris Wilson | f803aa5 | 2010-09-19 12:38:26 +0100 | [diff] [blame] | 1965 | DRM_DEBUG_DRIVER("resetting chip\n"); |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1966 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
Daniel Vetter | 7db0ba2 | 2012-12-06 16:23:37 +0100 | [diff] [blame] | 1967 | reset_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1968 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 1969 | /* |
| 1970 | * All state reset _must_ be completed before we update the |
| 1971 | * reset counter, for otherwise waiters might miss the reset |
| 1972 | * pending state and not properly drop locks, resulting in |
| 1973 | * deadlocks with the reset work. |
| 1974 | */ |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1975 | ret = i915_reset(dev); |
| 1976 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 1977 | intel_display_handle_reset(dev); |
| 1978 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1979 | if (ret == 0) { |
| 1980 | /* |
| 1981 | * After all the gem state is reset, increment the reset |
| 1982 | * counter and wake up everyone waiting for the reset to |
| 1983 | * complete. |
| 1984 | * |
| 1985 | * Since unlock operations are a one-sided barrier only, |
| 1986 | * we need to insert a barrier here to order any seqno |
| 1987 | * updates before |
| 1988 | * the counter increment. |
| 1989 | */ |
| 1990 | smp_mb__before_atomic_inc(); |
| 1991 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
| 1992 | |
Dave Airlie | 5bdebb1 | 2013-10-11 14:07:25 +1000 | [diff] [blame] | 1993 | kobject_uevent_env(&dev->primary->kdev->kobj, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1994 | KOBJ_CHANGE, reset_done_event); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1995 | } else { |
| 1996 | atomic_set(&error->reset_counter, I915_WEDGED); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 1997 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1998 | |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 1999 | /* |
| 2000 | * Note: The wake_up also serves as a memory barrier so that |
| 2001 | * waiters see the update value of the reset counter atomic_t. |
| 2002 | */ |
| 2003 | i915_error_wake_up(dev_priv, true); |
Ben Gamari | f316a42 | 2009-09-14 17:48:46 -0400 | [diff] [blame] | 2004 | } |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2005 | } |
| 2006 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2007 | static void i915_report_and_clear_eir(struct drm_device *dev) |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2008 | { |
| 2009 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2010 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2011 | u32 eir = I915_READ(EIR); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2012 | int pipe, i; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2013 | |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2014 | if (!eir) |
| 2015 | return; |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2016 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2017 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2018 | |
Ben Widawsky | bd9854f | 2012-08-23 15:18:09 -0700 | [diff] [blame] | 2019 | i915_get_extra_instdone(dev, instdone); |
| 2020 | |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2021 | if (IS_G4X(dev)) { |
| 2022 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
| 2023 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2024 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2025 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2026 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2027 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2028 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2029 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2030 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2031 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2032 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2033 | } |
| 2034 | if (eir & GM45_ERROR_PAGE_TABLE) { |
| 2035 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2036 | pr_err("page table error\n"); |
| 2037 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2038 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2039 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2040 | } |
| 2041 | } |
| 2042 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2043 | if (!IS_GEN2(dev)) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2044 | if (eir & I915_ERROR_PAGE_TABLE) { |
| 2045 | u32 pgtbl_err = I915_READ(PGTBL_ER); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2046 | pr_err("page table error\n"); |
| 2047 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2048 | I915_WRITE(PGTBL_ER, pgtbl_err); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2049 | POSTING_READ(PGTBL_ER); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2050 | } |
| 2051 | } |
| 2052 | |
| 2053 | if (eir & I915_ERROR_MEMORY_REFRESH) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2054 | pr_err("memory refresh error:\n"); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2055 | for_each_pipe(pipe) |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2056 | pr_err("pipe %c stat: 0x%08x\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2057 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2058 | /* pipestat has already been acked */ |
| 2059 | } |
| 2060 | if (eir & I915_ERROR_INSTRUCTION) { |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2061 | pr_err("instruction error\n"); |
| 2062 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); |
Ben Widawsky | 050ee91 | 2012-08-22 11:32:15 -0700 | [diff] [blame] | 2063 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
| 2064 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2065 | if (INTEL_INFO(dev)->gen < 4) { |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2066 | u32 ipeir = I915_READ(IPEIR); |
| 2067 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2068 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
| 2069 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2070 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2071 | I915_WRITE(IPEIR, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2072 | POSTING_READ(IPEIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2073 | } else { |
| 2074 | u32 ipeir = I915_READ(IPEIR_I965); |
| 2075 | |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2076 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
| 2077 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2078 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
Joe Perches | a70491c | 2012-03-18 13:00:11 -0700 | [diff] [blame] | 2079 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2080 | I915_WRITE(IPEIR_I965, ipeir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2081 | POSTING_READ(IPEIR_I965); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2082 | } |
| 2083 | } |
| 2084 | |
| 2085 | I915_WRITE(EIR, eir); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2086 | POSTING_READ(EIR); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2087 | eir = I915_READ(EIR); |
| 2088 | if (eir) { |
| 2089 | /* |
| 2090 | * some errors might have become stuck, |
| 2091 | * mask them. |
| 2092 | */ |
| 2093 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); |
| 2094 | I915_WRITE(EMR, I915_READ(EMR) | eir); |
| 2095 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 2096 | } |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2097 | } |
| 2098 | |
| 2099 | /** |
| 2100 | * i915_handle_error - handle an error interrupt |
| 2101 | * @dev: drm device |
| 2102 | * |
| 2103 | * Do some basic checking of regsiter state at error interrupt time and |
| 2104 | * dump it to the syslog. Also call i915_capture_error_state() to make |
| 2105 | * sure we get a record and make it available in debugfs. Fire a uevent |
| 2106 | * so userspace knows something bad happened (should trigger collection |
| 2107 | * of a ring dump etc.). |
| 2108 | */ |
Chris Wilson | 527f9e9 | 2010-11-11 01:16:58 +0000 | [diff] [blame] | 2109 | void i915_handle_error(struct drm_device *dev, bool wedged) |
Chris Wilson | 35aed2e | 2010-05-27 13:18:12 +0100 | [diff] [blame] | 2110 | { |
| 2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2112 | |
| 2113 | i915_capture_error_state(dev); |
| 2114 | i915_report_and_clear_eir(dev); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2115 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2116 | if (wedged) { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2117 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
| 2118 | &dev_priv->gpu_error.reset_counter); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2119 | |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2120 | /* |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2121 | * Wakeup waiting processes so that the reset work function |
| 2122 | * i915_error_work_func doesn't deadlock trying to grab various |
| 2123 | * locks. By bumping the reset counter first, the woken |
| 2124 | * processes will see a reset in progress and back off, |
| 2125 | * releasing their locks and then wait for the reset completion. |
| 2126 | * We must do this for _all_ gpu waiters that might hold locks |
| 2127 | * that the reset work needs to acquire. |
| 2128 | * |
| 2129 | * Note: The wake_up serves as the required memory barrier to |
| 2130 | * ensure that the waiters see the updated value of the reset |
| 2131 | * counter atomic_t. |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2132 | */ |
Daniel Vetter | 17e1df0 | 2013-09-08 21:57:13 +0200 | [diff] [blame] | 2133 | i915_error_wake_up(dev_priv, false); |
Ben Gamari | 11ed50e | 2009-09-14 17:48:45 -0400 | [diff] [blame] | 2134 | } |
| 2135 | |
Daniel Vetter | 122f46b | 2013-09-04 17:36:14 +0200 | [diff] [blame] | 2136 | /* |
| 2137 | * Our reset work can grab modeset locks (since it needs to reset the |
| 2138 | * state of outstanding pagelips). Hence it must not be run on our own |
| 2139 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip |
| 2140 | * code will deadlock. |
| 2141 | */ |
| 2142 | schedule_work(&dev_priv->gpu_error.work); |
Jesse Barnes | 8a90523 | 2009-07-11 16:48:03 -0400 | [diff] [blame] | 2143 | } |
| 2144 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 2145 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2146 | { |
| 2147 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2148 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 2149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2150 | struct drm_i915_gem_object *obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2151 | struct intel_unpin_work *work; |
| 2152 | unsigned long flags; |
| 2153 | bool stall_detected; |
| 2154 | |
| 2155 | /* Ignore early vblank irqs */ |
| 2156 | if (intel_crtc == NULL) |
| 2157 | return; |
| 2158 | |
| 2159 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2160 | work = intel_crtc->unpin_work; |
| 2161 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 2162 | if (work == NULL || |
| 2163 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || |
| 2164 | !work->enable_stall_check) { |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2165 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
| 2166 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2167 | return; |
| 2168 | } |
| 2169 | |
| 2170 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2171 | obj = work->pending_flip_obj; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2172 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2173 | int dspsurf = DSPSURF(intel_crtc->plane); |
Armin Reese | 446f254 | 2012-03-30 16:20:16 -0700 | [diff] [blame] | 2174 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2175 | i915_gem_obj_ggtt_offset(obj); |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2176 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 2177 | int dspaddr = DSPADDR(intel_crtc->plane); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2178 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2179 | crtc->y * crtc->fb->pitches[0] + |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 2180 | crtc->x * crtc->fb->bits_per_pixel/8); |
| 2181 | } |
| 2182 | |
| 2183 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2184 | |
| 2185 | if (stall_detected) { |
| 2186 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); |
| 2187 | intel_prepare_page_flip(dev, intel_crtc->plane); |
| 2188 | } |
| 2189 | } |
| 2190 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2191 | /* Called from drm generic code, passed 'crtc' which |
| 2192 | * we use as a pipe index |
| 2193 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2194 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2195 | { |
| 2196 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2197 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2198 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2199 | if (!i915_pipe_enabled(dev, pipe)) |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 2200 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2201 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2202 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2203 | if (INTEL_INFO(dev)->gen >= 4) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2204 | i915_enable_pipestat(dev_priv, pipe, |
| 2205 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2206 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2207 | i915_enable_pipestat(dev_priv, pipe, |
| 2208 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2209 | |
| 2210 | /* maintain vblank delivery even in deep C-states */ |
| 2211 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 2212 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2213 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2214 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2215 | return 0; |
| 2216 | } |
| 2217 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2218 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2219 | { |
| 2220 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2221 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2222 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2223 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2224 | |
| 2225 | if (!i915_pipe_enabled(dev, pipe)) |
| 2226 | return -EINVAL; |
| 2227 | |
| 2228 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2229 | ironlake_enable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2230 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2231 | |
| 2232 | return 0; |
| 2233 | } |
| 2234 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2235 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
| 2236 | { |
| 2237 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2238 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2239 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2240 | |
| 2241 | if (!i915_pipe_enabled(dev, pipe)) |
| 2242 | return -EINVAL; |
| 2243 | |
| 2244 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2245 | imr = I915_READ(VLV_IMR); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 2246 | if (pipe == PIPE_A) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2247 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2248 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2249 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2250 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2251 | i915_enable_pipestat(dev_priv, pipe, |
| 2252 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2253 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2254 | |
| 2255 | return 0; |
| 2256 | } |
| 2257 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2258 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
| 2259 | { |
| 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2261 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2262 | |
| 2263 | if (!i915_pipe_enabled(dev, pipe)) |
| 2264 | return -EINVAL; |
| 2265 | |
| 2266 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 2267 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
| 2268 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2269 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2270 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2271 | return 0; |
| 2272 | } |
| 2273 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 2274 | /* Called from drm generic code, passed 'crtc' which |
| 2275 | * we use as a pipe index |
| 2276 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2277 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2278 | { |
| 2279 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 2280 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2281 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2282 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2283 | if (dev_priv->info->gen == 3) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 2284 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
Chris Wilson | 8692d00e | 2011-02-05 10:08:21 +0000 | [diff] [blame] | 2285 | |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2286 | i915_disable_pipestat(dev_priv, pipe, |
| 2287 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 2288 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
| 2289 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2290 | } |
| 2291 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2292 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2293 | { |
| 2294 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2295 | unsigned long irqflags; |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2296 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
Daniel Vetter | 40da17c | 2013-10-21 18:04:36 +0200 | [diff] [blame] | 2297 | DE_PIPE_VBLANK(pipe); |
Jesse Barnes | f796cf8 | 2011-04-07 13:58:17 -0700 | [diff] [blame] | 2298 | |
| 2299 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Paulo Zanoni | b518421 | 2013-07-12 20:00:08 -0300 | [diff] [blame] | 2300 | ironlake_disable_display_irq(dev_priv, bit); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2301 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2302 | } |
| 2303 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2304 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
| 2305 | { |
| 2306 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2307 | unsigned long irqflags; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2308 | u32 imr; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2309 | |
| 2310 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2311 | i915_disable_pipestat(dev_priv, pipe, |
| 2312 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2313 | imr = I915_READ(VLV_IMR); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 2314 | if (pipe == PIPE_A) |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2315 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2316 | else |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2317 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2318 | I915_WRITE(VLV_IMR, imr); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2319 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2320 | } |
| 2321 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2322 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
| 2323 | { |
| 2324 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2325 | unsigned long irqflags; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2326 | |
| 2327 | if (!i915_pipe_enabled(dev, pipe)) |
| 2328 | return; |
| 2329 | |
| 2330 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 7167d7c | 2013-11-07 11:05:45 +0100 | [diff] [blame] | 2331 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
| 2332 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2333 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2334 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 2335 | } |
| 2336 | |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2337 | static u32 |
| 2338 | ring_last_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2339 | { |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2340 | return list_entry(ring->request_list.prev, |
| 2341 | struct drm_i915_gem_request, list)->seqno; |
| 2342 | } |
| 2343 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2344 | static bool |
| 2345 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2346 | { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2347 | return (list_empty(&ring->request_list) || |
| 2348 | i915_seqno_passed(seqno, ring_last_seqno(ring))); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2349 | } |
| 2350 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2351 | static struct intel_ring_buffer * |
| 2352 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2353 | { |
| 2354 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2355 | u32 cmd, ipehr, acthd, acthd_min; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2356 | |
| 2357 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); |
| 2358 | if ((ipehr & ~(0x3 << 16)) != |
| 2359 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2360 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2361 | |
| 2362 | /* ACTHD is likely pointing to the dword after the actual command, |
| 2363 | * so scan backwards until we find the MBOX. |
| 2364 | */ |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2365 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2366 | acthd_min = max((int)acthd - 3 * 4, 0); |
| 2367 | do { |
| 2368 | cmd = ioread32(ring->virtual_start + acthd); |
| 2369 | if (cmd == ipehr) |
| 2370 | break; |
| 2371 | |
| 2372 | acthd -= 4; |
| 2373 | if (acthd < acthd_min) |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2374 | return NULL; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2375 | } while (1); |
| 2376 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2377 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
| 2378 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2379 | } |
| 2380 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2381 | static int semaphore_passed(struct intel_ring_buffer *ring) |
| 2382 | { |
| 2383 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 2384 | struct intel_ring_buffer *signaller; |
| 2385 | u32 seqno, ctl; |
| 2386 | |
| 2387 | ring->hangcheck.deadlock = true; |
| 2388 | |
| 2389 | signaller = semaphore_waits_for(ring, &seqno); |
| 2390 | if (signaller == NULL || signaller->hangcheck.deadlock) |
| 2391 | return -1; |
| 2392 | |
| 2393 | /* cursory check for an unkickable deadlock */ |
| 2394 | ctl = I915_READ_CTL(signaller); |
| 2395 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) |
| 2396 | return -1; |
| 2397 | |
| 2398 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); |
| 2399 | } |
| 2400 | |
| 2401 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) |
| 2402 | { |
| 2403 | struct intel_ring_buffer *ring; |
| 2404 | int i; |
| 2405 | |
| 2406 | for_each_ring(ring, dev_priv, i) |
| 2407 | ring->hangcheck.deadlock = false; |
| 2408 | } |
| 2409 | |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 2410 | static enum intel_ring_hangcheck_action |
| 2411 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2412 | { |
| 2413 | struct drm_device *dev = ring->dev; |
| 2414 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2415 | u32 tmp; |
| 2416 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2417 | if (ring->hangcheck.acthd != acthd) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2418 | return HANGCHECK_ACTIVE; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2419 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2420 | if (IS_GEN2(dev)) |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2421 | return HANGCHECK_HUNG; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2422 | |
| 2423 | /* Is the chip hanging on a WAIT_FOR_EVENT? |
| 2424 | * If so we can simply poke the RB_WAIT bit |
| 2425 | * and break the hang. This should work on |
| 2426 | * all but the second generation chipsets. |
| 2427 | */ |
| 2428 | tmp = I915_READ_CTL(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2429 | if (tmp & RING_WAIT) { |
| 2430 | DRM_ERROR("Kicking stuck wait on %s\n", |
| 2431 | ring->name); |
Chris Wilson | 09e14bf | 2013-10-10 09:37:19 +0100 | [diff] [blame] | 2432 | i915_handle_error(dev, false); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2433 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2434 | return HANGCHECK_KICK; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2435 | } |
Chris Wilson | a24a11e | 2013-03-14 17:52:05 +0200 | [diff] [blame] | 2436 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2437 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
| 2438 | switch (semaphore_passed(ring)) { |
| 2439 | default: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2440 | return HANGCHECK_HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2441 | case 1: |
| 2442 | DRM_ERROR("Kicking stuck semaphore on %s\n", |
| 2443 | ring->name); |
Chris Wilson | 09e14bf | 2013-10-10 09:37:19 +0100 | [diff] [blame] | 2444 | i915_handle_error(dev, false); |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2445 | I915_WRITE_CTL(ring, tmp); |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2446 | return HANGCHECK_KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2447 | case 0: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2448 | return HANGCHECK_WAIT; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2449 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2450 | } |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 2451 | |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2452 | return HANGCHECK_HUNG; |
Mika Kuoppala | ed5cbb0 | 2013-05-13 16:32:11 +0300 | [diff] [blame] | 2453 | } |
| 2454 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2455 | /** |
| 2456 | * This is called when the chip hasn't reported back with completed |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2457 | * batchbuffers in a long time. We keep track per ring seqno progress and |
| 2458 | * if there are no progress, hangcheck score for that ring is increased. |
| 2459 | * Further, acthd is inspected to see if the ring is stuck. On stuck case |
| 2460 | * we kick the ring. If we see no progress on three subsequent calls |
| 2461 | * we assume chip is wedged and try to fix it by resetting the chip. |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2462 | */ |
Damien Lespiau | a658b5d | 2013-08-08 22:28:56 +0100 | [diff] [blame] | 2463 | static void i915_hangcheck_elapsed(unsigned long data) |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2464 | { |
| 2465 | struct drm_device *dev = (struct drm_device *)data; |
| 2466 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2467 | struct intel_ring_buffer *ring; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2468 | int i; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2469 | int busy_count = 0, rings_hung = 0; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2470 | bool stuck[I915_NUM_RINGS] = { 0 }; |
| 2471 | #define BUSY 1 |
| 2472 | #define KICK 5 |
| 2473 | #define HUNG 20 |
| 2474 | #define FIRE 30 |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2475 | |
Ben Widawsky | 3e0dc6b | 2011-06-29 10:26:42 -0700 | [diff] [blame] | 2476 | if (!i915_enable_hangcheck) |
| 2477 | return; |
| 2478 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2479 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2480 | u32 seqno, acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2481 | bool busy = true; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2482 | |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2483 | semaphore_clear_deadlocks(dev_priv); |
| 2484 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2485 | seqno = ring->get_seqno(ring, false); |
| 2486 | acthd = intel_ring_get_active_head(ring); |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2487 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2488 | if (ring->hangcheck.seqno == seqno) { |
| 2489 | if (ring_idle(ring, seqno)) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2490 | ring->hangcheck.action = HANGCHECK_IDLE; |
| 2491 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2492 | if (waitqueue_active(&ring->irq_queue)) { |
| 2493 | /* Issue a wake-up to catch stuck h/w. */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 2494 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
Daniel Vetter | f4adcd2 | 2013-10-28 09:24:13 +0100 | [diff] [blame] | 2495 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
| 2496 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", |
| 2497 | ring->name); |
| 2498 | else |
| 2499 | DRM_INFO("Fake missed irq on %s\n", |
| 2500 | ring->name); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 2501 | wake_up_all(&ring->irq_queue); |
| 2502 | } |
| 2503 | /* Safeguard against driver failure */ |
| 2504 | ring->hangcheck.score += BUSY; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2505 | } else |
| 2506 | busy = false; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2507 | } else { |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2508 | /* We always increment the hangcheck score |
| 2509 | * if the ring is busy and still processing |
| 2510 | * the same request, so that no single request |
| 2511 | * can run indefinitely (such as a chain of |
| 2512 | * batches). The only time we do not increment |
| 2513 | * the hangcheck score on this ring, if this |
| 2514 | * ring is in a legitimate wait for another |
| 2515 | * ring. In that case the waiting ring is a |
| 2516 | * victim and we want to be sure we catch the |
| 2517 | * right culprit. Then every time we do kick |
| 2518 | * the ring, add a small increment to the |
| 2519 | * score so that we can catch a batch that is |
| 2520 | * being repeatedly kicked and so responsible |
| 2521 | * for stalling the machine. |
| 2522 | */ |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 2523 | ring->hangcheck.action = ring_stuck(ring, |
| 2524 | acthd); |
| 2525 | |
| 2526 | switch (ring->hangcheck.action) { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2527 | case HANGCHECK_IDLE: |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2528 | case HANGCHECK_WAIT: |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2529 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2530 | case HANGCHECK_ACTIVE: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2531 | ring->hangcheck.score += BUSY; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2532 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2533 | case HANGCHECK_KICK: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2534 | ring->hangcheck.score += KICK; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2535 | break; |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 2536 | case HANGCHECK_HUNG: |
Jani Nikula | ea04cb3 | 2013-08-11 12:44:02 +0300 | [diff] [blame] | 2537 | ring->hangcheck.score += HUNG; |
Chris Wilson | 6274f21 | 2013-06-10 11:20:21 +0100 | [diff] [blame] | 2538 | stuck[i] = true; |
| 2539 | break; |
| 2540 | } |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2541 | } |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2542 | } else { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 2543 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
| 2544 | |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2545 | /* Gradually reduce the count so that we catch DoS |
| 2546 | * attempts across multiple batches. |
| 2547 | */ |
| 2548 | if (ring->hangcheck.score > 0) |
| 2549 | ring->hangcheck.score--; |
Chris Wilson | d1e61e7 | 2012-04-10 17:00:41 +0100 | [diff] [blame] | 2550 | } |
| 2551 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2552 | ring->hangcheck.seqno = seqno; |
| 2553 | ring->hangcheck.acthd = acthd; |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2554 | busy_count += busy; |
Chris Wilson | 893eead | 2010-10-27 14:44:35 +0100 | [diff] [blame] | 2555 | } |
Eric Anholt | b9201c1 | 2010-01-08 14:25:16 -0800 | [diff] [blame] | 2556 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2557 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 9107e9d | 2013-06-10 11:20:20 +0100 | [diff] [blame] | 2558 | if (ring->hangcheck.score > FIRE) { |
Daniel Vetter | b8d88d1 | 2013-08-28 10:57:59 +0200 | [diff] [blame] | 2559 | DRM_INFO("%s on %s\n", |
| 2560 | stuck[i] ? "stuck" : "no progress", |
| 2561 | ring->name); |
Chris Wilson | a43adf0 | 2013-06-10 11:20:22 +0100 | [diff] [blame] | 2562 | rings_hung++; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 2563 | } |
| 2564 | } |
| 2565 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2566 | if (rings_hung) |
| 2567 | return i915_handle_error(dev, true); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2568 | |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 2569 | if (busy_count) |
| 2570 | /* Reset timer case chip hangs without another request |
| 2571 | * being added */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2572 | i915_queue_hangcheck(dev); |
| 2573 | } |
| 2574 | |
| 2575 | void i915_queue_hangcheck(struct drm_device *dev) |
| 2576 | { |
| 2577 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2578 | if (!i915_enable_hangcheck) |
| 2579 | return; |
| 2580 | |
| 2581 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 2582 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2583 | } |
| 2584 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2585 | static void ibx_irq_preinstall(struct drm_device *dev) |
| 2586 | { |
| 2587 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2588 | |
| 2589 | if (HAS_PCH_NOP(dev)) |
| 2590 | return; |
| 2591 | |
| 2592 | /* south display irq */ |
| 2593 | I915_WRITE(SDEIMR, 0xffffffff); |
| 2594 | /* |
| 2595 | * SDEIER is also touched by the interrupt handler to work around missed |
| 2596 | * PCH interrupts. Hence we can't update it after the interrupt handler |
| 2597 | * is enabled - instead we unconditionally enable all PCH interrupt |
| 2598 | * sources here, but then only unmask them as needed with SDEIMR. |
| 2599 | */ |
| 2600 | I915_WRITE(SDEIER, 0xffffffff); |
| 2601 | POSTING_READ(SDEIER); |
| 2602 | } |
| 2603 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2604 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
| 2605 | { |
| 2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2607 | |
| 2608 | /* and GT */ |
| 2609 | I915_WRITE(GTIMR, 0xffffffff); |
| 2610 | I915_WRITE(GTIER, 0x0); |
| 2611 | POSTING_READ(GTIER); |
| 2612 | |
| 2613 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2614 | /* and PM */ |
| 2615 | I915_WRITE(GEN6_PMIMR, 0xffffffff); |
| 2616 | I915_WRITE(GEN6_PMIER, 0x0); |
| 2617 | POSTING_READ(GEN6_PMIER); |
| 2618 | } |
| 2619 | } |
| 2620 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2621 | /* drm_dma.h hooks |
| 2622 | */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2623 | static void ironlake_irq_preinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2624 | { |
| 2625 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2626 | |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 2627 | atomic_set(&dev_priv->irq_received, 0); |
| 2628 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2629 | I915_WRITE(HWSTAM, 0xeffe); |
Daniel Vetter | bdfcdb6 | 2012-01-05 01:05:26 +0100 | [diff] [blame] | 2630 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2631 | I915_WRITE(DEIMR, 0xffffffff); |
| 2632 | I915_WRITE(DEIER, 0x0); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2633 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2634 | |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2635 | gen5_gt_irq_preinstall(dev); |
Zhenyu Wang | c650156 | 2009-11-03 18:57:21 +0000 | [diff] [blame] | 2636 | |
Paulo Zanoni | 91738a9 | 2013-06-05 14:21:51 -0300 | [diff] [blame] | 2637 | ibx_irq_preinstall(dev); |
Ben Widawsky | 7d99163 | 2013-05-28 19:22:25 -0700 | [diff] [blame] | 2638 | } |
| 2639 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2640 | static void valleyview_irq_preinstall(struct drm_device *dev) |
| 2641 | { |
| 2642 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 2643 | int pipe; |
| 2644 | |
| 2645 | atomic_set(&dev_priv->irq_received, 0); |
| 2646 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2647 | /* VLV magic */ |
| 2648 | I915_WRITE(VLV_IMR, 0); |
| 2649 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); |
| 2650 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); |
| 2651 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); |
| 2652 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2653 | /* and GT */ |
| 2654 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2655 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Daniel Vetter | d18ea1b | 2013-07-12 22:43:25 +0200 | [diff] [blame] | 2656 | |
| 2657 | gen5_gt_irq_preinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2658 | |
| 2659 | I915_WRITE(DPINVGTT, 0xff); |
| 2660 | |
| 2661 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2662 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 2663 | for_each_pipe(pipe) |
| 2664 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 2665 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2666 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 2667 | I915_WRITE(VLV_IER, 0x0); |
| 2668 | POSTING_READ(VLV_IER); |
| 2669 | } |
| 2670 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2671 | static void gen8_irq_preinstall(struct drm_device *dev) |
| 2672 | { |
| 2673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2674 | int pipe; |
| 2675 | |
| 2676 | atomic_set(&dev_priv->irq_received, 0); |
| 2677 | |
| 2678 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 2679 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2680 | |
| 2681 | /* IIR can theoretically queue up two events. Be paranoid */ |
| 2682 | #define GEN8_IRQ_INIT_NDX(type, which) do { \ |
| 2683 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 2684 | POSTING_READ(GEN8_##type##_IMR(which)); \ |
| 2685 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 2686 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 2687 | POSTING_READ(GEN8_##type##_IIR(which)); \ |
| 2688 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 2689 | } while (0) |
| 2690 | |
| 2691 | #define GEN8_IRQ_INIT(type) do { \ |
| 2692 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ |
| 2693 | POSTING_READ(GEN8_##type##_IMR); \ |
| 2694 | I915_WRITE(GEN8_##type##_IER, 0); \ |
| 2695 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ |
| 2696 | POSTING_READ(GEN8_##type##_IIR); \ |
| 2697 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ |
| 2698 | } while (0) |
| 2699 | |
| 2700 | GEN8_IRQ_INIT_NDX(GT, 0); |
| 2701 | GEN8_IRQ_INIT_NDX(GT, 1); |
| 2702 | GEN8_IRQ_INIT_NDX(GT, 2); |
| 2703 | GEN8_IRQ_INIT_NDX(GT, 3); |
| 2704 | |
| 2705 | for_each_pipe(pipe) { |
| 2706 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); |
| 2707 | } |
| 2708 | |
| 2709 | GEN8_IRQ_INIT(DE_PORT); |
| 2710 | GEN8_IRQ_INIT(DE_MISC); |
| 2711 | GEN8_IRQ_INIT(PCU); |
| 2712 | #undef GEN8_IRQ_INIT |
| 2713 | #undef GEN8_IRQ_INIT_NDX |
| 2714 | |
| 2715 | POSTING_READ(GEN8_PCU_IIR); |
Jesse Barnes | 09f2344 | 2014-01-10 13:13:09 -0800 | [diff] [blame] | 2716 | |
| 2717 | ibx_irq_preinstall(dev); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2718 | } |
| 2719 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2720 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2721 | { |
| 2722 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2723 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2724 | struct intel_encoder *intel_encoder; |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2725 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2726 | |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2727 | if (HAS_PCH_IBX(dev)) { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2728 | hotplug_irqs = SDE_HOTPLUG_MASK; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2729 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2730 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2731 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2732 | } else { |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2733 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2734 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 2735 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2736 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2737 | } |
| 2738 | |
Daniel Vetter | fee884e | 2013-07-04 23:35:21 +0200 | [diff] [blame] | 2739 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2740 | |
| 2741 | /* |
| 2742 | * Enable digital hotplug on the PCH, and configure the DP short pulse |
| 2743 | * duration to 2ms (which is the minimum in the Display Port spec) |
| 2744 | * |
| 2745 | * This register is the same on all known PCH chips. |
| 2746 | */ |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2747 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
| 2748 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
| 2749 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
| 2750 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
| 2751 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
| 2752 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
| 2753 | } |
| 2754 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2755 | static void ibx_irq_postinstall(struct drm_device *dev) |
| 2756 | { |
| 2757 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 2758 | u32 mask; |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2759 | |
Daniel Vetter | 692a04c | 2013-05-29 21:43:05 +0200 | [diff] [blame] | 2760 | if (HAS_PCH_NOP(dev)) |
| 2761 | return; |
| 2762 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2763 | if (HAS_PCH_IBX(dev)) { |
| 2764 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | |
Paulo Zanoni | de032bf | 2013-04-12 17:57:58 -0300 | [diff] [blame] | 2765 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 2766 | } else { |
| 2767 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; |
| 2768 | |
| 2769 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
| 2770 | } |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 2771 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2772 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
| 2773 | I915_WRITE(SDEIMR, ~mask); |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2774 | } |
| 2775 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2776 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
| 2777 | { |
| 2778 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2779 | u32 pm_irqs, gt_irqs; |
| 2780 | |
| 2781 | pm_irqs = gt_irqs = 0; |
| 2782 | |
| 2783 | dev_priv->gt_irq_mask = ~0; |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 2784 | if (HAS_L3_DPF(dev)) { |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2785 | /* L3 parity interrupt is always unmasked. */ |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 2786 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
| 2787 | gt_irqs |= GT_PARITY_ERROR(dev); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2788 | } |
| 2789 | |
| 2790 | gt_irqs |= GT_RENDER_USER_INTERRUPT; |
| 2791 | if (IS_GEN5(dev)) { |
| 2792 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | |
| 2793 | ILK_BSD_USER_INTERRUPT; |
| 2794 | } else { |
| 2795 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; |
| 2796 | } |
| 2797 | |
| 2798 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 2799 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 2800 | I915_WRITE(GTIER, gt_irqs); |
| 2801 | POSTING_READ(GTIER); |
| 2802 | |
| 2803 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2804 | pm_irqs |= GEN6_PM_RPS_EVENTS; |
| 2805 | |
| 2806 | if (HAS_VEBOX(dev)) |
| 2807 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; |
| 2808 | |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 2809 | dev_priv->pm_irq_mask = 0xffffffff; |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2810 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 2811 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2812 | I915_WRITE(GEN6_PMIER, pm_irqs); |
| 2813 | POSTING_READ(GEN6_PMIER); |
| 2814 | } |
| 2815 | } |
| 2816 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2817 | static int ironlake_irq_postinstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2818 | { |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2819 | unsigned long irqflags; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2820 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2821 | u32 display_mask, extra_mask; |
| 2822 | |
| 2823 | if (INTEL_INFO(dev)->gen >= 7) { |
| 2824 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | |
| 2825 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | |
| 2826 | DE_PLANEB_FLIP_DONE_IVB | |
| 2827 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | |
| 2828 | DE_ERR_INT_IVB); |
| 2829 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
| 2830 | DE_PIPEA_VBLANK_IVB); |
| 2831 | |
| 2832 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
| 2833 | } else { |
| 2834 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
| 2835 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 2836 | DE_AUX_CHANNEL_A | |
| 2837 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | |
| 2838 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
| 2839 | DE_POISON); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2840 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; |
| 2841 | } |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2842 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2843 | dev_priv->irq_mask = ~display_mask; |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2844 | |
| 2845 | /* should always can generate irq */ |
| 2846 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2847 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
Paulo Zanoni | 8e76f8d | 2013-07-12 20:01:56 -0300 | [diff] [blame] | 2848 | I915_WRITE(DEIER, display_mask | extra_mask); |
Chris Wilson | 3143a2b | 2010-11-16 15:55:10 +0000 | [diff] [blame] | 2849 | POSTING_READ(DEIER); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2850 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2851 | gen5_gt_irq_postinstall(dev); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2852 | |
Paulo Zanoni | d46da43 | 2013-02-08 17:35:15 -0200 | [diff] [blame] | 2853 | ibx_irq_postinstall(dev); |
Keith Packard | 7fe0b97 | 2011-09-19 13:31:02 -0700 | [diff] [blame] | 2854 | |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2855 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 6005ce4 | 2013-06-27 13:44:59 +0200 | [diff] [blame] | 2856 | /* Enable PCU event interrupts |
| 2857 | * |
| 2858 | * spinlocking not required here for correctness since interrupt |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2859 | * setup is guaranteed to run in single-threaded context. But we |
| 2860 | * need it to make the assert_spin_locked happy. */ |
| 2861 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2862 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
Daniel Vetter | 4bc9d43 | 2013-06-27 13:44:58 +0200 | [diff] [blame] | 2863 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 2864 | } |
| 2865 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2866 | return 0; |
| 2867 | } |
| 2868 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2869 | static int valleyview_irq_postinstall(struct drm_device *dev) |
| 2870 | { |
| 2871 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2872 | u32 enable_mask; |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 2873 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | |
| 2874 | PIPE_CRC_DONE_ENABLE; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2875 | unsigned long irqflags; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2876 | |
| 2877 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2878 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 2879 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2880 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2881 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
| 2882 | |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2883 | /* |
| 2884 | *Leave vblank interrupts masked initially. enable/disable will |
| 2885 | * toggle them based on usage. |
| 2886 | */ |
| 2887 | dev_priv->irq_mask = (~enable_mask) | |
| 2888 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | |
| 2889 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2890 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2891 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 2892 | POSTING_READ(PORT_HOTPLUG_EN); |
| 2893 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2894 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
| 2895 | I915_WRITE(VLV_IER, enable_mask); |
| 2896 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2897 | I915_WRITE(PIPESTAT(0), 0xffff); |
| 2898 | I915_WRITE(PIPESTAT(1), 0xffff); |
| 2899 | POSTING_READ(VLV_IER); |
| 2900 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2901 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 2902 | * just to make the assert_spin_locked check happy. */ |
| 2903 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 2904 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); |
| 2905 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); |
| 2906 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 2907 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Jesse Barnes | 31acc7f | 2012-06-20 10:53:11 -0700 | [diff] [blame] | 2908 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2909 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2910 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 2911 | |
Daniel Vetter | 0a9a8c9 | 2013-07-12 22:43:26 +0200 | [diff] [blame] | 2912 | gen5_gt_irq_postinstall(dev); |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 2913 | |
| 2914 | /* ack & enable invalid PTE error interrupts */ |
| 2915 | #if 0 /* FIXME: add support to irq handler for checking these bits */ |
| 2916 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
| 2917 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); |
| 2918 | #endif |
| 2919 | |
| 2920 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2921 | |
| 2922 | return 0; |
| 2923 | } |
| 2924 | |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2925 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
| 2926 | { |
| 2927 | int i; |
| 2928 | |
| 2929 | /* These are interrupts we'll toggle with the ring mask register */ |
| 2930 | uint32_t gt_interrupts[] = { |
| 2931 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
| 2932 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
| 2933 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, |
| 2934 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
| 2935 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, |
| 2936 | 0, |
| 2937 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
| 2938 | }; |
| 2939 | |
| 2940 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { |
| 2941 | u32 tmp = I915_READ(GEN8_GT_IIR(i)); |
| 2942 | if (tmp) |
| 2943 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", |
| 2944 | i, tmp); |
| 2945 | I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); |
| 2946 | I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); |
| 2947 | } |
| 2948 | POSTING_READ(GEN8_GT_IER(0)); |
| 2949 | } |
| 2950 | |
| 2951 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) |
| 2952 | { |
| 2953 | struct drm_device *dev = dev_priv->dev; |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 2954 | uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | |
| 2955 | GEN8_PIPE_CDCLK_CRC_DONE | |
| 2956 | GEN8_PIPE_FIFO_UNDERRUN | |
| 2957 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
| 2958 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2959 | int pipe; |
Daniel Vetter | 13b3a0a | 2013-11-07 15:31:52 +0100 | [diff] [blame] | 2960 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
| 2961 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; |
| 2962 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2963 | |
| 2964 | for_each_pipe(pipe) { |
| 2965 | u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
| 2966 | if (tmp) |
| 2967 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", |
| 2968 | pipe, tmp); |
| 2969 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); |
| 2970 | I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); |
| 2971 | } |
| 2972 | POSTING_READ(GEN8_DE_PIPE_ISR(0)); |
| 2973 | |
Daniel Vetter | 6d766f0 | 2013-11-07 14:49:55 +0100 | [diff] [blame] | 2974 | I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); |
| 2975 | I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 2976 | POSTING_READ(GEN8_DE_PORT_IER); |
| 2977 | } |
| 2978 | |
| 2979 | static int gen8_irq_postinstall(struct drm_device *dev) |
| 2980 | { |
| 2981 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2982 | |
| 2983 | gen8_gt_irq_postinstall(dev_priv); |
| 2984 | gen8_de_irq_postinstall(dev_priv); |
| 2985 | |
| 2986 | ibx_irq_postinstall(dev); |
| 2987 | |
| 2988 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
| 2989 | POSTING_READ(GEN8_MASTER_IRQ); |
| 2990 | |
| 2991 | return 0; |
| 2992 | } |
| 2993 | |
| 2994 | static void gen8_irq_uninstall(struct drm_device *dev) |
| 2995 | { |
| 2996 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2997 | int pipe; |
| 2998 | |
| 2999 | if (!dev_priv) |
| 3000 | return; |
| 3001 | |
| 3002 | atomic_set(&dev_priv->irq_received, 0); |
| 3003 | |
| 3004 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
| 3005 | |
| 3006 | #define GEN8_IRQ_FINI_NDX(type, which) do { \ |
| 3007 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
| 3008 | I915_WRITE(GEN8_##type##_IER(which), 0); \ |
| 3009 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ |
| 3010 | } while (0) |
| 3011 | |
| 3012 | #define GEN8_IRQ_FINI(type) do { \ |
| 3013 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ |
| 3014 | I915_WRITE(GEN8_##type##_IER, 0); \ |
| 3015 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ |
| 3016 | } while (0) |
| 3017 | |
| 3018 | GEN8_IRQ_FINI_NDX(GT, 0); |
| 3019 | GEN8_IRQ_FINI_NDX(GT, 1); |
| 3020 | GEN8_IRQ_FINI_NDX(GT, 2); |
| 3021 | GEN8_IRQ_FINI_NDX(GT, 3); |
| 3022 | |
| 3023 | for_each_pipe(pipe) { |
| 3024 | GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); |
| 3025 | } |
| 3026 | |
| 3027 | GEN8_IRQ_FINI(DE_PORT); |
| 3028 | GEN8_IRQ_FINI(DE_MISC); |
| 3029 | GEN8_IRQ_FINI(PCU); |
| 3030 | #undef GEN8_IRQ_FINI |
| 3031 | #undef GEN8_IRQ_FINI_NDX |
| 3032 | |
| 3033 | POSTING_READ(GEN8_PCU_IIR); |
| 3034 | } |
| 3035 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3036 | static void valleyview_irq_uninstall(struct drm_device *dev) |
| 3037 | { |
| 3038 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3039 | int pipe; |
| 3040 | |
| 3041 | if (!dev_priv) |
| 3042 | return; |
| 3043 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3044 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 3045 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3046 | for_each_pipe(pipe) |
| 3047 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3048 | |
| 3049 | I915_WRITE(HWSTAM, 0xffffffff); |
| 3050 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3051 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3052 | for_each_pipe(pipe) |
| 3053 | I915_WRITE(PIPESTAT(pipe), 0xffff); |
| 3054 | I915_WRITE(VLV_IIR, 0xffffffff); |
| 3055 | I915_WRITE(VLV_IMR, 0xffffffff); |
| 3056 | I915_WRITE(VLV_IER, 0x0); |
| 3057 | POSTING_READ(VLV_IER); |
| 3058 | } |
| 3059 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3060 | static void ironlake_irq_uninstall(struct drm_device *dev) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3061 | { |
| 3062 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 4697995 | 2011-04-07 13:53:55 -0700 | [diff] [blame] | 3063 | |
| 3064 | if (!dev_priv) |
| 3065 | return; |
| 3066 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3067 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 3068 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3069 | I915_WRITE(HWSTAM, 0xffffffff); |
| 3070 | |
| 3071 | I915_WRITE(DEIMR, 0xffffffff); |
| 3072 | I915_WRITE(DEIER, 0x0); |
| 3073 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3074 | if (IS_GEN7(dev)) |
| 3075 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3076 | |
| 3077 | I915_WRITE(GTIMR, 0xffffffff); |
| 3078 | I915_WRITE(GTIER, 0x0); |
| 3079 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 3080 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 3081 | if (HAS_PCH_NOP(dev)) |
| 3082 | return; |
| 3083 | |
Keith Packard | 192aac1f | 2011-09-20 10:12:44 -0700 | [diff] [blame] | 3084 | I915_WRITE(SDEIMR, 0xffffffff); |
| 3085 | I915_WRITE(SDEIER, 0x0); |
| 3086 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3087 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
| 3088 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 3089 | } |
| 3090 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3091 | static void i8xx_irq_preinstall(struct drm_device * dev) |
| 3092 | { |
| 3093 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3094 | int pipe; |
| 3095 | |
| 3096 | atomic_set(&dev_priv->irq_received, 0); |
| 3097 | |
| 3098 | for_each_pipe(pipe) |
| 3099 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3100 | I915_WRITE16(IMR, 0xffff); |
| 3101 | I915_WRITE16(IER, 0x0); |
| 3102 | POSTING_READ16(IER); |
| 3103 | } |
| 3104 | |
| 3105 | static int i8xx_irq_postinstall(struct drm_device *dev) |
| 3106 | { |
| 3107 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3108 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3109 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3110 | I915_WRITE16(EMR, |
| 3111 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 3112 | |
| 3113 | /* Unmask the interrupts that we always want on. */ |
| 3114 | dev_priv->irq_mask = |
| 3115 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3116 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3117 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3118 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 3119 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3120 | I915_WRITE16(IMR, dev_priv->irq_mask); |
| 3121 | |
| 3122 | I915_WRITE16(IER, |
| 3123 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3124 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3125 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 3126 | I915_USER_INTERRUPT); |
| 3127 | POSTING_READ16(IER); |
| 3128 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3129 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3130 | * just to make the assert_spin_locked check happy. */ |
| 3131 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 3132 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
| 3133 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3134 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3135 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3136 | return 0; |
| 3137 | } |
| 3138 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3139 | /* |
| 3140 | * Returns true when a page flip has completed. |
| 3141 | */ |
| 3142 | static bool i8xx_handle_vblank(struct drm_device *dev, |
| 3143 | int pipe, u16 iir) |
| 3144 | { |
| 3145 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3146 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); |
| 3147 | |
| 3148 | if (!drm_handle_vblank(dev, pipe)) |
| 3149 | return false; |
| 3150 | |
| 3151 | if ((iir & flip_pending) == 0) |
| 3152 | return false; |
| 3153 | |
| 3154 | intel_prepare_page_flip(dev, pipe); |
| 3155 | |
| 3156 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 3157 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 3158 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 3159 | * the flip is completed (no longer pending). Since this doesn't raise |
| 3160 | * an interrupt per se, we watch for the change at vblank. |
| 3161 | */ |
| 3162 | if (I915_READ16(ISR) & flip_pending) |
| 3163 | return false; |
| 3164 | |
| 3165 | intel_finish_page_flip(dev, pipe); |
| 3166 | |
| 3167 | return true; |
| 3168 | } |
| 3169 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 3170 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3171 | { |
| 3172 | struct drm_device *dev = (struct drm_device *) arg; |
| 3173 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3174 | u16 iir, new_iir; |
| 3175 | u32 pipe_stats[2]; |
| 3176 | unsigned long irqflags; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3177 | int pipe; |
| 3178 | u16 flip_mask = |
| 3179 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3180 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
| 3181 | |
| 3182 | atomic_inc(&dev_priv->irq_received); |
| 3183 | |
| 3184 | iir = I915_READ16(IIR); |
| 3185 | if (iir == 0) |
| 3186 | return IRQ_NONE; |
| 3187 | |
| 3188 | while (iir & ~flip_mask) { |
| 3189 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 3190 | * have been cleared after the pipestat interrupt was received. |
| 3191 | * It doesn't set the bit in iir again, but it still produces |
| 3192 | * interrupts (for non-MSI). |
| 3193 | */ |
| 3194 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3195 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 3196 | i915_handle_error(dev, false); |
| 3197 | |
| 3198 | for_each_pipe(pipe) { |
| 3199 | int reg = PIPESTAT(pipe); |
| 3200 | pipe_stats[pipe] = I915_READ(reg); |
| 3201 | |
| 3202 | /* |
| 3203 | * Clear the PIPE*STAT regs before the IIR |
| 3204 | */ |
| 3205 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 3206 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 3207 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 3208 | pipe_name(pipe)); |
| 3209 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3210 | } |
| 3211 | } |
| 3212 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3213 | |
| 3214 | I915_WRITE16(IIR, iir & ~flip_mask); |
| 3215 | new_iir = I915_READ16(IIR); /* Flush posted writes */ |
| 3216 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3217 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3218 | |
| 3219 | if (iir & I915_USER_INTERRUPT) |
| 3220 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 3221 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3222 | for_each_pipe(pipe) { |
| 3223 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 3224 | i8xx_handle_vblank(dev, pipe, iir)) |
| 3225 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3226 | |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3227 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 3228 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3229 | } |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3230 | |
| 3231 | iir = new_iir; |
| 3232 | } |
| 3233 | |
| 3234 | return IRQ_HANDLED; |
| 3235 | } |
| 3236 | |
| 3237 | static void i8xx_irq_uninstall(struct drm_device * dev) |
| 3238 | { |
| 3239 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3240 | int pipe; |
| 3241 | |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3242 | for_each_pipe(pipe) { |
| 3243 | /* Clear enable bits; then clear status bits */ |
| 3244 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3245 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 3246 | } |
| 3247 | I915_WRITE16(IMR, 0xffff); |
| 3248 | I915_WRITE16(IER, 0x0); |
| 3249 | I915_WRITE16(IIR, I915_READ16(IIR)); |
| 3250 | } |
| 3251 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3252 | static void i915_irq_preinstall(struct drm_device * dev) |
| 3253 | { |
| 3254 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3255 | int pipe; |
| 3256 | |
| 3257 | atomic_set(&dev_priv->irq_received, 0); |
| 3258 | |
| 3259 | if (I915_HAS_HOTPLUG(dev)) { |
| 3260 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3261 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3262 | } |
| 3263 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 3264 | I915_WRITE16(HWSTAM, 0xeffe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3265 | for_each_pipe(pipe) |
| 3266 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3267 | I915_WRITE(IMR, 0xffffffff); |
| 3268 | I915_WRITE(IER, 0x0); |
| 3269 | POSTING_READ(IER); |
| 3270 | } |
| 3271 | |
| 3272 | static int i915_irq_postinstall(struct drm_device *dev) |
| 3273 | { |
| 3274 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3275 | u32 enable_mask; |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3276 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3277 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3278 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
| 3279 | |
| 3280 | /* Unmask the interrupts that we always want on. */ |
| 3281 | dev_priv->irq_mask = |
| 3282 | ~(I915_ASLE_INTERRUPT | |
| 3283 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3284 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3285 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3286 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 3287 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3288 | |
| 3289 | enable_mask = |
| 3290 | I915_ASLE_INTERRUPT | |
| 3291 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3292 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3293 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | |
| 3294 | I915_USER_INTERRUPT; |
| 3295 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3296 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3297 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3298 | POSTING_READ(PORT_HOTPLUG_EN); |
| 3299 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3300 | /* Enable in IER... */ |
| 3301 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 3302 | /* and unmask in IMR */ |
| 3303 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
| 3304 | } |
| 3305 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3306 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 3307 | I915_WRITE(IER, enable_mask); |
| 3308 | POSTING_READ(IER); |
| 3309 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 3310 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3311 | |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3312 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3313 | * just to make the assert_spin_locked check happy. */ |
| 3314 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 3315 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
| 3316 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); |
Daniel Vetter | 379ef82 | 2013-10-16 22:55:56 +0200 | [diff] [blame] | 3317 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3318 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3319 | return 0; |
| 3320 | } |
| 3321 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3322 | /* |
| 3323 | * Returns true when a page flip has completed. |
| 3324 | */ |
| 3325 | static bool i915_handle_vblank(struct drm_device *dev, |
| 3326 | int plane, int pipe, u32 iir) |
| 3327 | { |
| 3328 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3329 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
| 3330 | |
| 3331 | if (!drm_handle_vblank(dev, pipe)) |
| 3332 | return false; |
| 3333 | |
| 3334 | if ((iir & flip_pending) == 0) |
| 3335 | return false; |
| 3336 | |
| 3337 | intel_prepare_page_flip(dev, plane); |
| 3338 | |
| 3339 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
| 3340 | * to '0' on the following vblank, i.e. IIR has the Pendingflip |
| 3341 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence |
| 3342 | * the flip is completed (no longer pending). Since this doesn't raise |
| 3343 | * an interrupt per se, we watch for the change at vblank. |
| 3344 | */ |
| 3345 | if (I915_READ(ISR) & flip_pending) |
| 3346 | return false; |
| 3347 | |
| 3348 | intel_finish_page_flip(dev, pipe); |
| 3349 | |
| 3350 | return true; |
| 3351 | } |
| 3352 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 3353 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3354 | { |
| 3355 | struct drm_device *dev = (struct drm_device *) arg; |
| 3356 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3357 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3358 | unsigned long irqflags; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3359 | u32 flip_mask = |
| 3360 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3361 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3362 | int pipe, ret = IRQ_NONE; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3363 | |
| 3364 | atomic_inc(&dev_priv->irq_received); |
| 3365 | |
| 3366 | iir = I915_READ(IIR); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3367 | do { |
| 3368 | bool irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3369 | bool blc_event = false; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3370 | |
| 3371 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 3372 | * have been cleared after the pipestat interrupt was received. |
| 3373 | * It doesn't set the bit in iir again, but it still produces |
| 3374 | * interrupts (for non-MSI). |
| 3375 | */ |
| 3376 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3377 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 3378 | i915_handle_error(dev, false); |
| 3379 | |
| 3380 | for_each_pipe(pipe) { |
| 3381 | int reg = PIPESTAT(pipe); |
| 3382 | pipe_stats[pipe] = I915_READ(reg); |
| 3383 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3384 | /* Clear the PIPE*STAT regs before the IIR */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3385 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 3386 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 3387 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 3388 | pipe_name(pipe)); |
| 3389 | I915_WRITE(reg, pipe_stats[pipe]); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3390 | irq_received = true; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3391 | } |
| 3392 | } |
| 3393 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3394 | |
| 3395 | if (!irq_received) |
| 3396 | break; |
| 3397 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3398 | /* Consume port. Then clear IIR or we'll miss events */ |
| 3399 | if ((I915_HAS_HOTPLUG(dev)) && |
| 3400 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 3401 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 3402 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3403 | |
| 3404 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 3405 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 3406 | |
| 3407 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
| 3408 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3409 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3410 | POSTING_READ(PORT_HOTPLUG_STAT); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3411 | } |
| 3412 | |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3413 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3414 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 3415 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3416 | if (iir & I915_USER_INTERRUPT) |
| 3417 | notify_ring(dev, &dev_priv->ring[RCS]); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3418 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3419 | for_each_pipe(pipe) { |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3420 | int plane = pipe; |
| 3421 | if (IS_MOBILE(dev)) |
| 3422 | plane = !plane; |
Ville Syrjälä | 5e2032d | 2013-02-19 15:16:38 +0200 | [diff] [blame] | 3423 | |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3424 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
| 3425 | i915_handle_vblank(dev, plane, pipe, iir)) |
| 3426 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3427 | |
| 3428 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 3429 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3430 | |
| 3431 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 3432 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3433 | } |
| 3434 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3435 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 3436 | intel_opregion_asle_intr(dev); |
| 3437 | |
| 3438 | /* With MSI, interrupts are only generated when iir |
| 3439 | * transitions from zero to nonzero. If another bit got |
| 3440 | * set while we were handling the existing iir bits, then |
| 3441 | * we would never get another interrupt. |
| 3442 | * |
| 3443 | * This is fine on non-MSI as well, as if we hit this path |
| 3444 | * we avoid exiting the interrupt handler only to generate |
| 3445 | * another one. |
| 3446 | * |
| 3447 | * Note that for MSI this could cause a stray interrupt report |
| 3448 | * if an interrupt landed in the time between writing IIR and |
| 3449 | * the posting read. This should be rare enough to never |
| 3450 | * trigger the 99% of 100,000 interrupts test for disabling |
| 3451 | * stray interrupts. |
| 3452 | */ |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3453 | ret = IRQ_HANDLED; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3454 | iir = new_iir; |
Chris Wilson | 38bde18 | 2012-04-24 22:59:50 +0100 | [diff] [blame] | 3455 | } while (iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3456 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3457 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 8291ee9 | 2012-04-24 22:59:47 +0100 | [diff] [blame] | 3458 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3459 | return ret; |
| 3460 | } |
| 3461 | |
| 3462 | static void i915_irq_uninstall(struct drm_device * dev) |
| 3463 | { |
| 3464 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3465 | int pipe; |
| 3466 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3467 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 3468 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3469 | if (I915_HAS_HOTPLUG(dev)) { |
| 3470 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3471 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 3472 | } |
| 3473 | |
Chris Wilson | 00d98eb | 2012-04-24 22:59:48 +0100 | [diff] [blame] | 3474 | I915_WRITE16(HWSTAM, 0xffff); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 3475 | for_each_pipe(pipe) { |
| 3476 | /* Clear enable bits; then clear status bits */ |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3477 | I915_WRITE(PIPESTAT(pipe), 0); |
Chris Wilson | 55b3975 | 2012-04-24 22:59:49 +0100 | [diff] [blame] | 3478 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
| 3479 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3480 | I915_WRITE(IMR, 0xffffffff); |
| 3481 | I915_WRITE(IER, 0x0); |
| 3482 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3483 | I915_WRITE(IIR, I915_READ(IIR)); |
| 3484 | } |
| 3485 | |
| 3486 | static void i965_irq_preinstall(struct drm_device * dev) |
| 3487 | { |
| 3488 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3489 | int pipe; |
| 3490 | |
| 3491 | atomic_set(&dev_priv->irq_received, 0); |
| 3492 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 3493 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3494 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3495 | |
| 3496 | I915_WRITE(HWSTAM, 0xeffe); |
| 3497 | for_each_pipe(pipe) |
| 3498 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3499 | I915_WRITE(IMR, 0xffffffff); |
| 3500 | I915_WRITE(IER, 0x0); |
| 3501 | POSTING_READ(IER); |
| 3502 | } |
| 3503 | |
| 3504 | static int i965_irq_postinstall(struct drm_device *dev) |
| 3505 | { |
| 3506 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 3507 | u32 enable_mask; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3508 | u32 error_mask; |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3509 | unsigned long irqflags; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3510 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3511 | /* Unmask the interrupts that we always want on. */ |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 3512 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 3513 | I915_DISPLAY_PORT_INTERRUPT | |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 3514 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
| 3515 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | |
| 3516 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3517 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | |
| 3518 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); |
| 3519 | |
| 3520 | enable_mask = ~dev_priv->irq_mask; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 3521 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3522 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
Chris Wilson | bbba0a9 | 2012-04-24 22:59:51 +0100 | [diff] [blame] | 3523 | enable_mask |= I915_USER_INTERRUPT; |
| 3524 | |
| 3525 | if (IS_G4X(dev)) |
| 3526 | enable_mask |= I915_BSD_USER_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3527 | |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3528 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3529 | * just to make the assert_spin_locked check happy. */ |
| 3530 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 3b6c42e | 2013-10-21 18:04:35 +0200 | [diff] [blame] | 3531 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); |
| 3532 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); |
| 3533 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); |
Daniel Vetter | b79480b | 2013-06-27 17:52:10 +0200 | [diff] [blame] | 3534 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3535 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3536 | /* |
| 3537 | * Enable some error detection, note the instruction error mask |
| 3538 | * bit is reserved, so we leave it masked. |
| 3539 | */ |
| 3540 | if (IS_G4X(dev)) { |
| 3541 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
| 3542 | GM45_ERROR_MEM_PRIV | |
| 3543 | GM45_ERROR_CP_PRIV | |
| 3544 | I915_ERROR_MEMORY_REFRESH); |
| 3545 | } else { |
| 3546 | error_mask = ~(I915_ERROR_PAGE_TABLE | |
| 3547 | I915_ERROR_MEMORY_REFRESH); |
| 3548 | } |
| 3549 | I915_WRITE(EMR, error_mask); |
| 3550 | |
| 3551 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 3552 | I915_WRITE(IER, enable_mask); |
| 3553 | POSTING_READ(IER); |
| 3554 | |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3555 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3556 | POSTING_READ(PORT_HOTPLUG_EN); |
| 3557 | |
Jani Nikula | f49e38d | 2013-04-29 13:02:54 +0300 | [diff] [blame] | 3558 | i915_enable_asle_pipestat(dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3559 | |
| 3560 | return 0; |
| 3561 | } |
| 3562 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3563 | static void i915_hpd_irq_setup(struct drm_device *dev) |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3564 | { |
| 3565 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 3566 | struct drm_mode_config *mode_config = &dev->mode_config; |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3567 | struct intel_encoder *intel_encoder; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3568 | u32 hotplug_en; |
| 3569 | |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3570 | assert_spin_locked(&dev_priv->irq_lock); |
| 3571 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3572 | if (I915_HAS_HOTPLUG(dev)) { |
| 3573 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 3574 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; |
| 3575 | /* Note HDMI and DP share hotplug bits */ |
Egbert Eich | e5868a3 | 2013-02-28 04:17:12 -0500 | [diff] [blame] | 3576 | /* enable bits are the same for all generations */ |
Egbert Eich | cd569ae | 2013-04-16 13:36:57 +0200 | [diff] [blame] | 3577 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
| 3578 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
| 3579 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3580 | /* Programming the CRT detection parameters tends |
| 3581 | to generate a spurious hotplug event about three |
| 3582 | seconds later. So just do it once. |
| 3583 | */ |
| 3584 | if (IS_G4X(dev)) |
| 3585 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
Daniel Vetter | 85fc95b | 2013-03-27 15:47:11 +0100 | [diff] [blame] | 3586 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3587 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3588 | |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3589 | /* Ignore TV since it's buggy */ |
| 3590 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 3591 | } |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3592 | } |
| 3593 | |
Daniel Vetter | ff1f525 | 2012-10-02 15:10:55 +0200 | [diff] [blame] | 3594 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3595 | { |
| 3596 | struct drm_device *dev = (struct drm_device *) arg; |
| 3597 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3598 | u32 iir, new_iir; |
| 3599 | u32 pipe_stats[I915_MAX_PIPES]; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3600 | unsigned long irqflags; |
| 3601 | int irq_received; |
| 3602 | int ret = IRQ_NONE, pipe; |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 3603 | u32 flip_mask = |
| 3604 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
| 3605 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3606 | |
| 3607 | atomic_inc(&dev_priv->irq_received); |
| 3608 | |
| 3609 | iir = I915_READ(IIR); |
| 3610 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3611 | for (;;) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 3612 | bool blc_event = false; |
| 3613 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 3614 | irq_received = (iir & ~flip_mask) != 0; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3615 | |
| 3616 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 3617 | * have been cleared after the pipestat interrupt was received. |
| 3618 | * It doesn't set the bit in iir again, but it still produces |
| 3619 | * interrupts (for non-MSI). |
| 3620 | */ |
| 3621 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3622 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
| 3623 | i915_handle_error(dev, false); |
| 3624 | |
| 3625 | for_each_pipe(pipe) { |
| 3626 | int reg = PIPESTAT(pipe); |
| 3627 | pipe_stats[pipe] = I915_READ(reg); |
| 3628 | |
| 3629 | /* |
| 3630 | * Clear the PIPE*STAT regs before the IIR |
| 3631 | */ |
| 3632 | if (pipe_stats[pipe] & 0x8000ffff) { |
| 3633 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
| 3634 | DRM_DEBUG_DRIVER("pipe %c underrun\n", |
| 3635 | pipe_name(pipe)); |
| 3636 | I915_WRITE(reg, pipe_stats[pipe]); |
| 3637 | irq_received = 1; |
| 3638 | } |
| 3639 | } |
| 3640 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3641 | |
| 3642 | if (!irq_received) |
| 3643 | break; |
| 3644 | |
| 3645 | ret = IRQ_HANDLED; |
| 3646 | |
| 3647 | /* Consume port. Then clear IIR or we'll miss events */ |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 3648 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3649 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 3650 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
| 3651 | HOTPLUG_INT_STATUS_G4X : |
Daniel Vetter | 4f7fd70 | 2013-06-24 21:33:28 +0200 | [diff] [blame] | 3652 | HOTPLUG_INT_STATUS_I915); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3653 | |
| 3654 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
| 3655 | hotplug_status); |
Daniel Vetter | 91d131d | 2013-06-27 17:52:14 +0200 | [diff] [blame] | 3656 | |
| 3657 | intel_hpd_irq_handler(dev, hotplug_trigger, |
| 3658 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); |
| 3659 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3660 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 3661 | I915_READ(PORT_HOTPLUG_STAT); |
| 3662 | } |
| 3663 | |
Ville Syrjälä | 21ad833 | 2013-02-19 15:16:39 +0200 | [diff] [blame] | 3664 | I915_WRITE(IIR, iir & ~flip_mask); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3665 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
| 3666 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3667 | if (iir & I915_USER_INTERRUPT) |
| 3668 | notify_ring(dev, &dev_priv->ring[RCS]); |
| 3669 | if (iir & I915_BSD_USER_INTERRUPT) |
| 3670 | notify_ring(dev, &dev_priv->ring[VCS]); |
| 3671 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3672 | for_each_pipe(pipe) { |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 3673 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
Ville Syrjälä | 90a72f8 | 2013-02-19 23:16:44 +0200 | [diff] [blame] | 3674 | i915_handle_vblank(dev, pipe, pipe, iir)) |
| 3675 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3676 | |
| 3677 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
| 3678 | blc_event = true; |
Daniel Vetter | 4356d58 | 2013-10-16 22:55:55 +0200 | [diff] [blame] | 3679 | |
| 3680 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
Daniel Vetter | 277de95 | 2013-10-18 16:37:07 +0200 | [diff] [blame] | 3681 | i9xx_pipe_crc_irq_handler(dev, pipe); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3682 | } |
| 3683 | |
| 3684 | |
| 3685 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
| 3686 | intel_opregion_asle_intr(dev); |
| 3687 | |
Daniel Vetter | 515ac2b | 2012-12-01 13:53:44 +0100 | [diff] [blame] | 3688 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
| 3689 | gmbus_irq_handler(dev); |
| 3690 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3691 | /* With MSI, interrupts are only generated when iir |
| 3692 | * transitions from zero to nonzero. If another bit got |
| 3693 | * set while we were handling the existing iir bits, then |
| 3694 | * we would never get another interrupt. |
| 3695 | * |
| 3696 | * This is fine on non-MSI as well, as if we hit this path |
| 3697 | * we avoid exiting the interrupt handler only to generate |
| 3698 | * another one. |
| 3699 | * |
| 3700 | * Note that for MSI this could cause a stray interrupt report |
| 3701 | * if an interrupt landed in the time between writing IIR and |
| 3702 | * the posting read. This should be rare enough to never |
| 3703 | * trigger the 99% of 100,000 interrupts test for disabling |
| 3704 | * stray interrupts. |
| 3705 | */ |
| 3706 | iir = new_iir; |
| 3707 | } |
| 3708 | |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 3709 | i915_update_dri1_breadcrumb(dev); |
Chris Wilson | 2c8ba29 | 2012-04-24 22:59:46 +0100 | [diff] [blame] | 3710 | |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3711 | return ret; |
| 3712 | } |
| 3713 | |
| 3714 | static void i965_irq_uninstall(struct drm_device * dev) |
| 3715 | { |
| 3716 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 3717 | int pipe; |
| 3718 | |
| 3719 | if (!dev_priv) |
| 3720 | return; |
| 3721 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3722 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
| 3723 | |
Chris Wilson | adca473 | 2012-05-11 18:01:31 +0100 | [diff] [blame] | 3724 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 3725 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3726 | |
| 3727 | I915_WRITE(HWSTAM, 0xffffffff); |
| 3728 | for_each_pipe(pipe) |
| 3729 | I915_WRITE(PIPESTAT(pipe), 0); |
| 3730 | I915_WRITE(IMR, 0xffffffff); |
| 3731 | I915_WRITE(IER, 0x0); |
| 3732 | |
| 3733 | for_each_pipe(pipe) |
| 3734 | I915_WRITE(PIPESTAT(pipe), |
| 3735 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); |
| 3736 | I915_WRITE(IIR, I915_READ(IIR)); |
| 3737 | } |
| 3738 | |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3739 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
| 3740 | { |
| 3741 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; |
| 3742 | struct drm_device *dev = dev_priv->dev; |
| 3743 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3744 | unsigned long irqflags; |
| 3745 | int i; |
| 3746 | |
| 3747 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3748 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { |
| 3749 | struct drm_connector *connector; |
| 3750 | |
| 3751 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) |
| 3752 | continue; |
| 3753 | |
| 3754 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3755 | |
| 3756 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3757 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3758 | |
| 3759 | if (intel_connector->encoder->hpd_pin == i) { |
| 3760 | if (connector->polled != intel_connector->polled) |
| 3761 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", |
| 3762 | drm_get_connector_name(connector)); |
| 3763 | connector->polled = intel_connector->polled; |
| 3764 | if (!connector->polled) |
| 3765 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3766 | } |
| 3767 | } |
| 3768 | } |
| 3769 | if (dev_priv->display.hpd_irq_setup) |
| 3770 | dev_priv->display.hpd_irq_setup(dev); |
| 3771 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3772 | } |
| 3773 | |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3774 | void intel_irq_init(struct drm_device *dev) |
| 3775 | { |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3776 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3777 | |
| 3778 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3779 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3780 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 3781 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
Chris Wilson | 8b2e326 | 2012-04-24 22:59:41 +0100 | [diff] [blame] | 3782 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 3783 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
| 3784 | i915_hangcheck_elapsed, |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3785 | (unsigned long) dev); |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 3786 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
| 3787 | (unsigned long) dev_priv); |
Daniel Vetter | 61bac78 | 2012-12-01 21:03:21 +0100 | [diff] [blame] | 3788 | |
Tomas Janousek | 97a19a2 | 2012-12-08 13:48:13 +0100 | [diff] [blame] | 3789 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 3790 | |
Ville Syrjälä | 4cdb83e | 2013-10-11 21:52:44 +0300 | [diff] [blame] | 3791 | if (IS_GEN2(dev)) { |
| 3792 | dev->max_vblank_count = 0; |
| 3793 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; |
| 3794 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3795 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
| 3796 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; |
Ville Syrjälä | 391f75e | 2013-09-25 19:55:26 +0300 | [diff] [blame] | 3797 | } else { |
| 3798 | dev->driver->get_vblank_counter = i915_get_vblank_counter; |
| 3799 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3800 | } |
| 3801 | |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 3802 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
Keith Packard | c3613de | 2011-08-12 17:05:54 -0700 | [diff] [blame] | 3803 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
Ville Syrjälä | c2baf4b | 2013-09-23 14:48:50 +0300 | [diff] [blame] | 3804 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
| 3805 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3806 | |
Jesse Barnes | 7e231dbe | 2012-03-28 13:39:38 -0700 | [diff] [blame] | 3807 | if (IS_VALLEYVIEW(dev)) { |
| 3808 | dev->driver->irq_handler = valleyview_irq_handler; |
| 3809 | dev->driver->irq_preinstall = valleyview_irq_preinstall; |
| 3810 | dev->driver->irq_postinstall = valleyview_irq_postinstall; |
| 3811 | dev->driver->irq_uninstall = valleyview_irq_uninstall; |
| 3812 | dev->driver->enable_vblank = valleyview_enable_vblank; |
| 3813 | dev->driver->disable_vblank = valleyview_disable_vblank; |
Egbert Eich | fa00abe | 2013-02-25 12:06:48 -0500 | [diff] [blame] | 3814 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 3815 | } else if (IS_GEN8(dev)) { |
| 3816 | dev->driver->irq_handler = gen8_irq_handler; |
| 3817 | dev->driver->irq_preinstall = gen8_irq_preinstall; |
| 3818 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
| 3819 | dev->driver->irq_uninstall = gen8_irq_uninstall; |
| 3820 | dev->driver->enable_vblank = gen8_enable_vblank; |
| 3821 | dev->driver->disable_vblank = gen8_disable_vblank; |
| 3822 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3823 | } else if (HAS_PCH_SPLIT(dev)) { |
| 3824 | dev->driver->irq_handler = ironlake_irq_handler; |
| 3825 | dev->driver->irq_preinstall = ironlake_irq_preinstall; |
| 3826 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
| 3827 | dev->driver->irq_uninstall = ironlake_irq_uninstall; |
| 3828 | dev->driver->enable_vblank = ironlake_enable_vblank; |
| 3829 | dev->driver->disable_vblank = ironlake_disable_vblank; |
Daniel Vetter | 82a28bc | 2013-03-27 15:55:01 +0100 | [diff] [blame] | 3830 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3831 | } else { |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3832 | if (INTEL_INFO(dev)->gen == 2) { |
| 3833 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
| 3834 | dev->driver->irq_postinstall = i8xx_irq_postinstall; |
| 3835 | dev->driver->irq_handler = i8xx_irq_handler; |
| 3836 | dev->driver->irq_uninstall = i8xx_irq_uninstall; |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3837 | } else if (INTEL_INFO(dev)->gen == 3) { |
| 3838 | dev->driver->irq_preinstall = i915_irq_preinstall; |
| 3839 | dev->driver->irq_postinstall = i915_irq_postinstall; |
| 3840 | dev->driver->irq_uninstall = i915_irq_uninstall; |
| 3841 | dev->driver->irq_handler = i915_irq_handler; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3842 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3843 | } else { |
Chris Wilson | a266c7d | 2012-04-24 22:59:44 +0100 | [diff] [blame] | 3844 | dev->driver->irq_preinstall = i965_irq_preinstall; |
| 3845 | dev->driver->irq_postinstall = i965_irq_postinstall; |
| 3846 | dev->driver->irq_uninstall = i965_irq_uninstall; |
| 3847 | dev->driver->irq_handler = i965_irq_handler; |
Egbert Eich | bac56d5 | 2013-02-25 12:06:51 -0500 | [diff] [blame] | 3848 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
Chris Wilson | c2798b1 | 2012-04-22 21:13:57 +0100 | [diff] [blame] | 3849 | } |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 3850 | dev->driver->enable_vblank = i915_enable_vblank; |
| 3851 | dev->driver->disable_vblank = i915_disable_vblank; |
| 3852 | } |
| 3853 | } |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3854 | |
| 3855 | void intel_hpd_init(struct drm_device *dev) |
| 3856 | { |
| 3857 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3858 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 3859 | struct drm_connector *connector; |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3860 | unsigned long irqflags; |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3861 | int i; |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3862 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 3863 | for (i = 1; i < HPD_NUM_PINS; i++) { |
| 3864 | dev_priv->hpd_stats[i].hpd_cnt = 0; |
| 3865 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; |
| 3866 | } |
| 3867 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 3868 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3869 | connector->polled = intel_connector->polled; |
| 3870 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) |
| 3871 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 3872 | } |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3873 | |
| 3874 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
| 3875 | * just to make the assert_spin_locked checks happy. */ |
| 3876 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3877 | if (dev_priv->display.hpd_irq_setup) |
| 3878 | dev_priv->display.hpd_irq_setup(dev); |
Daniel Vetter | b5ea2d5 | 2013-06-27 17:52:15 +0200 | [diff] [blame] | 3879 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 3880 | } |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 3881 | |
| 3882 | /* Disable interrupts so we can allow Package C8+. */ |
| 3883 | void hsw_pc8_disable_interrupts(struct drm_device *dev) |
| 3884 | { |
| 3885 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3886 | unsigned long irqflags; |
| 3887 | |
| 3888 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3889 | |
| 3890 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); |
| 3891 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); |
| 3892 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); |
| 3893 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); |
| 3894 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); |
| 3895 | |
| 3896 | ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB); |
| 3897 | ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT); |
| 3898 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
| 3899 | snb_disable_pm_irq(dev_priv, 0xffffffff); |
| 3900 | |
| 3901 | dev_priv->pc8.irqs_disabled = true; |
| 3902 | |
| 3903 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3904 | } |
| 3905 | |
| 3906 | /* Restore interrupts so we can recover from Package C8+. */ |
| 3907 | void hsw_pc8_restore_interrupts(struct drm_device *dev) |
| 3908 | { |
| 3909 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3910 | unsigned long irqflags; |
| 3911 | uint32_t val, expected; |
| 3912 | |
| 3913 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 3914 | |
| 3915 | val = I915_READ(DEIMR); |
| 3916 | expected = ~DE_PCH_EVENT_IVB; |
| 3917 | WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected); |
| 3918 | |
| 3919 | val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT; |
| 3920 | expected = ~SDE_HOTPLUG_MASK_CPT; |
| 3921 | WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n", |
| 3922 | val, expected); |
| 3923 | |
| 3924 | val = I915_READ(GTIMR); |
| 3925 | expected = 0xffffffff; |
| 3926 | WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected); |
| 3927 | |
| 3928 | val = I915_READ(GEN6_PMIMR); |
| 3929 | expected = 0xffffffff; |
| 3930 | WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val, |
| 3931 | expected); |
| 3932 | |
| 3933 | dev_priv->pc8.irqs_disabled = false; |
| 3934 | |
| 3935 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); |
| 3936 | ibx_enable_display_interrupt(dev_priv, |
| 3937 | ~dev_priv->pc8.regsave.sdeimr & |
| 3938 | ~SDE_HOTPLUG_MASK_CPT); |
| 3939 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); |
| 3940 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); |
| 3941 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); |
| 3942 | |
| 3943 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 3944 | } |