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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000072#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010073
Dave Airliec2142712009-09-22 08:50:10 +100074#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075#include "radeon_mode.h"
76#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020077
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020089extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100091extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020092extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040093extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040094extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -050095extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -040096extern int radeon_msi;
Christian König3368ff02012-05-02 15:11:21 +020097extern int radeon_lockup_timeout;
Samuel Lia0a53aa2013-04-08 17:25:47 -040098extern int radeon_fastfb;
Alex Deucherda321c82013-04-12 13:55:22 -040099extern int radeon_dpm;
Alex Deucher1294d4a2013-07-16 15:58:50 -0400100extern int radeon_aspm;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000101extern int radeon_runtime_pm;
Alex Deucher363eb0b2014-01-08 17:55:08 -0500102extern int radeon_hard_reset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
Jerome Glissebb635562012-05-09 15:34:46 +0200108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100110/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glissebb635562012-05-09 15:34:46 +0200111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200115
Jerome Glissebb635562012-05-09 15:34:46 +0200116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
Alex Deucher1b370782011-11-17 20:13:28 -0500118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
Christian Königd93f7932013-05-23 12:10:04 +0200121#define RADEON_RING_TYPE_GFX_INDEX 0
Alex Deucher1b370782011-11-17 20:13:28 -0500122
123/* cayman has 2 compute CP rings */
Christian Königd93f7932013-05-23 12:10:04 +0200124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
Alex Deucher1b370782011-11-17 20:13:28 -0500126
Alex Deucher4d756582012-09-27 15:08:35 -0400127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
Alex Deucherf60cbd12012-12-04 15:27:33 -0500129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
Alex Deucher4d756582012-09-27 15:08:35 -0400131
Christian Königf2ba57b2013-04-08 12:41:29 +0200132/* R600+ */
Christian Königd93f7932013-05-23 12:10:04 +0200133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
Christian Königf2ba57b2013-04-08 12:41:29 +0200141
Christian König1c61eae2014-02-18 01:50:22 -0700142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200144
Christian König8f534922014-02-18 11:37:20 +0100145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
147
Jerome Glisse721604a2012-01-05 22:11:05 -0500148/* hardcode those limit for now */
Christian Königca19f212012-09-11 16:09:59 +0200149#define RADEON_VA_IB_OFFSET (1 << 20)
Jerome Glissebb635562012-05-09 15:34:46 +0200150#define RADEON_VA_RESERVED_SIZE (8 << 20)
151#define RADEON_IB_VM_MAX_SIZE (64 << 10)
Jerome Glisse721604a2012-01-05 22:11:05 -0500152
Alex Deucher1a0041b2013-10-02 13:01:36 -0400153/* hard reset data */
154#define RADEON_ASIC_RESET_DATA 0x39d5e86b
155
Alex Deucherec46c762013-01-03 12:07:30 -0500156/* reset flags */
157#define RADEON_RESET_GFX (1 << 0)
158#define RADEON_RESET_COMPUTE (1 << 1)
159#define RADEON_RESET_DMA (1 << 2)
Alex Deucher9ff07442013-01-18 12:18:17 -0500160#define RADEON_RESET_CP (1 << 3)
161#define RADEON_RESET_GRBM (1 << 4)
162#define RADEON_RESET_DMA1 (1 << 5)
163#define RADEON_RESET_RLC (1 << 6)
164#define RADEON_RESET_SEM (1 << 7)
165#define RADEON_RESET_IH (1 << 8)
166#define RADEON_RESET_VMC (1 << 9)
167#define RADEON_RESET_MC (1 << 10)
168#define RADEON_RESET_DISPLAY (1 << 11)
Alex Deucherec46c762013-01-03 12:07:30 -0500169
Alex Deucher22c775c2013-07-23 09:41:05 -0400170/* CG block flags */
171#define RADEON_CG_BLOCK_GFX (1 << 0)
172#define RADEON_CG_BLOCK_MC (1 << 1)
173#define RADEON_CG_BLOCK_SDMA (1 << 2)
174#define RADEON_CG_BLOCK_UVD (1 << 3)
175#define RADEON_CG_BLOCK_VCE (1 << 4)
176#define RADEON_CG_BLOCK_HDP (1 << 5)
Alex Deuchere16866e2013-08-08 19:34:07 -0400177#define RADEON_CG_BLOCK_BIF (1 << 6)
Alex Deucher22c775c2013-07-23 09:41:05 -0400178
Alex Deucher64d8a722013-08-08 16:31:25 -0400179/* CG flags */
180#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
197
198/* PG flags */
Alex Deucher2b19d172013-09-04 16:58:29 -0400199#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
Alex Deucher64d8a722013-08-08 16:31:25 -0400200#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202#define RADEON_PG_SUPPORT_UVD (1 << 3)
203#define RADEON_PG_SUPPORT_VCE (1 << 4)
204#define RADEON_PG_SUPPORT_CP (1 << 5)
205#define RADEON_PG_SUPPORT_GDS (1 << 6)
206#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207#define RADEON_PG_SUPPORT_SDMA (1 << 8)
208#define RADEON_PG_SUPPORT_ACP (1 << 9)
209#define RADEON_PG_SUPPORT_SAMU (1 << 10)
210
Alex Deucher9e05fa12013-01-24 10:06:33 -0500211/* max cursor sizes (in pixels) */
212#define CURSOR_WIDTH 64
213#define CURSOR_HEIGHT 64
214
215#define CIK_CURSOR_WIDTH 128
216#define CIK_CURSOR_HEIGHT 128
217
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218/*
219 * Errata workarounds.
220 */
221enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
225};
226
227
228struct radeon_device;
229
230
231/*
232 * BIOS.
233 */
234bool radeon_get_bios(struct radeon_device *rdev);
235
Jerome Glisse9fc04b52012-01-23 11:52:15 -0500236/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000237 * Dummy page
238 */
239struct radeon_dummy_page {
240 struct page *page;
241 dma_addr_t addr;
242};
243int radeon_dummy_page_init(struct radeon_device *rdev);
244void radeon_dummy_page_fini(struct radeon_device *rdev);
245
246
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247/*
248 * Clocks
249 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200250struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500253 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254 struct radeon_pll spll;
255 struct radeon_pll mpll;
256 /* 10 Khz units */
257 uint32_t default_mclk;
258 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500259 uint32_t default_dispclk;
Alex Deucher4489cd622013-03-22 15:59:10 -0400260 uint32_t current_dispclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500261 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400262 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200263};
264
Rafał Miłecki74338742009-11-03 00:53:02 +0100265/*
266 * Power management
267 */
268int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -0500269int radeon_pm_late_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500270void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100271void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400272void radeon_pm_suspend(struct radeon_device *rdev);
273void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500274void radeon_combios_get_power_modes(struct radeon_device *rdev);
275void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Christian König7062ab62013-04-08 12:41:31 +0200276int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 u8 clock_type,
278 u32 clock,
279 bool strobe_mode,
280 struct atom_clock_dividers *dividers);
Alex Deuchereaa778a2013-02-13 16:38:25 -0500281int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_mpll_param *mpll_param);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400285void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400286int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400293int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
Alex Deucherbeb79f42013-02-19 17:14:43 -0500295int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
296 u16 *voltage,
297 u16 leakage_idx);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400298int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
299 u16 *leakage_id);
300int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400304int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 u8 voltage_type,
306 u16 nominal_voltage,
307 u16 *true_voltage);
308int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312int radeon_atom_get_voltage_table(struct radeon_device *rdev,
Alex Deucher65171942013-02-13 17:29:54 -0500313 u8 voltage_type, u8 voltage_mode,
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400314 struct atom_voltage_table *voltage_table);
Alex Deucher58653ab2013-02-13 17:04:59 -0500315bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
Alex Deucherae5b0ab2013-06-24 10:50:34 -0400317void radeon_atom_update_memory_dll(struct radeon_device *rdev,
318 u32 mem_clock);
319void radeon_atom_set_ac_timing(struct radeon_device *rdev,
320 u32 mem_clock);
321int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
322 u8 module_index,
323 struct atom_mc_reg_table *reg_table);
324int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
Alex Deucherf8920342010-06-30 12:02:03 -0400331void rs690_pm_info(struct radeon_device *rdev);
Jerome Glisse285484e2011-12-16 17:03:42 -0500332extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000335
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200336/*
337 * Fences.
338 */
339struct radeon_fence_driver {
340 uint32_t scratch_reg;
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000341 uint64_t gpu_addr;
342 volatile uint32_t *cpu_addr;
Christian König68e250b2012-05-10 15:57:31 +0200343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
Jerome Glissebb635562012-05-09 15:34:46 +0200345 atomic64_t last_seq;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100346 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200347};
348
349struct radeon_fence {
350 struct radeon_device *rdev;
351 struct kref kref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200352 /* protected by radeon_fence.lock */
Jerome Glissebb635562012-05-09 15:34:46 +0200353 uint64_t seq;
Alex Deucher74652802011-08-25 13:39:48 -0400354 /* RB, DMA, etc. */
Jerome Glissebb635562012-05-09 15:34:46 +0200355 unsigned ring;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200356};
357
Jerome Glisse30eb77f2011-11-20 20:45:34 +0000358int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359int radeon_fence_driver_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360void radeon_fence_driver_fini(struct radeon_device *rdev);
Jerome Glisse76903b92012-12-17 10:29:06 -0500361void radeon_fence_driver_force_completion(struct radeon_device *rdev);
Christian König876dc9f2012-05-08 14:24:01 +0200362int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Alex Deucher74652802011-08-25 13:39:48 -0400363void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364bool radeon_fence_signaled(struct radeon_fence *fence);
365int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Christian König37615522014-02-18 15:58:31 +0100366int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
Jerome Glisse0085c9502012-05-09 15:34:55 +0200368int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
370 bool intr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200371struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372void radeon_fence_unref(struct radeon_fence **fence);
Jerome Glisse3b7a2b22012-05-09 15:34:47 +0200373unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Christian König68e250b2012-05-10 15:57:31 +0200374bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
378{
379 if (!a) {
380 return b;
381 }
382
383 if (!b) {
384 return a;
385 }
386
387 BUG_ON(a->ring != b->ring);
388
389 if (a->seq > b->seq) {
390 return a;
391 } else {
392 return b;
393 }
394}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200395
Christian Königee60e292012-08-09 16:21:08 +0200396static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
398{
399 if (!a) {
400 return false;
401 }
402
403 if (!b) {
404 return true;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 return a->seq < b->seq;
410}
411
Dave Airliee024e112009-06-24 09:48:08 +1000412/*
413 * Tiling registers
414 */
415struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100416 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000417};
418
419#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200420
421/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100422 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200423 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100424struct radeon_mman {
425 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000426 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100427 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100428 bool mem_global_referenced;
429 bool initialized;
Christian König2014b562013-12-18 21:07:39 +0100430
431#if defined(CONFIG_DEBUG_FS)
432 struct dentry *vram;
Christian Königdd66d202013-12-18 21:07:40 +0100433 struct dentry *gtt;
Christian König2014b562013-12-18 21:07:39 +0100434#endif
Jerome Glisse4c788672009-11-20 14:29:23 +0100435};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200436
Jerome Glisse721604a2012-01-05 22:11:05 -0500437/* bo virtual address in a specific vm */
438struct radeon_bo_va {
Christian Könige971bd52012-09-11 16:10:04 +0200439 /* protected by bo being reserved */
Jerome Glisse721604a2012-01-05 22:11:05 -0500440 struct list_head bo_list;
Jerome Glisse721604a2012-01-05 22:11:05 -0500441 uint64_t soffset;
442 uint64_t eoffset;
443 uint32_t flags;
444 bool valid;
Christian Könige971bd52012-09-11 16:10:04 +0200445 unsigned ref_count;
446
447 /* protected by vm mutex */
448 struct list_head vm_list;
449
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
Jerome Glisse721604a2012-01-05 22:11:05 -0500453};
454
Jerome Glisse4c788672009-11-20 14:29:23 +0100455struct radeon_bo {
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
Marek Olšákbda72d52014-03-02 00:56:17 +0100459 u32 initial_domain;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100460 u32 placements[3];
461 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
464 unsigned pin_count;
465 void *kptr;
466 u32 tiling_flags;
467 u32 pitch;
468 int surface_reg;
Jerome Glisse721604a2012-01-05 22:11:05 -0500469 /* list of all virtual address to which this bo
470 * is associated to
471 */
472 struct list_head va;
Jerome Glisse4c788672009-11-20 14:29:23 +0100473 /* Constant after initialization */
474 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100475 struct drm_gem_object gem_base;
Dave Airlie63bc6202012-05-31 13:52:53 +0100476
Jerome Glisse409851f2013-04-25 22:29:27 -0400477 struct ttm_bo_kmap_obj dma_buf_vmap;
478 pid_t pid;
Jerome Glisse4c788672009-11-20 14:29:23 +0100479};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100480#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100481
Jerome Glisse409851f2013-04-25 22:29:27 -0400482int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
Jerome Glisseb15ba512011-11-15 11:48:34 -0500484/* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507struct radeon_sa_manager {
Christian Königbfb38d32012-07-11 21:07:57 +0200508 wait_queue_head_t wq;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500509 struct radeon_bo *bo;
Christian Königc3b7fe82012-05-09 15:34:56 +0200510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
Alex Deucher6c4f9782013-07-12 15:46:09 -0400517 uint32_t align;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500518};
519
520struct radeon_sa_bo;
521
522/* sub-allocation buffer */
523struct radeon_sa_bo {
Christian Königc3b7fe82012-05-09 15:34:56 +0200524 struct list_head olist;
525 struct list_head flist;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500526 struct radeon_sa_manager *manager;
Christian Könige6661a92012-05-09 15:34:52 +0200527 unsigned soffset;
528 unsigned eoffset;
Christian König557017a2012-05-09 15:34:54 +0200529 struct radeon_fence *fence;
Jerome Glisseb15ba512011-11-15 11:48:34 -0500530};
531
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200532/*
533 * GEM objects.
534 */
535struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100536 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200537 struct list_head objects;
538};
539
540int radeon_gem_init(struct radeon_device *rdev);
541void radeon_gem_fini(struct radeon_device *rdev);
542int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200546
Dave Airlieff72145b2011-02-07 12:16:14 +1000547int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200553
554/*
Jerome Glissec1341e52011-12-21 12:13:47 -0500555 * Semaphores.
556 */
Jerome Glissec1341e52011-12-21 12:13:47 -0500557struct radeon_semaphore {
Jerome Glissea8c05942012-05-09 15:34:57 +0200558 struct radeon_sa_bo *sa_bo;
559 signed waiters;
Jerome Glissec1341e52011-12-21 12:13:47 -0500560 uint64_t gpu_addr;
Christian König1654b812013-11-12 12:58:05 +0100561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
Jerome Glissec1341e52011-12-21 12:13:47 -0500562};
563
Jerome Glissec1341e52011-12-21 12:13:47 -0500564int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
Christian König1654b812013-11-12 12:58:05 +0100566bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500567 struct radeon_semaphore *semaphore);
Christian König1654b812013-11-12 12:58:05 +0100568bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
Jerome Glissec1341e52011-12-21 12:13:47 -0500569 struct radeon_semaphore *semaphore);
Christian König1654b812013-11-12 12:58:05 +0100570void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
Christian König8f676c42012-05-02 15:11:18 +0200572int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
Christian König1654b812013-11-12 12:58:05 +0100574 int waiting_ring);
Jerome Glissec1341e52011-12-21 12:13:47 -0500575void radeon_semaphore_free(struct radeon_device *rdev,
Christian König220907d2012-05-10 16:46:43 +0200576 struct radeon_semaphore **semaphore,
Jerome Glissea8c05942012-05-09 15:34:57 +0200577 struct radeon_fence *fence);
Jerome Glissec1341e52011-12-21 12:13:47 -0500578
579/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200580 * GART structures, functions & helpers
581 */
582struct radeon_mc;
583
Matt Turnera77f1712009-10-14 00:34:41 -0400584#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000585#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400586#define RADEON_GPU_PAGE_SHIFT 12
Jerome Glisse721604a2012-01-05 22:11:05 -0500587#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
Matt Turnera77f1712009-10-14 00:34:41 -0400588
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200589struct radeon_gart {
590 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400591 struct radeon_bo *robj;
592 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
595 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200596 struct page **pages;
597 dma_addr_t *pages_addr;
598 bool ready;
599};
600
601int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602void radeon_gart_table_ram_free(struct radeon_device *rdev);
603int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400605int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200607int radeon_gart_init(struct radeon_device *rdev);
608void radeon_gart_fini(struct radeon_device *rdev);
609void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
610 int pages);
611int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400614void radeon_gart_restore(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200615
616
617/*
618 * GPU MC structures, functions & helpers
619 */
620struct radeon_mc {
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000626 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000627 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000628 u64 gtt_size;
629 u64 gtt_start;
630 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000631 u64 vram_start;
632 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200633 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000634 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200635 int vram_mtrr;
636 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000637 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400638 u64 gtt_base_align;
Alex Deucher9ed8b1f2013-04-08 11:13:01 -0400639 u64 mc_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200640};
641
Alex Deucher06b64762010-01-05 11:27:29 -0500642bool radeon_combios_sideport_present(struct radeon_device *rdev);
643bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200644
645/*
646 * GPU scratch registers structures, functions & helpers
647 */
648struct radeon_scratch {
649 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400650 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200651 bool free[32];
652 uint32_t reg[32];
653};
654
655int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
657
Alex Deucher75efdee2013-03-04 12:47:46 -0500658/*
659 * GPU doorbell structures, functions & helpers
660 */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500661#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
662
Alex Deucher75efdee2013-03-04 12:47:46 -0500663struct radeon_doorbell {
Alex Deucher75efdee2013-03-04 12:47:46 -0500664 /* doorbell mmio */
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500665 resource_size_t base;
666 resource_size_t size;
667 u32 __iomem *ptr;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
Alex Deucher75efdee2013-03-04 12:47:46 -0500670};
671
672int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200674
675/*
676 * IRQS.
677 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500678
679struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
682 int crtc_id;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
686 u64 new_crtc_base;
687};
688
689struct r500_irq_stat_regs {
690 u32 disp_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400691 u32 hdmi0_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500692};
693
694struct r600_irq_stat_regs {
695 u32 disp_int;
696 u32 disp_int_cont;
697 u32 disp_int_cont2;
698 u32 d1grph_int;
699 u32 d2grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400700 u32 hdmi0_status;
701 u32 hdmi1_status;
Alex Deucher6f34be52010-11-21 10:59:01 -0500702};
703
704struct evergreen_irq_stat_regs {
705 u32 disp_int;
706 u32 disp_int_cont;
707 u32 disp_int_cont2;
708 u32 disp_int_cont3;
709 u32 disp_int_cont4;
710 u32 disp_int_cont5;
711 u32 d1grph_int;
712 u32 d2grph_int;
713 u32 d3grph_int;
714 u32 d4grph_int;
715 u32 d5grph_int;
716 u32 d6grph_int;
Alex Deucherf122c612012-03-30 08:59:57 -0400717 u32 afmt_status1;
718 u32 afmt_status2;
719 u32 afmt_status3;
720 u32 afmt_status4;
721 u32 afmt_status5;
722 u32 afmt_status6;
Alex Deucher6f34be52010-11-21 10:59:01 -0500723};
724
Alex Deuchera59781b2012-11-09 10:45:57 -0500725struct cik_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 disp_int_cont3;
730 u32 disp_int_cont4;
731 u32 disp_int_cont5;
732 u32 disp_int_cont6;
Christian Königf5d636d2014-04-23 20:46:06 +0200733 u32 d1grph_int;
734 u32 d2grph_int;
735 u32 d3grph_int;
736 u32 d4grph_int;
737 u32 d5grph_int;
738 u32 d6grph_int;
Alex Deuchera59781b2012-11-09 10:45:57 -0500739};
740
Alex Deucher6f34be52010-11-21 10:59:01 -0500741union radeon_irq_stat_regs {
742 struct r500_irq_stat_regs r500;
743 struct r600_irq_stat_regs r600;
744 struct evergreen_irq_stat_regs evergreen;
Alex Deuchera59781b2012-11-09 10:45:57 -0500745 struct cik_irq_stat_regs cik;
Alex Deucher6f34be52010-11-21 10:59:01 -0500746};
747
Alex Deucherbe0949f2014-04-08 11:28:54 -0400748#define RADEON_MAX_HPD_PINS 7
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400749#define RADEON_MAX_CRTCS 6
Alex Deucherb5306022013-07-31 16:51:33 -0400750#define RADEON_MAX_AFMT_BLOCKS 7
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400751
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200752struct radeon_irq {
Christian Koenigfb982572012-05-17 01:33:30 +0200753 bool installed;
754 spinlock_t lock;
Christian Koenig736fc372012-05-17 19:52:00 +0200755 atomic_t ring_int[RADEON_NUM_RINGS];
Christian Koenigfb982572012-05-17 01:33:30 +0200756 bool crtc_vblank_int[RADEON_MAX_CRTCS];
Christian Koenig736fc372012-05-17 19:52:00 +0200757 atomic_t pflip[RADEON_MAX_CRTCS];
Christian Koenigfb982572012-05-17 01:33:30 +0200758 wait_queue_head_t vblank_queue;
759 bool hpd[RADEON_MAX_HPD_PINS];
Christian Koenigfb982572012-05-17 01:33:30 +0200760 bool afmt[RADEON_MAX_AFMT_BLOCKS];
761 union radeon_irq_stat_regs stat_regs;
Alex Deucher4a6369e2013-04-12 14:04:10 -0400762 bool dpm_thermal;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200763};
764
765int radeon_irq_kms_init(struct radeon_device *rdev);
766void radeon_irq_kms_fini(struct radeon_device *rdev);
Alex Deucher1b370782011-11-17 20:13:28 -0500767void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
768void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
Alex Deucher6f34be52010-11-21 10:59:01 -0500769void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
770void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Christian Koenigfb982572012-05-17 01:33:30 +0200771void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
772void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200775
776/*
Christian Könige32eb502011-10-23 12:56:27 +0200777 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200778 */
Alex Deucher74652802011-08-25 13:39:48 -0400779
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200780struct radeon_ib {
Jerome Glisse68470ae2012-05-09 15:35:00 +0200781 struct radeon_sa_bo *sa_bo;
782 uint32_t length_dw;
783 uint64_t gpu_addr;
784 uint32_t *ptr;
Christian König876dc9f2012-05-08 14:24:01 +0200785 int ring;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200786 struct radeon_fence *fence;
Christian König4bf3dd92012-08-06 18:57:44 +0200787 struct radeon_vm *vm;
Jerome Glisse68470ae2012-05-09 15:35:00 +0200788 bool is_const_ib;
789 struct radeon_semaphore *semaphore;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200790};
791
Christian Könige32eb502011-10-23 12:56:27 +0200792struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100793 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200794 volatile uint32_t *ring;
Christian König5596a9d2011-10-13 12:48:45 +0200795 unsigned rptr_offs;
Christian König45df6802012-07-06 16:22:55 +0200796 unsigned rptr_save_reg;
Alex Deucher89d35802012-07-17 14:02:31 -0400797 u64 next_rptr_gpu_addr;
798 volatile u32 *next_rptr_cpu_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200799 unsigned wptr;
800 unsigned wptr_old;
801 unsigned ring_size;
802 unsigned ring_free_dw;
803 int count_dw;
Christian Königaee4aa72014-02-18 15:24:06 +0100804 atomic_t last_rptr;
805 atomic64_t last_activity;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200806 uint64_t gpu_addr;
807 uint32_t align_mask;
808 uint32_t ptr_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200809 bool ready;
Alex Deucher78c55602011-11-17 14:25:56 -0500810 u32 nop;
Alex Deucher8b25ed32012-07-17 14:02:30 -0400811 u32 idx;
Jerome Glisse5f0839c2013-01-11 15:19:43 -0500812 u64 last_semaphore_signal_addr;
813 u64 last_semaphore_wait_addr;
Alex Deucher963e81f2013-06-26 17:37:11 -0400814 /* for CIK queues */
815 u32 me;
816 u32 pipe;
817 u32 queue;
818 struct radeon_bo *mqd_obj;
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -0500819 u32 doorbell_index;
Alex Deucher963e81f2013-06-26 17:37:11 -0400820 unsigned wptr_offs;
821};
822
823struct radeon_mec {
824 struct radeon_bo *hpd_eop_obj;
825 u64 hpd_eop_gpu_addr;
826 u32 num_pipe;
827 u32 num_mec;
828 u32 num_queue;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200829};
830
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500831/*
Jerome Glisse721604a2012-01-05 22:11:05 -0500832 * VM
833 */
Christian Königee60e292012-08-09 16:21:08 +0200834
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200835/* maximum number of VMIDs */
Christian Königee60e292012-08-09 16:21:08 +0200836#define RADEON_NUM_VM 16
837
Dmitry Cherkasovfa87e622012-09-17 19:36:19 +0200838/* defines number of bits in page table versus page directory,
839 * a page is 4KB so we have 12 bits offset, 9 bits in the page
840 * table and the remaining 19 bits are in the page directory */
841#define RADEON_VM_BLOCK_SIZE 9
842
843/* number of entries in page table */
844#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
845
Alex Deucher1c011032013-07-12 15:56:02 -0400846/* PTBs (Page Table Blocks) need to be aligned to 32K */
847#define RADEON_VM_PTB_ALIGN_SIZE 32768
848#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
849#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
850
Christian König24c16432013-10-30 11:51:09 -0400851#define R600_PTE_VALID (1 << 0)
852#define R600_PTE_SYSTEM (1 << 1)
853#define R600_PTE_SNOOPED (1 << 2)
854#define R600_PTE_READABLE (1 << 5)
855#define R600_PTE_WRITEABLE (1 << 6)
856
Christian König6d2f2942014-02-20 13:42:17 +0100857struct radeon_vm_pt {
858 struct radeon_bo *bo;
859 uint64_t addr;
860};
861
Jerome Glisse721604a2012-01-05 22:11:05 -0500862struct radeon_vm {
Jerome Glisse721604a2012-01-05 22:11:05 -0500863 struct list_head va;
Christian Königee60e292012-08-09 16:21:08 +0200864 unsigned id;
Christian König90a51a32012-10-09 13:31:17 +0200865
866 /* contains the page directory */
Christian König6d2f2942014-02-20 13:42:17 +0100867 struct radeon_bo *page_directory;
Christian König90a51a32012-10-09 13:31:17 +0200868 uint64_t pd_gpu_addr;
Christian König6d2f2942014-02-20 13:42:17 +0100869 unsigned max_pde_used;
Christian König90a51a32012-10-09 13:31:17 +0200870
871 /* array of page tables, one for each page directory entry */
Christian König6d2f2942014-02-20 13:42:17 +0100872 struct radeon_vm_pt *page_tables;
Christian König90a51a32012-10-09 13:31:17 +0200873
Jerome Glisse721604a2012-01-05 22:11:05 -0500874 struct mutex mutex;
875 /* last fence for cs using this vm */
876 struct radeon_fence *fence;
Christian König9b40e5d2012-08-08 12:22:43 +0200877 /* last flush or NULL if we still need to flush */
878 struct radeon_fence *last_flush;
Christian König593b2632014-01-23 14:24:15 +0100879 /* last use of vmid */
880 struct radeon_fence *last_id_use;
Jerome Glisse721604a2012-01-05 22:11:05 -0500881};
882
Jerome Glisse721604a2012-01-05 22:11:05 -0500883struct radeon_vm_manager {
Christian Königee60e292012-08-09 16:21:08 +0200884 struct radeon_fence *active[RADEON_NUM_VM];
Jerome Glisse721604a2012-01-05 22:11:05 -0500885 uint32_t max_pfn;
Jerome Glisse721604a2012-01-05 22:11:05 -0500886 /* number of VMIDs */
887 unsigned nvm;
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
Alex Deucher67e915e2012-01-06 09:38:15 -0500890 /* is vm enabled? */
891 bool enabled;
Jerome Glisse721604a2012-01-05 22:11:05 -0500892};
893
894/*
895 * file private structure
896 */
897struct radeon_fpriv {
898 struct radeon_vm vm;
899};
900
901/*
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500902 * R6xx+ IH ring
903 */
904struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100905 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500906 volatile uint32_t *ring;
907 unsigned rptr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500908 unsigned ring_size;
909 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500910 uint32_t ptr_mask;
Christian Koenigc20dc362012-05-16 21:45:24 +0200911 atomic_t lock;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500912 bool enabled;
913};
914
Alex Deucher347e7592012-03-20 17:18:21 -0400915/*
Alex Deucher2948f5e2013-04-12 13:52:52 -0400916 * RLC stuff
Alex Deucher347e7592012-03-20 17:18:21 -0400917 */
Alex Deucher2948f5e2013-04-12 13:52:52 -0400918#include "clearstate_defs.h"
919
920struct radeon_rlc {
Alex Deucher347e7592012-03-20 17:18:21 -0400921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400924 volatile uint32_t *sr_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400925 const u32 *reg_list;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400926 u32 reg_list_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
Alex Deucher2948f5e2013-04-12 13:52:52 -0400930 volatile uint32_t *cs_ptr;
Alex Deucher1fd11772013-04-17 17:53:50 -0400931 const struct cs_section_def *cs_data;
Alex Deucher22c775c2013-07-23 09:41:05 -0400932 u32 clear_state_size;
933 /* for cp tables */
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
937 u32 cp_table_size;
Alex Deucher347e7592012-03-20 17:18:21 -0400938};
939
Jerome Glisse69e130a2011-12-21 12:13:46 -0500940int radeon_ib_get(struct radeon_device *rdev, int ring,
Christian König4bf3dd92012-08-06 18:57:44 +0200941 struct radeon_ib *ib, struct radeon_vm *vm,
942 unsigned size);
Jerome Glissef2e39222012-05-09 15:35:02 +0200943void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
Christian König4ef72562012-07-13 13:06:00 +0200944int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200946int radeon_ib_pool_init(struct radeon_device *rdev);
947void radeon_ib_pool_fini(struct radeon_device *rdev);
Christian König7bd560e2012-05-02 15:11:12 +0200948int radeon_ib_ring_tests(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200949/* Ring access between begin & end cannot sleep */
Alex Deucher89d35802012-07-17 14:02:31 -0400950bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200952void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königd6999bc2012-05-09 15:34:45 +0200957void radeon_ring_undo(struct radeon_ring *ring);
Christian Könige32eb502011-10-23 12:56:27 +0200958void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königff212f22014-02-18 14:52:33 +0100960void radeon_ring_lockup_update(struct radeon_device *rdev,
961 struct radeon_ring *ring);
Christian König069211e2012-05-02 15:11:20 +0200962bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König55d7c222012-07-09 11:52:44 +0200963unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
964 uint32_t **data);
965int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
Christian Könige32eb502011-10-23 12:56:27 +0200967int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Alex Deucherea31bf62013-12-09 19:44:30 -0500968 unsigned rptr_offs, u32 nop);
Christian Könige32eb502011-10-23 12:56:27 +0200969void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200970
971
Alex Deucher4d756582012-09-27 15:08:35 -0400972/* r600 async dma */
973void r600_dma_stop(struct radeon_device *rdev);
974int r600_dma_resume(struct radeon_device *rdev);
975void r600_dma_fini(struct radeon_device *rdev);
976
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500977void cayman_dma_stop(struct radeon_device *rdev);
978int cayman_dma_resume(struct radeon_device *rdev);
979void cayman_dma_fini(struct radeon_device *rdev);
980
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200981/*
982 * CS.
983 */
984struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100986 struct radeon_bo *robj;
Christian Königdf0af442014-03-03 12:38:08 +0100987 struct ttm_validate_buffer tv;
988 uint64_t gpu_offset;
989 unsigned domain;
990 unsigned alt_domain;
991 uint32_t tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200992 uint32_t handle;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200993};
994
995struct radeon_cs_chunk {
996 uint32_t chunk_id;
997 uint32_t length_dw;
998 uint32_t *kdata;
Jerome Glisse721604a2012-01-05 22:11:05 -0500999 void __user *user_ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001000};
1001
1002struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +01001003 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001004 struct radeon_device *rdev;
1005 struct drm_file *filp;
1006 /* chunks */
1007 unsigned nchunks;
1008 struct radeon_cs_chunk *chunks;
1009 uint64_t *chunks_array;
1010 /* IB */
1011 unsigned idx;
1012 /* relocations */
1013 unsigned nrelocs;
1014 struct radeon_cs_reloc *relocs;
1015 struct radeon_cs_reloc **relocs_ptr;
Christian Königdf0af442014-03-03 12:38:08 +01001016 struct radeon_cs_reloc *vm_bos;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001017 struct list_head validated;
Alex Deuchercf4ccd02011-11-18 10:19:47 -05001018 unsigned dma_reloc_idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001019 /* indices of various chunks */
1020 int chunk_ib_idx;
1021 int chunk_relocs_idx;
Jerome Glisse721604a2012-01-05 22:11:05 -05001022 int chunk_flags_idx;
Alex Deucherdfcf5f32012-03-20 17:18:14 -04001023 int chunk_const_ib_idx;
Jerome Glissef2e39222012-05-09 15:35:02 +02001024 struct radeon_ib ib;
1025 struct radeon_ib const_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001026 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001027 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +02001028 int parser_error;
Jerome Glisse721604a2012-01-05 22:11:05 -05001029 u32 cs_flags;
1030 u32 ring;
1031 s32 priority;
Maarten Lankhorstecff6652013-06-27 13:48:17 +02001032 struct ww_acquire_ctx ticket;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001033};
1034
Maarten Lankhorst28a326c2013-10-09 14:36:57 +02001035static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1036{
1037 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1038
1039 if (ibc->kdata)
1040 return ibc->kdata[idx];
1041 return p->ib.ptr[idx];
1042}
1043
Dave Airlie513bcb42009-09-23 16:56:27 +10001044
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001045struct radeon_cs_packet {
1046 unsigned idx;
1047 unsigned type;
1048 unsigned reg;
1049 unsigned opcode;
1050 int count;
1051 unsigned one_reg_wr;
1052};
1053
1054typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1056 unsigned idx, unsigned reg);
1057typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1058 struct radeon_cs_packet *pkt);
1059
1060
1061/*
1062 * AGP
1063 */
1064int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +10001065void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +02001066void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001067void radeon_agp_fini(struct radeon_device *rdev);
1068
1069
1070/*
1071 * Writeback
1072 */
1073struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +01001074 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001075 volatile uint32_t *wb;
1076 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -04001077 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -04001078 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001079};
1080
Alex Deucher724c80e2010-08-27 18:25:25 -04001081#define RADEON_WB_SCRATCH_OFFSET 0
Alex Deucher89d35802012-07-17 14:02:31 -04001082#define RADEON_WB_RING0_NEXT_RPTR 256
Alex Deucher724c80e2010-08-27 18:25:25 -04001083#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -05001084#define RADEON_WB_CP1_RPTR_OFFSET 1280
1085#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher4d756582012-09-27 15:08:35 -04001086#define R600_WB_DMA_RPTR_OFFSET 1792
Alex Deucher724c80e2010-08-27 18:25:25 -04001087#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherf60cbd12012-12-04 15:27:33 -05001088#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
Alex Deucherd0f8a852010-09-04 05:04:34 -04001089#define R600_WB_EVENT_OFFSET 3072
Alex Deucher963e81f2013-06-26 17:37:11 -04001090#define CIK_WB_CP1_WPTR_OFFSET 3328
1091#define CIK_WB_CP2_WPTR_OFFSET 3584
Alex Deucher724c80e2010-08-27 18:25:25 -04001092
Jerome Glissec93bb852009-07-13 21:04:08 +02001093/**
1094 * struct radeon_pm - power management datas
1095 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1096 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1097 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1098 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1099 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1100 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1101 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1102 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1103 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001104 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +02001105 * @needed_bandwidth: current bandwidth needs
1106 *
1107 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001108 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +02001109 * Equation between gpu/memory clock and available bandwidth is hw dependent
1110 * (type of memory, bus size, efficiency, ...)
1111 */
Alex Deucherce8f5372010-05-07 15:10:16 -04001112
1113enum radeon_pm_method {
1114 PM_METHOD_PROFILE,
1115 PM_METHOD_DYNPM,
Alex Deucherda321c82013-04-12 13:55:22 -04001116 PM_METHOD_DPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +01001117};
Alex Deucherce8f5372010-05-07 15:10:16 -04001118
1119enum radeon_dynpm_state {
1120 DYNPM_STATE_DISABLED,
1121 DYNPM_STATE_MINIMUM,
1122 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +00001123 DYNPM_STATE_ACTIVE,
1124 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -04001125};
1126enum radeon_dynpm_action {
1127 DYNPM_ACTION_NONE,
1128 DYNPM_ACTION_MINIMUM,
1129 DYNPM_ACTION_DOWNCLOCK,
1130 DYNPM_ACTION_UPCLOCK,
1131 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +01001132};
Alex Deucher56278a82009-12-28 13:58:44 -05001133
1134enum radeon_voltage_type {
1135 VOLTAGE_NONE = 0,
1136 VOLTAGE_GPIO,
1137 VOLTAGE_VDDC,
1138 VOLTAGE_SW
1139};
1140
Alex Deucher0ec0e742009-12-23 13:21:58 -05001141enum radeon_pm_state_type {
Alex Deucherda321c82013-04-12 13:55:22 -04001142 /* not used for dpm */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001143 POWER_STATE_TYPE_DEFAULT,
1144 POWER_STATE_TYPE_POWERSAVE,
Alex Deucherda321c82013-04-12 13:55:22 -04001145 /* user selectable states */
Alex Deucher0ec0e742009-12-23 13:21:58 -05001146 POWER_STATE_TYPE_BATTERY,
1147 POWER_STATE_TYPE_BALANCED,
1148 POWER_STATE_TYPE_PERFORMANCE,
Alex Deucherda321c82013-04-12 13:55:22 -04001149 /* internal states */
1150 POWER_STATE_TYPE_INTERNAL_UVD,
1151 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1152 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1153 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1154 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1155 POWER_STATE_TYPE_INTERNAL_BOOT,
1156 POWER_STATE_TYPE_INTERNAL_THERMAL,
1157 POWER_STATE_TYPE_INTERNAL_ACPI,
1158 POWER_STATE_TYPE_INTERNAL_ULV,
Alex Deucheredcaa5b2013-07-05 11:48:31 -04001159 POWER_STATE_TYPE_INTERNAL_3DPERF,
Alex Deucher0ec0e742009-12-23 13:21:58 -05001160};
1161
Alex Deucherce8f5372010-05-07 15:10:16 -04001162enum radeon_pm_profile_type {
1163 PM_PROFILE_DEFAULT,
1164 PM_PROFILE_AUTO,
1165 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -04001166 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -04001167 PM_PROFILE_HIGH,
1168};
1169
1170#define PM_PROFILE_DEFAULT_IDX 0
1171#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -04001172#define PM_PROFILE_MID_SH_IDX 2
1173#define PM_PROFILE_HIGH_SH_IDX 3
1174#define PM_PROFILE_LOW_MH_IDX 4
1175#define PM_PROFILE_MID_MH_IDX 5
1176#define PM_PROFILE_HIGH_MH_IDX 6
1177#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -04001178
1179struct radeon_pm_profile {
1180 int dpms_off_ps_idx;
1181 int dpms_on_ps_idx;
1182 int dpms_off_cm_idx;
1183 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -05001184};
1185
Alex Deucher21a81222010-07-02 12:58:16 -04001186enum radeon_int_thermal_type {
1187 THERMAL_TYPE_NONE,
Alex Deucherda321c82013-04-12 13:55:22 -04001188 THERMAL_TYPE_EXTERNAL,
1189 THERMAL_TYPE_EXTERNAL_GPIO,
Alex Deucher21a81222010-07-02 12:58:16 -04001190 THERMAL_TYPE_RV6XX,
1191 THERMAL_TYPE_RV770,
Alex Deucherda321c82013-04-12 13:55:22 -04001192 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
Alex Deucher21a81222010-07-02 12:58:16 -04001193 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -05001194 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -05001195 THERMAL_TYPE_NI,
Alex Deucher14607d02012-03-20 17:18:09 -04001196 THERMAL_TYPE_SI,
Alex Deucherda321c82013-04-12 13:55:22 -04001197 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
Alex Deucher51150202012-12-18 22:07:14 -05001198 THERMAL_TYPE_CI,
Alex Deucher16fbe002013-04-22 21:41:26 -04001199 THERMAL_TYPE_KV,
Alex Deucher21a81222010-07-02 12:58:16 -04001200};
1201
Alex Deucher56278a82009-12-28 13:58:44 -05001202struct radeon_voltage {
1203 enum radeon_voltage_type type;
1204 /* gpio voltage */
1205 struct radeon_gpio_rec gpio;
1206 u32 delay; /* delay in usec from voltage drop to sclk change */
1207 bool active_high; /* voltage drop is active when bit is high */
1208 /* VDDC voltage */
1209 u8 vddc_id; /* index into vddc voltage table */
1210 u8 vddci_id; /* index into vddci voltage table */
1211 bool vddci_enabled;
1212 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -04001213 u16 voltage;
1214 /* evergreen+ vddci */
1215 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -05001216};
1217
Alex Deucherd7311172010-05-03 01:13:14 -04001218/* clock mode flags */
1219#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1220
Alex Deucher56278a82009-12-28 13:58:44 -05001221struct radeon_pm_clock_info {
1222 /* memory clock */
1223 u32 mclk;
1224 /* engine clock */
1225 u32 sclk;
1226 /* voltage info */
1227 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -04001228 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -05001229 u32 flags;
1230};
1231
Alex Deuchera48b9b42010-04-22 14:03:55 -04001232/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -04001233#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -04001234
Alex Deucher56278a82009-12-28 13:58:44 -05001235struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -05001236 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -04001237 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -05001238 /* number of valid clock modes in this power state */
1239 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -05001240 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001241 /* standardized state flags */
1242 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -04001243 u32 misc; /* vbios specific flags */
1244 u32 misc2; /* vbios specific flags */
1245 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -05001246};
1247
Rafał Miłecki27459322010-02-11 22:16:36 +00001248/*
1249 * Some modes are overclocked by very low value, accept them
1250 */
1251#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1252
Alex Deucher2e9d4c02013-04-12 13:58:03 -04001253enum radeon_dpm_auto_throttle_src {
1254 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1255 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1256};
1257
1258enum radeon_dpm_event_src {
1259 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1260 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1261 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1262 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1263 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1264};
1265
Alex Deucher58bd2a82013-09-04 16:13:56 -04001266#define RADEON_MAX_VCE_LEVELS 6
1267
Alex Deucherb62d6282013-08-20 20:29:05 -04001268enum radeon_vce_level {
1269 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1270 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1271 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1272 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1273 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1274 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1275};
1276
Alex Deucherda321c82013-04-12 13:55:22 -04001277struct radeon_ps {
1278 u32 caps; /* vbios flags */
1279 u32 class; /* vbios flags */
1280 u32 class2; /* vbios flags */
1281 /* UVD clocks */
1282 u32 vclk;
1283 u32 dclk;
Alex Deucherc4453e62013-05-15 15:53:57 -04001284 /* VCE clocks */
1285 u32 evclk;
1286 u32 ecclk;
Alex Deucherb62d6282013-08-20 20:29:05 -04001287 bool vce_active;
1288 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001289 /* asic priv */
1290 void *ps_priv;
1291};
1292
1293struct radeon_dpm_thermal {
1294 /* thermal interrupt work */
1295 struct work_struct work;
1296 /* low temperature threshold */
1297 int min_temp;
1298 /* high temperature threshold */
1299 int max_temp;
1300 /* was interrupt low to high or high to low */
1301 bool high_to_low;
1302};
1303
Alex Deucherd22b7e42012-11-29 19:27:56 -05001304enum radeon_clk_action
1305{
1306 RADEON_SCLK_UP = 1,
1307 RADEON_SCLK_DOWN
1308};
1309
1310struct radeon_blacklist_clocks
1311{
1312 u32 sclk;
1313 u32 mclk;
1314 enum radeon_clk_action action;
1315};
1316
Alex Deucher61b7d602012-11-14 19:57:42 -05001317struct radeon_clock_and_voltage_limits {
1318 u32 sclk;
1319 u32 mclk;
Alex Deuchercdf6e802013-10-23 16:13:42 -04001320 u16 vddc;
1321 u16 vddci;
Alex Deucher61b7d602012-11-14 19:57:42 -05001322};
1323
1324struct radeon_clock_array {
1325 u32 count;
1326 u32 *values;
1327};
1328
1329struct radeon_clock_voltage_dependency_entry {
1330 u32 clk;
1331 u16 v;
1332};
1333
1334struct radeon_clock_voltage_dependency_table {
1335 u32 count;
1336 struct radeon_clock_voltage_dependency_entry *entries;
1337};
1338
Alex Deucheref976ec2013-05-06 11:31:04 -04001339union radeon_cac_leakage_entry {
1340 struct {
1341 u16 vddc;
1342 u32 leakage;
1343 };
1344 struct {
1345 u16 vddc1;
1346 u16 vddc2;
1347 u16 vddc3;
1348 };
Alex Deucher61b7d602012-11-14 19:57:42 -05001349};
1350
1351struct radeon_cac_leakage_table {
1352 u32 count;
Alex Deucheref976ec2013-05-06 11:31:04 -04001353 union radeon_cac_leakage_entry *entries;
Alex Deucher61b7d602012-11-14 19:57:42 -05001354};
1355
Alex Deucher929ee7a2013-03-20 12:30:25 -04001356struct radeon_phase_shedding_limits_entry {
1357 u16 voltage;
1358 u32 sclk;
1359 u32 mclk;
1360};
1361
1362struct radeon_phase_shedding_limits_table {
1363 u32 count;
1364 struct radeon_phase_shedding_limits_entry *entries;
1365};
1366
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001367struct radeon_uvd_clock_voltage_dependency_entry {
1368 u32 vclk;
1369 u32 dclk;
1370 u16 v;
1371};
1372
1373struct radeon_uvd_clock_voltage_dependency_table {
1374 u8 count;
1375 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1376};
1377
Alex Deucherd29f0132013-05-09 16:37:28 -04001378struct radeon_vce_clock_voltage_dependency_entry {
1379 u32 ecclk;
1380 u32 evclk;
1381 u16 v;
1382};
1383
1384struct radeon_vce_clock_voltage_dependency_table {
1385 u8 count;
1386 struct radeon_vce_clock_voltage_dependency_entry *entries;
1387};
1388
Alex Deuchera5cb3182013-03-20 13:00:18 -04001389struct radeon_ppm_table {
1390 u8 ppm_design;
1391 u16 cpu_core_number;
1392 u32 platform_tdp;
1393 u32 small_ac_platform_tdp;
1394 u32 platform_tdc;
1395 u32 small_ac_platform_tdc;
1396 u32 apu_tdp;
1397 u32 dgpu_tdp;
1398 u32 dgpu_ulv_power;
1399 u32 tj_max;
1400};
1401
Alex Deucher58cb7632013-05-06 12:15:33 -04001402struct radeon_cac_tdp_table {
1403 u16 tdp;
1404 u16 configurable_tdp;
1405 u16 tdc;
1406 u16 battery_power_limit;
1407 u16 small_power_limit;
1408 u16 low_cac_leakage;
1409 u16 high_cac_leakage;
1410 u16 maximum_power_delivery_limit;
1411};
1412
Alex Deucher61b7d602012-11-14 19:57:42 -05001413struct radeon_dpm_dynamic_state {
1414 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1415 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1416 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
Alex Deucherdd621a22013-05-06 14:37:56 -04001417 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
Alex Deucher4489cd622013-03-22 15:59:10 -04001418 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
Alex Deucher84a9d9e2013-04-19 19:11:37 -04001419 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
Alex Deucherd29f0132013-05-09 16:37:28 -04001420 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
Alex Deucher94a914f2013-05-09 16:42:33 -04001421 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1422 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001423 struct radeon_clock_array valid_sclk_values;
1424 struct radeon_clock_array valid_mclk_values;
1425 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1426 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1427 u32 mclk_sclk_ratio;
1428 u32 sclk_mclk_delta;
1429 u16 vddc_vddci_delta;
1430 u16 min_vddc_for_pcie_gen2;
1431 struct radeon_cac_leakage_table cac_leakage_table;
Alex Deucher929ee7a2013-03-20 12:30:25 -04001432 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
Alex Deuchera5cb3182013-03-20 13:00:18 -04001433 struct radeon_ppm_table *ppm_table;
Alex Deucher58cb7632013-05-06 12:15:33 -04001434 struct radeon_cac_tdp_table *cac_tdp_table;
Alex Deucher61b7d602012-11-14 19:57:42 -05001435};
1436
1437struct radeon_dpm_fan {
1438 u16 t_min;
1439 u16 t_med;
1440 u16 t_high;
1441 u16 pwm_min;
1442 u16 pwm_med;
1443 u16 pwm_high;
1444 u8 t_hyst;
1445 u32 cycle_delay;
1446 u16 t_max;
1447 bool ucode_fan_control;
1448};
1449
Alex Deucher32ce4652013-03-18 17:03:01 -04001450enum radeon_pcie_gen {
1451 RADEON_PCIE_GEN1 = 0,
1452 RADEON_PCIE_GEN2 = 1,
1453 RADEON_PCIE_GEN3 = 2,
1454 RADEON_PCIE_GEN_INVALID = 0xffff
1455};
1456
Alex Deucher70d01a52013-07-02 18:38:02 -04001457enum radeon_dpm_forced_level {
1458 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1459 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1460 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1461};
1462
Alex Deucher58bd2a82013-09-04 16:13:56 -04001463struct radeon_vce_state {
1464 /* vce clocks */
1465 u32 evclk;
1466 u32 ecclk;
1467 /* gpu clocks */
1468 u32 sclk;
1469 u32 mclk;
1470 u8 clk_idx;
1471 u8 pstate;
1472};
1473
Alex Deucherda321c82013-04-12 13:55:22 -04001474struct radeon_dpm {
1475 struct radeon_ps *ps;
1476 /* number of valid power states */
1477 int num_ps;
1478 /* current power state that is active */
1479 struct radeon_ps *current_ps;
1480 /* requested power state */
1481 struct radeon_ps *requested_ps;
1482 /* boot up power state */
1483 struct radeon_ps *boot_ps;
1484 /* default uvd power state */
1485 struct radeon_ps *uvd_ps;
Alex Deucher58bd2a82013-09-04 16:13:56 -04001486 /* vce requirements */
1487 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1488 enum radeon_vce_level vce_level;
Alex Deucherda321c82013-04-12 13:55:22 -04001489 enum radeon_pm_state_type state;
1490 enum radeon_pm_state_type user_state;
1491 u32 platform_caps;
1492 u32 voltage_response_time;
1493 u32 backbias_response_time;
1494 void *priv;
1495 u32 new_active_crtcs;
1496 int new_active_crtc_count;
1497 u32 current_active_crtcs;
1498 int current_active_crtc_count;
Alex Deucher61b7d602012-11-14 19:57:42 -05001499 struct radeon_dpm_dynamic_state dyn_state;
1500 struct radeon_dpm_fan fan;
1501 u32 tdp_limit;
1502 u32 near_tdp_limit;
Alex Deuchera9e61412013-06-25 17:56:16 -04001503 u32 near_tdp_limit_adjusted;
Alex Deucher61b7d602012-11-14 19:57:42 -05001504 u32 sq_ramping_threshold;
1505 u32 cac_leakage;
1506 u16 tdp_od_limit;
1507 u32 tdp_adjustment;
1508 u16 load_line_slope;
1509 bool power_control;
Alex Deucher5ca302f2012-11-30 10:56:57 -05001510 bool ac_power;
Alex Deucherda321c82013-04-12 13:55:22 -04001511 /* special states active */
1512 bool thermal_active;
Alex Deucher8a227552013-06-21 15:12:57 -04001513 bool uvd_active;
Alex Deucherb62d6282013-08-20 20:29:05 -04001514 bool vce_active;
Alex Deucherda321c82013-04-12 13:55:22 -04001515 /* thermal handling */
1516 struct radeon_dpm_thermal thermal;
Alex Deucher70d01a52013-07-02 18:38:02 -04001517 /* forced levels */
1518 enum radeon_dpm_forced_level forced_level;
Alex Deucherce3537d2013-07-24 12:12:49 -04001519 /* track UVD streams */
1520 unsigned sd;
1521 unsigned hd;
Alex Deucherda321c82013-04-12 13:55:22 -04001522};
1523
Alex Deucherce3537d2013-07-24 12:12:49 -04001524void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001525void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001526
Jerome Glissec93bb852009-07-13 21:04:08 +02001527struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +01001528 struct mutex mutex;
Christian Königdb7fce32012-05-11 14:57:18 +02001529 /* write locked while reprogramming mclk */
1530 struct rw_semaphore mclk_lock;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001531 u32 active_crtcs;
1532 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +01001533 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +01001534 bool vblank_sync;
Jerome Glissec93bb852009-07-13 21:04:08 +02001535 fixed20_12 max_bandwidth;
1536 fixed20_12 igp_sideport_mclk;
1537 fixed20_12 igp_system_mclk;
1538 fixed20_12 igp_ht_link_clk;
1539 fixed20_12 igp_ht_link_width;
1540 fixed20_12 k8_bandwidth;
1541 fixed20_12 sideport_bandwidth;
1542 fixed20_12 ht_bandwidth;
1543 fixed20_12 core_bandwidth;
1544 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -04001545 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +02001546 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -05001547 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -05001548 /* number of valid power states */
1549 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -04001550 int current_power_state_index;
1551 int current_clock_mode_index;
1552 int requested_power_state_index;
1553 int requested_clock_mode_index;
1554 int default_power_state_index;
1555 u32 current_sclk;
1556 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001557 u16 current_vddc;
1558 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -05001559 u32 default_sclk;
1560 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -04001561 u16 default_vddc;
1562 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -05001563 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -04001564 /* selected pm method */
1565 enum radeon_pm_method pm_method;
1566 /* dynpm power management */
1567 struct delayed_work dynpm_idle_work;
1568 enum radeon_dynpm_state dynpm_state;
1569 enum radeon_dynpm_action dynpm_planned_action;
1570 unsigned long dynpm_action_timeout;
1571 bool dynpm_can_upclock;
1572 bool dynpm_can_downclock;
1573 /* profile-based power management */
1574 enum radeon_pm_profile_type profile;
1575 int profile_index;
1576 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -04001577 /* internal thermal controller on rv6xx+ */
1578 enum radeon_int_thermal_type int_thermal_type;
1579 struct device *int_hwmon_dev;
Alex Deucherda321c82013-04-12 13:55:22 -04001580 /* dpm */
1581 bool dpm_enabled;
1582 struct radeon_dpm dpm;
Jerome Glissec93bb852009-07-13 21:04:08 +02001583};
1584
Alex Deuchera4c9e2e2011-11-04 10:09:41 -04001585int radeon_pm_get_type_index(struct radeon_device *rdev,
1586 enum radeon_pm_state_type ps_type,
1587 int instance);
Christian Königf2ba57b2013-04-08 12:41:29 +02001588/*
1589 * UVD
1590 */
1591#define RADEON_MAX_UVD_HANDLES 10
1592#define RADEON_UVD_STACK_SIZE (1024*1024)
1593#define RADEON_UVD_HEAP_SIZE (1024*1024)
1594
1595struct radeon_uvd {
1596 struct radeon_bo *vcpu_bo;
1597 void *cpu_addr;
1598 uint64_t gpu_addr;
Christian König9cc2e0e2013-07-12 10:18:09 -04001599 void *saved_bo;
Christian Königf2ba57b2013-04-08 12:41:29 +02001600 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1601 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
Alex Deucher85a129c2013-08-05 12:41:20 -04001602 unsigned img_size[RADEON_MAX_UVD_HANDLES];
Christian König55b51c82013-04-18 15:25:59 +02001603 struct delayed_work idle_work;
Christian Königf2ba57b2013-04-08 12:41:29 +02001604};
1605
1606int radeon_uvd_init(struct radeon_device *rdev);
1607void radeon_uvd_fini(struct radeon_device *rdev);
1608int radeon_uvd_suspend(struct radeon_device *rdev);
1609int radeon_uvd_resume(struct radeon_device *rdev);
1610int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1611 uint32_t handle, struct radeon_fence **fence);
1612int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1613 uint32_t handle, struct radeon_fence **fence);
1614void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1615void radeon_uvd_free_handles(struct radeon_device *rdev,
1616 struct drm_file *filp);
1617int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
Christian König55b51c82013-04-18 15:25:59 +02001618void radeon_uvd_note_usage(struct radeon_device *rdev);
Christian Königfacd1122013-04-29 11:55:02 +02001619int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1620 unsigned vclk, unsigned dclk,
1621 unsigned vco_min, unsigned vco_max,
1622 unsigned fb_factor, unsigned fb_mask,
1623 unsigned pd_min, unsigned pd_max,
1624 unsigned pd_even,
1625 unsigned *optimal_fb_div,
1626 unsigned *optimal_vclk_div,
1627 unsigned *optimal_dclk_div);
1628int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1629 unsigned cg_upll_func_cntl);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001630
Christian Königd93f7932013-05-23 12:10:04 +02001631/*
1632 * VCE
1633 */
1634#define RADEON_MAX_VCE_HANDLES 16
1635#define RADEON_VCE_STACK_SIZE (1024*1024)
1636#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1637
1638struct radeon_vce {
1639 struct radeon_bo *vcpu_bo;
Christian Königd93f7932013-05-23 12:10:04 +02001640 uint64_t gpu_addr;
Christian König98ccc292014-01-23 09:50:49 -07001641 unsigned fw_version;
1642 unsigned fb_version;
Christian Königd93f7932013-05-23 12:10:04 +02001643 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1644 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
Leo Liu2fc57032014-05-05 15:42:18 -04001645 unsigned img_size[RADEON_MAX_VCE_HANDLES];
Alex Deucher03afe6f2013-08-23 11:56:26 -04001646 struct delayed_work idle_work;
Christian Königd93f7932013-05-23 12:10:04 +02001647};
1648
1649int radeon_vce_init(struct radeon_device *rdev);
1650void radeon_vce_fini(struct radeon_device *rdev);
1651int radeon_vce_suspend(struct radeon_device *rdev);
1652int radeon_vce_resume(struct radeon_device *rdev);
1653int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1656 uint32_t handle, struct radeon_fence **fence);
1657void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
Alex Deucher03afe6f2013-08-23 11:56:26 -04001658void radeon_vce_note_usage(struct radeon_device *rdev);
Leo Liu2fc57032014-05-05 15:42:18 -04001659int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
Christian Königd93f7932013-05-23 12:10:04 +02001660int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1661bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1662 struct radeon_ring *ring,
1663 struct radeon_semaphore *semaphore,
1664 bool emit_wait);
1665void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1666void radeon_vce_fence_emit(struct radeon_device *rdev,
1667 struct radeon_fence *fence);
1668int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1669int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1670
Alex Deucherb5306022013-07-31 16:51:33 -04001671struct r600_audio_pin {
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001672 int channels;
1673 int rate;
1674 int bits_per_sample;
1675 u8 status_bits;
1676 u8 category_code;
Alex Deucherb5306022013-07-31 16:51:33 -04001677 u32 offset;
1678 bool connected;
1679 u32 id;
1680};
1681
1682struct r600_audio {
1683 bool enabled;
1684 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1685 int num_pins;
Rafał Miłeckia92553a2012-04-28 23:35:20 +02001686};
1687
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001688/*
1689 * Benchmarking
1690 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -04001691void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001692
1693
1694/*
Michel Dänzerecc0b322009-07-21 11:23:57 +02001695 * Testing
1696 */
1697void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +02001698void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +02001699 struct radeon_ring *cpA,
1700 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +02001701void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +02001702
1703
1704/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001705 * Debugfs
1706 */
Christian König4d8bf9a2011-10-24 14:54:54 +02001707struct radeon_debugfs {
1708 struct drm_info_list *files;
1709 unsigned num_files;
1710};
1711
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001712int radeon_debugfs_add_files(struct radeon_device *rdev,
1713 struct drm_info_list *files,
1714 unsigned nfiles);
1715int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001716
Christian König76a0df82013-08-13 11:56:50 +02001717/*
1718 * ASIC ring specific functions.
1719 */
1720struct radeon_asic_ring {
1721 /* ring read/write ptr handling */
1722 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1723 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1724 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1725
1726 /* validating and patching of IBs */
1727 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1728 int (*cs_parse)(struct radeon_cs_parser *p);
1729
1730 /* command emmit functions */
1731 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1732 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +01001733 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König76a0df82013-08-13 11:56:50 +02001734 struct radeon_semaphore *semaphore, bool emit_wait);
1735 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1736
1737 /* testing functions */
1738 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1739 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1740 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1741
1742 /* deprecated */
1743 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1744};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001745
1746/*
1747 * ASIC specific functions.
1748 */
1749struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +02001750 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001751 void (*fini)(struct radeon_device *rdev);
1752 int (*resume)(struct radeon_device *rdev);
1753 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +10001754 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Jerome Glissea2d07b72010-03-09 14:45:11 +00001755 int (*asic_reset)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001756 /* ioctl hw specific callback. Some hw might want to perform special
1757 * operation on specific ioctl. For instance on wait idle some hw
1758 * might want to perform and HDP flush through MMIO as it seems that
1759 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1760 * through ring.
1761 */
1762 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1763 /* check if 3D engine is idle */
1764 bool (*gui_idle)(struct radeon_device *rdev);
1765 /* wait for mc_idle */
1766 int (*mc_wait_for_idle)(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -05001767 /* get the reference clock */
1768 u32 (*get_xclk)(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -05001769 /* get the gpu clock counter */
1770 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
Alex Deucher54e88e02012-02-23 18:10:29 -05001771 /* gart */
Alex Deucherc5b3b852012-02-23 17:53:46 -05001772 struct {
1773 void (*tlb_flush)(struct radeon_device *rdev);
1774 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1775 } gart;
Christian König05b07142012-08-06 20:21:10 +02001776 struct {
1777 int (*init)(struct radeon_device *rdev);
1778 void (*fini)(struct radeon_device *rdev);
Alex Deucher43f12142013-02-01 17:32:42 +01001779 void (*set_page)(struct radeon_device *rdev,
1780 struct radeon_ib *ib,
1781 uint64_t pe,
Christian Königdce34bf2012-09-17 19:36:18 +02001782 uint64_t addr, unsigned count,
1783 uint32_t incr, uint32_t flags);
Christian König05b07142012-08-06 20:21:10 +02001784 } vm;
Alex Deucher54e88e02012-02-23 18:10:29 -05001785 /* ring specific callbacks */
Christian König76a0df82013-08-13 11:56:50 +02001786 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
Alex Deucher54e88e02012-02-23 18:10:29 -05001787 /* irqs */
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001788 struct {
1789 int (*set)(struct radeon_device *rdev);
1790 int (*process)(struct radeon_device *rdev);
1791 } irq;
Alex Deucher54e88e02012-02-23 18:10:29 -05001792 /* displays */
Alex Deucherc79a49c2012-02-23 17:53:47 -05001793 struct {
1794 /* display watermarks */
1795 void (*bandwidth_update)(struct radeon_device *rdev);
1796 /* get frame count */
1797 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1798 /* wait for vblank */
1799 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001800 /* set backlight level */
1801 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -04001802 /* get backlight level */
1803 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -04001804 /* audio callbacks */
1805 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1806 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucherc79a49c2012-02-23 17:53:47 -05001807 } display;
Alex Deucher54e88e02012-02-23 18:10:29 -05001808 /* copy functions for bo handling */
Alex Deucher27cd7762012-02-23 17:53:42 -05001809 struct {
1810 int (*blit)(struct radeon_device *rdev,
1811 uint64_t src_offset,
1812 uint64_t dst_offset,
1813 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001814 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001815 u32 blit_ring_index;
1816 int (*dma)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001820 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001821 u32 dma_ring_index;
1822 /* method used for bo copy */
1823 int (*copy)(struct radeon_device *rdev,
1824 uint64_t src_offset,
1825 uint64_t dst_offset,
1826 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +02001827 struct radeon_fence **fence);
Alex Deucher27cd7762012-02-23 17:53:42 -05001828 /* ring used for bo copies */
1829 u32 copy_ring_index;
1830 } copy;
Alex Deucher54e88e02012-02-23 18:10:29 -05001831 /* surfaces */
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001832 struct {
1833 int (*set_reg)(struct radeon_device *rdev, int reg,
1834 uint32_t tiling_flags, uint32_t pitch,
1835 uint32_t offset, uint32_t obj_size);
1836 void (*clear_reg)(struct radeon_device *rdev, int reg);
1837 } surface;
Alex Deucher54e88e02012-02-23 18:10:29 -05001838 /* hotplug detect */
Alex Deucher901ea572012-02-23 17:53:39 -05001839 struct {
1840 void (*init)(struct radeon_device *rdev);
1841 void (*fini)(struct radeon_device *rdev);
1842 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1843 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1844 } hpd;
Alex Deucherda321c82013-04-12 13:55:22 -04001845 /* static power management */
Alex Deuchera02fa392012-02-23 17:53:41 -05001846 struct {
1847 void (*misc)(struct radeon_device *rdev);
1848 void (*prepare)(struct radeon_device *rdev);
1849 void (*finish)(struct radeon_device *rdev);
1850 void (*init_profile)(struct radeon_device *rdev);
1851 void (*get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher798bcf72012-02-23 17:53:48 -05001852 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1853 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1854 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1855 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1856 int (*get_pcie_lanes)(struct radeon_device *rdev);
1857 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1858 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Alex Deucher73afc702013-04-08 12:41:30 +02001859 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucherb59b7332013-08-20 20:01:18 -04001860 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -04001861 int (*get_temperature)(struct radeon_device *rdev);
Alex Deuchera02fa392012-02-23 17:53:41 -05001862 } pm;
Alex Deucherda321c82013-04-12 13:55:22 -04001863 /* dynamic power management */
1864 struct {
1865 int (*init)(struct radeon_device *rdev);
1866 void (*setup_asic)(struct radeon_device *rdev);
1867 int (*enable)(struct radeon_device *rdev);
Alex Deucher914a8982013-12-19 11:37:22 -05001868 int (*late_enable)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001869 void (*disable)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001870 int (*pre_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001871 int (*set_power_state)(struct radeon_device *rdev);
Alex Deucher84dd1922013-01-16 12:52:04 -05001872 void (*post_set_power_state)(struct radeon_device *rdev);
Alex Deucherda321c82013-04-12 13:55:22 -04001873 void (*display_configuration_changed)(struct radeon_device *rdev);
1874 void (*fini)(struct radeon_device *rdev);
1875 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1876 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1877 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
Alex Deucher1316b792013-06-28 09:28:39 -04001878 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
Alex Deucher70d01a52013-07-02 18:38:02 -04001879 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
Alex Deucher48783062013-07-08 11:35:06 -04001880 bool (*vblank_too_short)(struct radeon_device *rdev);
Alex Deucher9e9d9762013-07-31 18:13:23 -04001881 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
Alex Deucher1c71bda2013-09-09 19:11:52 -04001882 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
Alex Deucherda321c82013-04-12 13:55:22 -04001883 } dpm;
Alex Deucher6f34be52010-11-21 10:59:01 -05001884 /* pageflipping */
Alex Deucher0f9e0062012-02-23 17:53:40 -05001885 struct {
1886 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1887 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1888 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1889 } pflip;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001890};
1891
Jerome Glisse21f9a432009-09-11 15:55:33 +02001892/*
1893 * Asic structures
1894 */
Dave Airlie551ebd82009-09-01 15:25:57 +10001895struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001896 const unsigned *reg_safe_bm;
1897 unsigned reg_safe_bm_size;
1898 u32 hdp_cntl;
Dave Airlie551ebd82009-09-01 15:25:57 +10001899};
1900
Jerome Glisse21f9a432009-09-11 15:55:33 +02001901struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001902 const unsigned *reg_safe_bm;
1903 unsigned reg_safe_bm_size;
1904 u32 resync_scratch;
1905 u32 hdp_cntl;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001906};
1907
1908struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001909 unsigned max_pipes;
1910 unsigned max_tile_pipes;
1911 unsigned max_simds;
1912 unsigned max_backends;
1913 unsigned max_gprs;
1914 unsigned max_threads;
1915 unsigned max_stack_entries;
1916 unsigned max_hw_contexts;
1917 unsigned max_gs_threads;
1918 unsigned sx_max_export_size;
1919 unsigned sx_max_export_pos_size;
1920 unsigned sx_max_export_smx_size;
1921 unsigned sq_num_cf_insts;
1922 unsigned tiling_nbanks;
1923 unsigned tiling_npipes;
1924 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001925 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001926 unsigned backend_map;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001927};
1928
1929struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001930 unsigned max_pipes;
1931 unsigned max_tile_pipes;
1932 unsigned max_simds;
1933 unsigned max_backends;
1934 unsigned max_gprs;
1935 unsigned max_threads;
1936 unsigned max_stack_entries;
1937 unsigned max_hw_contexts;
1938 unsigned max_gs_threads;
1939 unsigned sx_max_export_size;
1940 unsigned sx_max_export_pos_size;
1941 unsigned sx_max_export_smx_size;
1942 unsigned sq_num_cf_insts;
1943 unsigned sx_num_of_sets;
1944 unsigned sc_prim_fifo_size;
1945 unsigned sc_hiz_tile_fifo_size;
1946 unsigned sc_earlyz_tile_fifo_fize;
1947 unsigned tiling_nbanks;
1948 unsigned tiling_npipes;
1949 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001950 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001951 unsigned backend_map;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001952};
1953
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001954struct evergreen_asic {
1955 unsigned num_ses;
1956 unsigned max_pipes;
1957 unsigned max_tile_pipes;
1958 unsigned max_simds;
1959 unsigned max_backends;
1960 unsigned max_gprs;
1961 unsigned max_threads;
1962 unsigned max_stack_entries;
1963 unsigned max_hw_contexts;
1964 unsigned max_gs_threads;
1965 unsigned sx_max_export_size;
1966 unsigned sx_max_export_pos_size;
1967 unsigned sx_max_export_smx_size;
1968 unsigned sq_num_cf_insts;
1969 unsigned sx_num_of_sets;
1970 unsigned sc_prim_fifo_size;
1971 unsigned sc_hiz_tile_fifo_size;
1972 unsigned sc_earlyz_tile_fifo_size;
1973 unsigned tiling_nbanks;
1974 unsigned tiling_npipes;
1975 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001976 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001977 unsigned backend_map;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001978};
1979
Alex Deucherfecf1d02011-03-02 20:07:29 -05001980struct cayman_asic {
1981 unsigned max_shader_engines;
1982 unsigned max_pipes_per_simd;
1983 unsigned max_tile_pipes;
1984 unsigned max_simds_per_se;
1985 unsigned max_backends_per_se;
1986 unsigned max_texture_channel_caches;
1987 unsigned max_gprs;
1988 unsigned max_threads;
1989 unsigned max_gs_threads;
1990 unsigned max_stack_entries;
1991 unsigned sx_num_of_sets;
1992 unsigned sx_max_export_size;
1993 unsigned sx_max_export_pos_size;
1994 unsigned sx_max_export_smx_size;
1995 unsigned max_hw_contexts;
1996 unsigned sq_num_cf_insts;
1997 unsigned sc_prim_fifo_size;
1998 unsigned sc_hiz_tile_fifo_size;
1999 unsigned sc_earlyz_tile_fifo_size;
2000
2001 unsigned num_shader_engines;
2002 unsigned num_shader_pipes_per_simd;
2003 unsigned num_tile_pipes;
2004 unsigned num_simds_per_se;
2005 unsigned num_backends_per_se;
2006 unsigned backend_disable_mask_per_asic;
2007 unsigned backend_map;
2008 unsigned num_texture_channel_caches;
2009 unsigned mem_max_burst_length_bytes;
2010 unsigned mem_row_size_in_kb;
2011 unsigned shader_engine_tile_size;
2012 unsigned num_gpus;
2013 unsigned multi_gpu_tile_size;
2014
2015 unsigned tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002016};
2017
Alex Deucher0a96d722012-03-20 17:18:11 -04002018struct si_asic {
2019 unsigned max_shader_engines;
Alex Deucher0a96d722012-03-20 17:18:11 -04002020 unsigned max_tile_pipes;
Alex Deucher1a8ca752012-06-01 18:58:22 -04002021 unsigned max_cu_per_sh;
2022 unsigned max_sh_per_se;
Alex Deucher0a96d722012-03-20 17:18:11 -04002023 unsigned max_backends_per_se;
2024 unsigned max_texture_channel_caches;
2025 unsigned max_gprs;
2026 unsigned max_gs_threads;
2027 unsigned max_hw_contexts;
2028 unsigned sc_prim_fifo_size_frontend;
2029 unsigned sc_prim_fifo_size_backend;
2030 unsigned sc_hiz_tile_fifo_size;
2031 unsigned sc_earlyz_tile_fifo_size;
2032
Alex Deucher0a96d722012-03-20 17:18:11 -04002033 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002034 unsigned backend_enable_mask;
Alex Deucher0a96d722012-03-20 17:18:11 -04002035 unsigned backend_disable_mask_per_asic;
2036 unsigned backend_map;
2037 unsigned num_texture_channel_caches;
2038 unsigned mem_max_burst_length_bytes;
2039 unsigned mem_row_size_in_kb;
2040 unsigned shader_engine_tile_size;
2041 unsigned num_gpus;
2042 unsigned multi_gpu_tile_size;
2043
2044 unsigned tile_config;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -04002045 uint32_t tile_mode_array[32];
Alex Deucher0a96d722012-03-20 17:18:11 -04002046};
2047
Alex Deucher8cc1a532013-04-09 12:41:24 -04002048struct cik_asic {
2049 unsigned max_shader_engines;
2050 unsigned max_tile_pipes;
2051 unsigned max_cu_per_sh;
2052 unsigned max_sh_per_se;
2053 unsigned max_backends_per_se;
2054 unsigned max_texture_channel_caches;
2055 unsigned max_gprs;
2056 unsigned max_gs_threads;
2057 unsigned max_hw_contexts;
2058 unsigned sc_prim_fifo_size_frontend;
2059 unsigned sc_prim_fifo_size_backend;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_size;
2062
2063 unsigned num_tile_pipes;
Marek Olšák439a1cf2013-12-22 02:18:01 +01002064 unsigned backend_enable_mask;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002065 unsigned backend_disable_mask_per_asic;
2066 unsigned backend_map;
2067 unsigned num_texture_channel_caches;
2068 unsigned mem_max_burst_length_bytes;
2069 unsigned mem_row_size_in_kb;
2070 unsigned shader_engine_tile_size;
2071 unsigned num_gpus;
2072 unsigned multi_gpu_tile_size;
2073
2074 unsigned tile_config;
Alex Deucher39aee492013-04-10 13:41:25 -04002075 uint32_t tile_mode_array[32];
Michel Dänzer32f79a82013-11-18 18:26:00 +09002076 uint32_t macrotile_mode_array[16];
Alex Deucher8cc1a532013-04-09 12:41:24 -04002077};
2078
Jerome Glisse068a1172009-06-17 13:28:30 +02002079union radeon_asic_config {
2080 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10002081 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002082 struct r600_asic r600;
2083 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04002084 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05002085 struct cayman_asic cayman;
Alex Deucher0a96d722012-03-20 17:18:11 -04002086 struct si_asic si;
Alex Deucher8cc1a532013-04-09 12:41:24 -04002087 struct cik_asic cik;
Jerome Glisse068a1172009-06-17 13:28:30 +02002088};
2089
Daniel Vetter0a10c852010-03-11 21:19:14 +00002090/*
2091 * asic initizalization from radeon_asic.c
2092 */
2093void radeon_agp_disable(struct radeon_device *rdev);
2094int radeon_asic_init(struct radeon_device *rdev);
2095
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002096
2097/*
2098 * IOCTL.
2099 */
2100int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *filp);
2102int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *filp);
2104int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
2116int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *filp);
2118int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *filp);
Jerome Glisse721604a2012-01-05 22:11:05 -05002120int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *filp);
Marek Olšákbda72d52014-03-02 00:56:17 +01002122int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002124int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10002125int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *filp);
2127int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002129
Alex Deucher16cdf042011-10-28 10:30:02 -04002130/* VRAM scratch page for HDP bug, default vram page */
2131struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002132 struct radeon_bo *robj;
2133 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04002134 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04002135};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002136
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002137/*
2138 * ACPI
2139 */
2140struct radeon_atif_notification_cfg {
2141 bool enabled;
2142 int command_code;
2143};
2144
2145struct radeon_atif_notifications {
2146 bool display_switch;
2147 bool expansion_mode_change;
2148 bool thermal_state;
2149 bool forced_power_state;
2150 bool system_power_state;
2151 bool display_conf_change;
2152 bool px_gfx_switch;
2153 bool brightness_change;
2154 bool dgpu_display_event;
2155};
2156
2157struct radeon_atif_functions {
2158 bool system_params;
2159 bool sbios_requests;
2160 bool select_active_disp;
2161 bool lid_state;
2162 bool get_tv_standard;
2163 bool set_tv_standard;
2164 bool get_panel_expansion_mode;
2165 bool set_panel_expansion_mode;
2166 bool temperature_change;
2167 bool graphics_device_types;
2168};
2169
2170struct radeon_atif {
2171 struct radeon_atif_notifications notifications;
2172 struct radeon_atif_functions functions;
2173 struct radeon_atif_notification_cfg notification_cfg;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002174 struct radeon_encoder *encoder_for_bl;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002175};
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002176
Alex Deuchere3a15922012-08-16 11:13:43 -04002177struct radeon_atcs_functions {
2178 bool get_ext_state;
2179 bool pcie_perf_req;
2180 bool pcie_dev_rdy;
2181 bool pcie_bus_width;
2182};
2183
2184struct radeon_atcs {
2185 struct radeon_atcs_functions functions;
2186};
2187
Michel Dänzer7a1619b2011-11-10 18:57:26 +01002188/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002189 * Core structure, functions and helpers.
2190 */
2191typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2192typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2193
2194struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002195 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002196 struct drm_device *ddev;
2197 struct pci_dev *pdev;
Jerome Glissedee53e72012-07-02 12:45:19 -04002198 struct rw_semaphore exclusive_lock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002199 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02002200 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002201 enum radeon_family family;
2202 unsigned long flags;
2203 int usec_timeout;
2204 enum radeon_pll_errata pll_errata;
2205 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04002206 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002207 int disp_priority;
2208 /* BIOS */
2209 uint8_t *bios;
2210 bool is_atom_bios;
2211 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01002212 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002213 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10002214 resource_size_t rmmio_base;
2215 resource_size_t rmmio_size;
Daniel Vetter2c385152012-12-02 14:06:15 +01002216 /* protects concurrent MM_INDEX/DATA based register access */
2217 spinlock_t mmio_idx_lock;
Alex Deucherfe781182013-09-03 18:19:42 -04002218 /* protects concurrent SMC based register access */
2219 spinlock_t smc_idx_lock;
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002220 /* protects concurrent PLL register access */
2221 spinlock_t pll_idx_lock;
2222 /* protects concurrent MC register access */
2223 spinlock_t mc_idx_lock;
2224 /* protects concurrent PCIE register access */
2225 spinlock_t pcie_idx_lock;
2226 /* protects concurrent PCIE_PORT register access */
2227 spinlock_t pciep_idx_lock;
2228 /* protects concurrent PIF register access */
2229 spinlock_t pif_idx_lock;
2230 /* protects concurrent CG register access */
2231 spinlock_t cg_idx_lock;
2232 /* protects concurrent UVD register access */
2233 spinlock_t uvd_idx_lock;
2234 /* protects concurrent RCU register access */
2235 spinlock_t rcu_idx_lock;
2236 /* protects concurrent DIDT register access */
2237 spinlock_t didt_idx_lock;
2238 /* protects concurrent ENDPOINT (audio) register access */
2239 spinlock_t end_idx_lock;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002240 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002241 radeon_rreg_t mc_rreg;
2242 radeon_wreg_t mc_wreg;
2243 radeon_rreg_t pll_rreg;
2244 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10002245 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002246 radeon_rreg_t pciep_rreg;
2247 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04002248 /* io port */
2249 void __iomem *rio_mem;
2250 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002251 struct radeon_clock clock;
2252 struct radeon_mc mc;
2253 struct radeon_gart gart;
2254 struct radeon_mode_info mode_info;
2255 struct radeon_scratch scratch;
Alex Deucher75efdee2013-03-04 12:47:46 -05002256 struct radeon_doorbell doorbell;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002257 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04002258 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Jerome Glisse0085c9502012-05-09 15:34:55 +02002259 wait_queue_head_t fence_queue;
Christian Königd6999bc2012-05-09 15:34:45 +02002260 struct mutex ring_lock;
Christian Könige32eb502011-10-23 12:56:27 +02002261 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glissec507f7e2012-05-09 15:34:58 +02002262 bool ib_pool_ready;
2263 struct radeon_sa_manager ring_tmp_bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002264 struct radeon_irq irq;
2265 struct radeon_asic *asic;
2266 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02002267 struct radeon_pm pm;
Christian Königf2ba57b2013-04-08 12:41:29 +02002268 struct radeon_uvd uvd;
Christian Königd93f7932013-05-23 12:10:04 +02002269 struct radeon_vce vce;
Yang Zhaof657c2a2009-09-15 12:21:01 +10002270 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002271 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002272 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002273 bool shutdown;
2274 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10002275 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02002276 bool accel_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -04002277 bool fastfb_working; /* IGP feature*/
Christian Königf9eaf9a2013-10-29 20:14:47 +01002278 bool needs_reset;
Dave Airliee024e112009-06-24 09:48:08 +10002279 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002280 const struct firmware *me_fw; /* all family ME firmware */
2281 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002282 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05002283 const struct firmware *mc_fw; /* NI MC firmware */
Alex Deucher0f0de062012-03-20 17:18:17 -04002284 const struct firmware *ce_fw; /* SI CE firmware */
Alex Deucher02c81322012-12-18 21:43:07 -05002285 const struct firmware *mec_fw; /* CIK MEC firmware */
Alex Deucher21a93e12013-04-09 12:47:11 -04002286 const struct firmware *sdma_fw; /* CIK SDMA firmware */
Alex Deucher66229b22013-06-26 00:11:19 -04002287 const struct firmware *smc_fw; /* SMC firmware */
Christian König4ad9c1c2013-08-05 14:10:55 +02002288 const struct firmware *uvd_fw; /* UVD firmware */
Christian Königd93f7932013-05-23 12:10:04 +02002289 const struct firmware *vce_fw; /* VCE firmware */
Alex Deucher16cdf042011-10-28 10:30:02 -04002290 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04002291 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05002292 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucher2948f5e2013-04-12 13:52:52 -04002293 struct radeon_rlc rlc;
Alex Deucher963e81f2013-06-26 17:37:11 -04002294 struct radeon_mec mec;
Alex Deucherd4877cf2009-12-04 16:56:37 -05002295 struct work_struct hotplug_work;
Alex Deucherf122c612012-03-30 08:59:57 -04002296 struct work_struct audio_work;
Alex Deucher8f61b342013-06-14 09:13:52 -04002297 struct work_struct reset_work;
Alex Deucher18917b62010-02-01 16:02:25 -05002298 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05002299 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Alex Deucher948bee32013-05-14 12:08:35 -04002300 bool has_uvd;
Alex Deucherb5306022013-07-31 16:51:33 -04002301 struct r600_audio audio; /* audio stuff */
Alex Deucherce8f5372010-05-07 15:10:16 -04002302 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002303 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10002304 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01002305 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04002306 /* i2c buses */
2307 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02002308 /* debugfs */
2309 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2310 unsigned debugfs_count;
Jerome Glisse721604a2012-01-05 22:11:05 -05002311 /* virtual memory */
2312 struct radeon_vm_manager vm_manager;
Marek Olšák6759a0a2012-08-09 16:34:17 +02002313 struct mutex gpu_clock_mutex;
Marek Olšák67e8e3f2014-03-02 00:56:18 +01002314 /* memory stats */
2315 atomic64_t vram_usage;
2316 atomic64_t gtt_usage;
2317 atomic64_t num_bytes_moved;
Luca Tettamantifd64ca82012-08-16 11:11:18 -04002318 /* ACPI interface */
2319 struct radeon_atif atif;
Alex Deuchere3a15922012-08-16 11:13:43 -04002320 struct radeon_atcs atcs;
Alex Deucherf61d5b462013-08-06 12:40:16 -04002321 /* srbm instance registers */
2322 struct mutex srbm_mutex;
Alex Deucher64d8a722013-08-08 16:31:25 -04002323 /* clock, powergating flags */
2324 u32 cg_flags;
2325 u32 pg_flags;
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002326
2327 struct dev_pm_domain vga_pm_domain;
2328 bool have_disp_power_ref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002329};
2330
Alex Deucher90c4cde2014-04-10 22:29:01 -04002331bool radeon_is_px(struct drm_device *dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002332int radeon_device_init(struct radeon_device *rdev,
2333 struct drm_device *ddev,
2334 struct pci_dev *pdev,
2335 uint32_t flags);
2336void radeon_device_fini(struct radeon_device *rdev);
2337int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2338
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002339uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2340 bool always_indirect);
2341void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2342 bool always_indirect);
Andi Kleen6fcbef72011-10-13 16:08:42 -07002343u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2344void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04002345
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002346u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2347void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
Alex Deucher75efdee2013-03-04 12:47:46 -05002348
Jerome Glisse4c788672009-11-20 14:29:23 +01002349/*
2350 * Cast helper
2351 */
2352#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002353
2354/*
2355 * Registers read & write functions.
2356 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00002357#define RREG8(reg) readb((rdev->rmmio) + (reg))
2358#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2359#define RREG16(reg) readw((rdev->rmmio) + (reg))
2360#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002361#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2362#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2363#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2364#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2365#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002366#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2367#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2368#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2369#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2370#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2371#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10002372#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2373#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Alex Deucher492d2b62012-10-25 16:06:59 -04002374#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2375#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002376#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2377#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
Alex Deucherff82bbc2013-04-12 11:27:20 -04002378#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2379#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
Alex Deucher46f95642013-04-12 11:49:51 -04002380#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2381#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
Alex Deucher792edd62013-02-14 18:18:12 -05002382#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2383#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2384#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2385#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
Alex Deucher93656cd2013-02-25 15:18:39 -05002386#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2387#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
Alex Deucher1d582342013-04-19 13:03:37 -04002388#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2389#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002390#define WREG32_P(reg, val, mask) \
2391 do { \
2392 uint32_t tmp_ = RREG32(reg); \
2393 tmp_ &= (mask); \
2394 tmp_ |= ((val) & ~(mask)); \
2395 WREG32(reg, tmp_); \
2396 } while (0)
Rafał Miłeckid5169fc2013-04-14 01:26:19 +02002397#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
Rafał Miłeckid43a93c2013-08-15 18:55:22 +02002398#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002399#define WREG32_PLL_P(reg, val, mask) \
2400 do { \
2401 uint32_t tmp_ = RREG32_PLL(reg); \
2402 tmp_ &= (mask); \
2403 tmp_ |= ((val) & ~(mask)); \
2404 WREG32_PLL(reg, tmp_); \
2405 } while (0)
Daniel Vetter2ef9bdf2012-12-02 14:02:51 +01002406#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
Alex Deucher351a52a2010-06-30 11:52:50 -04002407#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2408#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002409
Andrew Lewyckyd5754ab2013-11-13 15:54:17 -05002410#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2411#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
Alex Deucher75efdee2013-03-04 12:47:46 -05002412
Dave Airliede1b2892009-08-12 18:43:14 +10002413/*
2414 * Indirect registers accessor
2415 */
2416static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2417{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002418 unsigned long flags;
Dave Airliede1b2892009-08-12 18:43:14 +10002419 uint32_t r;
2420
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002421 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002422 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2423 r = RREG32(RADEON_PCIE_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002424 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002425 return r;
2426}
2427
2428static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2429{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002430 unsigned long flags;
2431
2432 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002433 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2434 WREG32(RADEON_PCIE_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002435 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
Dave Airliede1b2892009-08-12 18:43:14 +10002436}
2437
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002438static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2439{
Alex Deucherfe781182013-09-03 18:19:42 -04002440 unsigned long flags;
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002441 u32 r;
2442
Alex Deucherfe781182013-09-03 18:19:42 -04002443 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002444 WREG32(TN_SMC_IND_INDEX_0, (reg));
2445 r = RREG32(TN_SMC_IND_DATA_0);
Alex Deucherfe781182013-09-03 18:19:42 -04002446 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002447 return r;
2448}
2449
2450static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2451{
Alex Deucherfe781182013-09-03 18:19:42 -04002452 unsigned long flags;
2453
2454 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002455 WREG32(TN_SMC_IND_INDEX_0, (reg));
2456 WREG32(TN_SMC_IND_DATA_0, (v));
Alex Deucherfe781182013-09-03 18:19:42 -04002457 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
Alex Deucher1d5d0c32012-04-20 12:39:49 -04002458}
2459
Alex Deucherff82bbc2013-04-12 11:27:20 -04002460static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2461{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002462 unsigned long flags;
Alex Deucherff82bbc2013-04-12 11:27:20 -04002463 u32 r;
2464
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002465 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002466 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2467 r = RREG32(R600_RCU_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002468 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002469 return r;
2470}
2471
2472static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2473{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002474 unsigned long flags;
2475
2476 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002477 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2478 WREG32(R600_RCU_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002479 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
Alex Deucherff82bbc2013-04-12 11:27:20 -04002480}
2481
Alex Deucher46f95642013-04-12 11:49:51 -04002482static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2483{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002484 unsigned long flags;
Alex Deucher46f95642013-04-12 11:49:51 -04002485 u32 r;
2486
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002487 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002488 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2489 r = RREG32(EVERGREEN_CG_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002490 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002491 return r;
2492}
2493
2494static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2495{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002496 unsigned long flags;
2497
2498 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002499 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2500 WREG32(EVERGREEN_CG_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002501 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
Alex Deucher46f95642013-04-12 11:49:51 -04002502}
2503
Alex Deucher792edd62013-02-14 18:18:12 -05002504static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2505{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002506 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002507 u32 r;
2508
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002509 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002510 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2511 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002512 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002513 return r;
2514}
2515
2516static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2517{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002518 unsigned long flags;
2519
2520 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002521 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2522 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002523 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002524}
2525
2526static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2527{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002528 unsigned long flags;
Alex Deucher792edd62013-02-14 18:18:12 -05002529 u32 r;
2530
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002531 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002532 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2533 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002534 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002535 return r;
2536}
2537
2538static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2539{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002540 unsigned long flags;
2541
2542 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002543 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2544 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002545 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
Alex Deucher792edd62013-02-14 18:18:12 -05002546}
2547
Alex Deucher93656cd2013-02-25 15:18:39 -05002548static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2549{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002550 unsigned long flags;
Alex Deucher93656cd2013-02-25 15:18:39 -05002551 u32 r;
2552
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002553 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002554 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2555 r = RREG32(R600_UVD_CTX_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002556 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002557 return r;
2558}
2559
2560static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2561{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002562 unsigned long flags;
2563
2564 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002565 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2566 WREG32(R600_UVD_CTX_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002567 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
Alex Deucher93656cd2013-02-25 15:18:39 -05002568}
2569
Alex Deucher1d582342013-04-19 13:03:37 -04002570
2571static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2572{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002573 unsigned long flags;
Alex Deucher1d582342013-04-19 13:03:37 -04002574 u32 r;
2575
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002576 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002577 WREG32(CIK_DIDT_IND_INDEX, (reg));
2578 r = RREG32(CIK_DIDT_IND_DATA);
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002579 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002580 return r;
2581}
2582
2583static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2584{
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002585 unsigned long flags;
2586
2587 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002588 WREG32(CIK_DIDT_IND_INDEX, (reg));
2589 WREG32(CIK_DIDT_IND_DATA, (v));
Alex Deucher0a5b7b02013-09-03 19:00:09 -04002590 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
Alex Deucher1d582342013-04-19 13:03:37 -04002591}
2592
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002593void r100_pll_errata_after_index(struct radeon_device *rdev);
2594
2595
2596/*
2597 * ASICs helpers.
2598 */
Dave Airlieb995e432009-07-14 02:02:32 +10002599#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2600 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002601#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2602 (rdev->family == CHIP_RV200) || \
2603 (rdev->family == CHIP_RS100) || \
2604 (rdev->family == CHIP_RS200) || \
2605 (rdev->family == CHIP_RV250) || \
2606 (rdev->family == CHIP_RV280) || \
2607 (rdev->family == CHIP_RS300))
2608#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2609 (rdev->family == CHIP_RV350) || \
2610 (rdev->family == CHIP_R350) || \
2611 (rdev->family == CHIP_RV380) || \
2612 (rdev->family == CHIP_R420) || \
2613 (rdev->family == CHIP_R423) || \
2614 (rdev->family == CHIP_RV410) || \
2615 (rdev->family == CHIP_RS400) || \
2616 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05002617#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2618 (rdev->ddev->pdev->device == 0x9443) || \
2619 (rdev->ddev->pdev->device == 0x944B) || \
2620 (rdev->ddev->pdev->device == 0x9506) || \
2621 (rdev->ddev->pdev->device == 0x9509) || \
2622 (rdev->ddev->pdev->device == 0x950F) || \
2623 (rdev->ddev->pdev->device == 0x689C) || \
2624 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002625#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05002626#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2627 (rdev->family == CHIP_RS690) || \
2628 (rdev->family == CHIP_RS740) || \
2629 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002630#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2631#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05002632#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05002633#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2634 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05002635#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Alex Deucher8848f752012-03-20 17:18:28 -04002636#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2637#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2638 (rdev->flags & RADEON_IS_IGP))
Alex Deucher624d3522012-12-18 17:01:35 -05002639#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
Alex Deucherb5d9d722012-07-26 18:53:55 -04002640#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
Alex Deuchere2829172013-06-07 11:37:11 -04002641#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
Alex Deucherbe0949f2014-04-08 11:28:54 -04002642#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2643#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
Alex Deucher89d26182014-05-08 18:26:23 -04002644#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2645 (rdev->family == CHIP_MULLINS))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002646
Alex Deucherdc50ba72013-06-26 00:33:35 -04002647#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2648 (rdev->ddev->pdev->device == 0x6850) || \
2649 (rdev->ddev->pdev->device == 0x6858) || \
2650 (rdev->ddev->pdev->device == 0x6859) || \
2651 (rdev->ddev->pdev->device == 0x6840) || \
2652 (rdev->ddev->pdev->device == 0x6841) || \
2653 (rdev->ddev->pdev->device == 0x6842) || \
2654 (rdev->ddev->pdev->device == 0x6843))
2655
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002656/*
2657 * BIOS helpers.
2658 */
2659#define RBIOS8(i) (rdev->bios[i])
2660#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2661#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2662
2663int radeon_combios_init(struct radeon_device *rdev);
2664void radeon_combios_fini(struct radeon_device *rdev);
2665int radeon_atombios_init(struct radeon_device *rdev);
2666void radeon_atombios_fini(struct radeon_device *rdev);
2667
2668
2669/*
2670 * RING helpers.
2671 */
Andi Kleence580fa2011-10-13 16:08:47 -07002672#if DRM_DEBUG_CODE == 0
Christian Könige32eb502011-10-23 12:56:27 +02002673static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002674{
Christian Könige32eb502011-10-23 12:56:27 +02002675 ring->ring[ring->wptr++] = v;
2676 ring->wptr &= ring->ptr_mask;
2677 ring->count_dw--;
2678 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002679}
Andi Kleence580fa2011-10-13 16:08:47 -07002680#else
2681/* With debugging this is just too big to inline */
Christian Könige32eb502011-10-23 12:56:27 +02002682void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
Andi Kleence580fa2011-10-13 16:08:47 -07002683#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002684
2685/*
2686 * ASICs macro.
2687 */
Jerome Glisse068a1172009-06-17 13:28:30 +02002688#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10002689#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2690#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2691#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Christian König76a0df82013-08-13 11:56:50 +02002692#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10002693#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Jerome Glissea2d07b72010-03-09 14:45:11 +00002694#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Alex Deucherc5b3b852012-02-23 17:53:46 -05002695#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2696#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
Christian König05b07142012-08-06 20:21:10 +02002697#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2698#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
Alex Deucher43f12142013-02-01 17:32:42 +01002699#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
Christian König76a0df82013-08-13 11:56:50 +02002700#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2701#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2702#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2703#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2704#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2705#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2706#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2707#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2708#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2709#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
Alex Deucherb35ea4a2012-02-23 17:53:43 -05002710#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2711#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002712#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
Alex Deucher37e9b6a2012-08-03 11:39:43 -04002713#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
Alex Deucher6d92f812012-09-14 09:59:26 -04002714#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
Alex Deuchera973bea2013-04-18 11:32:16 -04002715#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2716#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
Christian König76a0df82013-08-13 11:56:50 +02002717#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2718#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Alex Deucher27cd7762012-02-23 17:53:42 -05002719#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2720#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2721#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2722#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2723#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2724#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
Alex Deucher798bcf72012-02-23 17:53:48 -05002725#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2726#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2727#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2728#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2729#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2730#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2731#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
Alex Deucher73afc702013-04-08 12:41:30 +02002732#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
Alex Deucherb59b7332013-08-20 20:01:18 -04002733#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
Alex Deucher6bd1c382013-06-21 14:38:03 -04002734#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
Alex Deucher9e6f3d02012-02-23 17:53:49 -05002735#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2736#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
Alex Deucherc79a49c2012-02-23 17:53:47 -05002737#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
Alex Deucher901ea572012-02-23 17:53:39 -05002738#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2739#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2740#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2741#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
Alex Deucherdef9ba92010-04-22 12:39:58 -04002742#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera02fa392012-02-23 17:53:41 -05002743#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2744#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2745#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2746#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2747#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
Alex Deucher69b62ad2012-08-03 11:50:54 -04002748#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2749#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2750#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2751#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2752#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
Alex Deucher454d2e22013-02-14 10:04:02 -05002753#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
Alex Deucherd0418892013-01-24 10:35:23 -05002754#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002755#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2756#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2757#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
Alex Deucher914a8982013-12-19 11:37:22 -05002758#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002759#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002760#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002761#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
Alex Deucher84dd1922013-01-16 12:52:04 -05002762#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
Alex Deucherda321c82013-04-12 13:55:22 -04002763#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2764#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2765#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2766#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2767#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
Alex Deucher1316b792013-06-28 09:28:39 -04002768#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
Alex Deucher70d01a52013-07-02 18:38:02 -04002769#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
Alex Deucher48783062013-07-08 11:35:06 -04002770#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
Alex Deucher9e9d9762013-07-31 18:13:23 -04002771#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
Alex Deucher1c71bda2013-09-09 19:11:52 -04002772#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002773
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002774/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002775/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00002776extern int radeon_gpu_reset(struct radeon_device *rdev);
Alex Deucher1a0041b2013-10-02 13:01:36 -04002777extern void radeon_pci_config_reset(struct radeon_device *rdev);
Alex Deucher410a3412013-01-18 13:05:39 -05002778extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01002779extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02002780extern int radeon_modeset_init(struct radeon_device *rdev);
2781extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02002782extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04002783extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04002784extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10002785extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02002786extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04002787extern void radeon_wb_fini(struct radeon_device *rdev);
2788extern int radeon_wb_init(struct radeon_device *rdev);
2789extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02002790extern void radeon_surface_init(struct radeon_device *rdev);
2791extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02002792extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02002793extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01002794extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01002795extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glissed594e462010-02-17 21:54:29 +00002796extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2797extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie10ebc0b2012-09-17 14:40:31 +10002798extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2799extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
Dave Airlie53595332011-03-14 09:47:24 +10002800extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Alex Deucher2e1b65f2013-02-26 11:26:51 -05002801extern void radeon_program_register_sequence(struct radeon_device *rdev,
2802 const u32 *registers,
2803 const u32 array_size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02002804
Daniel Vetter3574dda2011-02-18 17:59:19 +01002805/*
Jerome Glisse721604a2012-01-05 22:11:05 -05002806 * vm
2807 */
2808int radeon_vm_manager_init(struct radeon_device *rdev);
2809void radeon_vm_manager_fini(struct radeon_device *rdev);
Christian König6d2f2942014-02-20 13:42:17 +01002810int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
Jerome Glisse721604a2012-01-05 22:11:05 -05002811void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
Christian Königdf0af442014-03-03 12:38:08 +01002812struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2813 struct radeon_vm *vm,
2814 struct list_head *head);
Christian Königee60e292012-08-09 16:21:08 +02002815struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2816 struct radeon_vm *vm, int ring);
Christian Königfa688342014-02-20 10:47:05 +01002817void radeon_vm_flush(struct radeon_device *rdev,
2818 struct radeon_vm *vm,
2819 int ring);
Christian Königee60e292012-08-09 16:21:08 +02002820void radeon_vm_fence(struct radeon_device *rdev,
2821 struct radeon_vm *vm,
2822 struct radeon_fence *fence);
Christian Königdce34bf2012-09-17 19:36:18 +02002823uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
Christian König6d2f2942014-02-20 13:42:17 +01002824int radeon_vm_update_page_directory(struct radeon_device *rdev,
2825 struct radeon_vm *vm);
Christian König9c57a6b2013-11-25 15:42:11 +01002826int radeon_vm_bo_update(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 struct radeon_bo *bo,
2829 struct ttm_mem_reg *mem);
Jerome Glisse721604a2012-01-05 22:11:05 -05002830void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2831 struct radeon_bo *bo);
Christian König421ca7a2012-09-11 16:10:00 +02002832struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2833 struct radeon_bo *bo);
Christian Könige971bd52012-09-11 16:10:04 +02002834struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2835 struct radeon_vm *vm,
2836 struct radeon_bo *bo);
2837int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2838 struct radeon_bo_va *bo_va,
2839 uint64_t offset,
2840 uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -05002841int radeon_vm_bo_rmv(struct radeon_device *rdev,
Christian Könige971bd52012-09-11 16:10:04 +02002842 struct radeon_bo_va *bo_va);
Jerome Glisse721604a2012-01-05 22:11:05 -05002843
Alex Deucherf122c612012-03-30 08:59:57 -04002844/* audio */
2845void r600_audio_update_hdmi(struct work_struct *work);
Alex Deucherb5306022013-07-31 16:51:33 -04002846struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2847struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
Alex Deucher832eafa2014-02-18 11:07:55 -05002848void r600_audio_enable(struct radeon_device *rdev,
2849 struct r600_audio_pin *pin,
2850 bool enable);
2851void dce6_audio_enable(struct radeon_device *rdev,
2852 struct r600_audio_pin *pin,
2853 bool enable);
Jerome Glisse721604a2012-01-05 22:11:05 -05002854
2855/*
Alex Deucher16cdf042011-10-28 10:30:02 -04002856 * R600 vram scratch functions
2857 */
2858int r600_vram_scratch_init(struct radeon_device *rdev);
2859void r600_vram_scratch_fini(struct radeon_device *rdev);
2860
2861/*
Jerome Glisse285484e2011-12-16 17:03:42 -05002862 * r600 cs checking helper
2863 */
2864unsigned r600_mip_minify(unsigned size, unsigned level);
2865bool r600_fmt_is_valid_color(u32 format);
2866bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2867int r600_fmt_get_blocksize(u32 format);
2868int r600_fmt_get_nblocksx(u32 format, u32 w);
2869int r600_fmt_get_nblocksy(u32 format, u32 h);
2870
2871/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01002872 * r600 functions used by radeon_encoder.c
2873 */
Rafał Miłecki1b688d082012-04-30 15:44:54 +02002874struct radeon_hdmi_acr {
2875 u32 clock;
2876
2877 int n_32khz;
2878 int cts_32khz;
2879
2880 int n_44_1khz;
2881 int cts_44_1khz;
2882
2883 int n_48khz;
2884 int cts_48khz;
2885
2886};
2887
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02002888extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2889
Alex Deucher416a2bd2012-05-31 19:00:25 -04002890extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2891 u32 tiling_pipe_num,
2892 u32 max_rb_num,
2893 u32 total_max_rb_num,
2894 u32 enabled_rb_mask);
Alex Deucherfe251e22010-03-24 13:36:43 -04002895
Rafał Miłeckie55d3e62012-05-06 17:29:44 +02002896/*
2897 * evergreen functions used by radeon_encoder.c
2898 */
2899
Alex Deucher0af62b02011-01-06 21:19:31 -05002900extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05002901extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05002902
Alex Deucherc4917072012-07-31 17:14:35 -04002903/* radeon_acpi.c */
2904#if defined(CONFIG_ACPI)
2905extern int radeon_acpi_init(struct radeon_device *rdev);
2906extern void radeon_acpi_fini(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -04002907extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2908extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
Alex Deuchere37e6a02013-02-13 15:47:24 -05002909 u8 perf_req, bool advertise);
Alex Deucherdc50ba72013-06-26 00:33:35 -04002910extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
Alex Deucherc4917072012-07-31 17:14:35 -04002911#else
2912static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2913static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2914#endif
Alberto Miloned7a29522010-07-06 11:40:24 -04002915
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05002916int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2917 struct radeon_cs_packet *pkt,
2918 unsigned idx);
Ilija Hadzic9ffb7a62013-01-02 18:27:42 -05002919bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -05002920void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2921 struct radeon_cs_packet *pkt);
Ilija Hadzice9716992013-01-02 18:27:46 -05002922int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2923 struct radeon_cs_reloc **cs_reloc,
2924 int nomm);
Ilija Hadzic40592a12013-01-02 18:27:43 -05002925int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2926 uint32_t *vline_start_end,
2927 uint32_t *vline_status);
Ilija Hadzicc38f34b2013-01-02 18:27:41 -05002928
Jerome Glisse4c788672009-11-20 14:29:23 +01002929#include "radeon_object.h"
2930
Jerome Glisse771fe6b2009-06-05 14:42:42 +02002931#endif