Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 34 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 38 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 39 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 42 | bool force); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 43 | static __must_check int |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 45 | bool readonly); |
| 46 | static __must_check int |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 48 | struct i915_address_space *vm, |
| 49 | unsigned alignment, |
| 50 | bool map_and_fenceable, |
| 51 | bool nonblocking); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
| 53 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 54 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 55 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 56 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 58 | struct drm_i915_gem_object *obj); |
| 59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 60 | struct drm_i915_fence_reg *fence, |
| 61 | bool enable); |
| 62 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 63 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
| 64 | struct shrink_control *sc); |
| 65 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, |
| 66 | struct shrink_control *sc); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 67 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
| 68 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 69 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 70 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 72 | enum i915_cache_level level) |
| 73 | { |
| 74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 75 | } |
| 76 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 78 | { |
| 79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 80 | return true; |
| 81 | |
| 82 | return obj->pin_display; |
| 83 | } |
| 84 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
| 86 | { |
| 87 | if (obj->tiling_mode) |
| 88 | i915_gem_release_mmap(obj); |
| 89 | |
| 90 | /* As we do not have an associated fence register, we will force |
| 91 | * a tiling change if we ever need to acquire one. |
| 92 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 93 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 94 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 95 | } |
| 96 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 97 | /* some bookkeeping */ |
| 98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 99 | size_t size) |
| 100 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 102 | dev_priv->mm.object_count++; |
| 103 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 108 | size_t size) |
| 109 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 111 | dev_priv->mm.object_count--; |
| 112 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 114 | } |
| 115 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 116 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 118 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 119 | int ret; |
| 120 | |
Daniel Vetter | 7abb690 | 2013-05-24 21:29:32 +0200 | [diff] [blame] | 121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
| 122 | i915_terminally_wedged(error)) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 123 | if (EXIT_COND) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 124 | return 0; |
| 125 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 126 | /* |
| 127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 128 | * userspace. If it takes that long something really bad is going on and |
| 129 | * we should simply try to bail out and fail as gracefully as possible. |
| 130 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
| 132 | EXIT_COND, |
| 133 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 134 | if (ret == 0) { |
| 135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 136 | return -EIO; |
| 137 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 138 | return ret; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 139 | } |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 140 | #undef EXIT_COND |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 141 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 142 | return 0; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 143 | } |
| 144 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 146 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 148 | int ret; |
| 149 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 151 | if (ret) |
| 152 | return ret; |
| 153 | |
| 154 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 155 | if (ret) |
| 156 | return ret; |
| 157 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 158 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 159 | return 0; |
| 160 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 161 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 162 | static inline bool |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 164 | { |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 166 | } |
| 167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 168 | int |
| 169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 170 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 171 | { |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 173 | struct drm_i915_gem_init *args = data; |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 174 | |
Daniel Vetter | 7bb6fb8 | 2012-04-24 08:22:52 +0200 | [diff] [blame] | 175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 176 | return -ENODEV; |
| 177 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 178 | if (args->gtt_start >= args->gtt_end || |
| 179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
| 180 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 181 | |
Daniel Vetter | f534bc0 | 2012-03-26 22:37:04 +0200 | [diff] [blame] | 182 | /* GEM with user mode setting was never supported on ilk and later. */ |
| 183 | if (INTEL_INFO(dev)->gen >= 5) |
| 184 | return -ENODEV; |
| 185 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 186 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
| 188 | args->gtt_end); |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 190 | mutex_unlock(&dev->struct_mutex); |
| 191 | |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 192 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 193 | } |
| 194 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 195 | int |
| 196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 197 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 198 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 200 | struct drm_i915_gem_get_aperture *args = data; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 201 | struct drm_i915_gem_object *obj; |
| 202 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 203 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 204 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 205 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 207 | if (i915_gem_obj_is_pinned(obj)) |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 209 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 210 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 211 | args->aper_size = dev_priv->gtt.base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 212 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 213 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 214 | return 0; |
| 215 | } |
| 216 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 217 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 218 | { |
| 219 | struct drm_i915_private *dev_priv = dev->dev_private; |
Joe Perches | fac15c1 | 2013-08-29 13:11:07 -0700 | [diff] [blame] | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 224 | { |
| 225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 226 | kmem_cache_free(dev_priv->slab, obj); |
| 227 | } |
| 228 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 229 | static int |
| 230 | i915_gem_create(struct drm_file *file, |
| 231 | struct drm_device *dev, |
| 232 | uint64_t size, |
| 233 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 234 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 235 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 236 | int ret; |
| 237 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 238 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 239 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 240 | if (size == 0) |
| 241 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 242 | |
| 243 | /* Allocate the new object */ |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 244 | obj = i915_gem_alloc_object(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 245 | if (obj == NULL) |
| 246 | return -ENOMEM; |
| 247 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 249 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 250 | drm_gem_object_unreference_unlocked(&obj->base); |
| 251 | if (ret) |
| 252 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 253 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 254 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 255 | return 0; |
| 256 | } |
| 257 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 258 | int |
| 259 | i915_gem_dumb_create(struct drm_file *file, |
| 260 | struct drm_device *dev, |
| 261 | struct drm_mode_create_dumb *args) |
| 262 | { |
| 263 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 264 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 265 | args->size = args->pitch * args->height; |
| 266 | return i915_gem_create(file, dev, |
| 267 | args->size, &args->handle); |
| 268 | } |
| 269 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 270 | /** |
| 271 | * Creates a new mm object and returns a handle to it. |
| 272 | */ |
| 273 | int |
| 274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 275 | struct drm_file *file) |
| 276 | { |
| 277 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 278 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 279 | return i915_gem_create(file, dev, |
| 280 | args->size, &args->handle); |
| 281 | } |
| 282 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 283 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 284 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 285 | const char *gpu_vaddr, int gpu_offset, |
| 286 | int length) |
| 287 | { |
| 288 | int ret, cpu_offset = 0; |
| 289 | |
| 290 | while (length > 0) { |
| 291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 292 | int this_length = min(cacheline_end - gpu_offset, length); |
| 293 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 294 | |
| 295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 296 | gpu_vaddr + swizzled_gpu_offset, |
| 297 | this_length); |
| 298 | if (ret) |
| 299 | return ret + length; |
| 300 | |
| 301 | cpu_offset += this_length; |
| 302 | gpu_offset += this_length; |
| 303 | length -= this_length; |
| 304 | } |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 311 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 312 | int length) |
| 313 | { |
| 314 | int ret, cpu_offset = 0; |
| 315 | |
| 316 | while (length > 0) { |
| 317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 318 | int this_length = min(cacheline_end - gpu_offset, length); |
| 319 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 320 | |
| 321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 322 | cpu_vaddr + cpu_offset, |
| 323 | this_length); |
| 324 | if (ret) |
| 325 | return ret + length; |
| 326 | |
| 327 | cpu_offset += this_length; |
| 328 | gpu_offset += this_length; |
| 329 | length -= this_length; |
| 330 | } |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 335 | /* Per-page copy function for the shmem pread fastpath. |
| 336 | * Flushes invalid cachelines before reading the target if |
| 337 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 338 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 339 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 340 | char __user *user_data, |
| 341 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 342 | { |
| 343 | char *vaddr; |
| 344 | int ret; |
| 345 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 346 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 347 | return -EINVAL; |
| 348 | |
| 349 | vaddr = kmap_atomic(page); |
| 350 | if (needs_clflush) |
| 351 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 352 | page_length); |
| 353 | ret = __copy_to_user_inatomic(user_data, |
| 354 | vaddr + shmem_page_offset, |
| 355 | page_length); |
| 356 | kunmap_atomic(vaddr); |
| 357 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 358 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 359 | } |
| 360 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 361 | static void |
| 362 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 363 | bool swizzled) |
| 364 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 365 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 366 | unsigned long start = (unsigned long) addr; |
| 367 | unsigned long end = (unsigned long) addr + length; |
| 368 | |
| 369 | /* For swizzling simply ensure that we always flush both |
| 370 | * channels. Lame, but simple and it works. Swizzled |
| 371 | * pwrite/pread is far from a hotpath - current userspace |
| 372 | * doesn't use it at all. */ |
| 373 | start = round_down(start, 128); |
| 374 | end = round_up(end, 128); |
| 375 | |
| 376 | drm_clflush_virt_range((void *)start, end - start); |
| 377 | } else { |
| 378 | drm_clflush_virt_range(addr, length); |
| 379 | } |
| 380 | |
| 381 | } |
| 382 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 383 | /* Only difference to the fast-path function is that this can handle bit17 |
| 384 | * and uses non-atomic copy and kmap functions. */ |
| 385 | static int |
| 386 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 387 | char __user *user_data, |
| 388 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 389 | { |
| 390 | char *vaddr; |
| 391 | int ret; |
| 392 | |
| 393 | vaddr = kmap(page); |
| 394 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 395 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 396 | page_length, |
| 397 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 398 | |
| 399 | if (page_do_bit17_swizzling) |
| 400 | ret = __copy_to_user_swizzled(user_data, |
| 401 | vaddr, shmem_page_offset, |
| 402 | page_length); |
| 403 | else |
| 404 | ret = __copy_to_user(user_data, |
| 405 | vaddr + shmem_page_offset, |
| 406 | page_length); |
| 407 | kunmap(page); |
| 408 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 409 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 410 | } |
| 411 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 412 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 413 | i915_gem_shmem_pread(struct drm_device *dev, |
| 414 | struct drm_i915_gem_object *obj, |
| 415 | struct drm_i915_gem_pread *args, |
| 416 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 417 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 418 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 419 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 420 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 421 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 422 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 423 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 424 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 425 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 427 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 428 | remain = args->size; |
| 429 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 430 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 432 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 433 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 434 | * read domain and manually flush cachelines (if required). This |
| 435 | * optimizes for the case when the gpu will dirty the data |
| 436 | * anyway again before the next pread happens. */ |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 437 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 438 | ret = i915_gem_object_wait_rendering(obj, true); |
| 439 | if (ret) |
| 440 | return ret; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 441 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 442 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 443 | ret = i915_gem_object_get_pages(obj); |
| 444 | if (ret) |
| 445 | return ret; |
| 446 | |
| 447 | i915_gem_object_pin_pages(obj); |
| 448 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 449 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 450 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 451 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 452 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 453 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 454 | |
| 455 | if (remain <= 0) |
| 456 | break; |
| 457 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | /* Operation in this page |
| 459 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 460 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 461 | * page_length = bytes to copy for this page |
| 462 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 463 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 464 | page_length = remain; |
| 465 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 466 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 467 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 469 | (page_to_phys(page) & (1 << 17)) != 0; |
| 470 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 472 | user_data, page_do_bit17_swizzling, |
| 473 | needs_clflush); |
| 474 | if (ret == 0) |
| 475 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 476 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 477 | mutex_unlock(&dev->struct_mutex); |
| 478 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 479 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 481 | /* Userspace is tricking us, but we've already clobbered |
| 482 | * its pages with the prefault and promised to write the |
| 483 | * data up to the first fault. Hence ignore any errors |
| 484 | * and just continue. */ |
| 485 | (void)ret; |
| 486 | prefaulted = 1; |
| 487 | } |
| 488 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 490 | user_data, page_do_bit17_swizzling, |
| 491 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 492 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 493 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 494 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 495 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 496 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 497 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 498 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 499 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 500 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 501 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 502 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 503 | offset += page_length; |
| 504 | } |
| 505 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 506 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 507 | i915_gem_object_unpin_pages(obj); |
| 508 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 509 | return ret; |
| 510 | } |
| 511 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 512 | /** |
| 513 | * Reads data from the object referenced by handle. |
| 514 | * |
| 515 | * On error, the contents of *data are undefined. |
| 516 | */ |
| 517 | int |
| 518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 519 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 520 | { |
| 521 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 522 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 523 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 524 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 525 | if (args->size == 0) |
| 526 | return 0; |
| 527 | |
| 528 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 529 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 530 | args->size)) |
| 531 | return -EFAULT; |
| 532 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 533 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 534 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 535 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 536 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 538 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 539 | ret = -ENOENT; |
| 540 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 541 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 542 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 543 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 544 | if (args->offset > obj->base.size || |
| 545 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 546 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 547 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 548 | } |
| 549 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 550 | /* prime objects have no backing filp to GEM pread/pwrite |
| 551 | * pages from. |
| 552 | */ |
| 553 | if (!obj->base.filp) { |
| 554 | ret = -EINVAL; |
| 555 | goto out; |
| 556 | } |
| 557 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 559 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 561 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 562 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 563 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 564 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 565 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 566 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 567 | } |
| 568 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 569 | /* This is the fast write path which cannot handle |
| 570 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 571 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 572 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 573 | static inline int |
| 574 | fast_user_write(struct io_mapping *mapping, |
| 575 | loff_t page_base, int page_offset, |
| 576 | char __user *user_data, |
| 577 | int length) |
| 578 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 579 | void __iomem *vaddr_atomic; |
| 580 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 581 | unsigned long unwritten; |
| 582 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 584 | /* We can use the cpu mem copy function because this is X86. */ |
| 585 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 587 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 589 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 590 | } |
| 591 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 592 | /** |
| 593 | * This is the fast pwrite path, where we copy the data directly from the |
| 594 | * user into the GTT, uncached. |
| 595 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 596 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 598 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 599 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 600 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 601 | { |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 603 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 604 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 605 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 606 | int page_offset, page_length, ret; |
| 607 | |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 608 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 609 | if (ret) |
| 610 | goto out; |
| 611 | |
| 612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 613 | if (ret) |
| 614 | goto out_unpin; |
| 615 | |
| 616 | ret = i915_gem_object_put_fence(obj); |
| 617 | if (ret) |
| 618 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 619 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 620 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 621 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 622 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 623 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 624 | |
| 625 | while (remain > 0) { |
| 626 | /* Operation in this page |
| 627 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 628 | * page_base = page offset within aperture |
| 629 | * page_offset = offset within page |
| 630 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 631 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 632 | page_base = offset & PAGE_MASK; |
| 633 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 634 | page_length = remain; |
| 635 | if ((page_offset + remain) > PAGE_SIZE) |
| 636 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 637 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 638 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 639 | * source page isn't available. Return the error and we'll |
| 640 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 641 | */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 643 | page_offset, user_data, page_length)) { |
| 644 | ret = -EFAULT; |
| 645 | goto out_unpin; |
| 646 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 647 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 648 | remain -= page_length; |
| 649 | user_data += page_length; |
| 650 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 651 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 652 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 653 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 654 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 655 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 656 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 657 | } |
| 658 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 659 | /* Per-page copy function for the shmem pwrite fastpath. |
| 660 | * Flushes invalid cachelines before writing to the target if |
| 661 | * needs_clflush_before is set and flushes out any written cachelines after |
| 662 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 663 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 665 | char __user *user_data, |
| 666 | bool page_do_bit17_swizzling, |
| 667 | bool needs_clflush_before, |
| 668 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 669 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 670 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 671 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 672 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 673 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 674 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 675 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 676 | vaddr = kmap_atomic(page); |
| 677 | if (needs_clflush_before) |
| 678 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 679 | page_length); |
| 680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, |
| 681 | user_data, |
| 682 | page_length); |
| 683 | if (needs_clflush_after) |
| 684 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 685 | page_length); |
| 686 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 687 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 688 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 689 | } |
| 690 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 691 | /* Only difference to the fast-path function is that this can handle bit17 |
| 692 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 693 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 695 | char __user *user_data, |
| 696 | bool page_do_bit17_swizzling, |
| 697 | bool needs_clflush_before, |
| 698 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 699 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 700 | char *vaddr; |
| 701 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 702 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 703 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 706 | page_length, |
| 707 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 708 | if (page_do_bit17_swizzling) |
| 709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 710 | user_data, |
| 711 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 712 | else |
| 713 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 714 | user_data, |
| 715 | page_length); |
| 716 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 718 | page_length, |
| 719 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 720 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 721 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 722 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 723 | } |
| 724 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 725 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 727 | struct drm_i915_gem_object *obj, |
| 728 | struct drm_i915_gem_pwrite *args, |
| 729 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 730 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 731 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 732 | loff_t offset; |
| 733 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 734 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 736 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 737 | int needs_clflush_after = 0; |
| 738 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 739 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 740 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 741 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 742 | remain = args->size; |
| 743 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 744 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 745 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 746 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 747 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 748 | * write domain and manually flush cachelines (if required). This |
| 749 | * optimizes for the case when the gpu will use the data |
| 750 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 751 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 752 | ret = i915_gem_object_wait_rendering(obj, false); |
| 753 | if (ret) |
| 754 | return ret; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 755 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 756 | /* Same trick applies to invalidate partially written cachelines read |
| 757 | * before writing. */ |
| 758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 759 | needs_clflush_before = |
| 760 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 761 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 762 | ret = i915_gem_object_get_pages(obj); |
| 763 | if (ret) |
| 764 | return ret; |
| 765 | |
| 766 | i915_gem_object_pin_pages(obj); |
| 767 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 768 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 769 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 770 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 771 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 772 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 773 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 774 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 775 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 776 | if (remain <= 0) |
| 777 | break; |
| 778 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 779 | /* Operation in this page |
| 780 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 781 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | * page_length = bytes to copy for this page |
| 783 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 784 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 785 | |
| 786 | page_length = remain; |
| 787 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 788 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 789 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 790 | /* If we don't overwrite a cacheline completely we need to be |
| 791 | * careful to have up-to-date data by first clflushing. Don't |
| 792 | * overcomplicate things and flush the entire patch. */ |
| 793 | partial_cacheline_write = needs_clflush_before && |
| 794 | ((shmem_page_offset | page_length) |
| 795 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 796 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 798 | (page_to_phys(page) & (1 << 17)) != 0; |
| 799 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 800 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 801 | user_data, page_do_bit17_swizzling, |
| 802 | partial_cacheline_write, |
| 803 | needs_clflush_after); |
| 804 | if (ret == 0) |
| 805 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 806 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 807 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 808 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 809 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 810 | user_data, page_do_bit17_swizzling, |
| 811 | partial_cacheline_write, |
| 812 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 813 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 814 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 815 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 816 | next_page: |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 817 | set_page_dirty(page); |
| 818 | mark_page_accessed(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 819 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 820 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 821 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 822 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 823 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 824 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 825 | offset += page_length; |
| 826 | } |
| 827 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 828 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 829 | i915_gem_object_unpin_pages(obj); |
| 830 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 831 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 832 | /* |
| 833 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 834 | * cachelines in-line while writing and the object moved |
| 835 | * out of the cpu write domain while we've dropped the lock. |
| 836 | */ |
| 837 | if (!needs_clflush_after && |
| 838 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 839 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
| 840 | i915_gem_chipset_flush(dev); |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 841 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 842 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 843 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 844 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 845 | i915_gem_chipset_flush(dev); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 846 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 847 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 848 | } |
| 849 | |
| 850 | /** |
| 851 | * Writes data to the object referenced by handle. |
| 852 | * |
| 853 | * On error, the contents of the buffer that were to be modified are undefined. |
| 854 | */ |
| 855 | int |
| 856 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 857 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 858 | { |
| 859 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 860 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 861 | int ret; |
| 862 | |
| 863 | if (args->size == 0) |
| 864 | return 0; |
| 865 | |
| 866 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 867 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 868 | args->size)) |
| 869 | return -EFAULT; |
| 870 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 871 | if (likely(!i915.prefault_disable)) { |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 872 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 873 | args->size); |
| 874 | if (ret) |
| 875 | return -EFAULT; |
| 876 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 877 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 878 | ret = i915_mutex_lock_interruptible(dev); |
| 879 | if (ret) |
| 880 | return ret; |
| 881 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 883 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 884 | ret = -ENOENT; |
| 885 | goto unlock; |
| 886 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 887 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 888 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 889 | if (args->offset > obj->base.size || |
| 890 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 891 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 892 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 893 | } |
| 894 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 895 | /* prime objects have no backing filp to GEM pread/pwrite |
| 896 | * pages from. |
| 897 | */ |
| 898 | if (!obj->base.filp) { |
| 899 | ret = -EINVAL; |
| 900 | goto out; |
| 901 | } |
| 902 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 903 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 904 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 905 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 906 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 907 | * it would end up going through the fenced access, and we'll get |
| 908 | * different detiling behavior between reading and writing. |
| 909 | * pread/pwrite currently are reading and writing from the CPU |
| 910 | * perspective, requiring manual detiling by the client. |
| 911 | */ |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 912 | if (obj->phys_obj) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 913 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 914 | goto out; |
| 915 | } |
| 916 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 917 | if (obj->tiling_mode == I915_TILING_NONE && |
| 918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 919 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 920 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 921 | /* Note that the gtt paths might fail with non-page-backed user |
| 922 | * pointers (e.g. gtt mappings when moving data between |
| 923 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 924 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 925 | |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 926 | if (ret == -EFAULT || ret == -ENOSPC) |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 927 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 928 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 929 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 930 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 931 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 932 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 933 | return ret; |
| 934 | } |
| 935 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 936 | int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 937 | i915_gem_check_wedge(struct i915_gpu_error *error, |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 938 | bool interruptible) |
| 939 | { |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 940 | if (i915_reset_in_progress(error)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 941 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 942 | * -EIO unconditionally for these. */ |
| 943 | if (!interruptible) |
| 944 | return -EIO; |
| 945 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 946 | /* Recovery complete, but the reset failed ... */ |
| 947 | if (i915_terminally_wedged(error)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 948 | return -EIO; |
| 949 | |
| 950 | return -EAGAIN; |
| 951 | } |
| 952 | |
| 953 | return 0; |
| 954 | } |
| 955 | |
| 956 | /* |
| 957 | * Compare seqno against outstanding lazy request. Emit a request if they are |
| 958 | * equal. |
| 959 | */ |
| 960 | static int |
| 961 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) |
| 962 | { |
| 963 | int ret; |
| 964 | |
| 965 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); |
| 966 | |
| 967 | ret = 0; |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 968 | if (seqno == ring->outstanding_lazy_seqno) |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 969 | ret = i915_add_request(ring, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 970 | |
| 971 | return ret; |
| 972 | } |
| 973 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 974 | static void fake_irq(unsigned long data) |
| 975 | { |
| 976 | wake_up_process((struct task_struct *)data); |
| 977 | } |
| 978 | |
| 979 | static bool missed_irq(struct drm_i915_private *dev_priv, |
| 980 | struct intel_ring_buffer *ring) |
| 981 | { |
| 982 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); |
| 983 | } |
| 984 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 985 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
| 986 | { |
| 987 | if (file_priv == NULL) |
| 988 | return true; |
| 989 | |
| 990 | return !atomic_xchg(&file_priv->rps_wait_boost, true); |
| 991 | } |
| 992 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 993 | /** |
| 994 | * __wait_seqno - wait until execution of seqno has finished |
| 995 | * @ring: the ring expected to report seqno |
| 996 | * @seqno: duh! |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 997 | * @reset_counter: reset sequence associated with the given seqno |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 998 | * @interruptible: do an interruptible wait (normally yes) |
| 999 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1000 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1001 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1002 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1003 | * locks are involved, it is sufficient to read the reset_counter before |
| 1004 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1005 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1006 | * inserted. |
| 1007 | * |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1008 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
| 1009 | * errno with remaining time filled in timeout argument. |
| 1010 | */ |
| 1011 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1012 | unsigned reset_counter, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1013 | bool interruptible, |
| 1014 | struct timespec *timeout, |
| 1015 | struct drm_i915_file_private *file_priv) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1016 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1017 | struct drm_device *dev = ring->dev; |
| 1018 | drm_i915_private_t *dev_priv = dev->dev_private; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1019 | const bool irq_test_in_progress = |
| 1020 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1021 | struct timespec before, now; |
| 1022 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1023 | unsigned long timeout_expire; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1024 | int ret; |
| 1025 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1026 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
| 1027 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1028 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
| 1029 | return 0; |
| 1030 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1031 | timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1032 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1033 | if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1034 | gen6_rps_boost(dev_priv); |
| 1035 | if (file_priv) |
| 1036 | mod_delayed_work(dev_priv->wq, |
| 1037 | &file_priv->mm.idle_work, |
| 1038 | msecs_to_jiffies(100)); |
| 1039 | } |
| 1040 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1041 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1042 | return -ENODEV; |
| 1043 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1044 | /* Record current time in case interrupted by signal, or wedged */ |
| 1045 | trace_i915_gem_request_wait_begin(ring, seqno); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1046 | getrawmonotonic(&before); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1047 | for (;;) { |
| 1048 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1049 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1050 | prepare_to_wait(&ring->irq_queue, &wait, |
| 1051 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1052 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1053 | /* We need to check whether any gpu reset happened in between |
| 1054 | * the caller grabbing the seqno and now ... */ |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1055 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
| 1056 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu |
| 1057 | * is truely gone. */ |
| 1058 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
| 1059 | if (ret == 0) |
| 1060 | ret = -EAGAIN; |
| 1061 | break; |
| 1062 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1063 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1064 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
| 1065 | ret = 0; |
| 1066 | break; |
| 1067 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1068 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1069 | if (interruptible && signal_pending(current)) { |
| 1070 | ret = -ERESTARTSYS; |
| 1071 | break; |
| 1072 | } |
| 1073 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1074 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1075 | ret = -ETIME; |
| 1076 | break; |
| 1077 | } |
| 1078 | |
| 1079 | timer.function = NULL; |
| 1080 | if (timeout || missed_irq(dev_priv, ring)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1081 | unsigned long expire; |
| 1082 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1083 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1084 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1085 | mod_timer(&timer, expire); |
| 1086 | } |
| 1087 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1088 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1089 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1090 | if (timer.function) { |
| 1091 | del_singleshot_timer_sync(&timer); |
| 1092 | destroy_timer_on_stack(&timer); |
| 1093 | } |
| 1094 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1095 | getrawmonotonic(&now); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1096 | trace_i915_gem_request_wait_end(ring, seqno); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1097 | |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1098 | if (!irq_test_in_progress) |
| 1099 | ring->irq_put(ring); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1100 | |
| 1101 | finish_wait(&ring->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1102 | |
| 1103 | if (timeout) { |
| 1104 | struct timespec sleep_time = timespec_sub(now, before); |
| 1105 | *timeout = timespec_sub(*timeout, sleep_time); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 1106 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
| 1107 | set_normalized_timespec(timeout, 0, 0); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1108 | } |
| 1109 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1110 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | /** |
| 1114 | * Waits for a sequence number to be signaled, and cleans up the |
| 1115 | * request and object lists appropriately for that event. |
| 1116 | */ |
| 1117 | int |
| 1118 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
| 1119 | { |
| 1120 | struct drm_device *dev = ring->dev; |
| 1121 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1122 | bool interruptible = dev_priv->mm.interruptible; |
| 1123 | int ret; |
| 1124 | |
| 1125 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1126 | BUG_ON(seqno == 0); |
| 1127 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1128 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1129 | if (ret) |
| 1130 | return ret; |
| 1131 | |
| 1132 | ret = i915_gem_check_olr(ring, seqno); |
| 1133 | if (ret) |
| 1134 | return ret; |
| 1135 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1136 | return __wait_seqno(ring, seqno, |
| 1137 | atomic_read(&dev_priv->gpu_error.reset_counter), |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1138 | interruptible, NULL, NULL); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1139 | } |
| 1140 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1141 | static int |
| 1142 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, |
| 1143 | struct intel_ring_buffer *ring) |
| 1144 | { |
| 1145 | i915_gem_retire_requests_ring(ring); |
| 1146 | |
| 1147 | /* Manually manage the write flush as we may have not yet |
| 1148 | * retired the buffer. |
| 1149 | * |
| 1150 | * Note that the last_write_seqno is always the earlier of |
| 1151 | * the two (read/write) seqno, so if we haved successfully waited, |
| 1152 | * we know we have passed the last write. |
| 1153 | */ |
| 1154 | obj->last_write_seqno = 0; |
| 1155 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1160 | /** |
| 1161 | * Ensures that all rendering to the object has completed and the object is |
| 1162 | * safe to unbind from the GTT or access from the CPU. |
| 1163 | */ |
| 1164 | static __must_check int |
| 1165 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1166 | bool readonly) |
| 1167 | { |
| 1168 | struct intel_ring_buffer *ring = obj->ring; |
| 1169 | u32 seqno; |
| 1170 | int ret; |
| 1171 | |
| 1172 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1173 | if (seqno == 0) |
| 1174 | return 0; |
| 1175 | |
| 1176 | ret = i915_wait_seqno(ring, seqno); |
| 1177 | if (ret) |
| 1178 | return ret; |
| 1179 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1180 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1181 | } |
| 1182 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1183 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1184 | * as the object state may change during this call. |
| 1185 | */ |
| 1186 | static __must_check int |
| 1187 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame^] | 1188 | struct drm_i915_file_private *file_priv, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1189 | bool readonly) |
| 1190 | { |
| 1191 | struct drm_device *dev = obj->base.dev; |
| 1192 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1193 | struct intel_ring_buffer *ring = obj->ring; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1194 | unsigned reset_counter; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1195 | u32 seqno; |
| 1196 | int ret; |
| 1197 | |
| 1198 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1199 | BUG_ON(!dev_priv->mm.interruptible); |
| 1200 | |
| 1201 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; |
| 1202 | if (seqno == 0) |
| 1203 | return 0; |
| 1204 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1205 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1206 | if (ret) |
| 1207 | return ret; |
| 1208 | |
| 1209 | ret = i915_gem_check_olr(ring, seqno); |
| 1210 | if (ret) |
| 1211 | return ret; |
| 1212 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1213 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1214 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame^] | 1215 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1216 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1217 | if (ret) |
| 1218 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1219 | |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1220 | return i915_gem_object_wait_rendering__tail(obj, ring); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1221 | } |
| 1222 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1223 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1224 | * Called when user space prepares to use an object with the CPU, either |
| 1225 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1226 | */ |
| 1227 | int |
| 1228 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1229 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1230 | { |
| 1231 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1232 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1233 | uint32_t read_domains = args->read_domains; |
| 1234 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1235 | int ret; |
| 1236 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1237 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1238 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1239 | return -EINVAL; |
| 1240 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1241 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1242 | return -EINVAL; |
| 1243 | |
| 1244 | /* Having something in the write domain implies it's in the read |
| 1245 | * domain, and only that read domain. Enforce that in the request. |
| 1246 | */ |
| 1247 | if (write_domain != 0 && read_domains != write_domain) |
| 1248 | return -EINVAL; |
| 1249 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1250 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1251 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1252 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1253 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1254 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1255 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1256 | ret = -ENOENT; |
| 1257 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1258 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1259 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1260 | /* Try to flush the object off the GPU without holding the lock. |
| 1261 | * We will repeat the flush holding the lock in the normal manner |
| 1262 | * to catch cases where we are gazumped. |
| 1263 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame^] | 1264 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
| 1265 | file->driver_priv, |
| 1266 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1267 | if (ret) |
| 1268 | goto unref; |
| 1269 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1270 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1271 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1272 | |
| 1273 | /* Silently promote "you're not bound, there was nothing to do" |
| 1274 | * to success, since the client was just asking us to |
| 1275 | * make sure everything was done. |
| 1276 | */ |
| 1277 | if (ret == -EINVAL) |
| 1278 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1279 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1280 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1281 | } |
| 1282 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1283 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1284 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1285 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1286 | mutex_unlock(&dev->struct_mutex); |
| 1287 | return ret; |
| 1288 | } |
| 1289 | |
| 1290 | /** |
| 1291 | * Called when user space has done writes to this buffer |
| 1292 | */ |
| 1293 | int |
| 1294 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1295 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1296 | { |
| 1297 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1298 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1299 | int ret = 0; |
| 1300 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1301 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1302 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1303 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1304 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1305 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1306 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1307 | ret = -ENOENT; |
| 1308 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1309 | } |
| 1310 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1311 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1312 | if (obj->pin_display) |
| 1313 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1314 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1315 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1316 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1317 | mutex_unlock(&dev->struct_mutex); |
| 1318 | return ret; |
| 1319 | } |
| 1320 | |
| 1321 | /** |
| 1322 | * Maps the contents of an object, returning the address it is mapped |
| 1323 | * into. |
| 1324 | * |
| 1325 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1326 | * imply a ref on the object itself. |
| 1327 | */ |
| 1328 | int |
| 1329 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1330 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1331 | { |
| 1332 | struct drm_i915_gem_mmap *args = data; |
| 1333 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1334 | unsigned long addr; |
| 1335 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1336 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1337 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1338 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1339 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1340 | /* prime objects have no backing filp to GEM mmap |
| 1341 | * pages from. |
| 1342 | */ |
| 1343 | if (!obj->filp) { |
| 1344 | drm_gem_object_unreference_unlocked(obj); |
| 1345 | return -EINVAL; |
| 1346 | } |
| 1347 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1348 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1349 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1350 | args->offset); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1351 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1352 | if (IS_ERR((void *)addr)) |
| 1353 | return addr; |
| 1354 | |
| 1355 | args->addr_ptr = (uint64_t) addr; |
| 1356 | |
| 1357 | return 0; |
| 1358 | } |
| 1359 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1360 | /** |
| 1361 | * i915_gem_fault - fault a page into the GTT |
| 1362 | * vma: VMA in question |
| 1363 | * vmf: fault info |
| 1364 | * |
| 1365 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1366 | * from userspace. The fault handler takes care of binding the object to |
| 1367 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1368 | * only if needed based on whether the old reg is still valid or the object |
| 1369 | * is tiled) and inserting a new PTE into the faulting process. |
| 1370 | * |
| 1371 | * Note that the faulting process may involve evicting existing objects |
| 1372 | * from the GTT and/or fence registers to make room. So performance may |
| 1373 | * suffer if the GTT working set is large or there are few fence registers |
| 1374 | * left. |
| 1375 | */ |
| 1376 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1377 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1378 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1379 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1380 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1381 | pgoff_t page_offset; |
| 1382 | unsigned long pfn; |
| 1383 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1384 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1385 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1386 | intel_runtime_pm_get(dev_priv); |
| 1387 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1388 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1389 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1390 | PAGE_SHIFT; |
| 1391 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1392 | ret = i915_mutex_lock_interruptible(dev); |
| 1393 | if (ret) |
| 1394 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1395 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1396 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1397 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame^] | 1398 | /* Try to flush the object off the GPU first without holding the lock. |
| 1399 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1400 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1401 | * where we are gazumped. |
| 1402 | */ |
| 1403 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1404 | if (ret) |
| 1405 | goto unlock; |
| 1406 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1407 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1408 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
| 1409 | ret = -EINVAL; |
| 1410 | goto unlock; |
| 1411 | } |
| 1412 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1413 | /* Now bind it into the GTT if needed */ |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 1414 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1415 | if (ret) |
| 1416 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1417 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1418 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1419 | if (ret) |
| 1420 | goto unpin; |
| 1421 | |
| 1422 | ret = i915_gem_object_get_fence(obj); |
| 1423 | if (ret) |
| 1424 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1425 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1426 | obj->fault_mappable = true; |
| 1427 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1428 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
| 1429 | pfn >>= PAGE_SHIFT; |
| 1430 | pfn += page_offset; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1431 | |
| 1432 | /* Finally, remap it using the new GTT offset */ |
| 1433 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1434 | unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1435 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1436 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1437 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1438 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1439 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1440 | case -EIO: |
Daniel Vetter | a9340cc | 2012-07-04 22:18:42 +0200 | [diff] [blame] | 1441 | /* If this -EIO is due to a gpu hang, give the reset code a |
| 1442 | * chance to clean up the mess. Otherwise return the proper |
| 1443 | * SIGBUS. */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1444 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
| 1445 | ret = VM_FAULT_SIGBUS; |
| 1446 | break; |
| 1447 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1448 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1449 | /* |
| 1450 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1451 | * handler to reset everything when re-faulting in |
| 1452 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1453 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1454 | case 0: |
| 1455 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1456 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1457 | case -EBUSY: |
| 1458 | /* |
| 1459 | * EBUSY is ok: this just means that another thread |
| 1460 | * already did the job. |
| 1461 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1462 | ret = VM_FAULT_NOPAGE; |
| 1463 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1464 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1465 | ret = VM_FAULT_OOM; |
| 1466 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1467 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1468 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1469 | ret = VM_FAULT_SIGBUS; |
| 1470 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1471 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1472 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1473 | ret = VM_FAULT_SIGBUS; |
| 1474 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1475 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1476 | |
| 1477 | intel_runtime_pm_put(dev_priv); |
| 1478 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1479 | } |
| 1480 | |
Paulo Zanoni | 48018a5 | 2013-12-13 15:22:31 -0200 | [diff] [blame] | 1481 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1482 | { |
| 1483 | struct i915_vma *vma; |
| 1484 | |
| 1485 | /* |
| 1486 | * Only the global gtt is relevant for gtt memory mappings, so restrict |
| 1487 | * list traversal to objects bound into the global address space. Note |
| 1488 | * that the active list should be empty, but better safe than sorry. |
| 1489 | */ |
| 1490 | WARN_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
| 1491 | list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list) |
| 1492 | i915_gem_release_mmap(vma->obj); |
| 1493 | list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list) |
| 1494 | i915_gem_release_mmap(vma->obj); |
| 1495 | } |
| 1496 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1497 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1498 | * i915_gem_release_mmap - remove physical page mappings |
| 1499 | * @obj: obj in question |
| 1500 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1501 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1502 | * relinquish ownership of the pages back to the system. |
| 1503 | * |
| 1504 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1505 | * object through the GTT and then lose the fence register due to |
| 1506 | * resource pressure. Similarly if the object has been moved out of the |
| 1507 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1508 | * mapping will then trigger a page fault on the next user access, allowing |
| 1509 | * fixup by i915_gem_fault(). |
| 1510 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1511 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1512 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1513 | { |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1514 | if (!obj->fault_mappable) |
| 1515 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1516 | |
David Herrmann | 51335df | 2013-07-24 21:10:03 +0200 | [diff] [blame] | 1517 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1518 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1519 | } |
| 1520 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1521 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1522 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1523 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1524 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1525 | |
| 1526 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1527 | tiling_mode == I915_TILING_NONE) |
| 1528 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1529 | |
| 1530 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1531 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1532 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1533 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1534 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1535 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1536 | while (gtt_size < size) |
| 1537 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1538 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1539 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1540 | } |
| 1541 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1542 | /** |
| 1543 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1544 | * @obj: object to check |
| 1545 | * |
| 1546 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1547 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1548 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1549 | uint32_t |
| 1550 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1551 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1552 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1553 | /* |
| 1554 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1555 | * if a fence register is needed for the object. |
| 1556 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1557 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1558 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1559 | return 4096; |
| 1560 | |
| 1561 | /* |
| 1562 | * Previous chips need to be aligned to the size of the smallest |
| 1563 | * fence register that can contain the object. |
| 1564 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1565 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1566 | } |
| 1567 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1568 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 1569 | { |
| 1570 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1571 | int ret; |
| 1572 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1573 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1574 | return 0; |
| 1575 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1576 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 1577 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1578 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1579 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1580 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1581 | |
| 1582 | /* Badly fragmented mmap space? The only way we can recover |
| 1583 | * space is by destroying unwanted objects. We can't randomly release |
| 1584 | * mmap_offsets as userspace expects them to be persistent for the |
| 1585 | * lifetime of the objects. The closest we can is to release the |
| 1586 | * offsets on purgeable objects by truncating it and marking it purged, |
| 1587 | * which prevents userspace from ever using that object again. |
| 1588 | */ |
| 1589 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); |
| 1590 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1591 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1592 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1593 | |
| 1594 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 1595 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 1596 | out: |
| 1597 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 1598 | |
| 1599 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1600 | } |
| 1601 | |
| 1602 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 1603 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1604 | drm_gem_free_mmap_offset(&obj->base); |
| 1605 | } |
| 1606 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1607 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1608 | i915_gem_mmap_gtt(struct drm_file *file, |
| 1609 | struct drm_device *dev, |
| 1610 | uint32_t handle, |
| 1611 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1612 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1613 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1614 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1615 | int ret; |
| 1616 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1617 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1618 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1619 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1620 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1621 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1622 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1623 | ret = -ENOENT; |
| 1624 | goto unlock; |
| 1625 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1626 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1627 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1628 | ret = -E2BIG; |
Eric Anholt | ff56b0b | 2011-10-31 23:16:21 -0700 | [diff] [blame] | 1629 | goto out; |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1630 | } |
| 1631 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1632 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 1633 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 1634 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1635 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1636 | } |
| 1637 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 1638 | ret = i915_gem_object_create_mmap_offset(obj); |
| 1639 | if (ret) |
| 1640 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1641 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 1642 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1643 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1644 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1645 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1646 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1647 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1648 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1649 | } |
| 1650 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1651 | /** |
| 1652 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1653 | * @dev: DRM device |
| 1654 | * @data: GTT mapping ioctl data |
| 1655 | * @file: GEM object info |
| 1656 | * |
| 1657 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1658 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1659 | * up so we can get faults in the handler above. |
| 1660 | * |
| 1661 | * The fault handler will take care of binding the object into the GTT |
| 1662 | * (since it may have been evicted to make room for something), allocating |
| 1663 | * a fence register, and mapping the appropriate aperture address into |
| 1664 | * userspace. |
| 1665 | */ |
| 1666 | int |
| 1667 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1668 | struct drm_file *file) |
| 1669 | { |
| 1670 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1671 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 1672 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
| 1673 | } |
| 1674 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1675 | /* Immediately discard the backing storage */ |
| 1676 | static void |
| 1677 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1678 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1679 | struct inode *inode; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1680 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1681 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1682 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 1683 | if (obj->base.filp == NULL) |
| 1684 | return; |
| 1685 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1686 | /* Our goal here is to return as much of the memory as |
| 1687 | * is possible back to the system as we are called from OOM. |
| 1688 | * To do this we must instruct the shmfs to drop all of its |
| 1689 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1690 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1691 | inode = file_inode(obj->base.filp); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1692 | shmem_truncate_range(inode, 0, (loff_t)-1); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 1693 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1694 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1695 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1696 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1697 | static inline int |
| 1698 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
| 1699 | { |
| 1700 | return obj->madv == I915_MADV_DONTNEED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1701 | } |
| 1702 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1703 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1704 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1706 | struct sg_page_iter sg_iter; |
| 1707 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1708 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1709 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1710 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1711 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 1712 | if (ret) { |
| 1713 | /* In the event of a disaster, abandon all caches and |
| 1714 | * hope for the best. |
| 1715 | */ |
| 1716 | WARN_ON(ret != -EIO); |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1717 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1718 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 1719 | } |
| 1720 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 1721 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1722 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1723 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1724 | if (obj->madv == I915_MADV_DONTNEED) |
| 1725 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1726 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1727 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1728 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1729 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1730 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1731 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1732 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1733 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1734 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1735 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1736 | page_cache_release(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1737 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1738 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1739 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1740 | sg_free_table(obj->pages); |
| 1741 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1742 | } |
| 1743 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 1744 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1745 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 1746 | { |
| 1747 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1748 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1749 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1750 | return 0; |
| 1751 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1752 | if (obj->pages_pin_count) |
| 1753 | return -EBUSY; |
| 1754 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 1755 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 1756 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1757 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 1758 | * array, hence protect them from being reaped by removing them from gtt |
| 1759 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1760 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 1761 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1762 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1763 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1764 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1765 | if (i915_gem_object_is_purgeable(obj)) |
| 1766 | i915_gem_object_truncate(obj); |
| 1767 | |
| 1768 | return 0; |
| 1769 | } |
| 1770 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1771 | static unsigned long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1772 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
| 1773 | bool purgeable_only) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1774 | { |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1775 | struct list_head still_bound_list; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1776 | struct drm_i915_gem_object *obj, *next; |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1777 | unsigned long count = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1778 | |
| 1779 | list_for_each_entry_safe(obj, next, |
| 1780 | &dev_priv->mm.unbound_list, |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1781 | global_list) { |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1782 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1783 | i915_gem_object_put_pages(obj) == 0) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1784 | count += obj->base.size >> PAGE_SHIFT; |
| 1785 | if (count >= target) |
| 1786 | return count; |
| 1787 | } |
| 1788 | } |
| 1789 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1790 | /* |
| 1791 | * As we may completely rewrite the bound list whilst unbinding |
| 1792 | * (due to retiring requests) we have to strictly process only |
| 1793 | * one element of the list at the time, and recheck the list |
| 1794 | * on every iteration. |
| 1795 | */ |
| 1796 | INIT_LIST_HEAD(&still_bound_list); |
| 1797 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1798 | struct i915_vma *vma, *v; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1799 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1800 | obj = list_first_entry(&dev_priv->mm.bound_list, |
| 1801 | typeof(*obj), global_list); |
| 1802 | list_move_tail(&obj->global_list, &still_bound_list); |
| 1803 | |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1804 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
| 1805 | continue; |
| 1806 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1807 | /* |
| 1808 | * Hold a reference whilst we unbind this object, as we may |
| 1809 | * end up waiting for and retiring requests. This might |
| 1810 | * release the final reference (held by the active list) |
| 1811 | * and result in the object being freed from under us. |
| 1812 | * in this object being freed. |
| 1813 | * |
| 1814 | * Note 1: Shrinking the bound list is special since only active |
| 1815 | * (and hence bound objects) can contain such limbo objects, so |
| 1816 | * we don't need special tricks for shrinking the unbound list. |
| 1817 | * The only other place where we have to be careful with active |
| 1818 | * objects suddenly disappearing due to retiring requests is the |
| 1819 | * eviction code. |
| 1820 | * |
| 1821 | * Note 2: Even though the bound list doesn't hold a reference |
| 1822 | * to the object we can safely grab one here: The final object |
| 1823 | * unreferencing and the bound_list are both protected by the |
| 1824 | * dev->struct_mutex and so we won't ever be able to observe an |
| 1825 | * object on the bound_list with a reference count equals 0. |
| 1826 | */ |
| 1827 | drm_gem_object_reference(&obj->base); |
| 1828 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 1829 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
| 1830 | if (i915_vma_unbind(vma)) |
| 1831 | break; |
Ben Widawsky | 80dcfdb | 2013-07-31 17:00:01 -0700 | [diff] [blame] | 1832 | |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1833 | if (i915_gem_object_put_pages(obj) == 0) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1834 | count += obj->base.size >> PAGE_SHIFT; |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1835 | |
| 1836 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1837 | } |
Chris Wilson | 57094f8 | 2013-09-04 10:45:50 +0100 | [diff] [blame] | 1838 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1839 | |
| 1840 | return count; |
| 1841 | } |
| 1842 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1843 | static unsigned long |
Daniel Vetter | 93927ca | 2013-01-10 18:03:00 +0100 | [diff] [blame] | 1844 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
| 1845 | { |
| 1846 | return __i915_gem_shrink(dev_priv, target, true); |
| 1847 | } |
| 1848 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1849 | static unsigned long |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1850 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
| 1851 | { |
| 1852 | struct drm_i915_gem_object *obj, *next; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1853 | long freed = 0; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1854 | |
| 1855 | i915_gem_evict_everything(dev_priv->dev); |
| 1856 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1857 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1858 | global_list) { |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 1859 | if (i915_gem_object_put_pages(obj) == 0) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1860 | freed += obj->base.size >> PAGE_SHIFT; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 1861 | } |
| 1862 | return freed; |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 1863 | } |
| 1864 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1865 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1866 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1867 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1868 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1869 | int page_count, i; |
| 1870 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1871 | struct sg_table *st; |
| 1872 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1873 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1874 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1875 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1876 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1877 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1878 | /* Assert that the object is not currently in any GPU domain. As it |
| 1879 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 1880 | * a GPU cache |
| 1881 | */ |
| 1882 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 1883 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 1884 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1885 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 1886 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1887 | return -ENOMEM; |
| 1888 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1889 | page_count = obj->base.size / PAGE_SIZE; |
| 1890 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1891 | kfree(st); |
| 1892 | return -ENOMEM; |
| 1893 | } |
| 1894 | |
| 1895 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1896 | * at this point until we release them. |
| 1897 | * |
| 1898 | * Fail silently without starting the shrinker |
| 1899 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 1900 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1901 | gfp = mapping_gfp_mask(mapping); |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1902 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1903 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1904 | sg = st->sgl; |
| 1905 | st->nents = 0; |
| 1906 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1907 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1908 | if (IS_ERR(page)) { |
| 1909 | i915_gem_purge(dev_priv, page_count); |
| 1910 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1911 | } |
| 1912 | if (IS_ERR(page)) { |
| 1913 | /* We've tried hard to allocate the memory by reaping |
| 1914 | * our own buffer, now let the real VM do its job and |
| 1915 | * go down in flames if truly OOM. |
| 1916 | */ |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1917 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1918 | gfp |= __GFP_IO | __GFP_WAIT; |
| 1919 | |
| 1920 | i915_gem_shrink_all(dev_priv); |
| 1921 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 1922 | if (IS_ERR(page)) |
| 1923 | goto err_pages; |
| 1924 | |
Linus Torvalds | caf4919 | 2012-12-10 10:51:16 -0800 | [diff] [blame] | 1925 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 1926 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
| 1927 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1928 | #ifdef CONFIG_SWIOTLB |
| 1929 | if (swiotlb_nr_tbl()) { |
| 1930 | st->nents++; |
| 1931 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1932 | sg = sg_next(sg); |
| 1933 | continue; |
| 1934 | } |
| 1935 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1936 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 1937 | if (i) |
| 1938 | sg = sg_next(sg); |
| 1939 | st->nents++; |
| 1940 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 1941 | } else { |
| 1942 | sg->length += PAGE_SIZE; |
| 1943 | } |
| 1944 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 1945 | |
| 1946 | /* Check that the i965g/gm workaround works. */ |
| 1947 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1948 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 1949 | #ifdef CONFIG_SWIOTLB |
| 1950 | if (!swiotlb_nr_tbl()) |
| 1951 | #endif |
| 1952 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 1953 | obj->pages = st; |
| 1954 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 1956 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1957 | |
| 1958 | return 0; |
| 1959 | |
| 1960 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 1961 | sg_mark_end(sg); |
| 1962 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1963 | page_cache_release(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1964 | sg_free_table(st); |
| 1965 | kfree(st); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1966 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1967 | } |
| 1968 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1969 | /* Ensure that the associated pages are gathered from the backing storage |
| 1970 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 1971 | * multiple times before they are released by a single call to |
| 1972 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 1973 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 1974 | * or as the object is itself released. |
| 1975 | */ |
| 1976 | int |
| 1977 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 1978 | { |
| 1979 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 1980 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 1981 | int ret; |
| 1982 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 1983 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1984 | return 0; |
| 1985 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 1986 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 1987 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 1988 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 1989 | } |
| 1990 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1991 | BUG_ON(obj->pages_pin_count); |
| 1992 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1993 | ret = ops->get_pages(obj); |
| 1994 | if (ret) |
| 1995 | return ret; |
| 1996 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1997 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1998 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1999 | } |
| 2000 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2001 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2002 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2003 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2004 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2005 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2006 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2007 | u32 seqno = intel_ring_get_seqno(ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 2008 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2009 | BUG_ON(ring == NULL); |
Chris Wilson | 02978ff | 2013-07-09 09:22:39 +0100 | [diff] [blame] | 2010 | if (obj->ring != ring && obj->last_write_seqno) { |
| 2011 | /* Keep the seqno relative to the current ring */ |
| 2012 | obj->last_write_seqno = seqno; |
| 2013 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2014 | obj->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2015 | |
| 2016 | /* Add a reference if we're newly entering the active list. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2017 | if (!obj->active) { |
| 2018 | drm_gem_object_reference(&obj->base); |
| 2019 | obj->active = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2020 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2021 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2022 | list_move_tail(&obj->ring_list, &ring->active_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2023 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2024 | obj->last_read_seqno = seqno; |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 2025 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2026 | if (obj->fenced_gpu_access) { |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2027 | obj->last_fenced_seqno = seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2028 | |
Chris Wilson | 7dd4906 | 2012-03-21 10:48:18 +0000 | [diff] [blame] | 2029 | /* Bump MRU to take account of the delayed flush */ |
| 2030 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2031 | struct drm_i915_fence_reg *reg; |
| 2032 | |
| 2033 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
| 2034 | list_move_tail(®->lru_list, |
| 2035 | &dev_priv->mm.fence_list); |
| 2036 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2037 | } |
| 2038 | } |
| 2039 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2040 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2041 | struct intel_ring_buffer *ring) |
| 2042 | { |
| 2043 | list_move_tail(&vma->mm_list, &vma->vm->active_list); |
| 2044 | return i915_gem_object_move_to_active(vma->obj, ring); |
| 2045 | } |
| 2046 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2047 | static void |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2048 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
| 2049 | { |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2050 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2051 | struct i915_address_space *vm; |
| 2052 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2053 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2054 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2055 | BUG_ON(!obj->active); |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2056 | |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2057 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2058 | vma = i915_gem_obj_to_vma(obj, vm); |
| 2059 | if (vma && !list_empty(&vma->mm_list)) |
| 2060 | list_move_tail(&vma->mm_list, &vm->inactive_list); |
| 2061 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2062 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2063 | list_del_init(&obj->ring_list); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2064 | obj->ring = NULL; |
| 2065 | |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2066 | obj->last_read_seqno = 0; |
| 2067 | obj->last_write_seqno = 0; |
| 2068 | obj->base.write_domain = 0; |
| 2069 | |
| 2070 | obj->last_fenced_seqno = 0; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2071 | obj->fenced_gpu_access = false; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2072 | |
| 2073 | obj->active = 0; |
| 2074 | drm_gem_object_unreference(&obj->base); |
| 2075 | |
| 2076 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 2077 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2078 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2079 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2080 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2081 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2082 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2083 | struct intel_ring_buffer *ring; |
| 2084 | int ret, i, j; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2085 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2086 | /* Carefully retire all requests without writing to the rings */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2087 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2088 | ret = intel_ring_idle(ring); |
| 2089 | if (ret) |
| 2090 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2091 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2092 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2093 | |
| 2094 | /* Finally reset hw state */ |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2095 | for_each_ring(ring, dev_priv, i) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2096 | intel_ring_init_seqno(ring, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2097 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2098 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
| 2099 | ring->sync_seqno[j] = 0; |
| 2100 | } |
| 2101 | |
| 2102 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2103 | } |
| 2104 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2105 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2106 | { |
| 2107 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2108 | int ret; |
| 2109 | |
| 2110 | if (seqno == 0) |
| 2111 | return -EINVAL; |
| 2112 | |
| 2113 | /* HWS page needs to be set less than what we |
| 2114 | * will inject to ring |
| 2115 | */ |
| 2116 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2117 | if (ret) |
| 2118 | return ret; |
| 2119 | |
| 2120 | /* Carefully set the last_seqno value so that wrap |
| 2121 | * detection still works |
| 2122 | */ |
| 2123 | dev_priv->next_seqno = seqno; |
| 2124 | dev_priv->last_seqno = seqno - 1; |
| 2125 | if (dev_priv->last_seqno == 0) |
| 2126 | dev_priv->last_seqno--; |
| 2127 | |
| 2128 | return 0; |
| 2129 | } |
| 2130 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2131 | int |
| 2132 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2133 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2134 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2135 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2136 | /* reserve 0 for non-seqno */ |
| 2137 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2138 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2139 | if (ret) |
| 2140 | return ret; |
| 2141 | |
| 2142 | dev_priv->next_seqno = 1; |
| 2143 | } |
| 2144 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2145 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2146 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2147 | } |
| 2148 | |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2149 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2150 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2151 | struct drm_i915_gem_object *obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2152 | u32 *out_seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2153 | { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2154 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2155 | struct drm_i915_gem_request *request; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2156 | u32 request_ring_position, request_start; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2157 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2158 | int ret; |
| 2159 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2160 | request_start = intel_ring_get_tail(ring); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2161 | /* |
| 2162 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2163 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2164 | * things up similar to emitting the lazy request. The difference here |
| 2165 | * is that the flush _must_ happen before the next request, no matter |
| 2166 | * what. |
| 2167 | */ |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 2168 | ret = intel_ring_flush_all_caches(ring); |
| 2169 | if (ret) |
| 2170 | return ret; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2171 | |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2172 | request = ring->preallocated_lazy_request; |
| 2173 | if (WARN_ON(request == NULL)) |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2174 | return -ENOMEM; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2175 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2176 | /* Record the position of the start of the request so that |
| 2177 | * should we detect the updated seqno part-way through the |
| 2178 | * GPU processing the request, we never over-estimate the |
| 2179 | * position of the head. |
| 2180 | */ |
| 2181 | request_ring_position = intel_ring_get_tail(ring); |
| 2182 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2183 | ret = ring->add_request(ring); |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2184 | if (ret) |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2185 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2186 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2187 | request->seqno = intel_ring_get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2188 | request->ring = ring; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2189 | request->head = request_start; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2190 | request->tail = request_ring_position; |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2191 | |
| 2192 | /* Whilst this request exists, batch_obj will be on the |
| 2193 | * active_list, and so will hold the active reference. Only when this |
| 2194 | * request is retired will the the batch_obj be moved onto the |
| 2195 | * inactive_list and lose its active reference. Hence we do not need |
| 2196 | * to explicitly hold another reference here. |
| 2197 | */ |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2198 | request->batch_obj = obj; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2199 | |
Chris Wilson | 9a7e0c2 | 2013-08-26 19:50:54 -0300 | [diff] [blame] | 2200 | /* Hold a reference to the current context so that we can inspect |
| 2201 | * it later in case a hangcheck error event fires. |
| 2202 | */ |
| 2203 | request->ctx = ring->last_context; |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2204 | if (request->ctx) |
| 2205 | i915_gem_context_reference(request->ctx); |
| 2206 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2207 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2208 | was_empty = list_empty(&ring->request_list); |
| 2209 | list_add_tail(&request->list, &ring->request_list); |
Chris Wilson | 3bb73ab | 2012-07-20 12:40:59 +0100 | [diff] [blame] | 2210 | request->file_priv = NULL; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2211 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2212 | if (file) { |
| 2213 | struct drm_i915_file_private *file_priv = file->driver_priv; |
| 2214 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2215 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2216 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2217 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2218 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2219 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2220 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2221 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2222 | trace_i915_gem_request_add(ring, request->seqno); |
Chris Wilson | 1823521 | 2013-09-04 10:45:51 +0100 | [diff] [blame] | 2223 | ring->outstanding_lazy_seqno = 0; |
Chris Wilson | 3c0e234 | 2013-09-04 10:45:52 +0100 | [diff] [blame] | 2224 | ring->preallocated_lazy_request = NULL; |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2225 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 2226 | if (!dev_priv->ums.mm_suspended) { |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2227 | i915_queue_hangcheck(ring->dev); |
| 2228 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2229 | if (was_empty) { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2230 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 2231 | queue_delayed_work(dev_priv->wq, |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2232 | &dev_priv->mm.retire_work, |
| 2233 | round_jiffies_up_relative(HZ)); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 2234 | intel_mark_busy(dev_priv->dev); |
| 2235 | } |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 2236 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2237 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 2238 | if (out_seqno) |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2239 | *out_seqno = request->seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2240 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2241 | } |
| 2242 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2243 | static inline void |
| 2244 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2245 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2246 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2247 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2248 | if (!file_priv) |
| 2249 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2250 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2251 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2252 | list_del(&request->client_list); |
| 2253 | request->file_priv = NULL; |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 2254 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2255 | } |
| 2256 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2257 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2258 | const struct i915_hw_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2259 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2260 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2261 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2262 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2263 | |
| 2264 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2265 | return true; |
| 2266 | |
| 2267 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2268 | if (dev_priv->gpu_error.stop_rings == 0 && |
| 2269 | i915_gem_context_is_default(ctx)) { |
| 2270 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
| 2271 | } else { |
| 2272 | DRM_DEBUG("context hanging too fast, banning!\n"); |
| 2273 | } |
| 2274 | |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2275 | return true; |
| 2276 | } |
| 2277 | |
| 2278 | return false; |
| 2279 | } |
| 2280 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2281 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
| 2282 | struct i915_hw_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2283 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2284 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2285 | struct i915_ctx_hang_stats *hs; |
| 2286 | |
| 2287 | if (WARN_ON(!ctx)) |
| 2288 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2289 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2290 | hs = &ctx->hang_stats; |
| 2291 | |
| 2292 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2293 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2294 | hs->batch_active++; |
| 2295 | hs->guilty_ts = get_seconds(); |
| 2296 | } else { |
| 2297 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2298 | } |
| 2299 | } |
| 2300 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2301 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
| 2302 | { |
| 2303 | list_del(&request->list); |
| 2304 | i915_gem_request_remove_from_client(request); |
| 2305 | |
| 2306 | if (request->ctx) |
| 2307 | i915_gem_context_unreference(request->ctx); |
| 2308 | |
| 2309 | kfree(request); |
| 2310 | } |
| 2311 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2312 | static struct drm_i915_gem_request * |
| 2313 | i915_gem_find_first_non_complete(struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2314 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2315 | struct drm_i915_gem_request *request; |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2316 | const u32 completed_seqno = ring->get_seqno(ring, false); |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2317 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2318 | list_for_each_entry(request, &ring->request_list, list) { |
| 2319 | if (i915_seqno_passed(completed_seqno, request->seqno)) |
| 2320 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2321 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2322 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2323 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2324 | |
| 2325 | return NULL; |
| 2326 | } |
| 2327 | |
| 2328 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, |
| 2329 | struct intel_ring_buffer *ring) |
| 2330 | { |
| 2331 | struct drm_i915_gem_request *request; |
| 2332 | bool ring_hung; |
| 2333 | |
| 2334 | request = i915_gem_find_first_non_complete(ring); |
| 2335 | |
| 2336 | if (request == NULL) |
| 2337 | return; |
| 2338 | |
| 2339 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
| 2340 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2341 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2342 | |
| 2343 | list_for_each_entry_continue(request, &ring->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2344 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2345 | } |
| 2346 | |
| 2347 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
| 2348 | struct intel_ring_buffer *ring) |
| 2349 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2350 | while (!list_empty(&ring->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2351 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2352 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2353 | obj = list_first_entry(&ring->active_list, |
| 2354 | struct drm_i915_gem_object, |
| 2355 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2356 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2357 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2358 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2359 | |
| 2360 | /* |
| 2361 | * We must free the requests after all the corresponding objects have |
| 2362 | * been moved off active lists. Which is the same order as the normal |
| 2363 | * retire_requests function does. This is important if object hold |
| 2364 | * implicit references on things like e.g. ppgtt address spaces through |
| 2365 | * the request. |
| 2366 | */ |
| 2367 | while (!list_empty(&ring->request_list)) { |
| 2368 | struct drm_i915_gem_request *request; |
| 2369 | |
| 2370 | request = list_first_entry(&ring->request_list, |
| 2371 | struct drm_i915_gem_request, |
| 2372 | list); |
| 2373 | |
| 2374 | i915_gem_free_request(request); |
| 2375 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2376 | } |
| 2377 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2378 | void i915_gem_restore_fences(struct drm_device *dev) |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2379 | { |
| 2380 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2381 | int i; |
| 2382 | |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 2383 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2384 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
Chris Wilson | 7d2cb39 | 2010-11-27 17:38:29 +0000 | [diff] [blame] | 2385 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2386 | /* |
| 2387 | * Commit delayed tiling changes if we have an object still |
| 2388 | * attached to the fence, otherwise just clear the fence. |
| 2389 | */ |
| 2390 | if (reg->obj) { |
| 2391 | i915_gem_object_update_fence(reg->obj, reg, |
| 2392 | reg->obj->tiling_mode); |
| 2393 | } else { |
| 2394 | i915_gem_write_fence(dev, i, NULL); |
| 2395 | } |
Chris Wilson | 312817a | 2010-11-22 11:50:11 +0000 | [diff] [blame] | 2396 | } |
| 2397 | } |
| 2398 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2399 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2400 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2401 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2402 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2403 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2404 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2405 | /* |
| 2406 | * Before we free the objects from the requests, we need to inspect |
| 2407 | * them for finding the guilty party. As the requests only borrow |
| 2408 | * their reference to the objects, the inspection must be done first. |
| 2409 | */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2410 | for_each_ring(ring, dev_priv, i) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2411 | i915_gem_reset_ring_status(dev_priv, ring); |
| 2412 | |
| 2413 | for_each_ring(ring, dev_priv, i) |
| 2414 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2415 | |
Ben Widawsky | 3d57e5b | 2013-10-14 10:01:36 -0700 | [diff] [blame] | 2416 | i915_gem_cleanup_ringbuffer(dev); |
| 2417 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2418 | i915_gem_context_reset(dev); |
| 2419 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2420 | i915_gem_restore_fences(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2421 | } |
| 2422 | |
| 2423 | /** |
| 2424 | * This function clears the request list as sequence numbers are passed. |
| 2425 | */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2426 | void |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2427 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2428 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2429 | uint32_t seqno; |
| 2430 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2431 | if (list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 2432 | return; |
| 2433 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2434 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2435 | |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 2436 | seqno = ring->get_seqno(ring, true); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2437 | |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2438 | /* Move any buffers on the active list that are no longer referenced |
| 2439 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2440 | * before we free the context associated with the requests. |
| 2441 | */ |
| 2442 | while (!list_empty(&ring->active_list)) { |
| 2443 | struct drm_i915_gem_object *obj; |
| 2444 | |
| 2445 | obj = list_first_entry(&ring->active_list, |
| 2446 | struct drm_i915_gem_object, |
| 2447 | ring_list); |
| 2448 | |
| 2449 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
| 2450 | break; |
| 2451 | |
| 2452 | i915_gem_object_move_to_inactive(obj); |
| 2453 | } |
| 2454 | |
| 2455 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2456 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2457 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2458 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2459 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2460 | struct drm_i915_gem_request, |
| 2461 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2462 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2463 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2464 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2465 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2466 | trace_i915_gem_request_retire(ring, request->seqno); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2467 | /* We know the GPU must have read the request to have |
| 2468 | * sent us the seqno + interrupt, so use the position |
| 2469 | * of tail of the request to update the last known position |
| 2470 | * of the GPU head. |
| 2471 | */ |
| 2472 | ring->last_retired_head = request->tail; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2473 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2474 | i915_gem_free_request(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2475 | } |
| 2476 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2477 | if (unlikely(ring->trace_irq_seqno && |
| 2478 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2479 | ring->irq_put(ring); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2480 | ring->trace_irq_seqno = 0; |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2481 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2482 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2483 | WARN_ON(i915_verify_lists(ring->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2484 | } |
| 2485 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2486 | bool |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2487 | i915_gem_retire_requests(struct drm_device *dev) |
| 2488 | { |
| 2489 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2490 | struct intel_ring_buffer *ring; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2491 | bool idle = true; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2492 | int i; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2493 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2494 | for_each_ring(ring, dev_priv, i) { |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2495 | i915_gem_retire_requests_ring(ring); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2496 | idle &= list_empty(&ring->request_list); |
| 2497 | } |
| 2498 | |
| 2499 | if (idle) |
| 2500 | mod_delayed_work(dev_priv->wq, |
| 2501 | &dev_priv->mm.idle_work, |
| 2502 | msecs_to_jiffies(100)); |
| 2503 | |
| 2504 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2505 | } |
| 2506 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2507 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2508 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2509 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2510 | struct drm_i915_private *dev_priv = |
| 2511 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 2512 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 2513 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2514 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2515 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2516 | idle = false; |
| 2517 | if (mutex_trylock(&dev->struct_mutex)) { |
| 2518 | idle = i915_gem_retire_requests(dev); |
| 2519 | mutex_unlock(&dev->struct_mutex); |
| 2520 | } |
| 2521 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 2522 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 2523 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2524 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2525 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2526 | static void |
| 2527 | i915_gem_idle_work_handler(struct work_struct *work) |
| 2528 | { |
| 2529 | struct drm_i915_private *dev_priv = |
| 2530 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2531 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2532 | intel_mark_idle(dev_priv->dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2533 | } |
| 2534 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2535 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2536 | * Ensures that an object will eventually get non-busy by flushing any required |
| 2537 | * write domains, emitting any outstanding lazy request and retiring and |
| 2538 | * completed requests. |
| 2539 | */ |
| 2540 | static int |
| 2541 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 2542 | { |
| 2543 | int ret; |
| 2544 | |
| 2545 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2546 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2547 | if (ret) |
| 2548 | return ret; |
| 2549 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2550 | i915_gem_retire_requests_ring(obj->ring); |
| 2551 | } |
| 2552 | |
| 2553 | return 0; |
| 2554 | } |
| 2555 | |
| 2556 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2557 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 2558 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 2559 | * |
| 2560 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 2561 | * the timeout parameter. |
| 2562 | * -ETIME: object is still busy after timeout |
| 2563 | * -ERESTARTSYS: signal interrupted the wait |
| 2564 | * -ENONENT: object doesn't exist |
| 2565 | * Also possible, but rare: |
| 2566 | * -EAGAIN: GPU wedged |
| 2567 | * -ENOMEM: damn |
| 2568 | * -ENODEV: Internal IRQ fail |
| 2569 | * -E?: The add request failed |
| 2570 | * |
| 2571 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 2572 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 2573 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 2574 | * without holding struct_mutex the object may become re-busied before this |
| 2575 | * function completes. A similar but shorter * race condition exists in the busy |
| 2576 | * ioctl |
| 2577 | */ |
| 2578 | int |
| 2579 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 2580 | { |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2581 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2582 | struct drm_i915_gem_wait *args = data; |
| 2583 | struct drm_i915_gem_object *obj; |
| 2584 | struct intel_ring_buffer *ring = NULL; |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2585 | struct timespec timeout_stack, *timeout = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2586 | unsigned reset_counter; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2587 | u32 seqno = 0; |
| 2588 | int ret = 0; |
| 2589 | |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2590 | if (args->timeout_ns >= 0) { |
| 2591 | timeout_stack = ns_to_timespec(args->timeout_ns); |
| 2592 | timeout = &timeout_stack; |
| 2593 | } |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2594 | |
| 2595 | ret = i915_mutex_lock_interruptible(dev); |
| 2596 | if (ret) |
| 2597 | return ret; |
| 2598 | |
| 2599 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 2600 | if (&obj->base == NULL) { |
| 2601 | mutex_unlock(&dev->struct_mutex); |
| 2602 | return -ENOENT; |
| 2603 | } |
| 2604 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 2605 | /* Need to make sure the object gets inactive eventually. */ |
| 2606 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2607 | if (ret) |
| 2608 | goto out; |
| 2609 | |
| 2610 | if (obj->active) { |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2611 | seqno = obj->last_read_seqno; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2612 | ring = obj->ring; |
| 2613 | } |
| 2614 | |
| 2615 | if (seqno == 0) |
| 2616 | goto out; |
| 2617 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2618 | /* Do this after OLR check to make sure we make forward progress polling |
| 2619 | * on this IOCTL with a 0 timeout (like busy ioctl) |
| 2620 | */ |
| 2621 | if (!args->timeout_ns) { |
| 2622 | ret = -ETIME; |
| 2623 | goto out; |
| 2624 | } |
| 2625 | |
| 2626 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 2627 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2628 | mutex_unlock(&dev->struct_mutex); |
| 2629 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2630 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
Chris Wilson | 4f42f4e | 2013-04-26 16:22:46 +0300 | [diff] [blame] | 2631 | if (timeout) |
Ben Widawsky | eac1f14 | 2012-06-05 15:24:24 -0700 | [diff] [blame] | 2632 | args->timeout_ns = timespec_to_ns(timeout); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2633 | return ret; |
| 2634 | |
| 2635 | out: |
| 2636 | drm_gem_object_unreference(&obj->base); |
| 2637 | mutex_unlock(&dev->struct_mutex); |
| 2638 | return ret; |
| 2639 | } |
| 2640 | |
| 2641 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2642 | * i915_gem_object_sync - sync an object to a ring. |
| 2643 | * |
| 2644 | * @obj: object which may be in use on another ring. |
| 2645 | * @to: ring we wish to use the object on. May be NULL. |
| 2646 | * |
| 2647 | * This code is meant to abstract object synchronization with the GPU. |
| 2648 | * Calling with NULL implies synchronizing the object with the CPU |
| 2649 | * rather than a particular GPU ring. |
| 2650 | * |
| 2651 | * Returns 0 if successful, else propagates up the lower layer error. |
| 2652 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2653 | int |
| 2654 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2655 | struct intel_ring_buffer *to) |
| 2656 | { |
| 2657 | struct intel_ring_buffer *from = obj->ring; |
| 2658 | u32 seqno; |
| 2659 | int ret, idx; |
| 2660 | |
| 2661 | if (from == NULL || to == from) |
| 2662 | return 0; |
| 2663 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 2664 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2665 | return i915_gem_object_wait_rendering(obj, false); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2666 | |
| 2667 | idx = intel_ring_sync_index(from, to); |
| 2668 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 2669 | seqno = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2670 | if (seqno <= from->sync_seqno[idx]) |
| 2671 | return 0; |
| 2672 | |
Ben Widawsky | b4aca01 | 2012-04-25 20:50:12 -0700 | [diff] [blame] | 2673 | ret = i915_gem_check_olr(obj->ring, seqno); |
| 2674 | if (ret) |
| 2675 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2676 | |
Chris Wilson | b52b89d | 2013-09-25 11:43:28 +0100 | [diff] [blame] | 2677 | trace_i915_gem_ring_sync_to(from, to, seqno); |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 2678 | ret = to->sync_to(to, from, seqno); |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2679 | if (!ret) |
Mika Kuoppala | 7b01e26 | 2012-11-28 17:18:45 +0200 | [diff] [blame] | 2680 | /* We use last_read_seqno because sync_to() |
| 2681 | * might have just caused seqno wrap under |
| 2682 | * the radar. |
| 2683 | */ |
| 2684 | from->sync_seqno[idx] = obj->last_read_seqno; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2685 | |
Ben Widawsky | e3a5a22 | 2012-04-11 11:18:20 -0700 | [diff] [blame] | 2686 | return ret; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2687 | } |
| 2688 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2689 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 2690 | { |
| 2691 | u32 old_write_domain, old_read_domains; |
| 2692 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2693 | /* Force a pagefault for domain tracking on next user access */ |
| 2694 | i915_gem_release_mmap(obj); |
| 2695 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 2696 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 2697 | return; |
| 2698 | |
Chris Wilson | 97c809fd | 2012-10-09 19:24:38 +0100 | [diff] [blame] | 2699 | /* Wait for any direct GTT access to complete */ |
| 2700 | mb(); |
| 2701 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2702 | old_read_domains = obj->base.read_domains; |
| 2703 | old_write_domain = obj->base.write_domain; |
| 2704 | |
| 2705 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 2706 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 2707 | |
| 2708 | trace_i915_gem_object_change_domain(obj, |
| 2709 | old_read_domains, |
| 2710 | old_write_domain); |
| 2711 | } |
| 2712 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2713 | int i915_vma_unbind(struct i915_vma *vma) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2714 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2715 | struct drm_i915_gem_object *obj = vma->obj; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2716 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2717 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2718 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2719 | if (list_empty(&vma->vma_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2720 | return 0; |
| 2721 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 2722 | if (!drm_mm_node_allocated(&vma->node)) { |
| 2723 | i915_gem_vma_destroy(vma); |
| 2724 | |
| 2725 | return 0; |
| 2726 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 2727 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2728 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 2729 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2730 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 2731 | BUG_ON(obj->pages == NULL); |
| 2732 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2733 | ret = i915_gem_object_finish_gpu(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2734 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2735 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2736 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2737 | * should be safe and we need to cleanup or else we might |
| 2738 | * cause memory corruption through use-after-free. |
| 2739 | */ |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2740 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 2741 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2742 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2743 | /* release the fence reg _after_ flushing */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2744 | ret = i915_gem_object_put_fence(obj); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 2745 | if (ret) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2746 | return ret; |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2747 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2748 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 2749 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2750 | vma->unbind_vma(vma); |
| 2751 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 2752 | i915_gem_gtt_finish_object(obj); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 2753 | |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 2754 | list_del(&vma->mm_list); |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 2755 | /* Avoid an unnecessary call to unbind on rebind. */ |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 2756 | if (i915_is_ggtt(vma->vm)) |
| 2757 | obj->map_and_fenceable = true; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2758 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2759 | drm_mm_remove_node(&vma->node); |
| 2760 | i915_gem_vma_destroy(vma); |
| 2761 | |
| 2762 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 2763 | * no more VMAs exist. */ |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2764 | if (list_empty(&obj->vma_list)) |
| 2765 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2766 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 2767 | /* And finally now the object is completely decoupled from this vma, |
| 2768 | * we can drop its hold on the backing storage and allow it to be |
| 2769 | * reaped by the shrinker. |
| 2770 | */ |
| 2771 | i915_gem_object_unpin_pages(obj); |
| 2772 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 2773 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2774 | } |
| 2775 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2776 | /** |
| 2777 | * Unbinds an object from the global GTT aperture. |
| 2778 | */ |
| 2779 | int |
| 2780 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
| 2781 | { |
| 2782 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2783 | struct i915_address_space *ggtt = &dev_priv->gtt.base; |
| 2784 | |
Dan Carpenter | 58e73e1 | 2013-08-09 12:44:11 +0300 | [diff] [blame] | 2785 | if (!i915_gem_obj_ggtt_bound(obj)) |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2786 | return 0; |
| 2787 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2788 | if (i915_gem_obj_to_ggtt(obj)->pin_count) |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2789 | return -EBUSY; |
| 2790 | |
| 2791 | BUG_ON(obj->pages == NULL); |
| 2792 | |
| 2793 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); |
| 2794 | } |
| 2795 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2796 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2797 | { |
| 2798 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2799 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2800 | int ret, i; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2801 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2802 | /* Flush everything onto the inactive list. */ |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 2803 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 2804 | ret = i915_switch_context(ring, NULL, ring->default_context); |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 2805 | if (ret) |
| 2806 | return ret; |
| 2807 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 2808 | ret = intel_ring_idle(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 2809 | if (ret) |
| 2810 | return ret; |
| 2811 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2812 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2813 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2814 | } |
| 2815 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2816 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
| 2817 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2818 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2819 | drm_i915_private_t *dev_priv = dev->dev_private; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2820 | int fence_reg; |
| 2821 | int fence_pitch_shift; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2822 | |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2823 | if (INTEL_INFO(dev)->gen >= 6) { |
| 2824 | fence_reg = FENCE_REG_SANDYBRIDGE_0; |
| 2825 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2826 | } else { |
| 2827 | fence_reg = FENCE_REG_965_0; |
| 2828 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; |
| 2829 | } |
| 2830 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2831 | fence_reg += reg * 8; |
| 2832 | |
| 2833 | /* To w/a incoherency with non-atomic 64-bit register updates, |
| 2834 | * we split the 64-bit update into two 32-bit writes. In order |
| 2835 | * for a partial fence not to be evaluated between writes, we |
| 2836 | * precede the update with write to turn off the fence register, |
| 2837 | * and only enable the fence as the last step. |
| 2838 | * |
| 2839 | * For extra levels of paranoia, we make sure each step lands |
| 2840 | * before applying the next step. |
| 2841 | */ |
| 2842 | I915_WRITE(fence_reg, 0); |
| 2843 | POSTING_READ(fence_reg); |
| 2844 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2845 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2846 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2847 | uint64_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2848 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2849 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2850 | 0xfffff000) << 32; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2851 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2852 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2853 | if (obj->tiling_mode == I915_TILING_Y) |
| 2854 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2855 | val |= I965_FENCE_REG_VALID; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2856 | |
Chris Wilson | d18b961 | 2013-07-10 13:36:23 +0100 | [diff] [blame] | 2857 | I915_WRITE(fence_reg + 4, val >> 32); |
| 2858 | POSTING_READ(fence_reg + 4); |
| 2859 | |
| 2860 | I915_WRITE(fence_reg + 0, val); |
| 2861 | POSTING_READ(fence_reg); |
| 2862 | } else { |
| 2863 | I915_WRITE(fence_reg + 4, 0); |
| 2864 | POSTING_READ(fence_reg + 4); |
| 2865 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2866 | } |
| 2867 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2868 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
| 2869 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2870 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2871 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2872 | u32 val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2873 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2874 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2875 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2876 | int pitch_val; |
| 2877 | int tile_width; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2878 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2879 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2880 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2881 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2882 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", |
| 2883 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2884 | |
| 2885 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
| 2886 | tile_width = 128; |
| 2887 | else |
| 2888 | tile_width = 512; |
| 2889 | |
| 2890 | /* Note: pitch better be a power of two tile widths */ |
| 2891 | pitch_val = obj->stride / tile_width; |
| 2892 | pitch_val = ffs(pitch_val) - 1; |
| 2893 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2894 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2895 | if (obj->tiling_mode == I915_TILING_Y) |
| 2896 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2897 | val |= I915_FENCE_SIZE_BITS(size); |
| 2898 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2899 | val |= I830_FENCE_REG_VALID; |
| 2900 | } else |
| 2901 | val = 0; |
| 2902 | |
| 2903 | if (reg < 8) |
| 2904 | reg = FENCE_REG_830_0 + reg * 4; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2905 | else |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2906 | reg = FENCE_REG_945_8 + (reg - 8) * 4; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2907 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2908 | I915_WRITE(reg, val); |
| 2909 | POSTING_READ(reg); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2910 | } |
| 2911 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2912 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
| 2913 | struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2914 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2915 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2916 | uint32_t val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2917 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2918 | if (obj) { |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2919 | u32 size = i915_gem_obj_ggtt_size(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2920 | uint32_t pitch_val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2921 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2922 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2923 | (size & -size) != size || |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2924 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
| 2925 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", |
| 2926 | i915_gem_obj_ggtt_offset(obj), size); |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2927 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2928 | pitch_val = obj->stride / 128; |
| 2929 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2930 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2931 | val = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2932 | if (obj->tiling_mode == I915_TILING_Y) |
| 2933 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2934 | val |= I830_FENCE_SIZE_BITS(size); |
| 2935 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2936 | val |= I830_FENCE_REG_VALID; |
| 2937 | } else |
| 2938 | val = 0; |
Daniel Vetter | c664278 | 2010-11-12 13:46:18 +0000 | [diff] [blame] | 2939 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2940 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
| 2941 | POSTING_READ(FENCE_REG_830_0 + reg * 4); |
| 2942 | } |
| 2943 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2944 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
| 2945 | { |
| 2946 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; |
| 2947 | } |
| 2948 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2949 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
| 2950 | struct drm_i915_gem_object *obj) |
| 2951 | { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2952 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2953 | |
| 2954 | /* Ensure that all CPU reads are completed before installing a fence |
| 2955 | * and all writes before removing the fence. |
| 2956 | */ |
| 2957 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) |
| 2958 | mb(); |
| 2959 | |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 2960 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
| 2961 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", |
| 2962 | obj->stride, obj->tiling_mode); |
| 2963 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2964 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | 5ab3133 | 2013-11-02 21:07:03 -0700 | [diff] [blame] | 2965 | case 8: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2966 | case 7: |
Imre Deak | 56c844e | 2013-01-07 21:47:34 +0200 | [diff] [blame] | 2967 | case 6: |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2968 | case 5: |
| 2969 | case 4: i965_write_fence_reg(dev, reg, obj); break; |
| 2970 | case 3: i915_write_fence_reg(dev, reg, obj); break; |
| 2971 | case 2: i830_write_fence_reg(dev, reg, obj); break; |
Ben Widawsky | 7dbf9d6 | 2012-12-18 10:31:22 -0800 | [diff] [blame] | 2972 | default: BUG(); |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 2973 | } |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 2974 | |
| 2975 | /* And similarly be paranoid that no direct access to this region |
| 2976 | * is reordered to before the fence is installed. |
| 2977 | */ |
| 2978 | if (i915_gem_object_needs_mb(obj)) |
| 2979 | mb(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2980 | } |
| 2981 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2982 | static inline int fence_number(struct drm_i915_private *dev_priv, |
| 2983 | struct drm_i915_fence_reg *fence) |
| 2984 | { |
| 2985 | return fence - dev_priv->fence_regs; |
| 2986 | } |
| 2987 | |
| 2988 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
| 2989 | struct drm_i915_fence_reg *fence, |
| 2990 | bool enable) |
| 2991 | { |
Chris Wilson | 2dc8aae | 2013-05-22 17:08:06 +0100 | [diff] [blame] | 2992 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2993 | int reg = fence_number(dev_priv, fence); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2994 | |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2995 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2996 | |
| 2997 | if (enable) { |
Chris Wilson | 46a0b63 | 2013-07-10 13:36:24 +0100 | [diff] [blame] | 2998 | obj->fence_reg = reg; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 2999 | fence->obj = obj; |
| 3000 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); |
| 3001 | } else { |
| 3002 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 3003 | fence->obj = NULL; |
| 3004 | list_del_init(&fence->lru_list); |
| 3005 | } |
Daniel Vetter | 94a335d | 2013-07-17 14:51:28 +0200 | [diff] [blame] | 3006 | obj->fence_dirty = false; |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3007 | } |
| 3008 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3009 | static int |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3010 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3011 | { |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 3012 | if (obj->last_fenced_seqno) { |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 3013 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
Chris Wilson | 1899184 | 2012-04-17 15:31:29 +0100 | [diff] [blame] | 3014 | if (ret) |
| 3015 | return ret; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3016 | |
| 3017 | obj->last_fenced_seqno = 0; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3018 | } |
| 3019 | |
Chris Wilson | 86d5bc3 | 2012-07-20 12:41:04 +0100 | [diff] [blame] | 3020 | obj->fenced_gpu_access = false; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3021 | return 0; |
| 3022 | } |
| 3023 | |
| 3024 | int |
| 3025 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) |
| 3026 | { |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3027 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3028 | struct drm_i915_fence_reg *fence; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3029 | int ret; |
| 3030 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3031 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3032 | if (ret) |
| 3033 | return ret; |
| 3034 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3035 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
| 3036 | return 0; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3037 | |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3038 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
| 3039 | |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 3040 | i915_gem_object_fence_lost(obj); |
Chris Wilson | f9c513e | 2013-03-26 11:29:27 +0000 | [diff] [blame] | 3041 | i915_gem_object_update_fence(obj, fence, false); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3042 | |
| 3043 | return 0; |
| 3044 | } |
| 3045 | |
| 3046 | static struct drm_i915_fence_reg * |
Chris Wilson | a360bb1 | 2012-04-17 15:31:25 +0100 | [diff] [blame] | 3047 | i915_find_fence_reg(struct drm_device *dev) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3048 | { |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3049 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3050 | struct drm_i915_fence_reg *reg, *avail; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3051 | int i; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3052 | |
| 3053 | /* First try to find a free reg */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3054 | avail = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3055 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 3056 | reg = &dev_priv->fence_regs[i]; |
| 3057 | if (!reg->obj) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3058 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3059 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3060 | if (!reg->pin_count) |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3061 | avail = reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3062 | } |
| 3063 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3064 | if (avail == NULL) |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3065 | goto deadlock; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3066 | |
| 3067 | /* None available, try to steal one or wait for a user to finish */ |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3068 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 3069 | if (reg->pin_count) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3070 | continue; |
| 3071 | |
Chris Wilson | 8fe301a | 2012-04-17 15:31:28 +0100 | [diff] [blame] | 3072 | return reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3073 | } |
| 3074 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3075 | deadlock: |
| 3076 | /* Wait for completion of pending flips which consume fences */ |
| 3077 | if (intel_has_pending_fb_unpin(dev)) |
| 3078 | return ERR_PTR(-EAGAIN); |
| 3079 | |
| 3080 | return ERR_PTR(-EDEADLK); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3081 | } |
| 3082 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3083 | /** |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3084 | * i915_gem_object_get_fence - set up fencing for an object |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3085 | * @obj: object to map through a fence reg |
| 3086 | * |
| 3087 | * When mapping objects through the GTT, userspace wants to be able to write |
| 3088 | * to them without having to worry about swizzling if the object is tiled. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3089 | * This function walks the fence regs looking for a free one for @obj, |
| 3090 | * stealing one if it can't find any. |
| 3091 | * |
| 3092 | * It then sets up the reg based on the object's properties: address, pitch |
| 3093 | * and tiling format. |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3094 | * |
| 3095 | * For an untiled surface, this removes any existing fence. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3096 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3097 | int |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 3098 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3099 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3100 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3101 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3102 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3103 | struct drm_i915_fence_reg *reg; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 3104 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3105 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3106 | /* Have we updated the tiling parameters upon the object and so |
| 3107 | * will need to serialise the write to the associated fence register? |
| 3108 | */ |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3109 | if (obj->fence_dirty) { |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3110 | ret = i915_gem_object_wait_fence(obj); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3111 | if (ret) |
| 3112 | return ret; |
| 3113 | } |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 3114 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3115 | /* Just update our place in the LRU if our fence is getting reused. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3116 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 3117 | reg = &dev_priv->fence_regs[obj->fence_reg]; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 3118 | if (!obj->fence_dirty) { |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3119 | list_move_tail(®->lru_list, |
| 3120 | &dev_priv->mm.fence_list); |
| 3121 | return 0; |
| 3122 | } |
| 3123 | } else if (enable) { |
| 3124 | reg = i915_find_fence_reg(dev); |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3125 | if (IS_ERR(reg)) |
| 3126 | return PTR_ERR(reg); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 3127 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3128 | if (reg->obj) { |
| 3129 | struct drm_i915_gem_object *old = reg->obj; |
| 3130 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3131 | ret = i915_gem_object_wait_fence(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3132 | if (ret) |
| 3133 | return ret; |
| 3134 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3135 | i915_gem_object_fence_lost(old); |
Chris Wilson | 29c5a58 | 2011-03-17 15:23:22 +0000 | [diff] [blame] | 3136 | } |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3137 | } else |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3138 | return 0; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3139 | |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3140 | i915_gem_object_update_fence(obj, reg, enable); |
Chris Wilson | 1441574 | 2012-04-17 15:31:33 +0100 | [diff] [blame] | 3141 | |
Chris Wilson | 9ce079e | 2012-04-17 15:31:30 +0100 | [diff] [blame] | 3142 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3143 | } |
| 3144 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3145 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
| 3146 | struct drm_mm_node *gtt_space, |
| 3147 | unsigned long cache_level) |
| 3148 | { |
| 3149 | struct drm_mm_node *other; |
| 3150 | |
| 3151 | /* On non-LLC machines we have to be careful when putting differing |
| 3152 | * types of snoopable memory together to avoid the prefetcher |
Damien Lespiau | 4239ca7 | 2012-12-03 16:26:16 +0000 | [diff] [blame] | 3153 | * crossing memory domains and dying. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3154 | */ |
| 3155 | if (HAS_LLC(dev)) |
| 3156 | return true; |
| 3157 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3158 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3159 | return true; |
| 3160 | |
| 3161 | if (list_empty(>t_space->node_list)) |
| 3162 | return true; |
| 3163 | |
| 3164 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3165 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3166 | return false; |
| 3167 | |
| 3168 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3169 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3170 | return false; |
| 3171 | |
| 3172 | return true; |
| 3173 | } |
| 3174 | |
| 3175 | static void i915_gem_verify_gtt(struct drm_device *dev) |
| 3176 | { |
| 3177 | #if WATCH_GTT |
| 3178 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3179 | struct drm_i915_gem_object *obj; |
| 3180 | int err = 0; |
| 3181 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3182 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3183 | if (obj->gtt_space == NULL) { |
| 3184 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); |
| 3185 | err++; |
| 3186 | continue; |
| 3187 | } |
| 3188 | |
| 3189 | if (obj->cache_level != obj->gtt_space->color) { |
| 3190 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3191 | i915_gem_obj_ggtt_offset(obj), |
| 3192 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3193 | obj->cache_level, |
| 3194 | obj->gtt_space->color); |
| 3195 | err++; |
| 3196 | continue; |
| 3197 | } |
| 3198 | |
| 3199 | if (!i915_gem_valid_gtt_space(dev, |
| 3200 | obj->gtt_space, |
| 3201 | obj->cache_level)) { |
| 3202 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3203 | i915_gem_obj_ggtt_offset(obj), |
| 3204 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3205 | obj->cache_level); |
| 3206 | err++; |
| 3207 | continue; |
| 3208 | } |
| 3209 | } |
| 3210 | |
| 3211 | WARN_ON(err); |
| 3212 | #endif |
| 3213 | } |
| 3214 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3215 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3216 | * Finds free space in the GTT aperture and binds the object there. |
| 3217 | */ |
| 3218 | static int |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3219 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3220 | struct i915_address_space *vm, |
| 3221 | unsigned alignment, |
| 3222 | bool map_and_fenceable, |
| 3223 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3224 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3225 | struct drm_device *dev = obj->base.dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3226 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3227 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3228 | size_t gtt_max = |
| 3229 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3230 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3231 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3232 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3233 | fence_size = i915_gem_get_gtt_size(dev, |
| 3234 | obj->base.size, |
| 3235 | obj->tiling_mode); |
| 3236 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3237 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3238 | obj->tiling_mode, true); |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3239 | unfenced_alignment = |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3240 | i915_gem_get_gtt_alignment(dev, |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 3241 | obj->base.size, |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 3242 | obj->tiling_mode, false); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3243 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3244 | if (alignment == 0) |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3245 | alignment = map_and_fenceable ? fence_alignment : |
| 3246 | unfenced_alignment; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3247 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3248 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3249 | return -EINVAL; |
| 3250 | } |
| 3251 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3252 | size = map_and_fenceable ? fence_size : obj->base.size; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3253 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3254 | /* If the object is bigger than the entire aperture, reject it early |
| 3255 | * before evicting everything in a vain attempt to find space. |
| 3256 | */ |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3257 | if (obj->base.size > gtt_max) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3258 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
Chris Wilson | a36689c | 2013-05-21 16:58:49 +0100 | [diff] [blame] | 3259 | obj->base.size, |
| 3260 | map_and_fenceable ? "mappable" : "total", |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3261 | gtt_max); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3262 | return -E2BIG; |
| 3263 | } |
| 3264 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3265 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3266 | if (ret) |
| 3267 | return ret; |
| 3268 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3269 | i915_gem_object_pin_pages(obj); |
| 3270 | |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 3271 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
Dan Carpenter | db473b3 | 2013-07-19 08:45:46 +0300 | [diff] [blame] | 3272 | if (IS_ERR(vma)) { |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3273 | ret = PTR_ERR(vma); |
| 3274 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3275 | } |
| 3276 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3277 | search_free: |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3278 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3279 | size, alignment, |
David Herrmann | 31e5d7c | 2013-07-27 13:36:27 +0200 | [diff] [blame] | 3280 | obj->cache_level, 0, gtt_max, |
| 3281 | DRM_MM_SEARCH_DEFAULT); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3282 | if (ret) { |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 3283 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3284 | obj->cache_level, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3285 | map_and_fenceable, |
| 3286 | nonblocking); |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3287 | if (ret == 0) |
| 3288 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3289 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3290 | goto err_free_vma; |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3291 | } |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3292 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3293 | obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3294 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3295 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3296 | } |
| 3297 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 3298 | ret = i915_gem_gtt_prepare_object(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3299 | if (ret) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3300 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3301 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3302 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3303 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3304 | |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3305 | if (i915_is_ggtt(vm)) { |
| 3306 | bool mappable, fenceable; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3307 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3308 | fenceable = (vma->node.size == fence_size && |
| 3309 | (vma->node.start & (fence_alignment - 1)) == 0); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3310 | |
Daniel Vetter | 4998709 | 2013-08-14 10:21:23 +0200 | [diff] [blame] | 3311 | mappable = (vma->node.start + obj->base.size <= |
| 3312 | dev_priv->gtt.mappable_end); |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3313 | |
Ben Widawsky | 5cacaac | 2013-07-31 17:00:13 -0700 | [diff] [blame] | 3314 | obj->map_and_fenceable = mappable && fenceable; |
Ben Widawsky | 4bd561b | 2013-08-13 18:09:07 -0700 | [diff] [blame] | 3315 | } |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3316 | |
Ben Widawsky | 7ace7ef | 2013-08-09 22:12:12 -0700 | [diff] [blame] | 3317 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3318 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3319 | trace_i915_vma_bind(vma, map_and_fenceable); |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3320 | i915_gem_verify_gtt(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3321 | return 0; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3322 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3323 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3324 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3325 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3326 | i915_gem_vma_destroy(vma); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3327 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3328 | i915_gem_object_unpin_pages(obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3329 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3330 | } |
| 3331 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3332 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3333 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3334 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3335 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3336 | /* If we don't have a page list set up, then we're not pinned |
| 3337 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3338 | * again at bind time. |
| 3339 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3340 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3341 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3342 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3343 | /* |
| 3344 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3345 | * marked as wc by the system, or the system is cache-coherent. |
| 3346 | */ |
| 3347 | if (obj->stolen) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3348 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3349 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3350 | /* If the GPU is snooping the contents of the CPU cache, |
| 3351 | * we do not need to manually clear the CPU cache lines. However, |
| 3352 | * the caches are only snooped when the render cache is |
| 3353 | * flushed/invalidated. As we always have to emit invalidations |
| 3354 | * and flushes when moving into and out of the RENDER domain, correct |
| 3355 | * snooping behaviour occurs naturally as the result of our domain |
| 3356 | * tracking. |
| 3357 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3358 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3359 | return false; |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3360 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3361 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3362 | drm_clflush_sg(obj->pages); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3363 | |
| 3364 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3365 | } |
| 3366 | |
| 3367 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3368 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3369 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3370 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3371 | uint32_t old_write_domain; |
| 3372 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3373 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3374 | return; |
| 3375 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3376 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3377 | * to it immediately go to main memory as far as we know, so there's |
| 3378 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3379 | * |
| 3380 | * However, we do have to enforce the order so that all writes through |
| 3381 | * the GTT land before any writes to the device, such as updates to |
| 3382 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3383 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3384 | wmb(); |
| 3385 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3386 | old_write_domain = obj->base.write_domain; |
| 3387 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3388 | |
| 3389 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3390 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3391 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3392 | } |
| 3393 | |
| 3394 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3395 | static void |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3396 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
| 3397 | bool force) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3398 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3399 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3400 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3401 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3402 | return; |
| 3403 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3404 | if (i915_gem_clflush_object(obj, force)) |
| 3405 | i915_gem_chipset_flush(obj->base.dev); |
| 3406 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3407 | old_write_domain = obj->base.write_domain; |
| 3408 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3409 | |
| 3410 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3411 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3412 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3413 | } |
| 3414 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3415 | /** |
| 3416 | * Moves a single object to the GTT read, and possibly write domain. |
| 3417 | * |
| 3418 | * This function returns when the move is complete, including waiting on |
| 3419 | * flushes to occur. |
| 3420 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3421 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3422 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3423 | { |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3424 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3425 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3426 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3427 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3428 | /* Not valid to be called on unbound objects. */ |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 3429 | if (!i915_gem_obj_bound_any(obj)) |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 3430 | return -EINVAL; |
| 3431 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3432 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3433 | return 0; |
| 3434 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3435 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3436 | if (ret) |
| 3437 | return ret; |
| 3438 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3439 | i915_gem_object_flush_cpu_write_domain(obj, false); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3440 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3441 | /* Serialise direct access to this object with the barriers for |
| 3442 | * coherent writes from the GPU, by effectively invalidating the |
| 3443 | * GTT domain upon first access. |
| 3444 | */ |
| 3445 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3446 | mb(); |
| 3447 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3448 | old_write_domain = obj->base.write_domain; |
| 3449 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3450 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3451 | /* It should now be out of any other write domains, and we can update |
| 3452 | * the domain values for our changes. |
| 3453 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3454 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3455 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3456 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3457 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3458 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3459 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3460 | } |
| 3461 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3462 | trace_i915_gem_object_change_domain(obj, |
| 3463 | old_read_domains, |
| 3464 | old_write_domain); |
| 3465 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3466 | /* And bump the LRU for this access */ |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3467 | if (i915_gem_object_is_inactive(obj)) { |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 3468 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Ben Widawsky | ca191b1 | 2013-07-31 17:00:14 -0700 | [diff] [blame] | 3469 | if (vma) |
| 3470 | list_move_tail(&vma->mm_list, |
| 3471 | &dev_priv->gtt.base.inactive_list); |
| 3472 | |
| 3473 | } |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3474 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3475 | return 0; |
| 3476 | } |
| 3477 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3478 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3479 | enum i915_cache_level cache_level) |
| 3480 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3481 | struct drm_device *dev = obj->base.dev; |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3482 | struct i915_vma *vma; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3483 | int ret; |
| 3484 | |
| 3485 | if (obj->cache_level == cache_level) |
| 3486 | return 0; |
| 3487 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3488 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3489 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3490 | return -EBUSY; |
| 3491 | } |
| 3492 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3493 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
| 3494 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3495 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3496 | if (ret) |
| 3497 | return ret; |
| 3498 | |
| 3499 | break; |
| 3500 | } |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3501 | } |
| 3502 | |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3503 | if (i915_gem_obj_bound_any(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3504 | ret = i915_gem_object_finish_gpu(obj); |
| 3505 | if (ret) |
| 3506 | return ret; |
| 3507 | |
| 3508 | i915_gem_object_finish_gtt(obj); |
| 3509 | |
| 3510 | /* Before SandyBridge, you could not use tiling or fence |
| 3511 | * registers with snooped memory, so relinquish any fences |
| 3512 | * currently pointing to our region in the aperture. |
| 3513 | */ |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3514 | if (INTEL_INFO(dev)->gen < 6) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3515 | ret = i915_gem_object_put_fence(obj); |
| 3516 | if (ret) |
| 3517 | return ret; |
| 3518 | } |
| 3519 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3520 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3521 | vma->bind_vma(vma, cache_level, 0); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3522 | } |
| 3523 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3524 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 3525 | vma->node.color = cache_level; |
| 3526 | obj->cache_level = cache_level; |
| 3527 | |
| 3528 | if (cpu_write_needs_clflush(obj)) { |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3529 | u32 old_read_domains, old_write_domain; |
| 3530 | |
| 3531 | /* If we're coming from LLC cached, then we haven't |
| 3532 | * actually been tracking whether the data is in the |
| 3533 | * CPU cache or not, since we only allow one bit set |
| 3534 | * in obj->write_domain and have been skipping the clflushes. |
| 3535 | * Just set it to the CPU cache for now. |
| 3536 | */ |
| 3537 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3538 | |
| 3539 | old_read_domains = obj->base.read_domains; |
| 3540 | old_write_domain = obj->base.write_domain; |
| 3541 | |
| 3542 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3543 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 3544 | |
| 3545 | trace_i915_gem_object_change_domain(obj, |
| 3546 | old_read_domains, |
| 3547 | old_write_domain); |
| 3548 | } |
| 3549 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3550 | i915_gem_verify_gtt(dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3551 | return 0; |
| 3552 | } |
| 3553 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3554 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3555 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3556 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3557 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3558 | struct drm_i915_gem_object *obj; |
| 3559 | int ret; |
| 3560 | |
| 3561 | ret = i915_mutex_lock_interruptible(dev); |
| 3562 | if (ret) |
| 3563 | return ret; |
| 3564 | |
| 3565 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3566 | if (&obj->base == NULL) { |
| 3567 | ret = -ENOENT; |
| 3568 | goto unlock; |
| 3569 | } |
| 3570 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3571 | switch (obj->cache_level) { |
| 3572 | case I915_CACHE_LLC: |
| 3573 | case I915_CACHE_L3_LLC: |
| 3574 | args->caching = I915_CACHING_CACHED; |
| 3575 | break; |
| 3576 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3577 | case I915_CACHE_WT: |
| 3578 | args->caching = I915_CACHING_DISPLAY; |
| 3579 | break; |
| 3580 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3581 | default: |
| 3582 | args->caching = I915_CACHING_NONE; |
| 3583 | break; |
| 3584 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3585 | |
| 3586 | drm_gem_object_unreference(&obj->base); |
| 3587 | unlock: |
| 3588 | mutex_unlock(&dev->struct_mutex); |
| 3589 | return ret; |
| 3590 | } |
| 3591 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3592 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3593 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3594 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3595 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3596 | struct drm_i915_gem_object *obj; |
| 3597 | enum i915_cache_level level; |
| 3598 | int ret; |
| 3599 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3600 | switch (args->caching) { |
| 3601 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3602 | level = I915_CACHE_NONE; |
| 3603 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3604 | case I915_CACHING_CACHED: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3605 | level = I915_CACHE_LLC; |
| 3606 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3607 | case I915_CACHING_DISPLAY: |
| 3608 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3609 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3610 | default: |
| 3611 | return -EINVAL; |
| 3612 | } |
| 3613 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3614 | ret = i915_mutex_lock_interruptible(dev); |
| 3615 | if (ret) |
| 3616 | return ret; |
| 3617 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3618 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 3619 | if (&obj->base == NULL) { |
| 3620 | ret = -ENOENT; |
| 3621 | goto unlock; |
| 3622 | } |
| 3623 | |
| 3624 | ret = i915_gem_object_set_cache_level(obj, level); |
| 3625 | |
| 3626 | drm_gem_object_unreference(&obj->base); |
| 3627 | unlock: |
| 3628 | mutex_unlock(&dev->struct_mutex); |
| 3629 | return ret; |
| 3630 | } |
| 3631 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3632 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
| 3633 | { |
| 3634 | /* There are 3 sources that pin objects: |
| 3635 | * 1. The display engine (scanouts, sprites, cursors); |
| 3636 | * 2. Reservations for execbuffer; |
| 3637 | * 3. The user. |
| 3638 | * |
| 3639 | * We can ignore reservations as we hold the struct_mutex and |
| 3640 | * are only called outside of the reservation path. The user |
| 3641 | * can only increment pin_count once, and so if after |
| 3642 | * subtracting the potential reference by the user, any pin_count |
| 3643 | * remains, it must be due to another use by the display engine. |
| 3644 | */ |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3645 | return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3646 | } |
| 3647 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3648 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3649 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 3650 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 3651 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3652 | */ |
| 3653 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3654 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 3655 | u32 alignment, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3656 | struct intel_ring_buffer *pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3657 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3658 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3659 | int ret; |
| 3660 | |
Chris Wilson | 0be7328 | 2010-12-06 14:36:27 +0000 | [diff] [blame] | 3661 | if (pipelined != obj->ring) { |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3662 | ret = i915_gem_object_sync(obj, pipelined); |
| 3663 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3664 | return ret; |
| 3665 | } |
| 3666 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3667 | /* Mark the pin_display early so that we account for the |
| 3668 | * display coherency whilst setting up the cache domains. |
| 3669 | */ |
| 3670 | obj->pin_display = true; |
| 3671 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3672 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 3673 | * a result, we make sure that the pinning that is about to occur is |
| 3674 | * done with uncached PTEs. This is lowest common denominator for all |
| 3675 | * chipsets. |
| 3676 | * |
| 3677 | * However for gen6+, we could do better by using the GFDT bit instead |
| 3678 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 3679 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 3680 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3681 | ret = i915_gem_object_set_cache_level(obj, |
| 3682 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3683 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3684 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 3685 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3686 | /* As the user may map the buffer once pinned in the display plane |
| 3687 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 3688 | * always use map_and_fenceable for all scanout buffers. |
| 3689 | */ |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3690 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3691 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3692 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3693 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3694 | i915_gem_object_flush_cpu_write_domain(obj, true); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 3695 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3696 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3697 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3698 | |
| 3699 | /* It should now be out of any other write domains, and we can update |
| 3700 | * the domain values for our changes. |
| 3701 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 3702 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3703 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3704 | |
| 3705 | trace_i915_gem_object_change_domain(obj, |
| 3706 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 3707 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3708 | |
| 3709 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3710 | |
| 3711 | err_unpin_display: |
| 3712 | obj->pin_display = is_pin_display(obj); |
| 3713 | return ret; |
| 3714 | } |
| 3715 | |
| 3716 | void |
| 3717 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) |
| 3718 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3719 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 3720 | obj->pin_display = is_pin_display(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 3721 | } |
| 3722 | |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3723 | int |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3724 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3725 | { |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3726 | int ret; |
| 3727 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3728 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3729 | return 0; |
| 3730 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3731 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3732 | if (ret) |
| 3733 | return ret; |
| 3734 | |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3735 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
| 3736 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
Chris Wilson | c501ae7 | 2011-12-14 13:57:23 +0100 | [diff] [blame] | 3737 | return 0; |
Chris Wilson | 8534551 | 2010-11-13 09:49:11 +0000 | [diff] [blame] | 3738 | } |
| 3739 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3740 | /** |
| 3741 | * Moves a single object to the CPU read, and possibly write domain. |
| 3742 | * |
| 3743 | * This function returns when the move is complete, including waiting on |
| 3744 | * flushes to occur. |
| 3745 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 3746 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 3747 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3748 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3749 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3750 | int ret; |
| 3751 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3752 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 3753 | return 0; |
| 3754 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3755 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3756 | if (ret) |
| 3757 | return ret; |
| 3758 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3759 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3760 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3761 | old_write_domain = obj->base.write_domain; |
| 3762 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3763 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3764 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3765 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3766 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3767 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3768 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3769 | } |
| 3770 | |
| 3771 | /* It should now be out of any other write domains, and we can update |
| 3772 | * the domain values for our changes. |
| 3773 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3774 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3775 | |
| 3776 | /* If we're writing through the CPU, then the GPU read domains will |
| 3777 | * need to be invalidated at next use. |
| 3778 | */ |
| 3779 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3780 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 3781 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3782 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3783 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3784 | trace_i915_gem_object_change_domain(obj, |
| 3785 | old_read_domains, |
| 3786 | old_write_domain); |
| 3787 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3788 | return 0; |
| 3789 | } |
| 3790 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3791 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3792 | * emitted over 20 msec ago. |
| 3793 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3794 | * Note that if we were to use the current jiffies each time around the loop, |
| 3795 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3796 | * render a frame was over 20ms. |
| 3797 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3798 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3799 | * relatively low latency when blocking on a particular request to finish. |
| 3800 | */ |
| 3801 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3802 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3803 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3804 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3805 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3806 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3807 | struct drm_i915_gem_request *request; |
| 3808 | struct intel_ring_buffer *ring = NULL; |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3809 | unsigned reset_counter; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3810 | u32 seqno = 0; |
| 3811 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3812 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 3813 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 3814 | if (ret) |
| 3815 | return ret; |
| 3816 | |
| 3817 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); |
| 3818 | if (ret) |
| 3819 | return ret; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 3820 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3821 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3822 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3823 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3824 | break; |
| 3825 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3826 | ring = request->ring; |
| 3827 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3828 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 3829 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3830 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3831 | |
| 3832 | if (seqno == 0) |
| 3833 | return 0; |
| 3834 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3835 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3836 | if (ret == 0) |
| 3837 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3838 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3839 | return ret; |
| 3840 | } |
| 3841 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3842 | int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3843 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3844 | struct i915_address_space *vm, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3845 | uint32_t alignment, |
Chris Wilson | 86a1ee2 | 2012-08-11 15:41:04 +0100 | [diff] [blame] | 3846 | bool map_and_fenceable, |
| 3847 | bool nonblocking) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3848 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3849 | const u32 flags = map_and_fenceable ? GLOBAL_BIND : 0; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3850 | struct i915_vma *vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3851 | int ret; |
| 3852 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3853 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
| 3854 | |
| 3855 | vma = i915_gem_obj_to_vma(obj, vm); |
| 3856 | |
| 3857 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3858 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 3859 | return -EBUSY; |
| 3860 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3861 | if ((alignment && |
| 3862 | vma->node.start & (alignment - 1)) || |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3863 | (map_and_fenceable && !obj->map_and_fenceable)) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3864 | WARN(vma->pin_count, |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 3865 | "bo is already pinned with incorrect alignment:" |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3866 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3867 | " obj->map_and_fenceable=%d\n", |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3868 | i915_gem_obj_offset(obj, vm), alignment, |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 3869 | map_and_fenceable, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3870 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3871 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 3872 | if (ret) |
| 3873 | return ret; |
| 3874 | } |
| 3875 | } |
| 3876 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3877 | if (!i915_gem_obj_bound(obj, vm)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3878 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
| 3879 | map_and_fenceable, |
| 3880 | nonblocking); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3881 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3882 | return ret; |
Chris Wilson | 8742267 | 2012-11-21 13:04:03 +0000 | [diff] [blame] | 3883 | |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3884 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3885 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3886 | vma = i915_gem_obj_to_vma(obj, vm); |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 3887 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3888 | vma->bind_vma(vma, obj->cache_level, flags); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3889 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3890 | i915_gem_obj_to_vma(obj, vm)->pin_count++; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3891 | obj->pin_mappable |= map_and_fenceable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3892 | |
| 3893 | return 0; |
| 3894 | } |
| 3895 | |
| 3896 | void |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3897 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3898 | { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3899 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3900 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3901 | BUG_ON(!vma); |
| 3902 | BUG_ON(vma->pin_count == 0); |
| 3903 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); |
| 3904 | |
| 3905 | if (--vma->pin_count == 0) |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 3906 | obj->pin_mappable = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3907 | } |
| 3908 | |
| 3909 | int |
| 3910 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3911 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3912 | { |
| 3913 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3914 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3915 | int ret; |
| 3916 | |
Daniel Vetter | 02f6bcc | 2013-12-18 16:30:22 +0100 | [diff] [blame] | 3917 | if (INTEL_INFO(dev)->gen >= 6) |
| 3918 | return -ENODEV; |
| 3919 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3920 | ret = i915_mutex_lock_interruptible(dev); |
| 3921 | if (ret) |
| 3922 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3923 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3924 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3925 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3926 | ret = -ENOENT; |
| 3927 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3928 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3929 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3930 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3931 | DRM_DEBUG("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 3932 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3933 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3934 | } |
| 3935 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3936 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3937 | DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3938 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3939 | ret = -EINVAL; |
| 3940 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3941 | } |
| 3942 | |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 3943 | if (obj->user_pin_count == ULONG_MAX) { |
| 3944 | ret = -EBUSY; |
| 3945 | goto out; |
| 3946 | } |
| 3947 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3948 | if (obj->user_pin_count == 0) { |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 3949 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3950 | if (ret) |
| 3951 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3952 | } |
| 3953 | |
Chris Wilson | 93be878 | 2013-01-02 10:31:22 +0000 | [diff] [blame] | 3954 | obj->user_pin_count++; |
| 3955 | obj->pin_filp = file; |
| 3956 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 3957 | args->offset = i915_gem_obj_ggtt_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3958 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3959 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3960 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3961 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3962 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3963 | } |
| 3964 | |
| 3965 | int |
| 3966 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3967 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3968 | { |
| 3969 | struct drm_i915_gem_pin *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3970 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3971 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3972 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3973 | ret = i915_mutex_lock_interruptible(dev); |
| 3974 | if (ret) |
| 3975 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3976 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3977 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 3978 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3979 | ret = -ENOENT; |
| 3980 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3981 | } |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3982 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3983 | if (obj->pin_filp != file) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 3984 | DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3985 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3986 | ret = -EINVAL; |
| 3987 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3988 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3989 | obj->user_pin_count--; |
| 3990 | if (obj->user_pin_count == 0) { |
| 3991 | obj->pin_filp = NULL; |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3992 | i915_gem_object_ggtt_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3993 | } |
| 3994 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3995 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3996 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3997 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3998 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 3999 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4000 | } |
| 4001 | |
| 4002 | int |
| 4003 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4004 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4005 | { |
| 4006 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4007 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4008 | int ret; |
| 4009 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4010 | ret = i915_mutex_lock_interruptible(dev); |
| 4011 | if (ret) |
| 4012 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4013 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4014 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4015 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4016 | ret = -ENOENT; |
| 4017 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4018 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4019 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4020 | /* Count all active objects as busy, even if they are currently not used |
| 4021 | * by the gpu. Users of this interface expect objects to eventually |
| 4022 | * become non-busy without any further actions, therefore emit any |
| 4023 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4024 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4025 | ret = i915_gem_object_flush_active(obj); |
| 4026 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4027 | args->busy = obj->active; |
Chris Wilson | e9808ed | 2012-07-04 12:25:08 +0100 | [diff] [blame] | 4028 | if (obj->ring) { |
| 4029 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
| 4030 | args->busy |= intel_ring_flag(obj->ring) << 16; |
| 4031 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4032 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4033 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4034 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4035 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4036 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | int |
| 4040 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4041 | struct drm_file *file_priv) |
| 4042 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4043 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4044 | } |
| 4045 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4046 | int |
| 4047 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4048 | struct drm_file *file_priv) |
| 4049 | { |
| 4050 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4051 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4052 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4053 | |
| 4054 | switch (args->madv) { |
| 4055 | case I915_MADV_DONTNEED: |
| 4056 | case I915_MADV_WILLNEED: |
| 4057 | break; |
| 4058 | default: |
| 4059 | return -EINVAL; |
| 4060 | } |
| 4061 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4062 | ret = i915_mutex_lock_interruptible(dev); |
| 4063 | if (ret) |
| 4064 | return ret; |
| 4065 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4066 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4067 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4068 | ret = -ENOENT; |
| 4069 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4070 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4071 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4072 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4073 | ret = -EINVAL; |
| 4074 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4075 | } |
| 4076 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4077 | if (obj->madv != __I915_MADV_PURGED) |
| 4078 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4079 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4080 | /* if the object is no longer attached, discard its backing storage */ |
| 4081 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4082 | i915_gem_object_truncate(obj); |
| 4083 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4084 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4085 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4086 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4087 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4088 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4089 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4090 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4091 | } |
| 4092 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4093 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4094 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4095 | { |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4096 | INIT_LIST_HEAD(&obj->global_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4097 | INIT_LIST_HEAD(&obj->ring_list); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4098 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4099 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4100 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4101 | obj->ops = ops; |
| 4102 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4103 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4104 | obj->madv = I915_MADV_WILLNEED; |
| 4105 | /* Avoid an unnecessary call to unbind on the first bind. */ |
| 4106 | obj->map_and_fenceable = true; |
| 4107 | |
| 4108 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4109 | } |
| 4110 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4111 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
| 4112 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4113 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4114 | }; |
| 4115 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4116 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 4117 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4118 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4119 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4120 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4121 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4122 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4123 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4124 | if (obj == NULL) |
| 4125 | return NULL; |
| 4126 | |
| 4127 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4128 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4129 | return NULL; |
| 4130 | } |
| 4131 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4132 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4133 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4134 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4135 | mask &= ~__GFP_HIGHMEM; |
| 4136 | mask |= __GFP_DMA32; |
| 4137 | } |
| 4138 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4139 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4140 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4141 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4142 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4143 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4144 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4145 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4146 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4147 | if (HAS_LLC(dev)) { |
| 4148 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4149 | * cache) for about a 10% performance improvement |
| 4150 | * compared to uncached. Graphics requests other than |
| 4151 | * display scanout are coherent with the CPU in |
| 4152 | * accessing this cache. This means in this mode we |
| 4153 | * don't need to clflush on the CPU side, and on the |
| 4154 | * GPU side we only need to flush internal caches to |
| 4155 | * get data visible to the CPU. |
| 4156 | * |
| 4157 | * However, we maintain the display planes as UC, and so |
| 4158 | * need to rebind when first used as such. |
| 4159 | */ |
| 4160 | obj->cache_level = I915_CACHE_LLC; |
| 4161 | } else |
| 4162 | obj->cache_level = I915_CACHE_NONE; |
| 4163 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4164 | trace_i915_gem_object_create(obj); |
| 4165 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4166 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4167 | } |
| 4168 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4169 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4170 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4171 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4172 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4173 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4174 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4175 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4176 | intel_runtime_pm_get(dev_priv); |
| 4177 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4178 | trace_i915_gem_object_destroy(obj); |
| 4179 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4180 | if (obj->phys_obj) |
| 4181 | i915_gem_detach_phys_object(dev, obj); |
| 4182 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4183 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4184 | int ret; |
| 4185 | |
| 4186 | vma->pin_count = 0; |
| 4187 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4188 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4189 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4190 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4191 | was_interruptible = dev_priv->mm.interruptible; |
| 4192 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4193 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4194 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4195 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4196 | dev_priv->mm.interruptible = was_interruptible; |
| 4197 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4198 | } |
| 4199 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4200 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4201 | * before progressing. */ |
| 4202 | if (obj->stolen) |
| 4203 | i915_gem_object_unpin_pages(obj); |
| 4204 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4205 | if (WARN_ON(obj->pages_pin_count)) |
| 4206 | obj->pages_pin_count = 0; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4207 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4208 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 4209 | i915_gem_object_release_stolen(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4210 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4211 | BUG_ON(obj->pages); |
| 4212 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4213 | if (obj->base.import_attach) |
| 4214 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4215 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4216 | drm_gem_object_release(&obj->base); |
| 4217 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4218 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4219 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4220 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4221 | |
| 4222 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4223 | } |
| 4224 | |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4225 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4226 | struct i915_address_space *vm) |
| 4227 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4228 | struct i915_vma *vma; |
| 4229 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 4230 | if (vma->vm == vm) |
| 4231 | return vma; |
| 4232 | |
| 4233 | return NULL; |
| 4234 | } |
| 4235 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4236 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4237 | { |
| 4238 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4239 | |
| 4240 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4241 | if (!list_empty(&vma->exec_list)) |
| 4242 | return; |
| 4243 | |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4244 | list_del(&vma->vma_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4245 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4246 | kfree(vma); |
| 4247 | } |
| 4248 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4249 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4250 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4251 | { |
| 4252 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4253 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4254 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4255 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4256 | if (dev_priv->ums.mm_suspended) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4257 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4258 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4259 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4260 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4261 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4262 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4263 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4264 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4265 | /* Under UMS, be paranoid and evict. */ |
Chris Wilson | a39d7ef | 2012-04-24 18:22:52 +0100 | [diff] [blame] | 4266 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4267 | i915_gem_evict_everything(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4268 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4269 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4270 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4271 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4272 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4273 | * We need to replace this with a semaphore, or something. |
| 4274 | * And not confound ums.mm_suspended! |
| 4275 | */ |
| 4276 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, |
| 4277 | DRIVER_MODESET); |
| 4278 | mutex_unlock(&dev->struct_mutex); |
| 4279 | |
| 4280 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4281 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4282 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4283 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4284 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4285 | |
| 4286 | err: |
| 4287 | mutex_unlock(&dev->struct_mutex); |
| 4288 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4289 | } |
| 4290 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4291 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4292 | { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4293 | struct drm_device *dev = ring->dev; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4294 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4295 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
| 4296 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4297 | int i, ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4298 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 4299 | if (!HAS_L3_DPF(dev) || !remap_info) |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4300 | return 0; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4301 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4302 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
| 4303 | if (ret) |
| 4304 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4305 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4306 | /* |
| 4307 | * Note: We do not worry about the concurrent register cacheline hang |
| 4308 | * here because no other code should access these registers other than |
| 4309 | * at initialization time. |
| 4310 | */ |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4311 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4312 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 4313 | intel_ring_emit(ring, reg_base + i); |
| 4314 | intel_ring_emit(ring, remap_info[i/4]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4315 | } |
| 4316 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4317 | intel_ring_advance(ring); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4318 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4319 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4320 | } |
| 4321 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4322 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4323 | { |
| 4324 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4325 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4326 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4327 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4328 | return; |
| 4329 | |
| 4330 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4331 | DISP_TILE_SURFACE_SWIZZLING); |
| 4332 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4333 | if (IS_GEN5(dev)) |
| 4334 | return; |
| 4335 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4336 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4337 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4338 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4339 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4340 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4341 | else if (IS_GEN8(dev)) |
| 4342 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4343 | else |
| 4344 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4345 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4346 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4347 | static bool |
| 4348 | intel_enable_blt(struct drm_device *dev) |
| 4349 | { |
| 4350 | if (!HAS_BLT(dev)) |
| 4351 | return false; |
| 4352 | |
| 4353 | /* The blitter was dysfunctional on early prototypes */ |
| 4354 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { |
| 4355 | DRM_INFO("BLT not supported on this pre-production hardware;" |
| 4356 | " graphics performance will be degraded.\n"); |
| 4357 | return false; |
| 4358 | } |
| 4359 | |
| 4360 | return true; |
| 4361 | } |
| 4362 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4363 | static int i915_gem_init_rings(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4364 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4365 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4366 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4367 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4368 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4369 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4370 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4371 | |
| 4372 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4373 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4374 | if (ret) |
| 4375 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4376 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4377 | |
Chris Wilson | 67b1b57 | 2012-07-05 23:49:40 +0100 | [diff] [blame] | 4378 | if (intel_enable_blt(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4379 | ret = intel_init_blt_ring_buffer(dev); |
| 4380 | if (ret) |
| 4381 | goto cleanup_bsd_ring; |
| 4382 | } |
| 4383 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4384 | if (HAS_VEBOX(dev)) { |
| 4385 | ret = intel_init_vebox_ring_buffer(dev); |
| 4386 | if (ret) |
| 4387 | goto cleanup_blt_ring; |
| 4388 | } |
| 4389 | |
| 4390 | |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4391 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
| 4392 | if (ret) |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4393 | goto cleanup_vebox_ring; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4394 | |
| 4395 | return 0; |
| 4396 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4397 | cleanup_vebox_ring: |
| 4398 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4399 | cleanup_blt_ring: |
| 4400 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); |
| 4401 | cleanup_bsd_ring: |
| 4402 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
| 4403 | cleanup_render_ring: |
| 4404 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
| 4405 | |
| 4406 | return ret; |
| 4407 | } |
| 4408 | |
| 4409 | int |
| 4410 | i915_gem_init_hw(struct drm_device *dev) |
| 4411 | { |
| 4412 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4413 | int ret, i; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4414 | |
| 4415 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4416 | return -EIO; |
| 4417 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 4418 | if (dev_priv->ellc_size) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4419 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4420 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 4421 | if (IS_HASWELL(dev)) |
| 4422 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4423 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4424 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4425 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 4426 | if (IS_IVYBRIDGE(dev)) { |
| 4427 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4428 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4429 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4430 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4431 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4432 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4433 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4434 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4435 | } |
| 4436 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4437 | i915_gem_init_swizzling(dev); |
| 4438 | |
| 4439 | ret = i915_gem_init_rings(dev); |
| 4440 | if (ret) |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4441 | return ret; |
| 4442 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4443 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
| 4444 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); |
| 4445 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4446 | /* |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4447 | * XXX: Contexts should only be initialized once. Doing a switch to the |
| 4448 | * default context switch however is something we'd like to do after |
| 4449 | * reset or thaw (the latter may not actually be necessary for HW, but |
| 4450 | * goes with our code better). Context switching requires rings (for |
| 4451 | * the do_switch), but before enabling PPGTT. So don't move this. |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 4452 | */ |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4453 | ret = i915_gem_context_enable(dev_priv); |
Ben Widawsky | 8245be3 | 2013-11-06 13:56:29 -0200 | [diff] [blame] | 4454 | if (ret) { |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4455 | DRM_ERROR("Context enable failed %d\n", ret); |
| 4456 | goto err_out; |
Ben Widawsky | b7c36d2 | 2013-04-08 18:43:56 -0700 | [diff] [blame] | 4457 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4458 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4459 | return 0; |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4460 | |
| 4461 | err_out: |
| 4462 | i915_gem_cleanup_ringbuffer(dev); |
| 4463 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4464 | } |
| 4465 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4466 | int i915_gem_init(struct drm_device *dev) |
| 4467 | { |
| 4468 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4469 | int ret; |
| 4470 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4471 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4472 | |
| 4473 | if (IS_VALLEYVIEW(dev)) { |
| 4474 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ |
| 4475 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); |
| 4476 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) |
| 4477 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
| 4478 | } |
| 4479 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 4480 | i915_gem_init_global_gtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4481 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4482 | ret = i915_gem_context_init(dev); |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4483 | if (ret) { |
| 4484 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4485 | return ret; |
Mika Kuoppala | e384869 | 2014-01-31 17:14:02 +0200 | [diff] [blame] | 4486 | } |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4487 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4488 | ret = i915_gem_init_hw(dev); |
| 4489 | mutex_unlock(&dev->struct_mutex); |
| 4490 | if (ret) { |
Ben Widawsky | bdf4fd7 | 2013-12-06 14:11:18 -0800 | [diff] [blame] | 4491 | WARN_ON(dev_priv->mm.aliasing_ppgtt); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4492 | i915_gem_context_fini(dev); |
Ben Widawsky | c39538a | 2013-12-06 14:10:50 -0800 | [diff] [blame] | 4493 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4494 | return ret; |
| 4495 | } |
| 4496 | |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 4497 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
| 4498 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4499 | dev_priv->dri1.allow_batchbuffer = 1; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4500 | return 0; |
| 4501 | } |
| 4502 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4503 | void |
| 4504 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4505 | { |
| 4506 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4507 | struct intel_ring_buffer *ring; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4508 | int i; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4509 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4510 | for_each_ring(ring, dev_priv, i) |
| 4511 | intel_cleanup_ring_buffer(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4512 | } |
| 4513 | |
| 4514 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4515 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4516 | struct drm_file *file_priv) |
| 4517 | { |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4518 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 4519 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4520 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4521 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4522 | return 0; |
| 4523 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4524 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4525 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4526 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4527 | } |
| 4528 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4529 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4530 | dev_priv->ums.mm_suspended = 0; |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4531 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4532 | ret = i915_gem_init_hw(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4533 | if (ret != 0) { |
| 4534 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4535 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4536 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4537 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 4538 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4539 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4540 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4541 | ret = drm_irq_install(dev); |
| 4542 | if (ret) |
| 4543 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4544 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4545 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4546 | |
| 4547 | cleanup_ringbuffer: |
| 4548 | mutex_lock(&dev->struct_mutex); |
| 4549 | i915_gem_cleanup_ringbuffer(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4550 | dev_priv->ums.mm_suspended = 1; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4551 | mutex_unlock(&dev->struct_mutex); |
| 4552 | |
| 4553 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4554 | } |
| 4555 | |
| 4556 | int |
| 4557 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4558 | struct drm_file *file_priv) |
| 4559 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4560 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4561 | return 0; |
| 4562 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4563 | drm_irq_uninstall(dev); |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 4564 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4565 | return i915_gem_suspend(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4566 | } |
| 4567 | |
| 4568 | void |
| 4569 | i915_gem_lastclose(struct drm_device *dev) |
| 4570 | { |
| 4571 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4572 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4573 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4574 | return; |
| 4575 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4576 | ret = i915_gem_suspend(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4577 | if (ret) |
| 4578 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4579 | } |
| 4580 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4581 | static void |
| 4582 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4583 | { |
| 4584 | INIT_LIST_HEAD(&ring->active_list); |
| 4585 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4586 | } |
| 4587 | |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4588 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 4589 | struct i915_address_space *vm) |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4590 | { |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 4591 | if (!i915_is_ggtt(vm)) |
| 4592 | drm_mm_init(&vm->mm, vm->start, vm->total); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4593 | vm->dev = dev_priv->dev; |
| 4594 | INIT_LIST_HEAD(&vm->active_list); |
| 4595 | INIT_LIST_HEAD(&vm->inactive_list); |
| 4596 | INIT_LIST_HEAD(&vm->global_link); |
Chris Wilson | f72d21e | 2014-01-09 22:57:22 +0000 | [diff] [blame] | 4597 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4598 | } |
| 4599 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4600 | void |
| 4601 | i915_gem_load(struct drm_device *dev) |
| 4602 | { |
| 4603 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4604 | int i; |
| 4605 | |
| 4606 | dev_priv->slab = |
| 4607 | kmem_cache_create("i915_gem_object", |
| 4608 | sizeof(struct drm_i915_gem_object), 0, |
| 4609 | SLAB_HWCACHE_ALIGN, |
| 4610 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4611 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 4612 | INIT_LIST_HEAD(&dev_priv->vm_list); |
| 4613 | i915_init_vm(dev_priv, &dev_priv->gtt.base); |
| 4614 | |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 4615 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4616 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 4617 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4618 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 4619 | for (i = 0; i < I915_NUM_RINGS; i++) |
| 4620 | init_ring_lists(&dev_priv->ring[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 4621 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4622 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4623 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4624 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4625 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 4626 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 4627 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4628 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4629 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4630 | if (IS_GEN3(dev)) { |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 4631 | I915_WRITE(MI_ARB_STATE, |
| 4632 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4633 | } |
| 4634 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 4635 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 4636 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4637 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4638 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4639 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4640 | |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 4641 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
| 4642 | dev_priv->num_fence_regs = 32; |
| 4643 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4644 | dev_priv->num_fence_regs = 16; |
| 4645 | else |
| 4646 | dev_priv->num_fence_regs = 8; |
| 4647 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4648 | /* Initialize fence registers to zero */ |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 4649 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
| 4650 | i915_gem_restore_fences(dev); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 4651 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4652 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4653 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4654 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4655 | dev_priv->mm.interruptible = true; |
| 4656 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4657 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
| 4658 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4659 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4660 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4661 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4662 | |
| 4663 | /* |
| 4664 | * Create a physically contiguous memory object for this object |
| 4665 | * e.g. for cursor + overlay regs |
| 4666 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4667 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4668 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4669 | { |
| 4670 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4671 | struct drm_i915_gem_phys_object *phys_obj; |
| 4672 | int ret; |
| 4673 | |
| 4674 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4675 | return 0; |
| 4676 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 4677 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4678 | if (!phys_obj) |
| 4679 | return -ENOMEM; |
| 4680 | |
| 4681 | phys_obj->id = id; |
| 4682 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4683 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4684 | if (!phys_obj->handle) { |
| 4685 | ret = -ENOMEM; |
| 4686 | goto kfree_obj; |
| 4687 | } |
| 4688 | #ifdef CONFIG_X86 |
| 4689 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4690 | #endif |
| 4691 | |
| 4692 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4693 | |
| 4694 | return 0; |
| 4695 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4696 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4697 | return ret; |
| 4698 | } |
| 4699 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4700 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4701 | { |
| 4702 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4703 | struct drm_i915_gem_phys_object *phys_obj; |
| 4704 | |
| 4705 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4706 | return; |
| 4707 | |
| 4708 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4709 | if (phys_obj->cur_obj) { |
| 4710 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4711 | } |
| 4712 | |
| 4713 | #ifdef CONFIG_X86 |
| 4714 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4715 | #endif |
| 4716 | drm_pci_free(dev, phys_obj->handle); |
| 4717 | kfree(phys_obj); |
| 4718 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4719 | } |
| 4720 | |
| 4721 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4722 | { |
| 4723 | int i; |
| 4724 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4725 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4726 | i915_gem_free_phys_object(dev, i); |
| 4727 | } |
| 4728 | |
| 4729 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4730 | struct drm_i915_gem_object *obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4731 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4732 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4733 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4734 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4735 | int page_count; |
| 4736 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4737 | if (!obj->phys_obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4738 | return; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4739 | vaddr = obj->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4740 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4741 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4742 | for (i = 0; i < page_count; i++) { |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4743 | struct page *page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4744 | if (!IS_ERR(page)) { |
| 4745 | char *dst = kmap_atomic(page); |
| 4746 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4747 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4748 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4749 | drm_clflush_pages(&page, 1); |
| 4750 | |
| 4751 | set_page_dirty(page); |
| 4752 | mark_page_accessed(page); |
| 4753 | page_cache_release(page); |
| 4754 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4755 | } |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4756 | i915_gem_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4757 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4758 | obj->phys_obj->cur_obj = NULL; |
| 4759 | obj->phys_obj = NULL; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4760 | } |
| 4761 | |
| 4762 | int |
| 4763 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4764 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4765 | int id, |
| 4766 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4767 | { |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4768 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4769 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4770 | int ret = 0; |
| 4771 | int page_count; |
| 4772 | int i; |
| 4773 | |
| 4774 | if (id > I915_MAX_PHYS_OBJECT) |
| 4775 | return -EINVAL; |
| 4776 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4777 | if (obj->phys_obj) { |
| 4778 | if (obj->phys_obj->id == id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4779 | return 0; |
| 4780 | i915_gem_detach_phys_object(dev, obj); |
| 4781 | } |
| 4782 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4783 | /* create a new object */ |
| 4784 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4785 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4786 | obj->base.size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4787 | if (ret) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4788 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
| 4789 | id, obj->base.size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4790 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4791 | } |
| 4792 | } |
| 4793 | |
| 4794 | /* bind to the object */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4795 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4796 | obj->phys_obj->cur_obj = obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4797 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4798 | page_count = obj->base.size / PAGE_SIZE; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4799 | |
| 4800 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4801 | struct page *page; |
| 4802 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4803 | |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4804 | page = shmem_read_mapping_page(mapping, i); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4805 | if (IS_ERR(page)) |
| 4806 | return PTR_ERR(page); |
| 4807 | |
Chris Wilson | ff75b9b | 2010-10-30 22:52:31 +0100 | [diff] [blame] | 4808 | src = kmap_atomic(page); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4809 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4810 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4811 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4812 | |
| 4813 | mark_page_accessed(page); |
| 4814 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4815 | } |
| 4816 | |
| 4817 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4818 | } |
| 4819 | |
| 4820 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4821 | i915_gem_phys_pwrite(struct drm_device *dev, |
| 4822 | struct drm_i915_gem_object *obj, |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4823 | struct drm_i915_gem_pwrite *args, |
| 4824 | struct drm_file *file_priv) |
| 4825 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4826 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 4827 | char __user *user_data = to_user_ptr(args->data_ptr); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4828 | |
Chris Wilson | b47b30c | 2010-11-08 01:12:29 +0000 | [diff] [blame] | 4829 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 4830 | unsigned long unwritten; |
| 4831 | |
| 4832 | /* The physical object once assigned is fixed for the lifetime |
| 4833 | * of the obj, so we can safely drop the lock and continue |
| 4834 | * to access vaddr. |
| 4835 | */ |
| 4836 | mutex_unlock(&dev->struct_mutex); |
| 4837 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 4838 | mutex_lock(&dev->struct_mutex); |
| 4839 | if (unwritten) |
| 4840 | return -EFAULT; |
| 4841 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4842 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 4843 | i915_gem_chipset_flush(dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4844 | return 0; |
| 4845 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4846 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4847 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4848 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4849 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4850 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4851 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
| 4852 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4853 | /* Clean up our request list when the client is going away, so that |
| 4854 | * later retire_requests won't dereference our soon-to-be-gone |
| 4855 | * file_priv. |
| 4856 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4857 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4858 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4859 | struct drm_i915_gem_request *request; |
| 4860 | |
| 4861 | request = list_first_entry(&file_priv->mm.request_list, |
| 4862 | struct drm_i915_gem_request, |
| 4863 | client_list); |
| 4864 | list_del(&request->client_list); |
| 4865 | request->file_priv = NULL; |
| 4866 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4867 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4868 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4869 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4870 | static void |
| 4871 | i915_gem_file_idle_work_handler(struct work_struct *work) |
| 4872 | { |
| 4873 | struct drm_i915_file_private *file_priv = |
| 4874 | container_of(work, typeof(*file_priv), mm.idle_work.work); |
| 4875 | |
| 4876 | atomic_set(&file_priv->rps_wait_boost, false); |
| 4877 | } |
| 4878 | |
| 4879 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 4880 | { |
| 4881 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 4882 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4883 | |
| 4884 | DRM_DEBUG_DRIVER("\n"); |
| 4885 | |
| 4886 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 4887 | if (!file_priv) |
| 4888 | return -ENOMEM; |
| 4889 | |
| 4890 | file->driver_priv = file_priv; |
| 4891 | file_priv->dev_priv = dev->dev_private; |
| 4892 | |
| 4893 | spin_lock_init(&file_priv->mm.lock); |
| 4894 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
| 4895 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, |
| 4896 | i915_gem_file_idle_work_handler); |
| 4897 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 4898 | ret = i915_gem_context_open(dev, file); |
| 4899 | if (ret) |
| 4900 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4901 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 4902 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 4903 | } |
| 4904 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4905 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
| 4906 | { |
| 4907 | if (!mutex_is_locked(mutex)) |
| 4908 | return false; |
| 4909 | |
| 4910 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
| 4911 | return mutex->owner == task; |
| 4912 | #else |
| 4913 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ |
| 4914 | return false; |
| 4915 | #endif |
| 4916 | } |
| 4917 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4918 | static unsigned long |
| 4919 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4920 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4921 | struct drm_i915_private *dev_priv = |
| 4922 | container_of(shrinker, |
| 4923 | struct drm_i915_private, |
| 4924 | mm.inactive_shrinker); |
| 4925 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4926 | struct drm_i915_gem_object *obj; |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4927 | bool unlock = true; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4928 | unsigned long count; |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4929 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4930 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 4931 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
Daniel Vetter | d322704 | 2013-09-25 14:00:02 +0200 | [diff] [blame] | 4932 | return 0; |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4933 | |
Daniel Vetter | 677feac | 2012-12-19 14:33:45 +0100 | [diff] [blame] | 4934 | if (dev_priv->mm.shrinker_no_lock_stealing) |
Daniel Vetter | d322704 | 2013-09-25 14:00:02 +0200 | [diff] [blame] | 4935 | return 0; |
Daniel Vetter | 677feac | 2012-12-19 14:33:45 +0100 | [diff] [blame] | 4936 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4937 | unlock = false; |
| 4938 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4939 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4940 | count = 0; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4941 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 4942 | if (obj->pages_pin_count == 0) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4943 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 4944 | |
| 4945 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 4946 | if (obj->active) |
| 4947 | continue; |
| 4948 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4949 | if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4950 | count += obj->base.size >> PAGE_SHIFT; |
Ben Widawsky | fcb4a57 | 2013-07-31 16:59:57 -0700 | [diff] [blame] | 4951 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4952 | |
Chris Wilson | 5774506 | 2012-11-21 13:04:04 +0000 | [diff] [blame] | 4953 | if (unlock) |
| 4954 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 4955 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 4956 | return count; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4957 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4958 | |
| 4959 | /* All the new VM stuff */ |
| 4960 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 4961 | struct i915_address_space *vm) |
| 4962 | { |
| 4963 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 4964 | struct i915_vma *vma; |
| 4965 | |
Ben Widawsky | 6f42532 | 2013-12-06 14:10:48 -0800 | [diff] [blame] | 4966 | if (!dev_priv->mm.aliasing_ppgtt || |
| 4967 | vm == &dev_priv->mm.aliasing_ppgtt->base) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4968 | vm = &dev_priv->gtt.base; |
| 4969 | |
| 4970 | BUG_ON(list_empty(&o->vma_list)); |
| 4971 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
| 4972 | if (vma->vm == vm) |
| 4973 | return vma->node.start; |
| 4974 | |
| 4975 | } |
| 4976 | return -1; |
| 4977 | } |
| 4978 | |
| 4979 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 4980 | struct i915_address_space *vm) |
| 4981 | { |
| 4982 | struct i915_vma *vma; |
| 4983 | |
| 4984 | list_for_each_entry(vma, &o->vma_list, vma_link) |
Ben Widawsky | 8b9c2b9 | 2013-07-31 17:00:16 -0700 | [diff] [blame] | 4985 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4986 | return true; |
| 4987 | |
| 4988 | return false; |
| 4989 | } |
| 4990 | |
| 4991 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 4992 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 4993 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4994 | |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 4995 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 4996 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 4997 | return true; |
| 4998 | |
| 4999 | return false; |
| 5000 | } |
| 5001 | |
| 5002 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 5003 | struct i915_address_space *vm) |
| 5004 | { |
| 5005 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5006 | struct i915_vma *vma; |
| 5007 | |
Ben Widawsky | 6f42532 | 2013-12-06 14:10:48 -0800 | [diff] [blame] | 5008 | if (!dev_priv->mm.aliasing_ppgtt || |
| 5009 | vm == &dev_priv->mm.aliasing_ppgtt->base) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5010 | vm = &dev_priv->gtt.base; |
| 5011 | |
| 5012 | BUG_ON(list_empty(&o->vma_list)); |
| 5013 | |
| 5014 | list_for_each_entry(vma, &o->vma_list, vma_link) |
| 5015 | if (vma->vm == vm) |
| 5016 | return vma->node.size; |
| 5017 | |
| 5018 | return 0; |
| 5019 | } |
| 5020 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5021 | static unsigned long |
| 5022 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) |
| 5023 | { |
| 5024 | struct drm_i915_private *dev_priv = |
| 5025 | container_of(shrinker, |
| 5026 | struct drm_i915_private, |
| 5027 | mm.inactive_shrinker); |
| 5028 | struct drm_device *dev = dev_priv->dev; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5029 | unsigned long freed; |
| 5030 | bool unlock = true; |
| 5031 | |
| 5032 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 5033 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) |
Daniel Vetter | d322704 | 2013-09-25 14:00:02 +0200 | [diff] [blame] | 5034 | return SHRINK_STOP; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5035 | |
| 5036 | if (dev_priv->mm.shrinker_no_lock_stealing) |
Daniel Vetter | d322704 | 2013-09-25 14:00:02 +0200 | [diff] [blame] | 5037 | return SHRINK_STOP; |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5038 | |
| 5039 | unlock = false; |
| 5040 | } |
| 5041 | |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5042 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
| 5043 | if (freed < sc->nr_to_scan) |
| 5044 | freed += __i915_gem_shrink(dev_priv, |
| 5045 | sc->nr_to_scan - freed, |
| 5046 | false); |
| 5047 | if (freed < sc->nr_to_scan) |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5048 | freed += i915_gem_shrink_all(dev_priv); |
| 5049 | |
| 5050 | if (unlock) |
| 5051 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9973b4 | 2013-10-04 10:33:00 +0100 | [diff] [blame] | 5052 | |
Dave Chinner | 7dc19d5 | 2013-08-28 10:18:11 +1000 | [diff] [blame] | 5053 | return freed; |
| 5054 | } |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5055 | |
| 5056 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
| 5057 | { |
| 5058 | struct i915_vma *vma; |
| 5059 | |
| 5060 | if (WARN_ON(list_empty(&obj->vma_list))) |
| 5061 | return NULL; |
| 5062 | |
| 5063 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
Ben Widawsky | 6e164c3 | 2013-12-06 14:10:49 -0800 | [diff] [blame] | 5064 | if (vma->vm != obj_to_ggtt(obj)) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5065 | return NULL; |
| 5066 | |
| 5067 | return vma; |
| 5068 | } |