Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 63 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 72 | #include <ttm/ttm_execbuf_util.h> |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 73 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 74 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 91 | extern int radeon_tv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 92 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 93 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 94 | extern int radeon_hw_i2c; |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 95 | extern int radeon_pcie_gen2; |
Alex Deucher | a18cee1 | 2011-11-01 14:20:30 -0400 | [diff] [blame] | 96 | extern int radeon_msi; |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 97 | extern int radeon_lockup_timeout; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 98 | extern int radeon_fastfb; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 99 | extern int radeon_dpm; |
Alex Deucher | 1294d4a | 2013-07-16 15:58:50 -0400 | [diff] [blame] | 100 | extern int radeon_aspm; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 101 | extern int radeon_runtime_pm; |
Alex Deucher | 363eb0b | 2014-01-08 17:55:08 -0500 | [diff] [blame] | 102 | extern int radeon_hard_reset; |
Christian König | c1c4413 | 2014-06-05 23:47:32 -0400 | [diff] [blame^] | 103 | extern int radeon_vm_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | |
| 105 | /* |
| 106 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 107 | * symbol; |
| 108 | */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 109 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 110 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 111 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 112 | #define RADEON_IB_POOL_SIZE 16 |
| 113 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
| 114 | #define RADEONFB_CONN_LIMIT 4 |
| 115 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 116 | |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 117 | /* fence seq are set to this number when signaled */ |
| 118 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 119 | |
| 120 | /* internal ring indices */ |
| 121 | /* r1xx+ has gfx CP ring */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 122 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 123 | |
| 124 | /* cayman has 2 compute CP rings */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 125 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
| 126 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 127 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 128 | /* R600+ has an async dma ring */ |
| 129 | #define R600_RING_TYPE_DMA_INDEX 3 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 130 | /* cayman add a second async dma ring */ |
| 131 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 132 | |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 133 | /* R600+ */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 134 | #define R600_RING_TYPE_UVD_INDEX 5 |
| 135 | |
| 136 | /* TN+ */ |
| 137 | #define TN_RING_TYPE_VCE1_INDEX 6 |
| 138 | #define TN_RING_TYPE_VCE2_INDEX 7 |
| 139 | |
| 140 | /* max number of rings */ |
| 141 | #define RADEON_NUM_RINGS 8 |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 142 | |
Christian König | 1c61eae | 2014-02-18 01:50:22 -0700 | [diff] [blame] | 143 | /* number of hw syncs before falling back on blocking */ |
| 144 | #define RADEON_NUM_SYNCS 4 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 145 | |
Christian König | 8f53492 | 2014-02-18 11:37:20 +0100 | [diff] [blame] | 146 | /* number of hw syncs before falling back on blocking */ |
| 147 | #define RADEON_NUM_SYNCS 4 |
| 148 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 149 | /* hardcode those limit for now */ |
Christian König | ca19f21 | 2012-09-11 16:09:59 +0200 | [diff] [blame] | 150 | #define RADEON_VA_IB_OFFSET (1 << 20) |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 151 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
| 152 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 153 | |
Alex Deucher | 1a0041b | 2013-10-02 13:01:36 -0400 | [diff] [blame] | 154 | /* hard reset data */ |
| 155 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
| 156 | |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 157 | /* reset flags */ |
| 158 | #define RADEON_RESET_GFX (1 << 0) |
| 159 | #define RADEON_RESET_COMPUTE (1 << 1) |
| 160 | #define RADEON_RESET_DMA (1 << 2) |
Alex Deucher | 9ff0744 | 2013-01-18 12:18:17 -0500 | [diff] [blame] | 161 | #define RADEON_RESET_CP (1 << 3) |
| 162 | #define RADEON_RESET_GRBM (1 << 4) |
| 163 | #define RADEON_RESET_DMA1 (1 << 5) |
| 164 | #define RADEON_RESET_RLC (1 << 6) |
| 165 | #define RADEON_RESET_SEM (1 << 7) |
| 166 | #define RADEON_RESET_IH (1 << 8) |
| 167 | #define RADEON_RESET_VMC (1 << 9) |
| 168 | #define RADEON_RESET_MC (1 << 10) |
| 169 | #define RADEON_RESET_DISPLAY (1 << 11) |
Alex Deucher | ec46c76 | 2013-01-03 12:07:30 -0500 | [diff] [blame] | 170 | |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 171 | /* CG block flags */ |
| 172 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
| 173 | #define RADEON_CG_BLOCK_MC (1 << 1) |
| 174 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
| 175 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
| 176 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
| 177 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
Alex Deucher | e16866e | 2013-08-08 19:34:07 -0400 | [diff] [blame] | 178 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 179 | |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 180 | /* CG flags */ |
| 181 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
| 182 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
| 183 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
| 184 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
| 185 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
| 186 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
| 187 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
| 188 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
| 189 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
| 190 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
| 191 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
| 192 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
| 193 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
| 194 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
| 195 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
| 196 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
| 197 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
| 198 | |
| 199 | /* PG flags */ |
Alex Deucher | 2b19d17 | 2013-09-04 16:58:29 -0400 | [diff] [blame] | 200 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 201 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
| 202 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
| 203 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
| 204 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
| 205 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
| 206 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
| 207 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
| 208 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
| 209 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
| 210 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
| 211 | |
Alex Deucher | 9e05fa1 | 2013-01-24 10:06:33 -0500 | [diff] [blame] | 212 | /* max cursor sizes (in pixels) */ |
| 213 | #define CURSOR_WIDTH 64 |
| 214 | #define CURSOR_HEIGHT 64 |
| 215 | |
| 216 | #define CIK_CURSOR_WIDTH 128 |
| 217 | #define CIK_CURSOR_HEIGHT 128 |
| 218 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | /* |
| 220 | * Errata workarounds. |
| 221 | */ |
| 222 | enum radeon_pll_errata { |
| 223 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 224 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 225 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 226 | }; |
| 227 | |
| 228 | |
| 229 | struct radeon_device; |
| 230 | |
| 231 | |
| 232 | /* |
| 233 | * BIOS. |
| 234 | */ |
| 235 | bool radeon_get_bios(struct radeon_device *rdev); |
| 236 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 237 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 238 | * Dummy page |
| 239 | */ |
| 240 | struct radeon_dummy_page { |
| 241 | struct page *page; |
| 242 | dma_addr_t addr; |
| 243 | }; |
| 244 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 245 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 246 | |
| 247 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 248 | /* |
| 249 | * Clocks |
| 250 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | struct radeon_clock { |
| 252 | struct radeon_pll p1pll; |
| 253 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 254 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | struct radeon_pll spll; |
| 256 | struct radeon_pll mpll; |
| 257 | /* 10 Khz units */ |
| 258 | uint32_t default_mclk; |
| 259 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 260 | uint32_t default_dispclk; |
Alex Deucher | 4489cd62 | 2013-03-22 15:59:10 -0400 | [diff] [blame] | 261 | uint32_t current_dispclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 262 | uint32_t dp_extclk; |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 263 | uint32_t max_pixel_clock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 264 | }; |
| 265 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 266 | /* |
| 267 | * Power management |
| 268 | */ |
| 269 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 270 | int radeon_pm_late_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 271 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 272 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 273 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 274 | void radeon_pm_resume(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 275 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 276 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Christian König | 7062ab6 | 2013-04-08 12:41:31 +0200 | [diff] [blame] | 277 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
| 278 | u8 clock_type, |
| 279 | u32 clock, |
| 280 | bool strobe_mode, |
| 281 | struct atom_clock_dividers *dividers); |
Alex Deucher | eaa778a | 2013-02-13 16:38:25 -0500 | [diff] [blame] | 282 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
| 283 | u32 clock, |
| 284 | bool strobe_mode, |
| 285 | struct atom_mpll_param *mpll_param); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 286 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 287 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
| 288 | u16 voltage_level, u8 voltage_type, |
| 289 | u32 *gpio_value, u32 *gpio_mask); |
| 290 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
| 291 | u32 eng_clock, u32 mem_clock); |
| 292 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
| 293 | u8 voltage_type, u16 *voltage_step); |
Alex Deucher | 4a6369e | 2013-04-12 14:04:10 -0400 | [diff] [blame] | 294 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 295 | u16 voltage_id, u16 *voltage); |
Alex Deucher | beb79f4 | 2013-02-19 17:14:43 -0500 | [diff] [blame] | 296 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
| 297 | u16 *voltage, |
| 298 | u16 leakage_idx); |
Alex Deucher | cc8dbbb | 2013-08-14 01:03:41 -0400 | [diff] [blame] | 299 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
| 300 | u16 *leakage_id); |
| 301 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
| 302 | u16 *vddc, u16 *vddci, |
| 303 | u16 virtual_voltage_id, |
| 304 | u16 vbios_voltage_id); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 305 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
| 306 | u8 voltage_type, |
| 307 | u16 nominal_voltage, |
| 308 | u16 *true_voltage); |
| 309 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
| 310 | u8 voltage_type, u16 *min_voltage); |
| 311 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
| 312 | u8 voltage_type, u16 *max_voltage); |
| 313 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
Alex Deucher | 6517194 | 2013-02-13 17:29:54 -0500 | [diff] [blame] | 314 | u8 voltage_type, u8 voltage_mode, |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 315 | struct atom_voltage_table *voltage_table); |
Alex Deucher | 58653ab | 2013-02-13 17:04:59 -0500 | [diff] [blame] | 316 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
| 317 | u8 voltage_type, u8 voltage_mode); |
Alex Deucher | ae5b0ab | 2013-06-24 10:50:34 -0400 | [diff] [blame] | 318 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
| 319 | u32 mem_clock); |
| 320 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
| 321 | u32 mem_clock); |
| 322 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
| 323 | u8 module_index, |
| 324 | struct atom_mc_reg_table *reg_table); |
| 325 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
| 326 | u8 module_index, struct atom_memory_info *mem_info); |
| 327 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
| 328 | bool gddr5, u8 module_index, |
| 329 | struct atom_memory_clock_range_table *mclk_range_table); |
| 330 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 331 | u16 voltage_id, u16 *voltage); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 332 | void rs690_pm_info(struct radeon_device *rdev); |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 333 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
| 334 | unsigned *bankh, unsigned *mtaspect, |
| 335 | unsigned *tile_split); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 336 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | /* |
| 338 | * Fences. |
| 339 | */ |
| 340 | struct radeon_fence_driver { |
| 341 | uint32_t scratch_reg; |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 342 | uint64_t gpu_addr; |
| 343 | volatile uint32_t *cpu_addr; |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 344 | /* sync_seq is protected by ring emission lock */ |
| 345 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 346 | atomic64_t last_seq; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 347 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | struct radeon_fence { |
| 351 | struct radeon_device *rdev; |
| 352 | struct kref kref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 353 | /* protected by radeon_fence.lock */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 354 | uint64_t seq; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 355 | /* RB, DMA, etc. */ |
Jerome Glisse | bb63556 | 2012-05-09 15:34:46 +0200 | [diff] [blame] | 356 | unsigned ring; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 357 | }; |
| 358 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 359 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
| 360 | int radeon_fence_driver_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
Jerome Glisse | 76903b9 | 2012-12-17 10:29:06 -0500 | [diff] [blame] | 362 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 363 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 364 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 365 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 366 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
Christian König | 3761552 | 2014-02-18 15:58:31 +0100 | [diff] [blame] | 367 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
| 368 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 369 | int radeon_fence_wait_any(struct radeon_device *rdev, |
| 370 | struct radeon_fence **fences, |
| 371 | bool intr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 372 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 373 | void radeon_fence_unref(struct radeon_fence **fence); |
Jerome Glisse | 3b7a2b2 | 2012-05-09 15:34:47 +0200 | [diff] [blame] | 374 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
Christian König | 68e250b | 2012-05-10 15:57:31 +0200 | [diff] [blame] | 375 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
| 376 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
| 377 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
| 378 | struct radeon_fence *b) |
| 379 | { |
| 380 | if (!a) { |
| 381 | return b; |
| 382 | } |
| 383 | |
| 384 | if (!b) { |
| 385 | return a; |
| 386 | } |
| 387 | |
| 388 | BUG_ON(a->ring != b->ring); |
| 389 | |
| 390 | if (a->seq > b->seq) { |
| 391 | return a; |
| 392 | } else { |
| 393 | return b; |
| 394 | } |
| 395 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 397 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
| 398 | struct radeon_fence *b) |
| 399 | { |
| 400 | if (!a) { |
| 401 | return false; |
| 402 | } |
| 403 | |
| 404 | if (!b) { |
| 405 | return true; |
| 406 | } |
| 407 | |
| 408 | BUG_ON(a->ring != b->ring); |
| 409 | |
| 410 | return a->seq < b->seq; |
| 411 | } |
| 412 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 413 | /* |
| 414 | * Tiling registers |
| 415 | */ |
| 416 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 417 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 418 | }; |
| 419 | |
| 420 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 421 | |
| 422 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 423 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 424 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 425 | struct radeon_mman { |
| 426 | struct ttm_bo_global_ref bo_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 427 | struct drm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 428 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 429 | bool mem_global_referenced; |
| 430 | bool initialized; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 431 | |
| 432 | #if defined(CONFIG_DEBUG_FS) |
| 433 | struct dentry *vram; |
Christian König | dd66d20 | 2013-12-18 21:07:40 +0100 | [diff] [blame] | 434 | struct dentry *gtt; |
Christian König | 2014b56 | 2013-12-18 21:07:39 +0100 | [diff] [blame] | 435 | #endif |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 436 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 437 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 438 | /* bo virtual address in a specific vm */ |
| 439 | struct radeon_bo_va { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 440 | /* protected by bo being reserved */ |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 441 | struct list_head bo_list; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 442 | uint64_t soffset; |
| 443 | uint64_t eoffset; |
| 444 | uint32_t flags; |
| 445 | bool valid; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 446 | unsigned ref_count; |
| 447 | |
| 448 | /* protected by vm mutex */ |
| 449 | struct list_head vm_list; |
| 450 | |
| 451 | /* constant after initialization */ |
| 452 | struct radeon_vm *vm; |
| 453 | struct radeon_bo *bo; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 454 | }; |
| 455 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 456 | struct radeon_bo { |
| 457 | /* Protected by gem.mutex */ |
| 458 | struct list_head list; |
| 459 | /* Protected by tbo.reserved */ |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 460 | u32 initial_domain; |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 461 | u32 placements[3]; |
| 462 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 463 | struct ttm_buffer_object tbo; |
| 464 | struct ttm_bo_kmap_obj kmap; |
| 465 | unsigned pin_count; |
| 466 | void *kptr; |
| 467 | u32 tiling_flags; |
| 468 | u32 pitch; |
| 469 | int surface_reg; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 470 | /* list of all virtual address to which this bo |
| 471 | * is associated to |
| 472 | */ |
| 473 | struct list_head va; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 474 | /* Constant after initialization */ |
| 475 | struct radeon_device *rdev; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 476 | struct drm_gem_object gem_base; |
Dave Airlie | 63bc620 | 2012-05-31 13:52:53 +0100 | [diff] [blame] | 477 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 478 | struct ttm_bo_kmap_obj dma_buf_vmap; |
| 479 | pid_t pid; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 480 | }; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 481 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 482 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 483 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
| 484 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 485 | /* sub-allocation manager, it has to be protected by another lock. |
| 486 | * By conception this is an helper for other part of the driver |
| 487 | * like the indirect buffer or semaphore, which both have their |
| 488 | * locking. |
| 489 | * |
| 490 | * Principe is simple, we keep a list of sub allocation in offset |
| 491 | * order (first entry has offset == 0, last entry has the highest |
| 492 | * offset). |
| 493 | * |
| 494 | * When allocating new object we first check if there is room at |
| 495 | * the end total_size - (last_object_offset + last_object_size) >= |
| 496 | * alloc_size. If so we allocate new object there. |
| 497 | * |
| 498 | * When there is not enough room at the end, we start waiting for |
| 499 | * each sub object until we reach object_offset+object_size >= |
| 500 | * alloc_size, this object then become the sub object we return. |
| 501 | * |
| 502 | * Alignment can't be bigger than page size. |
| 503 | * |
| 504 | * Hole are not considered for allocation to keep things simple. |
| 505 | * Assumption is that there won't be hole (all object on same |
| 506 | * alignment). |
| 507 | */ |
| 508 | struct radeon_sa_manager { |
Christian König | bfb38d3 | 2012-07-11 21:07:57 +0200 | [diff] [blame] | 509 | wait_queue_head_t wq; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 510 | struct radeon_bo *bo; |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 511 | struct list_head *hole; |
| 512 | struct list_head flist[RADEON_NUM_RINGS]; |
| 513 | struct list_head olist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 514 | unsigned size; |
| 515 | uint64_t gpu_addr; |
| 516 | void *cpu_ptr; |
| 517 | uint32_t domain; |
Alex Deucher | 6c4f978 | 2013-07-12 15:46:09 -0400 | [diff] [blame] | 518 | uint32_t align; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 519 | }; |
| 520 | |
| 521 | struct radeon_sa_bo; |
| 522 | |
| 523 | /* sub-allocation buffer */ |
| 524 | struct radeon_sa_bo { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 525 | struct list_head olist; |
| 526 | struct list_head flist; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 527 | struct radeon_sa_manager *manager; |
Christian König | e6661a9 | 2012-05-09 15:34:52 +0200 | [diff] [blame] | 528 | unsigned soffset; |
| 529 | unsigned eoffset; |
Christian König | 557017a | 2012-05-09 15:34:54 +0200 | [diff] [blame] | 530 | struct radeon_fence *fence; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 531 | }; |
| 532 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 533 | /* |
| 534 | * GEM objects. |
| 535 | */ |
| 536 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 537 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 538 | struct list_head objects; |
| 539 | }; |
| 540 | |
| 541 | int radeon_gem_init(struct radeon_device *rdev); |
| 542 | void radeon_gem_fini(struct radeon_device *rdev); |
| 543 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 544 | int alignment, int initial_domain, |
| 545 | bool discardable, bool kernel, |
| 546 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 547 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 548 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 549 | struct drm_device *dev, |
| 550 | struct drm_mode_create_dumb *args); |
| 551 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 552 | struct drm_device *dev, |
| 553 | uint32_t handle, uint64_t *offset_p); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 554 | |
| 555 | /* |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 556 | * Semaphores. |
| 557 | */ |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 558 | struct radeon_semaphore { |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 559 | struct radeon_sa_bo *sa_bo; |
| 560 | signed waiters; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 561 | uint64_t gpu_addr; |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 562 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 563 | }; |
| 564 | |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 565 | int radeon_semaphore_create(struct radeon_device *rdev, |
| 566 | struct radeon_semaphore **semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 567 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 568 | struct radeon_semaphore *semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 569 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 570 | struct radeon_semaphore *semaphore); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 571 | void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, |
| 572 | struct radeon_fence *fence); |
Christian König | 8f676c4 | 2012-05-02 15:11:18 +0200 | [diff] [blame] | 573 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
| 574 | struct radeon_semaphore *semaphore, |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 575 | int waiting_ring); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 576 | void radeon_semaphore_free(struct radeon_device *rdev, |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 577 | struct radeon_semaphore **semaphore, |
Jerome Glisse | a8c0594 | 2012-05-09 15:34:57 +0200 | [diff] [blame] | 578 | struct radeon_fence *fence); |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 579 | |
| 580 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 581 | * GART structures, functions & helpers |
| 582 | */ |
| 583 | struct radeon_mc; |
| 584 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 585 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 586 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Alex Deucher | 003cefe | 2011-09-16 12:04:08 -0400 | [diff] [blame] | 587 | #define RADEON_GPU_PAGE_SHIFT 12 |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 588 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 589 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 590 | struct radeon_gart { |
| 591 | dma_addr_t table_addr; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 592 | struct radeon_bo *robj; |
| 593 | void *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 594 | unsigned num_gpu_pages; |
| 595 | unsigned num_cpu_pages; |
| 596 | unsigned table_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 597 | struct page **pages; |
| 598 | dma_addr_t *pages_addr; |
| 599 | bool ready; |
| 600 | }; |
| 601 | |
| 602 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 603 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 604 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 605 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 606 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
| 607 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 608 | int radeon_gart_init(struct radeon_device *rdev); |
| 609 | void radeon_gart_fini(struct radeon_device *rdev); |
| 610 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 611 | int pages); |
| 612 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 613 | int pages, struct page **pagelist, |
| 614 | dma_addr_t *dma_addr); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 615 | void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 616 | |
| 617 | |
| 618 | /* |
| 619 | * GPU MC structures, functions & helpers |
| 620 | */ |
| 621 | struct radeon_mc { |
| 622 | resource_size_t aper_size; |
| 623 | resource_size_t aper_base; |
| 624 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 625 | /* for some chips with <= 32MB we need to lie |
| 626 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 627 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 628 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 629 | u64 gtt_size; |
| 630 | u64 gtt_start; |
| 631 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 632 | u64 vram_start; |
| 633 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 634 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 635 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 636 | int vram_mtrr; |
| 637 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 638 | bool igp_sideport_enabled; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 639 | u64 gtt_base_align; |
Alex Deucher | 9ed8b1f | 2013-04-08 11:13:01 -0400 | [diff] [blame] | 640 | u64 mc_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 641 | }; |
| 642 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 643 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 644 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 645 | |
| 646 | /* |
| 647 | * GPU scratch registers structures, functions & helpers |
| 648 | */ |
| 649 | struct radeon_scratch { |
| 650 | unsigned num_reg; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 651 | uint32_t reg_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 652 | bool free[32]; |
| 653 | uint32_t reg[32]; |
| 654 | }; |
| 655 | |
| 656 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 657 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 658 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 659 | /* |
| 660 | * GPU doorbell structures, functions & helpers |
| 661 | */ |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 662 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
| 663 | |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 664 | struct radeon_doorbell { |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 665 | /* doorbell mmio */ |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 666 | resource_size_t base; |
| 667 | resource_size_t size; |
| 668 | u32 __iomem *ptr; |
| 669 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
| 670 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 671 | }; |
| 672 | |
| 673 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
| 674 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 675 | |
| 676 | /* |
| 677 | * IRQS. |
| 678 | */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 679 | |
Christian König | fa7f517 | 2014-06-03 18:13:21 -0400 | [diff] [blame] | 680 | struct radeon_flip_work { |
| 681 | struct work_struct flip_work; |
| 682 | struct work_struct unpin_work; |
| 683 | struct radeon_device *rdev; |
| 684 | int crtc_id; |
| 685 | struct drm_framebuffer *fb; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 686 | struct drm_pending_vblank_event *event; |
Christian König | fa7f517 | 2014-06-03 18:13:21 -0400 | [diff] [blame] | 687 | struct radeon_bo *old_rbo; |
| 688 | struct radeon_bo *new_rbo; |
| 689 | struct radeon_fence *fence; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 690 | }; |
| 691 | |
| 692 | struct r500_irq_stat_regs { |
| 693 | u32 disp_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 694 | u32 hdmi0_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 695 | }; |
| 696 | |
| 697 | struct r600_irq_stat_regs { |
| 698 | u32 disp_int; |
| 699 | u32 disp_int_cont; |
| 700 | u32 disp_int_cont2; |
| 701 | u32 d1grph_int; |
| 702 | u32 d2grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 703 | u32 hdmi0_status; |
| 704 | u32 hdmi1_status; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 705 | }; |
| 706 | |
| 707 | struct evergreen_irq_stat_regs { |
| 708 | u32 disp_int; |
| 709 | u32 disp_int_cont; |
| 710 | u32 disp_int_cont2; |
| 711 | u32 disp_int_cont3; |
| 712 | u32 disp_int_cont4; |
| 713 | u32 disp_int_cont5; |
| 714 | u32 d1grph_int; |
| 715 | u32 d2grph_int; |
| 716 | u32 d3grph_int; |
| 717 | u32 d4grph_int; |
| 718 | u32 d5grph_int; |
| 719 | u32 d6grph_int; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 720 | u32 afmt_status1; |
| 721 | u32 afmt_status2; |
| 722 | u32 afmt_status3; |
| 723 | u32 afmt_status4; |
| 724 | u32 afmt_status5; |
| 725 | u32 afmt_status6; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 726 | }; |
| 727 | |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 728 | struct cik_irq_stat_regs { |
| 729 | u32 disp_int; |
| 730 | u32 disp_int_cont; |
| 731 | u32 disp_int_cont2; |
| 732 | u32 disp_int_cont3; |
| 733 | u32 disp_int_cont4; |
| 734 | u32 disp_int_cont5; |
| 735 | u32 disp_int_cont6; |
Christian König | f5d636d | 2014-04-23 20:46:06 +0200 | [diff] [blame] | 736 | u32 d1grph_int; |
| 737 | u32 d2grph_int; |
| 738 | u32 d3grph_int; |
| 739 | u32 d4grph_int; |
| 740 | u32 d5grph_int; |
| 741 | u32 d6grph_int; |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 742 | }; |
| 743 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 744 | union radeon_irq_stat_regs { |
| 745 | struct r500_irq_stat_regs r500; |
| 746 | struct r600_irq_stat_regs r600; |
| 747 | struct evergreen_irq_stat_regs evergreen; |
Alex Deucher | a59781b | 2012-11-09 10:45:57 -0500 | [diff] [blame] | 748 | struct cik_irq_stat_regs cik; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 749 | }; |
| 750 | |
Alex Deucher | be0949f | 2014-04-08 11:28:54 -0400 | [diff] [blame] | 751 | #define RADEON_MAX_HPD_PINS 7 |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 752 | #define RADEON_MAX_CRTCS 6 |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 753 | #define RADEON_MAX_AFMT_BLOCKS 7 |
Ilija Hadzic | 54bd5206 | 2011-10-26 15:43:58 -0400 | [diff] [blame] | 754 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 755 | struct radeon_irq { |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 756 | bool installed; |
| 757 | spinlock_t lock; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 758 | atomic_t ring_int[RADEON_NUM_RINGS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 759 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 760 | atomic_t pflip[RADEON_MAX_CRTCS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 761 | wait_queue_head_t vblank_queue; |
| 762 | bool hpd[RADEON_MAX_HPD_PINS]; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 763 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
| 764 | union radeon_irq_stat_regs stat_regs; |
Alex Deucher | 4a6369e | 2013-04-12 14:04:10 -0400 | [diff] [blame] | 765 | bool dpm_thermal; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 766 | }; |
| 767 | |
| 768 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 769 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Alex Deucher | 1b37078 | 2011-11-17 20:13:28 -0500 | [diff] [blame] | 770 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
| 771 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 772 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 773 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 774 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
| 775 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
| 776 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
| 777 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 778 | |
| 779 | /* |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 780 | * CP & rings. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 781 | */ |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 782 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 783 | struct radeon_ib { |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 784 | struct radeon_sa_bo *sa_bo; |
| 785 | uint32_t length_dw; |
| 786 | uint64_t gpu_addr; |
| 787 | uint32_t *ptr; |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 788 | int ring; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 789 | struct radeon_fence *fence; |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 790 | struct radeon_vm *vm; |
Jerome Glisse | 68470ae | 2012-05-09 15:35:00 +0200 | [diff] [blame] | 791 | bool is_const_ib; |
| 792 | struct radeon_semaphore *semaphore; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 793 | }; |
| 794 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 795 | struct radeon_ring { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 796 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 797 | volatile uint32_t *ring; |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 798 | unsigned rptr_offs; |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 799 | unsigned rptr_save_reg; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 800 | u64 next_rptr_gpu_addr; |
| 801 | volatile u32 *next_rptr_cpu_addr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 802 | unsigned wptr; |
| 803 | unsigned wptr_old; |
| 804 | unsigned ring_size; |
| 805 | unsigned ring_free_dw; |
| 806 | int count_dw; |
Christian König | aee4aa7 | 2014-02-18 15:24:06 +0100 | [diff] [blame] | 807 | atomic_t last_rptr; |
| 808 | atomic64_t last_activity; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 809 | uint64_t gpu_addr; |
| 810 | uint32_t align_mask; |
| 811 | uint32_t ptr_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 812 | bool ready; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 813 | u32 nop; |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 814 | u32 idx; |
Jerome Glisse | 5f0839c | 2013-01-11 15:19:43 -0500 | [diff] [blame] | 815 | u64 last_semaphore_signal_addr; |
| 816 | u64 last_semaphore_wait_addr; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 817 | /* for CIK queues */ |
| 818 | u32 me; |
| 819 | u32 pipe; |
| 820 | u32 queue; |
| 821 | struct radeon_bo *mqd_obj; |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 822 | u32 doorbell_index; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 823 | unsigned wptr_offs; |
| 824 | }; |
| 825 | |
| 826 | struct radeon_mec { |
| 827 | struct radeon_bo *hpd_eop_obj; |
| 828 | u64 hpd_eop_gpu_addr; |
| 829 | u32 num_pipe; |
| 830 | u32 num_mec; |
| 831 | u32 num_queue; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 832 | }; |
| 833 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 834 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 835 | * VM |
| 836 | */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 837 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 838 | /* maximum number of VMIDs */ |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 839 | #define RADEON_NUM_VM 16 |
| 840 | |
Dmitry Cherkasov | fa87e62 | 2012-09-17 19:36:19 +0200 | [diff] [blame] | 841 | /* defines number of bits in page table versus page directory, |
| 842 | * a page is 4KB so we have 12 bits offset, 9 bits in the page |
| 843 | * table and the remaining 19 bits are in the page directory */ |
| 844 | #define RADEON_VM_BLOCK_SIZE 9 |
| 845 | |
| 846 | /* number of entries in page table */ |
| 847 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) |
| 848 | |
Alex Deucher | 1c01103 | 2013-07-12 15:56:02 -0400 | [diff] [blame] | 849 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
| 850 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
| 851 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
| 852 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
| 853 | |
Christian König | 24c1643 | 2013-10-30 11:51:09 -0400 | [diff] [blame] | 854 | #define R600_PTE_VALID (1 << 0) |
| 855 | #define R600_PTE_SYSTEM (1 << 1) |
| 856 | #define R600_PTE_SNOOPED (1 << 2) |
| 857 | #define R600_PTE_READABLE (1 << 5) |
| 858 | #define R600_PTE_WRITEABLE (1 << 6) |
| 859 | |
Christian König | ec3dbbc | 2014-05-10 12:17:55 +0200 | [diff] [blame] | 860 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
| 861 | #define R600_PTE_FRAG_4KB (0 << 7) |
| 862 | #define R600_PTE_FRAG_64KB (4 << 7) |
| 863 | #define R600_PTE_FRAG_256KB (6 << 7) |
| 864 | |
Christian König | 0e97703 | 2014-05-27 16:47:37 +0200 | [diff] [blame] | 865 | /* flags used for GART page table entries on R600+ */ |
| 866 | #define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \ |
| 867 | | R600_PTE_READABLE | R600_PTE_WRITEABLE) |
| 868 | |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 869 | struct radeon_vm_pt { |
| 870 | struct radeon_bo *bo; |
| 871 | uint64_t addr; |
| 872 | }; |
| 873 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 874 | struct radeon_vm { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 875 | struct list_head va; |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 876 | unsigned id; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 877 | |
| 878 | /* contains the page directory */ |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 879 | struct radeon_bo *page_directory; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 880 | uint64_t pd_gpu_addr; |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 881 | unsigned max_pde_used; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 882 | |
| 883 | /* array of page tables, one for each page directory entry */ |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 884 | struct radeon_vm_pt *page_tables; |
Christian König | 90a51a3 | 2012-10-09 13:31:17 +0200 | [diff] [blame] | 885 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 886 | struct mutex mutex; |
| 887 | /* last fence for cs using this vm */ |
| 888 | struct radeon_fence *fence; |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 889 | /* last flush or NULL if we still need to flush */ |
| 890 | struct radeon_fence *last_flush; |
Christian König | 593b263 | 2014-01-23 14:24:15 +0100 | [diff] [blame] | 891 | /* last use of vmid */ |
| 892 | struct radeon_fence *last_id_use; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 893 | }; |
| 894 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 895 | struct radeon_vm_manager { |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 896 | struct radeon_fence *active[RADEON_NUM_VM]; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 897 | uint32_t max_pfn; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 898 | /* number of VMIDs */ |
| 899 | unsigned nvm; |
| 900 | /* vram base address for page table entry */ |
| 901 | u64 vram_base_offset; |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 902 | /* is vm enabled? */ |
| 903 | bool enabled; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 904 | }; |
| 905 | |
| 906 | /* |
| 907 | * file private structure |
| 908 | */ |
| 909 | struct radeon_fpriv { |
| 910 | struct radeon_vm vm; |
| 911 | }; |
| 912 | |
| 913 | /* |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 914 | * R6xx+ IH ring |
| 915 | */ |
| 916 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 917 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 918 | volatile uint32_t *ring; |
| 919 | unsigned rptr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 920 | unsigned ring_size; |
| 921 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 922 | uint32_t ptr_mask; |
Christian Koenig | c20dc36 | 2012-05-16 21:45:24 +0200 | [diff] [blame] | 923 | atomic_t lock; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 924 | bool enabled; |
| 925 | }; |
| 926 | |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 927 | /* |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 928 | * RLC stuff |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 929 | */ |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 930 | #include "clearstate_defs.h" |
| 931 | |
| 932 | struct radeon_rlc { |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 933 | /* for power gating */ |
| 934 | struct radeon_bo *save_restore_obj; |
| 935 | uint64_t save_restore_gpu_addr; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 936 | volatile uint32_t *sr_ptr; |
Alex Deucher | 1fd1177 | 2013-04-17 17:53:50 -0400 | [diff] [blame] | 937 | const u32 *reg_list; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 938 | u32 reg_list_size; |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 939 | /* for clear state */ |
| 940 | struct radeon_bo *clear_state_obj; |
| 941 | uint64_t clear_state_gpu_addr; |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 942 | volatile uint32_t *cs_ptr; |
Alex Deucher | 1fd1177 | 2013-04-17 17:53:50 -0400 | [diff] [blame] | 943 | const struct cs_section_def *cs_data; |
Alex Deucher | 22c775c | 2013-07-23 09:41:05 -0400 | [diff] [blame] | 944 | u32 clear_state_size; |
| 945 | /* for cp tables */ |
| 946 | struct radeon_bo *cp_table_obj; |
| 947 | uint64_t cp_table_gpu_addr; |
| 948 | volatile uint32_t *cp_table_ptr; |
| 949 | u32 cp_table_size; |
Alex Deucher | 347e759 | 2012-03-20 17:18:21 -0400 | [diff] [blame] | 950 | }; |
| 951 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 952 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 953 | struct radeon_ib *ib, struct radeon_vm *vm, |
| 954 | unsigned size); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 955 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 956 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 957 | struct radeon_ib *const_ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 958 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 959 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 960 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 961 | /* Ring access between begin & end cannot sleep */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 962 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
| 963 | struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 964 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
| 965 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 966 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
| 967 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
| 968 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 969 | void radeon_ring_undo(struct radeon_ring *ring); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 970 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
| 971 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
Christian König | ff212f2 | 2014-02-18 14:52:33 +0100 | [diff] [blame] | 972 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
| 973 | struct radeon_ring *ring); |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 974 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 975 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 976 | uint32_t **data); |
| 977 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 978 | unsigned size, uint32_t *data); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 979 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
Alex Deucher | ea31bf6 | 2013-12-09 19:44:30 -0500 | [diff] [blame] | 980 | unsigned rptr_offs, u32 nop); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 981 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 982 | |
| 983 | |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 984 | /* r600 async dma */ |
| 985 | void r600_dma_stop(struct radeon_device *rdev); |
| 986 | int r600_dma_resume(struct radeon_device *rdev); |
| 987 | void r600_dma_fini(struct radeon_device *rdev); |
| 988 | |
Alex Deucher | 8c5fd7e | 2012-12-04 15:28:18 -0500 | [diff] [blame] | 989 | void cayman_dma_stop(struct radeon_device *rdev); |
| 990 | int cayman_dma_resume(struct radeon_device *rdev); |
| 991 | void cayman_dma_fini(struct radeon_device *rdev); |
| 992 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 993 | /* |
| 994 | * CS. |
| 995 | */ |
| 996 | struct radeon_cs_reloc { |
| 997 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 998 | struct radeon_bo *robj; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 999 | struct ttm_validate_buffer tv; |
| 1000 | uint64_t gpu_offset; |
Christian König | ce6758c | 2014-06-02 17:33:07 +0200 | [diff] [blame] | 1001 | unsigned prefered_domains; |
| 1002 | unsigned allowed_domains; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 1003 | uint32_t tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1004 | uint32_t handle; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1005 | }; |
| 1006 | |
| 1007 | struct radeon_cs_chunk { |
| 1008 | uint32_t chunk_id; |
| 1009 | uint32_t length_dw; |
| 1010 | uint32_t *kdata; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1011 | void __user *user_ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1012 | }; |
| 1013 | |
| 1014 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 1015 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1016 | struct radeon_device *rdev; |
| 1017 | struct drm_file *filp; |
| 1018 | /* chunks */ |
| 1019 | unsigned nchunks; |
| 1020 | struct radeon_cs_chunk *chunks; |
| 1021 | uint64_t *chunks_array; |
| 1022 | /* IB */ |
| 1023 | unsigned idx; |
| 1024 | /* relocations */ |
| 1025 | unsigned nrelocs; |
| 1026 | struct radeon_cs_reloc *relocs; |
| 1027 | struct radeon_cs_reloc **relocs_ptr; |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 1028 | struct radeon_cs_reloc *vm_bos; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1029 | struct list_head validated; |
Alex Deucher | cf4ccd0 | 2011-11-18 10:19:47 -0500 | [diff] [blame] | 1030 | unsigned dma_reloc_idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1031 | /* indices of various chunks */ |
| 1032 | int chunk_ib_idx; |
| 1033 | int chunk_relocs_idx; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1034 | int chunk_flags_idx; |
Alex Deucher | dfcf5f3 | 2012-03-20 17:18:14 -0400 | [diff] [blame] | 1035 | int chunk_const_ib_idx; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 1036 | struct radeon_ib ib; |
| 1037 | struct radeon_ib const_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1038 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1039 | unsigned family; |
Marek Olšák | e70f224 | 2011-10-25 01:38:45 +0200 | [diff] [blame] | 1040 | int parser_error; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 1041 | u32 cs_flags; |
| 1042 | u32 ring; |
| 1043 | s32 priority; |
Maarten Lankhorst | ecff665 | 2013-06-27 13:48:17 +0200 | [diff] [blame] | 1044 | struct ww_acquire_ctx ticket; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1045 | }; |
| 1046 | |
Maarten Lankhorst | 28a326c | 2013-10-09 14:36:57 +0200 | [diff] [blame] | 1047 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 1048 | { |
| 1049 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 1050 | |
| 1051 | if (ibc->kdata) |
| 1052 | return ibc->kdata[idx]; |
| 1053 | return p->ib.ptr[idx]; |
| 1054 | } |
| 1055 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1056 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1057 | struct radeon_cs_packet { |
| 1058 | unsigned idx; |
| 1059 | unsigned type; |
| 1060 | unsigned reg; |
| 1061 | unsigned opcode; |
| 1062 | int count; |
| 1063 | unsigned one_reg_wr; |
| 1064 | }; |
| 1065 | |
| 1066 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 1067 | struct radeon_cs_packet *pkt, |
| 1068 | unsigned idx, unsigned reg); |
| 1069 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 1070 | struct radeon_cs_packet *pkt); |
| 1071 | |
| 1072 | |
| 1073 | /* |
| 1074 | * AGP |
| 1075 | */ |
| 1076 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 1077 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 1078 | void radeon_agp_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1079 | void radeon_agp_fini(struct radeon_device *rdev); |
| 1080 | |
| 1081 | |
| 1082 | /* |
| 1083 | * Writeback |
| 1084 | */ |
| 1085 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1086 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1087 | volatile uint32_t *wb; |
| 1088 | uint64_t gpu_addr; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1089 | bool enabled; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 1090 | bool use_event; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1091 | }; |
| 1092 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1093 | #define RADEON_WB_SCRATCH_OFFSET 0 |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 1094 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1095 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 1096 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 1097 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
Alex Deucher | 4d75658 | 2012-09-27 15:08:35 -0400 | [diff] [blame] | 1098 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1099 | #define R600_WB_IH_WPTR_OFFSET 2048 |
Alex Deucher | f60cbd1 | 2012-12-04 15:27:33 -0500 | [diff] [blame] | 1100 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 1101 | #define R600_WB_EVENT_OFFSET 3072 |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 1102 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
| 1103 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1104 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1105 | /** |
| 1106 | * struct radeon_pm - power management datas |
| 1107 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 1108 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 1109 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 1110 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 1111 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 1112 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 1113 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 1114 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 1115 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1116 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1117 | * @needed_bandwidth: current bandwidth needs |
| 1118 | * |
| 1119 | * It keeps track of various data needed to take powermanagement decision. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1120 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1121 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 1122 | * (type of memory, bus size, efficiency, ...) |
| 1123 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1124 | |
| 1125 | enum radeon_pm_method { |
| 1126 | PM_METHOD_PROFILE, |
| 1127 | PM_METHOD_DYNPM, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1128 | PM_METHOD_DPM, |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1129 | }; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1130 | |
| 1131 | enum radeon_dynpm_state { |
| 1132 | DYNPM_STATE_DISABLED, |
| 1133 | DYNPM_STATE_MINIMUM, |
| 1134 | DYNPM_STATE_PAUSED, |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 1135 | DYNPM_STATE_ACTIVE, |
| 1136 | DYNPM_STATE_SUSPENDED, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1137 | }; |
| 1138 | enum radeon_dynpm_action { |
| 1139 | DYNPM_ACTION_NONE, |
| 1140 | DYNPM_ACTION_MINIMUM, |
| 1141 | DYNPM_ACTION_DOWNCLOCK, |
| 1142 | DYNPM_ACTION_UPCLOCK, |
| 1143 | DYNPM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1144 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1145 | |
| 1146 | enum radeon_voltage_type { |
| 1147 | VOLTAGE_NONE = 0, |
| 1148 | VOLTAGE_GPIO, |
| 1149 | VOLTAGE_VDDC, |
| 1150 | VOLTAGE_SW |
| 1151 | }; |
| 1152 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1153 | enum radeon_pm_state_type { |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1154 | /* not used for dpm */ |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1155 | POWER_STATE_TYPE_DEFAULT, |
| 1156 | POWER_STATE_TYPE_POWERSAVE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1157 | /* user selectable states */ |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1158 | POWER_STATE_TYPE_BATTERY, |
| 1159 | POWER_STATE_TYPE_BALANCED, |
| 1160 | POWER_STATE_TYPE_PERFORMANCE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1161 | /* internal states */ |
| 1162 | POWER_STATE_TYPE_INTERNAL_UVD, |
| 1163 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
| 1164 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
| 1165 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
| 1166 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
| 1167 | POWER_STATE_TYPE_INTERNAL_BOOT, |
| 1168 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
| 1169 | POWER_STATE_TYPE_INTERNAL_ACPI, |
| 1170 | POWER_STATE_TYPE_INTERNAL_ULV, |
Alex Deucher | edcaa5b | 2013-07-05 11:48:31 -0400 | [diff] [blame] | 1171 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1172 | }; |
| 1173 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1174 | enum radeon_pm_profile_type { |
| 1175 | PM_PROFILE_DEFAULT, |
| 1176 | PM_PROFILE_AUTO, |
| 1177 | PM_PROFILE_LOW, |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 1178 | PM_PROFILE_MID, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1179 | PM_PROFILE_HIGH, |
| 1180 | }; |
| 1181 | |
| 1182 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 1183 | #define PM_PROFILE_LOW_SH_IDX 1 |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 1184 | #define PM_PROFILE_MID_SH_IDX 2 |
| 1185 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 1186 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 1187 | #define PM_PROFILE_MID_MH_IDX 5 |
| 1188 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 1189 | #define PM_PROFILE_MAX 7 |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1190 | |
| 1191 | struct radeon_pm_profile { |
| 1192 | int dpms_off_ps_idx; |
| 1193 | int dpms_on_ps_idx; |
| 1194 | int dpms_off_cm_idx; |
| 1195 | int dpms_on_cm_idx; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 1196 | }; |
| 1197 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1198 | enum radeon_int_thermal_type { |
| 1199 | THERMAL_TYPE_NONE, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1200 | THERMAL_TYPE_EXTERNAL, |
| 1201 | THERMAL_TYPE_EXTERNAL_GPIO, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1202 | THERMAL_TYPE_RV6XX, |
| 1203 | THERMAL_TYPE_RV770, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1204 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1205 | THERMAL_TYPE_EVERGREEN, |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 1206 | THERMAL_TYPE_SUMO, |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 1207 | THERMAL_TYPE_NI, |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame] | 1208 | THERMAL_TYPE_SI, |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1209 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
Alex Deucher | 5115020 | 2012-12-18 22:07:14 -0500 | [diff] [blame] | 1210 | THERMAL_TYPE_CI, |
Alex Deucher | 16fbe00 | 2013-04-22 21:41:26 -0400 | [diff] [blame] | 1211 | THERMAL_TYPE_KV, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1212 | }; |
| 1213 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1214 | struct radeon_voltage { |
| 1215 | enum radeon_voltage_type type; |
| 1216 | /* gpio voltage */ |
| 1217 | struct radeon_gpio_rec gpio; |
| 1218 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 1219 | bool active_high; /* voltage drop is active when bit is high */ |
| 1220 | /* VDDC voltage */ |
| 1221 | u8 vddc_id; /* index into vddc voltage table */ |
| 1222 | u8 vddci_id; /* index into vddci voltage table */ |
| 1223 | bool vddci_enabled; |
| 1224 | /* r6xx+ sw */ |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1225 | u16 voltage; |
| 1226 | /* evergreen+ vddci */ |
| 1227 | u16 vddci; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1228 | }; |
| 1229 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1230 | /* clock mode flags */ |
| 1231 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 1232 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1233 | struct radeon_pm_clock_info { |
| 1234 | /* memory clock */ |
| 1235 | u32 mclk; |
| 1236 | /* engine clock */ |
| 1237 | u32 sclk; |
| 1238 | /* voltage info */ |
| 1239 | struct radeon_voltage voltage; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1240 | /* standardized clock flags */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1241 | u32 flags; |
| 1242 | }; |
| 1243 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1244 | /* state flags */ |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 1245 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1246 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1247 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 1248 | enum radeon_pm_state_type type; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 1249 | struct radeon_pm_clock_info *clock_info; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1250 | /* number of valid clock modes in this power state */ |
| 1251 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1252 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1253 | /* standardized state flags */ |
| 1254 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 1255 | u32 misc; /* vbios specific flags */ |
| 1256 | u32 misc2; /* vbios specific flags */ |
| 1257 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1258 | }; |
| 1259 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 1260 | /* |
| 1261 | * Some modes are overclocked by very low value, accept them |
| 1262 | */ |
| 1263 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 1264 | |
Alex Deucher | 2e9d4c0 | 2013-04-12 13:58:03 -0400 | [diff] [blame] | 1265 | enum radeon_dpm_auto_throttle_src { |
| 1266 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
| 1267 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
| 1268 | }; |
| 1269 | |
| 1270 | enum radeon_dpm_event_src { |
| 1271 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
| 1272 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
| 1273 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
| 1274 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
| 1275 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
| 1276 | }; |
| 1277 | |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1278 | #define RADEON_MAX_VCE_LEVELS 6 |
| 1279 | |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1280 | enum radeon_vce_level { |
| 1281 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
| 1282 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
| 1283 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
| 1284 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
| 1285 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
| 1286 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
| 1287 | }; |
| 1288 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1289 | struct radeon_ps { |
| 1290 | u32 caps; /* vbios flags */ |
| 1291 | u32 class; /* vbios flags */ |
| 1292 | u32 class2; /* vbios flags */ |
| 1293 | /* UVD clocks */ |
| 1294 | u32 vclk; |
| 1295 | u32 dclk; |
Alex Deucher | c4453e6 | 2013-05-15 15:53:57 -0400 | [diff] [blame] | 1296 | /* VCE clocks */ |
| 1297 | u32 evclk; |
| 1298 | u32 ecclk; |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1299 | bool vce_active; |
| 1300 | enum radeon_vce_level vce_level; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1301 | /* asic priv */ |
| 1302 | void *ps_priv; |
| 1303 | }; |
| 1304 | |
| 1305 | struct radeon_dpm_thermal { |
| 1306 | /* thermal interrupt work */ |
| 1307 | struct work_struct work; |
| 1308 | /* low temperature threshold */ |
| 1309 | int min_temp; |
| 1310 | /* high temperature threshold */ |
| 1311 | int max_temp; |
| 1312 | /* was interrupt low to high or high to low */ |
| 1313 | bool high_to_low; |
| 1314 | }; |
| 1315 | |
Alex Deucher | d22b7e4 | 2012-11-29 19:27:56 -0500 | [diff] [blame] | 1316 | enum radeon_clk_action |
| 1317 | { |
| 1318 | RADEON_SCLK_UP = 1, |
| 1319 | RADEON_SCLK_DOWN |
| 1320 | }; |
| 1321 | |
| 1322 | struct radeon_blacklist_clocks |
| 1323 | { |
| 1324 | u32 sclk; |
| 1325 | u32 mclk; |
| 1326 | enum radeon_clk_action action; |
| 1327 | }; |
| 1328 | |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1329 | struct radeon_clock_and_voltage_limits { |
| 1330 | u32 sclk; |
| 1331 | u32 mclk; |
Alex Deucher | cdf6e80 | 2013-10-23 16:13:42 -0400 | [diff] [blame] | 1332 | u16 vddc; |
| 1333 | u16 vddci; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1334 | }; |
| 1335 | |
| 1336 | struct radeon_clock_array { |
| 1337 | u32 count; |
| 1338 | u32 *values; |
| 1339 | }; |
| 1340 | |
| 1341 | struct radeon_clock_voltage_dependency_entry { |
| 1342 | u32 clk; |
| 1343 | u16 v; |
| 1344 | }; |
| 1345 | |
| 1346 | struct radeon_clock_voltage_dependency_table { |
| 1347 | u32 count; |
| 1348 | struct radeon_clock_voltage_dependency_entry *entries; |
| 1349 | }; |
| 1350 | |
Alex Deucher | ef976ec | 2013-05-06 11:31:04 -0400 | [diff] [blame] | 1351 | union radeon_cac_leakage_entry { |
| 1352 | struct { |
| 1353 | u16 vddc; |
| 1354 | u32 leakage; |
| 1355 | }; |
| 1356 | struct { |
| 1357 | u16 vddc1; |
| 1358 | u16 vddc2; |
| 1359 | u16 vddc3; |
| 1360 | }; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1361 | }; |
| 1362 | |
| 1363 | struct radeon_cac_leakage_table { |
| 1364 | u32 count; |
Alex Deucher | ef976ec | 2013-05-06 11:31:04 -0400 | [diff] [blame] | 1365 | union radeon_cac_leakage_entry *entries; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1366 | }; |
| 1367 | |
Alex Deucher | 929ee7a | 2013-03-20 12:30:25 -0400 | [diff] [blame] | 1368 | struct radeon_phase_shedding_limits_entry { |
| 1369 | u16 voltage; |
| 1370 | u32 sclk; |
| 1371 | u32 mclk; |
| 1372 | }; |
| 1373 | |
| 1374 | struct radeon_phase_shedding_limits_table { |
| 1375 | u32 count; |
| 1376 | struct radeon_phase_shedding_limits_entry *entries; |
| 1377 | }; |
| 1378 | |
Alex Deucher | 84a9d9e | 2013-04-19 19:11:37 -0400 | [diff] [blame] | 1379 | struct radeon_uvd_clock_voltage_dependency_entry { |
| 1380 | u32 vclk; |
| 1381 | u32 dclk; |
| 1382 | u16 v; |
| 1383 | }; |
| 1384 | |
| 1385 | struct radeon_uvd_clock_voltage_dependency_table { |
| 1386 | u8 count; |
| 1387 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
| 1388 | }; |
| 1389 | |
Alex Deucher | d29f013 | 2013-05-09 16:37:28 -0400 | [diff] [blame] | 1390 | struct radeon_vce_clock_voltage_dependency_entry { |
| 1391 | u32 ecclk; |
| 1392 | u32 evclk; |
| 1393 | u16 v; |
| 1394 | }; |
| 1395 | |
| 1396 | struct radeon_vce_clock_voltage_dependency_table { |
| 1397 | u8 count; |
| 1398 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
| 1399 | }; |
| 1400 | |
Alex Deucher | a5cb318 | 2013-03-20 13:00:18 -0400 | [diff] [blame] | 1401 | struct radeon_ppm_table { |
| 1402 | u8 ppm_design; |
| 1403 | u16 cpu_core_number; |
| 1404 | u32 platform_tdp; |
| 1405 | u32 small_ac_platform_tdp; |
| 1406 | u32 platform_tdc; |
| 1407 | u32 small_ac_platform_tdc; |
| 1408 | u32 apu_tdp; |
| 1409 | u32 dgpu_tdp; |
| 1410 | u32 dgpu_ulv_power; |
| 1411 | u32 tj_max; |
| 1412 | }; |
| 1413 | |
Alex Deucher | 58cb763 | 2013-05-06 12:15:33 -0400 | [diff] [blame] | 1414 | struct radeon_cac_tdp_table { |
| 1415 | u16 tdp; |
| 1416 | u16 configurable_tdp; |
| 1417 | u16 tdc; |
| 1418 | u16 battery_power_limit; |
| 1419 | u16 small_power_limit; |
| 1420 | u16 low_cac_leakage; |
| 1421 | u16 high_cac_leakage; |
| 1422 | u16 maximum_power_delivery_limit; |
| 1423 | }; |
| 1424 | |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1425 | struct radeon_dpm_dynamic_state { |
| 1426 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
| 1427 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
| 1428 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
Alex Deucher | dd621a2 | 2013-05-06 14:37:56 -0400 | [diff] [blame] | 1429 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
Alex Deucher | 4489cd62 | 2013-03-22 15:59:10 -0400 | [diff] [blame] | 1430 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
Alex Deucher | 84a9d9e | 2013-04-19 19:11:37 -0400 | [diff] [blame] | 1431 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
Alex Deucher | d29f013 | 2013-05-09 16:37:28 -0400 | [diff] [blame] | 1432 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
Alex Deucher | 94a914f | 2013-05-09 16:42:33 -0400 | [diff] [blame] | 1433 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
| 1434 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1435 | struct radeon_clock_array valid_sclk_values; |
| 1436 | struct radeon_clock_array valid_mclk_values; |
| 1437 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
| 1438 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
| 1439 | u32 mclk_sclk_ratio; |
| 1440 | u32 sclk_mclk_delta; |
| 1441 | u16 vddc_vddci_delta; |
| 1442 | u16 min_vddc_for_pcie_gen2; |
| 1443 | struct radeon_cac_leakage_table cac_leakage_table; |
Alex Deucher | 929ee7a | 2013-03-20 12:30:25 -0400 | [diff] [blame] | 1444 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
Alex Deucher | a5cb318 | 2013-03-20 13:00:18 -0400 | [diff] [blame] | 1445 | struct radeon_ppm_table *ppm_table; |
Alex Deucher | 58cb763 | 2013-05-06 12:15:33 -0400 | [diff] [blame] | 1446 | struct radeon_cac_tdp_table *cac_tdp_table; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1447 | }; |
| 1448 | |
| 1449 | struct radeon_dpm_fan { |
| 1450 | u16 t_min; |
| 1451 | u16 t_med; |
| 1452 | u16 t_high; |
| 1453 | u16 pwm_min; |
| 1454 | u16 pwm_med; |
| 1455 | u16 pwm_high; |
| 1456 | u8 t_hyst; |
| 1457 | u32 cycle_delay; |
| 1458 | u16 t_max; |
| 1459 | bool ucode_fan_control; |
| 1460 | }; |
| 1461 | |
Alex Deucher | 32ce465 | 2013-03-18 17:03:01 -0400 | [diff] [blame] | 1462 | enum radeon_pcie_gen { |
| 1463 | RADEON_PCIE_GEN1 = 0, |
| 1464 | RADEON_PCIE_GEN2 = 1, |
| 1465 | RADEON_PCIE_GEN3 = 2, |
| 1466 | RADEON_PCIE_GEN_INVALID = 0xffff |
| 1467 | }; |
| 1468 | |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1469 | enum radeon_dpm_forced_level { |
| 1470 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
| 1471 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
| 1472 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
| 1473 | }; |
| 1474 | |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1475 | struct radeon_vce_state { |
| 1476 | /* vce clocks */ |
| 1477 | u32 evclk; |
| 1478 | u32 ecclk; |
| 1479 | /* gpu clocks */ |
| 1480 | u32 sclk; |
| 1481 | u32 mclk; |
| 1482 | u8 clk_idx; |
| 1483 | u8 pstate; |
| 1484 | }; |
| 1485 | |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1486 | struct radeon_dpm { |
| 1487 | struct radeon_ps *ps; |
| 1488 | /* number of valid power states */ |
| 1489 | int num_ps; |
| 1490 | /* current power state that is active */ |
| 1491 | struct radeon_ps *current_ps; |
| 1492 | /* requested power state */ |
| 1493 | struct radeon_ps *requested_ps; |
| 1494 | /* boot up power state */ |
| 1495 | struct radeon_ps *boot_ps; |
| 1496 | /* default uvd power state */ |
| 1497 | struct radeon_ps *uvd_ps; |
Alex Deucher | 58bd2a8 | 2013-09-04 16:13:56 -0400 | [diff] [blame] | 1498 | /* vce requirements */ |
| 1499 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
| 1500 | enum radeon_vce_level vce_level; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1501 | enum radeon_pm_state_type state; |
| 1502 | enum radeon_pm_state_type user_state; |
| 1503 | u32 platform_caps; |
| 1504 | u32 voltage_response_time; |
| 1505 | u32 backbias_response_time; |
| 1506 | void *priv; |
| 1507 | u32 new_active_crtcs; |
| 1508 | int new_active_crtc_count; |
| 1509 | u32 current_active_crtcs; |
| 1510 | int current_active_crtc_count; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1511 | struct radeon_dpm_dynamic_state dyn_state; |
| 1512 | struct radeon_dpm_fan fan; |
| 1513 | u32 tdp_limit; |
| 1514 | u32 near_tdp_limit; |
Alex Deucher | a9e6141 | 2013-06-25 17:56:16 -0400 | [diff] [blame] | 1515 | u32 near_tdp_limit_adjusted; |
Alex Deucher | 61b7d60 | 2012-11-14 19:57:42 -0500 | [diff] [blame] | 1516 | u32 sq_ramping_threshold; |
| 1517 | u32 cac_leakage; |
| 1518 | u16 tdp_od_limit; |
| 1519 | u32 tdp_adjustment; |
| 1520 | u16 load_line_slope; |
| 1521 | bool power_control; |
Alex Deucher | 5ca302f | 2012-11-30 10:56:57 -0500 | [diff] [blame] | 1522 | bool ac_power; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1523 | /* special states active */ |
| 1524 | bool thermal_active; |
Alex Deucher | 8a22755 | 2013-06-21 15:12:57 -0400 | [diff] [blame] | 1525 | bool uvd_active; |
Alex Deucher | b62d628 | 2013-08-20 20:29:05 -0400 | [diff] [blame] | 1526 | bool vce_active; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1527 | /* thermal handling */ |
| 1528 | struct radeon_dpm_thermal thermal; |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1529 | /* forced levels */ |
| 1530 | enum radeon_dpm_forced_level forced_level; |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1531 | /* track UVD streams */ |
| 1532 | unsigned sd; |
| 1533 | unsigned hd; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1534 | }; |
| 1535 | |
Alex Deucher | ce3537d | 2013-07-24 12:12:49 -0400 | [diff] [blame] | 1536 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1537 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1538 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1539 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1540 | struct mutex mutex; |
Christian König | db7fce3 | 2012-05-11 14:57:18 +0200 | [diff] [blame] | 1541 | /* write locked while reprogramming mclk */ |
| 1542 | struct rw_semaphore mclk_lock; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1543 | u32 active_crtcs; |
| 1544 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 1545 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 1546 | bool vblank_sync; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1547 | fixed20_12 max_bandwidth; |
| 1548 | fixed20_12 igp_sideport_mclk; |
| 1549 | fixed20_12 igp_system_mclk; |
| 1550 | fixed20_12 igp_ht_link_clk; |
| 1551 | fixed20_12 igp_ht_link_width; |
| 1552 | fixed20_12 k8_bandwidth; |
| 1553 | fixed20_12 sideport_bandwidth; |
| 1554 | fixed20_12 ht_bandwidth; |
| 1555 | fixed20_12 core_bandwidth; |
| 1556 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1557 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1558 | fixed20_12 needed_bandwidth; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 1559 | struct radeon_power_state *power_state; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1560 | /* number of valid power states */ |
| 1561 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 1562 | int current_power_state_index; |
| 1563 | int current_clock_mode_index; |
| 1564 | int requested_power_state_index; |
| 1565 | int requested_clock_mode_index; |
| 1566 | int default_power_state_index; |
| 1567 | u32 current_sclk; |
| 1568 | u32 current_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1569 | u16 current_vddc; |
| 1570 | u16 current_vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 1571 | u32 default_sclk; |
| 1572 | u32 default_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 1573 | u16 default_vddc; |
| 1574 | u16 default_vddci; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1575 | struct radeon_i2c_chan *i2c_bus; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1576 | /* selected pm method */ |
| 1577 | enum radeon_pm_method pm_method; |
| 1578 | /* dynpm power management */ |
| 1579 | struct delayed_work dynpm_idle_work; |
| 1580 | enum radeon_dynpm_state dynpm_state; |
| 1581 | enum radeon_dynpm_action dynpm_planned_action; |
| 1582 | unsigned long dynpm_action_timeout; |
| 1583 | bool dynpm_can_upclock; |
| 1584 | bool dynpm_can_downclock; |
| 1585 | /* profile-based power management */ |
| 1586 | enum radeon_pm_profile_type profile; |
| 1587 | int profile_index; |
| 1588 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 1589 | /* internal thermal controller on rv6xx+ */ |
| 1590 | enum radeon_int_thermal_type int_thermal_type; |
| 1591 | struct device *int_hwmon_dev; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1592 | /* dpm */ |
| 1593 | bool dpm_enabled; |
| 1594 | struct radeon_dpm dpm; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1595 | }; |
| 1596 | |
Alex Deucher | a4c9e2e | 2011-11-04 10:09:41 -0400 | [diff] [blame] | 1597 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
| 1598 | enum radeon_pm_state_type ps_type, |
| 1599 | int instance); |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1600 | /* |
| 1601 | * UVD |
| 1602 | */ |
| 1603 | #define RADEON_MAX_UVD_HANDLES 10 |
| 1604 | #define RADEON_UVD_STACK_SIZE (1024*1024) |
| 1605 | #define RADEON_UVD_HEAP_SIZE (1024*1024) |
| 1606 | |
| 1607 | struct radeon_uvd { |
| 1608 | struct radeon_bo *vcpu_bo; |
| 1609 | void *cpu_addr; |
| 1610 | uint64_t gpu_addr; |
Christian König | 9cc2e0e | 2013-07-12 10:18:09 -0400 | [diff] [blame] | 1611 | void *saved_bo; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1612 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
| 1613 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
Alex Deucher | 85a129c | 2013-08-05 12:41:20 -0400 | [diff] [blame] | 1614 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
Christian König | 55b51c8 | 2013-04-18 15:25:59 +0200 | [diff] [blame] | 1615 | struct delayed_work idle_work; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 1616 | }; |
| 1617 | |
| 1618 | int radeon_uvd_init(struct radeon_device *rdev); |
| 1619 | void radeon_uvd_fini(struct radeon_device *rdev); |
| 1620 | int radeon_uvd_suspend(struct radeon_device *rdev); |
| 1621 | int radeon_uvd_resume(struct radeon_device *rdev); |
| 1622 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
| 1623 | uint32_t handle, struct radeon_fence **fence); |
| 1624 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
| 1625 | uint32_t handle, struct radeon_fence **fence); |
| 1626 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); |
| 1627 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
| 1628 | struct drm_file *filp); |
| 1629 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
Christian König | 55b51c8 | 2013-04-18 15:25:59 +0200 | [diff] [blame] | 1630 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
Christian König | facd112 | 2013-04-29 11:55:02 +0200 | [diff] [blame] | 1631 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
| 1632 | unsigned vclk, unsigned dclk, |
| 1633 | unsigned vco_min, unsigned vco_max, |
| 1634 | unsigned fb_factor, unsigned fb_mask, |
| 1635 | unsigned pd_min, unsigned pd_max, |
| 1636 | unsigned pd_even, |
| 1637 | unsigned *optimal_fb_div, |
| 1638 | unsigned *optimal_vclk_div, |
| 1639 | unsigned *optimal_dclk_div); |
| 1640 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
| 1641 | unsigned cg_upll_func_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1642 | |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1643 | /* |
| 1644 | * VCE |
| 1645 | */ |
| 1646 | #define RADEON_MAX_VCE_HANDLES 16 |
| 1647 | #define RADEON_VCE_STACK_SIZE (1024*1024) |
| 1648 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) |
| 1649 | |
| 1650 | struct radeon_vce { |
| 1651 | struct radeon_bo *vcpu_bo; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1652 | uint64_t gpu_addr; |
Christian König | 98ccc29 | 2014-01-23 09:50:49 -0700 | [diff] [blame] | 1653 | unsigned fw_version; |
| 1654 | unsigned fb_version; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1655 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
| 1656 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
Leo Liu | 2fc5703 | 2014-05-05 15:42:18 -0400 | [diff] [blame] | 1657 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1658 | struct delayed_work idle_work; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1659 | }; |
| 1660 | |
| 1661 | int radeon_vce_init(struct radeon_device *rdev); |
| 1662 | void radeon_vce_fini(struct radeon_device *rdev); |
| 1663 | int radeon_vce_suspend(struct radeon_device *rdev); |
| 1664 | int radeon_vce_resume(struct radeon_device *rdev); |
| 1665 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
| 1666 | uint32_t handle, struct radeon_fence **fence); |
| 1667 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
| 1668 | uint32_t handle, struct radeon_fence **fence); |
| 1669 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
Alex Deucher | 03afe6f | 2013-08-23 11:56:26 -0400 | [diff] [blame] | 1670 | void radeon_vce_note_usage(struct radeon_device *rdev); |
Leo Liu | 2fc5703 | 2014-05-05 15:42:18 -0400 | [diff] [blame] | 1671 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 1672 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
| 1673 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
| 1674 | struct radeon_ring *ring, |
| 1675 | struct radeon_semaphore *semaphore, |
| 1676 | bool emit_wait); |
| 1677 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1678 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
| 1679 | struct radeon_fence *fence); |
| 1680 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1681 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1682 | |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1683 | struct r600_audio_pin { |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1684 | int channels; |
| 1685 | int rate; |
| 1686 | int bits_per_sample; |
| 1687 | u8 status_bits; |
| 1688 | u8 category_code; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 1689 | u32 offset; |
| 1690 | bool connected; |
| 1691 | u32 id; |
| 1692 | }; |
| 1693 | |
| 1694 | struct r600_audio { |
| 1695 | bool enabled; |
| 1696 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
| 1697 | int num_pins; |
Rafał Miłecki | a92553a | 2012-04-28 23:35:20 +0200 | [diff] [blame] | 1698 | }; |
| 1699 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1700 | /* |
| 1701 | * Benchmarking |
| 1702 | */ |
Ilija Hadzic | 638dd7d | 2011-10-12 23:29:39 -0400 | [diff] [blame] | 1703 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1704 | |
| 1705 | |
| 1706 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1707 | * Testing |
| 1708 | */ |
| 1709 | void radeon_test_moves(struct radeon_device *rdev); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1710 | void radeon_test_ring_sync(struct radeon_device *rdev, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 1711 | struct radeon_ring *cpA, |
| 1712 | struct radeon_ring *cpB); |
Christian König | 60a7e39 | 2011-09-27 12:31:00 +0200 | [diff] [blame] | 1713 | void radeon_test_syncing(struct radeon_device *rdev); |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 1714 | |
| 1715 | |
| 1716 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1717 | * Debugfs |
| 1718 | */ |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 1719 | struct radeon_debugfs { |
| 1720 | struct drm_info_list *files; |
| 1721 | unsigned num_files; |
| 1722 | }; |
| 1723 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1724 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 1725 | struct drm_info_list *files, |
| 1726 | unsigned nfiles); |
| 1727 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1728 | |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1729 | /* |
| 1730 | * ASIC ring specific functions. |
| 1731 | */ |
| 1732 | struct radeon_asic_ring { |
| 1733 | /* ring read/write ptr handling */ |
| 1734 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1735 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1736 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
| 1737 | |
| 1738 | /* validating and patching of IBs */ |
| 1739 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1740 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 1741 | |
| 1742 | /* command emmit functions */ |
| 1743 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
| 1744 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
Christian König | 1654b81 | 2013-11-12 12:58:05 +0100 | [diff] [blame] | 1745 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1746 | struct radeon_semaphore *semaphore, bool emit_wait); |
| 1747 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
| 1748 | |
| 1749 | /* testing functions */ |
| 1750 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1751 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1752 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1753 | |
| 1754 | /* deprecated */ |
| 1755 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
| 1756 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1757 | |
| 1758 | /* |
| 1759 | * ASIC specific functions. |
| 1760 | */ |
| 1761 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1762 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1763 | void (*fini)(struct radeon_device *rdev); |
| 1764 | int (*resume)(struct radeon_device *rdev); |
| 1765 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1766 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1767 | int (*asic_reset)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1768 | /* ioctl hw specific callback. Some hw might want to perform special |
| 1769 | * operation on specific ioctl. For instance on wait idle some hw |
| 1770 | * might want to perform and HDP flush through MMIO as it seems that |
| 1771 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 1772 | * through ring. |
| 1773 | */ |
| 1774 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
| 1775 | /* check if 3D engine is idle */ |
| 1776 | bool (*gui_idle)(struct radeon_device *rdev); |
| 1777 | /* wait for mc_idle */ |
| 1778 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 1779 | /* get the reference clock */ |
| 1780 | u32 (*get_xclk)(struct radeon_device *rdev); |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 1781 | /* get the gpu clock counter */ |
| 1782 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1783 | /* gart */ |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1784 | struct { |
| 1785 | void (*tlb_flush)(struct radeon_device *rdev); |
Christian König | 7f90fc9 | 2014-06-04 15:29:57 +0200 | [diff] [blame] | 1786 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
| 1787 | uint64_t addr); |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 1788 | } gart; |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1789 | struct { |
| 1790 | int (*init)(struct radeon_device *rdev); |
| 1791 | void (*fini)(struct radeon_device *rdev); |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 1792 | void (*set_page)(struct radeon_device *rdev, |
| 1793 | struct radeon_ib *ib, |
| 1794 | uint64_t pe, |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 1795 | uint64_t addr, unsigned count, |
| 1796 | uint32_t incr, uint32_t flags); |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 1797 | } vm; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1798 | /* ring specific callbacks */ |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 1799 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1800 | /* irqs */ |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 1801 | struct { |
| 1802 | int (*set)(struct radeon_device *rdev); |
| 1803 | int (*process)(struct radeon_device *rdev); |
| 1804 | } irq; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1805 | /* displays */ |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1806 | struct { |
| 1807 | /* display watermarks */ |
| 1808 | void (*bandwidth_update)(struct radeon_device *rdev); |
| 1809 | /* get frame count */ |
| 1810 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 1811 | /* wait for vblank */ |
| 1812 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 1813 | /* set backlight level */ |
| 1814 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 1815 | /* get backlight level */ |
| 1816 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 1817 | /* audio callbacks */ |
| 1818 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
| 1819 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 1820 | } display; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1821 | /* copy functions for bo handling */ |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1822 | struct { |
| 1823 | int (*blit)(struct radeon_device *rdev, |
| 1824 | uint64_t src_offset, |
| 1825 | uint64_t dst_offset, |
| 1826 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1827 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1828 | u32 blit_ring_index; |
| 1829 | int (*dma)(struct radeon_device *rdev, |
| 1830 | uint64_t src_offset, |
| 1831 | uint64_t dst_offset, |
| 1832 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1833 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1834 | u32 dma_ring_index; |
| 1835 | /* method used for bo copy */ |
| 1836 | int (*copy)(struct radeon_device *rdev, |
| 1837 | uint64_t src_offset, |
| 1838 | uint64_t dst_offset, |
| 1839 | unsigned num_gpu_pages, |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 1840 | struct radeon_fence **fence); |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 1841 | /* ring used for bo copies */ |
| 1842 | u32 copy_ring_index; |
| 1843 | } copy; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1844 | /* surfaces */ |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 1845 | struct { |
| 1846 | int (*set_reg)(struct radeon_device *rdev, int reg, |
| 1847 | uint32_t tiling_flags, uint32_t pitch, |
| 1848 | uint32_t offset, uint32_t obj_size); |
| 1849 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
| 1850 | } surface; |
Alex Deucher | 54e88e0 | 2012-02-23 18:10:29 -0500 | [diff] [blame] | 1851 | /* hotplug detect */ |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 1852 | struct { |
| 1853 | void (*init)(struct radeon_device *rdev); |
| 1854 | void (*fini)(struct radeon_device *rdev); |
| 1855 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1856 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 1857 | } hpd; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1858 | /* static power management */ |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1859 | struct { |
| 1860 | void (*misc)(struct radeon_device *rdev); |
| 1861 | void (*prepare)(struct radeon_device *rdev); |
| 1862 | void (*finish)(struct radeon_device *rdev); |
| 1863 | void (*init_profile)(struct radeon_device *rdev); |
| 1864 | void (*get_dynpm_state)(struct radeon_device *rdev); |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 1865 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
| 1866 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| 1867 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
| 1868 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| 1869 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
| 1870 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 1871 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Alex Deucher | 73afc70 | 2013-04-08 12:41:30 +0200 | [diff] [blame] | 1872 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
Alex Deucher | b59b733 | 2013-08-20 20:01:18 -0400 | [diff] [blame] | 1873 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 1874 | int (*get_temperature)(struct radeon_device *rdev); |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 1875 | } pm; |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1876 | /* dynamic power management */ |
| 1877 | struct { |
| 1878 | int (*init)(struct radeon_device *rdev); |
| 1879 | void (*setup_asic)(struct radeon_device *rdev); |
| 1880 | int (*enable)(struct radeon_device *rdev); |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 1881 | int (*late_enable)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1882 | void (*disable)(struct radeon_device *rdev); |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1883 | int (*pre_set_power_state)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1884 | int (*set_power_state)(struct radeon_device *rdev); |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 1885 | void (*post_set_power_state)(struct radeon_device *rdev); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1886 | void (*display_configuration_changed)(struct radeon_device *rdev); |
| 1887 | void (*fini)(struct radeon_device *rdev); |
| 1888 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
| 1889 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
| 1890 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 1891 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 1892 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 1893 | bool (*vblank_too_short)(struct radeon_device *rdev); |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 1894 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 1895 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 1896 | } dpm; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 1897 | /* pageflipping */ |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1898 | struct { |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 1899 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 1900 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
Alex Deucher | 0f9e006 | 2012-02-23 17:53:40 -0500 | [diff] [blame] | 1901 | } pflip; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1902 | }; |
| 1903 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1904 | /* |
| 1905 | * Asic structures |
| 1906 | */ |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1907 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1908 | const unsigned *reg_safe_bm; |
| 1909 | unsigned reg_safe_bm_size; |
| 1910 | u32 hdp_cntl; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1911 | }; |
| 1912 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1913 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1914 | const unsigned *reg_safe_bm; |
| 1915 | unsigned reg_safe_bm_size; |
| 1916 | u32 resync_scratch; |
| 1917 | u32 hdp_cntl; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1918 | }; |
| 1919 | |
| 1920 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1921 | unsigned max_pipes; |
| 1922 | unsigned max_tile_pipes; |
| 1923 | unsigned max_simds; |
| 1924 | unsigned max_backends; |
| 1925 | unsigned max_gprs; |
| 1926 | unsigned max_threads; |
| 1927 | unsigned max_stack_entries; |
| 1928 | unsigned max_hw_contexts; |
| 1929 | unsigned max_gs_threads; |
| 1930 | unsigned sx_max_export_size; |
| 1931 | unsigned sx_max_export_pos_size; |
| 1932 | unsigned sx_max_export_smx_size; |
| 1933 | unsigned sq_num_cf_insts; |
| 1934 | unsigned tiling_nbanks; |
| 1935 | unsigned tiling_npipes; |
| 1936 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1937 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1938 | unsigned backend_map; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1939 | }; |
| 1940 | |
| 1941 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1942 | unsigned max_pipes; |
| 1943 | unsigned max_tile_pipes; |
| 1944 | unsigned max_simds; |
| 1945 | unsigned max_backends; |
| 1946 | unsigned max_gprs; |
| 1947 | unsigned max_threads; |
| 1948 | unsigned max_stack_entries; |
| 1949 | unsigned max_hw_contexts; |
| 1950 | unsigned max_gs_threads; |
| 1951 | unsigned sx_max_export_size; |
| 1952 | unsigned sx_max_export_pos_size; |
| 1953 | unsigned sx_max_export_smx_size; |
| 1954 | unsigned sq_num_cf_insts; |
| 1955 | unsigned sx_num_of_sets; |
| 1956 | unsigned sc_prim_fifo_size; |
| 1957 | unsigned sc_hiz_tile_fifo_size; |
| 1958 | unsigned sc_earlyz_tile_fifo_fize; |
| 1959 | unsigned tiling_nbanks; |
| 1960 | unsigned tiling_npipes; |
| 1961 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1962 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1963 | unsigned backend_map; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1964 | }; |
| 1965 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1966 | struct evergreen_asic { |
| 1967 | unsigned num_ses; |
| 1968 | unsigned max_pipes; |
| 1969 | unsigned max_tile_pipes; |
| 1970 | unsigned max_simds; |
| 1971 | unsigned max_backends; |
| 1972 | unsigned max_gprs; |
| 1973 | unsigned max_threads; |
| 1974 | unsigned max_stack_entries; |
| 1975 | unsigned max_hw_contexts; |
| 1976 | unsigned max_gs_threads; |
| 1977 | unsigned sx_max_export_size; |
| 1978 | unsigned sx_max_export_pos_size; |
| 1979 | unsigned sx_max_export_smx_size; |
| 1980 | unsigned sq_num_cf_insts; |
| 1981 | unsigned sx_num_of_sets; |
| 1982 | unsigned sc_prim_fifo_size; |
| 1983 | unsigned sc_hiz_tile_fifo_size; |
| 1984 | unsigned sc_earlyz_tile_fifo_size; |
| 1985 | unsigned tiling_nbanks; |
| 1986 | unsigned tiling_npipes; |
| 1987 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1988 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1989 | unsigned backend_map; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1990 | }; |
| 1991 | |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1992 | struct cayman_asic { |
| 1993 | unsigned max_shader_engines; |
| 1994 | unsigned max_pipes_per_simd; |
| 1995 | unsigned max_tile_pipes; |
| 1996 | unsigned max_simds_per_se; |
| 1997 | unsigned max_backends_per_se; |
| 1998 | unsigned max_texture_channel_caches; |
| 1999 | unsigned max_gprs; |
| 2000 | unsigned max_threads; |
| 2001 | unsigned max_gs_threads; |
| 2002 | unsigned max_stack_entries; |
| 2003 | unsigned sx_num_of_sets; |
| 2004 | unsigned sx_max_export_size; |
| 2005 | unsigned sx_max_export_pos_size; |
| 2006 | unsigned sx_max_export_smx_size; |
| 2007 | unsigned max_hw_contexts; |
| 2008 | unsigned sq_num_cf_insts; |
| 2009 | unsigned sc_prim_fifo_size; |
| 2010 | unsigned sc_hiz_tile_fifo_size; |
| 2011 | unsigned sc_earlyz_tile_fifo_size; |
| 2012 | |
| 2013 | unsigned num_shader_engines; |
| 2014 | unsigned num_shader_pipes_per_simd; |
| 2015 | unsigned num_tile_pipes; |
| 2016 | unsigned num_simds_per_se; |
| 2017 | unsigned num_backends_per_se; |
| 2018 | unsigned backend_disable_mask_per_asic; |
| 2019 | unsigned backend_map; |
| 2020 | unsigned num_texture_channel_caches; |
| 2021 | unsigned mem_max_burst_length_bytes; |
| 2022 | unsigned mem_row_size_in_kb; |
| 2023 | unsigned shader_engine_tile_size; |
| 2024 | unsigned num_gpus; |
| 2025 | unsigned multi_gpu_tile_size; |
| 2026 | |
| 2027 | unsigned tile_config; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 2028 | }; |
| 2029 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2030 | struct si_asic { |
| 2031 | unsigned max_shader_engines; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2032 | unsigned max_tile_pipes; |
Alex Deucher | 1a8ca75 | 2012-06-01 18:58:22 -0400 | [diff] [blame] | 2033 | unsigned max_cu_per_sh; |
| 2034 | unsigned max_sh_per_se; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2035 | unsigned max_backends_per_se; |
| 2036 | unsigned max_texture_channel_caches; |
| 2037 | unsigned max_gprs; |
| 2038 | unsigned max_gs_threads; |
| 2039 | unsigned max_hw_contexts; |
| 2040 | unsigned sc_prim_fifo_size_frontend; |
| 2041 | unsigned sc_prim_fifo_size_backend; |
| 2042 | unsigned sc_hiz_tile_fifo_size; |
| 2043 | unsigned sc_earlyz_tile_fifo_size; |
| 2044 | |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2045 | unsigned num_tile_pipes; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 2046 | unsigned backend_enable_mask; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2047 | unsigned backend_disable_mask_per_asic; |
| 2048 | unsigned backend_map; |
| 2049 | unsigned num_texture_channel_caches; |
| 2050 | unsigned mem_max_burst_length_bytes; |
| 2051 | unsigned mem_row_size_in_kb; |
| 2052 | unsigned shader_engine_tile_size; |
| 2053 | unsigned num_gpus; |
| 2054 | unsigned multi_gpu_tile_size; |
| 2055 | |
| 2056 | unsigned tile_config; |
Jerome Glisse | 64d7b8b | 2013-04-09 11:17:08 -0400 | [diff] [blame] | 2057 | uint32_t tile_mode_array[32]; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2058 | }; |
| 2059 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2060 | struct cik_asic { |
| 2061 | unsigned max_shader_engines; |
| 2062 | unsigned max_tile_pipes; |
| 2063 | unsigned max_cu_per_sh; |
| 2064 | unsigned max_sh_per_se; |
| 2065 | unsigned max_backends_per_se; |
| 2066 | unsigned max_texture_channel_caches; |
| 2067 | unsigned max_gprs; |
| 2068 | unsigned max_gs_threads; |
| 2069 | unsigned max_hw_contexts; |
| 2070 | unsigned sc_prim_fifo_size_frontend; |
| 2071 | unsigned sc_prim_fifo_size_backend; |
| 2072 | unsigned sc_hiz_tile_fifo_size; |
| 2073 | unsigned sc_earlyz_tile_fifo_size; |
| 2074 | |
| 2075 | unsigned num_tile_pipes; |
Marek Olšák | 439a1cf | 2013-12-22 02:18:01 +0100 | [diff] [blame] | 2076 | unsigned backend_enable_mask; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2077 | unsigned backend_disable_mask_per_asic; |
| 2078 | unsigned backend_map; |
| 2079 | unsigned num_texture_channel_caches; |
| 2080 | unsigned mem_max_burst_length_bytes; |
| 2081 | unsigned mem_row_size_in_kb; |
| 2082 | unsigned shader_engine_tile_size; |
| 2083 | unsigned num_gpus; |
| 2084 | unsigned multi_gpu_tile_size; |
| 2085 | |
| 2086 | unsigned tile_config; |
Alex Deucher | 39aee49 | 2013-04-10 13:41:25 -0400 | [diff] [blame] | 2087 | uint32_t tile_mode_array[32]; |
Michel Dänzer | 32f79a8 | 2013-11-18 18:26:00 +0900 | [diff] [blame] | 2088 | uint32_t macrotile_mode_array[16]; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2089 | }; |
| 2090 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2091 | union radeon_asic_config { |
| 2092 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2093 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2094 | struct r600_asic r600; |
| 2095 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 2096 | struct evergreen_asic evergreen; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 2097 | struct cayman_asic cayman; |
Alex Deucher | 0a96d72 | 2012-03-20 17:18:11 -0400 | [diff] [blame] | 2098 | struct si_asic si; |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 2099 | struct cik_asic cik; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2100 | }; |
| 2101 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 2102 | /* |
| 2103 | * asic initizalization from radeon_asic.c |
| 2104 | */ |
| 2105 | void radeon_agp_disable(struct radeon_device *rdev); |
| 2106 | int radeon_asic_init(struct radeon_device *rdev); |
| 2107 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2108 | |
| 2109 | /* |
| 2110 | * IOCTL. |
| 2111 | */ |
| 2112 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 2113 | struct drm_file *filp); |
| 2114 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 2115 | struct drm_file *filp); |
| 2116 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 2117 | struct drm_file *file_priv); |
| 2118 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 2119 | struct drm_file *file_priv); |
| 2120 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 2121 | struct drm_file *file_priv); |
| 2122 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 2123 | struct drm_file *file_priv); |
| 2124 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 2125 | struct drm_file *filp); |
| 2126 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 2127 | struct drm_file *filp); |
| 2128 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 2129 | struct drm_file *filp); |
| 2130 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 2131 | struct drm_file *filp); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2132 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 2133 | struct drm_file *filp); |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 2134 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
| 2135 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2136 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2137 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 2138 | struct drm_file *filp); |
| 2139 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 2140 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2141 | |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2142 | /* VRAM scratch page for HDP bug, default vram page */ |
| 2143 | struct r600_vram_scratch { |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 2144 | struct radeon_bo *robj; |
| 2145 | volatile uint32_t *ptr; |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2146 | u64 gpu_addr; |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 2147 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2148 | |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2149 | /* |
| 2150 | * ACPI |
| 2151 | */ |
| 2152 | struct radeon_atif_notification_cfg { |
| 2153 | bool enabled; |
| 2154 | int command_code; |
| 2155 | }; |
| 2156 | |
| 2157 | struct radeon_atif_notifications { |
| 2158 | bool display_switch; |
| 2159 | bool expansion_mode_change; |
| 2160 | bool thermal_state; |
| 2161 | bool forced_power_state; |
| 2162 | bool system_power_state; |
| 2163 | bool display_conf_change; |
| 2164 | bool px_gfx_switch; |
| 2165 | bool brightness_change; |
| 2166 | bool dgpu_display_event; |
| 2167 | }; |
| 2168 | |
| 2169 | struct radeon_atif_functions { |
| 2170 | bool system_params; |
| 2171 | bool sbios_requests; |
| 2172 | bool select_active_disp; |
| 2173 | bool lid_state; |
| 2174 | bool get_tv_standard; |
| 2175 | bool set_tv_standard; |
| 2176 | bool get_panel_expansion_mode; |
| 2177 | bool set_panel_expansion_mode; |
| 2178 | bool temperature_change; |
| 2179 | bool graphics_device_types; |
| 2180 | }; |
| 2181 | |
| 2182 | struct radeon_atif { |
| 2183 | struct radeon_atif_notifications notifications; |
| 2184 | struct radeon_atif_functions functions; |
| 2185 | struct radeon_atif_notification_cfg notification_cfg; |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 2186 | struct radeon_encoder *encoder_for_bl; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2187 | }; |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 2188 | |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 2189 | struct radeon_atcs_functions { |
| 2190 | bool get_ext_state; |
| 2191 | bool pcie_perf_req; |
| 2192 | bool pcie_dev_rdy; |
| 2193 | bool pcie_bus_width; |
| 2194 | }; |
| 2195 | |
| 2196 | struct radeon_atcs { |
| 2197 | struct radeon_atcs_functions functions; |
| 2198 | }; |
| 2199 | |
Michel Dänzer | 7a1619b | 2011-11-10 18:57:26 +0100 | [diff] [blame] | 2200 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2201 | * Core structure, functions and helpers. |
| 2202 | */ |
| 2203 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 2204 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 2205 | |
| 2206 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2207 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2208 | struct drm_device *ddev; |
| 2209 | struct pci_dev *pdev; |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 2210 | struct rw_semaphore exclusive_lock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2211 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2212 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2213 | enum radeon_family family; |
| 2214 | unsigned long flags; |
| 2215 | int usec_timeout; |
| 2216 | enum radeon_pll_errata pll_errata; |
| 2217 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 2218 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2219 | int disp_priority; |
| 2220 | /* BIOS */ |
| 2221 | uint8_t *bios; |
| 2222 | bool is_atom_bios; |
| 2223 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2224 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2225 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 2226 | resource_size_t rmmio_base; |
| 2227 | resource_size_t rmmio_size; |
Daniel Vetter | 2c38515 | 2012-12-02 14:06:15 +0100 | [diff] [blame] | 2228 | /* protects concurrent MM_INDEX/DATA based register access */ |
| 2229 | spinlock_t mmio_idx_lock; |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2230 | /* protects concurrent SMC based register access */ |
| 2231 | spinlock_t smc_idx_lock; |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2232 | /* protects concurrent PLL register access */ |
| 2233 | spinlock_t pll_idx_lock; |
| 2234 | /* protects concurrent MC register access */ |
| 2235 | spinlock_t mc_idx_lock; |
| 2236 | /* protects concurrent PCIE register access */ |
| 2237 | spinlock_t pcie_idx_lock; |
| 2238 | /* protects concurrent PCIE_PORT register access */ |
| 2239 | spinlock_t pciep_idx_lock; |
| 2240 | /* protects concurrent PIF register access */ |
| 2241 | spinlock_t pif_idx_lock; |
| 2242 | /* protects concurrent CG register access */ |
| 2243 | spinlock_t cg_idx_lock; |
| 2244 | /* protects concurrent UVD register access */ |
| 2245 | spinlock_t uvd_idx_lock; |
| 2246 | /* protects concurrent RCU register access */ |
| 2247 | spinlock_t rcu_idx_lock; |
| 2248 | /* protects concurrent DIDT register access */ |
| 2249 | spinlock_t didt_idx_lock; |
| 2250 | /* protects concurrent ENDPOINT (audio) register access */ |
| 2251 | spinlock_t end_idx_lock; |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 2252 | void __iomem *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2253 | radeon_rreg_t mc_rreg; |
| 2254 | radeon_wreg_t mc_wreg; |
| 2255 | radeon_rreg_t pll_rreg; |
| 2256 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2257 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2258 | radeon_rreg_t pciep_rreg; |
| 2259 | radeon_wreg_t pciep_wreg; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2260 | /* io port */ |
| 2261 | void __iomem *rio_mem; |
| 2262 | resource_size_t rio_mem_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2263 | struct radeon_clock clock; |
| 2264 | struct radeon_mc mc; |
| 2265 | struct radeon_gart gart; |
| 2266 | struct radeon_mode_info mode_info; |
| 2267 | struct radeon_scratch scratch; |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2268 | struct radeon_doorbell doorbell; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2269 | struct radeon_mman mman; |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 2270 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
Jerome Glisse | 0085c950 | 2012-05-09 15:34:55 +0200 | [diff] [blame] | 2271 | wait_queue_head_t fence_queue; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 2272 | struct mutex ring_lock; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2273 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 2274 | bool ib_pool_ready; |
| 2275 | struct radeon_sa_manager ring_tmp_bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2276 | struct radeon_irq irq; |
| 2277 | struct radeon_asic *asic; |
| 2278 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2279 | struct radeon_pm pm; |
Christian König | f2ba57b | 2013-04-08 12:41:29 +0200 | [diff] [blame] | 2280 | struct radeon_uvd uvd; |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 2281 | struct radeon_vce vce; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 2282 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2283 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2284 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2285 | bool shutdown; |
| 2286 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 2287 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 2288 | bool accel_working; |
Samuel Li | a0a53aa | 2013-04-08 17:25:47 -0400 | [diff] [blame] | 2289 | bool fastfb_working; /* IGP feature*/ |
Christian König | f9eaf9a | 2013-10-29 20:14:47 +0100 | [diff] [blame] | 2290 | bool needs_reset; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2291 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2292 | const struct firmware *me_fw; /* all family ME firmware */ |
| 2293 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2294 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2295 | const struct firmware *mc_fw; /* NI MC firmware */ |
Alex Deucher | 0f0de06 | 2012-03-20 17:18:17 -0400 | [diff] [blame] | 2296 | const struct firmware *ce_fw; /* SI CE firmware */ |
Alex Deucher | 02c8132 | 2012-12-18 21:43:07 -0500 | [diff] [blame] | 2297 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
Alex Deucher | 21a93e1 | 2013-04-09 12:47:11 -0400 | [diff] [blame] | 2298 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
Alex Deucher | 66229b2 | 2013-06-26 00:11:19 -0400 | [diff] [blame] | 2299 | const struct firmware *smc_fw; /* SMC firmware */ |
Christian König | 4ad9c1c | 2013-08-05 14:10:55 +0200 | [diff] [blame] | 2300 | const struct firmware *uvd_fw; /* UVD firmware */ |
Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame] | 2301 | const struct firmware *vce_fw; /* VCE firmware */ |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2302 | struct r600_vram_scratch vram_scratch; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 2303 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 2304 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | 2948f5e | 2013-04-12 13:52:52 -0400 | [diff] [blame] | 2305 | struct radeon_rlc rlc; |
Alex Deucher | 963e81f | 2013-06-26 17:37:11 -0400 | [diff] [blame] | 2306 | struct radeon_mec mec; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 2307 | struct work_struct hotplug_work; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 2308 | struct work_struct audio_work; |
Alex Deucher | 8f61b34 | 2013-06-14 09:13:52 -0400 | [diff] [blame] | 2309 | struct work_struct reset_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 2310 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 2311 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Alex Deucher | 948bee3 | 2013-05-14 12:08:35 -0400 | [diff] [blame] | 2312 | bool has_uvd; |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 2313 | struct r600_audio audio; /* audio stuff */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 2314 | struct notifier_block acpi_nb; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 2315 | /* only one userspace can use Hyperz features or CMASK at a time */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 2316 | struct drm_file *hyperz_filp; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 2317 | struct drm_file *cmask_filp; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 2318 | /* i2c buses */ |
| 2319 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
Christian König | 4d8bf9a | 2011-10-24 14:54:54 +0200 | [diff] [blame] | 2320 | /* debugfs */ |
| 2321 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
| 2322 | unsigned debugfs_count; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2323 | /* virtual memory */ |
| 2324 | struct radeon_vm_manager vm_manager; |
Marek Olšák | 6759a0a | 2012-08-09 16:34:17 +0200 | [diff] [blame] | 2325 | struct mutex gpu_clock_mutex; |
Marek Olšák | 67e8e3f | 2014-03-02 00:56:18 +0100 | [diff] [blame] | 2326 | /* memory stats */ |
| 2327 | atomic64_t vram_usage; |
| 2328 | atomic64_t gtt_usage; |
| 2329 | atomic64_t num_bytes_moved; |
Luca Tettamanti | fd64ca8 | 2012-08-16 11:11:18 -0400 | [diff] [blame] | 2330 | /* ACPI interface */ |
| 2331 | struct radeon_atif atif; |
Alex Deucher | e3a1592 | 2012-08-16 11:13:43 -0400 | [diff] [blame] | 2332 | struct radeon_atcs atcs; |
Alex Deucher | f61d5b46 | 2013-08-06 12:40:16 -0400 | [diff] [blame] | 2333 | /* srbm instance registers */ |
| 2334 | struct mutex srbm_mutex; |
Alex Deucher | 64d8a72 | 2013-08-08 16:31:25 -0400 | [diff] [blame] | 2335 | /* clock, powergating flags */ |
| 2336 | u32 cg_flags; |
| 2337 | u32 pg_flags; |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 2338 | |
| 2339 | struct dev_pm_domain vga_pm_domain; |
| 2340 | bool have_disp_power_ref; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2341 | }; |
| 2342 | |
Alex Deucher | 90c4cde | 2014-04-10 22:29:01 -0400 | [diff] [blame] | 2343 | bool radeon_is_px(struct drm_device *dev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2344 | int radeon_device_init(struct radeon_device *rdev, |
| 2345 | struct drm_device *ddev, |
| 2346 | struct pci_dev *pdev, |
| 2347 | uint32_t flags); |
| 2348 | void radeon_device_fini(struct radeon_device *rdev); |
| 2349 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 2350 | |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 2351 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
| 2352 | bool always_indirect); |
| 2353 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
| 2354 | bool always_indirect); |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 2355 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
| 2356 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2357 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 2358 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
| 2359 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2360 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2361 | /* |
| 2362 | * Cast helper |
| 2363 | */ |
| 2364 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2365 | |
| 2366 | /* |
| 2367 | * Registers read & write functions. |
| 2368 | */ |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 2369 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
| 2370 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
| 2371 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
| 2372 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 2373 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
| 2374 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
| 2375 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) |
| 2376 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
| 2377 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2378 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2379 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 2380 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 2381 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 2382 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 2383 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2384 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 2385 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Alex Deucher | 492d2b6 | 2012-10-25 16:06:59 -0400 | [diff] [blame] | 2386 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
| 2387 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2388 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
| 2389 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2390 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
| 2391 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2392 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
| 2393 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2394 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
| 2395 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
| 2396 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
| 2397 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2398 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
| 2399 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2400 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
| 2401 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2402 | #define WREG32_P(reg, val, mask) \ |
| 2403 | do { \ |
| 2404 | uint32_t tmp_ = RREG32(reg); \ |
| 2405 | tmp_ &= (mask); \ |
| 2406 | tmp_ |= ((val) & ~(mask)); \ |
| 2407 | WREG32(reg, tmp_); \ |
| 2408 | } while (0) |
Rafał Miłecki | d5169fc | 2013-04-14 01:26:19 +0200 | [diff] [blame] | 2409 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
Rafał Miłecki | d43a93c | 2013-08-15 18:55:22 +0200 | [diff] [blame] | 2410 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2411 | #define WREG32_PLL_P(reg, val, mask) \ |
| 2412 | do { \ |
| 2413 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 2414 | tmp_ &= (mask); \ |
| 2415 | tmp_ |= ((val) & ~(mask)); \ |
| 2416 | WREG32_PLL(reg, tmp_); \ |
| 2417 | } while (0) |
Daniel Vetter | 2ef9bdf | 2012-12-02 14:02:51 +0100 | [diff] [blame] | 2418 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 2419 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 2420 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2421 | |
Andrew Lewycky | d5754ab | 2013-11-13 15:54:17 -0500 | [diff] [blame] | 2422 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
| 2423 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
Alex Deucher | 75efdee | 2013-03-04 12:47:46 -0500 | [diff] [blame] | 2424 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2425 | /* |
| 2426 | * Indirect registers accessor |
| 2427 | */ |
| 2428 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 2429 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2430 | unsigned long flags; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2431 | uint32_t r; |
| 2432 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2433 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2434 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 2435 | r = RREG32(RADEON_PCIE_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2436 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2437 | return r; |
| 2438 | } |
| 2439 | |
| 2440 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 2441 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2442 | unsigned long flags; |
| 2443 | |
| 2444 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2445 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 2446 | WREG32(RADEON_PCIE_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2447 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 2448 | } |
| 2449 | |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2450 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
| 2451 | { |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2452 | unsigned long flags; |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2453 | u32 r; |
| 2454 | |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2455 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2456 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
| 2457 | r = RREG32(TN_SMC_IND_DATA_0); |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2458 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2459 | return r; |
| 2460 | } |
| 2461 | |
| 2462 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2463 | { |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2464 | unsigned long flags; |
| 2465 | |
| 2466 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2467 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
| 2468 | WREG32(TN_SMC_IND_DATA_0, (v)); |
Alex Deucher | fe78118 | 2013-09-03 18:19:42 -0400 | [diff] [blame] | 2469 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
Alex Deucher | 1d5d0c3 | 2012-04-20 12:39:49 -0400 | [diff] [blame] | 2470 | } |
| 2471 | |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2472 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
| 2473 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2474 | unsigned long flags; |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2475 | u32 r; |
| 2476 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2477 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2478 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
| 2479 | r = RREG32(R600_RCU_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2480 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2481 | return r; |
| 2482 | } |
| 2483 | |
| 2484 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2485 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2486 | unsigned long flags; |
| 2487 | |
| 2488 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2489 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
| 2490 | WREG32(R600_RCU_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2491 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
Alex Deucher | ff82bbc | 2013-04-12 11:27:20 -0400 | [diff] [blame] | 2492 | } |
| 2493 | |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2494 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
| 2495 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2496 | unsigned long flags; |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2497 | u32 r; |
| 2498 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2499 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2500 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
| 2501 | r = RREG32(EVERGREEN_CG_IND_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2502 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2503 | return r; |
| 2504 | } |
| 2505 | |
| 2506 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2507 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2508 | unsigned long flags; |
| 2509 | |
| 2510 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2511 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
| 2512 | WREG32(EVERGREEN_CG_IND_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2513 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
Alex Deucher | 46f9564 | 2013-04-12 11:49:51 -0400 | [diff] [blame] | 2514 | } |
| 2515 | |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2516 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
| 2517 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2518 | unsigned long flags; |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2519 | u32 r; |
| 2520 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2521 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2522 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
| 2523 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2524 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2525 | return r; |
| 2526 | } |
| 2527 | |
| 2528 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2529 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2530 | unsigned long flags; |
| 2531 | |
| 2532 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2533 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
| 2534 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2535 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2536 | } |
| 2537 | |
| 2538 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) |
| 2539 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2540 | unsigned long flags; |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2541 | u32 r; |
| 2542 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2543 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2544 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
| 2545 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2546 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2547 | return r; |
| 2548 | } |
| 2549 | |
| 2550 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2551 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2552 | unsigned long flags; |
| 2553 | |
| 2554 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2555 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
| 2556 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2557 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
Alex Deucher | 792edd6 | 2013-02-14 18:18:12 -0500 | [diff] [blame] | 2558 | } |
| 2559 | |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2560 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
| 2561 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2562 | unsigned long flags; |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2563 | u32 r; |
| 2564 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2565 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2566 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
| 2567 | r = RREG32(R600_UVD_CTX_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2568 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2569 | return r; |
| 2570 | } |
| 2571 | |
| 2572 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2573 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2574 | unsigned long flags; |
| 2575 | |
| 2576 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2577 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
| 2578 | WREG32(R600_UVD_CTX_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2579 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
Alex Deucher | 93656cd | 2013-02-25 15:18:39 -0500 | [diff] [blame] | 2580 | } |
| 2581 | |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2582 | |
| 2583 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) |
| 2584 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2585 | unsigned long flags; |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2586 | u32 r; |
| 2587 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2588 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2589 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| 2590 | r = RREG32(CIK_DIDT_IND_DATA); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2591 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2592 | return r; |
| 2593 | } |
| 2594 | |
| 2595 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| 2596 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2597 | unsigned long flags; |
| 2598 | |
| 2599 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2600 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
| 2601 | WREG32(CIK_DIDT_IND_DATA, (v)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 2602 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
Alex Deucher | 1d58234 | 2013-04-19 13:03:37 -0400 | [diff] [blame] | 2603 | } |
| 2604 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2605 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 2606 | |
| 2607 | |
| 2608 | /* |
| 2609 | * ASICs helpers. |
| 2610 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 2611 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 2612 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2613 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 2614 | (rdev->family == CHIP_RV200) || \ |
| 2615 | (rdev->family == CHIP_RS100) || \ |
| 2616 | (rdev->family == CHIP_RS200) || \ |
| 2617 | (rdev->family == CHIP_RV250) || \ |
| 2618 | (rdev->family == CHIP_RV280) || \ |
| 2619 | (rdev->family == CHIP_RS300)) |
| 2620 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 2621 | (rdev->family == CHIP_RV350) || \ |
| 2622 | (rdev->family == CHIP_R350) || \ |
| 2623 | (rdev->family == CHIP_RV380) || \ |
| 2624 | (rdev->family == CHIP_R420) || \ |
| 2625 | (rdev->family == CHIP_R423) || \ |
| 2626 | (rdev->family == CHIP_RV410) || \ |
| 2627 | (rdev->family == CHIP_RS400) || \ |
| 2628 | (rdev->family == CHIP_RS480)) |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 2629 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 2630 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 2631 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 2632 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 2633 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 2634 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 2635 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 2636 | (rdev->ddev->pdev->device == 0x689D)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2637 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 2638 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 2639 | (rdev->family == CHIP_RS690) || \ |
| 2640 | (rdev->family == CHIP_RS740) || \ |
| 2641 | (rdev->family >= CHIP_R600)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2642 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 2643 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 2644 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Alex Deucher | 633b916 | 2011-01-06 21:19:11 -0500 | [diff] [blame] | 2645 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 2646 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 2647 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
Alex Deucher | 8848f75 | 2012-03-20 17:18:28 -0400 | [diff] [blame] | 2648 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
| 2649 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
| 2650 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 624d352 | 2012-12-18 17:01:35 -0500 | [diff] [blame] | 2651 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
Alex Deucher | b5d9d72 | 2012-07-26 18:53:55 -0400 | [diff] [blame] | 2652 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
Alex Deucher | e282917 | 2013-06-07 11:37:11 -0400 | [diff] [blame] | 2653 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
Alex Deucher | be0949f | 2014-04-08 11:28:54 -0400 | [diff] [blame] | 2654 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
| 2655 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
Alex Deucher | 89d2618 | 2014-05-08 18:26:23 -0400 | [diff] [blame] | 2656 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
| 2657 | (rdev->family == CHIP_MULLINS)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2658 | |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2659 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
| 2660 | (rdev->ddev->pdev->device == 0x6850) || \ |
| 2661 | (rdev->ddev->pdev->device == 0x6858) || \ |
| 2662 | (rdev->ddev->pdev->device == 0x6859) || \ |
| 2663 | (rdev->ddev->pdev->device == 0x6840) || \ |
| 2664 | (rdev->ddev->pdev->device == 0x6841) || \ |
| 2665 | (rdev->ddev->pdev->device == 0x6842) || \ |
| 2666 | (rdev->ddev->pdev->device == 0x6843)) |
| 2667 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2668 | /* |
| 2669 | * BIOS helpers. |
| 2670 | */ |
| 2671 | #define RBIOS8(i) (rdev->bios[i]) |
| 2672 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 2673 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 2674 | |
| 2675 | int radeon_combios_init(struct radeon_device *rdev); |
| 2676 | void radeon_combios_fini(struct radeon_device *rdev); |
| 2677 | int radeon_atombios_init(struct radeon_device *rdev); |
| 2678 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 2679 | |
| 2680 | |
| 2681 | /* |
| 2682 | * RING helpers. |
| 2683 | */ |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2684 | #if DRM_DEBUG_CODE == 0 |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2685 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2686 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2687 | ring->ring[ring->wptr++] = v; |
| 2688 | ring->wptr &= ring->ptr_mask; |
| 2689 | ring->count_dw--; |
| 2690 | ring->ring_free_dw--; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2691 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2692 | #else |
| 2693 | /* With debugging this is just too big to inline */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 2694 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 2695 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2696 | |
| 2697 | /* |
| 2698 | * ASICs macro. |
| 2699 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2700 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 2701 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 2702 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 2703 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2704 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2705 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 2706 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Alex Deucher | c5b3b85 | 2012-02-23 17:53:46 -0500 | [diff] [blame] | 2707 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
| 2708 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) |
Christian König | 05b0714 | 2012-08-06 20:21:10 +0200 | [diff] [blame] | 2709 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
| 2710 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
Alex Deucher | 43f1214 | 2013-02-01 17:32:42 +0100 | [diff] [blame] | 2711 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2712 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
| 2713 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
| 2714 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
| 2715 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
| 2716 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
| 2717 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
| 2718 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) |
| 2719 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
| 2720 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
| 2721 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
Alex Deucher | b35ea4a | 2012-02-23 17:53:43 -0500 | [diff] [blame] | 2722 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
| 2723 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 2724 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
Alex Deucher | 37e9b6a | 2012-08-03 11:39:43 -0400 | [diff] [blame] | 2725 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
Alex Deucher | 6d92f81 | 2012-09-14 09:59:26 -0400 | [diff] [blame] | 2726 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
Alex Deucher | a973bea | 2013-04-18 11:32:16 -0400 | [diff] [blame] | 2727 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
| 2728 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
Christian König | 76a0df8 | 2013-08-13 11:56:50 +0200 | [diff] [blame] | 2729 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
| 2730 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
Alex Deucher | 27cd776 | 2012-02-23 17:53:42 -0500 | [diff] [blame] | 2731 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
| 2732 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
| 2733 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
| 2734 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
| 2735 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
| 2736 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 2737 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
| 2738 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
| 2739 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
| 2740 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
| 2741 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
| 2742 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
| 2743 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
Alex Deucher | 73afc70 | 2013-04-08 12:41:30 +0200 | [diff] [blame] | 2744 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
Alex Deucher | b59b733 | 2013-08-20 20:01:18 -0400 | [diff] [blame] | 2745 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
Alex Deucher | 6bd1c38 | 2013-06-21 14:38:03 -0400 | [diff] [blame] | 2746 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
Alex Deucher | 9e6f3d0 | 2012-02-23 17:53:49 -0500 | [diff] [blame] | 2747 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
| 2748 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
Alex Deucher | c79a49c | 2012-02-23 17:53:47 -0500 | [diff] [blame] | 2749 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
Alex Deucher | 901ea57 | 2012-02-23 17:53:39 -0500 | [diff] [blame] | 2750 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
| 2751 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
| 2752 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
| 2753 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 2754 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a02fa39 | 2012-02-23 17:53:41 -0500 | [diff] [blame] | 2755 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
| 2756 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
| 2757 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
| 2758 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
| 2759 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
Alex Deucher | 69b62ad | 2012-08-03 11:50:54 -0400 | [diff] [blame] | 2760 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 2761 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
Alex Deucher | 69b62ad | 2012-08-03 11:50:54 -0400 | [diff] [blame] | 2762 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
| 2763 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
Alex Deucher | 454d2e2 | 2013-02-14 10:04:02 -0500 | [diff] [blame] | 2764 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
Alex Deucher | d041889 | 2013-01-24 10:35:23 -0500 | [diff] [blame] | 2765 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2766 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
| 2767 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
| 2768 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
Alex Deucher | 914a898 | 2013-12-19 11:37:22 -0500 | [diff] [blame] | 2769 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2770 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 2771 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2772 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
Alex Deucher | 84dd192 | 2013-01-16 12:52:04 -0500 | [diff] [blame] | 2773 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
Alex Deucher | da321c8 | 2013-04-12 13:55:22 -0400 | [diff] [blame] | 2774 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
| 2775 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
| 2776 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
| 2777 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
| 2778 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
Alex Deucher | 1316b79 | 2013-06-28 09:28:39 -0400 | [diff] [blame] | 2779 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
Alex Deucher | 70d01a5 | 2013-07-02 18:38:02 -0400 | [diff] [blame] | 2780 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
Alex Deucher | 4878306 | 2013-07-08 11:35:06 -0400 | [diff] [blame] | 2781 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
Alex Deucher | 9e9d976 | 2013-07-31 18:13:23 -0400 | [diff] [blame] | 2782 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
Alex Deucher | 1c71bda | 2013-09-09 19:11:52 -0400 | [diff] [blame] | 2783 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2784 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 2785 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2786 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 2787 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Alex Deucher | 1a0041b | 2013-10-02 13:01:36 -0400 | [diff] [blame] | 2788 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
Alex Deucher | 410a341 | 2013-01-18 13:05:39 -0500 | [diff] [blame] | 2789 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 2790 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2791 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 2792 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 2793 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2794 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 2795 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 2796 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2797 | extern void radeon_scratch_init(struct radeon_device *rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 2798 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 2799 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 2800 | extern void radeon_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 2801 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 2802 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 2803 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 2804 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 2805 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 2806 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2807 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 2808 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 10ebc0b | 2012-09-17 14:40:31 +1000 | [diff] [blame] | 2809 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
| 2810 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 2811 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
Alex Deucher | 2e1b65f | 2013-02-26 11:26:51 -0500 | [diff] [blame] | 2812 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
| 2813 | const u32 *registers, |
| 2814 | const u32 array_size); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 2815 | |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 2816 | /* |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2817 | * vm |
| 2818 | */ |
| 2819 | int radeon_vm_manager_init(struct radeon_device *rdev); |
| 2820 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 2821 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2822 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
Christian König | df0af44 | 2014-03-03 12:38:08 +0100 | [diff] [blame] | 2823 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
| 2824 | struct radeon_vm *vm, |
| 2825 | struct list_head *head); |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 2826 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
| 2827 | struct radeon_vm *vm, int ring); |
Christian König | fa68834 | 2014-02-20 10:47:05 +0100 | [diff] [blame] | 2828 | void radeon_vm_flush(struct radeon_device *rdev, |
| 2829 | struct radeon_vm *vm, |
| 2830 | int ring); |
Christian König | ee60e29 | 2012-08-09 16:21:08 +0200 | [diff] [blame] | 2831 | void radeon_vm_fence(struct radeon_device *rdev, |
| 2832 | struct radeon_vm *vm, |
| 2833 | struct radeon_fence *fence); |
Christian König | dce34bf | 2012-09-17 19:36:18 +0200 | [diff] [blame] | 2834 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
Christian König | 6d2f294 | 2014-02-20 13:42:17 +0100 | [diff] [blame] | 2835 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
| 2836 | struct radeon_vm *vm); |
Christian König | 9c57a6b | 2013-11-25 15:42:11 +0100 | [diff] [blame] | 2837 | int radeon_vm_bo_update(struct radeon_device *rdev, |
| 2838 | struct radeon_vm *vm, |
| 2839 | struct radeon_bo *bo, |
| 2840 | struct ttm_mem_reg *mem); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2841 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
| 2842 | struct radeon_bo *bo); |
Christian König | 421ca7a | 2012-09-11 16:10:00 +0200 | [diff] [blame] | 2843 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
| 2844 | struct radeon_bo *bo); |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 2845 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
| 2846 | struct radeon_vm *vm, |
| 2847 | struct radeon_bo *bo); |
| 2848 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
| 2849 | struct radeon_bo_va *bo_va, |
| 2850 | uint64_t offset, |
| 2851 | uint32_t flags); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2852 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 2853 | struct radeon_bo_va *bo_va); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2854 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 2855 | /* audio */ |
| 2856 | void r600_audio_update_hdmi(struct work_struct *work); |
Alex Deucher | b530602 | 2013-07-31 16:51:33 -0400 | [diff] [blame] | 2857 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
| 2858 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
Alex Deucher | 832eafa | 2014-02-18 11:07:55 -0500 | [diff] [blame] | 2859 | void r600_audio_enable(struct radeon_device *rdev, |
| 2860 | struct r600_audio_pin *pin, |
| 2861 | bool enable); |
| 2862 | void dce6_audio_enable(struct radeon_device *rdev, |
| 2863 | struct r600_audio_pin *pin, |
| 2864 | bool enable); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 2865 | |
| 2866 | /* |
Alex Deucher | 16cdf04 | 2011-10-28 10:30:02 -0400 | [diff] [blame] | 2867 | * R600 vram scratch functions |
| 2868 | */ |
| 2869 | int r600_vram_scratch_init(struct radeon_device *rdev); |
| 2870 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
| 2871 | |
| 2872 | /* |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 2873 | * r600 cs checking helper |
| 2874 | */ |
| 2875 | unsigned r600_mip_minify(unsigned size, unsigned level); |
| 2876 | bool r600_fmt_is_valid_color(u32 format); |
| 2877 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
| 2878 | int r600_fmt_get_blocksize(u32 format); |
| 2879 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
| 2880 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
| 2881 | |
| 2882 | /* |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 2883 | * r600 functions used by radeon_encoder.c |
| 2884 | */ |
Rafał Miłecki | 1b688d08 | 2012-04-30 15:44:54 +0200 | [diff] [blame] | 2885 | struct radeon_hdmi_acr { |
| 2886 | u32 clock; |
| 2887 | |
| 2888 | int n_32khz; |
| 2889 | int cts_32khz; |
| 2890 | |
| 2891 | int n_44_1khz; |
| 2892 | int cts_44_1khz; |
| 2893 | |
| 2894 | int n_48khz; |
| 2895 | int cts_48khz; |
| 2896 | |
| 2897 | }; |
| 2898 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 2899 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
| 2900 | |
Alex Deucher | 416a2bd | 2012-05-31 19:00:25 -0400 | [diff] [blame] | 2901 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
| 2902 | u32 tiling_pipe_num, |
| 2903 | u32 max_rb_num, |
| 2904 | u32 total_max_rb_num, |
| 2905 | u32 enabled_rb_mask); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 2906 | |
Rafał Miłecki | e55d3e6 | 2012-05-06 17:29:44 +0200 | [diff] [blame] | 2907 | /* |
| 2908 | * evergreen functions used by radeon_encoder.c |
| 2909 | */ |
| 2910 | |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2911 | extern int ni_init_microcode(struct radeon_device *rdev); |
Alex Deucher | 755d819 | 2011-03-02 20:07:34 -0500 | [diff] [blame] | 2912 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 2913 | |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 2914 | /* radeon_acpi.c */ |
| 2915 | #if defined(CONFIG_ACPI) |
| 2916 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 2917 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2918 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
| 2919 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
Alex Deucher | e37e6a0 | 2013-02-13 15:47:24 -0500 | [diff] [blame] | 2920 | u8 perf_req, bool advertise); |
Alex Deucher | dc50ba7 | 2013-06-26 00:33:35 -0400 | [diff] [blame] | 2921 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
Alex Deucher | c491707 | 2012-07-31 17:14:35 -0400 | [diff] [blame] | 2922 | #else |
| 2923 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 2924 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
| 2925 | #endif |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 2926 | |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 2927 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
| 2928 | struct radeon_cs_packet *pkt, |
| 2929 | unsigned idx); |
Ilija Hadzic | 9ffb7a6 | 2013-01-02 18:27:42 -0500 | [diff] [blame] | 2930 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
Ilija Hadzic | c3ad63a | 2013-01-02 18:27:45 -0500 | [diff] [blame] | 2931 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
| 2932 | struct radeon_cs_packet *pkt); |
Ilija Hadzic | e971699 | 2013-01-02 18:27:46 -0500 | [diff] [blame] | 2933 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 2934 | struct radeon_cs_reloc **cs_reloc, |
| 2935 | int nomm); |
Ilija Hadzic | 40592a1 | 2013-01-02 18:27:43 -0500 | [diff] [blame] | 2936 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
| 2937 | uint32_t *vline_start_end, |
| 2938 | uint32_t *vline_status); |
Ilija Hadzic | c38f34b | 2013-01-02 18:27:41 -0500 | [diff] [blame] | 2939 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2940 | #include "radeon_object.h" |
| 2941 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2942 | #endif |