Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Daniel Vetter | 618563e | 2012-04-01 13:38:50 +0200 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | c1c7af6 | 2009-09-10 15:28:03 -0700 | [diff] [blame] | 28 | #include <linux/module.h> |
| 29 | #include <linux/input.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/i2c.h> |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 31 | #include <linux/kernel.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 34 | #include <drm/drm_edid.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 35 | #include <drm/drmP.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 37 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 38 | #include "i915_drv.h" |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 39 | #include "i915_trace.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 40 | #include <drm/drm_dp_helper.h> |
| 41 | #include <drm/drm_crtc_helper.h> |
Keith Packard | c0f372b3 | 2011-11-16 22:24:52 -0800 | [diff] [blame] | 42 | #include <linux/dma_remapping.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 43 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 46 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 48 | struct intel_crtc_config *pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 50 | struct intel_crtc_config *pipe_config); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 51 | |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 53 | int x, int y, struct drm_framebuffer *old_fb); |
Jesse Barnes | eb1bfe8 | 2014-02-12 12:26:25 -0800 | [diff] [blame] | 54 | static int intel_framebuffer_init(struct drm_device *dev, |
| 55 | struct intel_framebuffer *ifb, |
| 56 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 57 | struct drm_i915_gem_object *obj); |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 58 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 59 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 60 | int min, max; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 61 | } intel_range_t; |
| 62 | |
| 63 | typedef struct { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 64 | int dot_limit; |
| 65 | int p2_slow, p2_fast; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 66 | } intel_p2_t; |
| 67 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 68 | typedef struct intel_limit intel_limit_t; |
| 69 | struct intel_limit { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 70 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 71 | intel_p2_t p2; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 72 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 73 | |
Daniel Vetter | d2acd21 | 2012-10-20 20:57:43 +0200 | [diff] [blame] | 74 | int |
| 75 | intel_pch_rawclk(struct drm_device *dev) |
| 76 | { |
| 77 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 78 | |
| 79 | WARN_ON(!HAS_PCH_SPLIT(dev)); |
| 80 | |
| 81 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; |
| 82 | } |
| 83 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 84 | static inline u32 /* units of 100MHz */ |
| 85 | intel_fdi_link_freq(struct drm_device *dev) |
| 86 | { |
Chris Wilson | 8b99e68 | 2010-10-13 09:59:17 +0100 | [diff] [blame] | 87 | if (IS_GEN5(dev)) { |
| 88 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 89 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; |
| 90 | } else |
| 91 | return 27; |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 92 | } |
| 93 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 94 | static const intel_limit_t intel_limits_i8xx_dac = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 95 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 96 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 97 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 98 | .m = { .min = 96, .max = 140 }, |
| 99 | .m1 = { .min = 18, .max = 26 }, |
| 100 | .m2 = { .min = 6, .max = 16 }, |
| 101 | .p = { .min = 4, .max = 128 }, |
| 102 | .p1 = { .min = 2, .max = 33 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 103 | .p2 = { .dot_limit = 165000, |
| 104 | .p2_slow = 4, .p2_fast = 2 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 105 | }; |
| 106 | |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 107 | static const intel_limit_t intel_limits_i8xx_dvo = { |
| 108 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 109 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 110 | .n = { .min = 2, .max = 16 }, |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 111 | .m = { .min = 96, .max = 140 }, |
| 112 | .m1 = { .min = 18, .max = 26 }, |
| 113 | .m2 = { .min = 6, .max = 16 }, |
| 114 | .p = { .min = 4, .max = 128 }, |
| 115 | .p1 = { .min = 2, .max = 33 }, |
| 116 | .p2 = { .dot_limit = 165000, |
| 117 | .p2_slow = 4, .p2_fast = 4 }, |
| 118 | }; |
| 119 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 120 | static const intel_limit_t intel_limits_i8xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 121 | .dot = { .min = 25000, .max = 350000 }, |
Ville Syrjälä | 9c33371 | 2013-12-09 18:54:17 +0200 | [diff] [blame] | 122 | .vco = { .min = 908000, .max = 1512000 }, |
Ville Syrjälä | 91dbe5f | 2013-12-09 18:54:14 +0200 | [diff] [blame] | 123 | .n = { .min = 2, .max = 16 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 124 | .m = { .min = 96, .max = 140 }, |
| 125 | .m1 = { .min = 18, .max = 26 }, |
| 126 | .m2 = { .min = 6, .max = 16 }, |
| 127 | .p = { .min = 4, .max = 128 }, |
| 128 | .p1 = { .min = 1, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 129 | .p2 = { .dot_limit = 165000, |
| 130 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 131 | }; |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 132 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 133 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 134 | .dot = { .min = 20000, .max = 400000 }, |
| 135 | .vco = { .min = 1400000, .max = 2800000 }, |
| 136 | .n = { .min = 1, .max = 6 }, |
| 137 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 4f7dfb6 | 2013-02-13 22:20:22 +0100 | [diff] [blame] | 138 | .m1 = { .min = 8, .max = 18 }, |
| 139 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 140 | .p = { .min = 5, .max = 80 }, |
| 141 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 142 | .p2 = { .dot_limit = 200000, |
| 143 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | static const intel_limit_t intel_limits_i9xx_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 147 | .dot = { .min = 20000, .max = 400000 }, |
| 148 | .vco = { .min = 1400000, .max = 2800000 }, |
| 149 | .n = { .min = 1, .max = 6 }, |
| 150 | .m = { .min = 70, .max = 120 }, |
Patrik Jakobsson | 53a7d2d | 2013-02-13 22:20:21 +0100 | [diff] [blame] | 151 | .m1 = { .min = 8, .max = 18 }, |
| 152 | .m2 = { .min = 3, .max = 7 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 153 | .p = { .min = 7, .max = 98 }, |
| 154 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 155 | .p2 = { .dot_limit = 112000, |
| 156 | .p2_slow = 14, .p2_fast = 7 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 157 | }; |
| 158 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 159 | |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 160 | static const intel_limit_t intel_limits_g4x_sdvo = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 161 | .dot = { .min = 25000, .max = 270000 }, |
| 162 | .vco = { .min = 1750000, .max = 3500000}, |
| 163 | .n = { .min = 1, .max = 4 }, |
| 164 | .m = { .min = 104, .max = 138 }, |
| 165 | .m1 = { .min = 17, .max = 23 }, |
| 166 | .m2 = { .min = 5, .max = 11 }, |
| 167 | .p = { .min = 10, .max = 30 }, |
| 168 | .p1 = { .min = 1, .max = 3}, |
| 169 | .p2 = { .dot_limit = 270000, |
| 170 | .p2_slow = 10, |
| 171 | .p2_fast = 10 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 172 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | static const intel_limit_t intel_limits_g4x_hdmi = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 176 | .dot = { .min = 22000, .max = 400000 }, |
| 177 | .vco = { .min = 1750000, .max = 3500000}, |
| 178 | .n = { .min = 1, .max = 4 }, |
| 179 | .m = { .min = 104, .max = 138 }, |
| 180 | .m1 = { .min = 16, .max = 23 }, |
| 181 | .m2 = { .min = 5, .max = 11 }, |
| 182 | .p = { .min = 5, .max = 80 }, |
| 183 | .p1 = { .min = 1, .max = 8}, |
| 184 | .p2 = { .dot_limit = 165000, |
| 185 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 189 | .dot = { .min = 20000, .max = 115000 }, |
| 190 | .vco = { .min = 1750000, .max = 3500000 }, |
| 191 | .n = { .min = 1, .max = 3 }, |
| 192 | .m = { .min = 104, .max = 138 }, |
| 193 | .m1 = { .min = 17, .max = 23 }, |
| 194 | .m2 = { .min = 5, .max = 11 }, |
| 195 | .p = { .min = 28, .max = 112 }, |
| 196 | .p1 = { .min = 2, .max = 8 }, |
| 197 | .p2 = { .dot_limit = 0, |
| 198 | .p2_slow = 14, .p2_fast = 14 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 199 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 203 | .dot = { .min = 80000, .max = 224000 }, |
| 204 | .vco = { .min = 1750000, .max = 3500000 }, |
| 205 | .n = { .min = 1, .max = 3 }, |
| 206 | .m = { .min = 104, .max = 138 }, |
| 207 | .m1 = { .min = 17, .max = 23 }, |
| 208 | .m2 = { .min = 5, .max = 11 }, |
| 209 | .p = { .min = 14, .max = 42 }, |
| 210 | .p1 = { .min = 2, .max = 6 }, |
| 211 | .p2 = { .dot_limit = 0, |
| 212 | .p2_slow = 7, .p2_fast = 7 |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 213 | }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 214 | }; |
| 215 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 216 | static const intel_limit_t intel_limits_pineview_sdvo = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 217 | .dot = { .min = 20000, .max = 400000}, |
| 218 | .vco = { .min = 1700000, .max = 3500000 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 219 | /* Pineview's Ncounter is a ring counter */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 220 | .n = { .min = 3, .max = 6 }, |
| 221 | .m = { .min = 2, .max = 256 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 222 | /* Pineview only has one combined m divider, which we treat as m2. */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 223 | .m1 = { .min = 0, .max = 0 }, |
| 224 | .m2 = { .min = 0, .max = 254 }, |
| 225 | .p = { .min = 5, .max = 80 }, |
| 226 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 227 | .p2 = { .dot_limit = 200000, |
| 228 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 229 | }; |
| 230 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 231 | static const intel_limit_t intel_limits_pineview_lvds = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 232 | .dot = { .min = 20000, .max = 400000 }, |
| 233 | .vco = { .min = 1700000, .max = 3500000 }, |
| 234 | .n = { .min = 3, .max = 6 }, |
| 235 | .m = { .min = 2, .max = 256 }, |
| 236 | .m1 = { .min = 0, .max = 0 }, |
| 237 | .m2 = { .min = 0, .max = 254 }, |
| 238 | .p = { .min = 7, .max = 112 }, |
| 239 | .p1 = { .min = 1, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 240 | .p2 = { .dot_limit = 112000, |
| 241 | .p2_slow = 14, .p2_fast = 14 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 244 | /* Ironlake / Sandybridge |
| 245 | * |
| 246 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 247 | * the range value for them is (actual_value - 2). |
| 248 | */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 249 | static const intel_limit_t intel_limits_ironlake_dac = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 250 | .dot = { .min = 25000, .max = 350000 }, |
| 251 | .vco = { .min = 1760000, .max = 3510000 }, |
| 252 | .n = { .min = 1, .max = 5 }, |
| 253 | .m = { .min = 79, .max = 127 }, |
| 254 | .m1 = { .min = 12, .max = 22 }, |
| 255 | .m2 = { .min = 5, .max = 9 }, |
| 256 | .p = { .min = 5, .max = 80 }, |
| 257 | .p1 = { .min = 1, .max = 8 }, |
| 258 | .p2 = { .dot_limit = 225000, |
| 259 | .p2_slow = 10, .p2_fast = 5 }, |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 260 | }; |
| 261 | |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 262 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 263 | .dot = { .min = 25000, .max = 350000 }, |
| 264 | .vco = { .min = 1760000, .max = 3510000 }, |
| 265 | .n = { .min = 1, .max = 3 }, |
| 266 | .m = { .min = 79, .max = 118 }, |
| 267 | .m1 = { .min = 12, .max = 22 }, |
| 268 | .m2 = { .min = 5, .max = 9 }, |
| 269 | .p = { .min = 28, .max = 112 }, |
| 270 | .p1 = { .min = 2, .max = 8 }, |
| 271 | .p2 = { .dot_limit = 225000, |
| 272 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 276 | .dot = { .min = 25000, .max = 350000 }, |
| 277 | .vco = { .min = 1760000, .max = 3510000 }, |
| 278 | .n = { .min = 1, .max = 3 }, |
| 279 | .m = { .min = 79, .max = 127 }, |
| 280 | .m1 = { .min = 12, .max = 22 }, |
| 281 | .m2 = { .min = 5, .max = 9 }, |
| 282 | .p = { .min = 14, .max = 56 }, |
| 283 | .p1 = { .min = 2, .max = 8 }, |
| 284 | .p2 = { .dot_limit = 225000, |
| 285 | .p2_slow = 7, .p2_fast = 7 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 286 | }; |
| 287 | |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 288 | /* LVDS 100mhz refclk limits. */ |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 289 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 290 | .dot = { .min = 25000, .max = 350000 }, |
| 291 | .vco = { .min = 1760000, .max = 3510000 }, |
| 292 | .n = { .min = 1, .max = 2 }, |
| 293 | .m = { .min = 79, .max = 126 }, |
| 294 | .m1 = { .min = 12, .max = 22 }, |
| 295 | .m2 = { .min = 5, .max = 9 }, |
| 296 | .p = { .min = 28, .max = 112 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 297 | .p1 = { .min = 2, .max = 8 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 298 | .p2 = { .dot_limit = 225000, |
| 299 | .p2_slow = 14, .p2_fast = 14 }, |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 303 | .dot = { .min = 25000, .max = 350000 }, |
| 304 | .vco = { .min = 1760000, .max = 3510000 }, |
| 305 | .n = { .min = 1, .max = 3 }, |
| 306 | .m = { .min = 79, .max = 126 }, |
| 307 | .m1 = { .min = 12, .max = 22 }, |
| 308 | .m2 = { .min = 5, .max = 9 }, |
| 309 | .p = { .min = 14, .max = 42 }, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 310 | .p1 = { .min = 2, .max = 6 }, |
Eric Anholt | 273e27c | 2011-03-30 13:01:10 -0700 | [diff] [blame] | 311 | .p2 = { .dot_limit = 225000, |
| 312 | .p2_slow = 7, .p2_fast = 7 }, |
Zhao Yakui | 4547668 | 2009-12-31 16:06:04 +0800 | [diff] [blame] | 313 | }; |
| 314 | |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 315 | static const intel_limit_t intel_limits_vlv = { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 316 | /* |
| 317 | * These are the data rate limits (measured in fast clocks) |
| 318 | * since those are the strictest limits we have. The fast |
| 319 | * clock and actual rate limits are more relaxed, so checking |
| 320 | * them would make no difference. |
| 321 | */ |
| 322 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
Daniel Vetter | 75e5398 | 2013-04-18 21:10:43 +0200 | [diff] [blame] | 323 | .vco = { .min = 4000000, .max = 6000000 }, |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 324 | .n = { .min = 1, .max = 7 }, |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 325 | .m1 = { .min = 2, .max = 3 }, |
| 326 | .m2 = { .min = 11, .max = 156 }, |
Ville Syrjälä | b99ab66 | 2013-09-24 21:26:26 +0300 | [diff] [blame] | 327 | .p1 = { .min = 2, .max = 3 }, |
Ville Syrjälä | 5fdc9c49 | 2013-09-24 21:26:29 +0300 | [diff] [blame] | 328 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 329 | }; |
| 330 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 331 | static void vlv_clock(int refclk, intel_clock_t *clock) |
| 332 | { |
| 333 | clock->m = clock->m1 * clock->m2; |
| 334 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 335 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 336 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 337 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 338 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 339 | } |
| 340 | |
Paulo Zanoni | e0638cd | 2013-09-24 13:52:54 -0300 | [diff] [blame] | 341 | /** |
| 342 | * Returns whether any output on the specified pipe is of the specified type |
| 343 | */ |
| 344 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
| 345 | { |
| 346 | struct drm_device *dev = crtc->dev; |
| 347 | struct intel_encoder *encoder; |
| 348 | |
| 349 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 350 | if (encoder->type == type) |
| 351 | return true; |
| 352 | |
| 353 | return false; |
| 354 | } |
| 355 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 356 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
| 357 | int refclk) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 358 | { |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 359 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 360 | const intel_limit_t *limit; |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 361 | |
| 362 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 363 | if (intel_is_dual_link_lvds(dev)) { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 364 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 365 | limit = &intel_limits_ironlake_dual_lvds_100m; |
| 366 | else |
| 367 | limit = &intel_limits_ironlake_dual_lvds; |
| 368 | } else { |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 369 | if (refclk == 100000) |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 370 | limit = &intel_limits_ironlake_single_lvds_100m; |
| 371 | else |
| 372 | limit = &intel_limits_ironlake_single_lvds; |
| 373 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 374 | } else |
Zhenyu Wang | b91ad0e | 2010-02-05 09:14:17 +0800 | [diff] [blame] | 375 | limit = &intel_limits_ironlake_dac; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 376 | |
| 377 | return limit; |
| 378 | } |
| 379 | |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 380 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
| 381 | { |
| 382 | struct drm_device *dev = crtc->dev; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 383 | const intel_limit_t *limit; |
| 384 | |
| 385 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 386 | if (intel_is_dual_link_lvds(dev)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 387 | limit = &intel_limits_g4x_dual_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 388 | else |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 389 | limit = &intel_limits_g4x_single_channel_lvds; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
| 391 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 392 | limit = &intel_limits_g4x_hdmi; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 393 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 394 | limit = &intel_limits_g4x_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 395 | } else /* The option is for other outputs */ |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 396 | limit = &intel_limits_i9xx_sdvo; |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 397 | |
| 398 | return limit; |
| 399 | } |
| 400 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 401 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 402 | { |
| 403 | struct drm_device *dev = crtc->dev; |
| 404 | const intel_limit_t *limit; |
| 405 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 406 | if (HAS_PCH_SPLIT(dev)) |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 407 | limit = intel_ironlake_limit(crtc, refclk); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 408 | else if (IS_G4X(dev)) { |
Ma Ling | 044c7c4 | 2009-03-18 20:13:23 +0800 | [diff] [blame] | 409 | limit = intel_g4x_limit(crtc); |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 410 | } else if (IS_PINEVIEW(dev)) { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 411 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 412 | limit = &intel_limits_pineview_lvds; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 413 | else |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 414 | limit = &intel_limits_pineview_sdvo; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 415 | } else if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | dc73051 | 2013-09-24 21:26:30 +0300 | [diff] [blame] | 416 | limit = &intel_limits_vlv; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 417 | } else if (!IS_GEN2(dev)) { |
| 418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
| 419 | limit = &intel_limits_i9xx_lvds; |
| 420 | else |
| 421 | limit = &intel_limits_i9xx_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 422 | } else { |
| 423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 424 | limit = &intel_limits_i8xx_lvds; |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 425 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
Keith Packard | e4b3669 | 2009-06-05 19:22:17 -0700 | [diff] [blame] | 426 | limit = &intel_limits_i8xx_dvo; |
Daniel Vetter | 5d536e2 | 2013-07-06 12:52:06 +0200 | [diff] [blame] | 427 | else |
| 428 | limit = &intel_limits_i8xx_dac; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 429 | } |
| 430 | return limit; |
| 431 | } |
| 432 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 433 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 434 | static void pineview_clock(int refclk, intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 435 | { |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 436 | clock->m = clock->m2 + 2; |
| 437 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 438 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
| 439 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 440 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
| 441 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 442 | } |
| 443 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 444 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
| 445 | { |
| 446 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 447 | } |
| 448 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 449 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 450 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 451 | clock->m = i9xx_dpll_compute_m(clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 452 | clock->p = clock->p1 * clock->p2; |
Ville Syrjälä | ed5ca77 | 2013-12-02 19:00:45 +0200 | [diff] [blame] | 453 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
| 454 | return; |
Ville Syrjälä | fb03ac0 | 2013-10-14 14:50:30 +0300 | [diff] [blame] | 455 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
| 456 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 457 | } |
| 458 | |
Jesse Barnes | 7c04d1d | 2009-02-23 15:36:40 -0800 | [diff] [blame] | 459 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 460 | /** |
| 461 | * Returns whether the given set of divisors are valid for a given refclk with |
| 462 | * the given connectors. |
| 463 | */ |
| 464 | |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 465 | static bool intel_PLL_is_valid(struct drm_device *dev, |
| 466 | const intel_limit_t *limit, |
| 467 | const intel_clock_t *clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 468 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 469 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 470 | INTELPllInvalid("n out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 471 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 472 | INTELPllInvalid("p1 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 473 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 474 | INTELPllInvalid("m2 out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 475 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 476 | INTELPllInvalid("m1 out of range\n"); |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 477 | |
| 478 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) |
| 479 | if (clock->m1 <= clock->m2) |
| 480 | INTELPllInvalid("m1 <= m2\n"); |
| 481 | |
| 482 | if (!IS_VALLEYVIEW(dev)) { |
| 483 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 484 | INTELPllInvalid("p out of range\n"); |
| 485 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 486 | INTELPllInvalid("m out of range\n"); |
| 487 | } |
| 488 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 489 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 490 | INTELPllInvalid("vco out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 491 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 492 | * connector, etc., rather than just a single range. |
| 493 | */ |
| 494 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 495 | INTELPllInvalid("dot out of range\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 496 | |
| 497 | return true; |
| 498 | } |
| 499 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 500 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 501 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 502 | int target, int refclk, intel_clock_t *match_clock, |
| 503 | intel_clock_t *best_clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 504 | { |
| 505 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 506 | intel_clock_t clock; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 507 | int err = target; |
| 508 | |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 510 | /* |
Daniel Vetter | a210b02 | 2012-11-26 17:22:08 +0100 | [diff] [blame] | 511 | * For LVDS just rely on its current settings for dual-channel. |
| 512 | * We haven't figured out how to reliably set up different |
| 513 | * single/dual channel state, if we even can. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 514 | */ |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 515 | if (intel_is_dual_link_lvds(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 516 | clock.p2 = limit->p2.p2_fast; |
| 517 | else |
| 518 | clock.p2 = limit->p2.p2_slow; |
| 519 | } else { |
| 520 | if (target < limit->p2.dot_limit) |
| 521 | clock.p2 = limit->p2.p2_slow; |
| 522 | else |
| 523 | clock.p2 = limit->p2.p2_fast; |
| 524 | } |
| 525 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 526 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 527 | |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 528 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 529 | clock.m1++) { |
| 530 | for (clock.m2 = limit->m2.min; |
| 531 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | c0efc38 | 2013-06-03 20:56:24 +0200 | [diff] [blame] | 532 | if (clock.m2 >= clock.m1) |
Zhao Yakui | 4215866 | 2009-11-20 11:24:18 +0800 | [diff] [blame] | 533 | break; |
| 534 | for (clock.n = limit->n.min; |
| 535 | clock.n <= limit->n.max; clock.n++) { |
| 536 | for (clock.p1 = limit->p1.min; |
| 537 | clock.p1 <= limit->p1.max; clock.p1++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 538 | int this_err; |
| 539 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 540 | i9xx_clock(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 541 | if (!intel_PLL_is_valid(dev, limit, |
| 542 | &clock)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 543 | continue; |
Sean Paul | cec2f35 | 2012-01-10 15:09:36 -0800 | [diff] [blame] | 544 | if (match_clock && |
| 545 | clock.p != match_clock->p) |
| 546 | continue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 547 | |
| 548 | this_err = abs(clock.dot - target); |
| 549 | if (this_err < err) { |
| 550 | *best_clock = clock; |
| 551 | err = this_err; |
| 552 | } |
| 553 | } |
| 554 | } |
| 555 | } |
| 556 | } |
| 557 | |
| 558 | return (err != target); |
| 559 | } |
| 560 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 561 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 562 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 563 | int target, int refclk, intel_clock_t *match_clock, |
| 564 | intel_clock_t *best_clock) |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 565 | { |
| 566 | struct drm_device *dev = crtc->dev; |
| 567 | intel_clock_t clock; |
| 568 | int err = target; |
| 569 | |
| 570 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 571 | /* |
| 572 | * For LVDS just rely on its current settings for dual-channel. |
| 573 | * We haven't figured out how to reliably set up different |
| 574 | * single/dual channel state, if we even can. |
| 575 | */ |
| 576 | if (intel_is_dual_link_lvds(dev)) |
| 577 | clock.p2 = limit->p2.p2_fast; |
| 578 | else |
| 579 | clock.p2 = limit->p2.p2_slow; |
| 580 | } else { |
| 581 | if (target < limit->p2.dot_limit) |
| 582 | clock.p2 = limit->p2.p2_slow; |
| 583 | else |
| 584 | clock.p2 = limit->p2.p2_fast; |
| 585 | } |
| 586 | |
| 587 | memset(best_clock, 0, sizeof(*best_clock)); |
| 588 | |
| 589 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 590 | clock.m1++) { |
| 591 | for (clock.m2 = limit->m2.min; |
| 592 | clock.m2 <= limit->m2.max; clock.m2++) { |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 593 | for (clock.n = limit->n.min; |
| 594 | clock.n <= limit->n.max; clock.n++) { |
| 595 | for (clock.p1 = limit->p1.min; |
| 596 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 597 | int this_err; |
| 598 | |
| 599 | pineview_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 600 | if (!intel_PLL_is_valid(dev, limit, |
| 601 | &clock)) |
| 602 | continue; |
| 603 | if (match_clock && |
| 604 | clock.p != match_clock->p) |
| 605 | continue; |
| 606 | |
| 607 | this_err = abs(clock.dot - target); |
| 608 | if (this_err < err) { |
| 609 | *best_clock = clock; |
| 610 | err = this_err; |
| 611 | } |
| 612 | } |
| 613 | } |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | return (err != target); |
| 618 | } |
| 619 | |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 620 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 621 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 622 | int target, int refclk, intel_clock_t *match_clock, |
| 623 | intel_clock_t *best_clock) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 624 | { |
| 625 | struct drm_device *dev = crtc->dev; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 626 | intel_clock_t clock; |
| 627 | int max_n; |
| 628 | bool found; |
Adam Jackson | 6ba770d | 2010-07-02 16:43:30 -0400 | [diff] [blame] | 629 | /* approximately equals target * 0.00585 */ |
| 630 | int err_most = (target >> 8) + (target >> 9); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 631 | found = false; |
| 632 | |
| 633 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | 1974cad | 2012-11-26 17:22:09 +0100 | [diff] [blame] | 634 | if (intel_is_dual_link_lvds(dev)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 635 | clock.p2 = limit->p2.p2_fast; |
| 636 | else |
| 637 | clock.p2 = limit->p2.p2_slow; |
| 638 | } else { |
| 639 | if (target < limit->p2.dot_limit) |
| 640 | clock.p2 = limit->p2.p2_slow; |
| 641 | else |
| 642 | clock.p2 = limit->p2.p2_fast; |
| 643 | } |
| 644 | |
| 645 | memset(best_clock, 0, sizeof(*best_clock)); |
| 646 | max_n = limit->n.max; |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 647 | /* based on hardware requirement, prefer smaller n to precision */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 648 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Gilles Espinasse | f77f13e | 2010-03-29 15:41:47 +0200 | [diff] [blame] | 649 | /* based on hardware requirement, prefere larger m1,m2 */ |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 650 | for (clock.m1 = limit->m1.max; |
| 651 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 652 | for (clock.m2 = limit->m2.max; |
| 653 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 654 | for (clock.p1 = limit->p1.max; |
| 655 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 656 | int this_err; |
| 657 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 658 | i9xx_clock(refclk, &clock); |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 659 | if (!intel_PLL_is_valid(dev, limit, |
| 660 | &clock)) |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 661 | continue; |
Chris Wilson | 1b894b5 | 2010-12-14 20:04:54 +0000 | [diff] [blame] | 662 | |
| 663 | this_err = abs(clock.dot - target); |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 664 | if (this_err < err_most) { |
| 665 | *best_clock = clock; |
| 666 | err_most = this_err; |
| 667 | max_n = clock.n; |
| 668 | found = true; |
| 669 | } |
| 670 | } |
| 671 | } |
| 672 | } |
| 673 | } |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 674 | return found; |
| 675 | } |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 676 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 677 | static bool |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 678 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
| 679 | int target, int refclk, intel_clock_t *match_clock, |
| 680 | intel_clock_t *best_clock) |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 681 | { |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 682 | struct drm_device *dev = crtc->dev; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 683 | intel_clock_t clock; |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 684 | unsigned int bestppm = 1000000; |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 685 | /* min update 19.2 MHz */ |
| 686 | int max_n = min(limit->n.max, refclk / 19200); |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 687 | bool found = false; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 688 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 689 | target *= 5; /* fast clock */ |
| 690 | |
| 691 | memset(best_clock, 0, sizeof(*best_clock)); |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 692 | |
| 693 | /* based on hardware requirement, prefer smaller n to precision */ |
Ville Syrjälä | 27e639b | 2013-09-24 21:26:24 +0300 | [diff] [blame] | 694 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
Ville Syrjälä | 811bbf0 | 2013-09-24 21:26:25 +0300 | [diff] [blame] | 695 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
Ville Syrjälä | 889059d | 2013-09-24 21:26:27 +0300 | [diff] [blame] | 696 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
Ville Syrjälä | c1a9ae4 | 2013-09-24 21:26:23 +0300 | [diff] [blame] | 697 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 698 | clock.p = clock.p1 * clock.p2; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 699 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 700 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 701 | unsigned int ppm, diff; |
| 702 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 703 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
| 704 | refclk * clock.m1); |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 705 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 706 | vlv_clock(refclk, &clock); |
| 707 | |
Ville Syrjälä | f01b796 | 2013-09-27 16:55:49 +0300 | [diff] [blame] | 708 | if (!intel_PLL_is_valid(dev, limit, |
| 709 | &clock)) |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 710 | continue; |
| 711 | |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 712 | diff = abs(clock.dot - target); |
| 713 | ppm = div_u64(1000000ULL * diff, target); |
| 714 | |
| 715 | if (ppm < 100 && clock.p > best_clock->p) { |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 716 | bestppm = 0; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 717 | *best_clock = clock; |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 718 | found = true; |
Ville Syrjälä | 43b0ac5 | 2013-09-24 21:26:18 +0300 | [diff] [blame] | 719 | } |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 720 | |
Ville Syrjälä | c686122 | 2013-09-24 21:26:21 +0300 | [diff] [blame] | 721 | if (bestppm >= 10 && ppm < bestppm - 10) { |
Ville Syrjälä | 69e4f900 | 2013-09-24 21:26:20 +0300 | [diff] [blame] | 722 | bestppm = ppm; |
Ville Syrjälä | 6b4bf1c | 2013-09-27 16:54:19 +0300 | [diff] [blame] | 723 | *best_clock = clock; |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 724 | found = true; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 725 | } |
| 726 | } |
| 727 | } |
| 728 | } |
| 729 | } |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 730 | |
Ville Syrjälä | 49e497e | 2013-09-24 21:26:31 +0300 | [diff] [blame] | 731 | return found; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 732 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 733 | |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 734 | bool intel_crtc_active(struct drm_crtc *crtc) |
| 735 | { |
| 736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 737 | |
| 738 | /* Be paranoid as we can arrive here with only partial |
| 739 | * state retrieved from the hardware during setup. |
| 740 | * |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 741 | * We can ditch the adjusted_mode.crtc_clock check as soon |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 742 | * as Haswell has gained clock readout/fastboot support. |
| 743 | * |
| 744 | * We can ditch the crtc->fb check as soon as we can |
| 745 | * properly reconstruct framebuffers. |
| 746 | */ |
| 747 | return intel_crtc->active && crtc->fb && |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 748 | intel_crtc->config.adjusted_mode.crtc_clock; |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 749 | } |
| 750 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 751 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| 752 | enum pipe pipe) |
| 753 | { |
| 754 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 756 | |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 757 | return intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 758 | } |
| 759 | |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 760 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 761 | { |
| 762 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 763 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 764 | |
| 765 | frame = I915_READ(frame_reg); |
| 766 | |
| 767 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) |
| 768 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
| 769 | } |
| 770 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 771 | /** |
| 772 | * intel_wait_for_vblank - wait for vblank on a given pipe |
| 773 | * @dev: drm device |
| 774 | * @pipe: pipe to wait for |
| 775 | * |
| 776 | * Wait for vblank to occur on a given pipe. Needed for various bits of |
| 777 | * mode setting code. |
| 778 | */ |
| 779 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 780 | { |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 782 | int pipestat_reg = PIPESTAT(pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 783 | |
Ville Syrjälä | 57e22f4 | 2013-11-06 13:56:28 -0200 | [diff] [blame] | 784 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
| 785 | g4x_wait_for_vblank(dev, pipe); |
Paulo Zanoni | a928d53 | 2012-05-04 17:18:15 -0300 | [diff] [blame] | 786 | return; |
| 787 | } |
| 788 | |
Chris Wilson | 300387c | 2010-09-05 20:25:43 +0100 | [diff] [blame] | 789 | /* Clear existing vblank status. Note this will clear any other |
| 790 | * sticky status fields as well. |
| 791 | * |
| 792 | * This races with i915_driver_irq_handler() with the result |
| 793 | * that either function could miss a vblank event. Here it is not |
| 794 | * fatal, as we will either wait upon the next vblank interrupt or |
| 795 | * timeout. Generally speaking intel_wait_for_vblank() is only |
| 796 | * called during modeset at which time the GPU should be idle and |
| 797 | * should *not* be performing page flips and thus not waiting on |
| 798 | * vblanks... |
| 799 | * Currently, the result of us stealing a vblank from the irq |
| 800 | * handler is that a single frame will be skipped during swapbuffers. |
| 801 | */ |
| 802 | I915_WRITE(pipestat_reg, |
| 803 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); |
| 804 | |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 805 | /* Wait for vblank interrupt bit to set */ |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 806 | if (wait_for(I915_READ(pipestat_reg) & |
| 807 | PIPE_VBLANK_INTERRUPT_STATUS, |
| 808 | 50)) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 809 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
| 810 | } |
| 811 | |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 812 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
| 813 | { |
| 814 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 815 | u32 reg = PIPEDSL(pipe); |
| 816 | u32 line1, line2; |
| 817 | u32 line_mask; |
| 818 | |
| 819 | if (IS_GEN2(dev)) |
| 820 | line_mask = DSL_LINEMASK_GEN2; |
| 821 | else |
| 822 | line_mask = DSL_LINEMASK_GEN3; |
| 823 | |
| 824 | line1 = I915_READ(reg) & line_mask; |
| 825 | mdelay(5); |
| 826 | line2 = I915_READ(reg) & line_mask; |
| 827 | |
| 828 | return line1 == line2; |
| 829 | } |
| 830 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 831 | /* |
| 832 | * intel_wait_for_pipe_off - wait for pipe to turn off |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 833 | * @dev: drm device |
| 834 | * @pipe: pipe to wait for |
| 835 | * |
| 836 | * After disabling a pipe, we can't wait for vblank in the usual way, |
| 837 | * spinning on the vblank interrupt status bit, since we won't actually |
| 838 | * see an interrupt when the pipe is disabled. |
| 839 | * |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 840 | * On Gen4 and above: |
| 841 | * wait for the pipe register state bit to turn off |
| 842 | * |
| 843 | * Otherwise: |
| 844 | * wait for the display line value to settle (it usually |
| 845 | * ends up stopping at the start of the next frame). |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 846 | * |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 847 | */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 848 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 849 | { |
| 850 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 851 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 852 | pipe); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 853 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 854 | if (INTEL_INFO(dev)->gen >= 4) { |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 855 | int reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 856 | |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 857 | /* Wait for the Pipe State to go off */ |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 858 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
| 859 | 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 860 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 861 | } else { |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 862 | /* Wait for the display line to settle */ |
Ville Syrjälä | fbf49ea | 2013-10-11 14:21:31 +0300 | [diff] [blame] | 863 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
Daniel Vetter | 284637d | 2012-07-09 09:51:57 +0200 | [diff] [blame] | 864 | WARN(1, "pipe_off wait timed out\n"); |
Keith Packard | ab7ad7f | 2010-10-03 00:33:06 -0700 | [diff] [blame] | 865 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 866 | } |
| 867 | |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 868 | /* |
| 869 | * ibx_digital_port_connected - is the specified port connected? |
| 870 | * @dev_priv: i915 private structure |
| 871 | * @port: the port to test |
| 872 | * |
| 873 | * Returns true if @port is connected, false otherwise. |
| 874 | */ |
| 875 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
| 876 | struct intel_digital_port *port) |
| 877 | { |
| 878 | u32 bit; |
| 879 | |
Damien Lespiau | c36346e | 2012-12-13 16:09:03 +0000 | [diff] [blame] | 880 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 881 | switch(port->port) { |
| 882 | case PORT_B: |
| 883 | bit = SDE_PORTB_HOTPLUG; |
| 884 | break; |
| 885 | case PORT_C: |
| 886 | bit = SDE_PORTC_HOTPLUG; |
| 887 | break; |
| 888 | case PORT_D: |
| 889 | bit = SDE_PORTD_HOTPLUG; |
| 890 | break; |
| 891 | default: |
| 892 | return true; |
| 893 | } |
| 894 | } else { |
| 895 | switch(port->port) { |
| 896 | case PORT_B: |
| 897 | bit = SDE_PORTB_HOTPLUG_CPT; |
| 898 | break; |
| 899 | case PORT_C: |
| 900 | bit = SDE_PORTC_HOTPLUG_CPT; |
| 901 | break; |
| 902 | case PORT_D: |
| 903 | bit = SDE_PORTD_HOTPLUG_CPT; |
| 904 | break; |
| 905 | default: |
| 906 | return true; |
| 907 | } |
Damien Lespiau | b0ea7d3 | 2012-12-13 16:09:00 +0000 | [diff] [blame] | 908 | } |
| 909 | |
| 910 | return I915_READ(SDEISR) & bit; |
| 911 | } |
| 912 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 913 | static const char *state_string(bool enabled) |
| 914 | { |
| 915 | return enabled ? "on" : "off"; |
| 916 | } |
| 917 | |
| 918 | /* Only for pre-ILK configs */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 919 | void assert_pll(struct drm_i915_private *dev_priv, |
| 920 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 921 | { |
| 922 | int reg; |
| 923 | u32 val; |
| 924 | bool cur_state; |
| 925 | |
| 926 | reg = DPLL(pipe); |
| 927 | val = I915_READ(reg); |
| 928 | cur_state = !!(val & DPLL_VCO_ENABLE); |
| 929 | WARN(cur_state != state, |
| 930 | "PLL state assertion failure (expected %s, current %s)\n", |
| 931 | state_string(state), state_string(cur_state)); |
| 932 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 933 | |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 934 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
| 935 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
| 936 | { |
| 937 | u32 val; |
| 938 | bool cur_state; |
| 939 | |
| 940 | mutex_lock(&dev_priv->dpio_lock); |
| 941 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
| 942 | mutex_unlock(&dev_priv->dpio_lock); |
| 943 | |
| 944 | cur_state = val & DSI_PLL_VCO_EN; |
| 945 | WARN(cur_state != state, |
| 946 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
| 947 | state_string(state), state_string(cur_state)); |
| 948 | } |
| 949 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) |
| 950 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) |
| 951 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 952 | struct intel_shared_dpll * |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 953 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 954 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 955 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 956 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 957 | if (crtc->config.shared_dpll < 0) |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 958 | return NULL; |
| 959 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 960 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 961 | } |
| 962 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 963 | /* For ILK+ */ |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 964 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 965 | struct intel_shared_dpll *pll, |
| 966 | bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 967 | { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 968 | bool cur_state; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 969 | struct intel_dpll_hw_state hw_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 970 | |
Eugeni Dodonov | 9d82aa1 | 2012-05-09 15:37:17 -0300 | [diff] [blame] | 971 | if (HAS_PCH_LPT(dev_priv->dev)) { |
| 972 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); |
| 973 | return; |
| 974 | } |
| 975 | |
Chris Wilson | 92b27b0 | 2012-05-20 18:10:50 +0100 | [diff] [blame] | 976 | if (WARN (!pll, |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 977 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 978 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 979 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 980 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
Chris Wilson | 92b27b0 | 2012-05-20 18:10:50 +0100 | [diff] [blame] | 981 | WARN(cur_state != state, |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 982 | "%s assertion failure (expected %s, current %s)\n", |
| 983 | pll->name, state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 984 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 985 | |
| 986 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
| 987 | enum pipe pipe, bool state) |
| 988 | { |
| 989 | int reg; |
| 990 | u32 val; |
| 991 | bool cur_state; |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 992 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 993 | pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 994 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 995 | if (HAS_DDI(dev_priv->dev)) { |
| 996 | /* DDI does not have a specific FDI_TX register */ |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 997 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 998 | val = I915_READ(reg); |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 999 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1000 | } else { |
| 1001 | reg = FDI_TX_CTL(pipe); |
| 1002 | val = I915_READ(reg); |
| 1003 | cur_state = !!(val & FDI_TX_ENABLE); |
| 1004 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1005 | WARN(cur_state != state, |
| 1006 | "FDI TX state assertion failure (expected %s, current %s)\n", |
| 1007 | state_string(state), state_string(cur_state)); |
| 1008 | } |
| 1009 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) |
| 1010 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) |
| 1011 | |
| 1012 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, |
| 1013 | enum pipe pipe, bool state) |
| 1014 | { |
| 1015 | int reg; |
| 1016 | u32 val; |
| 1017 | bool cur_state; |
| 1018 | |
Paulo Zanoni | d63fa0d | 2012-11-20 13:27:35 -0200 | [diff] [blame] | 1019 | reg = FDI_RX_CTL(pipe); |
| 1020 | val = I915_READ(reg); |
| 1021 | cur_state = !!(val & FDI_RX_ENABLE); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1022 | WARN(cur_state != state, |
| 1023 | "FDI RX state assertion failure (expected %s, current %s)\n", |
| 1024 | state_string(state), state_string(cur_state)); |
| 1025 | } |
| 1026 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) |
| 1027 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) |
| 1028 | |
| 1029 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, |
| 1030 | enum pipe pipe) |
| 1031 | { |
| 1032 | int reg; |
| 1033 | u32 val; |
| 1034 | |
| 1035 | /* ILK FDI PLL is always enabled */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1036 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1037 | return; |
| 1038 | |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1039 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 1040 | if (HAS_DDI(dev_priv->dev)) |
Eugeni Dodonov | bf507ef | 2012-05-09 15:37:18 -0300 | [diff] [blame] | 1041 | return; |
| 1042 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1043 | reg = FDI_TX_CTL(pipe); |
| 1044 | val = I915_READ(reg); |
| 1045 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
| 1046 | } |
| 1047 | |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1048 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
| 1049 | enum pipe pipe, bool state) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1050 | { |
| 1051 | int reg; |
| 1052 | u32 val; |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1053 | bool cur_state; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1054 | |
| 1055 | reg = FDI_RX_CTL(pipe); |
| 1056 | val = I915_READ(reg); |
Daniel Vetter | 55607e8 | 2013-06-16 21:42:39 +0200 | [diff] [blame] | 1057 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
| 1058 | WARN(cur_state != state, |
| 1059 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
| 1060 | state_string(state), state_string(cur_state)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1061 | } |
| 1062 | |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1063 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
| 1064 | enum pipe pipe) |
| 1065 | { |
| 1066 | int pp_reg, lvds_reg; |
| 1067 | u32 val; |
| 1068 | enum pipe panel_pipe = PIPE_A; |
Thomas Jarosch | 0de3b48 | 2011-08-25 15:37:45 +0200 | [diff] [blame] | 1069 | bool locked = true; |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1070 | |
| 1071 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
| 1072 | pp_reg = PCH_PP_CONTROL; |
| 1073 | lvds_reg = PCH_LVDS; |
| 1074 | } else { |
| 1075 | pp_reg = PP_CONTROL; |
| 1076 | lvds_reg = LVDS; |
| 1077 | } |
| 1078 | |
| 1079 | val = I915_READ(pp_reg); |
| 1080 | if (!(val & PANEL_POWER_ON) || |
| 1081 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) |
| 1082 | locked = false; |
| 1083 | |
| 1084 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) |
| 1085 | panel_pipe = PIPE_B; |
| 1086 | |
| 1087 | WARN(panel_pipe == pipe && locked, |
| 1088 | "panel assertion failure, pipe %c regs locked\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1089 | pipe_name(pipe)); |
Jesse Barnes | ea0760c | 2011-01-04 15:09:32 -0800 | [diff] [blame] | 1090 | } |
| 1091 | |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1092 | static void assert_cursor(struct drm_i915_private *dev_priv, |
| 1093 | enum pipe pipe, bool state) |
| 1094 | { |
| 1095 | struct drm_device *dev = dev_priv->dev; |
| 1096 | bool cur_state; |
| 1097 | |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1098 | if (IS_845G(dev) || IS_I865G(dev)) |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1099 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1100 | else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1101 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
Paulo Zanoni | d9d8208 | 2014-02-27 16:30:56 -0300 | [diff] [blame] | 1102 | else |
| 1103 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1104 | |
| 1105 | WARN(cur_state != state, |
| 1106 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
| 1107 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
| 1108 | } |
| 1109 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) |
| 1110 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) |
| 1111 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1112 | void assert_pipe(struct drm_i915_private *dev_priv, |
| 1113 | enum pipe pipe, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1114 | { |
| 1115 | int reg; |
| 1116 | u32 val; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1117 | bool cur_state; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1119 | pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1120 | |
Daniel Vetter | 8e63678 | 2012-01-22 01:36:48 +0100 | [diff] [blame] | 1121 | /* if we need the pipe A quirk it must be always on */ |
| 1122 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 1123 | state = true; |
| 1124 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 1125 | if (!intel_display_power_enabled(dev_priv, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 1126 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
Paulo Zanoni | 6931016 | 2013-01-29 16:35:19 -0200 | [diff] [blame] | 1127 | cur_state = false; |
| 1128 | } else { |
| 1129 | reg = PIPECONF(cpu_transcoder); |
| 1130 | val = I915_READ(reg); |
| 1131 | cur_state = !!(val & PIPECONF_ENABLE); |
| 1132 | } |
| 1133 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1134 | WARN(cur_state != state, |
| 1135 | "pipe %c assertion failure (expected %s, current %s)\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1136 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1137 | } |
| 1138 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1139 | static void assert_plane(struct drm_i915_private *dev_priv, |
| 1140 | enum plane plane, bool state) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1141 | { |
| 1142 | int reg; |
| 1143 | u32 val; |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1144 | bool cur_state; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1145 | |
| 1146 | reg = DSPCNTR(plane); |
| 1147 | val = I915_READ(reg); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1148 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
| 1149 | WARN(cur_state != state, |
| 1150 | "plane %c assertion failure (expected %s, current %s)\n", |
| 1151 | plane_name(plane), state_string(state), state_string(cur_state)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1152 | } |
| 1153 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 1154 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
| 1155 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) |
| 1156 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1157 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
| 1158 | enum pipe pipe) |
| 1159 | { |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1160 | struct drm_device *dev = dev_priv->dev; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1161 | int reg, i; |
| 1162 | u32 val; |
| 1163 | int cur_pipe; |
| 1164 | |
Ville Syrjälä | 653e102 | 2013-06-04 13:49:05 +0300 | [diff] [blame] | 1165 | /* Primary planes are fixed to pipes on gen4+ */ |
| 1166 | if (INTEL_INFO(dev)->gen >= 4) { |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1167 | reg = DSPCNTR(pipe); |
| 1168 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1169 | WARN(val & DISPLAY_PLANE_ENABLE, |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1170 | "plane %c assertion failure, should be disabled but not\n", |
| 1171 | plane_name(pipe)); |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1172 | return; |
Adam Jackson | 28c05794 | 2011-10-07 14:38:42 -0400 | [diff] [blame] | 1173 | } |
Jesse Barnes | 19ec135 | 2011-02-02 12:28:02 -0800 | [diff] [blame] | 1174 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1175 | /* Need to check both planes against the pipe */ |
Damien Lespiau | 08e2a7d | 2013-07-11 20:10:54 +0100 | [diff] [blame] | 1176 | for_each_pipe(i) { |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1177 | reg = DSPCNTR(i); |
| 1178 | val = I915_READ(reg); |
| 1179 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> |
| 1180 | DISPPLANE_SEL_PIPE_SHIFT; |
| 1181 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1182 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
| 1183 | plane_name(i), pipe_name(pipe)); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1184 | } |
| 1185 | } |
| 1186 | |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1187 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
| 1188 | enum pipe pipe) |
| 1189 | { |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1190 | struct drm_device *dev = dev_priv->dev; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1191 | int reg, sprite; |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1192 | u32 val; |
| 1193 | |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1194 | if (IS_VALLEYVIEW(dev)) { |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1195 | for_each_sprite(pipe, sprite) { |
| 1196 | reg = SPCNTR(pipe, sprite); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1197 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1198 | WARN(val & SP_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1199 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 1200 | sprite_name(pipe, sprite), pipe_name(pipe)); |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1201 | } |
| 1202 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 1203 | reg = SPRCTL(pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1204 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1205 | WARN(val & SPRITE_ENABLE, |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 1206 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1207 | plane_name(pipe), pipe_name(pipe)); |
| 1208 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 1209 | reg = DVSCNTR(pipe); |
| 1210 | val = I915_READ(reg); |
Damien Lespiau | 83f26f1 | 2014-03-17 17:59:48 +0000 | [diff] [blame] | 1211 | WARN(val & DVS_ENABLE, |
Ville Syrjälä | 20674ee | 2013-06-04 13:49:06 +0300 | [diff] [blame] | 1212 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
| 1213 | plane_name(pipe), pipe_name(pipe)); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1214 | } |
| 1215 | } |
| 1216 | |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 1217 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1218 | { |
| 1219 | u32 val; |
| 1220 | bool enabled; |
| 1221 | |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 1222 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
Eugeni Dodonov | 9d82aa1 | 2012-05-09 15:37:17 -0300 | [diff] [blame] | 1223 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1224 | val = I915_READ(PCH_DREF_CONTROL); |
| 1225 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 1226 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 1227 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 1228 | } |
| 1229 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1230 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
| 1231 | enum pipe pipe) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1232 | { |
| 1233 | int reg; |
| 1234 | u32 val; |
| 1235 | bool enabled; |
| 1236 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1237 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1238 | val = I915_READ(reg); |
| 1239 | enabled = !!(val & TRANS_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1240 | WARN(enabled, |
| 1241 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
| 1242 | pipe_name(pipe)); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1243 | } |
| 1244 | |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1245 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1246 | enum pipe pipe, u32 port_sel, u32 val) |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1247 | { |
| 1248 | if ((val & DP_PORT_EN) == 0) |
| 1249 | return false; |
| 1250 | |
| 1251 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1252 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); |
| 1253 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); |
| 1254 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
| 1255 | return false; |
| 1256 | } else { |
| 1257 | if ((val & DP_PIPE_MASK) != (pipe << 30)) |
| 1258 | return false; |
| 1259 | } |
| 1260 | return true; |
| 1261 | } |
| 1262 | |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1263 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1264 | enum pipe pipe, u32 val) |
| 1265 | { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1266 | if ((val & SDVO_ENABLE) == 0) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1267 | return false; |
| 1268 | |
| 1269 | if (HAS_PCH_CPT(dev_priv->dev)) { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1270 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1271 | return false; |
| 1272 | } else { |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1273 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
Keith Packard | 1519b99 | 2011-08-06 10:35:34 -0700 | [diff] [blame] | 1274 | return false; |
| 1275 | } |
| 1276 | return true; |
| 1277 | } |
| 1278 | |
| 1279 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1280 | enum pipe pipe, u32 val) |
| 1281 | { |
| 1282 | if ((val & LVDS_PORT_EN) == 0) |
| 1283 | return false; |
| 1284 | |
| 1285 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1286 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1287 | return false; |
| 1288 | } else { |
| 1289 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) |
| 1290 | return false; |
| 1291 | } |
| 1292 | return true; |
| 1293 | } |
| 1294 | |
| 1295 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, |
| 1296 | enum pipe pipe, u32 val) |
| 1297 | { |
| 1298 | if ((val & ADPA_DAC_ENABLE) == 0) |
| 1299 | return false; |
| 1300 | if (HAS_PCH_CPT(dev_priv->dev)) { |
| 1301 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
| 1302 | return false; |
| 1303 | } else { |
| 1304 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) |
| 1305 | return false; |
| 1306 | } |
| 1307 | return true; |
| 1308 | } |
| 1309 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1310 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1311 | enum pipe pipe, int reg, u32 port_sel) |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1312 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1313 | u32 val = I915_READ(reg); |
Keith Packard | 4e63438 | 2011-08-06 10:39:45 -0700 | [diff] [blame] | 1314 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1315 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1316 | reg, pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1317 | |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1318 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
| 1319 | && (val & DP_PIPEB_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1320 | "IBX PCH dp port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1321 | } |
| 1322 | |
| 1323 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, |
| 1324 | enum pipe pipe, int reg) |
| 1325 | { |
Jesse Barnes | 47a05ec | 2011-02-07 13:46:40 -0800 | [diff] [blame] | 1326 | u32 val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1327 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
Adam Jackson | 23c99e7 | 2011-10-07 14:38:43 -0400 | [diff] [blame] | 1328 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1329 | reg, pipe_name(pipe)); |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1330 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 1331 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
Daniel Vetter | 75c5da2 | 2012-09-10 21:58:29 +0200 | [diff] [blame] | 1332 | && (val & SDVO_PIPE_B_SELECT), |
Daniel Vetter | de9a35a | 2012-06-05 11:03:40 +0200 | [diff] [blame] | 1333 | "IBX PCH hdmi port still using transcoder B\n"); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1334 | } |
| 1335 | |
| 1336 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, |
| 1337 | enum pipe pipe) |
| 1338 | { |
| 1339 | int reg; |
| 1340 | u32 val; |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1341 | |
Keith Packard | f0575e9 | 2011-07-25 22:12:43 -0700 | [diff] [blame] | 1342 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
| 1343 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); |
| 1344 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1345 | |
| 1346 | reg = PCH_ADPA; |
| 1347 | val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1348 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1349 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1350 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1351 | |
| 1352 | reg = PCH_LVDS; |
| 1353 | val = I915_READ(reg); |
Xu, Anhua | b70ad58 | 2012-08-13 03:08:33 +0000 | [diff] [blame] | 1354 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1355 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 1356 | pipe_name(pipe)); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1357 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 1358 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
| 1359 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); |
| 1360 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1361 | } |
| 1362 | |
Jesse Barnes | 40e9cf6 | 2013-10-03 11:35:46 -0700 | [diff] [blame] | 1363 | static void intel_init_dpio(struct drm_device *dev) |
| 1364 | { |
| 1365 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1366 | |
| 1367 | if (!IS_VALLEYVIEW(dev)) |
| 1368 | return; |
| 1369 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1370 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
Jesse Barnes | 5382f5f35 | 2013-12-16 16:34:24 -0800 | [diff] [blame] | 1371 | } |
| 1372 | |
| 1373 | static void intel_reset_dpio(struct drm_device *dev) |
| 1374 | { |
| 1375 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1376 | |
| 1377 | if (!IS_VALLEYVIEW(dev)) |
| 1378 | return; |
| 1379 | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1380 | /* |
| 1381 | * Enable the CRI clock source so we can get at the display and the |
| 1382 | * reference clock for VGA hotplug / manual detection. |
| 1383 | */ |
Imre Deak | 404faab | 2014-01-09 17:08:15 +0200 | [diff] [blame] | 1384 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1385 | DPLL_REFA_CLK_ENABLE_VLV | |
Imre Deak | 404faab | 2014-01-09 17:08:15 +0200 | [diff] [blame] | 1386 | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 1387 | |
Jesse Barnes | 40e9cf6 | 2013-10-03 11:35:46 -0700 | [diff] [blame] | 1388 | /* |
| 1389 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
| 1390 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
| 1391 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
| 1392 | * b. The other bits such as sfr settings / modesel may all be set |
| 1393 | * to 0. |
| 1394 | * |
| 1395 | * This should only be done on init and resume from S3 with both |
| 1396 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. |
| 1397 | */ |
| 1398 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
| 1399 | } |
| 1400 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1401 | static void vlv_enable_pll(struct intel_crtc *crtc) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1402 | { |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1403 | struct drm_device *dev = crtc->base.dev; |
| 1404 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1405 | int reg = DPLL(crtc->pipe); |
| 1406 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1407 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1408 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1409 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1410 | /* No really, not for ILK+ */ |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1411 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); |
| 1412 | |
| 1413 | /* PLL is protected by panel, make sure we can write it */ |
| 1414 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1415 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1416 | |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1417 | I915_WRITE(reg, dpll); |
| 1418 | POSTING_READ(reg); |
| 1419 | udelay(150); |
| 1420 | |
| 1421 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
| 1422 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); |
| 1423 | |
| 1424 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); |
| 1425 | POSTING_READ(DPLL_MD(crtc->pipe)); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1426 | |
| 1427 | /* We do this three times for luck */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1428 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1429 | POSTING_READ(reg); |
| 1430 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1431 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1432 | POSTING_READ(reg); |
| 1433 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 426115c | 2013-07-11 22:13:42 +0200 | [diff] [blame] | 1434 | I915_WRITE(reg, dpll); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1435 | POSTING_READ(reg); |
| 1436 | udelay(150); /* wait for warmup */ |
| 1437 | } |
| 1438 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1439 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1440 | { |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1441 | struct drm_device *dev = crtc->base.dev; |
| 1442 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1443 | int reg = DPLL(crtc->pipe); |
| 1444 | u32 dpll = crtc->config.dpll_hw_state.dpll; |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1445 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1446 | assert_pipe_disabled(dev_priv, crtc->pipe); |
Daniel Vetter | 87442f7 | 2013-06-06 00:52:17 +0200 | [diff] [blame] | 1447 | |
| 1448 | /* No really, not for ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1449 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1450 | |
| 1451 | /* PLL is protected by panel, make sure we can write it */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1452 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
| 1453 | assert_panel_unlocked(dev_priv, crtc->pipe); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1454 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1455 | I915_WRITE(reg, dpll); |
| 1456 | |
| 1457 | /* Wait for the clocks to stabilize. */ |
| 1458 | POSTING_READ(reg); |
| 1459 | udelay(150); |
| 1460 | |
| 1461 | if (INTEL_INFO(dev)->gen >= 4) { |
| 1462 | I915_WRITE(DPLL_MD(crtc->pipe), |
| 1463 | crtc->config.dpll_hw_state.dpll_md); |
| 1464 | } else { |
| 1465 | /* The pixel multiplier can only be updated once the |
| 1466 | * DPLL is enabled and the clocks are stable. |
| 1467 | * |
| 1468 | * So write it again. |
| 1469 | */ |
| 1470 | I915_WRITE(reg, dpll); |
| 1471 | } |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1472 | |
| 1473 | /* We do this three times for luck */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1474 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1475 | POSTING_READ(reg); |
| 1476 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1477 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1478 | POSTING_READ(reg); |
| 1479 | udelay(150); /* wait for warmup */ |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 1480 | I915_WRITE(reg, dpll); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1481 | POSTING_READ(reg); |
| 1482 | udelay(150); /* wait for warmup */ |
| 1483 | } |
| 1484 | |
| 1485 | /** |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1486 | * i9xx_disable_pll - disable a PLL |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1487 | * @dev_priv: i915 private structure |
| 1488 | * @pipe: pipe PLL to disable |
| 1489 | * |
| 1490 | * Disable the PLL for @pipe, making sure the pipe is off first. |
| 1491 | * |
| 1492 | * Note! This is for pre-ILK only. |
| 1493 | */ |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1494 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1495 | { |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1496 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1497 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1498 | return; |
| 1499 | |
| 1500 | /* Make sure the pipe isn't still relying on us */ |
| 1501 | assert_pipe_disabled(dev_priv, pipe); |
| 1502 | |
Daniel Vetter | 50b44a4 | 2013-06-05 13:34:33 +0200 | [diff] [blame] | 1503 | I915_WRITE(DPLL(pipe), 0); |
| 1504 | POSTING_READ(DPLL(pipe)); |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1505 | } |
| 1506 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1507 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 1508 | { |
| 1509 | u32 val = 0; |
| 1510 | |
| 1511 | /* Make sure the pipe isn't still relying on us */ |
| 1512 | assert_pipe_disabled(dev_priv, pipe); |
| 1513 | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1514 | /* |
| 1515 | * Leave integrated clock source and reference clock enabled for pipe B. |
| 1516 | * The latter is needed for VGA hotplug / manual detection. |
| 1517 | */ |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1518 | if (pipe == PIPE_B) |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 1519 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 1520 | I915_WRITE(DPLL(pipe), val); |
| 1521 | POSTING_READ(DPLL(pipe)); |
| 1522 | } |
| 1523 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1524 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
| 1525 | struct intel_digital_port *dport) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1526 | { |
| 1527 | u32 port_mask; |
| 1528 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1529 | switch (dport->port) { |
| 1530 | case PORT_B: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1531 | port_mask = DPLL_PORTB_READY_MASK; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1532 | break; |
| 1533 | case PORT_C: |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1534 | port_mask = DPLL_PORTC_READY_MASK; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1535 | break; |
| 1536 | default: |
| 1537 | BUG(); |
| 1538 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1539 | |
| 1540 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) |
| 1541 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
Ville Syrjälä | be46ffd | 2013-11-29 13:21:49 +0200 | [diff] [blame] | 1542 | port_name(dport->port), I915_READ(DPLL(0))); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1543 | } |
| 1544 | |
Jesse Barnes | 63d7bbe | 2011-01-04 15:09:33 -0800 | [diff] [blame] | 1545 | /** |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1546 | * ironlake_enable_shared_dpll - enable PCH PLL |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1547 | * @dev_priv: i915 private structure |
| 1548 | * @pipe: pipe PLL to enable |
| 1549 | * |
| 1550 | * The PCH PLL needs to be enabled before the PCH transcoder, since it |
| 1551 | * drives the transcoder clock. |
| 1552 | */ |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1553 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1554 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1555 | struct drm_device *dev = crtc->base.dev; |
| 1556 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1557 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1558 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1559 | /* PCH PLLs only available on ILK, SNB and IVB */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1560 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
Daniel Vetter | 87a875b | 2013-06-05 13:34:19 +0200 | [diff] [blame] | 1561 | if (WARN_ON(pll == NULL)) |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1562 | return; |
| 1563 | |
| 1564 | if (WARN_ON(pll->refcount == 0)) |
| 1565 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1566 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1567 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
| 1568 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1569 | crtc->base.base.id); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1570 | |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1571 | if (pll->active++) { |
| 1572 | WARN_ON(!pll->on); |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1573 | assert_shared_dpll_enabled(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1574 | return; |
| 1575 | } |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1576 | WARN_ON(pll->on); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1577 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1578 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1579 | pll->enable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1580 | pll->on = true; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1581 | } |
| 1582 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1583 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1584 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1585 | struct drm_device *dev = crtc->base.dev; |
| 1586 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1587 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | 4c609cb | 2011-09-02 12:52:11 -0700 | [diff] [blame] | 1588 | |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1589 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1590 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
Daniel Vetter | 87a875b | 2013-06-05 13:34:19 +0200 | [diff] [blame] | 1591 | if (WARN_ON(pll == NULL)) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1592 | return; |
| 1593 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1594 | if (WARN_ON(pll->refcount == 0)) |
| 1595 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1596 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1597 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
| 1598 | pll->name, pll->active, pll->on, |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1599 | crtc->base.base.id); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1600 | |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1601 | if (WARN_ON(pll->active == 0)) { |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1602 | assert_shared_dpll_disabled(dev_priv, pll); |
Chris Wilson | 48da64a | 2012-05-13 20:16:12 +0100 | [diff] [blame] | 1603 | return; |
| 1604 | } |
| 1605 | |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1606 | assert_shared_dpll_enabled(dev_priv, pll); |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 1607 | WARN_ON(!pll->on); |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 1608 | if (--pll->active) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1609 | return; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1610 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 1611 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 1612 | pll->disable(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1613 | pll->on = false; |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1614 | } |
| 1615 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1616 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1617 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1618 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1619 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1620 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 1621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1622 | uint32_t reg, val, pipeconf_val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1623 | |
| 1624 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1625 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1626 | |
| 1627 | /* Make sure PCH DPLL is enabled */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1628 | assert_shared_dpll_enabled(dev_priv, |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 1629 | intel_crtc_to_shared_dpll(intel_crtc)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1630 | |
| 1631 | /* FDI must be feeding us bits for PCH ports */ |
| 1632 | assert_fdi_tx_enabled(dev_priv, pipe); |
| 1633 | assert_fdi_rx_enabled(dev_priv, pipe); |
| 1634 | |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1635 | if (HAS_PCH_CPT(dev)) { |
| 1636 | /* Workaround: Set the timing override bit before enabling the |
| 1637 | * pch transcoder. */ |
| 1638 | reg = TRANS_CHICKEN2(pipe); |
| 1639 | val = I915_READ(reg); |
| 1640 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1641 | I915_WRITE(reg, val); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 1642 | } |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1643 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1644 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1645 | val = I915_READ(reg); |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1646 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1647 | |
| 1648 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 1649 | /* |
| 1650 | * make the BPC in transcoder be consistent with |
| 1651 | * that in pipeconf reg. |
| 1652 | */ |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 1653 | val &= ~PIPECONF_BPC_MASK; |
| 1654 | val |= pipeconf_val & PIPECONF_BPC_MASK; |
Jesse Barnes | e9bcff5 | 2011-06-24 12:19:20 -0700 | [diff] [blame] | 1655 | } |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1656 | |
| 1657 | val &= ~TRANS_INTERLACE_MASK; |
| 1658 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | 7c26e5c | 2012-02-14 17:07:09 -0200 | [diff] [blame] | 1659 | if (HAS_PCH_IBX(dev_priv->dev) && |
| 1660 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) |
| 1661 | val |= TRANS_LEGACY_INTERLACED_ILK; |
| 1662 | else |
| 1663 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 5f7f726 | 2012-02-03 17:47:15 -0200 | [diff] [blame] | 1664 | else |
| 1665 | val |= TRANS_PROGRESSIVE; |
| 1666 | |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1667 | I915_WRITE(reg, val | TRANS_ENABLE); |
| 1668 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1669 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1670 | } |
| 1671 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1672 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1673 | enum transcoder cpu_transcoder) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1674 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1675 | u32 val, pipeconf_val; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1676 | |
| 1677 | /* PCH only available on ILK+ */ |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1678 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1679 | |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1680 | /* FDI must be feeding us bits for PCH ports */ |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1681 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1682 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1683 | |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1684 | /* Workaround: set timing override bit. */ |
| 1685 | val = I915_READ(_TRANSA_CHICKEN2); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1686 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1687 | I915_WRITE(_TRANSA_CHICKEN2, val); |
| 1688 | |
Paulo Zanoni | 25f3ef1 | 2012-10-31 18:12:49 -0200 | [diff] [blame] | 1689 | val = TRANS_ENABLE; |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1690 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1691 | |
Paulo Zanoni | 9a76b1c | 2012-10-31 18:12:48 -0200 | [diff] [blame] | 1692 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
| 1693 | PIPECONF_INTERLACED_ILK) |
Paulo Zanoni | a35f267 | 2012-10-31 18:12:45 -0200 | [diff] [blame] | 1694 | val |= TRANS_INTERLACED; |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1695 | else |
| 1696 | val |= TRANS_PROGRESSIVE; |
| 1697 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1698 | I915_WRITE(LPT_TRANSCONF, val); |
| 1699 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 1700 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1701 | } |
| 1702 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 1703 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
| 1704 | enum pipe pipe) |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1705 | { |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1706 | struct drm_device *dev = dev_priv->dev; |
| 1707 | uint32_t reg, val; |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1708 | |
| 1709 | /* FDI relies on the transcoder */ |
| 1710 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 1711 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 1712 | |
Jesse Barnes | 291906f | 2011-02-02 12:28:03 -0800 | [diff] [blame] | 1713 | /* Ports must be off as well */ |
| 1714 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1715 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1716 | reg = PCH_TRANSCONF(pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1717 | val = I915_READ(reg); |
| 1718 | val &= ~TRANS_ENABLE; |
| 1719 | I915_WRITE(reg, val); |
| 1720 | /* wait for PCH transcoder off, transcoder state */ |
| 1721 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
Ville Syrjälä | 4bb6f1f | 2013-04-17 17:48:50 +0300 | [diff] [blame] | 1722 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1723 | |
| 1724 | if (!HAS_PCH_IBX(dev)) { |
| 1725 | /* Workaround: Clear the timing override chicken bit again. */ |
| 1726 | reg = TRANS_CHICKEN2(pipe); |
| 1727 | val = I915_READ(reg); |
| 1728 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 1729 | I915_WRITE(reg, val); |
| 1730 | } |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1731 | } |
| 1732 | |
Paulo Zanoni | ab4d966 | 2012-10-31 18:12:55 -0200 | [diff] [blame] | 1733 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1734 | { |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1735 | u32 val; |
| 1736 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1737 | val = I915_READ(LPT_TRANSCONF); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1738 | val &= ~TRANS_ENABLE; |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1739 | I915_WRITE(LPT_TRANSCONF, val); |
Paulo Zanoni | 8fb033d | 2012-10-31 18:12:43 -0200 | [diff] [blame] | 1740 | /* wait for PCH transcoder off, transcoder state */ |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 1741 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
Paulo Zanoni | 8a52fd9 | 2012-10-31 18:12:51 -0200 | [diff] [blame] | 1742 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1743 | |
| 1744 | /* Workaround: clear timing override bit. */ |
| 1745 | val = I915_READ(_TRANSA_CHICKEN2); |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 1746 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
Paulo Zanoni | 223a6fd | 2012-10-31 18:12:52 -0200 | [diff] [blame] | 1747 | I915_WRITE(_TRANSA_CHICKEN2, val); |
Jesse Barnes | 92f2584 | 2011-01-04 15:09:34 -0800 | [diff] [blame] | 1748 | } |
| 1749 | |
| 1750 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1751 | * intel_enable_pipe - enable a pipe, asserting requirements |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1752 | * @crtc: crtc responsible for the pipe |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1753 | * |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1754 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1755 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1756 | */ |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 1757 | static void intel_enable_pipe(struct intel_crtc *crtc) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1758 | { |
Paulo Zanoni | 0372264 | 2014-01-17 13:51:09 -0200 | [diff] [blame] | 1759 | struct drm_device *dev = crtc->base.dev; |
| 1760 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1761 | enum pipe pipe = crtc->pipe; |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1762 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1763 | pipe); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1764 | enum pipe pch_transcoder; |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1765 | int reg; |
| 1766 | u32 val; |
| 1767 | |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1768 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1769 | assert_cursor_disabled(dev_priv, pipe); |
Daniel Vetter | 58c6eaa | 2013-04-11 16:29:09 +0200 | [diff] [blame] | 1770 | assert_sprites_disabled(dev_priv, pipe); |
| 1771 | |
Paulo Zanoni | 681e581 | 2012-12-06 11:12:38 -0200 | [diff] [blame] | 1772 | if (HAS_PCH_LPT(dev_priv->dev)) |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 1773 | pch_transcoder = TRANSCODER_A; |
| 1774 | else |
| 1775 | pch_transcoder = pipe; |
| 1776 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1777 | /* |
| 1778 | * A pipe without a PLL won't actually be able to drive bits from |
| 1779 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 1780 | * need the check. |
| 1781 | */ |
| 1782 | if (!HAS_PCH_SPLIT(dev_priv->dev)) |
Paulo Zanoni | fbf3218 | 2014-01-17 13:51:11 -0200 | [diff] [blame] | 1783 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 1784 | assert_dsi_pll_enabled(dev_priv); |
| 1785 | else |
| 1786 | assert_pll_enabled(dev_priv, pipe); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1787 | else { |
Paulo Zanoni | 30421c4 | 2014-01-17 13:51:10 -0200 | [diff] [blame] | 1788 | if (crtc->config.has_pch_encoder) { |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1789 | /* if driving the PCH, we need FDI enabled */ |
Paulo Zanoni | cc391bb | 2012-11-20 13:27:37 -0200 | [diff] [blame] | 1790 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1791 | assert_fdi_tx_pll_enabled(dev_priv, |
| 1792 | (enum pipe) cpu_transcoder); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 1793 | } |
| 1794 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1795 | } |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1796 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1797 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1798 | val = I915_READ(reg); |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 1799 | if (val & PIPECONF_ENABLE) { |
| 1800 | WARN_ON(!(pipe == PIPE_A && |
| 1801 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1802 | return; |
Paulo Zanoni | 7ad25d4 | 2014-01-17 13:51:13 -0200 | [diff] [blame] | 1803 | } |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1804 | |
| 1805 | I915_WRITE(reg, val | PIPECONF_ENABLE); |
Paulo Zanoni | 851855d | 2013-12-19 19:12:29 -0200 | [diff] [blame] | 1806 | POSTING_READ(reg); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 1807 | |
| 1808 | /* |
| 1809 | * There's no guarantee the pipe will really start running now. It |
| 1810 | * depends on the Gen, the output type and the relative order between |
| 1811 | * pipe and plane enabling. Avoid waiting on HSW+ since it's not |
| 1812 | * necessary. |
| 1813 | * TODO: audit the previous gens. |
| 1814 | */ |
| 1815 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
Paulo Zanoni | 851855d | 2013-12-19 19:12:29 -0200 | [diff] [blame] | 1816 | intel_wait_for_vblank(dev_priv->dev, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1817 | } |
| 1818 | |
| 1819 | /** |
Chris Wilson | 309cfea | 2011-01-28 13:54:53 +0000 | [diff] [blame] | 1820 | * intel_disable_pipe - disable a pipe, asserting requirements |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1821 | * @dev_priv: i915 private structure |
| 1822 | * @pipe: pipe to disable |
| 1823 | * |
| 1824 | * Disable @pipe, making sure that various hardware specific requirements |
| 1825 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. |
| 1826 | * |
| 1827 | * @pipe should be %PIPE_A or %PIPE_B. |
| 1828 | * |
| 1829 | * Will wait until the pipe has shut down before returning. |
| 1830 | */ |
| 1831 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, |
| 1832 | enum pipe pipe) |
| 1833 | { |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1834 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
| 1835 | pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1836 | int reg; |
| 1837 | u32 val; |
| 1838 | |
| 1839 | /* |
| 1840 | * Make sure planes won't keep trying to pump pixels to us, |
| 1841 | * or we might hang the display. |
| 1842 | */ |
| 1843 | assert_planes_disabled(dev_priv, pipe); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 1844 | assert_cursor_disabled(dev_priv, pipe); |
Jesse Barnes | 19332d7 | 2013-03-28 09:55:38 -0700 | [diff] [blame] | 1845 | assert_sprites_disabled(dev_priv, pipe); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1846 | |
| 1847 | /* Don't disable pipe A or pipe A PLLs if needed */ |
| 1848 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
| 1849 | return; |
| 1850 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 1851 | reg = PIPECONF(cpu_transcoder); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1852 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1853 | if ((val & PIPECONF_ENABLE) == 0) |
| 1854 | return; |
| 1855 | |
| 1856 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1857 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
| 1858 | } |
| 1859 | |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1860 | /* |
| 1861 | * Plane regs are double buffered, going from enabled->disabled needs a |
| 1862 | * trigger in order to latch. The display address reg provides this. |
| 1863 | */ |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1864 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
| 1865 | enum plane plane) |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1866 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 1867 | struct drm_device *dev = dev_priv->dev; |
| 1868 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1869 | |
| 1870 | I915_WRITE(reg, I915_READ(reg)); |
| 1871 | POSTING_READ(reg); |
Keith Packard | d74362c | 2011-07-28 14:47:14 -0700 | [diff] [blame] | 1872 | } |
| 1873 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1874 | /** |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 1875 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1876 | * @dev_priv: i915 private structure |
| 1877 | * @plane: plane to enable |
| 1878 | * @pipe: pipe being fed |
| 1879 | * |
| 1880 | * Enable @plane on @pipe, making sure that @pipe is running first. |
| 1881 | */ |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 1882 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
| 1883 | enum plane plane, enum pipe pipe) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1884 | { |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 1885 | struct intel_crtc *intel_crtc = |
| 1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1887 | int reg; |
| 1888 | u32 val; |
| 1889 | |
| 1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ |
| 1891 | assert_pipe_enabled(dev_priv, pipe); |
| 1892 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
Ville Syrjälä | 0037f71 | 2013-10-01 18:02:20 +0300 | [diff] [blame] | 1894 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 1895 | intel_crtc->primary_enabled = true; |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 1896 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1897 | reg = DSPCNTR(plane); |
| 1898 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1899 | if (val & DISPLAY_PLANE_ENABLE) |
| 1900 | return; |
| 1901 | |
| 1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1903 | intel_flush_primary_plane(dev_priv, plane); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1905 | } |
| 1906 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1907 | /** |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 1908 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1909 | * @dev_priv: i915 private structure |
| 1910 | * @plane: plane to disable |
| 1911 | * @pipe: pipe consuming the data |
| 1912 | * |
| 1913 | * Disable @plane; should be an independent operation. |
| 1914 | */ |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 1915 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
| 1916 | enum plane plane, enum pipe pipe) |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1917 | { |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 1918 | struct intel_crtc *intel_crtc = |
| 1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1920 | int reg; |
| 1921 | u32 val; |
| 1922 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
Ville Syrjälä | 0037f71 | 2013-10-01 18:02:20 +0300 | [diff] [blame] | 1924 | |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 1925 | intel_crtc->primary_enabled = false; |
Ville Syrjälä | 939c2fe | 2013-10-01 18:02:10 +0300 | [diff] [blame] | 1926 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1927 | reg = DSPCNTR(plane); |
| 1928 | val = I915_READ(reg); |
Chris Wilson | 00d70b1 | 2011-03-17 07:18:29 +0000 | [diff] [blame] | 1929 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
| 1930 | return; |
| 1931 | |
| 1932 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 1933 | intel_flush_primary_plane(dev_priv, plane); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 1934 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 1935 | } |
| 1936 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 1937 | static bool need_vtd_wa(struct drm_device *dev) |
| 1938 | { |
| 1939 | #ifdef CONFIG_INTEL_IOMMU |
| 1940 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) |
| 1941 | return true; |
| 1942 | #endif |
| 1943 | return false; |
| 1944 | } |
| 1945 | |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 1946 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
| 1947 | { |
| 1948 | int tile_height; |
| 1949 | |
| 1950 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; |
| 1951 | return ALIGN(height, tile_height); |
| 1952 | } |
| 1953 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 1954 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1955 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1956 | struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 1957 | struct intel_ring_buffer *pipelined) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1958 | { |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1960 | u32 alignment; |
| 1961 | int ret; |
| 1962 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1963 | switch (obj->tiling_mode) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1964 | case I915_TILING_NONE: |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1965 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
| 1966 | alignment = 128 * 1024; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1967 | else if (INTEL_INFO(dev)->gen >= 4) |
Chris Wilson | 534843d | 2010-07-05 18:01:46 +0100 | [diff] [blame] | 1968 | alignment = 4 * 1024; |
| 1969 | else |
| 1970 | alignment = 64 * 1024; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1971 | break; |
| 1972 | case I915_TILING_X: |
| 1973 | /* pin() will align the object as required by fence */ |
| 1974 | alignment = 0; |
| 1975 | break; |
| 1976 | case I915_TILING_Y: |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 1977 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1978 | return -EINVAL; |
| 1979 | default: |
| 1980 | BUG(); |
| 1981 | } |
| 1982 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 1983 | /* Note that the w/a also requires 64 PTE of padding following the |
| 1984 | * bo. We currently fill all unused PTE with the shadow page and so |
| 1985 | * we should always have valid PTE following the scanout preventing |
| 1986 | * the VT-d warning. |
| 1987 | */ |
| 1988 | if (need_vtd_wa(dev) && alignment < 256 * 1024) |
| 1989 | alignment = 256 * 1024; |
| 1990 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1991 | dev_priv->mm.interruptible = false; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 1992 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 1993 | if (ret) |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1994 | goto err_interruptible; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1995 | |
| 1996 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
| 1997 | * fence, whereas 965+ only requires a fence if using |
| 1998 | * framebuffer compression. For simplicity, we always install |
| 1999 | * a fence as the cost is not that onerous. |
| 2000 | */ |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2001 | ret = i915_gem_object_get_fence(obj); |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2002 | if (ret) |
| 2003 | goto err_unpin; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2004 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2005 | i915_gem_object_pin_fence(obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2006 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2007 | dev_priv->mm.interruptible = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2008 | return 0; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2009 | |
| 2010 | err_unpin: |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2011 | i915_gem_object_unpin_from_display_plane(obj); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 2012 | err_interruptible: |
| 2013 | dev_priv->mm.interruptible = true; |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2014 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2015 | } |
| 2016 | |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2017 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
| 2018 | { |
| 2019 | i915_gem_object_unpin_fence(obj); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2020 | i915_gem_object_unpin_from_display_plane(obj); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2021 | } |
| 2022 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2023 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
| 2024 | * is assumed to be a power-of-two. */ |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2025 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
| 2026 | unsigned int tiling_mode, |
| 2027 | unsigned int cpp, |
| 2028 | unsigned int pitch) |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2029 | { |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2030 | if (tiling_mode != I915_TILING_NONE) { |
| 2031 | unsigned int tile_rows, tiles; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2032 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2033 | tile_rows = *y / 8; |
| 2034 | *y %= 8; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2035 | |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2036 | tiles = *x / (512/cpp); |
| 2037 | *x %= 512/cpp; |
| 2038 | |
| 2039 | return tile_rows * pitch * 8 + tiles * 4096; |
| 2040 | } else { |
| 2041 | unsigned int offset; |
| 2042 | |
| 2043 | offset = *y * pitch + *x * cpp; |
| 2044 | *y = 0; |
| 2045 | *x = (offset & 4095) / cpp; |
| 2046 | return offset & -4096; |
| 2047 | } |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2048 | } |
| 2049 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2050 | int intel_format_to_fourcc(int format) |
| 2051 | { |
| 2052 | switch (format) { |
| 2053 | case DISPPLANE_8BPP: |
| 2054 | return DRM_FORMAT_C8; |
| 2055 | case DISPPLANE_BGRX555: |
| 2056 | return DRM_FORMAT_XRGB1555; |
| 2057 | case DISPPLANE_BGRX565: |
| 2058 | return DRM_FORMAT_RGB565; |
| 2059 | default: |
| 2060 | case DISPPLANE_BGRX888: |
| 2061 | return DRM_FORMAT_XRGB8888; |
| 2062 | case DISPPLANE_RGBX888: |
| 2063 | return DRM_FORMAT_XBGR8888; |
| 2064 | case DISPPLANE_BGRX101010: |
| 2065 | return DRM_FORMAT_XRGB2101010; |
| 2066 | case DISPPLANE_RGBX101010: |
| 2067 | return DRM_FORMAT_XBGR2101010; |
| 2068 | } |
| 2069 | } |
| 2070 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2071 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2072 | struct intel_plane_config *plane_config) |
| 2073 | { |
| 2074 | struct drm_device *dev = crtc->base.dev; |
| 2075 | struct drm_i915_gem_object *obj = NULL; |
| 2076 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
| 2077 | u32 base = plane_config->base; |
| 2078 | |
Chris Wilson | ff2652e | 2014-03-10 08:07:02 +0000 | [diff] [blame] | 2079 | if (plane_config->size == 0) |
| 2080 | return false; |
| 2081 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2082 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
| 2083 | plane_config->size); |
| 2084 | if (!obj) |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2085 | return false; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2086 | |
| 2087 | if (plane_config->tiled) { |
| 2088 | obj->tiling_mode = I915_TILING_X; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2089 | obj->stride = crtc->base.fb->pitches[0]; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2090 | } |
| 2091 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2092 | mode_cmd.pixel_format = crtc->base.fb->pixel_format; |
| 2093 | mode_cmd.width = crtc->base.fb->width; |
| 2094 | mode_cmd.height = crtc->base.fb->height; |
| 2095 | mode_cmd.pitches[0] = crtc->base.fb->pitches[0]; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2096 | |
| 2097 | mutex_lock(&dev->struct_mutex); |
| 2098 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2099 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.fb), |
| 2100 | &mode_cmd, obj)) { |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2101 | DRM_DEBUG_KMS("intel fb init failed\n"); |
| 2102 | goto out_unref_obj; |
| 2103 | } |
| 2104 | |
| 2105 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2106 | |
| 2107 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); |
| 2108 | return true; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2109 | |
| 2110 | out_unref_obj: |
| 2111 | drm_gem_object_unreference(&obj->base); |
| 2112 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2113 | return false; |
| 2114 | } |
| 2115 | |
| 2116 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, |
| 2117 | struct intel_plane_config *plane_config) |
| 2118 | { |
| 2119 | struct drm_device *dev = intel_crtc->base.dev; |
| 2120 | struct drm_crtc *c; |
| 2121 | struct intel_crtc *i; |
| 2122 | struct intel_framebuffer *fb; |
| 2123 | |
| 2124 | if (!intel_crtc->base.fb) |
| 2125 | return; |
| 2126 | |
| 2127 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) |
| 2128 | return; |
| 2129 | |
| 2130 | kfree(intel_crtc->base.fb); |
Chris Wilson | d1a5986 | 2014-03-10 08:07:01 +0000 | [diff] [blame] | 2131 | intel_crtc->base.fb = NULL; |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 2132 | |
| 2133 | /* |
| 2134 | * Failed to alloc the obj, check to see if we should share |
| 2135 | * an fb with another CRTC instead |
| 2136 | */ |
| 2137 | list_for_each_entry(c, &dev->mode_config.crtc_list, head) { |
| 2138 | i = to_intel_crtc(c); |
| 2139 | |
| 2140 | if (c == &intel_crtc->base) |
| 2141 | continue; |
| 2142 | |
| 2143 | if (!i->active || !c->fb) |
| 2144 | continue; |
| 2145 | |
| 2146 | fb = to_intel_framebuffer(c->fb); |
| 2147 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
| 2148 | drm_framebuffer_reference(c->fb); |
| 2149 | intel_crtc->base.fb = c->fb; |
| 2150 | break; |
| 2151 | } |
| 2152 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 2153 | } |
| 2154 | |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2155 | static int i9xx_update_primary_plane(struct drm_crtc *crtc, |
| 2156 | struct drm_framebuffer *fb, |
| 2157 | int x, int y) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2158 | { |
| 2159 | struct drm_device *dev = crtc->dev; |
| 2160 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2161 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2162 | struct intel_framebuffer *intel_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2163 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2164 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2165 | unsigned long linear_offset; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2166 | u32 dspcntr; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2167 | u32 reg; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2168 | |
| 2169 | switch (plane) { |
| 2170 | case 0: |
| 2171 | case 1: |
| 2172 | break; |
| 2173 | default: |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2174 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2175 | return -EINVAL; |
| 2176 | } |
| 2177 | |
| 2178 | intel_fb = to_intel_framebuffer(fb); |
| 2179 | obj = intel_fb->obj; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2180 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2181 | reg = DSPCNTR(plane); |
| 2182 | dspcntr = I915_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2183 | /* Mask out pixel format bits in case we change it */ |
| 2184 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2185 | switch (fb->pixel_format) { |
| 2186 | case DRM_FORMAT_C8: |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2187 | dspcntr |= DISPPLANE_8BPP; |
| 2188 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2189 | case DRM_FORMAT_XRGB1555: |
| 2190 | case DRM_FORMAT_ARGB1555: |
| 2191 | dspcntr |= DISPPLANE_BGRX555; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2192 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2193 | case DRM_FORMAT_RGB565: |
| 2194 | dspcntr |= DISPPLANE_BGRX565; |
| 2195 | break; |
| 2196 | case DRM_FORMAT_XRGB8888: |
| 2197 | case DRM_FORMAT_ARGB8888: |
| 2198 | dspcntr |= DISPPLANE_BGRX888; |
| 2199 | break; |
| 2200 | case DRM_FORMAT_XBGR8888: |
| 2201 | case DRM_FORMAT_ABGR8888: |
| 2202 | dspcntr |= DISPPLANE_RGBX888; |
| 2203 | break; |
| 2204 | case DRM_FORMAT_XRGB2101010: |
| 2205 | case DRM_FORMAT_ARGB2101010: |
| 2206 | dspcntr |= DISPPLANE_BGRX101010; |
| 2207 | break; |
| 2208 | case DRM_FORMAT_XBGR2101010: |
| 2209 | case DRM_FORMAT_ABGR2101010: |
| 2210 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2211 | break; |
| 2212 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2213 | BUG(); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2214 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2215 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2216 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2217 | if (obj->tiling_mode != I915_TILING_NONE) |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2218 | dspcntr |= DISPPLANE_TILED; |
| 2219 | else |
| 2220 | dspcntr &= ~DISPPLANE_TILED; |
| 2221 | } |
| 2222 | |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 2223 | if (IS_G4X(dev)) |
| 2224 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2225 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2226 | I915_WRITE(reg, dspcntr); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2227 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2228 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2229 | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2230 | if (INTEL_INFO(dev)->gen >= 4) { |
| 2231 | intel_crtc->dspaddr_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2232 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 2233 | fb->bits_per_pixel / 8, |
| 2234 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2235 | linear_offset -= intel_crtc->dspaddr_offset; |
| 2236 | } else { |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2237 | intel_crtc->dspaddr_offset = linear_offset; |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2238 | } |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2239 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2240 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 2241 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
| 2242 | fb->pitches[0]); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2243 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 2244 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2245 | I915_WRITE(DSPSURF(plane), |
| 2246 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2247 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2248 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2249 | } else |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2250 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2251 | POSTING_READ(reg); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2252 | |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2253 | return 0; |
| 2254 | } |
| 2255 | |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2256 | static int ironlake_update_primary_plane(struct drm_crtc *crtc, |
| 2257 | struct drm_framebuffer *fb, |
| 2258 | int x, int y) |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2259 | { |
| 2260 | struct drm_device *dev = crtc->dev; |
| 2261 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2263 | struct intel_framebuffer *intel_fb; |
| 2264 | struct drm_i915_gem_object *obj; |
| 2265 | int plane = intel_crtc->plane; |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2266 | unsigned long linear_offset; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2267 | u32 dspcntr; |
| 2268 | u32 reg; |
| 2269 | |
| 2270 | switch (plane) { |
| 2271 | case 0: |
| 2272 | case 1: |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2273 | case 2: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2274 | break; |
| 2275 | default: |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2276 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2277 | return -EINVAL; |
| 2278 | } |
| 2279 | |
| 2280 | intel_fb = to_intel_framebuffer(fb); |
| 2281 | obj = intel_fb->obj; |
| 2282 | |
| 2283 | reg = DSPCNTR(plane); |
| 2284 | dspcntr = I915_READ(reg); |
| 2285 | /* Mask out pixel format bits in case we change it */ |
| 2286 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2287 | switch (fb->pixel_format) { |
| 2288 | case DRM_FORMAT_C8: |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2289 | dspcntr |= DISPPLANE_8BPP; |
| 2290 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2291 | case DRM_FORMAT_RGB565: |
| 2292 | dspcntr |= DISPPLANE_BGRX565; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2293 | break; |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 2294 | case DRM_FORMAT_XRGB8888: |
| 2295 | case DRM_FORMAT_ARGB8888: |
| 2296 | dspcntr |= DISPPLANE_BGRX888; |
| 2297 | break; |
| 2298 | case DRM_FORMAT_XBGR8888: |
| 2299 | case DRM_FORMAT_ABGR8888: |
| 2300 | dspcntr |= DISPPLANE_RGBX888; |
| 2301 | break; |
| 2302 | case DRM_FORMAT_XRGB2101010: |
| 2303 | case DRM_FORMAT_ARGB2101010: |
| 2304 | dspcntr |= DISPPLANE_BGRX101010; |
| 2305 | break; |
| 2306 | case DRM_FORMAT_XBGR2101010: |
| 2307 | case DRM_FORMAT_ABGR2101010: |
| 2308 | dspcntr |= DISPPLANE_RGBX101010; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2309 | break; |
| 2310 | default: |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 2311 | BUG(); |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2312 | } |
| 2313 | |
| 2314 | if (obj->tiling_mode != I915_TILING_NONE) |
| 2315 | dspcntr |= DISPPLANE_TILED; |
| 2316 | else |
| 2317 | dspcntr &= ~DISPPLANE_TILED; |
| 2318 | |
Ville Syrjälä | b42c600 | 2013-11-03 13:47:27 +0200 | [diff] [blame] | 2319 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 2320 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
| 2321 | else |
| 2322 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2323 | |
| 2324 | I915_WRITE(reg, dspcntr); |
| 2325 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 2326 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2327 | intel_crtc->dspaddr_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 2328 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 2329 | fb->bits_per_pixel / 8, |
| 2330 | fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 2331 | linear_offset -= intel_crtc->dspaddr_offset; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2332 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 2333 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
| 2334 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, |
| 2335 | fb->pitches[0]); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 2336 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 2337 | I915_WRITE(DSPSURF(plane), |
| 2338 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 2339 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Damien Lespiau | bc1c91e | 2012-10-29 12:14:21 +0000 | [diff] [blame] | 2340 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
| 2341 | } else { |
| 2342 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
| 2343 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
| 2344 | } |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2345 | POSTING_READ(reg); |
| 2346 | |
| 2347 | return 0; |
| 2348 | } |
| 2349 | |
| 2350 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
| 2351 | static int |
| 2352 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
| 2353 | int x, int y, enum mode_set_atomic state) |
| 2354 | { |
| 2355 | struct drm_device *dev = crtc->dev; |
| 2356 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 17638cd | 2011-06-24 12:19:23 -0700 | [diff] [blame] | 2357 | |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2358 | if (dev_priv->display.disable_fbc) |
| 2359 | dev_priv->display.disable_fbc(dev); |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 2360 | intel_increase_pllclock(crtc); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2361 | |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2362 | return dev_priv->display.update_primary_plane(crtc, fb, x, y); |
Jesse Barnes | 8125556 | 2010-08-02 12:07:50 -0700 | [diff] [blame] | 2363 | } |
| 2364 | |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2365 | void intel_display_handle_reset(struct drm_device *dev) |
| 2366 | { |
| 2367 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2368 | struct drm_crtc *crtc; |
| 2369 | |
| 2370 | /* |
| 2371 | * Flips in the rings have been nuked by the reset, |
| 2372 | * so complete all pending flips so that user space |
| 2373 | * will get its events and not get stuck. |
| 2374 | * |
| 2375 | * Also update the base address of all primary |
| 2376 | * planes to the the last fb to make sure we're |
| 2377 | * showing the correct fb after a reset. |
| 2378 | * |
| 2379 | * Need to make two loops over the crtcs so that we |
| 2380 | * don't try to grab a crtc mutex before the |
| 2381 | * pending_flip_queue really got woken up. |
| 2382 | */ |
| 2383 | |
| 2384 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 2385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2386 | enum plane plane = intel_crtc->plane; |
| 2387 | |
| 2388 | intel_prepare_page_flip(dev, plane); |
| 2389 | intel_finish_page_flip_plane(dev, plane); |
| 2390 | } |
| 2391 | |
| 2392 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 2393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2394 | |
| 2395 | mutex_lock(&crtc->mutex); |
Chris Wilson | 947fdaadf | 2013-11-27 12:01:32 +0000 | [diff] [blame] | 2396 | /* |
| 2397 | * FIXME: Once we have proper support for primary planes (and |
| 2398 | * disabling them without disabling the entire crtc) allow again |
| 2399 | * a NULL crtc->fb. |
| 2400 | */ |
| 2401 | if (intel_crtc->active && crtc->fb) |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2402 | dev_priv->display.update_primary_plane(crtc, |
| 2403 | crtc->fb, |
| 2404 | crtc->x, |
| 2405 | crtc->y); |
Ville Syrjälä | 96a0291 | 2013-02-18 19:08:49 +0200 | [diff] [blame] | 2406 | mutex_unlock(&crtc->mutex); |
| 2407 | } |
| 2408 | } |
| 2409 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2410 | static int |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2411 | intel_finish_fb(struct drm_framebuffer *old_fb) |
| 2412 | { |
| 2413 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
| 2414 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2415 | bool was_interruptible = dev_priv->mm.interruptible; |
| 2416 | int ret; |
| 2417 | |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2418 | /* Big Hammer, we also need to ensure that any pending |
| 2419 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 2420 | * current scanout is retired before unpinning the old |
| 2421 | * framebuffer. |
| 2422 | * |
| 2423 | * This should only fail upon a hung GPU, in which case we |
| 2424 | * can safely continue. |
| 2425 | */ |
| 2426 | dev_priv->mm.interruptible = false; |
| 2427 | ret = i915_gem_object_finish_gpu(obj); |
| 2428 | dev_priv->mm.interruptible = was_interruptible; |
| 2429 | |
| 2430 | return ret; |
| 2431 | } |
| 2432 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 2433 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
| 2434 | { |
| 2435 | struct drm_device *dev = crtc->dev; |
| 2436 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2438 | unsigned long flags; |
| 2439 | bool pending; |
| 2440 | |
| 2441 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
| 2442 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) |
| 2443 | return false; |
| 2444 | |
| 2445 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2446 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
| 2447 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2448 | |
| 2449 | return pending; |
| 2450 | } |
| 2451 | |
Chris Wilson | 14667a4 | 2012-04-03 17:58:35 +0100 | [diff] [blame] | 2452 | static int |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2453 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2454 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2455 | { |
| 2456 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2457 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2459 | struct drm_framebuffer *old_fb; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2460 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2461 | |
Chris Wilson | 7d5e379 | 2014-03-04 13:15:08 +0000 | [diff] [blame] | 2462 | if (intel_crtc_has_pending_flip(crtc)) { |
| 2463 | DRM_ERROR("pipe is still busy with an old pageflip\n"); |
| 2464 | return -EBUSY; |
| 2465 | } |
| 2466 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2467 | /* no fb bound */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2468 | if (!fb) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2469 | DRM_ERROR("No FB bound\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2470 | return 0; |
| 2471 | } |
| 2472 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 2473 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 2474 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
| 2475 | plane_name(intel_crtc->plane), |
| 2476 | INTEL_INFO(dev)->num_pipes); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2477 | return -EINVAL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2478 | } |
| 2479 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2480 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 265db95 | 2010-09-20 15:41:01 +0100 | [diff] [blame] | 2481 | ret = intel_pin_and_fence_fb_obj(dev, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2482 | to_intel_framebuffer(fb)->obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 2483 | NULL); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2484 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2485 | if (ret != 0) { |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2486 | DRM_ERROR("pin & fence failed\n"); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2487 | return ret; |
| 2488 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2489 | |
Damien Lespiau | bb2043d | 2013-09-30 14:21:49 +0100 | [diff] [blame] | 2490 | /* |
| 2491 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 2492 | * that in compute_mode_changes we check the native mode (not the pfit |
| 2493 | * mode) to see if we can flip rather than do a full mode set. In the |
| 2494 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 2495 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 2496 | * sized surface. |
| 2497 | * |
| 2498 | * To fix this properly, we need to hoist the checks up into |
| 2499 | * compute_mode_changes (or above), check the actual pfit state and |
| 2500 | * whether the platform allows pfit disable with pipe active, and only |
| 2501 | * then update the pipesrc and pfit state, even on the flip path. |
| 2502 | */ |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2503 | if (i915.fastboot) { |
Damien Lespiau | d7bf63f | 2013-09-30 14:21:50 +0100 | [diff] [blame] | 2504 | const struct drm_display_mode *adjusted_mode = |
| 2505 | &intel_crtc->config.adjusted_mode; |
| 2506 | |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2507 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
Damien Lespiau | d7bf63f | 2013-09-30 14:21:50 +0100 | [diff] [blame] | 2508 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
| 2509 | (adjusted_mode->crtc_vdisplay - 1)); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 2510 | if (!intel_crtc->config.pch_pfit.enabled && |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2511 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
| 2512 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
| 2513 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); |
| 2514 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); |
| 2515 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); |
| 2516 | } |
Jesse Barnes | 0637d60 | 2013-12-19 10:48:01 -0800 | [diff] [blame] | 2517 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
| 2518 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; |
Jesse Barnes | 4d6a3e6 | 2013-06-26 01:38:18 +0300 | [diff] [blame] | 2519 | } |
| 2520 | |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 2521 | ret = dev_priv->display.update_primary_plane(crtc, fb, x, y); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 2522 | if (ret) { |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2523 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2524 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2525 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | a5071c2 | 2011-07-19 15:38:56 -0700 | [diff] [blame] | 2526 | DRM_ERROR("failed to update base address\n"); |
Chris Wilson | 4e6cfef | 2010-08-08 13:20:19 +0100 | [diff] [blame] | 2527 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2528 | } |
Kristian Høgsberg | 3c4fdcf | 2008-12-17 22:14:46 -0500 | [diff] [blame] | 2529 | |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2530 | old_fb = crtc->fb; |
| 2531 | crtc->fb = fb; |
Daniel Vetter | 6c4c86f | 2012-09-10 21:58:30 +0200 | [diff] [blame] | 2532 | crtc->x = x; |
| 2533 | crtc->y = y; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 2534 | |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2535 | if (old_fb) { |
Daniel Vetter | d7697ee | 2013-06-02 17:23:01 +0200 | [diff] [blame] | 2536 | if (intel_crtc->active && old_fb != fb) |
| 2537 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2538 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2539 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2540 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | b7f1de2 | 2010-12-14 16:09:31 +0000 | [diff] [blame] | 2541 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2542 | |
Ville Syrjälä | 8ac36ec | 2014-03-11 19:37:33 +0200 | [diff] [blame] | 2543 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b8e6ed | 2012-04-17 15:08:19 +0100 | [diff] [blame] | 2544 | intel_update_fbc(dev); |
Rodrigo Vivi | 4906557 | 2013-07-11 18:45:05 -0300 | [diff] [blame] | 2545 | intel_edp_psr_update(dev); |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2546 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2547 | |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 2548 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2549 | } |
| 2550 | |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2551 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
| 2552 | { |
| 2553 | struct drm_device *dev = crtc->dev; |
| 2554 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2556 | int pipe = intel_crtc->pipe; |
| 2557 | u32 reg, temp; |
| 2558 | |
| 2559 | /* enable normal train */ |
| 2560 | reg = FDI_TX_CTL(pipe); |
| 2561 | temp = I915_READ(reg); |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2562 | if (IS_IVYBRIDGE(dev)) { |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2563 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2564 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; |
Keith Packard | 61e499b | 2011-05-17 16:13:52 -0700 | [diff] [blame] | 2565 | } else { |
| 2566 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2567 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2568 | } |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2569 | I915_WRITE(reg, temp); |
| 2570 | |
| 2571 | reg = FDI_RX_CTL(pipe); |
| 2572 | temp = I915_READ(reg); |
| 2573 | if (HAS_PCH_CPT(dev)) { |
| 2574 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2575 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; |
| 2576 | } else { |
| 2577 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2578 | temp |= FDI_LINK_TRAIN_NONE; |
| 2579 | } |
| 2580 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
| 2581 | |
| 2582 | /* wait one idle pattern time */ |
| 2583 | POSTING_READ(reg); |
| 2584 | udelay(1000); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2585 | |
| 2586 | /* IVB wants error correction enabled */ |
| 2587 | if (IS_IVYBRIDGE(dev)) |
| 2588 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
| 2589 | FDI_FE_ERRC_ENABLE); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 2590 | } |
| 2591 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 2592 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2593 | { |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 2594 | return crtc->base.enabled && crtc->active && |
| 2595 | crtc->config.has_pch_encoder; |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2596 | } |
| 2597 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 2598 | static void ivb_modeset_global_resources(struct drm_device *dev) |
| 2599 | { |
| 2600 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2601 | struct intel_crtc *pipe_B_crtc = |
| 2602 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
| 2603 | struct intel_crtc *pipe_C_crtc = |
| 2604 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); |
| 2605 | uint32_t temp; |
| 2606 | |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 2607 | /* |
| 2608 | * When everything is off disable fdi C so that we could enable fdi B |
| 2609 | * with all lanes. Note that we don't care about enabled pipes without |
| 2610 | * an enabled pch encoder. |
| 2611 | */ |
| 2612 | if (!pipe_has_enabled_pch(pipe_B_crtc) && |
| 2613 | !pipe_has_enabled_pch(pipe_C_crtc)) { |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 2614 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 2615 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 2616 | |
| 2617 | temp = I915_READ(SOUTH_CHICKEN1); |
| 2618 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
| 2619 | DRM_DEBUG_KMS("disabling fdi C rx\n"); |
| 2620 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 2621 | } |
| 2622 | } |
| 2623 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2624 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 2625 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) |
| 2626 | { |
| 2627 | struct drm_device *dev = crtc->dev; |
| 2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2630 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2631 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2632 | u32 reg, temp, tries; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2633 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 2634 | /* FDI needs bits from pipe & plane first */ |
| 2635 | assert_pipe_enabled(dev_priv, pipe); |
| 2636 | assert_plane_enabled(dev_priv, plane); |
| 2637 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2638 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2639 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2640 | reg = FDI_RX_IMR(pipe); |
| 2641 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2642 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2643 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2644 | I915_WRITE(reg, temp); |
| 2645 | I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2646 | udelay(150); |
| 2647 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2648 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2649 | reg = FDI_TX_CTL(pipe); |
| 2650 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 2651 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 2652 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2653 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2654 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2655 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2656 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2657 | reg = FDI_RX_CTL(pipe); |
| 2658 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2659 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2660 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2661 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2662 | |
| 2663 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2664 | udelay(150); |
| 2665 | |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2666 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
Daniel Vetter | 8f5718a | 2012-10-31 22:52:28 +0100 | [diff] [blame] | 2667 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
| 2668 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | |
| 2669 | FDI_RX_PHASE_SYNC_POINTER_EN); |
Jesse Barnes | 5b2adf8 | 2010-10-07 16:01:15 -0700 | [diff] [blame] | 2670 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2671 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2672 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2673 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2674 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2675 | |
| 2676 | if ((temp & FDI_RX_BIT_LOCK)) { |
| 2677 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2678 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2679 | break; |
| 2680 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2681 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2682 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2683 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2684 | |
| 2685 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2686 | reg = FDI_TX_CTL(pipe); |
| 2687 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2688 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2689 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2690 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2691 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2692 | reg = FDI_RX_CTL(pipe); |
| 2693 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2694 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2695 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2696 | I915_WRITE(reg, temp); |
| 2697 | |
| 2698 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2699 | udelay(150); |
| 2700 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2701 | reg = FDI_RX_IIR(pipe); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2702 | for (tries = 0; tries < 5; tries++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2703 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2704 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2705 | |
| 2706 | if (temp & FDI_RX_SYMBOL_LOCK) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2707 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2708 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2709 | break; |
| 2710 | } |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2711 | } |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2712 | if (tries == 5) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2713 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2714 | |
| 2715 | DRM_DEBUG_KMS("FDI train done\n"); |
Jesse Barnes | 5c5313c | 2010-10-07 16:01:11 -0700 | [diff] [blame] | 2716 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2717 | } |
| 2718 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2719 | static const int snb_b_fdi_train_param[] = { |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2720 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
| 2721 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, |
| 2722 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, |
| 2723 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, |
| 2724 | }; |
| 2725 | |
| 2726 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 2727 | static void gen6_fdi_link_train(struct drm_crtc *crtc) |
| 2728 | { |
| 2729 | struct drm_device *dev = crtc->dev; |
| 2730 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2732 | int pipe = intel_crtc->pipe; |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2733 | u32 reg, temp, i, retry; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2734 | |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2735 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2736 | for train result */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2737 | reg = FDI_RX_IMR(pipe); |
| 2738 | temp = I915_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2739 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2740 | temp &= ~FDI_RX_BIT_LOCK; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2741 | I915_WRITE(reg, temp); |
| 2742 | |
| 2743 | POSTING_READ(reg); |
Adam Jackson | e1a4474 | 2010-06-25 15:32:14 -0400 | [diff] [blame] | 2744 | udelay(150); |
| 2745 | |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2746 | /* enable CPU FDI TX and PCH FDI RX */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2747 | reg = FDI_TX_CTL(pipe); |
| 2748 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 2749 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 2750 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2751 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2752 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2753 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2754 | /* SNB-B */ |
| 2755 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2756 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2757 | |
Daniel Vetter | d74cf32 | 2012-10-26 10:58:13 +0200 | [diff] [blame] | 2758 | I915_WRITE(FDI_RX_MISC(pipe), |
| 2759 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 2760 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2761 | reg = FDI_RX_CTL(pipe); |
| 2762 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2763 | if (HAS_PCH_CPT(dev)) { |
| 2764 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2765 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2766 | } else { |
| 2767 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2768 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 2769 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2770 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2771 | |
| 2772 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2773 | udelay(150); |
| 2774 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2775 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2776 | reg = FDI_TX_CTL(pipe); |
| 2777 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2778 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2779 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2780 | I915_WRITE(reg, temp); |
| 2781 | |
| 2782 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2783 | udelay(500); |
| 2784 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2785 | for (retry = 0; retry < 5; retry++) { |
| 2786 | reg = FDI_RX_IIR(pipe); |
| 2787 | temp = I915_READ(reg); |
| 2788 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2789 | if (temp & FDI_RX_BIT_LOCK) { |
| 2790 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 2791 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
| 2792 | break; |
| 2793 | } |
| 2794 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2795 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2796 | if (retry < 5) |
| 2797 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2798 | } |
| 2799 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2800 | DRM_ERROR("FDI train 1 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2801 | |
| 2802 | /* Train 2 */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2803 | reg = FDI_TX_CTL(pipe); |
| 2804 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2805 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2806 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2807 | if (IS_GEN6(dev)) { |
| 2808 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2809 | /* SNB-B */ |
| 2810 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; |
| 2811 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2812 | I915_WRITE(reg, temp); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2813 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2814 | reg = FDI_RX_CTL(pipe); |
| 2815 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2816 | if (HAS_PCH_CPT(dev)) { |
| 2817 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2818 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
| 2819 | } else { |
| 2820 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 2821 | temp |= FDI_LINK_TRAIN_PATTERN_2; |
| 2822 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2823 | I915_WRITE(reg, temp); |
| 2824 | |
| 2825 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2826 | udelay(150); |
| 2827 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2828 | for (i = 0; i < 4; i++) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2829 | reg = FDI_TX_CTL(pipe); |
| 2830 | temp = I915_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2831 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
| 2832 | temp |= snb_b_fdi_train_param[i]; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2833 | I915_WRITE(reg, temp); |
| 2834 | |
| 2835 | POSTING_READ(reg); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2836 | udelay(500); |
| 2837 | |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2838 | for (retry = 0; retry < 5; retry++) { |
| 2839 | reg = FDI_RX_IIR(pipe); |
| 2840 | temp = I915_READ(reg); |
| 2841 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2842 | if (temp & FDI_RX_SYMBOL_LOCK) { |
| 2843 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 2844 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
| 2845 | break; |
| 2846 | } |
| 2847 | udelay(50); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2848 | } |
Sean Paul | fa37d39 | 2012-03-02 12:53:39 -0500 | [diff] [blame] | 2849 | if (retry < 5) |
| 2850 | break; |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2851 | } |
| 2852 | if (i == 4) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2853 | DRM_ERROR("FDI train 2 fail!\n"); |
Zhenyu Wang | 8db9d77 | 2010-04-07 16:15:54 +0800 | [diff] [blame] | 2854 | |
| 2855 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2856 | } |
| 2857 | |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2858 | /* Manual link training for Ivy Bridge A0 parts */ |
| 2859 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) |
| 2860 | { |
| 2861 | struct drm_device *dev = crtc->dev; |
| 2862 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2863 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2864 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2865 | u32 reg, temp, i, j; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2866 | |
| 2867 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 2868 | for train result */ |
| 2869 | reg = FDI_RX_IMR(pipe); |
| 2870 | temp = I915_READ(reg); |
| 2871 | temp &= ~FDI_RX_SYMBOL_LOCK; |
| 2872 | temp &= ~FDI_RX_BIT_LOCK; |
| 2873 | I915_WRITE(reg, temp); |
| 2874 | |
| 2875 | POSTING_READ(reg); |
| 2876 | udelay(150); |
| 2877 | |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 2878 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
| 2879 | I915_READ(FDI_RX_IIR(pipe))); |
| 2880 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2881 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 2882 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { |
| 2883 | /* disable first in case we need to retry */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2884 | reg = FDI_TX_CTL(pipe); |
| 2885 | temp = I915_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2886 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
| 2887 | temp &= ~FDI_TX_ENABLE; |
| 2888 | I915_WRITE(reg, temp); |
| 2889 | |
| 2890 | reg = FDI_RX_CTL(pipe); |
| 2891 | temp = I915_READ(reg); |
| 2892 | temp &= ~FDI_LINK_TRAIN_AUTO; |
| 2893 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2894 | temp &= ~FDI_RX_ENABLE; |
| 2895 | I915_WRITE(reg, temp); |
| 2896 | |
| 2897 | /* enable CPU FDI TX and PCH FDI RX */ |
| 2898 | reg = FDI_TX_CTL(pipe); |
| 2899 | temp = I915_READ(reg); |
| 2900 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
| 2901 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
| 2902 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2903 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2904 | temp |= snb_b_fdi_train_param[j/2]; |
| 2905 | temp |= FDI_COMPOSITE_SYNC; |
| 2906 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
| 2907 | |
| 2908 | I915_WRITE(FDI_RX_MISC(pipe), |
| 2909 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); |
| 2910 | |
| 2911 | reg = FDI_RX_CTL(pipe); |
| 2912 | temp = I915_READ(reg); |
| 2913 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 2914 | temp |= FDI_COMPOSITE_SYNC; |
| 2915 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
| 2916 | |
| 2917 | POSTING_READ(reg); |
| 2918 | udelay(1); /* should be 0.5us */ |
| 2919 | |
| 2920 | for (i = 0; i < 4; i++) { |
| 2921 | reg = FDI_RX_IIR(pipe); |
| 2922 | temp = I915_READ(reg); |
| 2923 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
| 2924 | |
| 2925 | if (temp & FDI_RX_BIT_LOCK || |
| 2926 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { |
| 2927 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
| 2928 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", |
| 2929 | i); |
| 2930 | break; |
| 2931 | } |
| 2932 | udelay(1); /* should be 0.5us */ |
| 2933 | } |
| 2934 | if (i == 4) { |
| 2935 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); |
| 2936 | continue; |
| 2937 | } |
| 2938 | |
| 2939 | /* Train 2 */ |
| 2940 | reg = FDI_TX_CTL(pipe); |
| 2941 | temp = I915_READ(reg); |
| 2942 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
| 2943 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; |
| 2944 | I915_WRITE(reg, temp); |
| 2945 | |
| 2946 | reg = FDI_RX_CTL(pipe); |
| 2947 | temp = I915_READ(reg); |
| 2948 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 2949 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2950 | I915_WRITE(reg, temp); |
| 2951 | |
| 2952 | POSTING_READ(reg); |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2953 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2954 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2955 | for (i = 0; i < 4; i++) { |
| 2956 | reg = FDI_RX_IIR(pipe); |
| 2957 | temp = I915_READ(reg); |
| 2958 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2959 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2960 | if (temp & FDI_RX_SYMBOL_LOCK || |
| 2961 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { |
| 2962 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
| 2963 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", |
| 2964 | i); |
| 2965 | goto train_done; |
| 2966 | } |
| 2967 | udelay(2); /* should be 1.5us */ |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2968 | } |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2969 | if (i == 4) |
| 2970 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2971 | } |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2972 | |
Jesse Barnes | 139ccd3 | 2013-08-19 11:04:55 -0700 | [diff] [blame] | 2973 | train_done: |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 2974 | DRM_DEBUG_KMS("FDI train done.\n"); |
| 2975 | } |
| 2976 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 2977 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2978 | { |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 2979 | struct drm_device *dev = intel_crtc->base.dev; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2980 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2981 | int pipe = intel_crtc->pipe; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2982 | u32 reg, temp; |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2983 | |
Jesse Barnes | c64e311 | 2010-09-10 11:27:03 -0700 | [diff] [blame] | 2984 | |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2985 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2986 | reg = FDI_RX_CTL(pipe); |
| 2987 | temp = I915_READ(reg); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 2988 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
| 2989 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 2990 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2991 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
| 2992 | |
| 2993 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 2994 | udelay(200); |
| 2995 | |
| 2996 | /* Switch from Rawclk to PCDclk */ |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 2997 | temp = I915_READ(reg); |
| 2998 | I915_WRITE(reg, temp | FDI_PCDCLK); |
| 2999 | |
| 3000 | POSTING_READ(reg); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3001 | udelay(200); |
| 3002 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3003 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 3004 | reg = FDI_TX_CTL(pipe); |
| 3005 | temp = I915_READ(reg); |
| 3006 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
| 3007 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3008 | |
Paulo Zanoni | 2074973 | 2012-11-23 15:30:38 -0200 | [diff] [blame] | 3009 | POSTING_READ(reg); |
| 3010 | udelay(100); |
Jesse Barnes | 0e23b99 | 2010-09-10 11:10:00 -0700 | [diff] [blame] | 3011 | } |
| 3012 | } |
| 3013 | |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3014 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 3015 | { |
| 3016 | struct drm_device *dev = intel_crtc->base.dev; |
| 3017 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3018 | int pipe = intel_crtc->pipe; |
| 3019 | u32 reg, temp; |
| 3020 | |
| 3021 | /* Switch from PCDclk to Rawclk */ |
| 3022 | reg = FDI_RX_CTL(pipe); |
| 3023 | temp = I915_READ(reg); |
| 3024 | I915_WRITE(reg, temp & ~FDI_PCDCLK); |
| 3025 | |
| 3026 | /* Disable CPU FDI TX PLL */ |
| 3027 | reg = FDI_TX_CTL(pipe); |
| 3028 | temp = I915_READ(reg); |
| 3029 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); |
| 3030 | |
| 3031 | POSTING_READ(reg); |
| 3032 | udelay(100); |
| 3033 | |
| 3034 | reg = FDI_RX_CTL(pipe); |
| 3035 | temp = I915_READ(reg); |
| 3036 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); |
| 3037 | |
| 3038 | /* Wait for the clocks to turn off. */ |
| 3039 | POSTING_READ(reg); |
| 3040 | udelay(100); |
| 3041 | } |
| 3042 | |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3043 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
| 3044 | { |
| 3045 | struct drm_device *dev = crtc->dev; |
| 3046 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3048 | int pipe = intel_crtc->pipe; |
| 3049 | u32 reg, temp; |
| 3050 | |
| 3051 | /* disable CPU FDI tx and PCH FDI rx */ |
| 3052 | reg = FDI_TX_CTL(pipe); |
| 3053 | temp = I915_READ(reg); |
| 3054 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); |
| 3055 | POSTING_READ(reg); |
| 3056 | |
| 3057 | reg = FDI_RX_CTL(pipe); |
| 3058 | temp = I915_READ(reg); |
| 3059 | temp &= ~(0x7 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3060 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3061 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
| 3062 | |
| 3063 | POSTING_READ(reg); |
| 3064 | udelay(100); |
| 3065 | |
| 3066 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 3067 | if (HAS_PCH_IBX(dev)) { |
| 3068 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
Jesse Barnes | 6f06ce1 | 2011-01-04 15:09:38 -0800 | [diff] [blame] | 3069 | } |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3070 | |
| 3071 | /* still set train pattern 1 */ |
| 3072 | reg = FDI_TX_CTL(pipe); |
| 3073 | temp = I915_READ(reg); |
| 3074 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3075 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3076 | I915_WRITE(reg, temp); |
| 3077 | |
| 3078 | reg = FDI_RX_CTL(pipe); |
| 3079 | temp = I915_READ(reg); |
| 3080 | if (HAS_PCH_CPT(dev)) { |
| 3081 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
| 3082 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
| 3083 | } else { |
| 3084 | temp &= ~FDI_LINK_TRAIN_NONE; |
| 3085 | temp |= FDI_LINK_TRAIN_PATTERN_1; |
| 3086 | } |
| 3087 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 3088 | temp &= ~(0x07 << 16); |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3089 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
Jesse Barnes | 0fc932b | 2011-01-04 15:09:37 -0800 | [diff] [blame] | 3090 | I915_WRITE(reg, temp); |
| 3091 | |
| 3092 | POSTING_READ(reg); |
| 3093 | udelay(100); |
| 3094 | } |
| 3095 | |
Chris Wilson | 5dce5b93 | 2014-01-20 10:17:36 +0000 | [diff] [blame] | 3096 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
| 3097 | { |
| 3098 | struct intel_crtc *crtc; |
| 3099 | |
| 3100 | /* Note that we don't need to be called with mode_config.lock here |
| 3101 | * as our list of CRTC objects is static for the lifetime of the |
| 3102 | * device and so cannot disappear as we iterate. Similarly, we can |
| 3103 | * happily treat the predicates as racy, atomic checks as userspace |
| 3104 | * cannot claim and pin a new fb without at least acquring the |
| 3105 | * struct_mutex and so serialising with us. |
| 3106 | */ |
| 3107 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 3108 | if (atomic_read(&crtc->unpin_work_count) == 0) |
| 3109 | continue; |
| 3110 | |
| 3111 | if (crtc->unpin_work) |
| 3112 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3113 | |
| 3114 | return true; |
| 3115 | } |
| 3116 | |
| 3117 | return false; |
| 3118 | } |
| 3119 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3120 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
| 3121 | { |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 3122 | struct drm_device *dev = crtc->dev; |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3123 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3124 | |
| 3125 | if (crtc->fb == NULL) |
| 3126 | return; |
| 3127 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 3128 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
| 3129 | |
Chris Wilson | 5bb6164 | 2012-09-27 21:25:58 +0100 | [diff] [blame] | 3130 | wait_event(dev_priv->pending_flip_queue, |
| 3131 | !intel_crtc_has_pending_flip(crtc)); |
| 3132 | |
Chris Wilson | 0f91128 | 2012-04-17 10:05:38 +0100 | [diff] [blame] | 3133 | mutex_lock(&dev->struct_mutex); |
| 3134 | intel_finish_fb(crtc->fb); |
| 3135 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3136 | } |
| 3137 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3138 | /* Program iCLKIP clock to the desired frequency */ |
| 3139 | static void lpt_program_iclkip(struct drm_crtc *crtc) |
| 3140 | { |
| 3141 | struct drm_device *dev = crtc->dev; |
| 3142 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 3143 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3144 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 3145 | u32 temp; |
| 3146 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 3147 | mutex_lock(&dev_priv->dpio_lock); |
| 3148 | |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3149 | /* It is necessary to ungate the pixclk gate prior to programming |
| 3150 | * the divisors, and gate it back when it is done. |
| 3151 | */ |
| 3152 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); |
| 3153 | |
| 3154 | /* Disable SSCCTL */ |
| 3155 | intel_sbi_write(dev_priv, SBI_SSCCTL6, |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3156 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
| 3157 | SBI_SSCCTL_DISABLE, |
| 3158 | SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3159 | |
| 3160 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3161 | if (clock == 20000) { |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3162 | auxdiv = 1; |
| 3163 | divsel = 0x41; |
| 3164 | phaseinc = 0x20; |
| 3165 | } else { |
| 3166 | /* The iCLK virtual clock root frequency is in MHz, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 3167 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 3168 | * divisors, it is necessary to divide one by another, so we |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3169 | * convert the virtual clock precision to KHz here for higher |
| 3170 | * precision. |
| 3171 | */ |
| 3172 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 3173 | u32 iclk_pi_range = 64; |
| 3174 | u32 desired_divisor, msb_divisor_value, pi_value; |
| 3175 | |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3176 | desired_divisor = (iclk_virtual_root_freq / clock); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3177 | msb_divisor_value = desired_divisor / iclk_pi_range; |
| 3178 | pi_value = desired_divisor % iclk_pi_range; |
| 3179 | |
| 3180 | auxdiv = 0; |
| 3181 | divsel = msb_divisor_value - 2; |
| 3182 | phaseinc = pi_value; |
| 3183 | } |
| 3184 | |
| 3185 | /* This should not happen with any sane values */ |
| 3186 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & |
| 3187 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); |
| 3188 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & |
| 3189 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); |
| 3190 | |
| 3191 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", |
Ville Syrjälä | 12d7cee | 2013-09-04 18:25:19 +0300 | [diff] [blame] | 3192 | clock, |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3193 | auxdiv, |
| 3194 | divsel, |
| 3195 | phasedir, |
| 3196 | phaseinc); |
| 3197 | |
| 3198 | /* Program SSCDIVINTPHASE6 */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3199 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3200 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
| 3201 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); |
| 3202 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; |
| 3203 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); |
| 3204 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); |
| 3205 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3206 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3207 | |
| 3208 | /* Program SSCAUXDIV */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3209 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3210 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
| 3211 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3212 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3213 | |
| 3214 | /* Enable modulator and associated divider */ |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3215 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3216 | temp &= ~SBI_SSCCTL_DISABLE; |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 3217 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3218 | |
| 3219 | /* Wait for initialization time */ |
| 3220 | udelay(24); |
| 3221 | |
| 3222 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 3223 | |
| 3224 | mutex_unlock(&dev_priv->dpio_lock); |
Eugeni Dodonov | e615efe | 2012-05-09 15:37:26 -0300 | [diff] [blame] | 3225 | } |
| 3226 | |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3227 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
| 3228 | enum pipe pch_transcoder) |
| 3229 | { |
| 3230 | struct drm_device *dev = crtc->base.dev; |
| 3231 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3232 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
| 3233 | |
| 3234 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), |
| 3235 | I915_READ(HTOTAL(cpu_transcoder))); |
| 3236 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), |
| 3237 | I915_READ(HBLANK(cpu_transcoder))); |
| 3238 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), |
| 3239 | I915_READ(HSYNC(cpu_transcoder))); |
| 3240 | |
| 3241 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), |
| 3242 | I915_READ(VTOTAL(cpu_transcoder))); |
| 3243 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), |
| 3244 | I915_READ(VBLANK(cpu_transcoder))); |
| 3245 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), |
| 3246 | I915_READ(VSYNC(cpu_transcoder))); |
| 3247 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), |
| 3248 | I915_READ(VSYNCSHIFT(cpu_transcoder))); |
| 3249 | } |
| 3250 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 3251 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
| 3252 | { |
| 3253 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3254 | uint32_t temp; |
| 3255 | |
| 3256 | temp = I915_READ(SOUTH_CHICKEN1); |
| 3257 | if (temp & FDI_BC_BIFURCATION_SELECT) |
| 3258 | return; |
| 3259 | |
| 3260 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
| 3261 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); |
| 3262 | |
| 3263 | temp |= FDI_BC_BIFURCATION_SELECT; |
| 3264 | DRM_DEBUG_KMS("enabling fdi C rx\n"); |
| 3265 | I915_WRITE(SOUTH_CHICKEN1, temp); |
| 3266 | POSTING_READ(SOUTH_CHICKEN1); |
| 3267 | } |
| 3268 | |
| 3269 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
| 3270 | { |
| 3271 | struct drm_device *dev = intel_crtc->base.dev; |
| 3272 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3273 | |
| 3274 | switch (intel_crtc->pipe) { |
| 3275 | case PIPE_A: |
| 3276 | break; |
| 3277 | case PIPE_B: |
| 3278 | if (intel_crtc->config.fdi_lanes > 2) |
| 3279 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
| 3280 | else |
| 3281 | cpt_enable_fdi_bc_bifurcation(dev); |
| 3282 | |
| 3283 | break; |
| 3284 | case PIPE_C: |
| 3285 | cpt_enable_fdi_bc_bifurcation(dev); |
| 3286 | |
| 3287 | break; |
| 3288 | default: |
| 3289 | BUG(); |
| 3290 | } |
| 3291 | } |
| 3292 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3293 | /* |
| 3294 | * Enable PCH resources required for PCH ports: |
| 3295 | * - PCH PLLs |
| 3296 | * - FDI training & RX/TX |
| 3297 | * - update transcoder timings |
| 3298 | * - DP transcoding bits |
| 3299 | * - transcoder |
| 3300 | */ |
| 3301 | static void ironlake_pch_enable(struct drm_crtc *crtc) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3302 | { |
| 3303 | struct drm_device *dev = crtc->dev; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 3304 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3306 | int pipe = intel_crtc->pipe; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3307 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3308 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 3309 | assert_pch_transcoder_disabled(dev_priv, pipe); |
Chris Wilson | e7e164d | 2012-05-11 09:21:25 +0100 | [diff] [blame] | 3310 | |
Daniel Vetter | 1fbc0d7 | 2013-10-29 12:04:08 +0100 | [diff] [blame] | 3311 | if (IS_IVYBRIDGE(dev)) |
| 3312 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
| 3313 | |
Daniel Vetter | cd986ab | 2012-10-26 10:58:12 +0200 | [diff] [blame] | 3314 | /* Write the TU size bits before fdi link training, so that error |
| 3315 | * detection works. */ |
| 3316 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
| 3317 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); |
| 3318 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3319 | /* For PCH output, training FDI link */ |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 3320 | dev_priv->display.fdi_link_train(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3321 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 3322 | /* We need to program the right clock selection before writing the pixel |
| 3323 | * mutliplier into the DPLL. */ |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 3324 | if (HAS_PCH_CPT(dev)) { |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3325 | u32 sel; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 3326 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3327 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 3328 | temp |= TRANS_DPLL_ENABLE(pipe); |
| 3329 | sel = TRANS_DPLLB_SEL(pipe); |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3330 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3331 | temp |= sel; |
| 3332 | else |
| 3333 | temp &= ~sel; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3334 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3335 | } |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3336 | |
Daniel Vetter | 3ad8a20 | 2013-06-05 13:34:32 +0200 | [diff] [blame] | 3337 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 3338 | * transcoder, and we actually should do this to not upset any PCH |
| 3339 | * transcoder that already use the clock when we share it. |
| 3340 | * |
| 3341 | * Note that enable_shared_dpll tries to do the right thing, but |
| 3342 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 3343 | * the right LVDS enable sequence. */ |
| 3344 | ironlake_enable_shared_dpll(intel_crtc); |
| 3345 | |
Jesse Barnes | d9b6cb5 | 2011-01-04 15:09:35 -0800 | [diff] [blame] | 3346 | /* set transcoder timing, panel must allow it */ |
| 3347 | assert_panel_unlocked(dev_priv, pipe); |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3348 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3349 | |
Paulo Zanoni | 303b81e | 2012-10-31 18:12:23 -0200 | [diff] [blame] | 3350 | intel_fdi_normal_train(crtc); |
Zhenyu Wang | 5e84e1a | 2010-10-28 16:38:08 +0800 | [diff] [blame] | 3351 | |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3352 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 3353 | if (HAS_PCH_CPT(dev) && |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 3354 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 3355 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 3356 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3357 | reg = TRANS_DP_CTL(pipe); |
| 3358 | temp = I915_READ(reg); |
| 3359 | temp &= ~(TRANS_DP_PORT_SEL_MASK | |
Eric Anholt | 220cad3 | 2010-11-18 09:32:58 +0800 | [diff] [blame] | 3360 | TRANS_DP_SYNC_MASK | |
| 3361 | TRANS_DP_BPC_MASK); |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3362 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
| 3363 | TRANS_DP_ENH_FRAMING); |
Jesse Barnes | 9325c9f | 2011-06-24 12:19:21 -0700 | [diff] [blame] | 3364 | temp |= bpc << 9; /* same format but at 11:9 */ |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3365 | |
| 3366 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3367 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3368 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3369 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3370 | |
| 3371 | switch (intel_trans_dp_port_sel(crtc)) { |
| 3372 | case PCH_DP_B: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3373 | temp |= TRANS_DP_PORT_SEL_B; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3374 | break; |
| 3375 | case PCH_DP_C: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3376 | temp |= TRANS_DP_PORT_SEL_C; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3377 | break; |
| 3378 | case PCH_DP_D: |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3379 | temp |= TRANS_DP_PORT_SEL_D; |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3380 | break; |
| 3381 | default: |
Daniel Vetter | e95d41e | 2012-10-26 10:58:16 +0200 | [diff] [blame] | 3382 | BUG(); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3383 | } |
| 3384 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3385 | I915_WRITE(reg, temp); |
Jesse Barnes | c98e9dc | 2010-09-10 10:57:18 -0700 | [diff] [blame] | 3386 | } |
| 3387 | |
Paulo Zanoni | b8a4f40 | 2012-10-31 18:12:42 -0200 | [diff] [blame] | 3388 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3389 | } |
| 3390 | |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3391 | static void lpt_pch_enable(struct drm_crtc *crtc) |
| 3392 | { |
| 3393 | struct drm_device *dev = crtc->dev; |
| 3394 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 3396 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3397 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 3398 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3399 | |
Paulo Zanoni | 8c52b5e | 2012-10-31 18:12:24 -0200 | [diff] [blame] | 3400 | lpt_program_iclkip(crtc); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3401 | |
Paulo Zanoni | 0540e48 | 2012-10-31 18:12:40 -0200 | [diff] [blame] | 3402 | /* Set transcoder timing. */ |
Daniel Vetter | 275f01b2 | 2013-05-03 11:49:47 +0200 | [diff] [blame] | 3403 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3404 | |
Paulo Zanoni | 937bb61 | 2012-10-31 18:12:47 -0200 | [diff] [blame] | 3405 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3406 | } |
| 3407 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3408 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3409 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3410 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3411 | |
| 3412 | if (pll == NULL) |
| 3413 | return; |
| 3414 | |
| 3415 | if (pll->refcount == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3416 | WARN(1, "bad %s refcount\n", pll->name); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3417 | return; |
| 3418 | } |
| 3419 | |
Daniel Vetter | f4a091c | 2013-06-10 17:28:22 +0200 | [diff] [blame] | 3420 | if (--pll->refcount == 0) { |
| 3421 | WARN_ON(pll->on); |
| 3422 | WARN_ON(pll->active); |
| 3423 | } |
| 3424 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3425 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3426 | } |
| 3427 | |
Daniel Vetter | b89a1d3 | 2013-06-05 13:34:24 +0200 | [diff] [blame] | 3428 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3429 | { |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3430 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 3431 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
| 3432 | enum intel_dpll_id i; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3433 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3434 | if (pll) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3435 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
| 3436 | crtc->base.base.id, pll->name); |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3437 | intel_put_shared_dpll(crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3438 | } |
| 3439 | |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3440 | if (HAS_PCH_IBX(dev_priv->dev)) { |
| 3441 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 3442 | i = (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3443 | pll = &dev_priv->shared_dplls[i]; |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3444 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3445 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
| 3446 | crtc->base.base.id, pll->name); |
Daniel Vetter | 98b6bd9 | 2012-05-20 20:00:25 +0200 | [diff] [blame] | 3447 | |
| 3448 | goto found; |
| 3449 | } |
| 3450 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3451 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 3452 | pll = &dev_priv->shared_dplls[i]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3453 | |
| 3454 | /* Only want to check enabled timings first */ |
| 3455 | if (pll->refcount == 0) |
| 3456 | continue; |
| 3457 | |
Daniel Vetter | b89a1d3 | 2013-06-05 13:34:24 +0200 | [diff] [blame] | 3458 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
| 3459 | sizeof(pll->hw_state)) == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3460 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 3461 | crtc->base.base.id, |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3462 | pll->name, pll->refcount, pll->active); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3463 | |
| 3464 | goto found; |
| 3465 | } |
| 3466 | } |
| 3467 | |
| 3468 | /* Ok no matching timings, maybe there's a free one? */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3469 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 3470 | pll = &dev_priv->shared_dplls[i]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3471 | if (pll->refcount == 0) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3472 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
| 3473 | crtc->base.base.id, pll->name); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3474 | goto found; |
| 3475 | } |
| 3476 | } |
| 3477 | |
| 3478 | return NULL; |
| 3479 | |
| 3480 | found: |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 3481 | crtc->config.shared_dpll = i; |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3482 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 3483 | pipe_name(crtc->pipe)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 3484 | |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 3485 | if (pll->active == 0) { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 3486 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
| 3487 | sizeof(pll->hw_state)); |
| 3488 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 3489 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 3490 | WARN_ON(pll->on); |
Daniel Vetter | e9d6944 | 2013-06-05 13:34:15 +0200 | [diff] [blame] | 3491 | assert_shared_dpll_disabled(dev_priv, pll); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3492 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 3493 | pll->mode_set(dev_priv, pll); |
Daniel Vetter | cdbd231 | 2013-06-05 13:34:03 +0200 | [diff] [blame] | 3494 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3495 | pll->refcount++; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3496 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3497 | return pll; |
| 3498 | } |
| 3499 | |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 3500 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3501 | { |
| 3502 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23670b32 | 2012-11-01 09:15:30 +0100 | [diff] [blame] | 3503 | int dslreg = PIPEDSL(pipe); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3504 | u32 temp; |
| 3505 | |
| 3506 | temp = I915_READ(dslreg); |
| 3507 | udelay(500); |
| 3508 | if (wait_for(I915_READ(dslreg) != temp, 5)) { |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3509 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 3510 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 3511 | } |
| 3512 | } |
| 3513 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3514 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
| 3515 | { |
| 3516 | struct drm_device *dev = crtc->base.dev; |
| 3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3518 | int pipe = crtc->pipe; |
| 3519 | |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 3520 | if (crtc->config.pch_pfit.enabled) { |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3521 | /* Force use of hard-coded filter coefficients |
| 3522 | * as some pre-programmed values are broken, |
| 3523 | * e.g. x201. |
| 3524 | */ |
| 3525 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 3526 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
| 3527 | PF_PIPE_SEL_IVB(pipe)); |
| 3528 | else |
| 3529 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
| 3530 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); |
| 3531 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); |
Jesse Barnes | 040484a | 2011-01-03 12:14:26 -0800 | [diff] [blame] | 3532 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3533 | } |
| 3534 | |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3535 | static void intel_enable_planes(struct drm_crtc *crtc) |
| 3536 | { |
| 3537 | struct drm_device *dev = crtc->dev; |
| 3538 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
| 3539 | struct intel_plane *intel_plane; |
| 3540 | |
| 3541 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
| 3542 | if (intel_plane->pipe == pipe) |
| 3543 | intel_plane_restore(&intel_plane->base); |
| 3544 | } |
| 3545 | |
| 3546 | static void intel_disable_planes(struct drm_crtc *crtc) |
| 3547 | { |
| 3548 | struct drm_device *dev = crtc->dev; |
| 3549 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
| 3550 | struct intel_plane *intel_plane; |
| 3551 | |
| 3552 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) |
| 3553 | if (intel_plane->pipe == pipe) |
| 3554 | intel_plane_disable(&intel_plane->base); |
| 3555 | } |
| 3556 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 3557 | void hsw_enable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3558 | { |
| 3559 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
| 3560 | |
| 3561 | if (!crtc->config.ips_enabled) |
| 3562 | return; |
| 3563 | |
| 3564 | /* We can only enable IPS after we enable a plane and wait for a vblank. |
| 3565 | * We guarantee that the plane is enabled by calling intel_enable_ips |
| 3566 | * only after intel_enable_plane. And intel_enable_plane already waits |
| 3567 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
| 3568 | assert_plane_enabled(dev_priv, crtc->plane); |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3569 | if (IS_BROADWELL(crtc->base.dev)) { |
| 3570 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3571 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
| 3572 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3573 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 3574 | * value in IPS_CTL bit 31 after enabling IPS through the |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3575 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 3576 | * so we need to just enable it and continue on. |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3577 | */ |
| 3578 | } else { |
| 3579 | I915_WRITE(IPS_CTL, IPS_ENABLE); |
| 3580 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 3581 | * is essentially intel_wait_for_vblank. If we don't have this |
| 3582 | * and don't wait for vblanks until the end of crtc_enable, then |
| 3583 | * the HW state readout code will complain that the expected |
| 3584 | * IPS_CTL value is not the one we read. */ |
| 3585 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) |
| 3586 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
| 3587 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3588 | } |
| 3589 | |
Ville Syrjälä | 20bc8673 | 2013-10-01 18:02:17 +0300 | [diff] [blame] | 3590 | void hsw_disable_ips(struct intel_crtc *crtc) |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3591 | { |
| 3592 | struct drm_device *dev = crtc->base.dev; |
| 3593 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3594 | |
| 3595 | if (!crtc->config.ips_enabled) |
| 3596 | return; |
| 3597 | |
| 3598 | assert_plane_enabled(dev_priv, crtc->plane); |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3599 | if (IS_BROADWELL(crtc->base.dev)) { |
| 3600 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3601 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); |
| 3602 | mutex_unlock(&dev_priv->rps.hw_lock); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3603 | } else { |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 3604 | I915_WRITE(IPS_CTL, 0); |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 3605 | POSTING_READ(IPS_CTL); |
| 3606 | } |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3607 | |
| 3608 | /* We need to wait for a vblank before we can disable the plane. */ |
| 3609 | intel_wait_for_vblank(dev, crtc->pipe); |
| 3610 | } |
| 3611 | |
| 3612 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 3613 | static void intel_crtc_load_lut(struct drm_crtc *crtc) |
| 3614 | { |
| 3615 | struct drm_device *dev = crtc->dev; |
| 3616 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3617 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3618 | enum pipe pipe = intel_crtc->pipe; |
| 3619 | int palreg = PALETTE(pipe); |
| 3620 | int i; |
| 3621 | bool reenable_ips = false; |
| 3622 | |
| 3623 | /* The clocks have to be on to load the palette. */ |
| 3624 | if (!crtc->enabled || !intel_crtc->active) |
| 3625 | return; |
| 3626 | |
| 3627 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
| 3628 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
| 3629 | assert_dsi_pll_enabled(dev_priv); |
| 3630 | else |
| 3631 | assert_pll_enabled(dev_priv, pipe); |
| 3632 | } |
| 3633 | |
| 3634 | /* use legacy palette for Ironlake */ |
| 3635 | if (HAS_PCH_SPLIT(dev)) |
| 3636 | palreg = LGC_PALETTE(pipe); |
| 3637 | |
| 3638 | /* Workaround : Do not read or write the pipe palette/gamma data while |
| 3639 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 3640 | */ |
Paulo Zanoni | 41e6fc4 | 2014-01-08 17:26:31 -0200 | [diff] [blame] | 3641 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
Paulo Zanoni | d77e453 | 2013-09-24 13:52:55 -0300 | [diff] [blame] | 3642 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
| 3643 | GAMMA_MODE_MODE_SPLIT)) { |
| 3644 | hsw_disable_ips(intel_crtc); |
| 3645 | reenable_ips = true; |
| 3646 | } |
| 3647 | |
| 3648 | for (i = 0; i < 256; i++) { |
| 3649 | I915_WRITE(palreg + 4 * i, |
| 3650 | (intel_crtc->lut_r[i] << 16) | |
| 3651 | (intel_crtc->lut_g[i] << 8) | |
| 3652 | intel_crtc->lut_b[i]); |
| 3653 | } |
| 3654 | |
| 3655 | if (reenable_ips) |
| 3656 | hsw_enable_ips(intel_crtc); |
| 3657 | } |
| 3658 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3659 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
| 3660 | { |
| 3661 | struct drm_device *dev = crtc->dev; |
| 3662 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 3664 | struct intel_encoder *encoder; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3665 | int pipe = intel_crtc->pipe; |
| 3666 | int plane = intel_crtc->plane; |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3667 | |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 3668 | WARN_ON(!crtc->enabled); |
| 3669 | |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3670 | if (intel_crtc->active) |
| 3671 | return; |
| 3672 | |
| 3673 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3674 | |
| 3675 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 3676 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
| 3677 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 3678 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Daniel Vetter | 952735e | 2013-06-05 13:34:27 +0200 | [diff] [blame] | 3679 | if (encoder->pre_enable) |
| 3680 | encoder->pre_enable(encoder); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3681 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3682 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | fff367c | 2012-10-27 15:50:28 +0200 | [diff] [blame] | 3683 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 3684 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 3685 | * enabling. */ |
Daniel Vetter | 88cefb6 | 2012-08-12 19:27:14 +0200 | [diff] [blame] | 3686 | ironlake_fdi_pll_enable(intel_crtc); |
Daniel Vetter | 46b6f81 | 2012-09-06 22:08:33 +0200 | [diff] [blame] | 3687 | } else { |
| 3688 | assert_fdi_tx_disabled(dev_priv, pipe); |
| 3689 | assert_fdi_rx_disabled(dev_priv, pipe); |
| 3690 | } |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3691 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3692 | ironlake_pfit_enable(intel_crtc); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3693 | |
Jesse Barnes | 9c54c0d | 2011-06-15 23:32:33 +0200 | [diff] [blame] | 3694 | /* |
| 3695 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 3696 | * clocks enabled |
| 3697 | */ |
| 3698 | intel_crtc_load_lut(crtc); |
| 3699 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 3700 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 3701 | intel_enable_pipe(intel_crtc); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 3702 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3703 | intel_enable_planes(crtc); |
Ville Syrjälä | 5c38d48 | 2013-06-04 13:49:00 +0300 | [diff] [blame] | 3704 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3705 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3706 | if (intel_crtc->config.has_pch_encoder) |
Jesse Barnes | f67a559 | 2011-01-05 10:31:48 -0800 | [diff] [blame] | 3707 | ironlake_pch_enable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3708 | |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3709 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | bed4a67 | 2010-09-11 10:47:47 +0100 | [diff] [blame] | 3710 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3711 | mutex_unlock(&dev->struct_mutex); |
| 3712 | |
Daniel Vetter | fa5c73b | 2012-07-01 23:24:36 +0200 | [diff] [blame] | 3713 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 3714 | encoder->enable(encoder); |
Daniel Vetter | 61b77dd | 2012-07-02 00:16:19 +0200 | [diff] [blame] | 3715 | |
| 3716 | if (HAS_PCH_CPT(dev)) |
Daniel Vetter | a152031 | 2013-05-03 11:49:50 +0200 | [diff] [blame] | 3717 | cpt_verify_modeset(dev, intel_crtc->pipe); |
Daniel Vetter | 6ce9410 | 2012-10-04 19:20:03 +0200 | [diff] [blame] | 3718 | |
| 3719 | /* |
| 3720 | * There seems to be a race in PCH platform hw (at least on some |
| 3721 | * outputs) where an enabled pipe still completes any pageflip right |
| 3722 | * away (as if the pipe is off) instead of waiting for vblank. As soon |
| 3723 | * as the first vblank happend, everything works as expected. Hence just |
| 3724 | * wait for one vblank before returning to avoid strange things |
| 3725 | * happening. |
| 3726 | */ |
| 3727 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3728 | } |
| 3729 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 3730 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 3731 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 3732 | { |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 3733 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 3734 | } |
| 3735 | |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 3736 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
| 3737 | { |
| 3738 | struct drm_device *dev = crtc->dev; |
| 3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3741 | int pipe = intel_crtc->pipe; |
| 3742 | int plane = intel_crtc->plane; |
| 3743 | |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 3744 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 3745 | intel_enable_planes(crtc); |
| 3746 | intel_crtc_update_cursor(crtc, true); |
| 3747 | |
| 3748 | hsw_enable_ips(intel_crtc); |
| 3749 | |
| 3750 | mutex_lock(&dev->struct_mutex); |
| 3751 | intel_update_fbc(dev); |
| 3752 | mutex_unlock(&dev->struct_mutex); |
| 3753 | } |
| 3754 | |
| 3755 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) |
| 3756 | { |
| 3757 | struct drm_device *dev = crtc->dev; |
| 3758 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3760 | int pipe = intel_crtc->pipe; |
| 3761 | int plane = intel_crtc->plane; |
| 3762 | |
| 3763 | intel_crtc_wait_for_pending_flips(crtc); |
| 3764 | drm_vblank_off(dev, pipe); |
| 3765 | |
| 3766 | /* FBC must be disabled before disabling the plane on HSW. */ |
| 3767 | if (dev_priv->fbc.plane == plane) |
| 3768 | intel_disable_fbc(dev); |
| 3769 | |
| 3770 | hsw_disable_ips(intel_crtc); |
| 3771 | |
| 3772 | intel_crtc_update_cursor(crtc, false); |
| 3773 | intel_disable_planes(crtc); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 3774 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 3775 | } |
| 3776 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 3777 | /* |
| 3778 | * This implements the workaround described in the "notes" section of the mode |
| 3779 | * set sequence documentation. When going from no pipes or single pipe to |
| 3780 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 3781 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 3782 | */ |
| 3783 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) |
| 3784 | { |
| 3785 | struct drm_device *dev = crtc->base.dev; |
| 3786 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; |
| 3787 | |
| 3788 | /* We want to get the other_active_crtc only if there's only 1 other |
| 3789 | * active crtc. */ |
| 3790 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { |
| 3791 | if (!crtc_it->active || crtc_it == crtc) |
| 3792 | continue; |
| 3793 | |
| 3794 | if (other_active_crtc) |
| 3795 | return; |
| 3796 | |
| 3797 | other_active_crtc = crtc_it; |
| 3798 | } |
| 3799 | if (!other_active_crtc) |
| 3800 | return; |
| 3801 | |
| 3802 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
| 3803 | intel_wait_for_vblank(dev, other_active_crtc->pipe); |
| 3804 | } |
| 3805 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3806 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
| 3807 | { |
| 3808 | struct drm_device *dev = crtc->dev; |
| 3809 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3810 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3811 | struct intel_encoder *encoder; |
| 3812 | int pipe = intel_crtc->pipe; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3813 | |
| 3814 | WARN_ON(!crtc->enabled); |
| 3815 | |
| 3816 | if (intel_crtc->active) |
| 3817 | return; |
| 3818 | |
| 3819 | intel_crtc->active = true; |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3820 | |
| 3821 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
| 3822 | if (intel_crtc->config.has_pch_encoder) |
| 3823 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
| 3824 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3825 | if (intel_crtc->config.has_pch_encoder) |
Paulo Zanoni | 0494564 | 2012-11-01 21:00:59 -0200 | [diff] [blame] | 3826 | dev_priv->display.fdi_link_train(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3827 | |
| 3828 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 3829 | if (encoder->pre_enable) |
| 3830 | encoder->pre_enable(encoder); |
| 3831 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 3832 | intel_ddi_enable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3833 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 3834 | ironlake_pfit_enable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3835 | |
| 3836 | /* |
| 3837 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 3838 | * clocks enabled |
| 3839 | */ |
| 3840 | intel_crtc_load_lut(crtc); |
| 3841 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 3842 | intel_ddi_set_pipe_settings(crtc); |
Damien Lespiau | 8228c25 | 2013-03-07 15:30:27 +0000 | [diff] [blame] | 3843 | intel_ddi_enable_transcoder_func(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3844 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 3845 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 3846 | intel_enable_pipe(intel_crtc); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 3847 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 3848 | if (intel_crtc->config.has_pch_encoder) |
Paulo Zanoni | 1507e5b | 2012-10-31 18:12:22 -0200 | [diff] [blame] | 3849 | lpt_pch_enable(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3850 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 3851 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3852 | encoder->enable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 3853 | intel_opregion_notify_encoder(encoder, true); |
| 3854 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3855 | |
Paulo Zanoni | e491694 | 2013-09-20 16:21:19 -0300 | [diff] [blame] | 3856 | /* If we change the relative order between pipe/planes enabling, we need |
| 3857 | * to change the workaround. */ |
| 3858 | haswell_mode_set_planes_workaround(intel_crtc); |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 3859 | haswell_crtc_enable_planes(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3860 | } |
| 3861 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 3862 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
| 3863 | { |
| 3864 | struct drm_device *dev = crtc->base.dev; |
| 3865 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3866 | int pipe = crtc->pipe; |
| 3867 | |
| 3868 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 3869 | * it's in use. The hw state code will make sure we get this right. */ |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 3870 | if (crtc->config.pch_pfit.enabled) { |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 3871 | I915_WRITE(PF_CTL(pipe), 0); |
| 3872 | I915_WRITE(PF_WIN_POS(pipe), 0); |
| 3873 | I915_WRITE(PF_WIN_SZ(pipe), 0); |
| 3874 | } |
| 3875 | } |
| 3876 | |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3877 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
| 3878 | { |
| 3879 | struct drm_device *dev = crtc->dev; |
| 3880 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 3882 | struct intel_encoder *encoder; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3883 | int pipe = intel_crtc->pipe; |
| 3884 | int plane = intel_crtc->plane; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 3885 | u32 reg, temp; |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3886 | |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 3887 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3888 | if (!intel_crtc->active) |
| 3889 | return; |
| 3890 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 3891 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 3892 | encoder->disable(encoder); |
| 3893 | |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 3894 | intel_crtc_wait_for_pending_flips(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3895 | drm_vblank_off(dev, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3896 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 3897 | if (dev_priv->fbc.plane == plane) |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 3898 | intel_disable_fbc(dev); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3899 | |
Ville Syrjälä | 0d5b8c6 | 2013-06-04 13:49:02 +0300 | [diff] [blame] | 3900 | intel_crtc_update_cursor(crtc, false); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 3901 | intel_disable_planes(crtc); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 3902 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | 0d5b8c6 | 2013-06-04 13:49:02 +0300 | [diff] [blame] | 3903 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3904 | if (intel_crtc->config.has_pch_encoder) |
| 3905 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
| 3906 | |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 3907 | intel_disable_pipe(dev_priv, pipe); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3908 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 3909 | ironlake_pfit_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3910 | |
Daniel Vetter | bf49ec8 | 2012-09-06 22:15:40 +0200 | [diff] [blame] | 3911 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 3912 | if (encoder->post_disable) |
| 3913 | encoder->post_disable(encoder); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3914 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3915 | if (intel_crtc->config.has_pch_encoder) { |
| 3916 | ironlake_fdi_disable(crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3917 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3918 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
| 3919 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3920 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3921 | if (HAS_PCH_CPT(dev)) { |
| 3922 | /* disable TRANS_DP_CTL */ |
| 3923 | reg = TRANS_DP_CTL(pipe); |
| 3924 | temp = I915_READ(reg); |
| 3925 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | |
| 3926 | TRANS_DP_PORT_SEL_MASK); |
| 3927 | temp |= TRANS_DP_PORT_SEL_NONE; |
| 3928 | I915_WRITE(reg, temp); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3929 | |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3930 | /* disable DPLL_SEL */ |
| 3931 | temp = I915_READ(PCH_DPLL_SEL); |
Daniel Vetter | 1188739 | 2013-06-05 13:34:09 +0200 | [diff] [blame] | 3932 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3933 | I915_WRITE(PCH_DPLL_SEL, temp); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 3934 | } |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3935 | |
| 3936 | /* disable PCH DPLL */ |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 3937 | intel_disable_shared_dpll(intel_crtc); |
Daniel Vetter | d925c59 | 2013-06-05 13:34:04 +0200 | [diff] [blame] | 3938 | |
| 3939 | ironlake_fdi_pll_disable(intel_crtc); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3940 | } |
| 3941 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 3942 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3943 | intel_update_watermarks(crtc); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3944 | |
| 3945 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 3946 | intel_update_fbc(dev); |
Ben Widawsky | d1ebd816 | 2011-04-25 20:11:50 +0100 | [diff] [blame] | 3947 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 6be4a60 | 2010-09-10 10:26:01 -0700 | [diff] [blame] | 3948 | } |
| 3949 | |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3950 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
| 3951 | { |
| 3952 | struct drm_device *dev = crtc->dev; |
| 3953 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 3955 | struct intel_encoder *encoder; |
| 3956 | int pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 3957 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3958 | |
| 3959 | if (!intel_crtc->active) |
| 3960 | return; |
| 3961 | |
Ville Syrjälä | dda9a66 | 2013-09-19 17:00:37 -0300 | [diff] [blame] | 3962 | haswell_crtc_disable_planes(crtc); |
| 3963 | |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 3964 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 3965 | intel_opregion_notify_encoder(encoder, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3966 | encoder->disable(encoder); |
Jani Nikula | 8807e55 | 2013-08-30 19:40:32 +0300 | [diff] [blame] | 3967 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3968 | |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3969 | if (intel_crtc->config.has_pch_encoder) |
| 3970 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3971 | intel_disable_pipe(dev_priv, pipe); |
| 3972 | |
Paulo Zanoni | ad80a81 | 2012-10-24 16:06:19 -0200 | [diff] [blame] | 3973 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3974 | |
Daniel Vetter | 3f8dce3 | 2013-05-08 10:36:30 +0200 | [diff] [blame] | 3975 | ironlake_pfit_disable(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3976 | |
Paulo Zanoni | 1f54438 | 2012-10-24 11:32:00 -0200 | [diff] [blame] | 3977 | intel_ddi_disable_pipe_clock(intel_crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3978 | |
| 3979 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 3980 | if (encoder->post_disable) |
| 3981 | encoder->post_disable(encoder); |
| 3982 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 3983 | if (intel_crtc->config.has_pch_encoder) { |
Paulo Zanoni | ab4d966 | 2012-10-31 18:12:55 -0200 | [diff] [blame] | 3984 | lpt_disable_pch_transcoder(dev_priv); |
Paulo Zanoni | 8664281 | 2013-04-12 17:57:57 -0300 | [diff] [blame] | 3985 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
Paulo Zanoni | 1ad960f | 2012-11-01 21:05:05 -0200 | [diff] [blame] | 3986 | intel_ddi_fdi_disable(crtc); |
Paulo Zanoni | 8361663 | 2012-10-23 18:29:54 -0200 | [diff] [blame] | 3987 | } |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3988 | |
| 3989 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3990 | intel_update_watermarks(crtc); |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 3991 | |
| 3992 | mutex_lock(&dev->struct_mutex); |
| 3993 | intel_update_fbc(dev); |
| 3994 | mutex_unlock(&dev->struct_mutex); |
| 3995 | } |
| 3996 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 3997 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
| 3998 | { |
| 3999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 4000 | intel_put_shared_dpll(intel_crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4001 | } |
| 4002 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 4003 | static void haswell_crtc_off(struct drm_crtc *crtc) |
| 4004 | { |
| 4005 | intel_ddi_put_crtc_pll(crtc); |
| 4006 | } |
| 4007 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4008 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
| 4009 | { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4010 | if (!enable && intel_crtc->overlay) { |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 4011 | struct drm_device *dev = intel_crtc->base.dev; |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 4013 | |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 4014 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 4015 | dev_priv->mm.interruptible = false; |
| 4016 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 4017 | dev_priv->mm.interruptible = true; |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 4018 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4019 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4020 | |
Chris Wilson | 5dcdbcb | 2010-08-12 13:50:28 +0100 | [diff] [blame] | 4021 | /* Let userspace switch the overlay on again. In most cases userspace |
| 4022 | * has to recompute where to put it anyway. |
| 4023 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 4024 | } |
| 4025 | |
Egbert Eich | 61bc95c | 2013-03-04 09:24:38 -0500 | [diff] [blame] | 4026 | /** |
| 4027 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware |
| 4028 | * cursor plane briefly if not already running after enabling the display |
| 4029 | * plane. |
| 4030 | * This workaround avoids occasional blank screens when self refresh is |
| 4031 | * enabled. |
| 4032 | */ |
| 4033 | static void |
| 4034 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) |
| 4035 | { |
| 4036 | u32 cntl = I915_READ(CURCNTR(pipe)); |
| 4037 | |
| 4038 | if ((cntl & CURSOR_MODE) == 0) { |
| 4039 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); |
| 4040 | |
| 4041 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); |
| 4042 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); |
| 4043 | intel_wait_for_vblank(dev_priv->dev, pipe); |
| 4044 | I915_WRITE(CURCNTR(pipe), cntl); |
| 4045 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); |
| 4046 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); |
| 4047 | } |
| 4048 | } |
| 4049 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4050 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
| 4051 | { |
| 4052 | struct drm_device *dev = crtc->base.dev; |
| 4053 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4054 | struct intel_crtc_config *pipe_config = &crtc->config; |
| 4055 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4056 | if (!crtc->config.gmch_pfit.control) |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4057 | return; |
| 4058 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 4059 | /* |
| 4060 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 4061 | * according to register description and PRM. |
| 4062 | */ |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4063 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
| 4064 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 4065 | |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 4066 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
| 4067 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); |
Daniel Vetter | 5a80c45 | 2013-04-25 22:52:18 +0200 | [diff] [blame] | 4068 | |
| 4069 | /* Border color in case we don't scale up to the full screen. Black by |
| 4070 | * default, change to something else for debugging. */ |
| 4071 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4072 | } |
| 4073 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4074 | #define for_each_power_domain(domain, mask) \ |
| 4075 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ |
| 4076 | if ((1 << (domain)) & (mask)) |
| 4077 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4078 | enum intel_display_power_domain |
| 4079 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4080 | { |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4081 | struct drm_device *dev = intel_encoder->base.dev; |
| 4082 | struct intel_digital_port *intel_dig_port; |
| 4083 | |
| 4084 | switch (intel_encoder->type) { |
| 4085 | case INTEL_OUTPUT_UNKNOWN: |
| 4086 | /* Only DDI platforms should ever use this output type */ |
| 4087 | WARN_ON_ONCE(!HAS_DDI(dev)); |
| 4088 | case INTEL_OUTPUT_DISPLAYPORT: |
| 4089 | case INTEL_OUTPUT_HDMI: |
| 4090 | case INTEL_OUTPUT_EDP: |
| 4091 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 4092 | switch (intel_dig_port->port) { |
| 4093 | case PORT_A: |
| 4094 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; |
| 4095 | case PORT_B: |
| 4096 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; |
| 4097 | case PORT_C: |
| 4098 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; |
| 4099 | case PORT_D: |
| 4100 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; |
| 4101 | default: |
| 4102 | WARN_ON_ONCE(1); |
| 4103 | return POWER_DOMAIN_PORT_OTHER; |
| 4104 | } |
| 4105 | case INTEL_OUTPUT_ANALOG: |
| 4106 | return POWER_DOMAIN_PORT_CRT; |
| 4107 | case INTEL_OUTPUT_DSI: |
| 4108 | return POWER_DOMAIN_PORT_DSI; |
| 4109 | default: |
| 4110 | return POWER_DOMAIN_PORT_OTHER; |
| 4111 | } |
| 4112 | } |
| 4113 | |
| 4114 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
| 4115 | { |
| 4116 | struct drm_device *dev = crtc->dev; |
| 4117 | struct intel_encoder *intel_encoder; |
| 4118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4119 | enum pipe pipe = intel_crtc->pipe; |
| 4120 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4121 | unsigned long mask; |
| 4122 | enum transcoder transcoder; |
| 4123 | |
| 4124 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
| 4125 | |
| 4126 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
| 4127 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); |
| 4128 | if (pfit_enabled) |
| 4129 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
| 4130 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4131 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 4132 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
| 4133 | |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4134 | return mask; |
| 4135 | } |
| 4136 | |
| 4137 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
| 4138 | bool enable) |
| 4139 | { |
| 4140 | if (dev_priv->power_domains.init_power_on == enable) |
| 4141 | return; |
| 4142 | |
| 4143 | if (enable) |
| 4144 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 4145 | else |
| 4146 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
| 4147 | |
| 4148 | dev_priv->power_domains.init_power_on = enable; |
| 4149 | } |
| 4150 | |
| 4151 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
| 4152 | { |
| 4153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4154 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
| 4155 | struct intel_crtc *crtc; |
| 4156 | |
| 4157 | /* |
| 4158 | * First get all needed power domains, then put all unneeded, to avoid |
| 4159 | * any unnecessary toggling of the power wells. |
| 4160 | */ |
| 4161 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 4162 | enum intel_display_power_domain domain; |
| 4163 | |
| 4164 | if (!crtc->base.enabled) |
| 4165 | continue; |
| 4166 | |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 4167 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
Imre Deak | 77d22dc | 2014-03-05 16:20:52 +0200 | [diff] [blame] | 4168 | |
| 4169 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) |
| 4170 | intel_display_power_get(dev_priv, domain); |
| 4171 | } |
| 4172 | |
| 4173 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 4174 | enum intel_display_power_domain domain; |
| 4175 | |
| 4176 | for_each_power_domain(domain, crtc->enabled_power_domains) |
| 4177 | intel_display_power_put(dev_priv, domain); |
| 4178 | |
| 4179 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; |
| 4180 | } |
| 4181 | |
| 4182 | intel_display_set_init_power(dev_priv, false); |
| 4183 | } |
| 4184 | |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4185 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4186 | { |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4187 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4188 | |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4189 | /* Obtain SKU information */ |
| 4190 | mutex_lock(&dev_priv->dpio_lock); |
| 4191 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
| 4192 | CCK_FUSE_HPLL_FREQ_MASK; |
| 4193 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4194 | |
Jesse Barnes | 586f49d | 2013-11-04 16:06:59 -0800 | [diff] [blame] | 4195 | return vco_freq[hpll_freq]; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4196 | } |
| 4197 | |
| 4198 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
| 4199 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) |
| 4200 | { |
| 4201 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4202 | u32 val, cmd; |
| 4203 | |
| 4204 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
| 4205 | cmd = 2; |
| 4206 | else if (cdclk == 266) |
| 4207 | cmd = 1; |
| 4208 | else |
| 4209 | cmd = 0; |
| 4210 | |
| 4211 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4212 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 4213 | val &= ~DSPFREQGUAR_MASK; |
| 4214 | val |= (cmd << DSPFREQGUAR_SHIFT); |
| 4215 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); |
| 4216 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & |
| 4217 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
| 4218 | 50)) { |
| 4219 | DRM_ERROR("timed out waiting for CDclk change\n"); |
| 4220 | } |
| 4221 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4222 | |
| 4223 | if (cdclk == 400) { |
| 4224 | u32 divider, vco; |
| 4225 | |
| 4226 | vco = valleyview_get_vco(dev_priv); |
| 4227 | divider = ((vco << 1) / cdclk) - 1; |
| 4228 | |
| 4229 | mutex_lock(&dev_priv->dpio_lock); |
| 4230 | /* adjust cdclk divider */ |
| 4231 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
| 4232 | val &= ~0xf; |
| 4233 | val |= divider; |
| 4234 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); |
| 4235 | mutex_unlock(&dev_priv->dpio_lock); |
| 4236 | } |
| 4237 | |
| 4238 | mutex_lock(&dev_priv->dpio_lock); |
| 4239 | /* adjust self-refresh exit latency value */ |
| 4240 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); |
| 4241 | val &= ~0x7f; |
| 4242 | |
| 4243 | /* |
| 4244 | * For high bandwidth configs, we set a higher latency in the bunit |
| 4245 | * so that the core display fetch happens in time to avoid underruns. |
| 4246 | */ |
| 4247 | if (cdclk == 400) |
| 4248 | val |= 4500 / 250; /* 4.5 usec */ |
| 4249 | else |
| 4250 | val |= 3000 / 250; /* 3.0 usec */ |
| 4251 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); |
| 4252 | mutex_unlock(&dev_priv->dpio_lock); |
| 4253 | |
| 4254 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ |
| 4255 | intel_i2c_reset(dev); |
| 4256 | } |
| 4257 | |
| 4258 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
| 4259 | { |
| 4260 | int cur_cdclk, vco; |
| 4261 | int divider; |
| 4262 | |
| 4263 | vco = valleyview_get_vco(dev_priv); |
| 4264 | |
| 4265 | mutex_lock(&dev_priv->dpio_lock); |
| 4266 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
| 4267 | mutex_unlock(&dev_priv->dpio_lock); |
| 4268 | |
| 4269 | divider &= 0xf; |
| 4270 | |
| 4271 | cur_cdclk = (vco << 1) / (divider + 1); |
| 4272 | |
| 4273 | return cur_cdclk; |
| 4274 | } |
| 4275 | |
| 4276 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
| 4277 | int max_pixclk) |
| 4278 | { |
| 4279 | int cur_cdclk; |
| 4280 | |
| 4281 | cur_cdclk = valleyview_cur_cdclk(dev_priv); |
| 4282 | |
| 4283 | /* |
| 4284 | * Really only a few cases to deal with, as only 4 CDclks are supported: |
| 4285 | * 200MHz |
| 4286 | * 267MHz |
| 4287 | * 320MHz |
| 4288 | * 400MHz |
| 4289 | * So we check to see whether we're above 90% of the lower bin and |
| 4290 | * adjust if needed. |
| 4291 | */ |
| 4292 | if (max_pixclk > 288000) { |
| 4293 | return 400; |
| 4294 | } else if (max_pixclk > 240000) { |
| 4295 | return 320; |
| 4296 | } else |
| 4297 | return 266; |
| 4298 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
| 4299 | } |
| 4300 | |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4301 | /* compute the max pixel clock for new configuration */ |
| 4302 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4303 | { |
| 4304 | struct drm_device *dev = dev_priv->dev; |
| 4305 | struct intel_crtc *intel_crtc; |
| 4306 | int max_pixclk = 0; |
| 4307 | |
| 4308 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 4309 | base.head) { |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4310 | if (intel_crtc->new_enabled) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4311 | max_pixclk = max(max_pixclk, |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4312 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4313 | } |
| 4314 | |
| 4315 | return max_pixclk; |
| 4316 | } |
| 4317 | |
| 4318 | static void valleyview_modeset_global_pipes(struct drm_device *dev, |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4319 | unsigned *prepare_pipes) |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4320 | { |
| 4321 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4322 | struct intel_crtc *intel_crtc; |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4323 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4324 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
| 4325 | |
| 4326 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) |
| 4327 | return; |
| 4328 | |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4329 | /* disable/enable all currently active pipes while we change cdclk */ |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4330 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 4331 | base.head) |
| 4332 | if (intel_crtc->base.enabled) |
| 4333 | *prepare_pipes |= (1 << intel_crtc->pipe); |
| 4334 | } |
| 4335 | |
| 4336 | static void valleyview_modeset_global_resources(struct drm_device *dev) |
| 4337 | { |
| 4338 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 4339 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4340 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
| 4341 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
| 4342 | |
| 4343 | if (req_cdclk != cur_cdclk) |
| 4344 | valleyview_set_cdclk(dev, req_cdclk); |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 4345 | modeset_update_crtc_power_domains(dev); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 4346 | } |
| 4347 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4348 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
| 4349 | { |
| 4350 | struct drm_device *dev = crtc->dev; |
| 4351 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4353 | struct intel_encoder *encoder; |
| 4354 | int pipe = intel_crtc->pipe; |
| 4355 | int plane = intel_crtc->plane; |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 4356 | bool is_dsi; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4357 | |
| 4358 | WARN_ON(!crtc->enabled); |
| 4359 | |
| 4360 | if (intel_crtc->active) |
| 4361 | return; |
| 4362 | |
| 4363 | intel_crtc->active = true; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4364 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4365 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4366 | if (encoder->pre_pll_enable) |
| 4367 | encoder->pre_pll_enable(encoder); |
| 4368 | |
Jani Nikula | 23538ef | 2013-08-27 15:12:22 +0300 | [diff] [blame] | 4369 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
| 4370 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 4371 | if (!is_dsi) |
| 4372 | vlv_enable_pll(intel_crtc); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4373 | |
| 4374 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4375 | if (encoder->pre_enable) |
| 4376 | encoder->pre_enable(encoder); |
| 4377 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4378 | i9xx_pfit_enable(intel_crtc); |
| 4379 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 4380 | intel_crtc_load_lut(crtc); |
| 4381 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4382 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4383 | intel_enable_pipe(intel_crtc); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4384 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 4385 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 4386 | intel_enable_planes(crtc); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4387 | intel_crtc_update_cursor(crtc, true); |
| 4388 | |
Ville Syrjälä | f440eb1 | 2013-06-04 13:49:01 +0300 | [diff] [blame] | 4389 | intel_update_fbc(dev); |
Jani Nikula | 5004945 | 2013-07-30 12:20:32 +0300 | [diff] [blame] | 4390 | |
| 4391 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4392 | encoder->enable(encoder); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4393 | } |
| 4394 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4395 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4396 | { |
| 4397 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4398 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4400 | struct intel_encoder *encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4401 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 4402 | int plane = intel_crtc->plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4403 | |
Daniel Vetter | 08a4846 | 2012-07-02 11:43:47 +0200 | [diff] [blame] | 4404 | WARN_ON(!crtc->enabled); |
| 4405 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4406 | if (intel_crtc->active) |
| 4407 | return; |
| 4408 | |
| 4409 | intel_crtc->active = true; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4410 | |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 4411 | for_each_encoder_on_crtc(dev, crtc, encoder) |
Mika Kuoppala | 9d6d9f1 | 2013-02-08 16:35:38 +0200 | [diff] [blame] | 4412 | if (encoder->pre_enable) |
| 4413 | encoder->pre_enable(encoder); |
| 4414 | |
Daniel Vetter | f6736a1 | 2013-06-05 13:34:30 +0200 | [diff] [blame] | 4415 | i9xx_enable_pll(intel_crtc); |
| 4416 | |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 4417 | i9xx_pfit_enable(intel_crtc); |
| 4418 | |
Ville Syrjälä | 63cbb07 | 2013-06-04 13:48:59 +0300 | [diff] [blame] | 4419 | intel_crtc_load_lut(crtc); |
| 4420 | |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4421 | intel_update_watermarks(crtc); |
Paulo Zanoni | e1fdc47 | 2014-01-17 13:51:12 -0200 | [diff] [blame] | 4422 | intel_enable_pipe(intel_crtc); |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4423 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 4424 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 4425 | intel_enable_planes(crtc); |
Ville Syrjälä | 22e407d | 2013-06-07 18:52:24 +0300 | [diff] [blame] | 4426 | /* The fixup needs to happen before cursor is enabled */ |
Egbert Eich | 61bc95c | 2013-03-04 09:24:38 -0500 | [diff] [blame] | 4427 | if (IS_G4X(dev)) |
| 4428 | g4x_fixup_plane(dev_priv, pipe); |
Ville Syrjälä | 22e407d | 2013-06-07 18:52:24 +0300 | [diff] [blame] | 4429 | intel_crtc_update_cursor(crtc, true); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4430 | |
| 4431 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
| 4432 | intel_crtc_dpms_overlay(intel_crtc, true); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4433 | |
Ville Syrjälä | f440eb1 | 2013-06-04 13:49:01 +0300 | [diff] [blame] | 4434 | intel_update_fbc(dev); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4435 | |
Daniel Vetter | fa5c73b | 2012-07-01 23:24:36 +0200 | [diff] [blame] | 4436 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4437 | encoder->enable(encoder); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4438 | } |
| 4439 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4440 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
| 4441 | { |
| 4442 | struct drm_device *dev = crtc->base.dev; |
| 4443 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4444 | |
| 4445 | if (!crtc->config.gmch_pfit.control) |
| 4446 | return; |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4447 | |
| 4448 | assert_pipe_disabled(dev_priv, crtc->pipe); |
| 4449 | |
Daniel Vetter | 328d8e8 | 2013-05-08 10:36:31 +0200 | [diff] [blame] | 4450 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
| 4451 | I915_READ(PFIT_CONTROL)); |
| 4452 | I915_WRITE(PFIT_CONTROL, 0); |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4453 | } |
| 4454 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4455 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
| 4456 | { |
| 4457 | struct drm_device *dev = crtc->dev; |
| 4458 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4460 | struct intel_encoder *encoder; |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4461 | int pipe = intel_crtc->pipe; |
| 4462 | int plane = intel_crtc->plane; |
Daniel Vetter | ef9c3ae | 2012-06-29 22:40:09 +0200 | [diff] [blame] | 4463 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4464 | if (!intel_crtc->active) |
| 4465 | return; |
| 4466 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 4467 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4468 | encoder->disable(encoder); |
| 4469 | |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4470 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
Chris Wilson | e6c3a2a | 2010-09-23 23:04:43 +0100 | [diff] [blame] | 4471 | intel_crtc_wait_for_pending_flips(crtc); |
| 4472 | drm_vblank_off(dev, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4473 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 4474 | if (dev_priv->fbc.plane == plane) |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 4475 | intel_disable_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4476 | |
Ville Syrjälä | 0d5b8c6 | 2013-06-04 13:49:02 +0300 | [diff] [blame] | 4477 | intel_crtc_dpms_overlay(intel_crtc, false); |
| 4478 | intel_crtc_update_cursor(crtc, false); |
Ville Syrjälä | bb53d4a | 2013-06-04 13:49:04 +0300 | [diff] [blame] | 4479 | intel_disable_planes(crtc); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 4480 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); |
Ville Syrjälä | 0d5b8c6 | 2013-06-04 13:49:02 +0300 | [diff] [blame] | 4481 | |
Ville Syrjälä | 2d9d2b0 | 2014-01-17 11:44:31 +0200 | [diff] [blame] | 4482 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 4483 | intel_disable_pipe(dev_priv, pipe); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 4484 | |
Daniel Vetter | 87476d6 | 2013-04-11 16:29:06 +0200 | [diff] [blame] | 4485 | i9xx_pfit_disable(intel_crtc); |
Mika Kuoppala | 24a1f16 | 2013-02-08 16:35:37 +0200 | [diff] [blame] | 4486 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 4487 | for_each_encoder_on_crtc(dev, crtc, encoder) |
| 4488 | if (encoder->post_disable) |
| 4489 | encoder->post_disable(encoder); |
| 4490 | |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 4491 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
| 4492 | vlv_disable_pll(dev_priv, pipe); |
| 4493 | else if (!IS_VALLEYVIEW(dev)) |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 4494 | i9xx_disable_pll(dev_priv, pipe); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4495 | |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 4496 | intel_crtc->active = false; |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 4497 | intel_update_watermarks(crtc); |
Ville Syrjälä | f37fcc2 | 2013-09-10 11:39:55 +0300 | [diff] [blame] | 4498 | |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 4499 | intel_update_fbc(dev); |
Jesse Barnes | 0b8765c6 | 2010-09-10 10:31:34 -0700 | [diff] [blame] | 4500 | } |
| 4501 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4502 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
| 4503 | { |
| 4504 | } |
| 4505 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4506 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
| 4507 | bool enabled) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4508 | { |
| 4509 | struct drm_device *dev = crtc->dev; |
| 4510 | struct drm_i915_master_private *master_priv; |
| 4511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 4512 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4513 | |
| 4514 | if (!dev->primary->master) |
| 4515 | return; |
| 4516 | |
| 4517 | master_priv = dev->primary->master->driver_priv; |
| 4518 | if (!master_priv->sarea_priv) |
| 4519 | return; |
| 4520 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4521 | switch (pipe) { |
| 4522 | case 0: |
| 4523 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; |
| 4524 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; |
| 4525 | break; |
| 4526 | case 1: |
| 4527 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; |
| 4528 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; |
| 4529 | break; |
| 4530 | default: |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 4531 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4532 | break; |
| 4533 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4534 | } |
| 4535 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4536 | /** |
| 4537 | * Sets the power management mode of the pipe and plane. |
| 4538 | */ |
| 4539 | void intel_crtc_update_dpms(struct drm_crtc *crtc) |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4540 | { |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4541 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4542 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4543 | struct intel_encoder *intel_encoder; |
| 4544 | bool enable = false; |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4545 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4546 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
| 4547 | enable |= intel_encoder->connectors_active; |
| 4548 | |
| 4549 | if (enable) |
| 4550 | dev_priv->display.crtc_enable(crtc); |
| 4551 | else |
| 4552 | dev_priv->display.crtc_disable(crtc); |
| 4553 | |
| 4554 | intel_crtc_update_sarea(crtc, enable); |
| 4555 | } |
| 4556 | |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4557 | static void intel_crtc_disable(struct drm_crtc *crtc) |
| 4558 | { |
| 4559 | struct drm_device *dev = crtc->dev; |
| 4560 | struct drm_connector *connector; |
| 4561 | struct drm_i915_private *dev_priv = dev->dev_private; |
Wang Xingchao | 7b9f35a | 2013-01-22 23:25:25 +0800 | [diff] [blame] | 4562 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4563 | |
| 4564 | /* crtc should still be enabled when we disable it. */ |
| 4565 | WARN_ON(!crtc->enabled); |
| 4566 | |
| 4567 | dev_priv->display.crtc_disable(crtc); |
Paulo Zanoni | c77bf56 | 2013-05-03 12:15:40 -0300 | [diff] [blame] | 4568 | intel_crtc->eld_vld = false; |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4569 | intel_crtc_update_sarea(crtc, false); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 4570 | dev_priv->display.off(crtc); |
| 4571 | |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 4572 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
Jani Nikula | 93ce0ba | 2013-09-13 11:03:08 +0300 | [diff] [blame] | 4573 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
Chris Wilson | 931872f | 2012-01-16 23:01:13 +0000 | [diff] [blame] | 4574 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4575 | |
| 4576 | if (crtc->fb) { |
| 4577 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 4578 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4579 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 976f8a2 | 2012-07-08 22:34:21 +0200 | [diff] [blame] | 4580 | crtc->fb = NULL; |
| 4581 | } |
| 4582 | |
| 4583 | /* Update computed state. */ |
| 4584 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 4585 | if (!connector->encoder || !connector->encoder->crtc) |
| 4586 | continue; |
| 4587 | |
| 4588 | if (connector->encoder->crtc != crtc) |
| 4589 | continue; |
| 4590 | |
| 4591 | connector->dpms = DRM_MODE_DPMS_OFF; |
| 4592 | to_intel_encoder(connector->encoder)->connectors_active = false; |
Chris Wilson | cdd5998 | 2010-09-08 16:30:16 +0100 | [diff] [blame] | 4593 | } |
| 4594 | } |
| 4595 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 4596 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 4597 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 4598 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 4599 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 4600 | drm_encoder_cleanup(encoder); |
| 4601 | kfree(intel_encoder); |
| 4602 | } |
| 4603 | |
Damien Lespiau | 9237329 | 2013-08-08 22:28:57 +0100 | [diff] [blame] | 4604 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4605 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
| 4606 | * state of the entire output pipe. */ |
Damien Lespiau | 9237329 | 2013-08-08 22:28:57 +0100 | [diff] [blame] | 4607 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4608 | { |
| 4609 | if (mode == DRM_MODE_DPMS_ON) { |
| 4610 | encoder->connectors_active = true; |
| 4611 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 4612 | intel_crtc_update_dpms(encoder->base.crtc); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4613 | } else { |
| 4614 | encoder->connectors_active = false; |
| 4615 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 4616 | intel_crtc_update_dpms(encoder->base.crtc); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4617 | } |
| 4618 | } |
| 4619 | |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 4620 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 4621 | * internal consistency). */ |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 4622 | static void intel_connector_check_state(struct intel_connector *connector) |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 4623 | { |
| 4624 | if (connector->get_hw_state(connector)) { |
| 4625 | struct intel_encoder *encoder = connector->encoder; |
| 4626 | struct drm_crtc *crtc; |
| 4627 | bool encoder_enabled; |
| 4628 | enum pipe pipe; |
| 4629 | |
| 4630 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 4631 | connector->base.base.id, |
| 4632 | drm_get_connector_name(&connector->base)); |
| 4633 | |
| 4634 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
| 4635 | "wrong connector dpms state\n"); |
| 4636 | WARN(connector->base.encoder != &encoder->base, |
| 4637 | "active connector not linked to encoder\n"); |
| 4638 | WARN(!encoder->connectors_active, |
| 4639 | "encoder->connectors_active not set\n"); |
| 4640 | |
| 4641 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); |
| 4642 | WARN(!encoder_enabled, "encoder not enabled\n"); |
| 4643 | if (WARN_ON(!encoder->base.crtc)) |
| 4644 | return; |
| 4645 | |
| 4646 | crtc = encoder->base.crtc; |
| 4647 | |
| 4648 | WARN(!crtc->enabled, "crtc not enabled\n"); |
| 4649 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
| 4650 | WARN(pipe != to_intel_crtc(crtc)->pipe, |
| 4651 | "encoder active on the wrong pipe\n"); |
| 4652 | } |
| 4653 | } |
| 4654 | |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4655 | /* Even simpler default implementation, if there's really no special case to |
| 4656 | * consider. */ |
| 4657 | void intel_connector_dpms(struct drm_connector *connector, int mode) |
| 4658 | { |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4659 | /* All the simple cases only support two dpms states. */ |
| 4660 | if (mode != DRM_MODE_DPMS_ON) |
| 4661 | mode = DRM_MODE_DPMS_OFF; |
| 4662 | |
| 4663 | if (mode == connector->dpms) |
| 4664 | return; |
| 4665 | |
| 4666 | connector->dpms = mode; |
| 4667 | |
| 4668 | /* Only need to change hw state when actually enabled */ |
Chris Wilson | c9976dc | 2013-09-29 19:15:07 +0100 | [diff] [blame] | 4669 | if (connector->encoder) |
| 4670 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); |
Daniel Vetter | 0a91ca2 | 2012-07-02 21:54:27 +0200 | [diff] [blame] | 4671 | |
Daniel Vetter | b980514 | 2012-08-31 17:37:33 +0200 | [diff] [blame] | 4672 | intel_modeset_check_state(connector->dev); |
Daniel Vetter | 5ab432e | 2012-06-30 08:59:56 +0200 | [diff] [blame] | 4673 | } |
| 4674 | |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 4675 | /* Simple connector->get_hw_state implementation for encoders that support only |
| 4676 | * one connector and no cloning and hence the encoder state determines the state |
| 4677 | * of the connector. */ |
| 4678 | bool intel_connector_get_hw_state(struct intel_connector *connector) |
| 4679 | { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 4680 | enum pipe pipe = 0; |
Daniel Vetter | f0947c3 | 2012-07-02 13:10:34 +0200 | [diff] [blame] | 4681 | struct intel_encoder *encoder = connector->encoder; |
| 4682 | |
| 4683 | return encoder->get_hw_state(encoder, &pipe); |
| 4684 | } |
| 4685 | |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 4686 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
| 4687 | struct intel_crtc_config *pipe_config) |
| 4688 | { |
| 4689 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4690 | struct intel_crtc *pipe_B_crtc = |
| 4691 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); |
| 4692 | |
| 4693 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
| 4694 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 4695 | if (pipe_config->fdi_lanes > 4) { |
| 4696 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", |
| 4697 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 4698 | return false; |
| 4699 | } |
| 4700 | |
Paulo Zanoni | bafb655 | 2013-11-02 21:07:44 -0700 | [diff] [blame] | 4701 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 4702 | if (pipe_config->fdi_lanes > 2) { |
| 4703 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", |
| 4704 | pipe_config->fdi_lanes); |
| 4705 | return false; |
| 4706 | } else { |
| 4707 | return true; |
| 4708 | } |
| 4709 | } |
| 4710 | |
| 4711 | if (INTEL_INFO(dev)->num_pipes == 2) |
| 4712 | return true; |
| 4713 | |
| 4714 | /* Ivybridge 3 pipe is really complicated */ |
| 4715 | switch (pipe) { |
| 4716 | case PIPE_A: |
| 4717 | return true; |
| 4718 | case PIPE_B: |
| 4719 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && |
| 4720 | pipe_config->fdi_lanes > 2) { |
| 4721 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 4722 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 4723 | return false; |
| 4724 | } |
| 4725 | return true; |
| 4726 | case PIPE_C: |
Daniel Vetter | 1e833f4 | 2013-02-19 22:31:57 +0100 | [diff] [blame] | 4727 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 4728 | pipe_B_crtc->config.fdi_lanes <= 2) { |
| 4729 | if (pipe_config->fdi_lanes > 2) { |
| 4730 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
| 4731 | pipe_name(pipe), pipe_config->fdi_lanes); |
| 4732 | return false; |
| 4733 | } |
| 4734 | } else { |
| 4735 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
| 4736 | return false; |
| 4737 | } |
| 4738 | return true; |
| 4739 | default: |
| 4740 | BUG(); |
| 4741 | } |
| 4742 | } |
| 4743 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4744 | #define RETRY 1 |
| 4745 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, |
| 4746 | struct intel_crtc_config *pipe_config) |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4747 | { |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 4748 | struct drm_device *dev = intel_crtc->base.dev; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4749 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 4750 | int lane, link_bw, fdi_dotclock; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4751 | bool setup_ok, needs_recompute = false; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4752 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4753 | retry: |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4754 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 4755 | * each output octet as 10 bits. The actual frequency |
| 4756 | * is stored as a divider into a 100MHz clock, and the |
| 4757 | * mode pixel clock is stored in units of 1KHz. |
| 4758 | * Hence the bw of each lane in terms of the mode signal |
| 4759 | * is: |
| 4760 | */ |
| 4761 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; |
| 4762 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 4763 | fdi_dotclock = adjusted_mode->crtc_clock; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4764 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 4765 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4766 | pipe_config->pipe_bpp); |
| 4767 | |
| 4768 | pipe_config->fdi_lanes = lane; |
| 4769 | |
Daniel Vetter | 2bd89a0 | 2013-06-01 17:16:19 +0200 | [diff] [blame] | 4770 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4771 | link_bw, &pipe_config->fdi_m_n); |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 4772 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4773 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
| 4774 | intel_crtc->pipe, pipe_config); |
| 4775 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { |
| 4776 | pipe_config->pipe_bpp -= 2*3; |
| 4777 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
| 4778 | pipe_config->pipe_bpp); |
| 4779 | needs_recompute = true; |
| 4780 | pipe_config->bw_constrained = true; |
| 4781 | |
| 4782 | goto retry; |
| 4783 | } |
| 4784 | |
| 4785 | if (needs_recompute) |
| 4786 | return RETRY; |
| 4787 | |
| 4788 | return setup_ok ? 0 : -EINVAL; |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4789 | } |
| 4790 | |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4791 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
| 4792 | struct intel_crtc_config *pipe_config) |
| 4793 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 4794 | pipe_config->ips_enabled = i915.enable_ips && |
Paulo Zanoni | 3c4ca58 | 2013-05-31 16:33:23 -0300 | [diff] [blame] | 4795 | hsw_crtc_supports_ips(crtc) && |
Jesse Barnes | b6dfdc9 | 2013-07-25 10:06:50 -0700 | [diff] [blame] | 4796 | pipe_config->pipe_bpp <= 24; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4797 | } |
| 4798 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 4799 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4800 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4801 | { |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 4802 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 4803 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 4804 | |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 4805 | /* FIXME should check pixel clock limits on all platforms */ |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 4806 | if (INTEL_INFO(dev)->gen < 4) { |
| 4807 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4808 | int clock_limit = |
| 4809 | dev_priv->display.get_display_clock_speed(dev); |
| 4810 | |
| 4811 | /* |
| 4812 | * Enable pixel doubling when the dot clock |
| 4813 | * is > 90% of the (display) core speed. |
| 4814 | * |
Ville Syrjälä | b397c96 | 2013-09-04 18:30:06 +0300 | [diff] [blame] | 4815 | * GDG double wide on either pipe, |
| 4816 | * otherwise pipe A only. |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 4817 | */ |
Ville Syrjälä | b397c96 | 2013-09-04 18:30:06 +0300 | [diff] [blame] | 4818 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 4819 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 4820 | clock_limit *= 2; |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 4821 | pipe_config->double_wide = true; |
Ville Syrjälä | ad3a447 | 2013-09-04 18:30:04 +0300 | [diff] [blame] | 4822 | } |
| 4823 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 4824 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4825 | return -EINVAL; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4826 | } |
Chris Wilson | 8974935 | 2010-09-12 18:25:19 +0100 | [diff] [blame] | 4827 | |
Ville Syrjälä | 1d1d0e2 | 2013-09-04 18:30:05 +0300 | [diff] [blame] | 4828 | /* |
| 4829 | * Pipe horizontal size must be even in: |
| 4830 | * - DVO ganged mode |
| 4831 | * - LVDS dual channel mode |
| 4832 | * - Double wide pipe |
| 4833 | */ |
| 4834 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
| 4835 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
| 4836 | pipe_config->pipe_src_w &= ~1; |
| 4837 | |
Damien Lespiau | 8693a82 | 2013-05-03 18:48:11 +0100 | [diff] [blame] | 4838 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 4839 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 4840 | */ |
| 4841 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && |
| 4842 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4843 | return -EINVAL; |
Chris Wilson | 44f46b42 | 2012-06-21 13:19:59 +0300 | [diff] [blame] | 4844 | |
Daniel Vetter | bd080ee | 2013-04-17 20:01:39 +0200 | [diff] [blame] | 4845 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
Daniel Vetter | 5d2d38d | 2013-03-27 00:45:01 +0100 | [diff] [blame] | 4846 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
Daniel Vetter | bd080ee | 2013-04-17 20:01:39 +0200 | [diff] [blame] | 4847 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
Daniel Vetter | 5d2d38d | 2013-03-27 00:45:01 +0100 | [diff] [blame] | 4848 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
| 4849 | * for lvds. */ |
| 4850 | pipe_config->pipe_bpp = 8*3; |
| 4851 | } |
| 4852 | |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 4853 | if (HAS_IPS(dev)) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 4854 | hsw_compute_ips_config(crtc, pipe_config); |
| 4855 | |
| 4856 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old |
| 4857 | * clock survives for now. */ |
| 4858 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 4859 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 4860 | |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4861 | if (pipe_config->has_pch_encoder) |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 4862 | return ironlake_fdi_compute_config(crtc, pipe_config); |
Daniel Vetter | 877d48d | 2013-04-19 11:24:43 +0200 | [diff] [blame] | 4863 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 4864 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4865 | } |
| 4866 | |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 4867 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
| 4868 | { |
| 4869 | return 400000; /* FIXME */ |
| 4870 | } |
| 4871 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4872 | static int i945_get_display_clock_speed(struct drm_device *dev) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4873 | { |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4874 | return 400000; |
| 4875 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4876 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4877 | static int i915_get_display_clock_speed(struct drm_device *dev) |
| 4878 | { |
| 4879 | return 333000; |
| 4880 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4881 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4882 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
| 4883 | { |
| 4884 | return 200000; |
| 4885 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4886 | |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 4887 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
| 4888 | { |
| 4889 | u16 gcfgc = 0; |
| 4890 | |
| 4891 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 4892 | |
| 4893 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 4894 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: |
| 4895 | return 267000; |
| 4896 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
| 4897 | return 333000; |
| 4898 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
| 4899 | return 444000; |
| 4900 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
| 4901 | return 200000; |
| 4902 | default: |
| 4903 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); |
| 4904 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
| 4905 | return 133000; |
| 4906 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
| 4907 | return 167000; |
| 4908 | } |
| 4909 | } |
| 4910 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4911 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 4912 | { |
| 4913 | u16 gcfgc = 0; |
| 4914 | |
| 4915 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
| 4916 | |
| 4917 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4918 | return 133000; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4919 | else { |
| 4920 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { |
| 4921 | case GC_DISPLAY_CLOCK_333_MHZ: |
| 4922 | return 333000; |
| 4923 | default: |
| 4924 | case GC_DISPLAY_CLOCK_190_200_MHZ: |
| 4925 | return 190000; |
| 4926 | } |
| 4927 | } |
| 4928 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4929 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 4930 | static int i865_get_display_clock_speed(struct drm_device *dev) |
| 4931 | { |
| 4932 | return 266000; |
| 4933 | } |
| 4934 | |
| 4935 | static int i855_get_display_clock_speed(struct drm_device *dev) |
| 4936 | { |
| 4937 | u16 hpllcc = 0; |
| 4938 | /* Assume that the hardware is in the high speed state. This |
| 4939 | * should be the default. |
| 4940 | */ |
| 4941 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { |
| 4942 | case GC_CLOCK_133_200: |
| 4943 | case GC_CLOCK_100_200: |
| 4944 | return 200000; |
| 4945 | case GC_CLOCK_166_250: |
| 4946 | return 250000; |
| 4947 | case GC_CLOCK_100_133: |
| 4948 | return 133000; |
| 4949 | } |
| 4950 | |
| 4951 | /* Shouldn't happen */ |
| 4952 | return 0; |
| 4953 | } |
| 4954 | |
| 4955 | static int i830_get_display_clock_speed(struct drm_device *dev) |
| 4956 | { |
| 4957 | return 133000; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4958 | } |
| 4959 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4960 | static void |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 4961 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4962 | { |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 4963 | while (*num > DATA_LINK_M_N_MASK || |
| 4964 | *den > DATA_LINK_M_N_MASK) { |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4965 | *num >>= 1; |
| 4966 | *den >>= 1; |
| 4967 | } |
| 4968 | } |
| 4969 | |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 4970 | static void compute_m_n(unsigned int m, unsigned int n, |
| 4971 | uint32_t *ret_m, uint32_t *ret_n) |
| 4972 | { |
| 4973 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
| 4974 | *ret_m = div_u64((uint64_t) m * *ret_n, n); |
| 4975 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 4976 | } |
| 4977 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 4978 | void |
| 4979 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, |
| 4980 | int pixel_clock, int link_clock, |
| 4981 | struct intel_link_m_n *m_n) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4982 | { |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 4983 | m_n->tu = 64; |
Ville Syrjälä | a65851a | 2013-04-23 15:03:34 +0300 | [diff] [blame] | 4984 | |
| 4985 | compute_m_n(bits_per_pixel * pixel_clock, |
| 4986 | link_clock * nlanes * 8, |
| 4987 | &m_n->gmch_m, &m_n->gmch_n); |
| 4988 | |
| 4989 | compute_m_n(pixel_clock, link_clock, |
| 4990 | &m_n->link_m, &m_n->link_n); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 4991 | } |
| 4992 | |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 4993 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
| 4994 | { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 4995 | if (i915.panel_use_ssc >= 0) |
| 4996 | return i915.panel_use_ssc != 0; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 4997 | return dev_priv->vbt.lvds_use_ssc |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 4998 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
Chris Wilson | a761503 | 2011-01-12 17:04:08 +0000 | [diff] [blame] | 4999 | } |
| 5000 | |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5001 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
| 5002 | { |
| 5003 | struct drm_device *dev = crtc->dev; |
| 5004 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5005 | int refclk; |
| 5006 | |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5007 | if (IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 9a0ea49 | 2013-09-16 11:29:34 +0200 | [diff] [blame] | 5008 | refclk = 100000; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5009 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5010 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 5011 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 5012 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5013 | } else if (!IS_GEN2(dev)) { |
| 5014 | refclk = 96000; |
| 5015 | } else { |
| 5016 | refclk = 48000; |
| 5017 | } |
| 5018 | |
| 5019 | return refclk; |
| 5020 | } |
| 5021 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5022 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5023 | { |
Daniel Vetter | 7df00d7 | 2013-05-21 21:54:55 +0200 | [diff] [blame] | 5024 | return (1 << dpll->n) << 16 | dpll->m2; |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5025 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5026 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5027 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
| 5028 | { |
| 5029 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
Jesse Barnes | c65d77d | 2011-12-15 12:30:36 -0800 | [diff] [blame] | 5030 | } |
| 5031 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5032 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5033 | intel_clock_t *reduced_clock) |
| 5034 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5035 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5036 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5037 | int pipe = crtc->pipe; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5038 | u32 fp, fp2 = 0; |
| 5039 | |
| 5040 | if (IS_PINEVIEW(dev)) { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5041 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5042 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5043 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5044 | } else { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5045 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5046 | if (reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 5047 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5048 | } |
| 5049 | |
| 5050 | I915_WRITE(FP0(pipe), fp); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5051 | crtc->config.dpll_hw_state.fp0 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5052 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5053 | crtc->lowfreq_avail = false; |
| 5054 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 5055 | reduced_clock && i915.powersave) { |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5056 | I915_WRITE(FP1(pipe), fp2); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5057 | crtc->config.dpll_hw_state.fp1 = fp2; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5058 | crtc->lowfreq_avail = true; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5059 | } else { |
| 5060 | I915_WRITE(FP1(pipe), fp); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5061 | crtc->config.dpll_hw_state.fp1 = fp; |
Jesse Barnes | a7516a0 | 2011-12-15 12:30:37 -0800 | [diff] [blame] | 5062 | } |
| 5063 | } |
| 5064 | |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 5065 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
| 5066 | pipe) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5067 | { |
| 5068 | u32 reg_val; |
| 5069 | |
| 5070 | /* |
| 5071 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 5072 | * and set it to a reasonable value instead. |
| 5073 | */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5074 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5075 | reg_val &= 0xffffff00; |
| 5076 | reg_val |= 0x00000030; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5077 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5078 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5079 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5080 | reg_val &= 0x8cffffff; |
| 5081 | reg_val = 0x8c000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5082 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5083 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5084 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5085 | reg_val &= 0xffffff00; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5086 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5087 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5088 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5089 | reg_val &= 0x00ffffff; |
| 5090 | reg_val |= 0xb0000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5091 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5092 | } |
| 5093 | |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5094 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
| 5095 | struct intel_link_m_n *m_n) |
| 5096 | { |
| 5097 | struct drm_device *dev = crtc->base.dev; |
| 5098 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5099 | int pipe = crtc->pipe; |
| 5100 | |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 5101 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5102 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); |
| 5103 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); |
| 5104 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5105 | } |
| 5106 | |
| 5107 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
| 5108 | struct intel_link_m_n *m_n) |
| 5109 | { |
| 5110 | struct drm_device *dev = crtc->base.dev; |
| 5111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5112 | int pipe = crtc->pipe; |
| 5113 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
| 5114 | |
| 5115 | if (INTEL_INFO(dev)->gen >= 5) { |
| 5116 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5117 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); |
| 5118 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); |
| 5119 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); |
| 5120 | } else { |
Daniel Vetter | e3b95f1 | 2013-05-03 11:49:49 +0200 | [diff] [blame] | 5121 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 5122 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); |
| 5123 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); |
| 5124 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); |
Daniel Vetter | b551842 | 2013-05-03 11:49:48 +0200 | [diff] [blame] | 5125 | } |
| 5126 | } |
| 5127 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 5128 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
| 5129 | { |
| 5130 | if (crtc->config.has_pch_encoder) |
| 5131 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
| 5132 | else |
| 5133 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); |
| 5134 | } |
| 5135 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5136 | static void vlv_update_pll(struct intel_crtc *crtc) |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5137 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5138 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5139 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5140 | int pipe = crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5141 | u32 dpll, mdiv; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5142 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5143 | u32 coreclk, reg_val, dpll_md; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5144 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 5145 | mutex_lock(&dev_priv->dpio_lock); |
| 5146 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5147 | bestn = crtc->config.dpll.n; |
| 5148 | bestm1 = crtc->config.dpll.m1; |
| 5149 | bestm2 = crtc->config.dpll.m2; |
| 5150 | bestp1 = crtc->config.dpll.p1; |
| 5151 | bestp2 = crtc->config.dpll.p2; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5152 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5153 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 5154 | |
| 5155 | /* PLL B needs special handling */ |
| 5156 | if (pipe) |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 5157 | vlv_pllb_recal_opamp(dev_priv, pipe); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5158 | |
| 5159 | /* Set up Tx target for periodic Rcomp update */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5160 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5161 | |
| 5162 | /* Disable target IRef on PLL */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5163 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5164 | reg_val &= 0x00ffffff; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5165 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5166 | |
| 5167 | /* Disable fast lock */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5168 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5169 | |
| 5170 | /* Set idtafcrecal before PLL is enabled */ |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5171 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
| 5172 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); |
| 5173 | mdiv |= ((bestn << DPIO_N_SHIFT)); |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5174 | mdiv |= (1 << DPIO_K_SHIFT); |
Jesse Barnes | 7df5080 | 2013-05-02 10:48:09 -0700 | [diff] [blame] | 5175 | |
| 5176 | /* |
| 5177 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 5178 | * but we don't support that). |
| 5179 | * Note: don't use the DAC post divider as it seems unstable. |
| 5180 | */ |
| 5181 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5182 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5183 | |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5184 | mdiv |= DPIO_ENABLE_CALIBRATION; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5185 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5186 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5187 | /* Set HBR and RBR LPF coefficients */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 5188 | if (crtc->config.port_clock == 162000 || |
Ville Syrjälä | 99750bd | 2013-06-14 14:02:52 +0300 | [diff] [blame] | 5189 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5190 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5191 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Ville Syrjälä | 885b012 | 2013-07-05 19:21:38 +0300 | [diff] [blame] | 5192 | 0x009f0003); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5193 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5194 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5195 | 0x00d0000f); |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5196 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5197 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || |
| 5198 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { |
| 5199 | /* Use SSC source */ |
| 5200 | if (!pipe) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5201 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5202 | 0x0df40000); |
| 5203 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5204 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5205 | 0x0df70000); |
| 5206 | } else { /* HDMI or VGA */ |
| 5207 | /* Use bend source */ |
| 5208 | if (!pipe) |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5209 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5210 | 0x0df70000); |
| 5211 | else |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5212 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5213 | 0x0df40000); |
| 5214 | } |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5215 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5216 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5217 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
| 5218 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || |
| 5219 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) |
| 5220 | coreclk |= 0x01000000; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5221 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5222 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5223 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5224 | |
Imre Deak | e5cbfbf | 2014-01-09 17:08:16 +0200 | [diff] [blame] | 5225 | /* |
| 5226 | * Enable DPIO clock input. We should never disable the reference |
| 5227 | * clock for pipe B, since VGA hotplug / manual detection depends |
| 5228 | * on it. |
| 5229 | */ |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5230 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
| 5231 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
Jesse Barnes | f607116 | 2013-10-01 10:41:38 -0700 | [diff] [blame] | 5232 | /* We should never disable this, set it here for state tracking */ |
| 5233 | if (pipe == PIPE_B) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5234 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5235 | dpll |= DPLL_VCO_ENABLE; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5236 | crtc->config.dpll_hw_state.dpll = dpll; |
| 5237 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 5238 | dpll_md = (crtc->config.pixel_multiplier - 1) |
| 5239 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5240 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
| 5241 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5242 | if (crtc->config.has_dp_encoder) |
| 5243 | intel_dp_set_m_n(crtc); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5244 | |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 5245 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | a0c4da2 | 2012-06-15 11:55:13 -0700 | [diff] [blame] | 5246 | } |
| 5247 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5248 | static void i9xx_update_pll(struct intel_crtc *crtc, |
| 5249 | intel_clock_t *reduced_clock, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5250 | int num_connectors) |
| 5251 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5252 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5253 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5254 | u32 dpll; |
| 5255 | bool is_sdvo; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5256 | struct dpll *clock = &crtc->config.dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5257 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5258 | i9xx_update_pll_dividers(crtc, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5259 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5260 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
| 5261 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5262 | |
| 5263 | dpll = DPLL_VGA_MODE_DIS; |
| 5264 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5265 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5266 | dpll |= DPLLB_MODE_LVDS; |
| 5267 | else |
| 5268 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 5269 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 5270 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5271 | dpll |= (crtc->config.pixel_multiplier - 1) |
| 5272 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5273 | } |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5274 | |
| 5275 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5276 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 5277 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5278 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5279 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5280 | |
| 5281 | /* compute bitmask from p1 value */ |
| 5282 | if (IS_PINEVIEW(dev)) |
| 5283 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
| 5284 | else { |
| 5285 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5286 | if (IS_G4X(dev) && reduced_clock) |
| 5287 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
| 5288 | } |
| 5289 | switch (clock->p2) { |
| 5290 | case 5: |
| 5291 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 5292 | break; |
| 5293 | case 7: |
| 5294 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 5295 | break; |
| 5296 | case 10: |
| 5297 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 5298 | break; |
| 5299 | case 14: |
| 5300 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 5301 | break; |
| 5302 | } |
| 5303 | if (INTEL_INFO(dev)->gen >= 4) |
| 5304 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
| 5305 | |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 5306 | if (crtc->config.sdvo_tv_clock) |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5307 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5308 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5309 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 5310 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5311 | else |
| 5312 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5313 | |
| 5314 | dpll |= DPLL_VCO_ENABLE; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5315 | crtc->config.dpll_hw_state.dpll = dpll; |
| 5316 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5317 | if (INTEL_INFO(dev)->gen >= 4) { |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 5318 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
| 5319 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5320 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5321 | } |
Daniel Vetter | 66e3d5c | 2013-06-16 21:24:16 +0200 | [diff] [blame] | 5322 | |
| 5323 | if (crtc->config.has_dp_encoder) |
| 5324 | intel_dp_set_m_n(crtc); |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5325 | } |
| 5326 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5327 | static void i8xx_update_pll(struct intel_crtc *crtc, |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5328 | intel_clock_t *reduced_clock, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5329 | int num_connectors) |
| 5330 | { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5331 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5332 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5333 | u32 dpll; |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5334 | struct dpll *clock = &crtc->config.dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5335 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5336 | i9xx_update_pll_dividers(crtc, reduced_clock); |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5337 | |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5338 | dpll = DPLL_VGA_MODE_DIS; |
| 5339 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5340 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5341 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5342 | } else { |
| 5343 | if (clock->p1 == 2) |
| 5344 | dpll |= PLL_P1_DIVIDE_BY_TWO; |
| 5345 | else |
| 5346 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
| 5347 | if (clock->p2 == 4) |
| 5348 | dpll |= PLL_P2_DIVIDE_BY_4; |
| 5349 | } |
| 5350 | |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 5351 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
| 5352 | dpll |= DPLL_DVO_2X_MODE; |
| 5353 | |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5354 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5355 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
| 5356 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
| 5357 | else |
| 5358 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 5359 | |
| 5360 | dpll |= DPLL_VCO_ENABLE; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5361 | crtc->config.dpll_hw_state.dpll = dpll; |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5362 | } |
| 5363 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5364 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5365 | { |
| 5366 | struct drm_device *dev = intel_crtc->base.dev; |
| 5367 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5368 | enum pipe pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 5369 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5370 | struct drm_display_mode *adjusted_mode = |
| 5371 | &intel_crtc->config.adjusted_mode; |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5372 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
| 5373 | |
| 5374 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 5375 | * the hw state checker will get angry at the mismatch. */ |
| 5376 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 5377 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5378 | |
| 5379 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 5380 | /* the chip adds 2 halflines automatically */ |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5381 | crtc_vtotal -= 1; |
| 5382 | crtc_vblank_end -= 1; |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5383 | vsyncshift = adjusted_mode->crtc_hsync_start |
| 5384 | - adjusted_mode->crtc_htotal / 2; |
| 5385 | } else { |
| 5386 | vsyncshift = 0; |
| 5387 | } |
| 5388 | |
| 5389 | if (INTEL_INFO(dev)->gen > 3) |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5390 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5391 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5392 | I915_WRITE(HTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5393 | (adjusted_mode->crtc_hdisplay - 1) | |
| 5394 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5395 | I915_WRITE(HBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5396 | (adjusted_mode->crtc_hblank_start - 1) | |
| 5397 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5398 | I915_WRITE(HSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5399 | (adjusted_mode->crtc_hsync_start - 1) | |
| 5400 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 5401 | |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5402 | I915_WRITE(VTOTAL(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5403 | (adjusted_mode->crtc_vdisplay - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5404 | ((crtc_vtotal - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5405 | I915_WRITE(VBLANK(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5406 | (adjusted_mode->crtc_vblank_start - 1) | |
Daniel Vetter | 4d8a62e | 2013-05-03 11:49:51 +0200 | [diff] [blame] | 5407 | ((crtc_vblank_end - 1) << 16)); |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 5408 | I915_WRITE(VSYNC(cpu_transcoder), |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5409 | (adjusted_mode->crtc_vsync_start - 1) | |
| 5410 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 5411 | |
Paulo Zanoni | b5e508d | 2012-10-24 11:34:43 -0200 | [diff] [blame] | 5412 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 5413 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 5414 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 5415 | * bits. */ |
| 5416 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && |
| 5417 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 5418 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); |
| 5419 | |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5420 | /* pipesrc controls the size that is scaled from, which should |
| 5421 | * always be the user's requested size. |
| 5422 | */ |
| 5423 | I915_WRITE(PIPESRC(pipe), |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 5424 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
| 5425 | (intel_crtc->config.pipe_src_h - 1)); |
Paulo Zanoni | b0e77b9 | 2012-10-01 18:10:53 -0300 | [diff] [blame] | 5426 | } |
| 5427 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 5428 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
| 5429 | struct intel_crtc_config *pipe_config) |
| 5430 | { |
| 5431 | struct drm_device *dev = crtc->base.dev; |
| 5432 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5433 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 5434 | uint32_t tmp; |
| 5435 | |
| 5436 | tmp = I915_READ(HTOTAL(cpu_transcoder)); |
| 5437 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 5438 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
| 5439 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
| 5440 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
| 5441 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 5442 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
| 5443 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 5444 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 5445 | |
| 5446 | tmp = I915_READ(VTOTAL(cpu_transcoder)); |
| 5447 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 5448 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
| 5449 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
| 5450 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
| 5451 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; |
| 5452 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
| 5453 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 5454 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 5455 | |
| 5456 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { |
| 5457 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 5458 | pipe_config->adjusted_mode.crtc_vtotal += 1; |
| 5459 | pipe_config->adjusted_mode.crtc_vblank_end += 1; |
| 5460 | } |
| 5461 | |
| 5462 | tmp = I915_READ(PIPESRC(crtc->pipe)); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 5463 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 5464 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 5465 | |
| 5466 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; |
| 5467 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 5468 | } |
| 5469 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 5470 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 5471 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 5472 | { |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 5473 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
| 5474 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; |
| 5475 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; |
| 5476 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 5477 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 5478 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
| 5479 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; |
| 5480 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; |
| 5481 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 5482 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 5483 | mode->flags = pipe_config->adjusted_mode.flags; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 5484 | |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 5485 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
| 5486 | mode->flags |= pipe_config->adjusted_mode.flags; |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 5487 | } |
| 5488 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5489 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
| 5490 | { |
| 5491 | struct drm_device *dev = intel_crtc->base.dev; |
| 5492 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5493 | uint32_t pipeconf; |
| 5494 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 5495 | pipeconf = 0; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5496 | |
Daniel Vetter | 67c72a1 | 2013-09-24 11:46:14 +0200 | [diff] [blame] | 5497 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 5498 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) |
| 5499 | pipeconf |= PIPECONF_ENABLE; |
| 5500 | |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 5501 | if (intel_crtc->config.double_wide) |
| 5502 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5503 | |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 5504 | /* only g4x and later have fancy bpc/dither controls */ |
| 5505 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
Daniel Vetter | ff9ce46 | 2013-04-24 14:57:17 +0200 | [diff] [blame] | 5506 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
| 5507 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) |
| 5508 | pipeconf |= PIPECONF_DITHER_EN | |
| 5509 | PIPECONF_DITHER_TYPE_SP; |
| 5510 | |
| 5511 | switch (intel_crtc->config.pipe_bpp) { |
| 5512 | case 18: |
| 5513 | pipeconf |= PIPECONF_6BPC; |
| 5514 | break; |
| 5515 | case 24: |
| 5516 | pipeconf |= PIPECONF_8BPC; |
| 5517 | break; |
| 5518 | case 30: |
| 5519 | pipeconf |= PIPECONF_10BPC; |
| 5520 | break; |
| 5521 | default: |
| 5522 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 5523 | BUG(); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5524 | } |
| 5525 | } |
| 5526 | |
| 5527 | if (HAS_PIPE_CXSR(dev)) { |
| 5528 | if (intel_crtc->lowfreq_avail) { |
| 5529 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
| 5530 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
| 5531 | } else { |
| 5532 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5533 | } |
| 5534 | } |
| 5535 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5536 | if (!IS_GEN2(dev) && |
| 5537 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
| 5538 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
| 5539 | else |
| 5540 | pipeconf |= PIPECONF_PROGRESSIVE; |
| 5541 | |
Daniel Vetter | 9f11a9e | 2013-06-13 00:54:58 +0200 | [diff] [blame] | 5542 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
| 5543 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 9c8e09b | 2013-04-02 16:10:09 +0300 | [diff] [blame] | 5544 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5545 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
| 5546 | POSTING_READ(PIPECONF(intel_crtc->pipe)); |
| 5547 | } |
| 5548 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5549 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5550 | int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 5551 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5552 | { |
| 5553 | struct drm_device *dev = crtc->dev; |
| 5554 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 5556 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 5557 | int plane = intel_crtc->plane; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 5558 | int refclk, num_connectors = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 5559 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5560 | u32 dspcntr; |
Daniel Vetter | a16af721 | 2013-04-30 14:01:44 +0200 | [diff] [blame] | 5561 | bool ok, has_reduced_clock = false; |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5562 | bool is_lvds = false, is_dsi = false; |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5563 | struct intel_encoder *encoder; |
Ma Ling | d490609 | 2009-03-18 20:13:27 +0800 | [diff] [blame] | 5564 | const intel_limit_t *limit; |
Chris Wilson | 5c3b82e | 2009-02-11 13:25:09 +0000 | [diff] [blame] | 5565 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5566 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 5567 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 5568 | switch (encoder->type) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5569 | case INTEL_OUTPUT_LVDS: |
| 5570 | is_lvds = true; |
| 5571 | break; |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5572 | case INTEL_OUTPUT_DSI: |
| 5573 | is_dsi = true; |
| 5574 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5575 | } |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 5576 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 5577 | num_connectors++; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5578 | } |
| 5579 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5580 | if (is_dsi) |
| 5581 | goto skip_dpll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 5582 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5583 | if (!intel_crtc->config.clock_set) { |
| 5584 | refclk = i9xx_get_refclk(crtc, num_connectors); |
| 5585 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5586 | /* |
| 5587 | * Returns a set of divisors for the desired target clock with |
| 5588 | * the given refclk, or FALSE. The returned values represent |
| 5589 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + |
| 5590 | * 2) / p1 / p2. |
| 5591 | */ |
| 5592 | limit = intel_limit(crtc, refclk); |
| 5593 | ok = dev_priv->display.find_dpll(limit, crtc, |
| 5594 | intel_crtc->config.port_clock, |
| 5595 | refclk, NULL, &clock); |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5596 | if (!ok) { |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5597 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 5598 | return -EINVAL; |
| 5599 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5600 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5601 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 5602 | /* |
| 5603 | * Ensure we match the reduced clock's P to the target |
| 5604 | * clock. If the clocks don't match, we can't switch |
| 5605 | * the display clock by using the FP0/FP1. In such case |
| 5606 | * we will disable the LVDS downclock feature. |
| 5607 | */ |
| 5608 | has_reduced_clock = |
| 5609 | dev_priv->display.find_dpll(limit, crtc, |
| 5610 | dev_priv->lvds_downclock, |
| 5611 | refclk, &clock, |
| 5612 | &reduced_clock); |
| 5613 | } |
| 5614 | /* Compat-code for transition, will disappear. */ |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5615 | intel_crtc->config.dpll.n = clock.n; |
| 5616 | intel_crtc->config.dpll.m1 = clock.m1; |
| 5617 | intel_crtc->config.dpll.m2 = clock.m2; |
| 5618 | intel_crtc->config.dpll.p1 = clock.p1; |
| 5619 | intel_crtc->config.dpll.p2 = clock.p2; |
| 5620 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5621 | |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5622 | if (IS_GEN2(dev)) { |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5623 | i8xx_update_pll(intel_crtc, |
Vijay Purushothaman | 2a8f64c | 2012-09-27 19:13:06 +0530 | [diff] [blame] | 5624 | has_reduced_clock ? &reduced_clock : NULL, |
| 5625 | num_connectors); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5626 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5627 | vlv_update_pll(intel_crtc); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5628 | } else { |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 5629 | i9xx_update_pll(intel_crtc, |
Daniel Vetter | eb1cbe4 | 2012-03-28 23:12:16 +0200 | [diff] [blame] | 5630 | has_reduced_clock ? &reduced_clock : NULL, |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 5631 | num_connectors); |
Jani Nikula | e9fd1c0 | 2013-08-27 15:12:23 +0300 | [diff] [blame] | 5632 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5633 | |
Jani Nikula | f233533 | 2013-09-13 11:03:09 +0300 | [diff] [blame] | 5634 | skip_dpll: |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5635 | /* Set up the display plane register */ |
| 5636 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 5637 | |
Jesse Barnes | da6ecc5 | 2013-03-08 10:46:00 -0800 | [diff] [blame] | 5638 | if (!IS_VALLEYVIEW(dev)) { |
| 5639 | if (pipe == 0) |
| 5640 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
| 5641 | else |
| 5642 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 5643 | } |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5644 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 5645 | intel_set_pipe_timings(intel_crtc); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5646 | |
| 5647 | /* pipesrc and dspsize control the size that is scaled from, |
| 5648 | * which should always be the user's requested size. |
| 5649 | */ |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5650 | I915_WRITE(DSPSIZE(plane), |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 5651 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
| 5652 | (intel_crtc->config.pipe_src_w - 1)); |
Eric Anholt | 929c77f | 2011-03-30 13:01:04 -0700 | [diff] [blame] | 5653 | I915_WRITE(DSPPOS(plane), 0); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5654 | |
Daniel Vetter | 84b046f | 2013-02-19 18:48:54 +0100 | [diff] [blame] | 5655 | i9xx_set_pipeconf(intel_crtc); |
| 5656 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5657 | I915_WRITE(DSPCNTR(plane), dspcntr); |
| 5658 | POSTING_READ(DSPCNTR(plane)); |
| 5659 | |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 5660 | ret = intel_pipe_set_base(crtc, x, y, fb); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5661 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 5662 | return ret; |
| 5663 | } |
| 5664 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5665 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
| 5666 | struct intel_crtc_config *pipe_config) |
| 5667 | { |
| 5668 | struct drm_device *dev = crtc->base.dev; |
| 5669 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5670 | uint32_t tmp; |
| 5671 | |
Ville Syrjälä | dc9e7dec | 2014-01-10 14:06:45 +0200 | [diff] [blame] | 5672 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
| 5673 | return; |
| 5674 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5675 | tmp = I915_READ(PFIT_CONTROL); |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 5676 | if (!(tmp & PFIT_ENABLE)) |
| 5677 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5678 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 5679 | /* Check whether the pfit is attached to our pipe. */ |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5680 | if (INTEL_INFO(dev)->gen < 4) { |
| 5681 | if (crtc->pipe != PIPE_B) |
| 5682 | return; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5683 | } else { |
| 5684 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) |
| 5685 | return; |
| 5686 | } |
| 5687 | |
Daniel Vetter | 0692282 | 2013-07-11 13:35:40 +0200 | [diff] [blame] | 5688 | pipe_config->gmch_pfit.control = tmp; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5689 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
| 5690 | if (INTEL_INFO(dev)->gen < 5) |
| 5691 | pipe_config->gmch_pfit.lvds_border_bits = |
| 5692 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
| 5693 | } |
| 5694 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5695 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
| 5696 | struct intel_crtc_config *pipe_config) |
| 5697 | { |
| 5698 | struct drm_device *dev = crtc->base.dev; |
| 5699 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5700 | int pipe = pipe_config->cpu_transcoder; |
| 5701 | intel_clock_t clock; |
| 5702 | u32 mdiv; |
Chris Wilson | 662c6ec | 2013-09-25 14:24:01 -0700 | [diff] [blame] | 5703 | int refclk = 100000; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5704 | |
| 5705 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 5706 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5707 | mutex_unlock(&dev_priv->dpio_lock); |
| 5708 | |
| 5709 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
| 5710 | clock.m2 = mdiv & DPIO_M2DIV_MASK; |
| 5711 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
| 5712 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
| 5713 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
| 5714 | |
Ville Syrjälä | f646628 | 2013-10-14 14:50:31 +0300 | [diff] [blame] | 5715 | vlv_clock(refclk, &clock); |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5716 | |
Ville Syrjälä | f646628 | 2013-10-14 14:50:31 +0300 | [diff] [blame] | 5717 | /* clock.dot is the fast clock */ |
| 5718 | pipe_config->port_clock = clock.dot / 5; |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5719 | } |
| 5720 | |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5721 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
| 5722 | struct intel_plane_config *plane_config) |
| 5723 | { |
| 5724 | struct drm_device *dev = crtc->base.dev; |
| 5725 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5726 | u32 val, base, offset; |
| 5727 | int pipe = crtc->pipe, plane = crtc->plane; |
| 5728 | int fourcc, pixel_format; |
| 5729 | int aligned_height; |
| 5730 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5731 | crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
| 5732 | if (!crtc->base.fb) { |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5733 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 5734 | return; |
| 5735 | } |
| 5736 | |
| 5737 | val = I915_READ(DSPCNTR(plane)); |
| 5738 | |
| 5739 | if (INTEL_INFO(dev)->gen >= 4) |
| 5740 | if (val & DISPPLANE_TILED) |
| 5741 | plane_config->tiled = true; |
| 5742 | |
| 5743 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 5744 | fourcc = intel_format_to_fourcc(pixel_format); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5745 | crtc->base.fb->pixel_format = fourcc; |
| 5746 | crtc->base.fb->bits_per_pixel = |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5747 | drm_format_plane_cpp(fourcc, 0) * 8; |
| 5748 | |
| 5749 | if (INTEL_INFO(dev)->gen >= 4) { |
| 5750 | if (plane_config->tiled) |
| 5751 | offset = I915_READ(DSPTILEOFF(plane)); |
| 5752 | else |
| 5753 | offset = I915_READ(DSPLINOFF(plane)); |
| 5754 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 5755 | } else { |
| 5756 | base = I915_READ(DSPADDR(plane)); |
| 5757 | } |
| 5758 | plane_config->base = base; |
| 5759 | |
| 5760 | val = I915_READ(PIPESRC(pipe)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5761 | crtc->base.fb->width = ((val >> 16) & 0xfff) + 1; |
| 5762 | crtc->base.fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5763 | |
| 5764 | val = I915_READ(DSPSTRIDE(pipe)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5765 | crtc->base.fb->pitches[0] = val & 0xffffff80; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5766 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5767 | aligned_height = intel_align_height(dev, crtc->base.fb->height, |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5768 | plane_config->tiled); |
| 5769 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5770 | plane_config->size = ALIGN(crtc->base.fb->pitches[0] * |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5771 | aligned_height, PAGE_SIZE); |
| 5772 | |
| 5773 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 5774 | pipe, plane, crtc->base.fb->width, |
| 5775 | crtc->base.fb->height, |
| 5776 | crtc->base.fb->bits_per_pixel, base, |
| 5777 | crtc->base.fb->pitches[0], |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 5778 | plane_config->size); |
| 5779 | |
| 5780 | } |
| 5781 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 5782 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
| 5783 | struct intel_crtc_config *pipe_config) |
| 5784 | { |
| 5785 | struct drm_device *dev = crtc->base.dev; |
| 5786 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5787 | uint32_t tmp; |
| 5788 | |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 5789 | if (!intel_display_power_enabled(dev_priv, |
| 5790 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 5791 | return false; |
| 5792 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 5793 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 5794 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 5795 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 5796 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 5797 | if (!(tmp & PIPECONF_ENABLE)) |
| 5798 | return false; |
| 5799 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 5800 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
| 5801 | switch (tmp & PIPECONF_BPC_MASK) { |
| 5802 | case PIPECONF_6BPC: |
| 5803 | pipe_config->pipe_bpp = 18; |
| 5804 | break; |
| 5805 | case PIPECONF_8BPC: |
| 5806 | pipe_config->pipe_bpp = 24; |
| 5807 | break; |
| 5808 | case PIPECONF_10BPC: |
| 5809 | pipe_config->pipe_bpp = 30; |
| 5810 | break; |
| 5811 | default: |
| 5812 | break; |
| 5813 | } |
| 5814 | } |
| 5815 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 5816 | if (INTEL_INFO(dev)->gen < 4) |
| 5817 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
| 5818 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 5819 | intel_get_pipe_timings(crtc, pipe_config); |
| 5820 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 5821 | i9xx_get_pfit_config(crtc, pipe_config); |
| 5822 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 5823 | if (INTEL_INFO(dev)->gen >= 4) { |
| 5824 | tmp = I915_READ(DPLL_MD(crtc->pipe)); |
| 5825 | pipe_config->pixel_multiplier = |
| 5826 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) |
| 5827 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5828 | pipe_config->dpll_hw_state.dpll_md = tmp; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 5829 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 5830 | tmp = I915_READ(DPLL(crtc->pipe)); |
| 5831 | pipe_config->pixel_multiplier = |
| 5832 | ((tmp & SDVO_MULTIPLIER_MASK) |
| 5833 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; |
| 5834 | } else { |
| 5835 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 5836 | * port and will be fixed up in the encoder->get_config |
| 5837 | * function. */ |
| 5838 | pipe_config->pixel_multiplier = 1; |
| 5839 | } |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5840 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
| 5841 | if (!IS_VALLEYVIEW(dev)) { |
| 5842 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
| 5843 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); |
Ville Syrjälä | 165e901 | 2013-06-26 17:44:15 +0300 | [diff] [blame] | 5844 | } else { |
| 5845 | /* Mask out read-only status bits. */ |
| 5846 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | |
| 5847 | DPLL_PORTC_READY_MASK | |
| 5848 | DPLL_PORTB_READY_MASK); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 5849 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 5850 | |
Jesse Barnes | acbec81 | 2013-09-20 11:29:32 -0700 | [diff] [blame] | 5851 | if (IS_VALLEYVIEW(dev)) |
| 5852 | vlv_crtc_clock_get(crtc, pipe_config); |
| 5853 | else |
| 5854 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 5855 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 5856 | return true; |
| 5857 | } |
| 5858 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 5859 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5860 | { |
| 5861 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5862 | struct drm_mode_config *mode_config = &dev->mode_config; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5863 | struct intel_encoder *encoder; |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5864 | u32 val, final; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5865 | bool has_lvds = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5866 | bool has_cpu_edp = false; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5867 | bool has_panel = false; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5868 | bool has_ck505 = false; |
| 5869 | bool can_ssc = false; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5870 | |
| 5871 | /* We need to take the global config into account */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5872 | list_for_each_entry(encoder, &mode_config->encoder_list, |
| 5873 | base.head) { |
| 5874 | switch (encoder->type) { |
| 5875 | case INTEL_OUTPUT_LVDS: |
| 5876 | has_panel = true; |
| 5877 | has_lvds = true; |
| 5878 | break; |
| 5879 | case INTEL_OUTPUT_EDP: |
| 5880 | has_panel = true; |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 5881 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5882 | has_cpu_edp = true; |
| 5883 | break; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5884 | } |
| 5885 | } |
| 5886 | |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5887 | if (HAS_PCH_IBX(dev)) { |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5888 | has_ck505 = dev_priv->vbt.display_clock_mode; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5889 | can_ssc = has_ck505; |
| 5890 | } else { |
| 5891 | has_ck505 = false; |
| 5892 | can_ssc = true; |
| 5893 | } |
| 5894 | |
Imre Deak | 2de6905 | 2013-05-08 13:14:04 +0300 | [diff] [blame] | 5895 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
| 5896 | has_panel, has_lvds, has_ck505); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5897 | |
| 5898 | /* Ironlake: try to setup display ref clock before DPLL |
| 5899 | * enabling. This is only under driver's control after |
| 5900 | * PCH B stepping, previous chipset stepping should be |
| 5901 | * ignoring this setting. |
| 5902 | */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5903 | val = I915_READ(PCH_DREF_CONTROL); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5904 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5905 | /* As we must carefully and slowly disable/enable each source in turn, |
| 5906 | * compute the final state we want first and check if we need to |
| 5907 | * make any changes at all. |
| 5908 | */ |
| 5909 | final = val; |
| 5910 | final &= ~DREF_NONSPREAD_SOURCE_MASK; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5911 | if (has_ck505) |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5912 | final |= DREF_NONSPREAD_CK505_ENABLE; |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5913 | else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5914 | final |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 5915 | |
| 5916 | final &= ~DREF_SSC_SOURCE_MASK; |
| 5917 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
| 5918 | final &= ~DREF_SSC1_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5919 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5920 | if (has_panel) { |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5921 | final |= DREF_SSC_SOURCE_ENABLE; |
| 5922 | |
| 5923 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 5924 | final |= DREF_SSC1_ENABLE; |
| 5925 | |
| 5926 | if (has_cpu_edp) { |
| 5927 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 5928 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
| 5929 | else |
| 5930 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
| 5931 | } else |
| 5932 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 5933 | } else { |
| 5934 | final |= DREF_SSC_SOURCE_DISABLE; |
| 5935 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
| 5936 | } |
| 5937 | |
| 5938 | if (final == val) |
| 5939 | return; |
| 5940 | |
| 5941 | /* Always enable nonspread source */ |
| 5942 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
| 5943 | |
| 5944 | if (has_ck505) |
| 5945 | val |= DREF_NONSPREAD_CK505_ENABLE; |
| 5946 | else |
| 5947 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
| 5948 | |
| 5949 | if (has_panel) { |
| 5950 | val &= ~DREF_SSC_SOURCE_MASK; |
| 5951 | val |= DREF_SSC_SOURCE_ENABLE; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5952 | |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5953 | /* SSC must be turned on before enabling the CPU output */ |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5954 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5955 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5956 | val |= DREF_SSC1_ENABLE; |
Daniel Vetter | e77166b | 2012-03-30 22:14:05 +0200 | [diff] [blame] | 5957 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5958 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5959 | |
| 5960 | /* Get SSC going before enabling the outputs */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5961 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5962 | POSTING_READ(PCH_DREF_CONTROL); |
| 5963 | udelay(200); |
| 5964 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5965 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5966 | |
| 5967 | /* Enable CPU source on CPU attached eDP */ |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5968 | if (has_cpu_edp) { |
Keith Packard | 99eb6a0 | 2011-09-26 14:29:12 -0700 | [diff] [blame] | 5969 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5970 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5971 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5972 | } |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 5973 | else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5974 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5975 | } else |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5976 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5977 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5978 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5979 | POSTING_READ(PCH_DREF_CONTROL); |
| 5980 | udelay(200); |
| 5981 | } else { |
| 5982 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); |
| 5983 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5984 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5985 | |
| 5986 | /* Turn off CPU output */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5987 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5988 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5989 | I915_WRITE(PCH_DREF_CONTROL, val); |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5990 | POSTING_READ(PCH_DREF_CONTROL); |
| 5991 | udelay(200); |
| 5992 | |
| 5993 | /* Turn off the SSC source */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5994 | val &= ~DREF_SSC_SOURCE_MASK; |
| 5995 | val |= DREF_SSC_SOURCE_DISABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5996 | |
| 5997 | /* Turn off SSC1 */ |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 5998 | val &= ~DREF_SSC1_ENABLE; |
Keith Packard | 199e5d7 | 2011-09-22 12:01:57 -0700 | [diff] [blame] | 5999 | |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6000 | I915_WRITE(PCH_DREF_CONTROL, val); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6001 | POSTING_READ(PCH_DREF_CONTROL); |
| 6002 | udelay(200); |
| 6003 | } |
Chris Wilson | 74cfd7a | 2013-03-26 16:33:04 -0700 | [diff] [blame] | 6004 | |
| 6005 | BUG_ON(val != final); |
Jesse Barnes | 13d83a6 | 2011-08-03 12:59:20 -0700 | [diff] [blame] | 6006 | } |
| 6007 | |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6008 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6009 | { |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6010 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6011 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6012 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 6013 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; |
| 6014 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6015 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6016 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
| 6017 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) |
| 6018 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6019 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6020 | tmp = I915_READ(SOUTH_CHICKEN2); |
| 6021 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; |
| 6022 | I915_WRITE(SOUTH_CHICKEN2, tmp); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6023 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6024 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
| 6025 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) |
| 6026 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6027 | } |
| 6028 | |
| 6029 | /* WaMPhyProgramming:hsw */ |
| 6030 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) |
| 6031 | { |
| 6032 | uint32_t tmp; |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6033 | |
| 6034 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 6035 | tmp &= ~(0xFF << 24); |
| 6036 | tmp |= (0x12 << 24); |
| 6037 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 6038 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6039 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 6040 | tmp |= (1 << 11); |
| 6041 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 6042 | |
| 6043 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 6044 | tmp |= (1 << 11); |
| 6045 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 6046 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6047 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 6048 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 6049 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 6050 | |
| 6051 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 6052 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 6053 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 6054 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6055 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 6056 | tmp &= ~(7 << 13); |
| 6057 | tmp |= (5 << 13); |
| 6058 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6059 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6060 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 6061 | tmp &= ~(7 << 13); |
| 6062 | tmp |= (5 << 13); |
| 6063 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6064 | |
| 6065 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 6066 | tmp &= ~0xFF; |
| 6067 | tmp |= 0x1C; |
| 6068 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 6069 | |
| 6070 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 6071 | tmp &= ~0xFF; |
| 6072 | tmp |= 0x1C; |
| 6073 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 6074 | |
| 6075 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 6076 | tmp &= ~(0xFF << 16); |
| 6077 | tmp |= (0x1C << 16); |
| 6078 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 6079 | |
| 6080 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 6081 | tmp &= ~(0xFF << 16); |
| 6082 | tmp |= (0x1C << 16); |
| 6083 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 6084 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6085 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 6086 | tmp |= (1 << 27); |
| 6087 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6088 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6089 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 6090 | tmp |= (1 << 27); |
| 6091 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6092 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6093 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 6094 | tmp &= ~(0xF << 28); |
| 6095 | tmp |= (4 << 28); |
| 6096 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6097 | |
Paulo Zanoni | 0ff066a | 2013-07-12 14:19:36 -0300 | [diff] [blame] | 6098 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 6099 | tmp &= ~(0xF << 28); |
| 6100 | tmp |= (4 << 28); |
| 6101 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6102 | } |
| 6103 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6104 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 6105 | * Programming" based on the parameters passed: |
| 6106 | * - Sequence to enable CLKOUT_DP |
| 6107 | * - Sequence to enable CLKOUT_DP without spread |
| 6108 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 6109 | */ |
| 6110 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, |
| 6111 | bool with_fdi) |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6112 | { |
| 6113 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6114 | uint32_t reg, tmp; |
| 6115 | |
| 6116 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) |
| 6117 | with_spread = true; |
| 6118 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && |
| 6119 | with_fdi, "LP PCH doesn't have FDI\n")) |
| 6120 | with_fdi = false; |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6121 | |
| 6122 | mutex_lock(&dev_priv->dpio_lock); |
| 6123 | |
| 6124 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6125 | tmp &= ~SBI_SSCCTL_DISABLE; |
| 6126 | tmp |= SBI_SSCCTL_PATHALT; |
| 6127 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6128 | |
| 6129 | udelay(24); |
| 6130 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6131 | if (with_spread) { |
| 6132 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6133 | tmp &= ~SBI_SSCCTL_PATHALT; |
| 6134 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
Paulo Zanoni | f31f2d5 | 2013-07-18 18:51:11 -0300 | [diff] [blame] | 6135 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6136 | if (with_fdi) { |
| 6137 | lpt_reset_fdi_mphy(dev_priv); |
| 6138 | lpt_program_fdi_mphy(dev_priv); |
| 6139 | } |
| 6140 | } |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6141 | |
Paulo Zanoni | 2fa86a1 | 2013-07-23 11:19:24 -0300 | [diff] [blame] | 6142 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
| 6143 | SBI_GEN0 : SBI_DBUFF0; |
| 6144 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 6145 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 6146 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
Daniel Vetter | c00db24 | 2013-01-22 15:33:27 +0100 | [diff] [blame] | 6147 | |
| 6148 | mutex_unlock(&dev_priv->dpio_lock); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6149 | } |
| 6150 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 6151 | /* Sequence to disable CLKOUT_DP */ |
| 6152 | static void lpt_disable_clkout_dp(struct drm_device *dev) |
| 6153 | { |
| 6154 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6155 | uint32_t reg, tmp; |
| 6156 | |
| 6157 | mutex_lock(&dev_priv->dpio_lock); |
| 6158 | |
| 6159 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
| 6160 | SBI_GEN0 : SBI_DBUFF0; |
| 6161 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 6162 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; |
| 6163 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 6164 | |
| 6165 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); |
| 6166 | if (!(tmp & SBI_SSCCTL_DISABLE)) { |
| 6167 | if (!(tmp & SBI_SSCCTL_PATHALT)) { |
| 6168 | tmp |= SBI_SSCCTL_PATHALT; |
| 6169 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6170 | udelay(32); |
| 6171 | } |
| 6172 | tmp |= SBI_SSCCTL_DISABLE; |
| 6173 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); |
| 6174 | } |
| 6175 | |
| 6176 | mutex_unlock(&dev_priv->dpio_lock); |
| 6177 | } |
| 6178 | |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6179 | static void lpt_init_pch_refclk(struct drm_device *dev) |
| 6180 | { |
| 6181 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 6182 | struct intel_encoder *encoder; |
| 6183 | bool has_vga = false; |
| 6184 | |
| 6185 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
| 6186 | switch (encoder->type) { |
| 6187 | case INTEL_OUTPUT_ANALOG: |
| 6188 | has_vga = true; |
| 6189 | break; |
| 6190 | } |
| 6191 | } |
| 6192 | |
Paulo Zanoni | 47701c3 | 2013-07-23 11:19:25 -0300 | [diff] [blame] | 6193 | if (has_vga) |
| 6194 | lpt_enable_clkout_dp(dev, true, true); |
| 6195 | else |
| 6196 | lpt_disable_clkout_dp(dev); |
Paulo Zanoni | bf8fa3d | 2013-07-12 14:19:38 -0300 | [diff] [blame] | 6197 | } |
| 6198 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 6199 | /* |
| 6200 | * Initialize reference clocks when the driver loads |
| 6201 | */ |
| 6202 | void intel_init_pch_refclk(struct drm_device *dev) |
| 6203 | { |
| 6204 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 6205 | ironlake_init_pch_refclk(dev); |
| 6206 | else if (HAS_PCH_LPT(dev)) |
| 6207 | lpt_init_pch_refclk(dev); |
| 6208 | } |
| 6209 | |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6210 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
| 6211 | { |
| 6212 | struct drm_device *dev = crtc->dev; |
| 6213 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6214 | struct intel_encoder *encoder; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6215 | int num_connectors = 0; |
| 6216 | bool is_lvds = false; |
| 6217 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 6218 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6219 | switch (encoder->type) { |
| 6220 | case INTEL_OUTPUT_LVDS: |
| 6221 | is_lvds = true; |
| 6222 | break; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6223 | } |
| 6224 | num_connectors++; |
| 6225 | } |
| 6226 | |
| 6227 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 6228 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 6229 | dev_priv->vbt.lvds_ssc_freq); |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 6230 | return dev_priv->vbt.lvds_ssc_freq; |
Jesse Barnes | d9d444c | 2011-09-02 13:03:05 -0700 | [diff] [blame] | 6231 | } |
| 6232 | |
| 6233 | return 120000; |
| 6234 | } |
| 6235 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6236 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6237 | { |
| 6238 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 6239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6240 | int pipe = intel_crtc->pipe; |
| 6241 | uint32_t val; |
| 6242 | |
Daniel Vetter | 7811407 | 2013-06-13 00:54:57 +0200 | [diff] [blame] | 6243 | val = 0; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6244 | |
Daniel Vetter | 965e0c4 | 2013-03-27 00:44:57 +0100 | [diff] [blame] | 6245 | switch (intel_crtc->config.pipe_bpp) { |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6246 | case 18: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6247 | val |= PIPECONF_6BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6248 | break; |
| 6249 | case 24: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6250 | val |= PIPECONF_8BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6251 | break; |
| 6252 | case 30: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6253 | val |= PIPECONF_10BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6254 | break; |
| 6255 | case 36: |
Daniel Vetter | dfd07d7 | 2012-12-17 11:21:38 +0100 | [diff] [blame] | 6256 | val |= PIPECONF_12BPC; |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6257 | break; |
| 6258 | default: |
Paulo Zanoni | cc769b6 | 2012-09-20 18:36:03 -0300 | [diff] [blame] | 6259 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 6260 | BUG(); |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6261 | } |
| 6262 | |
Daniel Vetter | d8b3224 | 2013-04-25 17:54:44 +0200 | [diff] [blame] | 6263 | if (intel_crtc->config.dither) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6264 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 6265 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6266 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6267 | val |= PIPECONF_INTERLACED_ILK; |
| 6268 | else |
| 6269 | val |= PIPECONF_PROGRESSIVE; |
| 6270 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6271 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 6272 | val |= PIPECONF_COLOR_RANGE_SELECT; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 6273 | |
Paulo Zanoni | c820356 | 2012-09-12 10:06:29 -0300 | [diff] [blame] | 6274 | I915_WRITE(PIPECONF(pipe), val); |
| 6275 | POSTING_READ(PIPECONF(pipe)); |
| 6276 | } |
| 6277 | |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6278 | /* |
| 6279 | * Set up the pipe CSC unit. |
| 6280 | * |
| 6281 | * Currently only full range RGB to limited range RGB conversion |
| 6282 | * is supported, but eventually this should handle various |
| 6283 | * RGB<->YCbCr scenarios as well. |
| 6284 | */ |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6285 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6286 | { |
| 6287 | struct drm_device *dev = crtc->dev; |
| 6288 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6289 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6290 | int pipe = intel_crtc->pipe; |
| 6291 | uint16_t coeff = 0x7800; /* 1.0 */ |
| 6292 | |
| 6293 | /* |
| 6294 | * TODO: Check what kind of values actually come out of the pipe |
| 6295 | * with these coeff/postoff values and adjust to get the best |
| 6296 | * accuracy. Perhaps we even need to take the bpc value into |
| 6297 | * consideration. |
| 6298 | */ |
| 6299 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6300 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6301 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
| 6302 | |
| 6303 | /* |
| 6304 | * GY/GU and RY/RU should be the other way around according |
| 6305 | * to BSpec, but reality doesn't agree. Just set them up in |
| 6306 | * a way that results in the correct picture. |
| 6307 | */ |
| 6308 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); |
| 6309 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); |
| 6310 | |
| 6311 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); |
| 6312 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); |
| 6313 | |
| 6314 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); |
| 6315 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); |
| 6316 | |
| 6317 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); |
| 6318 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); |
| 6319 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); |
| 6320 | |
| 6321 | if (INTEL_INFO(dev)->gen > 6) { |
| 6322 | uint16_t postoff = 0; |
| 6323 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6324 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 32cf0cb | 2013-11-28 22:10:38 +0200 | [diff] [blame] | 6325 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6326 | |
| 6327 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
| 6328 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
| 6329 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); |
| 6330 | |
| 6331 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); |
| 6332 | } else { |
| 6333 | uint32_t mode = CSC_MODE_YUV_TO_RGB; |
| 6334 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 6335 | if (intel_crtc->config.limited_color_range) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 6336 | mode |= CSC_BLACK_SCREEN_OFFSET; |
| 6337 | |
| 6338 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); |
| 6339 | } |
| 6340 | } |
| 6341 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6342 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6343 | { |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6344 | struct drm_device *dev = crtc->dev; |
| 6345 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6347 | enum pipe pipe = intel_crtc->pipe; |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 6348 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6349 | uint32_t val; |
| 6350 | |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 6351 | val = 0; |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6352 | |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6353 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6354 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
| 6355 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6356 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6357 | val |= PIPECONF_INTERLACED_ILK; |
| 6358 | else |
| 6359 | val |= PIPECONF_PROGRESSIVE; |
| 6360 | |
Paulo Zanoni | 702e7a5 | 2012-10-23 18:29:59 -0200 | [diff] [blame] | 6361 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
| 6362 | POSTING_READ(PIPECONF(cpu_transcoder)); |
Daniel Vetter | 3eff4fa | 2013-06-13 00:54:59 +0200 | [diff] [blame] | 6363 | |
| 6364 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); |
| 6365 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); |
Paulo Zanoni | 756f85c | 2013-11-02 21:07:38 -0700 | [diff] [blame] | 6366 | |
| 6367 | if (IS_BROADWELL(dev)) { |
| 6368 | val = 0; |
| 6369 | |
| 6370 | switch (intel_crtc->config.pipe_bpp) { |
| 6371 | case 18: |
| 6372 | val |= PIPEMISC_DITHER_6_BPC; |
| 6373 | break; |
| 6374 | case 24: |
| 6375 | val |= PIPEMISC_DITHER_8_BPC; |
| 6376 | break; |
| 6377 | case 30: |
| 6378 | val |= PIPEMISC_DITHER_10_BPC; |
| 6379 | break; |
| 6380 | case 36: |
| 6381 | val |= PIPEMISC_DITHER_12_BPC; |
| 6382 | break; |
| 6383 | default: |
| 6384 | /* Case prevented by pipe_config_set_bpp. */ |
| 6385 | BUG(); |
| 6386 | } |
| 6387 | |
| 6388 | if (intel_crtc->config.dither) |
| 6389 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
| 6390 | |
| 6391 | I915_WRITE(PIPEMISC(pipe), val); |
| 6392 | } |
Paulo Zanoni | ee2b0b3 | 2012-10-05 12:05:57 -0300 | [diff] [blame] | 6393 | } |
| 6394 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6395 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6396 | intel_clock_t *clock, |
| 6397 | bool *has_reduced_clock, |
| 6398 | intel_clock_t *reduced_clock) |
| 6399 | { |
| 6400 | struct drm_device *dev = crtc->dev; |
| 6401 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6402 | struct intel_encoder *intel_encoder; |
| 6403 | int refclk; |
| 6404 | const intel_limit_t *limit; |
Daniel Vetter | a16af721 | 2013-04-30 14:01:44 +0200 | [diff] [blame] | 6405 | bool ret, is_lvds = false; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6406 | |
| 6407 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 6408 | switch (intel_encoder->type) { |
| 6409 | case INTEL_OUTPUT_LVDS: |
| 6410 | is_lvds = true; |
| 6411 | break; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6412 | } |
| 6413 | } |
| 6414 | |
| 6415 | refclk = ironlake_get_refclk(crtc); |
| 6416 | |
| 6417 | /* |
| 6418 | * Returns a set of divisors for the desired target clock with the given |
| 6419 | * refclk, or FALSE. The returned values represent the clock equation: |
| 6420 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 6421 | */ |
| 6422 | limit = intel_limit(crtc, refclk); |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 6423 | ret = dev_priv->display.find_dpll(limit, crtc, |
| 6424 | to_intel_crtc(crtc)->config.port_clock, |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 6425 | refclk, NULL, clock); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6426 | if (!ret) |
| 6427 | return false; |
| 6428 | |
| 6429 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
| 6430 | /* |
| 6431 | * Ensure we match the reduced clock's P to the target clock. |
| 6432 | * If the clocks don't match, we can't switch the display clock |
| 6433 | * by using the FP0/FP1. In such case we will disable the LVDS |
| 6434 | * downclock feature. |
| 6435 | */ |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 6436 | *has_reduced_clock = |
| 6437 | dev_priv->display.find_dpll(limit, crtc, |
| 6438 | dev_priv->lvds_downclock, |
| 6439 | refclk, clock, |
| 6440 | reduced_clock); |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6441 | } |
| 6442 | |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6443 | return true; |
| 6444 | } |
| 6445 | |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 6446 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 6447 | { |
| 6448 | /* |
| 6449 | * Account for spread spectrum to avoid |
| 6450 | * oversubscribing the link. Max center spread |
| 6451 | * is 2.5%; use 5% for safety's sake. |
| 6452 | */ |
| 6453 | u32 bps = target_clock * bpp * 21 / 20; |
Ville Syrjälä | 619d4d0 | 2014-02-27 14:23:14 +0200 | [diff] [blame] | 6454 | return DIV_ROUND_UP(bps, link_bw * 8); |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 6455 | } |
| 6456 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6457 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
Daniel Vetter | 6cf86a5 | 2013-04-02 23:38:10 +0200 | [diff] [blame] | 6458 | { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6459 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 6460 | } |
| 6461 | |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6462 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6463 | u32 *fp, |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 6464 | intel_clock_t *reduced_clock, u32 *fp2) |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6465 | { |
| 6466 | struct drm_crtc *crtc = &intel_crtc->base; |
| 6467 | struct drm_device *dev = crtc->dev; |
| 6468 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6469 | struct intel_encoder *intel_encoder; |
| 6470 | uint32_t dpll; |
Daniel Vetter | 6cc5f34 | 2013-03-27 00:44:53 +0100 | [diff] [blame] | 6471 | int factor, num_connectors = 0; |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 6472 | bool is_lvds = false, is_sdvo = false; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6473 | |
| 6474 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 6475 | switch (intel_encoder->type) { |
| 6476 | case INTEL_OUTPUT_LVDS: |
| 6477 | is_lvds = true; |
| 6478 | break; |
| 6479 | case INTEL_OUTPUT_SDVO: |
| 6480 | case INTEL_OUTPUT_HDMI: |
| 6481 | is_sdvo = true; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6482 | break; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6483 | } |
| 6484 | |
| 6485 | num_connectors++; |
| 6486 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6487 | |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 6488 | /* Enable autotuning of the PLL clock (if permissible) */ |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6489 | factor = 21; |
| 6490 | if (is_lvds) { |
| 6491 | if ((intel_panel_use_ssc(dev_priv) && |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 6492 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
Daniel Vetter | f0b4405 | 2013-04-04 22:20:33 +0200 | [diff] [blame] | 6493 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6494 | factor = 25; |
Daniel Vetter | 09ede54 | 2013-04-30 14:01:45 +0200 | [diff] [blame] | 6495 | } else if (intel_crtc->config.sdvo_tv_clock) |
Eric Anholt | 8febb29 | 2011-03-30 13:01:07 -0700 | [diff] [blame] | 6496 | factor = 20; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 6497 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6498 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
Daniel Vetter | 7d0ac5b | 2013-04-04 22:20:32 +0200 | [diff] [blame] | 6499 | *fp |= FP_CB_TUNE; |
Chris Wilson | c185812 | 2010-12-03 21:35:48 +0000 | [diff] [blame] | 6500 | |
Daniel Vetter | 9a7c789 | 2013-04-04 22:20:34 +0200 | [diff] [blame] | 6501 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
| 6502 | *fp2 |= FP_CB_TUNE; |
| 6503 | |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6504 | dpll = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 6505 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 6506 | if (is_lvds) |
| 6507 | dpll |= DPLLB_MODE_LVDS; |
| 6508 | else |
| 6509 | dpll |= DPLLB_MODE_DAC_SERIAL; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 6510 | |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 6511 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
| 6512 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
Daniel Vetter | 198a037f | 2013-04-19 11:14:37 +0200 | [diff] [blame] | 6513 | |
| 6514 | if (is_sdvo) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 6515 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Daniel Vetter | 9566e9a | 2013-04-19 11:14:36 +0200 | [diff] [blame] | 6516 | if (intel_crtc->config.has_dp_encoder) |
Daniel Vetter | 4a33e48 | 2013-07-06 12:52:05 +0200 | [diff] [blame] | 6517 | dpll |= DPLL_SDVO_HIGH_SPEED; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6518 | |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 6519 | /* compute bitmask from p1 value */ |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6520 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 6521 | /* also FPA1 */ |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6522 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 6523 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6524 | switch (intel_crtc->config.dpll.p2) { |
Eric Anholt | a07d678 | 2011-03-30 13:01:08 -0700 | [diff] [blame] | 6525 | case 5: |
| 6526 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; |
| 6527 | break; |
| 6528 | case 7: |
| 6529 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; |
| 6530 | break; |
| 6531 | case 10: |
| 6532 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; |
| 6533 | break; |
| 6534 | case 14: |
| 6535 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; |
| 6536 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6537 | } |
| 6538 | |
Daniel Vetter | b4c09f3 | 2013-04-30 14:01:42 +0200 | [diff] [blame] | 6539 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
Kristian Høgsberg | 43565a0 | 2009-02-13 20:56:52 -0500 | [diff] [blame] | 6540 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6541 | else |
| 6542 | dpll |= PLL_REF_INPUT_DREFCLK; |
| 6543 | |
Daniel Vetter | 959e16d | 2013-06-05 13:34:21 +0200 | [diff] [blame] | 6544 | return dpll | DPLL_VCO_ENABLE; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6545 | } |
| 6546 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6547 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6548 | int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 6549 | struct drm_framebuffer *fb) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6550 | { |
| 6551 | struct drm_device *dev = crtc->dev; |
| 6552 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 6554 | int pipe = intel_crtc->pipe; |
| 6555 | int plane = intel_crtc->plane; |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6556 | int num_connectors = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6557 | intel_clock_t clock, reduced_clock; |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 6558 | u32 dpll = 0, fp = 0, fp2 = 0; |
Paulo Zanoni | e2f12b0 | 2012-09-20 18:36:06 -0300 | [diff] [blame] | 6559 | bool ok, has_reduced_clock = false; |
Daniel Vetter | 8b47047 | 2013-03-28 10:41:59 +0100 | [diff] [blame] | 6560 | bool is_lvds = false; |
Paulo Zanoni | f48d8f2 | 2012-09-20 18:36:04 -0300 | [diff] [blame] | 6561 | struct intel_encoder *encoder; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 6562 | struct intel_shared_dpll *pll; |
Paulo Zanoni | de13a2e | 2012-09-20 18:36:05 -0300 | [diff] [blame] | 6563 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6564 | |
| 6565 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 6566 | switch (encoder->type) { |
| 6567 | case INTEL_OUTPUT_LVDS: |
| 6568 | is_lvds = true; |
| 6569 | break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6570 | } |
| 6571 | |
| 6572 | num_connectors++; |
| 6573 | } |
| 6574 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 6575 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
| 6576 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); |
| 6577 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 6578 | ok = ironlake_compute_clocks(crtc, &clock, |
Paulo Zanoni | 6591c6e | 2012-09-12 10:06:34 -0300 | [diff] [blame] | 6579 | &has_reduced_clock, &reduced_clock); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 6580 | if (!ok && !intel_crtc->config.clock_set) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6581 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
| 6582 | return -EINVAL; |
| 6583 | } |
Daniel Vetter | f47709a | 2013-03-28 10:42:02 +0100 | [diff] [blame] | 6584 | /* Compat-code for transition, will disappear. */ |
| 6585 | if (!intel_crtc->config.clock_set) { |
| 6586 | intel_crtc->config.dpll.n = clock.n; |
| 6587 | intel_crtc->config.dpll.m1 = clock.m1; |
| 6588 | intel_crtc->config.dpll.m2 = clock.m2; |
| 6589 | intel_crtc->config.dpll.p1 = clock.p1; |
| 6590 | intel_crtc->config.dpll.p2 = clock.p2; |
| 6591 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6592 | |
Paulo Zanoni | 5dc5298 | 2012-10-05 12:05:56 -0300 | [diff] [blame] | 6593 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
Daniel Vetter | 8b47047 | 2013-03-28 10:41:59 +0100 | [diff] [blame] | 6594 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6595 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 6596 | if (has_reduced_clock) |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6597 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 6598 | |
Daniel Vetter | 7429e9d | 2013-04-20 17:19:46 +0200 | [diff] [blame] | 6599 | dpll = ironlake_compute_dpll(intel_crtc, |
Daniel Vetter | cbbab5b | 2013-04-19 11:14:31 +0200 | [diff] [blame] | 6600 | &fp, &reduced_clock, |
| 6601 | has_reduced_clock ? &fp2 : NULL); |
| 6602 | |
Daniel Vetter | 959e16d | 2013-06-05 13:34:21 +0200 | [diff] [blame] | 6603 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 6604 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
| 6605 | if (has_reduced_clock) |
| 6606 | intel_crtc->config.dpll_hw_state.fp1 = fp2; |
| 6607 | else |
| 6608 | intel_crtc->config.dpll_hw_state.fp1 = fp; |
| 6609 | |
Daniel Vetter | b89a1d3 | 2013-06-05 13:34:24 +0200 | [diff] [blame] | 6610 | pll = intel_get_shared_dpll(intel_crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6611 | if (pll == NULL) { |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 6612 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
| 6613 | pipe_name(pipe)); |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 6614 | return -EINVAL; |
| 6615 | } |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 6616 | } else |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 6617 | intel_put_shared_dpll(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6618 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 6619 | if (intel_crtc->config.has_dp_encoder) |
| 6620 | intel_dp_set_m_n(intel_crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6621 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 6622 | if (is_lvds && has_reduced_clock && i915.powersave) |
Daniel Vetter | bcd644e | 2013-06-05 13:34:22 +0200 | [diff] [blame] | 6623 | intel_crtc->lowfreq_avail = true; |
| 6624 | else |
| 6625 | intel_crtc->lowfreq_avail = false; |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 6626 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 6627 | intel_set_pipe_timings(intel_crtc); |
Krzysztof Halasa | 734b415 | 2010-05-25 18:41:46 +0200 | [diff] [blame] | 6628 | |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 6629 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 6630 | intel_cpu_transcoder_set_m_n(intel_crtc, |
| 6631 | &intel_crtc->config.fdi_m_n); |
| 6632 | } |
Chris Wilson | 5eddb70 | 2010-09-11 13:48:45 +0100 | [diff] [blame] | 6633 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 6634 | ironlake_set_pipeconf(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6635 | |
Paulo Zanoni | a1f9e77 | 2012-09-12 10:06:32 -0300 | [diff] [blame] | 6636 | /* Set up the display plane register */ |
| 6637 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); |
Jesse Barnes | b24e717 | 2011-01-04 15:09:30 -0800 | [diff] [blame] | 6638 | POSTING_READ(DSPCNTR(plane)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6639 | |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 6640 | ret = intel_pipe_set_base(crtc, x, y, fb); |
Shaohua Li | 7662c8b | 2009-06-26 11:23:55 +0800 | [diff] [blame] | 6641 | |
Daniel Vetter | 1857e1d | 2013-04-29 19:34:16 +0200 | [diff] [blame] | 6642 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6643 | } |
| 6644 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 6645 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 6646 | struct intel_link_m_n *m_n) |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 6647 | { |
| 6648 | struct drm_device *dev = crtc->base.dev; |
| 6649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 6650 | enum pipe pipe = crtc->pipe; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 6651 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 6652 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); |
| 6653 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); |
| 6654 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 6655 | & ~TU_SIZE_MASK; |
| 6656 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); |
| 6657 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) |
| 6658 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 6659 | } |
| 6660 | |
| 6661 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 6662 | enum transcoder transcoder, |
| 6663 | struct intel_link_m_n *m_n) |
| 6664 | { |
| 6665 | struct drm_device *dev = crtc->base.dev; |
| 6666 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6667 | enum pipe pipe = crtc->pipe; |
| 6668 | |
| 6669 | if (INTEL_INFO(dev)->gen >= 5) { |
| 6670 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
| 6671 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); |
| 6672 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) |
| 6673 | & ~TU_SIZE_MASK; |
| 6674 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); |
| 6675 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) |
| 6676 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 6677 | } else { |
| 6678 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); |
| 6679 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); |
| 6680 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 6681 | & ~TU_SIZE_MASK; |
| 6682 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); |
| 6683 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) |
| 6684 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; |
| 6685 | } |
| 6686 | } |
| 6687 | |
| 6688 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 6689 | struct intel_crtc_config *pipe_config) |
| 6690 | { |
| 6691 | if (crtc->config.has_pch_encoder) |
| 6692 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 6693 | else |
| 6694 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 6695 | &pipe_config->dp_m_n); |
| 6696 | } |
| 6697 | |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 6698 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
| 6699 | struct intel_crtc_config *pipe_config) |
| 6700 | { |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 6701 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 6702 | &pipe_config->fdi_m_n); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 6703 | } |
| 6704 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6705 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
| 6706 | struct intel_crtc_config *pipe_config) |
| 6707 | { |
| 6708 | struct drm_device *dev = crtc->base.dev; |
| 6709 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6710 | uint32_t tmp; |
| 6711 | |
| 6712 | tmp = I915_READ(PF_CTL(crtc->pipe)); |
| 6713 | |
| 6714 | if (tmp & PF_ENABLE) { |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 6715 | pipe_config->pch_pfit.enabled = true; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6716 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
| 6717 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); |
Daniel Vetter | cb8b2a3 | 2013-06-01 17:16:23 +0200 | [diff] [blame] | 6718 | |
| 6719 | /* We currently do not free assignements of panel fitters on |
| 6720 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 6721 | * differentiates them) so just WARN about this case for now. */ |
| 6722 | if (IS_GEN7(dev)) { |
| 6723 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
| 6724 | PF_PIPE_SEL_IVB(crtc->pipe)); |
| 6725 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6726 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 6727 | } |
| 6728 | |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6729 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
| 6730 | struct intel_plane_config *plane_config) |
| 6731 | { |
| 6732 | struct drm_device *dev = crtc->base.dev; |
| 6733 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6734 | u32 val, base, offset; |
| 6735 | int pipe = crtc->pipe, plane = crtc->plane; |
| 6736 | int fourcc, pixel_format; |
| 6737 | int aligned_height; |
| 6738 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6739 | crtc->base.fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
| 6740 | if (!crtc->base.fb) { |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6741 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
| 6742 | return; |
| 6743 | } |
| 6744 | |
| 6745 | val = I915_READ(DSPCNTR(plane)); |
| 6746 | |
| 6747 | if (INTEL_INFO(dev)->gen >= 4) |
| 6748 | if (val & DISPPLANE_TILED) |
| 6749 | plane_config->tiled = true; |
| 6750 | |
| 6751 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; |
| 6752 | fourcc = intel_format_to_fourcc(pixel_format); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6753 | crtc->base.fb->pixel_format = fourcc; |
| 6754 | crtc->base.fb->bits_per_pixel = |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6755 | drm_format_plane_cpp(fourcc, 0) * 8; |
| 6756 | |
| 6757 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; |
| 6758 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
| 6759 | offset = I915_READ(DSPOFFSET(plane)); |
| 6760 | } else { |
| 6761 | if (plane_config->tiled) |
| 6762 | offset = I915_READ(DSPTILEOFF(plane)); |
| 6763 | else |
| 6764 | offset = I915_READ(DSPLINOFF(plane)); |
| 6765 | } |
| 6766 | plane_config->base = base; |
| 6767 | |
| 6768 | val = I915_READ(PIPESRC(pipe)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6769 | crtc->base.fb->width = ((val >> 16) & 0xfff) + 1; |
| 6770 | crtc->base.fb->height = ((val >> 0) & 0xfff) + 1; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6771 | |
| 6772 | val = I915_READ(DSPSTRIDE(pipe)); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6773 | crtc->base.fb->pitches[0] = val & 0xffffff80; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6774 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6775 | aligned_height = intel_align_height(dev, crtc->base.fb->height, |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6776 | plane_config->tiled); |
| 6777 | |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6778 | plane_config->size = ALIGN(crtc->base.fb->pitches[0] * |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6779 | aligned_height, PAGE_SIZE); |
| 6780 | |
| 6781 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 6782 | pipe, plane, crtc->base.fb->width, |
| 6783 | crtc->base.fb->height, |
| 6784 | crtc->base.fb->bits_per_pixel, base, |
| 6785 | crtc->base.fb->pitches[0], |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 6786 | plane_config->size); |
| 6787 | } |
| 6788 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6789 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
| 6790 | struct intel_crtc_config *pipe_config) |
| 6791 | { |
| 6792 | struct drm_device *dev = crtc->base.dev; |
| 6793 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6794 | uint32_t tmp; |
| 6795 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 6796 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 6797 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 6798 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6799 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
| 6800 | if (!(tmp & PIPECONF_ENABLE)) |
| 6801 | return false; |
| 6802 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 6803 | switch (tmp & PIPECONF_BPC_MASK) { |
| 6804 | case PIPECONF_6BPC: |
| 6805 | pipe_config->pipe_bpp = 18; |
| 6806 | break; |
| 6807 | case PIPECONF_8BPC: |
| 6808 | pipe_config->pipe_bpp = 24; |
| 6809 | break; |
| 6810 | case PIPECONF_10BPC: |
| 6811 | pipe_config->pipe_bpp = 30; |
| 6812 | break; |
| 6813 | case PIPECONF_12BPC: |
| 6814 | pipe_config->pipe_bpp = 36; |
| 6815 | break; |
| 6816 | default: |
| 6817 | break; |
| 6818 | } |
| 6819 | |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 6820 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 6821 | struct intel_shared_dpll *pll; |
| 6822 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 6823 | pipe_config->has_pch_encoder = true; |
| 6824 | |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 6825 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
| 6826 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 6827 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 6828 | |
| 6829 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 6830 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 6831 | if (HAS_PCH_IBX(dev_priv->dev)) { |
Daniel Vetter | d94ab06 | 2013-07-04 12:01:16 +0200 | [diff] [blame] | 6832 | pipe_config->shared_dpll = |
| 6833 | (enum intel_dpll_id) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 6834 | } else { |
| 6835 | tmp = I915_READ(PCH_DPLL_SEL); |
| 6836 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) |
| 6837 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; |
| 6838 | else |
| 6839 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; |
| 6840 | } |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 6841 | |
| 6842 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |
| 6843 | |
| 6844 | WARN_ON(!pll->get_hw_state(dev_priv, pll, |
| 6845 | &pipe_config->dpll_hw_state)); |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 6846 | |
| 6847 | tmp = pipe_config->dpll_hw_state.dpll; |
| 6848 | pipe_config->pixel_multiplier = |
| 6849 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) |
| 6850 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 6851 | |
| 6852 | ironlake_pch_clock_get(crtc, pipe_config); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 6853 | } else { |
| 6854 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 6855 | } |
| 6856 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 6857 | intel_get_pipe_timings(crtc, pipe_config); |
| 6858 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 6859 | ironlake_get_pfit_config(crtc, pipe_config); |
| 6860 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 6861 | return true; |
| 6862 | } |
| 6863 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6864 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
| 6865 | { |
| 6866 | struct drm_device *dev = dev_priv->dev; |
| 6867 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; |
| 6868 | struct intel_crtc *crtc; |
| 6869 | unsigned long irqflags; |
Paulo Zanoni | bd633a7 | 2013-08-19 13:18:08 -0300 | [diff] [blame] | 6870 | uint32_t val; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6871 | |
| 6872 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) |
Paulo Zanoni | 798183c | 2013-12-06 20:29:01 -0200 | [diff] [blame] | 6873 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6874 | pipe_name(crtc->pipe)); |
| 6875 | |
| 6876 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
| 6877 | WARN(plls->spll_refcount, "SPLL enabled\n"); |
| 6878 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); |
| 6879 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); |
| 6880 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
| 6881 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
| 6882 | "CPU PWM1 enabled\n"); |
| 6883 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
| 6884 | "CPU PWM2 enabled\n"); |
| 6885 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
| 6886 | "PCH PWM1 enabled\n"); |
| 6887 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
| 6888 | "Utility pin enabled\n"); |
| 6889 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
| 6890 | |
| 6891 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
| 6892 | val = I915_READ(DEIMR); |
Paulo Zanoni | 6806e63 | 2013-11-21 13:47:24 -0200 | [diff] [blame] | 6893 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6894 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
| 6895 | val = I915_READ(SDEIMR); |
Paulo Zanoni | bd633a7 | 2013-08-19 13:18:08 -0300 | [diff] [blame] | 6896 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6897 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
| 6898 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
| 6899 | } |
| 6900 | |
| 6901 | /* |
| 6902 | * This function implements pieces of two sequences from BSpec: |
| 6903 | * - Sequence for display software to disable LCPLL |
| 6904 | * - Sequence for display software to allow package C8+ |
| 6905 | * The steps implemented here are just the steps that actually touch the LCPLL |
| 6906 | * register. Callers should take care of disabling all the display engine |
| 6907 | * functions, doing the mode unset, fixing interrupts, etc. |
| 6908 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 6909 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
| 6910 | bool switch_to_fclk, bool allow_power_down) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6911 | { |
| 6912 | uint32_t val; |
| 6913 | |
| 6914 | assert_can_disable_lcpll(dev_priv); |
| 6915 | |
| 6916 | val = I915_READ(LCPLL_CTL); |
| 6917 | |
| 6918 | if (switch_to_fclk) { |
| 6919 | val |= LCPLL_CD_SOURCE_FCLK; |
| 6920 | I915_WRITE(LCPLL_CTL, val); |
| 6921 | |
| 6922 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & |
| 6923 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) |
| 6924 | DRM_ERROR("Switching to FCLK failed\n"); |
| 6925 | |
| 6926 | val = I915_READ(LCPLL_CTL); |
| 6927 | } |
| 6928 | |
| 6929 | val |= LCPLL_PLL_DISABLE; |
| 6930 | I915_WRITE(LCPLL_CTL, val); |
| 6931 | POSTING_READ(LCPLL_CTL); |
| 6932 | |
| 6933 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
| 6934 | DRM_ERROR("LCPLL still locked\n"); |
| 6935 | |
| 6936 | val = I915_READ(D_COMP); |
| 6937 | val |= D_COMP_COMP_DISABLE; |
Paulo Zanoni | 515b239 | 2013-09-10 19:36:37 -0300 | [diff] [blame] | 6938 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6939 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
| 6940 | DRM_ERROR("Failed to disable D_COMP\n"); |
| 6941 | mutex_unlock(&dev_priv->rps.hw_lock); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6942 | POSTING_READ(D_COMP); |
| 6943 | ndelay(100); |
| 6944 | |
| 6945 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) |
| 6946 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
| 6947 | |
| 6948 | if (allow_power_down) { |
| 6949 | val = I915_READ(LCPLL_CTL); |
| 6950 | val |= LCPLL_POWER_DOWN_ALLOW; |
| 6951 | I915_WRITE(LCPLL_CTL, val); |
| 6952 | POSTING_READ(LCPLL_CTL); |
| 6953 | } |
| 6954 | } |
| 6955 | |
| 6956 | /* |
| 6957 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL |
| 6958 | * source. |
| 6959 | */ |
Paulo Zanoni | 6ff58d5 | 2013-09-24 13:52:57 -0300 | [diff] [blame] | 6960 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6961 | { |
| 6962 | uint32_t val; |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 6963 | unsigned long irqflags; |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6964 | |
| 6965 | val = I915_READ(LCPLL_CTL); |
| 6966 | |
| 6967 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | |
| 6968 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) |
| 6969 | return; |
| 6970 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 6971 | /* |
| 6972 | * Make sure we're not on PC8 state before disabling PC8, otherwise |
| 6973 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. |
| 6974 | * |
| 6975 | * The other problem is that hsw_restore_lcpll() is called as part of |
| 6976 | * the runtime PM resume sequence, so we can't just call |
| 6977 | * gen6_gt_force_wake_get() because that function calls |
| 6978 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount |
| 6979 | * while we are on the resume sequence. So to solve this problem we have |
| 6980 | * to call special forcewake code that doesn't touch runtime PM and |
| 6981 | * doesn't enable the forcewake delayed work. |
| 6982 | */ |
| 6983 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 6984 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 6985 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
| 6986 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 6987 | |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6988 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
| 6989 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
| 6990 | I915_WRITE(LCPLL_CTL, val); |
Daniel Vetter | 35d8f2e | 2013-08-21 23:38:08 +0200 | [diff] [blame] | 6991 | POSTING_READ(LCPLL_CTL); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 6992 | } |
| 6993 | |
| 6994 | val = I915_READ(D_COMP); |
| 6995 | val |= D_COMP_COMP_FORCE; |
| 6996 | val &= ~D_COMP_COMP_DISABLE; |
Paulo Zanoni | 515b239 | 2013-09-10 19:36:37 -0300 | [diff] [blame] | 6997 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6998 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) |
| 6999 | DRM_ERROR("Failed to enable D_COMP\n"); |
| 7000 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 35d8f2e | 2013-08-21 23:38:08 +0200 | [diff] [blame] | 7001 | POSTING_READ(D_COMP); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7002 | |
| 7003 | val = I915_READ(LCPLL_CTL); |
| 7004 | val &= ~LCPLL_PLL_DISABLE; |
| 7005 | I915_WRITE(LCPLL_CTL, val); |
| 7006 | |
| 7007 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) |
| 7008 | DRM_ERROR("LCPLL not locked yet\n"); |
| 7009 | |
| 7010 | if (val & LCPLL_CD_SOURCE_FCLK) { |
| 7011 | val = I915_READ(LCPLL_CTL); |
| 7012 | val &= ~LCPLL_CD_SOURCE_FCLK; |
| 7013 | I915_WRITE(LCPLL_CTL, val); |
| 7014 | |
| 7015 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & |
| 7016 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) |
| 7017 | DRM_ERROR("Switching back to LCPLL failed\n"); |
| 7018 | } |
Paulo Zanoni | 215733f | 2013-08-19 13:18:07 -0300 | [diff] [blame] | 7019 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7020 | /* See the big comment above. */ |
| 7021 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 7022 | if (--dev_priv->uncore.forcewake_count == 0) |
| 7023 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
| 7024 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | be256dc | 2013-07-23 11:19:26 -0300 | [diff] [blame] | 7025 | } |
| 7026 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7027 | void __hsw_do_enable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7028 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7029 | struct drm_device *dev = dev_priv->dev; |
| 7030 | uint32_t val; |
| 7031 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7032 | WARN_ON(!HAS_PC8(dev)); |
| 7033 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7034 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
| 7035 | |
| 7036 | dev_priv->pc8.enabled = true; |
| 7037 | |
| 7038 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 7039 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 7040 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 7041 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 7042 | } |
| 7043 | |
| 7044 | lpt_disable_clkout_dp(dev); |
| 7045 | hsw_pc8_disable_interrupts(dev); |
| 7046 | hsw_disable_lcpll(dev_priv, true, true); |
Paulo Zanoni | b4d2a9a | 2014-03-07 20:08:04 -0300 | [diff] [blame] | 7047 | } |
Paulo Zanoni | 8771a7f | 2013-11-21 13:47:28 -0200 | [diff] [blame] | 7048 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7049 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
| 7050 | { |
| 7051 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7052 | intel_runtime_pm_put(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7053 | } |
| 7054 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7055 | void __hsw_do_disable_pc8(struct drm_i915_private *dev_priv) |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7056 | { |
| 7057 | struct drm_device *dev = dev_priv->dev; |
| 7058 | uint32_t val; |
| 7059 | |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 7060 | WARN_ON(!HAS_PC8(dev)); |
| 7061 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7062 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
| 7063 | |
| 7064 | hsw_restore_lcpll(dev_priv); |
| 7065 | hsw_pc8_restore_interrupts(dev); |
| 7066 | lpt_init_pch_refclk(dev); |
| 7067 | |
| 7068 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 7069 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 7070 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; |
| 7071 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 7072 | } |
| 7073 | |
| 7074 | intel_prepare_ddi(dev); |
| 7075 | i915_gem_init_swizzling(dev); |
| 7076 | mutex_lock(&dev_priv->rps.hw_lock); |
| 7077 | gen6_update_ring_freq(dev); |
| 7078 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 7079 | dev_priv->pc8.enabled = false; |
| 7080 | } |
| 7081 | |
Paulo Zanoni | b4d2a9a | 2014-03-07 20:08:04 -0300 | [diff] [blame] | 7082 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
| 7083 | { |
Paulo Zanoni | b4d2a9a | 2014-03-07 20:08:04 -0300 | [diff] [blame] | 7084 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); |
Paulo Zanoni | b4d2a9a | 2014-03-07 20:08:04 -0300 | [diff] [blame] | 7085 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | b4d2a9a | 2014-03-07 20:08:04 -0300 | [diff] [blame] | 7086 | } |
| 7087 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7088 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) |
| 7089 | { |
Chris Wilson | 7c6c265 | 2013-11-18 18:32:37 -0800 | [diff] [blame] | 7090 | if (!HAS_PC8(dev_priv->dev)) |
| 7091 | return; |
| 7092 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7093 | mutex_lock(&dev_priv->pc8.lock); |
| 7094 | __hsw_enable_package_c8(dev_priv); |
| 7095 | mutex_unlock(&dev_priv->pc8.lock); |
| 7096 | } |
| 7097 | |
| 7098 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) |
| 7099 | { |
Chris Wilson | 7c6c265 | 2013-11-18 18:32:37 -0800 | [diff] [blame] | 7100 | if (!HAS_PC8(dev_priv->dev)) |
| 7101 | return; |
| 7102 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7103 | mutex_lock(&dev_priv->pc8.lock); |
| 7104 | __hsw_disable_package_c8(dev_priv); |
| 7105 | mutex_unlock(&dev_priv->pc8.lock); |
| 7106 | } |
| 7107 | |
Imre Deak | 4f07412 | 2013-10-16 17:25:51 +0300 | [diff] [blame] | 7108 | static void haswell_modeset_global_resources(struct drm_device *dev) |
| 7109 | { |
Paulo Zanoni | da72356 | 2013-12-19 11:54:51 -0200 | [diff] [blame] | 7110 | modeset_update_crtc_power_domains(dev); |
Daniel Vetter | d6dd9eb | 2013-01-29 16:35:20 -0200 | [diff] [blame] | 7111 | } |
| 7112 | |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7113 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7114 | int x, int y, |
| 7115 | struct drm_framebuffer *fb) |
| 7116 | { |
| 7117 | struct drm_device *dev = crtc->dev; |
| 7118 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7119 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7120 | int plane = intel_crtc->plane; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7121 | int ret; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7122 | |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 7123 | if (!intel_ddi_pll_select(intel_crtc)) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 7124 | return -EINVAL; |
Paulo Zanoni | 566b734 | 2013-11-25 15:27:08 -0200 | [diff] [blame] | 7125 | intel_ddi_pll_enable(intel_crtc); |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 7126 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 7127 | if (intel_crtc->config.has_dp_encoder) |
| 7128 | intel_dp_set_m_n(intel_crtc); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7129 | |
| 7130 | intel_crtc->lowfreq_avail = false; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7131 | |
Daniel Vetter | 8a654f3 | 2013-06-01 17:16:22 +0200 | [diff] [blame] | 7132 | intel_set_pipe_timings(intel_crtc); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7133 | |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 7134 | if (intel_crtc->config.has_pch_encoder) { |
Daniel Vetter | ca3a0ff | 2013-02-14 16:54:22 +0100 | [diff] [blame] | 7135 | intel_cpu_transcoder_set_m_n(intel_crtc, |
| 7136 | &intel_crtc->config.fdi_m_n); |
| 7137 | } |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7138 | |
Daniel Vetter | 6ff9360 | 2013-04-19 11:24:36 +0200 | [diff] [blame] | 7139 | haswell_set_pipeconf(crtc); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7140 | |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 7141 | intel_set_pipe_csc(crtc); |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 7142 | |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7143 | /* Set up the display plane register */ |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 7144 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 7145 | POSTING_READ(DSPCNTR(plane)); |
| 7146 | |
| 7147 | ret = intel_pipe_set_base(crtc, x, y, fb); |
| 7148 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7149 | return ret; |
| 7150 | } |
| 7151 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7152 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
| 7153 | struct intel_crtc_config *pipe_config) |
| 7154 | { |
| 7155 | struct drm_device *dev = crtc->base.dev; |
| 7156 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7157 | enum intel_display_power_domain pfit_domain; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7158 | uint32_t tmp; |
| 7159 | |
Imre Deak | b5482bd | 2014-03-05 16:20:55 +0200 | [diff] [blame] | 7160 | if (!intel_display_power_enabled(dev_priv, |
| 7161 | POWER_DOMAIN_PIPE(crtc->pipe))) |
| 7162 | return false; |
| 7163 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 7164 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 7165 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
| 7166 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7167 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
| 7168 | if (tmp & TRANS_DDI_FUNC_ENABLE) { |
| 7169 | enum pipe trans_edp_pipe; |
| 7170 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
| 7171 | default: |
| 7172 | WARN(1, "unknown pipe linked to edp transcoder\n"); |
| 7173 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
| 7174 | case TRANS_DDI_EDP_INPUT_A_ON: |
| 7175 | trans_edp_pipe = PIPE_A; |
| 7176 | break; |
| 7177 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
| 7178 | trans_edp_pipe = PIPE_B; |
| 7179 | break; |
| 7180 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
| 7181 | trans_edp_pipe = PIPE_C; |
| 7182 | break; |
| 7183 | } |
| 7184 | |
| 7185 | if (trans_edp_pipe == crtc->pipe) |
| 7186 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
| 7187 | } |
| 7188 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7189 | if (!intel_display_power_enabled(dev_priv, |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7190 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
Paulo Zanoni | 2bfce95 | 2013-04-18 16:35:40 -0300 | [diff] [blame] | 7191 | return false; |
| 7192 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7193 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7194 | if (!(tmp & PIPECONF_ENABLE)) |
| 7195 | return false; |
| 7196 | |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7197 | /* |
Paulo Zanoni | f196e6b | 2013-04-18 16:35:41 -0300 | [diff] [blame] | 7198 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7199 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 7200 | * the PCH transcoder is on. |
| 7201 | */ |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 7202 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7203 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
Daniel Vetter | ab9412b | 2013-05-03 11:49:46 +0200 | [diff] [blame] | 7204 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7205 | pipe_config->has_pch_encoder = true; |
| 7206 | |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 7207 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
| 7208 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> |
| 7209 | FDI_DP_PORT_WIDTH_SHIFT) + 1; |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 7210 | |
| 7211 | ironlake_get_fdi_m_n_config(crtc, pipe_config); |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 7212 | } |
| 7213 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 7214 | intel_get_pipe_timings(crtc, pipe_config); |
| 7215 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7216 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7217 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 7218 | ironlake_get_pfit_config(crtc, pipe_config); |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 7219 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 7220 | if (IS_HASWELL(dev)) |
| 7221 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
| 7222 | (I915_READ(IPS_CTL) & IPS_ENABLE); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 7223 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 7224 | pipe_config->pixel_multiplier = 1; |
| 7225 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 7226 | return true; |
| 7227 | } |
| 7228 | |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 7229 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 7230 | int x, int y, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 7231 | struct drm_framebuffer *fb) |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 7232 | { |
| 7233 | struct drm_device *dev = crtc->dev; |
| 7234 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9256aa1 | 2012-10-31 19:26:13 +0100 | [diff] [blame] | 7235 | struct intel_encoder *encoder; |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 7236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 7237 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 7238 | int pipe = intel_crtc->pipe; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 7239 | int ret; |
| 7240 | |
Eric Anholt | 0b701d2 | 2011-03-30 13:01:03 -0700 | [diff] [blame] | 7241 | drm_vblank_pre_modeset(dev, pipe); |
| 7242 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 7243 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
| 7244 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7245 | drm_vblank_post_modeset(dev, pipe); |
| 7246 | |
Daniel Vetter | 9256aa1 | 2012-10-31 19:26:13 +0100 | [diff] [blame] | 7247 | if (ret != 0) |
| 7248 | return ret; |
| 7249 | |
| 7250 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 7251 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", |
| 7252 | encoder->base.base.id, |
| 7253 | drm_get_encoder_name(&encoder->base), |
| 7254 | mode->base.id, mode->name); |
Daniel Vetter | 36f2d1f | 2013-07-21 21:37:08 +0200 | [diff] [blame] | 7255 | encoder->mode_set(encoder); |
Daniel Vetter | 9256aa1 | 2012-10-31 19:26:13 +0100 | [diff] [blame] | 7256 | } |
| 7257 | |
| 7258 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7259 | } |
| 7260 | |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 7261 | static struct { |
| 7262 | int clock; |
| 7263 | u32 config; |
| 7264 | } hdmi_audio_clock[] = { |
| 7265 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
| 7266 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
| 7267 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
| 7268 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
| 7269 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
| 7270 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
| 7271 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
| 7272 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
| 7273 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
| 7274 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
| 7275 | }; |
| 7276 | |
| 7277 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
| 7278 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
| 7279 | { |
| 7280 | int i; |
| 7281 | |
| 7282 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
| 7283 | if (mode->clock == hdmi_audio_clock[i].clock) |
| 7284 | break; |
| 7285 | } |
| 7286 | |
| 7287 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
| 7288 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
| 7289 | i = 1; |
| 7290 | } |
| 7291 | |
| 7292 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
| 7293 | hdmi_audio_clock[i].clock, |
| 7294 | hdmi_audio_clock[i].config); |
| 7295 | |
| 7296 | return hdmi_audio_clock[i].config; |
| 7297 | } |
| 7298 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7299 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 7300 | int reg_eldv, uint32_t bits_eldv, |
| 7301 | int reg_elda, uint32_t bits_elda, |
| 7302 | int reg_edid) |
| 7303 | { |
| 7304 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7305 | uint8_t *eld = connector->eld; |
| 7306 | uint32_t i; |
| 7307 | |
| 7308 | i = I915_READ(reg_eldv); |
| 7309 | i &= bits_eldv; |
| 7310 | |
| 7311 | if (!eld[0]) |
| 7312 | return !i; |
| 7313 | |
| 7314 | if (!i) |
| 7315 | return false; |
| 7316 | |
| 7317 | i = I915_READ(reg_elda); |
| 7318 | i &= ~bits_elda; |
| 7319 | I915_WRITE(reg_elda, i); |
| 7320 | |
| 7321 | for (i = 0; i < eld[2]; i++) |
| 7322 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 7323 | return false; |
| 7324 | |
| 7325 | return true; |
| 7326 | } |
| 7327 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7328 | static void g4x_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7329 | struct drm_crtc *crtc, |
| 7330 | struct drm_display_mode *mode) |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7331 | { |
| 7332 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7333 | uint8_t *eld = connector->eld; |
| 7334 | uint32_t eldv; |
| 7335 | uint32_t len; |
| 7336 | uint32_t i; |
| 7337 | |
| 7338 | i = I915_READ(G4X_AUD_VID_DID); |
| 7339 | |
| 7340 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) |
| 7341 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 7342 | else |
| 7343 | eldv = G4X_ELDV_DEVCTG; |
| 7344 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7345 | if (intel_eld_uptodate(connector, |
| 7346 | G4X_AUD_CNTL_ST, eldv, |
| 7347 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, |
| 7348 | G4X_HDMIW_HDMIEDID)) |
| 7349 | return; |
| 7350 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7351 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 7352 | i &= ~(eldv | G4X_ELD_ADDR); |
| 7353 | len = (i >> 9) & 0x1f; /* ELD buffer size */ |
| 7354 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 7355 | |
| 7356 | if (!eld[0]) |
| 7357 | return; |
| 7358 | |
| 7359 | len = min_t(uint8_t, eld[2], len); |
| 7360 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 7361 | for (i = 0; i < len; i++) |
| 7362 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 7363 | |
| 7364 | i = I915_READ(G4X_AUD_CNTL_ST); |
| 7365 | i |= eldv; |
| 7366 | I915_WRITE(G4X_AUD_CNTL_ST, i); |
| 7367 | } |
| 7368 | |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7369 | static void haswell_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7370 | struct drm_crtc *crtc, |
| 7371 | struct drm_display_mode *mode) |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7372 | { |
| 7373 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7374 | uint8_t *eld = connector->eld; |
| 7375 | struct drm_device *dev = crtc->dev; |
Wang Xingchao | 7b9f35a | 2013-01-22 23:25:25 +0800 | [diff] [blame] | 7376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7377 | uint32_t eldv; |
| 7378 | uint32_t i; |
| 7379 | int len; |
| 7380 | int pipe = to_intel_crtc(crtc)->pipe; |
| 7381 | int tmp; |
| 7382 | |
| 7383 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); |
| 7384 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); |
| 7385 | int aud_config = HSW_AUD_CFG(pipe); |
| 7386 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; |
| 7387 | |
| 7388 | |
| 7389 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); |
| 7390 | |
| 7391 | /* Audio output enable */ |
| 7392 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); |
| 7393 | tmp = I915_READ(aud_cntrl_st2); |
| 7394 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); |
| 7395 | I915_WRITE(aud_cntrl_st2, tmp); |
| 7396 | |
| 7397 | /* Wait for 1 vertical blank */ |
| 7398 | intel_wait_for_vblank(dev, pipe); |
| 7399 | |
| 7400 | /* Set ELD valid state */ |
| 7401 | tmp = I915_READ(aud_cntrl_st2); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7402 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7403 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
| 7404 | I915_WRITE(aud_cntrl_st2, tmp); |
| 7405 | tmp = I915_READ(aud_cntrl_st2); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7406 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7407 | |
| 7408 | /* Enable HDMI mode */ |
| 7409 | tmp = I915_READ(aud_config); |
Takashi Iwai | 7e7cb34 | 2013-09-10 07:30:36 +0200 | [diff] [blame] | 7410 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7411 | /* clear N_programing_enable and N_value_index */ |
| 7412 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); |
| 7413 | I915_WRITE(aud_config, tmp); |
| 7414 | |
| 7415 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
| 7416 | |
| 7417 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); |
Wang Xingchao | 7b9f35a | 2013-01-22 23:25:25 +0800 | [diff] [blame] | 7418 | intel_crtc->eld_vld = true; |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7419 | |
| 7420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 7421 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 7422 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
| 7423 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 7424 | } else { |
| 7425 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
| 7426 | } |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 7427 | |
| 7428 | if (intel_eld_uptodate(connector, |
| 7429 | aud_cntrl_st2, eldv, |
| 7430 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 7431 | hdmiw_hdmiedid)) |
| 7432 | return; |
| 7433 | |
| 7434 | i = I915_READ(aud_cntrl_st2); |
| 7435 | i &= ~eldv; |
| 7436 | I915_WRITE(aud_cntrl_st2, i); |
| 7437 | |
| 7438 | if (!eld[0]) |
| 7439 | return; |
| 7440 | |
| 7441 | i = I915_READ(aud_cntl_st); |
| 7442 | i &= ~IBX_ELD_ADDRESS; |
| 7443 | I915_WRITE(aud_cntl_st, i); |
| 7444 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
| 7445 | DRM_DEBUG_DRIVER("port num:%d\n", i); |
| 7446 | |
| 7447 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 7448 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 7449 | for (i = 0; i < len; i++) |
| 7450 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 7451 | |
| 7452 | i = I915_READ(aud_cntrl_st2); |
| 7453 | i |= eldv; |
| 7454 | I915_WRITE(aud_cntrl_st2, i); |
| 7455 | |
| 7456 | } |
| 7457 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7458 | static void ironlake_write_eld(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7459 | struct drm_crtc *crtc, |
| 7460 | struct drm_display_mode *mode) |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7461 | { |
| 7462 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 7463 | uint8_t *eld = connector->eld; |
| 7464 | uint32_t eldv; |
| 7465 | uint32_t i; |
| 7466 | int len; |
| 7467 | int hdmiw_hdmiedid; |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 7468 | int aud_config; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7469 | int aud_cntl_st; |
| 7470 | int aud_cntrl_st2; |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7471 | int pipe = to_intel_crtc(crtc)->pipe; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7472 | |
Wu Fengguang | b3f33cb | 2011-12-09 20:42:17 +0800 | [diff] [blame] | 7473 | if (HAS_PCH_IBX(connector->dev)) { |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7474 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
| 7475 | aud_config = IBX_AUD_CFG(pipe); |
| 7476 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 7477 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 7478 | } else if (IS_VALLEYVIEW(connector->dev)) { |
| 7479 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
| 7480 | aud_config = VLV_AUD_CFG(pipe); |
| 7481 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
| 7482 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7483 | } else { |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7484 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
| 7485 | aud_config = CPT_AUD_CFG(pipe); |
| 7486 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 7487 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7488 | } |
| 7489 | |
Wang Xingchao | 9b138a8 | 2012-08-09 16:52:18 +0800 | [diff] [blame] | 7490 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7491 | |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 7492 | if (IS_VALLEYVIEW(connector->dev)) { |
| 7493 | struct intel_encoder *intel_encoder; |
| 7494 | struct intel_digital_port *intel_dig_port; |
| 7495 | |
| 7496 | intel_encoder = intel_attached_encoder(connector); |
| 7497 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
| 7498 | i = intel_dig_port->port; |
| 7499 | } else { |
| 7500 | i = I915_READ(aud_cntl_st); |
| 7501 | i = (i >> 29) & DIP_PORT_SEL_MASK; |
| 7502 | /* DIP_Port_Select, 0x1 = PortB */ |
| 7503 | } |
| 7504 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7505 | if (!i) { |
| 7506 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); |
| 7507 | /* operate blindly on all ports */ |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 7508 | eldv = IBX_ELD_VALIDB; |
| 7509 | eldv |= IBX_ELD_VALIDB << 4; |
| 7510 | eldv |= IBX_ELD_VALIDB << 8; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7511 | } else { |
Ville Syrjälä | 2582a85 | 2013-04-17 17:48:47 +0300 | [diff] [blame] | 7512 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 7513 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7514 | } |
| 7515 | |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7516 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
| 7517 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); |
| 7518 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ |
Wu Fengguang | b6daa02 | 2012-01-06 14:41:31 -0600 | [diff] [blame] | 7519 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
Jani Nikula | 1a91510 | 2013-10-16 12:34:48 +0300 | [diff] [blame] | 7520 | } else { |
| 7521 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); |
| 7522 | } |
Wu Fengguang | 3a9627f | 2011-12-09 20:42:19 +0800 | [diff] [blame] | 7523 | |
| 7524 | if (intel_eld_uptodate(connector, |
| 7525 | aud_cntrl_st2, eldv, |
| 7526 | aud_cntl_st, IBX_ELD_ADDRESS, |
| 7527 | hdmiw_hdmiedid)) |
| 7528 | return; |
| 7529 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7530 | i = I915_READ(aud_cntrl_st2); |
| 7531 | i &= ~eldv; |
| 7532 | I915_WRITE(aud_cntrl_st2, i); |
| 7533 | |
| 7534 | if (!eld[0]) |
| 7535 | return; |
| 7536 | |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7537 | i = I915_READ(aud_cntl_st); |
Wu Fengguang | 1202b4c6 | 2011-12-09 20:42:18 +0800 | [diff] [blame] | 7538 | i &= ~IBX_ELD_ADDRESS; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7539 | I915_WRITE(aud_cntl_st, i); |
| 7540 | |
| 7541 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ |
| 7542 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 7543 | for (i = 0; i < len; i++) |
| 7544 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 7545 | |
| 7546 | i = I915_READ(aud_cntrl_st2); |
| 7547 | i |= eldv; |
| 7548 | I915_WRITE(aud_cntrl_st2, i); |
| 7549 | } |
| 7550 | |
| 7551 | void intel_write_eld(struct drm_encoder *encoder, |
| 7552 | struct drm_display_mode *mode) |
| 7553 | { |
| 7554 | struct drm_crtc *crtc = encoder->crtc; |
| 7555 | struct drm_connector *connector; |
| 7556 | struct drm_device *dev = encoder->dev; |
| 7557 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7558 | |
| 7559 | connector = drm_select_eld(encoder, mode); |
| 7560 | if (!connector) |
| 7561 | return; |
| 7562 | |
| 7563 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 7564 | connector->base.id, |
| 7565 | drm_get_connector_name(connector), |
| 7566 | connector->encoder->base.id, |
| 7567 | drm_get_encoder_name(connector->encoder)); |
| 7568 | |
| 7569 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 7570 | |
| 7571 | if (dev_priv->display.write_eld) |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 7572 | dev_priv->display.write_eld(connector, crtc, mode); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 7573 | } |
| 7574 | |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7575 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
| 7576 | { |
| 7577 | struct drm_device *dev = crtc->dev; |
| 7578 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7580 | bool visible = base != 0; |
| 7581 | u32 cntl; |
| 7582 | |
| 7583 | if (intel_crtc->cursor_visible == visible) |
| 7584 | return; |
| 7585 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7586 | cntl = I915_READ(_CURACNTR); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7587 | if (visible) { |
| 7588 | /* On these chipsets we can only modify the base whilst |
| 7589 | * the cursor is disabled. |
| 7590 | */ |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7591 | I915_WRITE(_CURABASE, base); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7592 | |
| 7593 | cntl &= ~(CURSOR_FORMAT_MASK); |
| 7594 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
| 7595 | cntl |= CURSOR_ENABLE | |
| 7596 | CURSOR_GAMMA_ENABLE | |
| 7597 | CURSOR_FORMAT_ARGB; |
| 7598 | } else |
| 7599 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7600 | I915_WRITE(_CURACNTR, cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7601 | |
| 7602 | intel_crtc->cursor_visible = visible; |
| 7603 | } |
| 7604 | |
| 7605 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
| 7606 | { |
| 7607 | struct drm_device *dev = crtc->dev; |
| 7608 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7609 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7610 | int pipe = intel_crtc->pipe; |
| 7611 | bool visible = base != 0; |
| 7612 | |
| 7613 | if (intel_crtc->cursor_visible != visible) { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 7614 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7615 | if (base) { |
| 7616 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); |
| 7617 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 7618 | cntl |= pipe << 28; /* Connect to correct pipe */ |
| 7619 | } else { |
| 7620 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 7621 | cntl |= CURSOR_MODE_DISABLE; |
| 7622 | } |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7623 | I915_WRITE(CURCNTR(pipe), cntl); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7624 | |
| 7625 | intel_crtc->cursor_visible = visible; |
| 7626 | } |
| 7627 | /* and commit changes on next vblank */ |
Daniel Vetter | b2ea8ef | 2013-11-04 08:13:45 +0100 | [diff] [blame] | 7628 | POSTING_READ(CURCNTR(pipe)); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 7629 | I915_WRITE(CURBASE(pipe), base); |
Daniel Vetter | b2ea8ef | 2013-11-04 08:13:45 +0100 | [diff] [blame] | 7630 | POSTING_READ(CURBASE(pipe)); |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7631 | } |
| 7632 | |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 7633 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
| 7634 | { |
| 7635 | struct drm_device *dev = crtc->dev; |
| 7636 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7638 | int pipe = intel_crtc->pipe; |
| 7639 | bool visible = base != 0; |
| 7640 | |
| 7641 | if (intel_crtc->cursor_visible != visible) { |
| 7642 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); |
| 7643 | if (base) { |
| 7644 | cntl &= ~CURSOR_MODE; |
| 7645 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 7646 | } else { |
| 7647 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); |
| 7648 | cntl |= CURSOR_MODE_DISABLE; |
| 7649 | } |
Ville Syrjälä | 6bbfa1c | 2013-11-02 21:07:39 -0700 | [diff] [blame] | 7650 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 7651 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 7652 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
| 7653 | } |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 7654 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
| 7655 | |
| 7656 | intel_crtc->cursor_visible = visible; |
| 7657 | } |
| 7658 | /* and commit changes on next vblank */ |
Daniel Vetter | b2ea8ef | 2013-11-04 08:13:45 +0100 | [diff] [blame] | 7659 | POSTING_READ(CURCNTR_IVB(pipe)); |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 7660 | I915_WRITE(CURBASE_IVB(pipe), base); |
Daniel Vetter | b2ea8ef | 2013-11-04 08:13:45 +0100 | [diff] [blame] | 7661 | POSTING_READ(CURBASE_IVB(pipe)); |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 7662 | } |
| 7663 | |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7664 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 7665 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
| 7666 | bool on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7667 | { |
| 7668 | struct drm_device *dev = crtc->dev; |
| 7669 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 7671 | int pipe = intel_crtc->pipe; |
| 7672 | int x = intel_crtc->cursor_x; |
| 7673 | int y = intel_crtc->cursor_y; |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 7674 | u32 base = 0, pos = 0; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7675 | bool visible; |
| 7676 | |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 7677 | if (on) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7678 | base = intel_crtc->cursor_addr; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7679 | |
Ville Syrjälä | d6e4db1 | 2013-09-04 18:25:31 +0300 | [diff] [blame] | 7680 | if (x >= intel_crtc->config.pipe_src_w) |
| 7681 | base = 0; |
| 7682 | |
| 7683 | if (y >= intel_crtc->config.pipe_src_h) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7684 | base = 0; |
| 7685 | |
| 7686 | if (x < 0) { |
Ville Syrjälä | efc9064 | 2013-09-04 18:25:30 +0300 | [diff] [blame] | 7687 | if (x + intel_crtc->cursor_width <= 0) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7688 | base = 0; |
| 7689 | |
| 7690 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
| 7691 | x = -x; |
| 7692 | } |
| 7693 | pos |= x << CURSOR_X_SHIFT; |
| 7694 | |
| 7695 | if (y < 0) { |
Ville Syrjälä | efc9064 | 2013-09-04 18:25:30 +0300 | [diff] [blame] | 7696 | if (y + intel_crtc->cursor_height <= 0) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7697 | base = 0; |
| 7698 | |
| 7699 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
| 7700 | y = -y; |
| 7701 | } |
| 7702 | pos |= y << CURSOR_Y_SHIFT; |
| 7703 | |
| 7704 | visible = base != 0; |
Chris Wilson | 560b85b | 2010-08-07 11:01:38 +0100 | [diff] [blame] | 7705 | if (!visible && !intel_crtc->cursor_visible) |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7706 | return; |
| 7707 | |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 7708 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Jesse Barnes | 65a21cd | 2011-10-12 11:10:21 -0700 | [diff] [blame] | 7709 | I915_WRITE(CURPOS_IVB(pipe), pos); |
| 7710 | ivb_update_cursor(crtc, base); |
| 7711 | } else { |
| 7712 | I915_WRITE(CURPOS(pipe), pos); |
| 7713 | if (IS_845G(dev) || IS_I865G(dev)) |
| 7714 | i845_update_cursor(crtc, base); |
| 7715 | else |
| 7716 | i9xx_update_cursor(crtc, base); |
| 7717 | } |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7718 | } |
| 7719 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7720 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7721 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7722 | uint32_t handle, |
| 7723 | uint32_t width, uint32_t height) |
| 7724 | { |
| 7725 | struct drm_device *dev = crtc->dev; |
| 7726 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7728 | struct drm_i915_gem_object *obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7729 | uint32_t addr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7730 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7731 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7732 | /* if we want to turn off the cursor ignore width and height */ |
| 7733 | if (!handle) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 7734 | DRM_DEBUG_KMS("cursor off\n"); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7735 | addr = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7736 | obj = NULL; |
Pierre Willenbrock | 5004417 | 2009-02-23 10:12:15 +1000 | [diff] [blame] | 7737 | mutex_lock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7738 | goto finish; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7739 | } |
| 7740 | |
| 7741 | /* Currently we only support 64x64 cursors */ |
| 7742 | if (width != 64 || height != 64) { |
| 7743 | DRM_ERROR("we currently only support 64x64 cursors\n"); |
| 7744 | return -EINVAL; |
| 7745 | } |
| 7746 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7747 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 7748 | if (&obj->base == NULL) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7749 | return -ENOENT; |
| 7750 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7751 | if (obj->base.size < width * height * 4) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 7752 | DRM_DEBUG_KMS("buffer is to small\n"); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 7753 | ret = -ENOMEM; |
| 7754 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7755 | } |
| 7756 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 7757 | /* we only need to pin inside GTT if cursor is non-phy */ |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 7758 | mutex_lock(&dev->struct_mutex); |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 7759 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 7760 | unsigned alignment; |
| 7761 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7762 | if (obj->tiling_mode) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 7763 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7764 | ret = -EINVAL; |
| 7765 | goto fail_locked; |
| 7766 | } |
| 7767 | |
Chris Wilson | 693db18 | 2013-03-05 14:52:39 +0000 | [diff] [blame] | 7768 | /* Note that the w/a also requires 2 PTE of padding following |
| 7769 | * the bo. We currently fill all unused PTE with the shadow |
| 7770 | * page and so we should always have valid PTE following the |
| 7771 | * cursor preventing the VT-d warning. |
| 7772 | */ |
| 7773 | alignment = 0; |
| 7774 | if (need_vtd_wa(dev)) |
| 7775 | alignment = 64*1024; |
| 7776 | |
| 7777 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 7778 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 7779 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 7780 | goto fail_locked; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 7781 | } |
| 7782 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7783 | ret = i915_gem_object_put_fence(obj); |
| 7784 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 7785 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 7786 | goto fail_unpin; |
| 7787 | } |
| 7788 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 7789 | addr = i915_gem_obj_ggtt_offset(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 7790 | } else { |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 7791 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7792 | ret = i915_gem_attach_phys_object(dev, obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 7793 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
| 7794 | align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 7795 | if (ret) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 7796 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 7797 | goto fail_locked; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 7798 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7799 | addr = obj->phys_obj->handle->busaddr; |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7800 | } |
| 7801 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 7802 | if (IS_GEN2(dev)) |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 7803 | I915_WRITE(CURSIZE, (height << 12) | width); |
| 7804 | |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7805 | finish: |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7806 | if (intel_crtc->cursor_bo) { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 7807 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7808 | if (intel_crtc->cursor_bo != obj) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 7809 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
| 7810 | } else |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 7811 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7812 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7813 | } |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 7814 | |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 7815 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7816 | |
| 7817 | intel_crtc->cursor_addr = addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7818 | intel_crtc->cursor_bo = obj; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 7819 | intel_crtc->cursor_width = width; |
| 7820 | intel_crtc->cursor_height = height; |
| 7821 | |
Ville Syrjälä | f2f5f77 | 2013-09-17 18:33:44 +0300 | [diff] [blame] | 7822 | if (intel_crtc->active) |
| 7823 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
Kristian Høgsberg | 3f8bc37 | 2008-12-17 22:14:59 -0500 | [diff] [blame] | 7824 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7825 | return 0; |
Chris Wilson | e7b526b | 2010-06-02 08:30:48 +0100 | [diff] [blame] | 7826 | fail_unpin: |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 7827 | i915_gem_object_unpin_from_display_plane(obj); |
Kristian Høgsberg | 7f9872e | 2009-02-13 20:56:49 -0500 | [diff] [blame] | 7828 | fail_locked: |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 7829 | mutex_unlock(&dev->struct_mutex); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 7830 | fail: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 7831 | drm_gem_object_unreference_unlocked(&obj->base); |
Dave Airlie | 34b8686e | 2009-01-15 14:03:07 +1000 | [diff] [blame] | 7832 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7833 | } |
| 7834 | |
| 7835 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 7836 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7838 | |
Ville Syrjälä | 92e76c8 | 2013-10-21 19:01:58 +0300 | [diff] [blame] | 7839 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
| 7840 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 7841 | |
Ville Syrjälä | f2f5f77 | 2013-09-17 18:33:44 +0300 | [diff] [blame] | 7842 | if (intel_crtc->active) |
| 7843 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7844 | |
| 7845 | return 0; |
| 7846 | } |
| 7847 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7848 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 7849 | u16 *blue, uint32_t start, uint32_t size) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7850 | { |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 7851 | int end = (start + size > 256) ? 256 : start + size, i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7852 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7853 | |
James Simmons | 7203425 | 2010-08-03 01:33:19 +0100 | [diff] [blame] | 7854 | for (i = start; i < end; i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7855 | intel_crtc->lut_r[i] = red[i] >> 8; |
| 7856 | intel_crtc->lut_g[i] = green[i] >> 8; |
| 7857 | intel_crtc->lut_b[i] = blue[i] >> 8; |
| 7858 | } |
| 7859 | |
| 7860 | intel_crtc_load_lut(crtc); |
| 7861 | } |
| 7862 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7863 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 7864 | static struct drm_display_mode load_detect_mode = { |
| 7865 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, |
| 7866 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
| 7867 | }; |
| 7868 | |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 7869 | struct drm_framebuffer * |
| 7870 | __intel_framebuffer_create(struct drm_device *dev, |
| 7871 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 7872 | struct drm_i915_gem_object *obj) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7873 | { |
| 7874 | struct intel_framebuffer *intel_fb; |
| 7875 | int ret; |
| 7876 | |
| 7877 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
| 7878 | if (!intel_fb) { |
| 7879 | drm_gem_object_unreference_unlocked(&obj->base); |
| 7880 | return ERR_PTR(-ENOMEM); |
| 7881 | } |
| 7882 | |
| 7883 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 7884 | if (ret) |
| 7885 | goto err; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7886 | |
| 7887 | return &intel_fb->base; |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 7888 | err: |
| 7889 | drm_gem_object_unreference_unlocked(&obj->base); |
| 7890 | kfree(intel_fb); |
| 7891 | |
| 7892 | return ERR_PTR(ret); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7893 | } |
| 7894 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 7895 | static struct drm_framebuffer * |
Daniel Vetter | a8bb681 | 2014-02-10 18:00:39 +0100 | [diff] [blame] | 7896 | intel_framebuffer_create(struct drm_device *dev, |
| 7897 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 7898 | struct drm_i915_gem_object *obj) |
| 7899 | { |
| 7900 | struct drm_framebuffer *fb; |
| 7901 | int ret; |
| 7902 | |
| 7903 | ret = i915_mutex_lock_interruptible(dev); |
| 7904 | if (ret) |
| 7905 | return ERR_PTR(ret); |
| 7906 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); |
| 7907 | mutex_unlock(&dev->struct_mutex); |
| 7908 | |
| 7909 | return fb; |
| 7910 | } |
| 7911 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7912 | static u32 |
| 7913 | intel_framebuffer_pitch_for_width(int width, int bpp) |
| 7914 | { |
| 7915 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); |
| 7916 | return ALIGN(pitch, 64); |
| 7917 | } |
| 7918 | |
| 7919 | static u32 |
| 7920 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) |
| 7921 | { |
| 7922 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); |
| 7923 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); |
| 7924 | } |
| 7925 | |
| 7926 | static struct drm_framebuffer * |
| 7927 | intel_framebuffer_create_for_mode(struct drm_device *dev, |
| 7928 | struct drm_display_mode *mode, |
| 7929 | int depth, int bpp) |
| 7930 | { |
| 7931 | struct drm_i915_gem_object *obj; |
Chris Wilson | 0fed39b | 2012-11-05 22:25:07 +0000 | [diff] [blame] | 7932 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7933 | |
| 7934 | obj = i915_gem_alloc_object(dev, |
| 7935 | intel_framebuffer_size_for_mode(mode, bpp)); |
| 7936 | if (obj == NULL) |
| 7937 | return ERR_PTR(-ENOMEM); |
| 7938 | |
| 7939 | mode_cmd.width = mode->hdisplay; |
| 7940 | mode_cmd.height = mode->vdisplay; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 7941 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
| 7942 | bpp); |
Dave Airlie | 5ca0c34 | 2012-02-23 15:33:40 +0000 | [diff] [blame] | 7943 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7944 | |
| 7945 | return intel_framebuffer_create(dev, &mode_cmd, obj); |
| 7946 | } |
| 7947 | |
| 7948 | static struct drm_framebuffer * |
| 7949 | mode_fits_in_fbdev(struct drm_device *dev, |
| 7950 | struct drm_display_mode *mode) |
| 7951 | { |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 7952 | #ifdef CONFIG_DRM_I915_FBDEV |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7953 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7954 | struct drm_i915_gem_object *obj; |
| 7955 | struct drm_framebuffer *fb; |
| 7956 | |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 7957 | if (!dev_priv->fbdev) |
| 7958 | return NULL; |
| 7959 | |
| 7960 | if (!dev_priv->fbdev->fb) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7961 | return NULL; |
| 7962 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 7963 | obj = dev_priv->fbdev->fb->obj; |
Daniel Vetter | 4c0e552 | 2014-02-14 16:35:54 +0100 | [diff] [blame] | 7964 | BUG_ON(!obj); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7965 | |
Jesse Barnes | 8bcd455 | 2014-02-07 12:10:38 -0800 | [diff] [blame] | 7966 | fb = &dev_priv->fbdev->fb->base; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7967 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
| 7968 | fb->bits_per_pixel)) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7969 | return NULL; |
| 7970 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 7971 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7972 | return NULL; |
| 7973 | |
| 7974 | return fb; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 7975 | #else |
| 7976 | return NULL; |
| 7977 | #endif |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7978 | } |
| 7979 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 7980 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 7981 | struct drm_display_mode *mode, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 7982 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7983 | { |
| 7984 | struct intel_crtc *intel_crtc; |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 7985 | struct intel_encoder *intel_encoder = |
| 7986 | intel_attached_encoder(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7987 | struct drm_crtc *possible_crtc; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 7988 | struct drm_encoder *encoder = &intel_encoder->base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7989 | struct drm_crtc *crtc = NULL; |
| 7990 | struct drm_device *dev = encoder->dev; |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 7991 | struct drm_framebuffer *fb; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7992 | int i = -1; |
| 7993 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 7994 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 7995 | connector->base.id, drm_get_connector_name(connector), |
| 7996 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 7997 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 7998 | /* |
| 7999 | * Algorithm gets a little messy: |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 8000 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8001 | * - if the connector already has an assigned crtc, use it (but make |
| 8002 | * sure it's on first) |
Chris Wilson | 7a5e480 | 2011-04-19 23:21:12 +0100 | [diff] [blame] | 8003 | * |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8004 | * - try to find the first unused crtc that can drive this connector, |
| 8005 | * and use that if we find one |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8006 | */ |
| 8007 | |
| 8008 | /* See if we already have a CRTC for this connector */ |
| 8009 | if (encoder->crtc) { |
| 8010 | crtc = encoder->crtc; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8011 | |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8012 | mutex_lock(&crtc->mutex); |
| 8013 | |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8014 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8015 | old->load_detect_temp = false; |
| 8016 | |
| 8017 | /* Make sure the crtc and connector are running */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8018 | if (connector->dpms != DRM_MODE_DPMS_ON) |
| 8019 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8020 | |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8021 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8022 | } |
| 8023 | |
| 8024 | /* Find an unused one (if possible) */ |
| 8025 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { |
| 8026 | i++; |
| 8027 | if (!(encoder->possible_crtcs & (1 << i))) |
| 8028 | continue; |
| 8029 | if (!possible_crtc->enabled) { |
| 8030 | crtc = possible_crtc; |
| 8031 | break; |
| 8032 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8033 | } |
| 8034 | |
| 8035 | /* |
| 8036 | * If we didn't find an unused CRTC, don't use any. |
| 8037 | */ |
| 8038 | if (!crtc) { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8039 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
| 8040 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8041 | } |
| 8042 | |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8043 | mutex_lock(&crtc->mutex); |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8044 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
| 8045 | to_intel_connector(connector)->new_encoder = intel_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8046 | |
| 8047 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8048 | intel_crtc->new_enabled = true; |
| 8049 | intel_crtc->new_config = &intel_crtc->config; |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8050 | old->dpms_mode = connector->dpms; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8051 | old->load_detect_temp = true; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8052 | old->release_fb = NULL; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8053 | |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 8054 | if (!mode) |
| 8055 | mode = &load_detect_mode; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8056 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8057 | /* We need a framebuffer large enough to accommodate all accesses |
| 8058 | * that the plane may generate whilst we perform load detection. |
| 8059 | * We can not rely on the fbcon either being present (we get called |
| 8060 | * during its initialisation to detect all boot displays, or it may |
| 8061 | * not even exist) or that it is large enough to satisfy the |
| 8062 | * requested mode. |
| 8063 | */ |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8064 | fb = mode_fits_in_fbdev(dev, mode); |
| 8065 | if (fb == NULL) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8066 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8067 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
| 8068 | old->release_fb = fb; |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8069 | } else |
| 8070 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 8071 | if (IS_ERR(fb)) { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8072 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8073 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8074 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8075 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 8076 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
Chris Wilson | 6492711 | 2011-04-20 07:25:26 +0100 | [diff] [blame] | 8077 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8078 | if (old->release_fb) |
| 8079 | old->release_fb->funcs->destroy(old->release_fb); |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8080 | goto fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8081 | } |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8082 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8083 | /* let the connector get through one full cycle before testing */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8084 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 8085 | return true; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8086 | |
| 8087 | fail: |
| 8088 | intel_crtc->new_enabled = crtc->enabled; |
| 8089 | if (intel_crtc->new_enabled) |
| 8090 | intel_crtc->new_config = &intel_crtc->config; |
| 8091 | else |
| 8092 | intel_crtc->new_config = NULL; |
| 8093 | mutex_unlock(&crtc->mutex); |
| 8094 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8095 | } |
| 8096 | |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8097 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8098 | struct intel_load_detect_pipe *old) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8099 | { |
Daniel Vetter | d2434ab | 2012-08-12 21:20:10 +0200 | [diff] [blame] | 8100 | struct intel_encoder *intel_encoder = |
| 8101 | intel_attached_encoder(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 8102 | struct drm_encoder *encoder = &intel_encoder->base; |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8103 | struct drm_crtc *crtc = encoder->crtc; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8104 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8105 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8106 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 8107 | connector->base.id, drm_get_connector_name(connector), |
| 8108 | encoder->base.id, drm_get_encoder_name(encoder)); |
| 8109 | |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 8110 | if (old->load_detect_temp) { |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8111 | to_intel_connector(connector)->new_encoder = NULL; |
| 8112 | intel_encoder->new_crtc = NULL; |
Ville Syrjälä | 412b61d | 2014-01-17 15:59:39 +0200 | [diff] [blame] | 8113 | intel_crtc->new_enabled = false; |
| 8114 | intel_crtc->new_config = NULL; |
Daniel Vetter | fc30310 | 2012-07-09 10:40:58 +0200 | [diff] [blame] | 8115 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8116 | |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 8117 | if (old->release_fb) { |
| 8118 | drm_framebuffer_unregister_private(old->release_fb); |
| 8119 | drm_framebuffer_unreference(old->release_fb); |
| 8120 | } |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 8121 | |
Daniel Vetter | 67c9640 | 2013-01-23 16:25:09 +0000 | [diff] [blame] | 8122 | mutex_unlock(&crtc->mutex); |
Chris Wilson | 0622a53 | 2011-04-21 09:32:11 +0100 | [diff] [blame] | 8123 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8124 | } |
| 8125 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 8126 | /* Switch crtc and encoder back off if necessary */ |
Daniel Vetter | 24218aa | 2012-08-12 19:27:11 +0200 | [diff] [blame] | 8127 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
| 8128 | connector->funcs->dpms(connector, old->dpms_mode); |
Daniel Vetter | 7b24056 | 2012-12-12 00:35:33 +0100 | [diff] [blame] | 8129 | |
| 8130 | mutex_unlock(&crtc->mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8131 | } |
| 8132 | |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8133 | static int i9xx_pll_refclk(struct drm_device *dev, |
| 8134 | const struct intel_crtc_config *pipe_config) |
| 8135 | { |
| 8136 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8137 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 8138 | |
| 8139 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) |
Ville Syrjälä | e91e941 | 2013-12-09 18:54:16 +0200 | [diff] [blame] | 8140 | return dev_priv->vbt.lvds_ssc_freq; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8141 | else if (HAS_PCH_SPLIT(dev)) |
| 8142 | return 120000; |
| 8143 | else if (!IS_GEN2(dev)) |
| 8144 | return 96000; |
| 8145 | else |
| 8146 | return 48000; |
| 8147 | } |
| 8148 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8149 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8150 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 8151 | struct intel_crtc_config *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8152 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8153 | struct drm_device *dev = crtc->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8154 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8155 | int pipe = pipe_config->cpu_transcoder; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8156 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8157 | u32 fp; |
| 8158 | intel_clock_t clock; |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8159 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8160 | |
| 8161 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8162 | fp = pipe_config->dpll_hw_state.fp0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8163 | else |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8164 | fp = pipe_config->dpll_hw_state.fp1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8165 | |
| 8166 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8167 | if (IS_PINEVIEW(dev)) { |
| 8168 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
| 8169 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 8170 | } else { |
| 8171 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 8172 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 8173 | } |
| 8174 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 8175 | if (!IS_GEN2(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 8176 | if (IS_PINEVIEW(dev)) |
| 8177 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
| 8178 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); |
Shaohua Li | 2177832 | 2009-02-23 15:19:16 +0800 | [diff] [blame] | 8179 | else |
| 8180 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8181 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 8182 | |
| 8183 | switch (dpll & DPLL_MODE_MASK) { |
| 8184 | case DPLLB_MODE_DAC_SERIAL: |
| 8185 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? |
| 8186 | 5 : 10; |
| 8187 | break; |
| 8188 | case DPLLB_MODE_LVDS: |
| 8189 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? |
| 8190 | 7 : 14; |
| 8191 | break; |
| 8192 | default: |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 8193 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8194 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8195 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8196 | } |
| 8197 | |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 8198 | if (IS_PINEVIEW(dev)) |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8199 | pineview_clock(refclk, &clock); |
Daniel Vetter | ac58c3f | 2013-06-01 17:16:17 +0200 | [diff] [blame] | 8200 | else |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8201 | i9xx_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8202 | } else { |
Ville Syrjälä | 0fb5822 | 2014-01-10 14:06:46 +0200 | [diff] [blame] | 8203 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 8204 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8205 | |
| 8206 | if (is_lvds) { |
| 8207 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 8208 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
Ville Syrjälä | b1c560d | 2013-12-09 18:54:13 +0200 | [diff] [blame] | 8209 | |
| 8210 | if (lvds & LVDS_CLKB_POWER_UP) |
| 8211 | clock.p2 = 7; |
| 8212 | else |
| 8213 | clock.p2 = 14; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8214 | } else { |
| 8215 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 8216 | clock.p1 = 2; |
| 8217 | else { |
| 8218 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 8219 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 8220 | } |
| 8221 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 8222 | clock.p2 = 4; |
| 8223 | else |
| 8224 | clock.p2 = 2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8225 | } |
Ville Syrjälä | da4a1ef | 2013-09-09 14:06:37 +0300 | [diff] [blame] | 8226 | |
| 8227 | i9xx_clock(refclk, &clock); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8228 | } |
| 8229 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8230 | /* |
| 8231 | * This value includes pixel_multiplier. We will use |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8232 | * port_clock to compute adjusted_mode.crtc_clock in the |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8233 | * encoder's get_config() function. |
| 8234 | */ |
| 8235 | pipe_config->port_clock = clock.dot; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8236 | } |
| 8237 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8238 | int intel_dotclock_calculate(int link_freq, |
| 8239 | const struct intel_link_m_n *m_n) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8240 | { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8241 | /* |
| 8242 | * The calculation for the data clock is: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8243 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8244 | * But we want to avoid losing precison if possible, so: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8245 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8246 | * |
| 8247 | * and the link clock is simpler: |
Ville Syrjälä | 1041a02 | 2013-09-06 23:28:58 +0300 | [diff] [blame] | 8248 | * link_clock = (m * link_clock) / n |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8249 | */ |
| 8250 | |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8251 | if (!m_n->link_n) |
| 8252 | return 0; |
| 8253 | |
| 8254 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
| 8255 | } |
| 8256 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8257 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
| 8258 | struct intel_crtc_config *pipe_config) |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8259 | { |
| 8260 | struct drm_device *dev = crtc->base.dev; |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8261 | |
| 8262 | /* read out port_clock from the DPLL */ |
| 8263 | i9xx_crtc_clock_get(crtc, pipe_config); |
Ville Syrjälä | 6878da0 | 2013-09-13 15:59:11 +0300 | [diff] [blame] | 8264 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8265 | /* |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8266 | * This value does not include pixel_multiplier. |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8267 | * We will check that port_clock and adjusted_mode.crtc_clock |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8268 | * agree once we know their relationship in the encoder's |
| 8269 | * get_config() function. |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8270 | */ |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 8271 | pipe_config->adjusted_mode.crtc_clock = |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 8272 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
| 8273 | &pipe_config->fdi_m_n); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8274 | } |
| 8275 | |
| 8276 | /** Returns the currently programmed mode of the given pipe. */ |
| 8277 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 8278 | struct drm_crtc *crtc) |
| 8279 | { |
Jesse Barnes | 548f245 | 2011-02-17 10:40:53 -0800 | [diff] [blame] | 8280 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 8282 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8283 | struct drm_display_mode *mode; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8284 | struct intel_crtc_config pipe_config; |
Paulo Zanoni | fe2b8f9 | 2012-10-23 18:30:02 -0200 | [diff] [blame] | 8285 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
| 8286 | int hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 8287 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); |
| 8288 | int vsync = I915_READ(VSYNC(cpu_transcoder)); |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8289 | enum pipe pipe = intel_crtc->pipe; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8290 | |
| 8291 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 8292 | if (!mode) |
| 8293 | return NULL; |
| 8294 | |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8295 | /* |
| 8296 | * Construct a pipe_config sufficient for getting the clock info |
| 8297 | * back out of crtc_clock_get. |
| 8298 | * |
| 8299 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need |
| 8300 | * to use a real value here instead. |
| 8301 | */ |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8302 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8303 | pipe_config.pixel_multiplier = 1; |
Ville Syrjälä | 293623f | 2013-09-13 16:18:46 +0300 | [diff] [blame] | 8304 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
| 8305 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); |
| 8306 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 8307 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
| 8308 | |
Ville Syrjälä | 773ae03 | 2013-09-23 17:48:20 +0300 | [diff] [blame] | 8309 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8310 | mode->hdisplay = (htot & 0xffff) + 1; |
| 8311 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 8312 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 8313 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 8314 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 8315 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 8316 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 8317 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 8318 | |
| 8319 | drm_mode_set_name(mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8320 | |
| 8321 | return mode; |
| 8322 | } |
| 8323 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 8324 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8325 | { |
| 8326 | struct drm_device *dev = crtc->dev; |
| 8327 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 8328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8329 | int pipe = intel_crtc->pipe; |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8330 | int dpll_reg = DPLL(pipe); |
| 8331 | int dpll; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8332 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 8333 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8334 | return; |
| 8335 | |
| 8336 | if (!dev_priv->lvds_downclock_avail) |
| 8337 | return; |
| 8338 | |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8339 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8340 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8341 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8342 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 8343 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8344 | |
| 8345 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; |
| 8346 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8347 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | dbdc647 | 2010-12-30 09:36:39 -0800 | [diff] [blame] | 8348 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8349 | dpll = I915_READ(dpll_reg); |
| 8350 | if (dpll & DISPLAY_RATE_SELECT_FPA1) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8351 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8352 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8353 | } |
| 8354 | |
| 8355 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
| 8356 | { |
| 8357 | struct drm_device *dev = crtc->dev; |
| 8358 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 8359 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8360 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 8361 | if (HAS_PCH_SPLIT(dev)) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8362 | return; |
| 8363 | |
| 8364 | if (!dev_priv->lvds_downclock_avail) |
| 8365 | return; |
| 8366 | |
| 8367 | /* |
| 8368 | * Since this is called by a timer, we should never get here in |
| 8369 | * the manual case. |
| 8370 | */ |
| 8371 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8372 | int pipe = intel_crtc->pipe; |
| 8373 | int dpll_reg = DPLL(pipe); |
Daniel Vetter | dc257cf | 2012-05-07 11:30:46 +0200 | [diff] [blame] | 8374 | int dpll; |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8375 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8376 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8377 | |
Sean Paul | 8ac5a6d | 2012-02-13 13:14:51 -0500 | [diff] [blame] | 8378 | assert_panel_unlocked(dev_priv, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8379 | |
Chris Wilson | 074b5e1 | 2012-05-02 12:07:06 +0100 | [diff] [blame] | 8380 | dpll = I915_READ(dpll_reg); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8381 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
| 8382 | I915_WRITE(dpll_reg, dpll); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 8383 | intel_wait_for_vblank(dev, pipe); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8384 | dpll = I915_READ(dpll_reg); |
| 8385 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 8386 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8387 | } |
| 8388 | |
| 8389 | } |
| 8390 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8391 | void intel_mark_busy(struct drm_device *dev) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8392 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8393 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8394 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8395 | if (dev_priv->mm.busy) |
| 8396 | return; |
| 8397 | |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 8398 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8399 | i915_update_gfx_val(dev_priv); |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8400 | dev_priv->mm.busy = true; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8401 | } |
| 8402 | |
| 8403 | void intel_mark_idle(struct drm_device *dev) |
| 8404 | { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 8405 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 8406 | struct drm_crtc *crtc; |
| 8407 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 8408 | if (!dev_priv->mm.busy) |
| 8409 | return; |
| 8410 | |
| 8411 | dev_priv->mm.busy = false; |
| 8412 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 8413 | if (!i915.powersave) |
Paulo Zanoni | bb4cdd5 | 2014-02-21 13:52:19 -0300 | [diff] [blame] | 8414 | goto out; |
Chris Wilson | 725a5b5 | 2013-01-08 11:02:57 +0000 | [diff] [blame] | 8415 | |
| 8416 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 8417 | if (!crtc->fb) |
| 8418 | continue; |
| 8419 | |
| 8420 | intel_decrease_pllclock(crtc); |
| 8421 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 8422 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 8423 | if (INTEL_INFO(dev)->gen >= 6) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 8424 | gen6_rps_idle(dev->dev_private); |
Paulo Zanoni | bb4cdd5 | 2014-02-21 13:52:19 -0300 | [diff] [blame] | 8425 | |
| 8426 | out: |
Paulo Zanoni | 43694d6 | 2014-03-07 20:08:08 -0300 | [diff] [blame] | 8427 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8428 | } |
| 8429 | |
Chris Wilson | c65355b | 2013-06-06 16:53:41 -0300 | [diff] [blame] | 8430 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
| 8431 | struct intel_ring_buffer *ring) |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 8432 | { |
| 8433 | struct drm_device *dev = obj->base.dev; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8434 | struct drm_crtc *crtc; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8435 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 8436 | if (!i915.powersave) |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8437 | return; |
| 8438 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8439 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8440 | if (!crtc->fb) |
| 8441 | continue; |
| 8442 | |
Chris Wilson | c65355b | 2013-06-06 16:53:41 -0300 | [diff] [blame] | 8443 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
| 8444 | continue; |
| 8445 | |
| 8446 | intel_increase_pllclock(crtc); |
| 8447 | if (ring && intel_fbc_enabled(dev)) |
| 8448 | ring->fbc_dirty = true; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8449 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 8450 | } |
| 8451 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8452 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 8453 | { |
| 8454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 8455 | struct drm_device *dev = crtc->dev; |
| 8456 | struct intel_unpin_work *work; |
| 8457 | unsigned long flags; |
| 8458 | |
| 8459 | spin_lock_irqsave(&dev->event_lock, flags); |
| 8460 | work = intel_crtc->unpin_work; |
| 8461 | intel_crtc->unpin_work = NULL; |
| 8462 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8463 | |
| 8464 | if (work) { |
| 8465 | cancel_work_sync(&work->work); |
| 8466 | kfree(work); |
| 8467 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8468 | |
Mika Kuoppala | 40ccc72 | 2013-04-23 17:27:08 +0300 | [diff] [blame] | 8469 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
| 8470 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8471 | drm_crtc_cleanup(crtc); |
Daniel Vetter | 67e77c5 | 2010-08-20 22:26:30 +0200 | [diff] [blame] | 8472 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 8473 | kfree(intel_crtc); |
| 8474 | } |
| 8475 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8476 | static void intel_unpin_work_fn(struct work_struct *__work) |
| 8477 | { |
| 8478 | struct intel_unpin_work *work = |
| 8479 | container_of(__work, struct intel_unpin_work, work); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8480 | struct drm_device *dev = work->crtc->dev; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8481 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8482 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 8483 | intel_unpin_fb_obj(work->old_fb_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8484 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
| 8485 | drm_gem_object_unreference(&work->old_fb_obj->base); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 8486 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8487 | intel_update_fbc(dev); |
| 8488 | mutex_unlock(&dev->struct_mutex); |
| 8489 | |
| 8490 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
| 8491 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); |
| 8492 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8493 | kfree(work); |
| 8494 | } |
| 8495 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 8496 | static void do_intel_finish_page_flip(struct drm_device *dev, |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 8497 | struct drm_crtc *crtc) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8498 | { |
| 8499 | drm_i915_private_t *dev_priv = dev->dev_private; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8500 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8501 | struct intel_unpin_work *work; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8502 | unsigned long flags; |
| 8503 | |
| 8504 | /* Ignore early vblank irqs */ |
| 8505 | if (intel_crtc == NULL) |
| 8506 | return; |
| 8507 | |
| 8508 | spin_lock_irqsave(&dev->event_lock, flags); |
| 8509 | work = intel_crtc->unpin_work; |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8510 | |
| 8511 | /* Ensure we don't miss a work->pending update ... */ |
| 8512 | smp_rmb(); |
| 8513 | |
| 8514 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8515 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8516 | return; |
| 8517 | } |
| 8518 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8519 | /* and that the unpin work is consistent wrt ->pending. */ |
| 8520 | smp_rmb(); |
| 8521 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8522 | intel_crtc->unpin_work = NULL; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8523 | |
Rob Clark | 45a066e | 2012-10-08 14:50:40 -0500 | [diff] [blame] | 8524 | if (work->event) |
| 8525 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8526 | |
Mario Kleiner | 0af7e4d | 2010-12-08 04:07:19 +0100 | [diff] [blame] | 8527 | drm_vblank_put(dev, intel_crtc->pipe); |
| 8528 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8529 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8530 | |
Daniel Vetter | 2c10d57 | 2012-12-20 21:24:07 +0100 | [diff] [blame] | 8531 | wake_up_all(&dev_priv->pending_flip_queue); |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8532 | |
| 8533 | queue_work(dev_priv->wq, &work->work); |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 8534 | |
| 8535 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8536 | } |
| 8537 | |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 8538 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
| 8539 | { |
| 8540 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 8541 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 8542 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 8543 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 8544 | } |
| 8545 | |
| 8546 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) |
| 8547 | { |
| 8548 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 8549 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
| 8550 | |
Mario Kleiner | 49b14a5 | 2010-12-09 07:00:07 +0100 | [diff] [blame] | 8551 | do_intel_finish_page_flip(dev, crtc); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 8552 | } |
| 8553 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8554 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
| 8555 | { |
| 8556 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 8557 | struct intel_crtc *intel_crtc = |
| 8558 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); |
| 8559 | unsigned long flags; |
| 8560 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8561 | /* NB: An MMIO update of the plane base pointer will also |
| 8562 | * generate a page-flip completion irq, i.e. every modeset |
| 8563 | * is also accompanied by a spurious intel_prepare_page_flip(). |
| 8564 | */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8565 | spin_lock_irqsave(&dev->event_lock, flags); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8566 | if (intel_crtc->unpin_work) |
| 8567 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8568 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8569 | } |
| 8570 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8571 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
| 8572 | { |
| 8573 | /* Ensure that the work item is consistent when activating it ... */ |
| 8574 | smp_wmb(); |
| 8575 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); |
| 8576 | /* and that it is marked active as soon as the irq could fire. */ |
| 8577 | smp_wmb(); |
| 8578 | } |
| 8579 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8580 | static int intel_gen2_queue_flip(struct drm_device *dev, |
| 8581 | struct drm_crtc *crtc, |
| 8582 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8583 | struct drm_i915_gem_object *obj, |
| 8584 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8585 | { |
| 8586 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8587 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8588 | u32 flip_mask; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8589 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8590 | int ret; |
| 8591 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8592 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8593 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8594 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8595 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8596 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8597 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8598 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8599 | |
| 8600 | /* Can't queue multiple flips, so wait for the previous |
| 8601 | * one to finish before executing the next. |
| 8602 | */ |
| 8603 | if (intel_crtc->plane) |
| 8604 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 8605 | else |
| 8606 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8607 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 8608 | intel_ring_emit(ring, MI_NOOP); |
| 8609 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 8610 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 8611 | intel_ring_emit(ring, fb->pitches[0]); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8612 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8613 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8614 | |
| 8615 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 8616 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8617 | return 0; |
| 8618 | |
| 8619 | err_unpin: |
| 8620 | intel_unpin_fb_obj(obj); |
| 8621 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8622 | return ret; |
| 8623 | } |
| 8624 | |
| 8625 | static int intel_gen3_queue_flip(struct drm_device *dev, |
| 8626 | struct drm_crtc *crtc, |
| 8627 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8628 | struct drm_i915_gem_object *obj, |
| 8629 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8630 | { |
| 8631 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8633 | u32 flip_mask; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8634 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8635 | int ret; |
| 8636 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8637 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8638 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8639 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8640 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8641 | ret = intel_ring_begin(ring, 6); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8642 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8643 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8644 | |
| 8645 | if (intel_crtc->plane) |
| 8646 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 8647 | else |
| 8648 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8649 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 8650 | intel_ring_emit(ring, MI_NOOP); |
| 8651 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | |
| 8652 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 8653 | intel_ring_emit(ring, fb->pitches[0]); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8654 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8655 | intel_ring_emit(ring, MI_NOOP); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8656 | |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8657 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 8658 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8659 | return 0; |
| 8660 | |
| 8661 | err_unpin: |
| 8662 | intel_unpin_fb_obj(obj); |
| 8663 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8664 | return ret; |
| 8665 | } |
| 8666 | |
| 8667 | static int intel_gen4_queue_flip(struct drm_device *dev, |
| 8668 | struct drm_crtc *crtc, |
| 8669 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8670 | struct drm_i915_gem_object *obj, |
| 8671 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8672 | { |
| 8673 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8675 | uint32_t pf, pipesrc; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8676 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8677 | int ret; |
| 8678 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8679 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8680 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8681 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8682 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8683 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8684 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8685 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8686 | |
| 8687 | /* i965+ uses the linear or tiled offsets from the |
| 8688 | * Display Registers (which do not change across a page-flip) |
| 8689 | * so we need only reprogram the base address. |
| 8690 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8691 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 8692 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 8693 | intel_ring_emit(ring, fb->pitches[0]); |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 8694 | intel_ring_emit(ring, |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8695 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
Daniel Vetter | c2c7513 | 2012-07-05 12:17:30 +0200 | [diff] [blame] | 8696 | obj->tiling_mode); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8697 | |
| 8698 | /* XXX Enabling the panel-fitter across page-flip is so far |
| 8699 | * untested on non-native modes, so ignore it for now. |
| 8700 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; |
| 8701 | */ |
| 8702 | pf = 0; |
| 8703 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8704 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8705 | |
| 8706 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 8707 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8708 | return 0; |
| 8709 | |
| 8710 | err_unpin: |
| 8711 | intel_unpin_fb_obj(obj); |
| 8712 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8713 | return ret; |
| 8714 | } |
| 8715 | |
| 8716 | static int intel_gen6_queue_flip(struct drm_device *dev, |
| 8717 | struct drm_crtc *crtc, |
| 8718 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8719 | struct drm_i915_gem_object *obj, |
| 8720 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8721 | { |
| 8722 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8724 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8725 | uint32_t pf, pipesrc; |
| 8726 | int ret; |
| 8727 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8728 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8729 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8730 | goto err; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8731 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8732 | ret = intel_ring_begin(ring, 4); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8733 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8734 | goto err_unpin; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8735 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8736 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
| 8737 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
| 8738 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8739 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8740 | |
Chris Wilson | 99d9acd | 2012-04-17 20:37:00 +0100 | [diff] [blame] | 8741 | /* Contrary to the suggestions in the documentation, |
| 8742 | * "Enable Panel Fitter" does not seem to be required when page |
| 8743 | * flipping with a non-native mode, and worse causes a normal |
| 8744 | * modeset to fail. |
| 8745 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; |
| 8746 | */ |
| 8747 | pf = 0; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8748 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 8749 | intel_ring_emit(ring, pf | pipesrc); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8750 | |
| 8751 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 8752 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8753 | return 0; |
| 8754 | |
| 8755 | err_unpin: |
| 8756 | intel_unpin_fb_obj(obj); |
| 8757 | err: |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8758 | return ret; |
| 8759 | } |
| 8760 | |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8761 | static int intel_gen7_queue_flip(struct drm_device *dev, |
| 8762 | struct drm_crtc *crtc, |
| 8763 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8764 | struct drm_i915_gem_object *obj, |
| 8765 | uint32_t flags) |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8766 | { |
| 8767 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 8768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8769 | struct intel_ring_buffer *ring; |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 8770 | uint32_t plane_bit = 0; |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8771 | int len, ret; |
| 8772 | |
| 8773 | ring = obj->ring; |
Chris Wilson | 1c5fd08 | 2013-09-04 10:54:30 +0100 | [diff] [blame] | 8774 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8775 | ring = &dev_priv->ring[BCS]; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8776 | |
| 8777 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
| 8778 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8779 | goto err; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8780 | |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 8781 | switch(intel_crtc->plane) { |
| 8782 | case PLANE_A: |
| 8783 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; |
| 8784 | break; |
| 8785 | case PLANE_B: |
| 8786 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; |
| 8787 | break; |
| 8788 | case PLANE_C: |
| 8789 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; |
| 8790 | break; |
| 8791 | default: |
| 8792 | WARN_ONCE(1, "unknown plane in flip command\n"); |
| 8793 | ret = -ENODEV; |
Eugeni Dodonov | ab3951e | 2012-06-18 19:03:38 -0300 | [diff] [blame] | 8794 | goto err_unpin; |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 8795 | } |
| 8796 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8797 | len = 4; |
| 8798 | if (ring->id == RCS) |
| 8799 | len += 6; |
| 8800 | |
Ville Syrjälä | f66fab8 | 2014-02-11 19:52:06 +0200 | [diff] [blame] | 8801 | /* |
| 8802 | * BSpec MI_DISPLAY_FLIP for IVB: |
| 8803 | * "The full packet must be contained within the same cache line." |
| 8804 | * |
| 8805 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| 8806 | * cacheline, if we ever start emitting more commands before |
| 8807 | * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| 8808 | * then do the cacheline alignment, and finally emit the |
| 8809 | * MI_DISPLAY_FLIP. |
| 8810 | */ |
| 8811 | ret = intel_ring_cacheline_align(ring); |
| 8812 | if (ret) |
| 8813 | goto err_unpin; |
| 8814 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8815 | ret = intel_ring_begin(ring, len); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8816 | if (ret) |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8817 | goto err_unpin; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8818 | |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8819 | /* Unmask the flip-done completion message. Note that the bspec says that |
| 8820 | * we should do this for both the BCS and RCS, and that we must not unmask |
| 8821 | * more than one flip event at any time (or ensure that one flip message |
| 8822 | * can be sent by waiting for flip-done prior to queueing new flips). |
| 8823 | * Experimentation says that BCS works despite DERRMR masking all |
| 8824 | * flip-done completion events and that unmasking all planes at once |
| 8825 | * for the RCS also doesn't appear to drop events. Setting the DERRMR |
| 8826 | * to zero does lead to lockups within MI_DISPLAY_FLIP. |
| 8827 | */ |
| 8828 | if (ring->id == RCS) { |
| 8829 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 8830 | intel_ring_emit(ring, DERRMR); |
| 8831 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
| 8832 | DERRMR_PIPEB_PRI_FLIP_DONE | |
| 8833 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
Ville Syrjälä | 22613c9 | 2013-11-29 13:13:42 +0200 | [diff] [blame] | 8834 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
| 8835 | MI_SRM_LRM_GLOBAL_GTT); |
Chris Wilson | ffe74d7 | 2013-08-26 20:58:12 +0100 | [diff] [blame] | 8836 | intel_ring_emit(ring, DERRMR); |
| 8837 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
| 8838 | } |
| 8839 | |
Daniel Vetter | cb05d8d | 2012-05-23 14:02:00 +0200 | [diff] [blame] | 8840 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 8841 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 8842 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8843 | intel_ring_emit(ring, (MI_NOOP)); |
Chris Wilson | e7d841c | 2012-12-03 11:36:30 +0000 | [diff] [blame] | 8844 | |
| 8845 | intel_mark_page_flip_active(intel_crtc); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 8846 | __intel_ring_advance(ring); |
Chris Wilson | 83d4092 | 2012-04-17 19:35:53 +0100 | [diff] [blame] | 8847 | return 0; |
| 8848 | |
| 8849 | err_unpin: |
| 8850 | intel_unpin_fb_obj(obj); |
| 8851 | err: |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 8852 | return ret; |
| 8853 | } |
| 8854 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8855 | static int intel_default_queue_flip(struct drm_device *dev, |
| 8856 | struct drm_crtc *crtc, |
| 8857 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8858 | struct drm_i915_gem_object *obj, |
| 8859 | uint32_t flags) |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8860 | { |
| 8861 | return -ENODEV; |
| 8862 | } |
| 8863 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8864 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
| 8865 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8866 | struct drm_pending_vblank_event *event, |
| 8867 | uint32_t page_flip_flags) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8868 | { |
| 8869 | struct drm_device *dev = crtc->dev; |
| 8870 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 4a35f83 | 2013-02-22 16:53:38 +0200 | [diff] [blame] | 8871 | struct drm_framebuffer *old_fb = crtc->fb; |
| 8872 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 8874 | struct intel_unpin_work *work; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8875 | unsigned long flags; |
Chris Wilson | 52e6863 | 2010-08-08 10:15:59 +0100 | [diff] [blame] | 8876 | int ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8877 | |
Ville Syrjälä | e6a595d | 2012-05-24 21:08:59 +0300 | [diff] [blame] | 8878 | /* Can't change pixel format via MI display flips. */ |
| 8879 | if (fb->pixel_format != crtc->fb->pixel_format) |
| 8880 | return -EINVAL; |
| 8881 | |
| 8882 | /* |
| 8883 | * TILEOFF/LINOFF registers can't be changed via MI display flips. |
| 8884 | * Note that pitch changes could also affect these register. |
| 8885 | */ |
| 8886 | if (INTEL_INFO(dev)->gen > 3 && |
| 8887 | (fb->offsets[0] != crtc->fb->offsets[0] || |
| 8888 | fb->pitches[0] != crtc->fb->pitches[0])) |
| 8889 | return -EINVAL; |
| 8890 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 8891 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 8892 | goto out_hang; |
| 8893 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 8894 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8895 | if (work == NULL) |
| 8896 | return -ENOMEM; |
| 8897 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8898 | work->event = event; |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8899 | work->crtc = crtc; |
Ville Syrjälä | 4a35f83 | 2013-02-22 16:53:38 +0200 | [diff] [blame] | 8900 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8901 | INIT_WORK(&work->work, intel_unpin_work_fn); |
| 8902 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 8903 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
| 8904 | if (ret) |
| 8905 | goto free_work; |
| 8906 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8907 | /* We borrow the event spin lock for protecting unpin_work */ |
| 8908 | spin_lock_irqsave(&dev->event_lock, flags); |
| 8909 | if (intel_crtc->unpin_work) { |
| 8910 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8911 | kfree(work); |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 8912 | drm_vblank_put(dev, intel_crtc->pipe); |
Chris Wilson | 468f0b4 | 2010-05-27 13:18:13 +0100 | [diff] [blame] | 8913 | |
| 8914 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8915 | return -EBUSY; |
| 8916 | } |
| 8917 | intel_crtc->unpin_work = work; |
| 8918 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8919 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8920 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
| 8921 | flush_workqueue(dev_priv->wq); |
| 8922 | |
Chris Wilson | 7915810 | 2012-05-23 11:13:58 +0100 | [diff] [blame] | 8923 | ret = i915_mutex_lock_interruptible(dev); |
| 8924 | if (ret) |
| 8925 | goto cleanup; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8926 | |
Jesse Barnes | 75dfca8 | 2010-02-10 15:09:44 -0800 | [diff] [blame] | 8927 | /* Reference the objects for the scheduled work. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8928 | drm_gem_object_reference(&work->old_fb_obj->base); |
| 8929 | drm_gem_object_reference(&obj->base); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8930 | |
| 8931 | crtc->fb = fb; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8932 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 8933 | work->pending_flip_obj = obj; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 8934 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 8935 | work->enable_stall_check = true; |
| 8936 | |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8937 | atomic_inc(&intel_crtc->unpin_work_count); |
Ville Syrjälä | 10d8373 | 2013-01-29 18:13:34 +0200 | [diff] [blame] | 8938 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 8939 | |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 8940 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8941 | if (ret) |
| 8942 | goto cleanup_pending; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8943 | |
Chris Wilson | 7782de3 | 2011-07-08 12:22:41 +0100 | [diff] [blame] | 8944 | intel_disable_fbc(dev); |
Chris Wilson | c65355b | 2013-06-06 16:53:41 -0300 | [diff] [blame] | 8945 | intel_mark_fb_busy(obj, NULL); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8946 | mutex_unlock(&dev->struct_mutex); |
| 8947 | |
Jesse Barnes | e5510fa | 2010-07-01 16:48:37 -0700 | [diff] [blame] | 8948 | trace_i915_flip_request(intel_crtc->plane, obj); |
| 8949 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8950 | return 0; |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8951 | |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 8952 | cleanup_pending: |
Chris Wilson | b4a98e5 | 2012-11-01 09:26:26 +0000 | [diff] [blame] | 8953 | atomic_dec(&intel_crtc->unpin_work_count); |
Ville Syrjälä | 4a35f83 | 2013-02-22 16:53:38 +0200 | [diff] [blame] | 8954 | crtc->fb = old_fb; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 8955 | drm_gem_object_unreference(&work->old_fb_obj->base); |
| 8956 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8957 | mutex_unlock(&dev->struct_mutex); |
| 8958 | |
Chris Wilson | 7915810 | 2012-05-23 11:13:58 +0100 | [diff] [blame] | 8959 | cleanup: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8960 | spin_lock_irqsave(&dev->event_lock, flags); |
| 8961 | intel_crtc->unpin_work = NULL; |
| 8962 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 8963 | |
Jesse Barnes | 7317c75e6 | 2011-08-29 09:45:28 -0700 | [diff] [blame] | 8964 | drm_vblank_put(dev, intel_crtc->pipe); |
| 8965 | free_work: |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8966 | kfree(work); |
| 8967 | |
Chris Wilson | f900db4 | 2014-02-20 09:26:13 +0000 | [diff] [blame] | 8968 | if (ret == -EIO) { |
| 8969 | out_hang: |
| 8970 | intel_crtc_wait_for_pending_flips(crtc); |
| 8971 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); |
| 8972 | if (ret == 0 && event) |
| 8973 | drm_send_vblank_event(dev, intel_crtc->pipe, event); |
| 8974 | } |
Chris Wilson | 96b099f | 2010-06-07 14:03:04 +0100 | [diff] [blame] | 8975 | return ret; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 8976 | } |
| 8977 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 8978 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 8979 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
| 8980 | .load_lut = intel_crtc_load_lut, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 8981 | }; |
| 8982 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 8983 | /** |
| 8984 | * intel_modeset_update_staged_output_state |
| 8985 | * |
| 8986 | * Updates the staged output configuration state, e.g. after we've read out the |
| 8987 | * current hw state. |
| 8988 | */ |
| 8989 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) |
| 8990 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 8991 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 8992 | struct intel_encoder *encoder; |
| 8993 | struct intel_connector *connector; |
| 8994 | |
| 8995 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 8996 | base.head) { |
| 8997 | connector->new_encoder = |
| 8998 | to_intel_encoder(connector->base.encoder); |
| 8999 | } |
| 9000 | |
| 9001 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9002 | base.head) { |
| 9003 | encoder->new_crtc = |
| 9004 | to_intel_crtc(encoder->base.crtc); |
| 9005 | } |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9006 | |
| 9007 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 9008 | base.head) { |
| 9009 | crtc->new_enabled = crtc->base.enabled; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 9010 | |
| 9011 | if (crtc->new_enabled) |
| 9012 | crtc->new_config = &crtc->config; |
| 9013 | else |
| 9014 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9015 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9016 | } |
| 9017 | |
| 9018 | /** |
| 9019 | * intel_modeset_commit_output_state |
| 9020 | * |
| 9021 | * This function copies the stage display pipe configuration to the real one. |
| 9022 | */ |
| 9023 | static void intel_modeset_commit_output_state(struct drm_device *dev) |
| 9024 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9025 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9026 | struct intel_encoder *encoder; |
| 9027 | struct intel_connector *connector; |
| 9028 | |
| 9029 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9030 | base.head) { |
| 9031 | connector->base.encoder = &connector->new_encoder->base; |
| 9032 | } |
| 9033 | |
| 9034 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9035 | base.head) { |
| 9036 | encoder->base.crtc = &encoder->new_crtc->base; |
| 9037 | } |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9038 | |
| 9039 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 9040 | base.head) { |
| 9041 | crtc->base.enabled = crtc->new_enabled; |
| 9042 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 9043 | } |
| 9044 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9045 | static void |
| 9046 | connected_sink_compute_bpp(struct intel_connector * connector, |
| 9047 | struct intel_crtc_config *pipe_config) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9048 | { |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9049 | int bpp = pipe_config->pipe_bpp; |
| 9050 | |
| 9051 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", |
| 9052 | connector->base.base.id, |
| 9053 | drm_get_connector_name(&connector->base)); |
| 9054 | |
| 9055 | /* Don't use an invalid EDID bpc value */ |
| 9056 | if (connector->base.display_info.bpc && |
| 9057 | connector->base.display_info.bpc * 3 < bpp) { |
| 9058 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
| 9059 | bpp, connector->base.display_info.bpc*3); |
| 9060 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; |
| 9061 | } |
| 9062 | |
| 9063 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
| 9064 | if (connector->base.display_info.bpc == 0 && bpp > 24) { |
| 9065 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
| 9066 | bpp); |
| 9067 | pipe_config->pipe_bpp = 24; |
| 9068 | } |
| 9069 | } |
| 9070 | |
| 9071 | static int |
| 9072 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
| 9073 | struct drm_framebuffer *fb, |
| 9074 | struct intel_crtc_config *pipe_config) |
| 9075 | { |
| 9076 | struct drm_device *dev = crtc->base.dev; |
| 9077 | struct intel_connector *connector; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9078 | int bpp; |
| 9079 | |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 9080 | switch (fb->pixel_format) { |
| 9081 | case DRM_FORMAT_C8: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9082 | bpp = 8*3; /* since we go through a colormap */ |
| 9083 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 9084 | case DRM_FORMAT_XRGB1555: |
| 9085 | case DRM_FORMAT_ARGB1555: |
| 9086 | /* checked in intel_framebuffer_init already */ |
| 9087 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) |
| 9088 | return -EINVAL; |
| 9089 | case DRM_FORMAT_RGB565: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9090 | bpp = 6*3; /* min is 18bpp */ |
| 9091 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 9092 | case DRM_FORMAT_XBGR8888: |
| 9093 | case DRM_FORMAT_ABGR8888: |
| 9094 | /* checked in intel_framebuffer_init already */ |
| 9095 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
| 9096 | return -EINVAL; |
| 9097 | case DRM_FORMAT_XRGB8888: |
| 9098 | case DRM_FORMAT_ARGB8888: |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9099 | bpp = 8*3; |
| 9100 | break; |
Daniel Vetter | d42264b | 2013-03-28 16:38:08 +0100 | [diff] [blame] | 9101 | case DRM_FORMAT_XRGB2101010: |
| 9102 | case DRM_FORMAT_ARGB2101010: |
| 9103 | case DRM_FORMAT_XBGR2101010: |
| 9104 | case DRM_FORMAT_ABGR2101010: |
| 9105 | /* checked in intel_framebuffer_init already */ |
| 9106 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 9107 | return -EINVAL; |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9108 | bpp = 10*3; |
| 9109 | break; |
Daniel Vetter | baba133 | 2013-03-27 00:45:00 +0100 | [diff] [blame] | 9110 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9111 | default: |
| 9112 | DRM_DEBUG_KMS("unsupported depth\n"); |
| 9113 | return -EINVAL; |
| 9114 | } |
| 9115 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9116 | pipe_config->pipe_bpp = bpp; |
| 9117 | |
| 9118 | /* Clamp display bpp to EDID value */ |
| 9119 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9120 | base.head) { |
Daniel Vetter | 1b829e0 | 2013-06-02 13:26:24 +0200 | [diff] [blame] | 9121 | if (!connector->new_encoder || |
| 9122 | connector->new_encoder->new_crtc != crtc) |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9123 | continue; |
| 9124 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9125 | connected_sink_compute_bpp(connector, pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9126 | } |
| 9127 | |
| 9128 | return bpp; |
| 9129 | } |
| 9130 | |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 9131 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
| 9132 | { |
| 9133 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " |
| 9134 | "type: 0x%x flags: 0x%x\n", |
Damien Lespiau | 1342830 | 2013-09-25 16:45:36 +0100 | [diff] [blame] | 9135 | mode->crtc_clock, |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 9136 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
| 9137 | mode->crtc_hsync_end, mode->crtc_htotal, |
| 9138 | mode->crtc_vdisplay, mode->crtc_vsync_start, |
| 9139 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); |
| 9140 | } |
| 9141 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9142 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
| 9143 | struct intel_crtc_config *pipe_config, |
| 9144 | const char *context) |
| 9145 | { |
| 9146 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, |
| 9147 | context, pipe_name(crtc->pipe)); |
| 9148 | |
| 9149 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); |
| 9150 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
| 9151 | pipe_config->pipe_bpp, pipe_config->dither); |
| 9152 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 9153 | pipe_config->has_pch_encoder, |
| 9154 | pipe_config->fdi_lanes, |
| 9155 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, |
| 9156 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, |
| 9157 | pipe_config->fdi_m_n.tu); |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9158 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
| 9159 | pipe_config->has_dp_encoder, |
| 9160 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
| 9161 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, |
| 9162 | pipe_config->dp_m_n.tu); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9163 | DRM_DEBUG_KMS("requested mode:\n"); |
| 9164 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); |
| 9165 | DRM_DEBUG_KMS("adjusted mode:\n"); |
| 9166 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); |
Daniel Vetter | 644db71 | 2013-09-19 14:53:58 +0200 | [diff] [blame] | 9167 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
Ville Syrjälä | d71b8d4 | 2013-09-06 23:29:08 +0300 | [diff] [blame] | 9168 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 9169 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
| 9170 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9171 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
| 9172 | pipe_config->gmch_pfit.control, |
| 9173 | pipe_config->gmch_pfit.pgm_ratios, |
| 9174 | pipe_config->gmch_pfit.lvds_border_bits); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 9175 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9176 | pipe_config->pch_pfit.pos, |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 9177 | pipe_config->pch_pfit.size, |
| 9178 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 9179 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
Ville Syrjälä | cf532bb | 2013-09-04 18:30:02 +0300 | [diff] [blame] | 9180 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9181 | } |
| 9182 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9183 | static bool encoders_cloneable(const struct intel_encoder *a, |
| 9184 | const struct intel_encoder *b) |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9185 | { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9186 | /* masks could be asymmetric, so check both ways */ |
| 9187 | return a == b || (a->cloneable & (1 << b->type) && |
| 9188 | b->cloneable & (1 << a->type)); |
| 9189 | } |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9190 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9191 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, |
| 9192 | struct intel_encoder *encoder) |
| 9193 | { |
| 9194 | struct drm_device *dev = crtc->base.dev; |
| 9195 | struct intel_encoder *source_encoder; |
| 9196 | |
| 9197 | list_for_each_entry(source_encoder, |
| 9198 | &dev->mode_config.encoder_list, base.head) { |
| 9199 | if (source_encoder->new_crtc != crtc) |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9200 | continue; |
| 9201 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9202 | if (!encoders_cloneable(encoder, source_encoder)) |
| 9203 | return false; |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9204 | } |
| 9205 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9206 | return true; |
| 9207 | } |
| 9208 | |
| 9209 | static bool check_encoder_cloning(struct intel_crtc *crtc) |
| 9210 | { |
| 9211 | struct drm_device *dev = crtc->base.dev; |
| 9212 | struct intel_encoder *encoder; |
| 9213 | |
| 9214 | list_for_each_entry(encoder, |
| 9215 | &dev->mode_config.encoder_list, base.head) { |
| 9216 | if (encoder->new_crtc != crtc) |
| 9217 | continue; |
| 9218 | |
| 9219 | if (!check_single_encoder_cloning(crtc, encoder)) |
| 9220 | return false; |
| 9221 | } |
| 9222 | |
| 9223 | return true; |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9224 | } |
| 9225 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9226 | static struct intel_crtc_config * |
| 9227 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9228 | struct drm_framebuffer *fb, |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9229 | struct drm_display_mode *mode) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9230 | { |
| 9231 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9232 | struct intel_encoder *encoder; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9233 | struct intel_crtc_config *pipe_config; |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 9234 | int plane_bpp, ret = -EINVAL; |
| 9235 | bool retry = true; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9236 | |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 9237 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
Daniel Vetter | accfc0c | 2013-05-30 15:04:25 +0200 | [diff] [blame] | 9238 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
| 9239 | return ERR_PTR(-EINVAL); |
| 9240 | } |
| 9241 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9242 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
| 9243 | if (!pipe_config) |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9244 | return ERR_PTR(-ENOMEM); |
| 9245 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9246 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
| 9247 | drm_mode_copy(&pipe_config->requested_mode, mode); |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 9248 | |
Daniel Vetter | e143a21 | 2013-07-04 12:01:15 +0200 | [diff] [blame] | 9249 | pipe_config->cpu_transcoder = |
| 9250 | (enum transcoder) to_intel_crtc(crtc)->pipe; |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9251 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9252 | |
Imre Deak | 2960bc9 | 2013-07-30 13:36:32 +0300 | [diff] [blame] | 9253 | /* |
| 9254 | * Sanitize sync polarity flags based on requested ones. If neither |
| 9255 | * positive or negative polarity is requested, treat this as meaning |
| 9256 | * negative polarity. |
| 9257 | */ |
| 9258 | if (!(pipe_config->adjusted_mode.flags & |
| 9259 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
| 9260 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
| 9261 | |
| 9262 | if (!(pipe_config->adjusted_mode.flags & |
| 9263 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
| 9264 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 9265 | |
Daniel Vetter | 050f7ae | 2013-06-02 13:26:23 +0200 | [diff] [blame] | 9266 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
| 9267 | * plane pixel format and any sink constraints into account. Returns the |
| 9268 | * source plane bpp so that dithering can be selected on mismatches |
| 9269 | * after encoders and crtc also have had their say. */ |
| 9270 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
| 9271 | fb, pipe_config); |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9272 | if (plane_bpp < 0) |
| 9273 | goto fail; |
| 9274 | |
Ville Syrjälä | e41a56b | 2013-10-01 22:52:14 +0300 | [diff] [blame] | 9275 | /* |
| 9276 | * Determine the real pipe dimensions. Note that stereo modes can |
| 9277 | * increase the actual pipe size due to the frame doubling and |
| 9278 | * insertion of additional space for blanks between the frame. This |
| 9279 | * is stored in the crtc timings. We use the requested mode to do this |
| 9280 | * computation to clearly distinguish it from the adjusted mode, which |
| 9281 | * can be changed by the connectors in the below retry loop. |
| 9282 | */ |
| 9283 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); |
| 9284 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; |
| 9285 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; |
| 9286 | |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 9287 | encoder_retry: |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 9288 | /* Ensure the port clock defaults are reset when retrying. */ |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 9289 | pipe_config->port_clock = 0; |
Daniel Vetter | ef1b460 | 2013-06-01 17:17:04 +0200 | [diff] [blame] | 9290 | pipe_config->pixel_multiplier = 1; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 9291 | |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 9292 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
Damien Lespiau | 6ce70f5 | 2013-09-25 16:45:38 +0100 | [diff] [blame] | 9293 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
Daniel Vetter | 135c81b | 2013-07-21 21:37:09 +0200 | [diff] [blame] | 9294 | |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9295 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 9296 | * adjust it according to limitations or connector properties, and also |
| 9297 | * a chance to reject the mode entirely. |
| 9298 | */ |
| 9299 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9300 | base.head) { |
| 9301 | |
| 9302 | if (&encoder->new_crtc->base != crtc) |
| 9303 | continue; |
Daniel Vetter | 7ae8923 | 2013-03-27 00:44:52 +0100 | [diff] [blame] | 9304 | |
Daniel Vetter | efea6e8 | 2013-07-21 21:36:59 +0200 | [diff] [blame] | 9305 | if (!(encoder->compute_config(encoder, pipe_config))) { |
| 9306 | DRM_DEBUG_KMS("Encoder config failure\n"); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9307 | goto fail; |
| 9308 | } |
| 9309 | } |
| 9310 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 9311 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 9312 | * done afterwards in case the encoder adjusts the mode. */ |
| 9313 | if (!pipe_config->port_clock) |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 9314 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
| 9315 | * pipe_config->pixel_multiplier; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 9316 | |
Daniel Vetter | a43f6e0 | 2013-06-07 23:10:32 +0200 | [diff] [blame] | 9317 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 9318 | if (ret < 0) { |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9319 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
| 9320 | goto fail; |
| 9321 | } |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 9322 | |
| 9323 | if (ret == RETRY) { |
| 9324 | if (WARN(!retry, "loop in pipe configuration computation\n")) { |
| 9325 | ret = -EINVAL; |
| 9326 | goto fail; |
| 9327 | } |
| 9328 | |
| 9329 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); |
| 9330 | retry = false; |
| 9331 | goto encoder_retry; |
| 9332 | } |
| 9333 | |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9334 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
| 9335 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
| 9336 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
| 9337 | |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9338 | return pipe_config; |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9339 | fail: |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9340 | kfree(pipe_config); |
Daniel Vetter | e29c22c | 2013-02-21 00:00:16 +0100 | [diff] [blame] | 9341 | return ERR_PTR(ret); |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9342 | } |
| 9343 | |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9344 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
| 9345 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ |
| 9346 | static void |
| 9347 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, |
| 9348 | unsigned *prepare_pipes, unsigned *disable_pipes) |
| 9349 | { |
| 9350 | struct intel_crtc *intel_crtc; |
| 9351 | struct drm_device *dev = crtc->dev; |
| 9352 | struct intel_encoder *encoder; |
| 9353 | struct intel_connector *connector; |
| 9354 | struct drm_crtc *tmp_crtc; |
| 9355 | |
| 9356 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
| 9357 | |
| 9358 | /* Check which crtcs have changed outputs connected to them, these need |
| 9359 | * to be part of the prepare_pipes mask. We don't (yet) support global |
| 9360 | * modeset across multiple crtcs, so modeset_pipes will only have one |
| 9361 | * bit set at most. */ |
| 9362 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9363 | base.head) { |
| 9364 | if (connector->base.encoder == &connector->new_encoder->base) |
| 9365 | continue; |
| 9366 | |
| 9367 | if (connector->base.encoder) { |
| 9368 | tmp_crtc = connector->base.encoder->crtc; |
| 9369 | |
| 9370 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
| 9371 | } |
| 9372 | |
| 9373 | if (connector->new_encoder) |
| 9374 | *prepare_pipes |= |
| 9375 | 1 << connector->new_encoder->new_crtc->pipe; |
| 9376 | } |
| 9377 | |
| 9378 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9379 | base.head) { |
| 9380 | if (encoder->base.crtc == &encoder->new_crtc->base) |
| 9381 | continue; |
| 9382 | |
| 9383 | if (encoder->base.crtc) { |
| 9384 | tmp_crtc = encoder->base.crtc; |
| 9385 | |
| 9386 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; |
| 9387 | } |
| 9388 | |
| 9389 | if (encoder->new_crtc) |
| 9390 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; |
| 9391 | } |
| 9392 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9393 | /* Check for pipes that will be enabled/disabled ... */ |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9394 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 9395 | base.head) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9396 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9397 | continue; |
| 9398 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9399 | if (!intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9400 | *disable_pipes |= 1 << intel_crtc->pipe; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9401 | else |
| 9402 | *prepare_pipes |= 1 << intel_crtc->pipe; |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9403 | } |
| 9404 | |
| 9405 | |
| 9406 | /* set_mode is also used to update properties on life display pipes. */ |
| 9407 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9408 | if (intel_crtc->new_enabled) |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9409 | *prepare_pipes |= 1 << intel_crtc->pipe; |
| 9410 | |
Daniel Vetter | b6c5164 | 2013-04-12 18:48:43 +0200 | [diff] [blame] | 9411 | /* |
| 9412 | * For simplicity do a full modeset on any pipe where the output routing |
| 9413 | * changed. We could be more clever, but that would require us to be |
| 9414 | * more careful with calling the relevant encoder->mode_set functions. |
| 9415 | */ |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9416 | if (*prepare_pipes) |
| 9417 | *modeset_pipes = *prepare_pipes; |
| 9418 | |
| 9419 | /* ... and mask these out. */ |
| 9420 | *modeset_pipes &= ~(*disable_pipes); |
| 9421 | *prepare_pipes &= ~(*disable_pipes); |
Daniel Vetter | b6c5164 | 2013-04-12 18:48:43 +0200 | [diff] [blame] | 9422 | |
| 9423 | /* |
| 9424 | * HACK: We don't (yet) fully support global modesets. intel_set_config |
| 9425 | * obies this rule, but the modeset restore mode of |
| 9426 | * intel_modeset_setup_hw_state does not. |
| 9427 | */ |
| 9428 | *modeset_pipes &= 1 << intel_crtc->pipe; |
| 9429 | *prepare_pipes &= 1 << intel_crtc->pipe; |
Daniel Vetter | e3641d3 | 2013-04-11 19:49:07 +0200 | [diff] [blame] | 9430 | |
| 9431 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", |
| 9432 | *modeset_pipes, *prepare_pipes, *disable_pipes); |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9433 | } |
| 9434 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9435 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
| 9436 | { |
| 9437 | struct drm_encoder *encoder; |
| 9438 | struct drm_device *dev = crtc->dev; |
| 9439 | |
| 9440 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
| 9441 | if (encoder->crtc == crtc) |
| 9442 | return true; |
| 9443 | |
| 9444 | return false; |
| 9445 | } |
| 9446 | |
| 9447 | static void |
| 9448 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) |
| 9449 | { |
| 9450 | struct intel_encoder *intel_encoder; |
| 9451 | struct intel_crtc *intel_crtc; |
| 9452 | struct drm_connector *connector; |
| 9453 | |
| 9454 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, |
| 9455 | base.head) { |
| 9456 | if (!intel_encoder->base.crtc) |
| 9457 | continue; |
| 9458 | |
| 9459 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); |
| 9460 | |
| 9461 | if (prepare_pipes & (1 << intel_crtc->pipe)) |
| 9462 | intel_encoder->connectors_active = false; |
| 9463 | } |
| 9464 | |
| 9465 | intel_modeset_commit_output_state(dev); |
| 9466 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9467 | /* Double check state. */ |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9468 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
| 9469 | base.head) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 9470 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 9471 | WARN_ON(intel_crtc->new_config && |
| 9472 | intel_crtc->new_config != &intel_crtc->config); |
| 9473 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9474 | } |
| 9475 | |
| 9476 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 9477 | if (!connector->encoder || !connector->encoder->crtc) |
| 9478 | continue; |
| 9479 | |
| 9480 | intel_crtc = to_intel_crtc(connector->encoder->crtc); |
| 9481 | |
| 9482 | if (prepare_pipes & (1 << intel_crtc->pipe)) { |
Daniel Vetter | 68d3472 | 2012-09-06 22:08:35 +0200 | [diff] [blame] | 9483 | struct drm_property *dpms_property = |
| 9484 | dev->mode_config.dpms_property; |
| 9485 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9486 | connector->dpms = DRM_MODE_DPMS_ON; |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 9487 | drm_object_property_set_value(&connector->base, |
Daniel Vetter | 68d3472 | 2012-09-06 22:08:35 +0200 | [diff] [blame] | 9488 | dpms_property, |
| 9489 | DRM_MODE_DPMS_ON); |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9490 | |
| 9491 | intel_encoder = to_intel_encoder(connector->encoder); |
| 9492 | intel_encoder->connectors_active = true; |
| 9493 | } |
| 9494 | } |
| 9495 | |
| 9496 | } |
| 9497 | |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 9498 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 9499 | { |
Ville Syrjälä | 3bd2626 | 2013-09-06 23:29:02 +0300 | [diff] [blame] | 9500 | int diff; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 9501 | |
| 9502 | if (clock1 == clock2) |
| 9503 | return true; |
| 9504 | |
| 9505 | if (!clock1 || !clock2) |
| 9506 | return false; |
| 9507 | |
| 9508 | diff = abs(clock1 - clock2); |
| 9509 | |
| 9510 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 9511 | return true; |
| 9512 | |
| 9513 | return false; |
| 9514 | } |
| 9515 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9516 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
| 9517 | list_for_each_entry((intel_crtc), \ |
| 9518 | &(dev)->mode_config.crtc_list, \ |
| 9519 | base.head) \ |
Daniel Vetter | 0973f18 | 2013-04-19 11:25:33 +0200 | [diff] [blame] | 9520 | if (mask & (1 <<(intel_crtc)->pipe)) |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9521 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9522 | static bool |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9523 | intel_pipe_config_compare(struct drm_device *dev, |
| 9524 | struct intel_crtc_config *current_config, |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9525 | struct intel_crtc_config *pipe_config) |
| 9526 | { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9527 | #define PIPE_CONF_CHECK_X(name) \ |
| 9528 | if (current_config->name != pipe_config->name) { \ |
| 9529 | DRM_ERROR("mismatch in " #name " " \ |
| 9530 | "(expected 0x%08x, found 0x%08x)\n", \ |
| 9531 | current_config->name, \ |
| 9532 | pipe_config->name); \ |
| 9533 | return false; \ |
| 9534 | } |
| 9535 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 9536 | #define PIPE_CONF_CHECK_I(name) \ |
| 9537 | if (current_config->name != pipe_config->name) { \ |
| 9538 | DRM_ERROR("mismatch in " #name " " \ |
| 9539 | "(expected %i, found %i)\n", \ |
| 9540 | current_config->name, \ |
| 9541 | pipe_config->name); \ |
| 9542 | return false; \ |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 9543 | } |
| 9544 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9545 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
| 9546 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
Jesse Barnes | 6f02488 | 2013-07-01 10:19:09 -0700 | [diff] [blame] | 9547 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9548 | "(expected %i, found %i)\n", \ |
| 9549 | current_config->name & (mask), \ |
| 9550 | pipe_config->name & (mask)); \ |
| 9551 | return false; \ |
| 9552 | } |
| 9553 | |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 9554 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
| 9555 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
| 9556 | DRM_ERROR("mismatch in " #name " " \ |
| 9557 | "(expected %i, found %i)\n", \ |
| 9558 | current_config->name, \ |
| 9559 | pipe_config->name); \ |
| 9560 | return false; \ |
| 9561 | } |
| 9562 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 9563 | #define PIPE_CONF_QUIRK(quirk) \ |
| 9564 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 9565 | |
Daniel Vetter | eccb140 | 2013-05-22 00:50:22 +0200 | [diff] [blame] | 9566 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 9567 | |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 9568 | PIPE_CONF_CHECK_I(has_pch_encoder); |
| 9569 | PIPE_CONF_CHECK_I(fdi_lanes); |
Daniel Vetter | 7241920 | 2013-04-04 13:28:53 +0200 | [diff] [blame] | 9570 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
| 9571 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); |
| 9572 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); |
| 9573 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); |
| 9574 | PIPE_CONF_CHECK_I(fdi_m_n.tu); |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 9575 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 9576 | PIPE_CONF_CHECK_I(has_dp_encoder); |
| 9577 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); |
| 9578 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); |
| 9579 | PIPE_CONF_CHECK_I(dp_m_n.link_m); |
| 9580 | PIPE_CONF_CHECK_I(dp_m_n.link_n); |
| 9581 | PIPE_CONF_CHECK_I(dp_m_n.tu); |
| 9582 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9583 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
| 9584 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); |
| 9585 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); |
| 9586 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); |
| 9587 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); |
| 9588 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); |
| 9589 | |
| 9590 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); |
| 9591 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); |
| 9592 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); |
| 9593 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); |
| 9594 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); |
| 9595 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); |
| 9596 | |
Daniel Vetter | c93f54c | 2013-06-27 19:47:19 +0200 | [diff] [blame] | 9597 | PIPE_CONF_CHECK_I(pixel_multiplier); |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9598 | |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9599 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 9600 | DRM_MODE_FLAG_INTERLACE); |
| 9601 | |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 9602 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
| 9603 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 9604 | DRM_MODE_FLAG_PHSYNC); |
| 9605 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 9606 | DRM_MODE_FLAG_NHSYNC); |
| 9607 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 9608 | DRM_MODE_FLAG_PVSYNC); |
| 9609 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
| 9610 | DRM_MODE_FLAG_NVSYNC); |
| 9611 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 9612 | |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 9613 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 9614 | PIPE_CONF_CHECK_I(pipe_src_h); |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9615 | |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9616 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
| 9617 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 9618 | if (INTEL_INFO(dev)->gen < 4) |
| 9619 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); |
| 9620 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 9621 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
| 9622 | if (current_config->pch_pfit.enabled) { |
| 9623 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
| 9624 | PIPE_CONF_CHECK_I(pch_pfit.size); |
| 9625 | } |
Daniel Vetter | 2fa2fe9 | 2013-05-07 23:34:16 +0200 | [diff] [blame] | 9626 | |
Jesse Barnes | e59150d | 2014-01-07 13:30:45 -0800 | [diff] [blame] | 9627 | /* BDW+ don't expose a synchronous way to read the state */ |
| 9628 | if (IS_HASWELL(dev)) |
| 9629 | PIPE_CONF_CHECK_I(ips_enabled); |
Paulo Zanoni | 42db64e | 2013-05-31 16:33:22 -0300 | [diff] [blame] | 9630 | |
Ville Syrjälä | 282740f | 2013-09-04 18:30:03 +0300 | [diff] [blame] | 9631 | PIPE_CONF_CHECK_I(double_wide); |
| 9632 | |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9633 | PIPE_CONF_CHECK_I(shared_dpll); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9634 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 9635 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9636 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 9637 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
Daniel Vetter | c0d43d6 | 2013-06-07 23:11:08 +0200 | [diff] [blame] | 9638 | |
Ville Syrjälä | 42571ae | 2013-09-06 23:29:00 +0300 | [diff] [blame] | 9639 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
| 9640 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 9641 | |
Jesse Barnes | a9a7e98 | 2014-01-20 14:18:04 -0800 | [diff] [blame] | 9642 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
| 9643 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 9644 | |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9645 | #undef PIPE_CONF_CHECK_X |
Daniel Vetter | 08a2403 | 2013-04-19 11:25:34 +0200 | [diff] [blame] | 9646 | #undef PIPE_CONF_CHECK_I |
Daniel Vetter | 1bd1bd8 | 2013-04-29 21:56:12 +0200 | [diff] [blame] | 9647 | #undef PIPE_CONF_CHECK_FLAGS |
Ville Syrjälä | 5e55065 | 2013-09-06 23:29:07 +0300 | [diff] [blame] | 9648 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
Daniel Vetter | bb76006 | 2013-06-06 14:55:52 +0200 | [diff] [blame] | 9649 | #undef PIPE_CONF_QUIRK |
Daniel Vetter | 627eb5a | 2013-04-29 19:33:42 +0200 | [diff] [blame] | 9650 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9651 | return true; |
| 9652 | } |
| 9653 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 9654 | static void |
| 9655 | check_connector_state(struct drm_device *dev) |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9656 | { |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9657 | struct intel_connector *connector; |
| 9658 | |
| 9659 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9660 | base.head) { |
| 9661 | /* This also checks the encoder/connector hw state with the |
| 9662 | * ->get_hw_state callbacks. */ |
| 9663 | intel_connector_check_state(connector); |
| 9664 | |
| 9665 | WARN(&connector->new_encoder->base != connector->base.encoder, |
| 9666 | "connector's staged encoder doesn't match current encoder\n"); |
| 9667 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 9668 | } |
| 9669 | |
| 9670 | static void |
| 9671 | check_encoder_state(struct drm_device *dev) |
| 9672 | { |
| 9673 | struct intel_encoder *encoder; |
| 9674 | struct intel_connector *connector; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9675 | |
| 9676 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9677 | base.head) { |
| 9678 | bool enabled = false; |
| 9679 | bool active = false; |
| 9680 | enum pipe pipe, tracked_pipe; |
| 9681 | |
| 9682 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", |
| 9683 | encoder->base.base.id, |
| 9684 | drm_get_encoder_name(&encoder->base)); |
| 9685 | |
| 9686 | WARN(&encoder->new_crtc->base != encoder->base.crtc, |
| 9687 | "encoder's stage crtc doesn't match current crtc\n"); |
| 9688 | WARN(encoder->connectors_active && !encoder->base.crtc, |
| 9689 | "encoder's active_connectors set, but no crtc\n"); |
| 9690 | |
| 9691 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 9692 | base.head) { |
| 9693 | if (connector->base.encoder != &encoder->base) |
| 9694 | continue; |
| 9695 | enabled = true; |
| 9696 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) |
| 9697 | active = true; |
| 9698 | } |
| 9699 | WARN(!!encoder->base.crtc != enabled, |
| 9700 | "encoder's enabled state mismatch " |
| 9701 | "(expected %i, found %i)\n", |
| 9702 | !!encoder->base.crtc, enabled); |
| 9703 | WARN(active && !encoder->base.crtc, |
| 9704 | "active encoder with no crtc\n"); |
| 9705 | |
| 9706 | WARN(encoder->connectors_active != active, |
| 9707 | "encoder's computed active state doesn't match tracked active state " |
| 9708 | "(expected %i, found %i)\n", active, encoder->connectors_active); |
| 9709 | |
| 9710 | active = encoder->get_hw_state(encoder, &pipe); |
| 9711 | WARN(active != encoder->connectors_active, |
| 9712 | "encoder's hw state doesn't match sw tracking " |
| 9713 | "(expected %i, found %i)\n", |
| 9714 | encoder->connectors_active, active); |
| 9715 | |
| 9716 | if (!encoder->base.crtc) |
| 9717 | continue; |
| 9718 | |
| 9719 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; |
| 9720 | WARN(active && pipe != tracked_pipe, |
| 9721 | "active encoder's pipe doesn't match" |
| 9722 | "(expected %i, found %i)\n", |
| 9723 | tracked_pipe, pipe); |
| 9724 | |
| 9725 | } |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 9726 | } |
| 9727 | |
| 9728 | static void |
| 9729 | check_crtc_state(struct drm_device *dev) |
| 9730 | { |
| 9731 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 9732 | struct intel_crtc *crtc; |
| 9733 | struct intel_encoder *encoder; |
| 9734 | struct intel_crtc_config pipe_config; |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9735 | |
| 9736 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 9737 | base.head) { |
| 9738 | bool enabled = false; |
| 9739 | bool active = false; |
| 9740 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 9741 | memset(&pipe_config, 0, sizeof(pipe_config)); |
| 9742 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9743 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
| 9744 | crtc->base.base.id); |
| 9745 | |
| 9746 | WARN(crtc->active && !crtc->base.enabled, |
| 9747 | "active crtc, but not enabled in sw tracking\n"); |
| 9748 | |
| 9749 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9750 | base.head) { |
| 9751 | if (encoder->base.crtc != &crtc->base) |
| 9752 | continue; |
| 9753 | enabled = true; |
| 9754 | if (encoder->connectors_active) |
| 9755 | active = true; |
| 9756 | } |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9757 | |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9758 | WARN(active != crtc->active, |
| 9759 | "crtc's computed active state doesn't match tracked active state " |
| 9760 | "(expected %i, found %i)\n", active, crtc->active); |
| 9761 | WARN(enabled != crtc->base.enabled, |
| 9762 | "crtc's computed enabled state doesn't match tracked enabled state " |
| 9763 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); |
| 9764 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9765 | active = dev_priv->display.get_pipe_config(crtc, |
| 9766 | &pipe_config); |
Daniel Vetter | d62cf62 | 2013-05-29 10:41:29 +0200 | [diff] [blame] | 9767 | |
| 9768 | /* hw state is inconsistent with the pipe A quirk */ |
| 9769 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) |
| 9770 | active = crtc->active; |
| 9771 | |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9772 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 9773 | base.head) { |
Ville Syrjälä | 3eaba51 | 2013-08-05 17:57:48 +0300 | [diff] [blame] | 9774 | enum pipe pipe; |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9775 | if (encoder->base.crtc != &crtc->base) |
| 9776 | continue; |
Daniel Vetter | 1d37b68 | 2013-11-18 09:00:59 +0100 | [diff] [blame] | 9777 | if (encoder->get_hw_state(encoder, &pipe)) |
Daniel Vetter | 6c49f24 | 2013-06-06 12:45:25 +0200 | [diff] [blame] | 9778 | encoder->get_config(encoder, &pipe_config); |
| 9779 | } |
| 9780 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 9781 | WARN(crtc->active != active, |
| 9782 | "crtc active state doesn't match with hw state " |
| 9783 | "(expected %i, found %i)\n", crtc->active, active); |
| 9784 | |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9785 | if (active && |
| 9786 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { |
| 9787 | WARN(1, "pipe state doesn't match!\n"); |
| 9788 | intel_dump_pipe_config(crtc, &pipe_config, |
| 9789 | "[hw state]"); |
| 9790 | intel_dump_pipe_config(crtc, &crtc->config, |
| 9791 | "[sw state]"); |
| 9792 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 9793 | } |
| 9794 | } |
| 9795 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 9796 | static void |
| 9797 | check_shared_dpll_state(struct drm_device *dev) |
| 9798 | { |
| 9799 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 9800 | struct intel_crtc *crtc; |
| 9801 | struct intel_dpll_hw_state dpll_hw_state; |
| 9802 | int i; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 9803 | |
| 9804 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 9805 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 9806 | int enabled_crtcs = 0, active_crtcs = 0; |
| 9807 | bool active; |
| 9808 | |
| 9809 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 9810 | |
| 9811 | DRM_DEBUG_KMS("%s\n", pll->name); |
| 9812 | |
| 9813 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 9814 | |
| 9815 | WARN(pll->active > pll->refcount, |
| 9816 | "more active pll users than references: %i vs %i\n", |
| 9817 | pll->active, pll->refcount); |
| 9818 | WARN(pll->active && !pll->on, |
| 9819 | "pll in active use but not on in sw tracking\n"); |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 9820 | WARN(pll->on && !pll->active, |
| 9821 | "pll in on but not on in use in sw tracking\n"); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 9822 | WARN(pll->on != active, |
| 9823 | "pll on state mismatch (expected %i, found %i)\n", |
| 9824 | pll->on, active); |
| 9825 | |
| 9826 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 9827 | base.head) { |
| 9828 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
| 9829 | enabled_crtcs++; |
| 9830 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 9831 | active_crtcs++; |
| 9832 | } |
| 9833 | WARN(pll->active != active_crtcs, |
| 9834 | "pll active crtcs mismatch (expected %i, found %i)\n", |
| 9835 | pll->active, active_crtcs); |
| 9836 | WARN(pll->refcount != enabled_crtcs, |
| 9837 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
| 9838 | pll->refcount, enabled_crtcs); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 9839 | |
| 9840 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, |
| 9841 | sizeof(dpll_hw_state)), |
| 9842 | "pll hw state mismatch\n"); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 9843 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9844 | } |
| 9845 | |
Daniel Vetter | 91d1b4b | 2013-06-05 13:34:18 +0200 | [diff] [blame] | 9846 | void |
| 9847 | intel_modeset_check_state(struct drm_device *dev) |
| 9848 | { |
| 9849 | check_connector_state(dev); |
| 9850 | check_encoder_state(dev); |
| 9851 | check_crtc_state(dev); |
| 9852 | check_shared_dpll_state(dev); |
| 9853 | } |
| 9854 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 9855 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
| 9856 | int dotclock) |
| 9857 | { |
| 9858 | /* |
| 9859 | * FDI already provided one idea for the dotclock. |
| 9860 | * Yell if the encoder disagrees. |
| 9861 | */ |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 9862 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 9863 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 9864 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 9865 | } |
| 9866 | |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 9867 | static int __intel_set_mode(struct drm_crtc *crtc, |
| 9868 | struct drm_display_mode *mode, |
| 9869 | int x, int y, struct drm_framebuffer *fb) |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9870 | { |
| 9871 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | dbf2b54e | 2012-07-02 11:18:29 +0200 | [diff] [blame] | 9872 | drm_i915_private_t *dev_priv = dev->dev_private; |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 9873 | struct drm_display_mode *saved_mode; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9874 | struct intel_crtc_config *pipe_config = NULL; |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9875 | struct intel_crtc *intel_crtc; |
| 9876 | unsigned disable_pipes, prepare_pipes, modeset_pipes; |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 9877 | int ret = 0; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9878 | |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 9879 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 9880 | if (!saved_mode) |
| 9881 | return -ENOMEM; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9882 | |
Daniel Vetter | e2e1ed4 | 2012-07-08 21:14:38 +0200 | [diff] [blame] | 9883 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9884 | &prepare_pipes, &disable_pipes); |
| 9885 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 9886 | *saved_mode = crtc->mode; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9887 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9888 | /* Hack: Because we don't (yet) support global modeset on multiple |
| 9889 | * crtcs, we don't keep track of the new mode for more than one crtc. |
| 9890 | * Hence simply check whether any bit is set in modeset_pipes in all the |
| 9891 | * pieces of code that are not yet converted to deal with mutliple crtcs |
| 9892 | * changing their mode at the same time. */ |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9893 | if (modeset_pipes) { |
Daniel Vetter | 4e53c2e | 2013-03-27 00:44:58 +0100 | [diff] [blame] | 9894 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9895 | if (IS_ERR(pipe_config)) { |
| 9896 | ret = PTR_ERR(pipe_config); |
| 9897 | pipe_config = NULL; |
| 9898 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 9899 | goto out; |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9900 | } |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 9901 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
| 9902 | "[modeset]"); |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 9903 | to_intel_crtc(crtc)->new_config = pipe_config; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9904 | } |
| 9905 | |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 9906 | /* |
| 9907 | * See if the config requires any additional preparation, e.g. |
| 9908 | * to adjust global state with pipes off. We need to do this |
| 9909 | * here so we can get the modeset_pipe updated config for the new |
| 9910 | * mode set on this crtc. For other crtcs we need to use the |
| 9911 | * adjusted_mode bits in the crtc directly. |
| 9912 | */ |
Ville Syrjälä | c164f83 | 2013-11-05 22:34:12 +0200 | [diff] [blame] | 9913 | if (IS_VALLEYVIEW(dev)) { |
Ville Syrjälä | 2f2d7aa | 2014-01-10 11:28:08 +0200 | [diff] [blame] | 9914 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 9915 | |
Ville Syrjälä | c164f83 | 2013-11-05 22:34:12 +0200 | [diff] [blame] | 9916 | /* may have added more to prepare_pipes than we should */ |
| 9917 | prepare_pipes &= ~disable_pipes; |
| 9918 | } |
| 9919 | |
Daniel Vetter | 460da916 | 2013-03-27 00:44:51 +0100 | [diff] [blame] | 9920 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
| 9921 | intel_crtc_disable(&intel_crtc->base); |
| 9922 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9923 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
| 9924 | if (intel_crtc->base.enabled) |
| 9925 | dev_priv->display.crtc_disable(&intel_crtc->base); |
| 9926 | } |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9927 | |
Daniel Vetter | 6c4c86f | 2012-09-10 21:58:30 +0200 | [diff] [blame] | 9928 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
| 9929 | * to set it here already despite that we pass it down the callchain. |
| 9930 | */ |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9931 | if (modeset_pipes) { |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9932 | crtc->mode = *mode; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9933 | /* mode_set/enable/disable functions rely on a correct pipe |
| 9934 | * config. */ |
| 9935 | to_intel_crtc(crtc)->config = *pipe_config; |
Ville Syrjälä | 50741ab | 2014-01-10 11:28:07 +0200 | [diff] [blame] | 9936 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
Ville Syrjälä | c326c0a | 2013-10-28 12:53:41 +0200 | [diff] [blame] | 9937 | |
| 9938 | /* |
| 9939 | * Calculate and store various constants which |
| 9940 | * are later needed by vblank and swap-completion |
| 9941 | * timestamping. They are derived from true hwmode. |
| 9942 | */ |
| 9943 | drm_calc_timestamping_constants(crtc, |
| 9944 | &pipe_config->adjusted_mode); |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9945 | } |
Daniel Vetter | 7758a11 | 2012-07-08 19:40:39 +0200 | [diff] [blame] | 9946 | |
Daniel Vetter | ea9d758 | 2012-07-10 10:42:52 +0200 | [diff] [blame] | 9947 | /* Only after disabling all output pipelines that will be changed can we |
| 9948 | * update the the output configuration. */ |
| 9949 | intel_modeset_update_state(dev, prepare_pipes); |
| 9950 | |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 9951 | if (dev_priv->display.modeset_global_resources) |
| 9952 | dev_priv->display.modeset_global_resources(dev); |
| 9953 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9954 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
| 9955 | * on the DPLL. |
| 9956 | */ |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9957 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 9958 | ret = intel_crtc_mode_set(&intel_crtc->base, |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 9959 | x, y, fb); |
| 9960 | if (ret) |
| 9961 | goto done; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9962 | } |
| 9963 | |
| 9964 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9965 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
| 9966 | dev_priv->display.crtc_enable(&intel_crtc->base); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9967 | |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9968 | /* FIXME: add subpixel order */ |
| 9969 | done: |
Ville Syrjälä | 4b4b923 | 2013-10-26 17:59:30 +0300 | [diff] [blame] | 9970 | if (ret && crtc->enabled) |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 9971 | crtc->mode = *saved_mode; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9972 | |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 9973 | out: |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 9974 | kfree(pipe_config); |
Tim Gardner | 3ac1823 | 2012-12-07 07:54:26 -0700 | [diff] [blame] | 9975 | kfree(saved_mode); |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 9976 | return ret; |
| 9977 | } |
| 9978 | |
Damien Lespiau | e7457a9 | 2013-08-08 22:28:59 +0100 | [diff] [blame] | 9979 | static int intel_set_mode(struct drm_crtc *crtc, |
| 9980 | struct drm_display_mode *mode, |
| 9981 | int x, int y, struct drm_framebuffer *fb) |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 9982 | { |
| 9983 | int ret; |
| 9984 | |
| 9985 | ret = __intel_set_mode(crtc, mode, x, y, fb); |
| 9986 | |
| 9987 | if (ret == 0) |
| 9988 | intel_modeset_check_state(crtc->dev); |
| 9989 | |
| 9990 | return ret; |
| 9991 | } |
| 9992 | |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 9993 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
| 9994 | { |
| 9995 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); |
| 9996 | } |
| 9997 | |
Daniel Vetter | 25c5b26 | 2012-07-08 22:08:04 +0200 | [diff] [blame] | 9998 | #undef for_each_intel_crtc_masked |
| 9999 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 10000 | static void intel_set_config_free(struct intel_set_config *config) |
| 10001 | { |
| 10002 | if (!config) |
| 10003 | return; |
| 10004 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 10005 | kfree(config->save_connector_encoders); |
| 10006 | kfree(config->save_encoder_crtcs); |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10007 | kfree(config->save_crtc_enabled); |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 10008 | kfree(config); |
| 10009 | } |
| 10010 | |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10011 | static int intel_set_config_save_state(struct drm_device *dev, |
| 10012 | struct intel_set_config *config) |
| 10013 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10014 | struct drm_crtc *crtc; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10015 | struct drm_encoder *encoder; |
| 10016 | struct drm_connector *connector; |
| 10017 | int count; |
| 10018 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10019 | config->save_crtc_enabled = |
| 10020 | kcalloc(dev->mode_config.num_crtc, |
| 10021 | sizeof(bool), GFP_KERNEL); |
| 10022 | if (!config->save_crtc_enabled) |
| 10023 | return -ENOMEM; |
| 10024 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 10025 | config->save_encoder_crtcs = |
| 10026 | kcalloc(dev->mode_config.num_encoder, |
| 10027 | sizeof(struct drm_crtc *), GFP_KERNEL); |
| 10028 | if (!config->save_encoder_crtcs) |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10029 | return -ENOMEM; |
| 10030 | |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 10031 | config->save_connector_encoders = |
| 10032 | kcalloc(dev->mode_config.num_connector, |
| 10033 | sizeof(struct drm_encoder *), GFP_KERNEL); |
| 10034 | if (!config->save_connector_encoders) |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10035 | return -ENOMEM; |
| 10036 | |
| 10037 | /* Copy data. Note that driver private data is not affected. |
| 10038 | * Should anything bad happen only the expected state is |
| 10039 | * restored, not the drivers personal bookkeeping. |
| 10040 | */ |
| 10041 | count = 0; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10042 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 10043 | config->save_crtc_enabled[count++] = crtc->enabled; |
| 10044 | } |
| 10045 | |
| 10046 | count = 0; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10047 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 10048 | config->save_encoder_crtcs[count++] = encoder->crtc; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10049 | } |
| 10050 | |
| 10051 | count = 0; |
| 10052 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Daniel Vetter | 1aa4b62 | 2012-07-05 16:20:48 +0200 | [diff] [blame] | 10053 | config->save_connector_encoders[count++] = connector->encoder; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10054 | } |
| 10055 | |
| 10056 | return 0; |
| 10057 | } |
| 10058 | |
| 10059 | static void intel_set_config_restore_state(struct drm_device *dev, |
| 10060 | struct intel_set_config *config) |
| 10061 | { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10062 | struct intel_crtc *crtc; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10063 | struct intel_encoder *encoder; |
| 10064 | struct intel_connector *connector; |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10065 | int count; |
| 10066 | |
| 10067 | count = 0; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10068 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 10069 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 10070 | |
| 10071 | if (crtc->new_enabled) |
| 10072 | crtc->new_config = &crtc->config; |
| 10073 | else |
| 10074 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10075 | } |
| 10076 | |
| 10077 | count = 0; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10078 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 10079 | encoder->new_crtc = |
| 10080 | to_intel_crtc(config->save_encoder_crtcs[count++]); |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10081 | } |
| 10082 | |
| 10083 | count = 0; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10084 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
| 10085 | connector->new_encoder = |
| 10086 | to_intel_encoder(config->save_connector_encoders[count++]); |
Daniel Vetter | 85f9eb7 | 2012-07-04 22:24:08 +0200 | [diff] [blame] | 10087 | } |
| 10088 | } |
| 10089 | |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10090 | static bool |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 10091 | is_crtc_connector_off(struct drm_mode_set *set) |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10092 | { |
| 10093 | int i; |
| 10094 | |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 10095 | if (set->num_connectors == 0) |
| 10096 | return false; |
| 10097 | |
| 10098 | if (WARN_ON(set->connectors == NULL)) |
| 10099 | return false; |
| 10100 | |
| 10101 | for (i = 0; i < set->num_connectors; i++) |
| 10102 | if (set->connectors[i]->encoder && |
| 10103 | set->connectors[i]->encoder->crtc == set->crtc && |
| 10104 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10105 | return true; |
| 10106 | |
| 10107 | return false; |
| 10108 | } |
| 10109 | |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10110 | static void |
| 10111 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, |
| 10112 | struct intel_set_config *config) |
| 10113 | { |
| 10114 | |
| 10115 | /* We should be able to check here if the fb has the same properties |
| 10116 | * and then just flip_or_move it */ |
Chris Wilson | 2e57f47 | 2013-07-17 12:14:40 +0100 | [diff] [blame] | 10117 | if (is_crtc_connector_off(set)) { |
| 10118 | config->mode_changed = true; |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10119 | } else if (set->crtc->fb != set->fb) { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10120 | /* If we have no fb then treat it as a full mode set */ |
| 10121 | if (set->crtc->fb == NULL) { |
Jesse Barnes | 319d982 | 2013-06-26 01:38:19 +0300 | [diff] [blame] | 10122 | struct intel_crtc *intel_crtc = |
| 10123 | to_intel_crtc(set->crtc); |
| 10124 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 10125 | if (intel_crtc->active && i915.fastboot) { |
Jesse Barnes | 319d982 | 2013-06-26 01:38:19 +0300 | [diff] [blame] | 10126 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
| 10127 | config->fb_changed = true; |
| 10128 | } else { |
| 10129 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); |
| 10130 | config->mode_changed = true; |
| 10131 | } |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10132 | } else if (set->fb == NULL) { |
| 10133 | config->mode_changed = true; |
Daniel Vetter | 72f4901 | 2013-03-28 16:01:35 +0100 | [diff] [blame] | 10134 | } else if (set->fb->pixel_format != |
| 10135 | set->crtc->fb->pixel_format) { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10136 | config->mode_changed = true; |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10137 | } else { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10138 | config->fb_changed = true; |
Imre Deak | e3de42b | 2013-05-03 19:44:07 +0200 | [diff] [blame] | 10139 | } |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10140 | } |
| 10141 | |
Daniel Vetter | 835c587 | 2012-07-10 18:11:08 +0200 | [diff] [blame] | 10142 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10143 | config->fb_changed = true; |
| 10144 | |
| 10145 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { |
| 10146 | DRM_DEBUG_KMS("modes are different, full mode set\n"); |
| 10147 | drm_mode_debug_printmodeline(&set->crtc->mode); |
| 10148 | drm_mode_debug_printmodeline(set->mode); |
| 10149 | config->mode_changed = true; |
| 10150 | } |
Chris Wilson | a1d9570 | 2013-08-13 18:48:47 +0100 | [diff] [blame] | 10151 | |
| 10152 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
| 10153 | set->crtc->base.id, config->mode_changed, config->fb_changed); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10154 | } |
| 10155 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10156 | static int |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10157 | intel_modeset_stage_output_state(struct drm_device *dev, |
| 10158 | struct drm_mode_set *set, |
| 10159 | struct intel_set_config *config) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10160 | { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10161 | struct intel_connector *connector; |
| 10162 | struct intel_encoder *encoder; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10163 | struct intel_crtc *crtc; |
Paulo Zanoni | f3f0857 | 2013-08-12 14:56:53 -0300 | [diff] [blame] | 10164 | int ro; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10165 | |
Damien Lespiau | 9abdda7 | 2013-02-13 13:29:23 +0000 | [diff] [blame] | 10166 | /* The upper layers ensure that we either disable a crtc or have a list |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10167 | * of connectors. For paranoia, double-check this. */ |
| 10168 | WARN_ON(!set->fb && (set->num_connectors != 0)); |
| 10169 | WARN_ON(set->fb && (set->num_connectors == 0)); |
| 10170 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10171 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 10172 | base.head) { |
| 10173 | /* Otherwise traverse passed in connector list and get encoders |
| 10174 | * for them. */ |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10175 | for (ro = 0; ro < set->num_connectors; ro++) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10176 | if (set->connectors[ro] == &connector->base) { |
| 10177 | connector->new_encoder = connector->encoder; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10178 | break; |
| 10179 | } |
| 10180 | } |
| 10181 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10182 | /* If we disable the crtc, disable all its connectors. Also, if |
| 10183 | * the connector is on the changing crtc but not on the new |
| 10184 | * connector list, disable it. */ |
| 10185 | if ((!set->fb || ro == set->num_connectors) && |
| 10186 | connector->base.encoder && |
| 10187 | connector->base.encoder->crtc == set->crtc) { |
| 10188 | connector->new_encoder = NULL; |
| 10189 | |
| 10190 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", |
| 10191 | connector->base.base.id, |
| 10192 | drm_get_connector_name(&connector->base)); |
| 10193 | } |
| 10194 | |
| 10195 | |
| 10196 | if (&connector->new_encoder->base != connector->base.encoder) { |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10197 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10198 | config->mode_changed = true; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10199 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10200 | } |
| 10201 | /* connector->new_encoder is now updated for all connectors. */ |
| 10202 | |
| 10203 | /* Update crtc of enabled connectors. */ |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10204 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 10205 | base.head) { |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10206 | struct drm_crtc *new_crtc; |
| 10207 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10208 | if (!connector->new_encoder) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10209 | continue; |
| 10210 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10211 | new_crtc = connector->new_encoder->base.crtc; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10212 | |
| 10213 | for (ro = 0; ro < set->num_connectors; ro++) { |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10214 | if (set->connectors[ro] == &connector->base) |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10215 | new_crtc = set->crtc; |
| 10216 | } |
| 10217 | |
| 10218 | /* Make sure the new CRTC will work with the encoder */ |
Thierry Reding | 1450991 | 2014-01-13 12:00:22 +0100 | [diff] [blame] | 10219 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
| 10220 | new_crtc)) { |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10221 | return -EINVAL; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10222 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10223 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
| 10224 | |
| 10225 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
| 10226 | connector->base.base.id, |
| 10227 | drm_get_connector_name(&connector->base), |
| 10228 | new_crtc->base.id); |
| 10229 | } |
| 10230 | |
| 10231 | /* Check for any encoders that needs to be disabled. */ |
| 10232 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 10233 | base.head) { |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 10234 | int num_connectors = 0; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10235 | list_for_each_entry(connector, |
| 10236 | &dev->mode_config.connector_list, |
| 10237 | base.head) { |
| 10238 | if (connector->new_encoder == encoder) { |
| 10239 | WARN_ON(!connector->new_encoder->new_crtc); |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 10240 | num_connectors++; |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10241 | } |
| 10242 | } |
Paulo Zanoni | 5a65f35 | 2014-01-07 14:55:53 -0200 | [diff] [blame] | 10243 | |
| 10244 | if (num_connectors == 0) |
| 10245 | encoder->new_crtc = NULL; |
| 10246 | else if (num_connectors > 1) |
| 10247 | return -EINVAL; |
| 10248 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10249 | /* Only now check for crtc changes so we don't miss encoders |
| 10250 | * that will be disabled. */ |
| 10251 | if (&encoder->new_crtc->base != encoder->base.crtc) { |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10252 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10253 | config->mode_changed = true; |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10254 | } |
| 10255 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10256 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10257 | |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10258 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 10259 | base.head) { |
| 10260 | crtc->new_enabled = false; |
| 10261 | |
| 10262 | list_for_each_entry(encoder, |
| 10263 | &dev->mode_config.encoder_list, |
| 10264 | base.head) { |
| 10265 | if (encoder->new_crtc == crtc) { |
| 10266 | crtc->new_enabled = true; |
| 10267 | break; |
| 10268 | } |
| 10269 | } |
| 10270 | |
| 10271 | if (crtc->new_enabled != crtc->base.enabled) { |
| 10272 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
| 10273 | crtc->new_enabled ? "en" : "dis"); |
| 10274 | config->mode_changed = true; |
| 10275 | } |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 10276 | |
| 10277 | if (crtc->new_enabled) |
| 10278 | crtc->new_config = &crtc->config; |
| 10279 | else |
| 10280 | crtc->new_config = NULL; |
Ville Syrjälä | 7668851 | 2014-01-10 11:28:06 +0200 | [diff] [blame] | 10281 | } |
| 10282 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10283 | return 0; |
| 10284 | } |
| 10285 | |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 10286 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
| 10287 | { |
| 10288 | struct drm_device *dev = crtc->base.dev; |
| 10289 | struct intel_encoder *encoder; |
| 10290 | struct intel_connector *connector; |
| 10291 | |
| 10292 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", |
| 10293 | pipe_name(crtc->pipe)); |
| 10294 | |
| 10295 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
| 10296 | if (connector->new_encoder && |
| 10297 | connector->new_encoder->new_crtc == crtc) |
| 10298 | connector->new_encoder = NULL; |
| 10299 | } |
| 10300 | |
| 10301 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 10302 | if (encoder->new_crtc == crtc) |
| 10303 | encoder->new_crtc = NULL; |
| 10304 | } |
| 10305 | |
| 10306 | crtc->new_enabled = false; |
Ville Syrjälä | 7bd0a8e | 2014-01-14 14:31:38 +0200 | [diff] [blame] | 10307 | crtc->new_config = NULL; |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 10308 | } |
| 10309 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10310 | static int intel_crtc_set_config(struct drm_mode_set *set) |
| 10311 | { |
| 10312 | struct drm_device *dev; |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10313 | struct drm_mode_set save_set; |
| 10314 | struct intel_set_config *config; |
| 10315 | int ret; |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10316 | |
Daniel Vetter | 8d3e375 | 2012-07-05 16:09:09 +0200 | [diff] [blame] | 10317 | BUG_ON(!set); |
| 10318 | BUG_ON(!set->crtc); |
| 10319 | BUG_ON(!set->crtc->helper_private); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10320 | |
Daniel Vetter | 7e53f3a | 2013-01-21 10:52:17 +0100 | [diff] [blame] | 10321 | /* Enforce sane interface api - has been abused by the fb helper. */ |
| 10322 | BUG_ON(!set->mode && set->fb); |
| 10323 | BUG_ON(set->fb && set->num_connectors == 0); |
Daniel Vetter | 431e50f | 2012-07-10 17:53:42 +0200 | [diff] [blame] | 10324 | |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10325 | if (set->fb) { |
| 10326 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", |
| 10327 | set->crtc->base.id, set->fb->base.id, |
| 10328 | (int)set->num_connectors, set->x, set->y); |
| 10329 | } else { |
| 10330 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10331 | } |
| 10332 | |
| 10333 | dev = set->crtc->dev; |
| 10334 | |
| 10335 | ret = -ENOMEM; |
| 10336 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
| 10337 | if (!config) |
| 10338 | goto out_config; |
| 10339 | |
| 10340 | ret = intel_set_config_save_state(dev, config); |
| 10341 | if (ret) |
| 10342 | goto out_config; |
| 10343 | |
| 10344 | save_set.crtc = set->crtc; |
| 10345 | save_set.mode = &set->crtc->mode; |
| 10346 | save_set.x = set->crtc->x; |
| 10347 | save_set.y = set->crtc->y; |
| 10348 | save_set.fb = set->crtc->fb; |
| 10349 | |
| 10350 | /* Compute whether we need a full modeset, only an fb base update or no |
| 10351 | * change at all. In the future we might also check whether only the |
| 10352 | * mode changed, e.g. for LVDS where we only change the panel fitter in |
| 10353 | * such cases. */ |
| 10354 | intel_set_config_compute_mode_changes(set, config); |
| 10355 | |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 10356 | ret = intel_modeset_stage_output_state(dev, set, config); |
Daniel Vetter | 2e43105 | 2012-07-04 22:42:15 +0200 | [diff] [blame] | 10357 | if (ret) |
| 10358 | goto fail; |
| 10359 | |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10360 | if (config->mode_changed) { |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 10361 | ret = intel_set_mode(set->crtc, set->mode, |
| 10362 | set->x, set->y, set->fb); |
Daniel Vetter | 5e2b584 | 2012-07-04 22:41:29 +0200 | [diff] [blame] | 10363 | } else if (config->fb_changed) { |
Ville Syrjälä | 4878cae | 2013-02-18 19:08:48 +0200 | [diff] [blame] | 10364 | intel_crtc_wait_for_pending_flips(set->crtc); |
| 10365 | |
Daniel Vetter | 4f660f4 | 2012-07-02 09:47:37 +0200 | [diff] [blame] | 10366 | ret = intel_pipe_set_base(set->crtc, |
Daniel Vetter | 94352cf | 2012-07-05 22:51:56 +0200 | [diff] [blame] | 10367 | set->x, set->y, set->fb); |
Jesse Barnes | 7ca51a3 | 2014-01-07 13:50:49 -0800 | [diff] [blame] | 10368 | /* |
| 10369 | * In the fastboot case this may be our only check of the |
| 10370 | * state after boot. It would be better to only do it on |
| 10371 | * the first update, but we don't have a nice way of doing that |
| 10372 | * (and really, set_config isn't used much for high freq page |
| 10373 | * flipping, so increasing its cost here shouldn't be a big |
| 10374 | * deal). |
| 10375 | */ |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 10376 | if (i915.fastboot && ret == 0) |
Jesse Barnes | 7ca51a3 | 2014-01-07 13:50:49 -0800 | [diff] [blame] | 10377 | intel_modeset_check_state(set->crtc->dev); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10378 | } |
| 10379 | |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 10380 | if (ret) { |
Daniel Vetter | bf67dfe | 2013-06-25 11:06:52 +0200 | [diff] [blame] | 10381 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
| 10382 | set->crtc->base.id, ret); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10383 | fail: |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 10384 | intel_set_config_restore_state(dev, config); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10385 | |
Ville Syrjälä | 7d00a1f | 2014-01-10 11:28:09 +0200 | [diff] [blame] | 10386 | /* |
| 10387 | * HACK: if the pipe was on, but we didn't have a framebuffer, |
| 10388 | * force the pipe off to avoid oopsing in the modeset code |
| 10389 | * due to fb==NULL. This should only happen during boot since |
| 10390 | * we don't yet reconstruct the FB from the hardware state. |
| 10391 | */ |
| 10392 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) |
| 10393 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); |
| 10394 | |
Chris Wilson | 2d05eae | 2013-05-03 17:36:25 +0100 | [diff] [blame] | 10395 | /* Try to restore the config */ |
| 10396 | if (config->mode_changed && |
| 10397 | intel_set_mode(save_set.crtc, save_set.mode, |
| 10398 | save_set.x, save_set.y, save_set.fb)) |
| 10399 | DRM_ERROR("failed to restore config after modeset failure\n"); |
| 10400 | } |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10401 | |
Daniel Vetter | d9e5560 | 2012-07-04 22:16:09 +0200 | [diff] [blame] | 10402 | out_config: |
| 10403 | intel_set_config_free(config); |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10404 | return ret; |
| 10405 | } |
| 10406 | |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 10407 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 10408 | .cursor_set = intel_crtc_cursor_set, |
| 10409 | .cursor_move = intel_crtc_cursor_move, |
| 10410 | .gamma_set = intel_crtc_gamma_set, |
Daniel Vetter | 50f5611 | 2012-07-02 09:35:43 +0200 | [diff] [blame] | 10411 | .set_config = intel_crtc_set_config, |
Chris Wilson | f6e5b16 | 2011-04-12 18:06:51 +0100 | [diff] [blame] | 10412 | .destroy = intel_crtc_destroy, |
| 10413 | .page_flip = intel_crtc_page_flip, |
| 10414 | }; |
| 10415 | |
Paulo Zanoni | 79f689a | 2012-10-05 12:05:52 -0300 | [diff] [blame] | 10416 | static void intel_cpu_pll_init(struct drm_device *dev) |
| 10417 | { |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 10418 | if (HAS_DDI(dev)) |
Paulo Zanoni | 79f689a | 2012-10-05 12:05:52 -0300 | [diff] [blame] | 10419 | intel_ddi_pll_init(dev); |
| 10420 | } |
| 10421 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10422 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 10423 | struct intel_shared_dpll *pll, |
| 10424 | struct intel_dpll_hw_state *hw_state) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10425 | { |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10426 | uint32_t val; |
| 10427 | |
| 10428 | val = I915_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 10429 | hw_state->dpll = val; |
| 10430 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 10431 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10432 | |
| 10433 | return val & DPLL_VCO_ENABLE; |
| 10434 | } |
| 10435 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 10436 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
| 10437 | struct intel_shared_dpll *pll) |
| 10438 | { |
| 10439 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); |
| 10440 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); |
| 10441 | } |
| 10442 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10443 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 10444 | struct intel_shared_dpll *pll) |
| 10445 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10446 | /* PCH refclock must be enabled first */ |
Paulo Zanoni | 89eff4b | 2014-01-08 11:12:28 -0200 | [diff] [blame] | 10447 | ibx_assert_pch_refclk_enabled(dev_priv); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10448 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 10449 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
| 10450 | |
| 10451 | /* Wait for the clocks to stabilize. */ |
| 10452 | POSTING_READ(PCH_DPLL(pll->id)); |
| 10453 | udelay(150); |
| 10454 | |
| 10455 | /* The pixel multiplier can only be updated once the |
| 10456 | * DPLL is enabled and the clocks are stable. |
| 10457 | * |
| 10458 | * So write it again. |
| 10459 | */ |
| 10460 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
| 10461 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10462 | udelay(200); |
| 10463 | } |
| 10464 | |
| 10465 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 10466 | struct intel_shared_dpll *pll) |
| 10467 | { |
| 10468 | struct drm_device *dev = dev_priv->dev; |
| 10469 | struct intel_crtc *crtc; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10470 | |
| 10471 | /* Make sure no transcoder isn't still depending on us. */ |
| 10472 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
| 10473 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
| 10474 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 10475 | } |
| 10476 | |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 10477 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 10478 | POSTING_READ(PCH_DPLL(pll->id)); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10479 | udelay(200); |
| 10480 | } |
| 10481 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 10482 | static char *ibx_pch_dpll_names[] = { |
| 10483 | "PCH DPLL A", |
| 10484 | "PCH DPLL B", |
| 10485 | }; |
| 10486 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 10487 | static void ibx_pch_dpll_init(struct drm_device *dev) |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10488 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10489 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10490 | int i; |
| 10491 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 10492 | dev_priv->num_shared_dpll = 2; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10493 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 10494 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 10495 | dev_priv->shared_dplls[i].id = i; |
| 10496 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 10497 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10498 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
| 10499 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 10500 | dev_priv->shared_dplls[i].get_hw_state = |
| 10501 | ibx_pch_dpll_get_hw_state; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10502 | } |
| 10503 | } |
| 10504 | |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 10505 | static void intel_shared_dpll_init(struct drm_device *dev) |
| 10506 | { |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 10507 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 10508 | |
| 10509 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
| 10510 | ibx_pch_dpll_init(dev); |
| 10511 | else |
| 10512 | dev_priv->num_shared_dpll = 0; |
| 10513 | |
| 10514 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
Daniel Vetter | 7c74ade | 2013-06-05 13:34:11 +0200 | [diff] [blame] | 10515 | } |
| 10516 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 10517 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10518 | { |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 10519 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10520 | struct intel_crtc *intel_crtc; |
| 10521 | int i; |
| 10522 | |
Daniel Vetter | 955382f | 2013-09-19 14:05:45 +0200 | [diff] [blame] | 10523 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10524 | if (intel_crtc == NULL) |
| 10525 | return; |
| 10526 | |
| 10527 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); |
| 10528 | |
| 10529 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10530 | for (i = 0; i < 256; i++) { |
| 10531 | intel_crtc->lut_r[i] = i; |
| 10532 | intel_crtc->lut_g[i] = i; |
| 10533 | intel_crtc->lut_b[i] = i; |
| 10534 | } |
| 10535 | |
Ville Syrjälä | 1f1c2e2 | 2013-11-28 17:30:01 +0200 | [diff] [blame] | 10536 | /* |
| 10537 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port |
| 10538 | * is hooked to plane B. Hence we want plane A feeding pipe B. |
| 10539 | */ |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 10540 | intel_crtc->pipe = pipe; |
| 10541 | intel_crtc->plane = pipe; |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 10542 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 10543 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
Chris Wilson | e2e767a | 2010-09-13 16:53:12 +0100 | [diff] [blame] | 10544 | intel_crtc->plane = !pipe; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 10545 | } |
| 10546 | |
Jesse Barnes | 22fd0fa | 2009-12-02 13:42:53 -0800 | [diff] [blame] | 10547 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
| 10548 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); |
| 10549 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; |
| 10550 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; |
| 10551 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10552 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10553 | } |
| 10554 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 10555 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
| 10556 | { |
| 10557 | struct drm_encoder *encoder = connector->base.encoder; |
| 10558 | |
| 10559 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); |
| 10560 | |
| 10561 | if (!encoder) |
| 10562 | return INVALID_PIPE; |
| 10563 | |
| 10564 | return to_intel_crtc(encoder->crtc)->pipe; |
| 10565 | } |
| 10566 | |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10567 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10568 | struct drm_file *file) |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10569 | { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10570 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 10571 | struct drm_mode_object *drmmode_obj; |
| 10572 | struct intel_crtc *crtc; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10573 | |
Daniel Vetter | 1cff8f6 | 2012-04-24 09:55:08 +0200 | [diff] [blame] | 10574 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 10575 | return -ENODEV; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10576 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 10577 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
| 10578 | DRM_MODE_OBJECT_CRTC); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10579 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 10580 | if (!drmmode_obj) { |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10581 | DRM_ERROR("no such CRTC id\n"); |
Ville Syrjälä | 3f2c205 | 2013-10-17 13:35:03 +0300 | [diff] [blame] | 10582 | return -ENOENT; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10583 | } |
| 10584 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 10585 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
| 10586 | pipe_from_crtc_id->pipe = crtc->pipe; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10587 | |
Daniel Vetter | c05422d | 2009-08-11 16:05:30 +0200 | [diff] [blame] | 10588 | return 0; |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 10589 | } |
| 10590 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 10591 | static int intel_encoder_clones(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10592 | { |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 10593 | struct drm_device *dev = encoder->base.dev; |
| 10594 | struct intel_encoder *source_encoder; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10595 | int index_mask = 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10596 | int entry = 0; |
| 10597 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 10598 | list_for_each_entry(source_encoder, |
| 10599 | &dev->mode_config.encoder_list, base.head) { |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 10600 | if (encoders_cloneable(encoder, source_encoder)) |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 10601 | index_mask |= (1 << entry); |
| 10602 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10603 | entry++; |
| 10604 | } |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 10605 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10606 | return index_mask; |
| 10607 | } |
| 10608 | |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 10609 | static bool has_edp_a(struct drm_device *dev) |
| 10610 | { |
| 10611 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10612 | |
| 10613 | if (!IS_MOBILE(dev)) |
| 10614 | return false; |
| 10615 | |
| 10616 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) |
| 10617 | return false; |
| 10618 | |
Damien Lespiau | e358990 | 2014-02-07 19:12:50 +0000 | [diff] [blame] | 10619 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
Chris Wilson | 4d30244 | 2010-12-14 19:21:29 +0000 | [diff] [blame] | 10620 | return false; |
| 10621 | |
| 10622 | return true; |
| 10623 | } |
| 10624 | |
Damien Lespiau | ba0fbca | 2014-01-08 14:18:23 +0000 | [diff] [blame] | 10625 | const char *intel_output_name(int output) |
| 10626 | { |
| 10627 | static const char *names[] = { |
| 10628 | [INTEL_OUTPUT_UNUSED] = "Unused", |
| 10629 | [INTEL_OUTPUT_ANALOG] = "Analog", |
| 10630 | [INTEL_OUTPUT_DVO] = "DVO", |
| 10631 | [INTEL_OUTPUT_SDVO] = "SDVO", |
| 10632 | [INTEL_OUTPUT_LVDS] = "LVDS", |
| 10633 | [INTEL_OUTPUT_TVOUT] = "TV", |
| 10634 | [INTEL_OUTPUT_HDMI] = "HDMI", |
| 10635 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", |
| 10636 | [INTEL_OUTPUT_EDP] = "eDP", |
| 10637 | [INTEL_OUTPUT_DSI] = "DSI", |
| 10638 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", |
| 10639 | }; |
| 10640 | |
| 10641 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) |
| 10642 | return "Invalid"; |
| 10643 | |
| 10644 | return names[output]; |
| 10645 | } |
| 10646 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10647 | static void intel_setup_outputs(struct drm_device *dev) |
| 10648 | { |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 10649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 10650 | struct intel_encoder *encoder; |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 10651 | bool dpd_is_edp = false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10652 | |
Daniel Vetter | c909335 | 2013-06-06 22:22:47 +0200 | [diff] [blame] | 10653 | intel_lvds_init(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10654 | |
Paulo Zanoni | c40c0f5 | 2013-04-12 18:16:53 -0300 | [diff] [blame] | 10655 | if (!IS_ULT(dev)) |
Paulo Zanoni | 79935fc | 2012-11-20 13:27:40 -0200 | [diff] [blame] | 10656 | intel_crt_init(dev); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 10657 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 10658 | if (HAS_DDI(dev)) { |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 10659 | int found; |
| 10660 | |
| 10661 | /* Haswell uses DDI functions to detect digital outputs */ |
| 10662 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
| 10663 | /* DDI A only supports eDP */ |
| 10664 | if (found) |
| 10665 | intel_ddi_init(dev, PORT_A); |
| 10666 | |
| 10667 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP |
| 10668 | * register */ |
| 10669 | found = I915_READ(SFUSE_STRAP); |
| 10670 | |
| 10671 | if (found & SFUSE_STRAP_DDIB_DETECTED) |
| 10672 | intel_ddi_init(dev, PORT_B); |
| 10673 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
| 10674 | intel_ddi_init(dev, PORT_C); |
| 10675 | if (found & SFUSE_STRAP_DDID_DETECTED) |
| 10676 | intel_ddi_init(dev, PORT_D); |
| 10677 | } else if (HAS_PCH_SPLIT(dev)) { |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 10678 | int found; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 10679 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 10680 | |
| 10681 | if (has_edp_a(dev)) |
| 10682 | intel_dp_init(dev, DP_A, PORT_A); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 10683 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 10684 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 10685 | /* PCH SDVOB multiplex with HDMIB */ |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 10686 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 10687 | if (!found) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10688 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 10689 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10690 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 10691 | } |
| 10692 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 10693 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10694 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 10695 | |
Paulo Zanoni | dc0fa71 | 2013-02-19 16:21:46 -0300 | [diff] [blame] | 10696 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10697 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
Zhenyu Wang | 30ad48b | 2009-06-05 15:38:43 +0800 | [diff] [blame] | 10698 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 10699 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10700 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 10701 | |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 10702 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10703 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
Jesse Barnes | 4a87d65 | 2012-06-15 11:55:16 -0700 | [diff] [blame] | 10704 | } else if (IS_VALLEYVIEW(dev)) { |
Artem Bityutskiy | 585a94b | 2013-10-16 18:10:41 +0300 | [diff] [blame] | 10705 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
| 10706 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
| 10707 | PORT_B); |
| 10708 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
| 10709 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); |
| 10710 | } |
| 10711 | |
Jesse Barnes | 6f6005a | 2013-08-09 09:34:35 -0700 | [diff] [blame] | 10712 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
| 10713 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
| 10714 | PORT_C); |
| 10715 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 10716 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
Jesse Barnes | 6f6005a | 2013-08-09 09:34:35 -0700 | [diff] [blame] | 10717 | } |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 10718 | |
Jani Nikula | 3cfca97 | 2013-08-27 15:12:26 +0300 | [diff] [blame] | 10719 | intel_dsi_init(dev); |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 10720 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 10721 | bool found = false; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 10722 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10723 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10724 | DRM_DEBUG_KMS("probing SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10725 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10726 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 10727 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10728 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10729 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 10730 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 10731 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10732 | intel_dp_init(dev, DP_B, PORT_B); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 10733 | } |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 10734 | |
| 10735 | /* Before G4X SDVOC doesn't have its own detect register */ |
Kristian Høgsberg | 13520b0 | 2009-03-13 15:42:14 -0400 | [diff] [blame] | 10736 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10737 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10738 | DRM_DEBUG_KMS("probing SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10739 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10740 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 10741 | |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10742 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 10743 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10744 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
| 10745 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
Paulo Zanoni | e2debe9 | 2013-02-18 19:00:27 -0300 | [diff] [blame] | 10746 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10747 | } |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 10748 | if (SUPPORTS_INTEGRATED_DP(dev)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10749 | intel_dp_init(dev, DP_C, PORT_C); |
Eric Anholt | 725e30a | 2009-01-22 13:01:02 -0800 | [diff] [blame] | 10750 | } |
Ma Ling | 27185ae | 2009-08-24 13:50:23 +0800 | [diff] [blame] | 10751 | |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 10752 | if (SUPPORTS_INTEGRATED_DP(dev) && |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 10753 | (I915_READ(DP_D) & DP_DETECTED)) |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 10754 | intel_dp_init(dev, DP_D, PORT_D); |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 10755 | } else if (IS_GEN2(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10756 | intel_dvo_init(dev); |
| 10757 | |
Zhenyu Wang | 103a196 | 2009-11-27 11:44:36 +0800 | [diff] [blame] | 10758 | if (SUPPORTS_TV(dev)) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10759 | intel_tv_init(dev); |
| 10760 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 10761 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
| 10762 | encoder->base.possible_crtcs = encoder->crtc_mask; |
| 10763 | encoder->base.possible_clones = |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 10764 | intel_encoder_clones(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10765 | } |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 10766 | |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 10767 | intel_init_pch_refclk(dev); |
Daniel Vetter | 270b304 | 2012-10-27 15:52:05 +0200 | [diff] [blame] | 10768 | |
| 10769 | drm_helper_move_panel_connectors_to_head(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10770 | } |
| 10771 | |
| 10772 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 10773 | { |
| 10774 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10775 | |
Daniel Vetter | ef2d633 | 2014-02-10 18:00:38 +0100 | [diff] [blame] | 10776 | drm_framebuffer_cleanup(fb); |
| 10777 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
| 10778 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10779 | kfree(intel_fb); |
| 10780 | } |
| 10781 | |
| 10782 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10783 | struct drm_file *file, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10784 | unsigned int *handle) |
| 10785 | { |
| 10786 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10787 | struct drm_i915_gem_object *obj = intel_fb->obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10788 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10789 | return drm_gem_handle_create(file, &obj->base, handle); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10790 | } |
| 10791 | |
| 10792 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 10793 | .destroy = intel_user_framebuffer_destroy, |
| 10794 | .create_handle = intel_user_framebuffer_create_handle, |
| 10795 | }; |
| 10796 | |
Daniel Vetter | b5ea642 | 2014-03-02 21:18:00 +0100 | [diff] [blame] | 10797 | static int intel_framebuffer_init(struct drm_device *dev, |
| 10798 | struct intel_framebuffer *intel_fb, |
| 10799 | struct drm_mode_fb_cmd2 *mode_cmd, |
| 10800 | struct drm_i915_gem_object *obj) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10801 | { |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 10802 | int aligned_height; |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 10803 | int pitch_limit; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10804 | int ret; |
| 10805 | |
Daniel Vetter | dd4916c | 2013-10-09 21:23:51 +0200 | [diff] [blame] | 10806 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 10807 | |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10808 | if (obj->tiling_mode == I915_TILING_Y) { |
| 10809 | DRM_DEBUG("hardware does not support tiling Y\n"); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10810 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10811 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10812 | |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10813 | if (mode_cmd->pitches[0] & 63) { |
| 10814 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", |
| 10815 | mode_cmd->pitches[0]); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10816 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10817 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10818 | |
Chris Wilson | a35cdaa | 2013-06-25 17:26:45 +0100 | [diff] [blame] | 10819 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
| 10820 | pitch_limit = 32*1024; |
| 10821 | } else if (INTEL_INFO(dev)->gen >= 4) { |
| 10822 | if (obj->tiling_mode) |
| 10823 | pitch_limit = 16*1024; |
| 10824 | else |
| 10825 | pitch_limit = 32*1024; |
| 10826 | } else if (INTEL_INFO(dev)->gen >= 3) { |
| 10827 | if (obj->tiling_mode) |
| 10828 | pitch_limit = 8*1024; |
| 10829 | else |
| 10830 | pitch_limit = 16*1024; |
| 10831 | } else |
| 10832 | /* XXX DSPC is limited to 4k tiled */ |
| 10833 | pitch_limit = 8*1024; |
| 10834 | |
| 10835 | if (mode_cmd->pitches[0] > pitch_limit) { |
| 10836 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", |
| 10837 | obj->tiling_mode ? "tiled" : "linear", |
| 10838 | mode_cmd->pitches[0], pitch_limit); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 10839 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10840 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 10841 | |
| 10842 | if (obj->tiling_mode != I915_TILING_NONE && |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10843 | mode_cmd->pitches[0] != obj->stride) { |
| 10844 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
| 10845 | mode_cmd->pitches[0], obj->stride); |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 10846 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10847 | } |
Ville Syrjälä | 5d7bd70 | 2012-10-31 17:50:18 +0200 | [diff] [blame] | 10848 | |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10849 | /* Reject formats not supported by any plane early. */ |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 10850 | switch (mode_cmd->pixel_format) { |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10851 | case DRM_FORMAT_C8: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 10852 | case DRM_FORMAT_RGB565: |
| 10853 | case DRM_FORMAT_XRGB8888: |
| 10854 | case DRM_FORMAT_ARGB8888: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10855 | break; |
| 10856 | case DRM_FORMAT_XRGB1555: |
| 10857 | case DRM_FORMAT_ARGB1555: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10858 | if (INTEL_INFO(dev)->gen > 3) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 10859 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 10860 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10861 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10862 | } |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10863 | break; |
| 10864 | case DRM_FORMAT_XBGR8888: |
| 10865 | case DRM_FORMAT_ABGR8888: |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 10866 | case DRM_FORMAT_XRGB2101010: |
| 10867 | case DRM_FORMAT_ARGB2101010: |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10868 | case DRM_FORMAT_XBGR2101010: |
| 10869 | case DRM_FORMAT_ABGR2101010: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10870 | if (INTEL_INFO(dev)->gen < 4) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 10871 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 10872 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10873 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10874 | } |
Jesse Barnes | b562674 | 2011-06-24 12:19:27 -0700 | [diff] [blame] | 10875 | break; |
Ville Syrjälä | 04b3924 | 2011-11-17 18:05:13 +0200 | [diff] [blame] | 10876 | case DRM_FORMAT_YUYV: |
| 10877 | case DRM_FORMAT_UYVY: |
| 10878 | case DRM_FORMAT_YVYU: |
| 10879 | case DRM_FORMAT_VYUY: |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10880 | if (INTEL_INFO(dev)->gen < 5) { |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 10881 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 10882 | drm_get_format_name(mode_cmd->pixel_format)); |
Ville Syrjälä | 57779d0 | 2012-10-31 17:50:14 +0200 | [diff] [blame] | 10883 | return -EINVAL; |
Chris Wilson | c16ed4b | 2012-12-18 22:13:14 +0000 | [diff] [blame] | 10884 | } |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10885 | break; |
| 10886 | default: |
Ville Syrjälä | 4ee62c7 | 2013-06-07 15:43:05 +0000 | [diff] [blame] | 10887 | DRM_DEBUG("unsupported pixel format: %s\n", |
| 10888 | drm_get_format_name(mode_cmd->pixel_format)); |
Chris Wilson | 57cd650 | 2010-08-08 12:34:44 +0100 | [diff] [blame] | 10889 | return -EINVAL; |
| 10890 | } |
| 10891 | |
Ville Syrjälä | 90f9a33 | 2012-10-31 17:50:19 +0200 | [diff] [blame] | 10892 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 10893 | if (mode_cmd->offsets[0] != 0) |
| 10894 | return -EINVAL; |
| 10895 | |
Jesse Barnes | a57ce0b | 2014-02-07 12:10:35 -0800 | [diff] [blame] | 10896 | aligned_height = intel_align_height(dev, mode_cmd->height, |
| 10897 | obj->tiling_mode); |
Daniel Vetter | 53155c0 | 2013-10-09 21:55:33 +0200 | [diff] [blame] | 10898 | /* FIXME drm helper for size checks (especially planar formats)? */ |
| 10899 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) |
| 10900 | return -EINVAL; |
| 10901 | |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 10902 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
| 10903 | intel_fb->obj = obj; |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 10904 | intel_fb->obj->framebuffer_references++; |
Daniel Vetter | c7d73f6 | 2012-12-13 23:38:38 +0100 | [diff] [blame] | 10905 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10906 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
| 10907 | if (ret) { |
| 10908 | DRM_ERROR("framebuffer init failed %d\n", ret); |
| 10909 | return ret; |
| 10910 | } |
| 10911 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10912 | return 0; |
| 10913 | } |
| 10914 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10915 | static struct drm_framebuffer * |
| 10916 | intel_user_framebuffer_create(struct drm_device *dev, |
| 10917 | struct drm_file *filp, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 10918 | struct drm_mode_fb_cmd2 *mode_cmd) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10919 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 10920 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10921 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 10922 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
| 10923 | mode_cmd->handles[0])); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 10924 | if (&obj->base == NULL) |
Chris Wilson | cce13ff | 2010-08-08 13:36:38 +0100 | [diff] [blame] | 10925 | return ERR_PTR(-ENOENT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10926 | |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 10927 | return intel_framebuffer_create(dev, mode_cmd, obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10928 | } |
| 10929 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 10930 | #ifndef CONFIG_DRM_I915_FBDEV |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 10931 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 10932 | { |
| 10933 | } |
| 10934 | #endif |
| 10935 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10936 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10937 | .fb_create = intel_user_framebuffer_create, |
Daniel Vetter | 0632fef | 2013-10-08 17:44:49 +0200 | [diff] [blame] | 10938 | .output_poll_changed = intel_fbdev_output_poll_changed, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 10939 | }; |
| 10940 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 10941 | /* Set up chip specific display functions */ |
| 10942 | static void intel_init_display(struct drm_device *dev) |
| 10943 | { |
| 10944 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 10945 | |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 10946 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
| 10947 | dev_priv->display.find_dpll = g4x_find_best_dpll; |
| 10948 | else if (IS_VALLEYVIEW(dev)) |
| 10949 | dev_priv->display.find_dpll = vlv_find_best_dpll; |
| 10950 | else if (IS_PINEVIEW(dev)) |
| 10951 | dev_priv->display.find_dpll = pnv_find_best_dpll; |
| 10952 | else |
| 10953 | dev_priv->display.find_dpll = i9xx_find_best_dpll; |
| 10954 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 10955 | if (HAS_DDI(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10956 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 10957 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 10958 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
Paulo Zanoni | 4f771f1 | 2012-10-23 18:29:51 -0200 | [diff] [blame] | 10959 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
| 10960 | dev_priv->display.crtc_disable = haswell_crtc_disable; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 10961 | dev_priv->display.off = haswell_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 10962 | dev_priv->display.update_primary_plane = |
| 10963 | ironlake_update_primary_plane; |
Paulo Zanoni | 09b4ddf | 2012-10-05 12:05:55 -0300 | [diff] [blame] | 10964 | } else if (HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10965 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
Jesse Barnes | 4c6baa5 | 2014-03-07 08:57:50 -0800 | [diff] [blame] | 10966 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 10967 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 10968 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
| 10969 | dev_priv->display.crtc_disable = ironlake_crtc_disable; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10970 | dev_priv->display.off = ironlake_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 10971 | dev_priv->display.update_primary_plane = |
| 10972 | ironlake_update_primary_plane; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 10973 | } else if (IS_VALLEYVIEW(dev)) { |
| 10974 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 10975 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 10976 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
| 10977 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 10978 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 10979 | dev_priv->display.off = i9xx_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 10980 | dev_priv->display.update_primary_plane = |
| 10981 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 10982 | } else { |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 10983 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
Jesse Barnes | 1ad292b | 2014-03-07 08:57:49 -0800 | [diff] [blame] | 10984 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 10985 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 10986 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 10987 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 10988 | dev_priv->display.off = i9xx_crtc_off; |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 10989 | dev_priv->display.update_primary_plane = |
| 10990 | i9xx_update_primary_plane; |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 10991 | } |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 10992 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 10993 | /* Returns the core display clock speed */ |
Jesse Barnes | 25eb05fc | 2012-03-28 13:39:23 -0700 | [diff] [blame] | 10994 | if (IS_VALLEYVIEW(dev)) |
| 10995 | dev_priv->display.get_display_clock_speed = |
| 10996 | valleyview_get_display_clock_speed; |
| 10997 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 10998 | dev_priv->display.get_display_clock_speed = |
| 10999 | i945_get_display_clock_speed; |
| 11000 | else if (IS_I915G(dev)) |
| 11001 | dev_priv->display.get_display_clock_speed = |
| 11002 | i915_get_display_clock_speed; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 11003 | else if (IS_I945GM(dev) || IS_845G(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11004 | dev_priv->display.get_display_clock_speed = |
| 11005 | i9xx_misc_get_display_clock_speed; |
Daniel Vetter | 257a7ff | 2013-07-26 08:35:42 +0200 | [diff] [blame] | 11006 | else if (IS_PINEVIEW(dev)) |
| 11007 | dev_priv->display.get_display_clock_speed = |
| 11008 | pnv_get_display_clock_speed; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11009 | else if (IS_I915GM(dev)) |
| 11010 | dev_priv->display.get_display_clock_speed = |
| 11011 | i915gm_get_display_clock_speed; |
| 11012 | else if (IS_I865G(dev)) |
| 11013 | dev_priv->display.get_display_clock_speed = |
| 11014 | i865_get_display_clock_speed; |
Daniel Vetter | f0f8a9c | 2009-09-15 22:57:33 +0200 | [diff] [blame] | 11015 | else if (IS_I85X(dev)) |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11016 | dev_priv->display.get_display_clock_speed = |
| 11017 | i855_get_display_clock_speed; |
| 11018 | else /* 852, 830 */ |
| 11019 | dev_priv->display.get_display_clock_speed = |
| 11020 | i830_get_display_clock_speed; |
| 11021 | |
Zhenyu Wang | 7f8a856 | 2010-04-01 13:07:53 +0800 | [diff] [blame] | 11022 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | f00a3dd | 2010-10-21 14:57:17 +0100 | [diff] [blame] | 11023 | if (IS_GEN5(dev)) { |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 11024 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 11025 | dev_priv->display.write_eld = ironlake_write_eld; |
Yuanhan Liu | 1398261 | 2010-12-15 15:42:31 +0800 | [diff] [blame] | 11026 | } else if (IS_GEN6(dev)) { |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 11027 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 11028 | dev_priv->display.write_eld = ironlake_write_eld; |
Jesse Barnes | 357555c | 2011-04-28 15:09:55 -0700 | [diff] [blame] | 11029 | } else if (IS_IVYBRIDGE(dev)) { |
| 11030 | /* FIXME: detect B0+ stepping and use auto training */ |
| 11031 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 11032 | dev_priv->display.write_eld = ironlake_write_eld; |
Daniel Vetter | 01a415f | 2012-10-27 15:58:40 +0200 | [diff] [blame] | 11033 | dev_priv->display.modeset_global_resources = |
| 11034 | ivb_modeset_global_resources; |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 11035 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 11036 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
Wang Xingchao | 83358c85 | 2012-08-16 22:43:37 +0800 | [diff] [blame] | 11037 | dev_priv->display.write_eld = haswell_write_eld; |
Daniel Vetter | d6dd9eb | 2013-01-29 16:35:20 -0200 | [diff] [blame] | 11038 | dev_priv->display.modeset_global_resources = |
| 11039 | haswell_modeset_global_resources; |
Paulo Zanoni | a0e63c2 | 2012-12-06 11:12:39 -0200 | [diff] [blame] | 11040 | } |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 11041 | } else if (IS_G4X(dev)) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 11042 | dev_priv->display.write_eld = g4x_write_eld; |
Jesse Barnes | 30a970c | 2013-11-04 13:48:12 -0800 | [diff] [blame] | 11043 | } else if (IS_VALLEYVIEW(dev)) { |
| 11044 | dev_priv->display.modeset_global_resources = |
| 11045 | valleyview_modeset_global_resources; |
Mengdong Lin | 9ca2fe7 | 2013-11-01 00:17:03 -0400 | [diff] [blame] | 11046 | dev_priv->display.write_eld = ironlake_write_eld; |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11047 | } |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11048 | |
| 11049 | /* Default just returns -ENODEV to indicate unsupported */ |
| 11050 | dev_priv->display.queue_flip = intel_default_queue_flip; |
| 11051 | |
| 11052 | switch (INTEL_INFO(dev)->gen) { |
| 11053 | case 2: |
| 11054 | dev_priv->display.queue_flip = intel_gen2_queue_flip; |
| 11055 | break; |
| 11056 | |
| 11057 | case 3: |
| 11058 | dev_priv->display.queue_flip = intel_gen3_queue_flip; |
| 11059 | break; |
| 11060 | |
| 11061 | case 4: |
| 11062 | case 5: |
| 11063 | dev_priv->display.queue_flip = intel_gen4_queue_flip; |
| 11064 | break; |
| 11065 | |
| 11066 | case 6: |
| 11067 | dev_priv->display.queue_flip = intel_gen6_queue_flip; |
| 11068 | break; |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11069 | case 7: |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 11070 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
Jesse Barnes | 7c9017e | 2011-06-16 12:18:54 -0700 | [diff] [blame] | 11071 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
| 11072 | break; |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 11073 | } |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 11074 | |
| 11075 | intel_panel_init_backlight_funcs(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11076 | } |
| 11077 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11078 | /* |
| 11079 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, |
| 11080 | * resume, or other times. This quirk makes sure that's the case for |
| 11081 | * affected systems. |
| 11082 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 11083 | static void quirk_pipea_force(struct drm_device *dev) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11084 | { |
| 11085 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11086 | |
| 11087 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 11088 | DRM_INFO("applying pipe a force quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11089 | } |
| 11090 | |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 11091 | /* |
| 11092 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason |
| 11093 | */ |
| 11094 | static void quirk_ssc_force_disable(struct drm_device *dev) |
| 11095 | { |
| 11096 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11097 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 11098 | DRM_INFO("applying lvds SSC disable quirk\n"); |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 11099 | } |
| 11100 | |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 11101 | /* |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 11102 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
| 11103 | * brightness value |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 11104 | */ |
| 11105 | static void quirk_invert_brightness(struct drm_device *dev) |
| 11106 | { |
| 11107 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11108 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 11109 | DRM_INFO("applying inverted panel brightness quirk\n"); |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11110 | } |
| 11111 | |
| 11112 | struct intel_quirk { |
| 11113 | int device; |
| 11114 | int subsystem_vendor; |
| 11115 | int subsystem_device; |
| 11116 | void (*hook)(struct drm_device *dev); |
| 11117 | }; |
| 11118 | |
Egbert Eich | 5f85f176 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 11119 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
| 11120 | struct intel_dmi_quirk { |
| 11121 | void (*hook)(struct drm_device *dev); |
| 11122 | const struct dmi_system_id (*dmi_id_list)[]; |
| 11123 | }; |
| 11124 | |
| 11125 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) |
| 11126 | { |
| 11127 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); |
| 11128 | return 1; |
| 11129 | } |
| 11130 | |
| 11131 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { |
| 11132 | { |
| 11133 | .dmi_id_list = &(const struct dmi_system_id[]) { |
| 11134 | { |
| 11135 | .callback = intel_dmi_reverse_brightness, |
| 11136 | .ident = "NCR Corporation", |
| 11137 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), |
| 11138 | DMI_MATCH(DMI_PRODUCT_NAME, ""), |
| 11139 | }, |
| 11140 | }, |
| 11141 | { } /* terminating entry */ |
| 11142 | }, |
| 11143 | .hook = quirk_invert_brightness, |
| 11144 | }, |
| 11145 | }; |
| 11146 | |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 11147 | static struct intel_quirk intel_quirks[] = { |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11148 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 11149 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11150 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11151 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
| 11152 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, |
| 11153 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11154 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
| 11155 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, |
| 11156 | |
Chris Wilson | a4945f9 | 2013-10-08 11:16:59 +0100 | [diff] [blame] | 11157 | /* 830 needs to leave pipe A & dpll A up */ |
Daniel Vetter | dcdaed6 | 2012-08-12 21:19:34 +0200 | [diff] [blame] | 11158 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 11159 | |
| 11160 | /* Lenovo U160 cannot use SSC on LVDS */ |
| 11161 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, |
Michel Alexandre Salim | 070d329 | 2011-07-28 18:52:06 +0200 | [diff] [blame] | 11162 | |
| 11163 | /* Sony Vaio Y cannot use SSC on LVDS */ |
| 11164 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, |
Carsten Emde | 5a15ab5 | 2012-03-15 15:56:27 +0100 | [diff] [blame] | 11165 | |
Alexander van Heukelum | be505f6 | 2013-12-28 21:00:39 +0100 | [diff] [blame] | 11166 | /* Acer Aspire 5734Z must invert backlight brightness */ |
| 11167 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, |
| 11168 | |
| 11169 | /* Acer/eMachines G725 */ |
| 11170 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, |
| 11171 | |
| 11172 | /* Acer/eMachines e725 */ |
| 11173 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, |
| 11174 | |
| 11175 | /* Acer/Packard Bell NCL20 */ |
| 11176 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, |
| 11177 | |
| 11178 | /* Acer Aspire 4736Z */ |
| 11179 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, |
Jani Nikula | 0f540c3 | 2014-01-13 17:30:34 +0200 | [diff] [blame] | 11180 | |
| 11181 | /* Acer Aspire 5336 */ |
| 11182 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11183 | }; |
| 11184 | |
| 11185 | static void intel_init_quirks(struct drm_device *dev) |
| 11186 | { |
| 11187 | struct pci_dev *d = dev->pdev; |
| 11188 | int i; |
| 11189 | |
| 11190 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { |
| 11191 | struct intel_quirk *q = &intel_quirks[i]; |
| 11192 | |
| 11193 | if (d->device == q->device && |
| 11194 | (d->subsystem_vendor == q->subsystem_vendor || |
| 11195 | q->subsystem_vendor == PCI_ANY_ID) && |
| 11196 | (d->subsystem_device == q->subsystem_device || |
| 11197 | q->subsystem_device == PCI_ANY_ID)) |
| 11198 | q->hook(dev); |
| 11199 | } |
Egbert Eich | 5f85f176 | 2012-10-14 15:46:38 +0200 | [diff] [blame] | 11200 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
| 11201 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) |
| 11202 | intel_dmi_quirks[i].hook(dev); |
| 11203 | } |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11204 | } |
| 11205 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 11206 | /* Disable the VGA plane that we never use */ |
| 11207 | static void i915_disable_vga(struct drm_device *dev) |
| 11208 | { |
| 11209 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11210 | u8 sr1; |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 11211 | u32 vga_reg = i915_vgacntrl_reg(dev); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 11212 | |
Ville Syrjälä | 2b37c61 | 2014-01-22 21:32:38 +0200 | [diff] [blame] | 11213 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 11214 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
Jesse Barnes | 3fdcf43 | 2012-04-06 11:46:27 -0700 | [diff] [blame] | 11215 | outb(SR01, VGA_SR_INDEX); |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 11216 | sr1 = inb(VGA_SR_DATA); |
| 11217 | outb(sr1 | 1<<5, VGA_SR_DATA); |
| 11218 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 11219 | udelay(300); |
| 11220 | |
| 11221 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
| 11222 | POSTING_READ(vga_reg); |
| 11223 | } |
| 11224 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 11225 | void intel_modeset_init_hw(struct drm_device *dev) |
| 11226 | { |
Eugeni Dodonov | a8f78b5 | 2012-06-28 15:55:35 -0300 | [diff] [blame] | 11227 | intel_prepare_ddi(dev); |
| 11228 | |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 11229 | intel_init_clock_gating(dev); |
| 11230 | |
Jesse Barnes | 5382f5f35 | 2013-12-16 16:34:24 -0800 | [diff] [blame] | 11231 | intel_reset_dpio(dev); |
Jesse Barnes | 40e9cf6 | 2013-10-03 11:35:46 -0700 | [diff] [blame] | 11232 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 11233 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 11234 | intel_enable_gt_powersave(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 11235 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 11236 | } |
| 11237 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 11238 | void intel_modeset_suspend_hw(struct drm_device *dev) |
| 11239 | { |
| 11240 | intel_suspend_hw(dev); |
| 11241 | } |
| 11242 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11243 | void intel_modeset_init(struct drm_device *dev) |
| 11244 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11245 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 11246 | int sprite, ret; |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 11247 | enum pipe pipe; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11248 | struct intel_crtc *crtc; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11249 | |
| 11250 | drm_mode_config_init(dev); |
| 11251 | |
| 11252 | dev->mode_config.min_width = 0; |
| 11253 | dev->mode_config.min_height = 0; |
| 11254 | |
Dave Airlie | 019d96c | 2011-09-29 16:20:42 +0100 | [diff] [blame] | 11255 | dev->mode_config.preferred_depth = 24; |
| 11256 | dev->mode_config.prefer_shadow = 1; |
| 11257 | |
Laurent Pinchart | e6ecefa | 2012-05-17 13:27:23 +0200 | [diff] [blame] | 11258 | dev->mode_config.funcs = &intel_mode_funcs; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11259 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 11260 | intel_init_quirks(dev); |
| 11261 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 11262 | intel_init_pm(dev); |
| 11263 | |
Ben Widawsky | e3c7475 | 2013-04-05 13:12:39 -0700 | [diff] [blame] | 11264 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 11265 | return; |
| 11266 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11267 | intel_init_display(dev); |
| 11268 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 11269 | if (IS_GEN2(dev)) { |
| 11270 | dev->mode_config.max_width = 2048; |
| 11271 | dev->mode_config.max_height = 2048; |
| 11272 | } else if (IS_GEN3(dev)) { |
Keith Packard | 5e4d6fa | 2009-07-12 23:53:17 -0700 | [diff] [blame] | 11273 | dev->mode_config.max_width = 4096; |
| 11274 | dev->mode_config.max_height = 4096; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11275 | } else { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 11276 | dev->mode_config.max_width = 8192; |
| 11277 | dev->mode_config.max_height = 8192; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11278 | } |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 11279 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11280 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 11281 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 11282 | INTEL_INFO(dev)->num_pipes, |
| 11283 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11284 | |
Damien Lespiau | 8cc87b7 | 2014-03-03 17:31:44 +0000 | [diff] [blame] | 11285 | for_each_pipe(pipe) { |
| 11286 | intel_crtc_init(dev, pipe); |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 11287 | for_each_sprite(pipe, sprite) { |
| 11288 | ret = intel_plane_init(dev, pipe, sprite); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 11289 | if (ret) |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 11290 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
Damien Lespiau | 1fe4778 | 2014-03-03 17:31:47 +0000 | [diff] [blame] | 11291 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 11292 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11293 | } |
| 11294 | |
Jesse Barnes | f42bb70 | 2013-12-16 16:34:23 -0800 | [diff] [blame] | 11295 | intel_init_dpio(dev); |
Jesse Barnes | 5382f5f35 | 2013-12-16 16:34:24 -0800 | [diff] [blame] | 11296 | intel_reset_dpio(dev); |
Jesse Barnes | f42bb70 | 2013-12-16 16:34:23 -0800 | [diff] [blame] | 11297 | |
Paulo Zanoni | 79f689a | 2012-10-05 12:05:52 -0300 | [diff] [blame] | 11298 | intel_cpu_pll_init(dev); |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 11299 | intel_shared_dpll_init(dev); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 11300 | |
Jesse Barnes | 9cce37f | 2010-08-13 15:11:26 -0700 | [diff] [blame] | 11301 | /* Just disable it once at startup */ |
| 11302 | i915_disable_vga(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11303 | intel_setup_outputs(dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 11304 | |
| 11305 | /* Just in case the BIOS is doing something questionable. */ |
| 11306 | intel_disable_fbc(dev); |
Jesse Barnes | fa9fa08 | 2014-02-11 15:28:56 -0800 | [diff] [blame] | 11307 | |
Jesse Barnes | 8b687df | 2014-02-21 13:13:39 -0800 | [diff] [blame] | 11308 | mutex_lock(&dev->mode_config.mutex); |
Jesse Barnes | fa9fa08 | 2014-02-11 15:28:56 -0800 | [diff] [blame] | 11309 | intel_modeset_setup_hw_state(dev, false); |
Jesse Barnes | 8b687df | 2014-02-21 13:13:39 -0800 | [diff] [blame] | 11310 | mutex_unlock(&dev->mode_config.mutex); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11311 | |
| 11312 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 11313 | base.head) { |
| 11314 | if (!crtc->active) |
| 11315 | continue; |
| 11316 | |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11317 | /* |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11318 | * Note that reserving the BIOS fb up front prevents us |
| 11319 | * from stuffing other stolen allocations like the ring |
| 11320 | * on top. This prevents some ugliness at boot time, and |
| 11321 | * can even allow for smooth boot transitions if the BIOS |
| 11322 | * fb is large enough for the active pipe configuration. |
| 11323 | */ |
| 11324 | if (dev_priv->display.get_plane_config) { |
| 11325 | dev_priv->display.get_plane_config(crtc, |
| 11326 | &crtc->plane_config); |
| 11327 | /* |
| 11328 | * If the fb is shared between multiple heads, we'll |
| 11329 | * just get the first one. |
| 11330 | */ |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 11331 | intel_find_plane_obj(crtc, &crtc->plane_config); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11332 | } |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 11333 | } |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 11334 | } |
Jesse Barnes | d5bb081 | 2011-01-05 12:01:26 -0800 | [diff] [blame] | 11335 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11336 | static void |
| 11337 | intel_connector_break_all_links(struct intel_connector *connector) |
| 11338 | { |
| 11339 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 11340 | connector->base.encoder = NULL; |
| 11341 | connector->encoder->connectors_active = false; |
| 11342 | connector->encoder->base.crtc = NULL; |
| 11343 | } |
| 11344 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 11345 | static void intel_enable_pipe_a(struct drm_device *dev) |
| 11346 | { |
| 11347 | struct intel_connector *connector; |
| 11348 | struct drm_connector *crt = NULL; |
| 11349 | struct intel_load_detect_pipe load_detect_temp; |
| 11350 | |
| 11351 | /* We can't just switch on the pipe A, we need to set things up with a |
| 11352 | * proper mode and output configuration. As a gross hack, enable pipe A |
| 11353 | * by enabling the load detect pipe once. */ |
| 11354 | list_for_each_entry(connector, |
| 11355 | &dev->mode_config.connector_list, |
| 11356 | base.head) { |
| 11357 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
| 11358 | crt = &connector->base; |
| 11359 | break; |
| 11360 | } |
| 11361 | } |
| 11362 | |
| 11363 | if (!crt) |
| 11364 | return; |
| 11365 | |
| 11366 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) |
| 11367 | intel_release_load_detect_pipe(crt, &load_detect_temp); |
| 11368 | |
| 11369 | |
| 11370 | } |
| 11371 | |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 11372 | static bool |
| 11373 | intel_check_plane_mapping(struct intel_crtc *crtc) |
| 11374 | { |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 11375 | struct drm_device *dev = crtc->base.dev; |
| 11376 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 11377 | u32 reg, val; |
| 11378 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 11379 | if (INTEL_INFO(dev)->num_pipes == 1) |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 11380 | return true; |
| 11381 | |
| 11382 | reg = DSPCNTR(!crtc->plane); |
| 11383 | val = I915_READ(reg); |
| 11384 | |
| 11385 | if ((val & DISPLAY_PLANE_ENABLE) && |
| 11386 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) |
| 11387 | return false; |
| 11388 | |
| 11389 | return true; |
| 11390 | } |
| 11391 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11392 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
| 11393 | { |
| 11394 | struct drm_device *dev = crtc->base.dev; |
| 11395 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 11396 | u32 reg; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11397 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11398 | /* Clear any frame start delays used for debugging left by the BIOS */ |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 11399 | reg = PIPECONF(crtc->config.cpu_transcoder); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11400 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
| 11401 | |
| 11402 | /* We need to sanitize the plane -> pipe mapping first because this will |
Daniel Vetter | fa55583 | 2012-10-10 23:14:00 +0200 | [diff] [blame] | 11403 | * disable the crtc (and hence change the state) if it is wrong. Note |
| 11404 | * that gen4+ has a fixed plane -> pipe mapping. */ |
| 11405 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11406 | struct intel_connector *connector; |
| 11407 | bool plane; |
| 11408 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11409 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
| 11410 | crtc->base.base.id); |
| 11411 | |
| 11412 | /* Pipe has the wrong plane attached and the plane is active. |
| 11413 | * Temporarily change the plane mapping and disable everything |
| 11414 | * ... */ |
| 11415 | plane = crtc->plane; |
| 11416 | crtc->plane = !plane; |
| 11417 | dev_priv->display.crtc_disable(&crtc->base); |
| 11418 | crtc->plane = plane; |
| 11419 | |
| 11420 | /* ... and break all links. */ |
| 11421 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 11422 | base.head) { |
| 11423 | if (connector->encoder->base.crtc != &crtc->base) |
| 11424 | continue; |
| 11425 | |
| 11426 | intel_connector_break_all_links(connector); |
| 11427 | } |
| 11428 | |
| 11429 | WARN_ON(crtc->active); |
| 11430 | crtc->base.enabled = false; |
| 11431 | } |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11432 | |
Daniel Vetter | 7fad798 | 2012-07-04 17:51:47 +0200 | [diff] [blame] | 11433 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
| 11434 | crtc->pipe == PIPE_A && !crtc->active) { |
| 11435 | /* BIOS forgot to enable pipe A, this mostly happens after |
| 11436 | * resume. Force-enable the pipe to fix this, the update_dpms |
| 11437 | * call below we restore the pipe to the right state, but leave |
| 11438 | * the required bits on. */ |
| 11439 | intel_enable_pipe_a(dev); |
| 11440 | } |
| 11441 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11442 | /* Adjust the state of the output pipe according to whether we |
| 11443 | * have active connectors/encoders. */ |
| 11444 | intel_crtc_update_dpms(&crtc->base); |
| 11445 | |
| 11446 | if (crtc->active != crtc->base.enabled) { |
| 11447 | struct intel_encoder *encoder; |
| 11448 | |
| 11449 | /* This can happen either due to bugs in the get_hw_state |
| 11450 | * functions or because the pipe is force-enabled due to the |
| 11451 | * pipe A quirk. */ |
| 11452 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", |
| 11453 | crtc->base.base.id, |
| 11454 | crtc->base.enabled ? "enabled" : "disabled", |
| 11455 | crtc->active ? "enabled" : "disabled"); |
| 11456 | |
| 11457 | crtc->base.enabled = crtc->active; |
| 11458 | |
| 11459 | /* Because we only establish the connector -> encoder -> |
| 11460 | * crtc links if something is active, this means the |
| 11461 | * crtc is now deactivated. Break the links. connector |
| 11462 | * -> encoder links are only establish when things are |
| 11463 | * actually up, hence no need to break them. */ |
| 11464 | WARN_ON(crtc->active); |
| 11465 | |
| 11466 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
| 11467 | WARN_ON(encoder->connectors_active); |
| 11468 | encoder->base.crtc = NULL; |
| 11469 | } |
| 11470 | } |
| 11471 | } |
| 11472 | |
| 11473 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 11474 | { |
| 11475 | struct intel_connector *connector; |
| 11476 | struct drm_device *dev = encoder->base.dev; |
| 11477 | |
| 11478 | /* We need to check both for a crtc link (meaning that the |
| 11479 | * encoder is active and trying to read from a pipe) and the |
| 11480 | * pipe itself being active. */ |
| 11481 | bool has_active_crtc = encoder->base.crtc && |
| 11482 | to_intel_crtc(encoder->base.crtc)->active; |
| 11483 | |
| 11484 | if (encoder->connectors_active && !has_active_crtc) { |
| 11485 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
| 11486 | encoder->base.base.id, |
| 11487 | drm_get_encoder_name(&encoder->base)); |
| 11488 | |
| 11489 | /* Connector is active, but has no active pipe. This is |
| 11490 | * fallout from our resume register restoring. Disable |
| 11491 | * the encoder manually again. */ |
| 11492 | if (encoder->base.crtc) { |
| 11493 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
| 11494 | encoder->base.base.id, |
| 11495 | drm_get_encoder_name(&encoder->base)); |
| 11496 | encoder->disable(encoder); |
| 11497 | } |
| 11498 | |
| 11499 | /* Inconsistent output/port/pipe state happens presumably due to |
| 11500 | * a bug in one of the get_hw_state functions. Or someplace else |
| 11501 | * in our code, like the register restore mess on resume. Clamp |
| 11502 | * things to off as a safer default. */ |
| 11503 | list_for_each_entry(connector, |
| 11504 | &dev->mode_config.connector_list, |
| 11505 | base.head) { |
| 11506 | if (connector->encoder != encoder) |
| 11507 | continue; |
| 11508 | |
| 11509 | intel_connector_break_all_links(connector); |
| 11510 | } |
| 11511 | } |
| 11512 | /* Enabled encoders without active connectors will be fixed in |
| 11513 | * the crtc fixup. */ |
| 11514 | } |
| 11515 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 11516 | void i915_redisable_vga_power_on(struct drm_device *dev) |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 11517 | { |
| 11518 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 11519 | u32 vga_reg = i915_vgacntrl_reg(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 11520 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 11521 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
| 11522 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
| 11523 | i915_disable_vga(dev); |
| 11524 | } |
| 11525 | } |
| 11526 | |
| 11527 | void i915_redisable_vga(struct drm_device *dev) |
| 11528 | { |
| 11529 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11530 | |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 11531 | /* This function can be called both from intel_modeset_setup_hw_state or |
| 11532 | * at a very early point in our resume sequence, where the power well |
| 11533 | * structures are not yet restored. Since this function is at a very |
| 11534 | * paranoid "someone might have enabled VGA while we were not looking" |
| 11535 | * level, just check if the power well is enabled instead of trying to |
| 11536 | * follow the "don't touch the power well if we don't need it" policy |
| 11537 | * the rest of the driver uses. */ |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 11538 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
Paulo Zanoni | 8dc8a27 | 2013-08-02 16:22:24 -0300 | [diff] [blame] | 11539 | return; |
| 11540 | |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 11541 | i915_redisable_vga_power_on(dev); |
Krzysztof Mazur | 0fde901 | 2012-12-19 11:03:41 +0100 | [diff] [blame] | 11542 | } |
| 11543 | |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 11544 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11545 | { |
| 11546 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11547 | enum pipe pipe; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11548 | struct intel_crtc *crtc; |
| 11549 | struct intel_encoder *encoder; |
| 11550 | struct intel_connector *connector; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11551 | int i; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11552 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 11553 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 11554 | base.head) { |
Daniel Vetter | 88adfff | 2013-03-28 10:42:01 +0100 | [diff] [blame] | 11555 | memset(&crtc->config, 0, sizeof(crtc->config)); |
Daniel Vetter | 3b117c8 | 2013-04-17 20:15:07 +0200 | [diff] [blame] | 11556 | |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 11557 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
| 11558 | &crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11559 | |
| 11560 | crtc->base.enabled = crtc->active; |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 11561 | crtc->primary_enabled = crtc->active; |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11562 | |
| 11563 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", |
| 11564 | crtc->base.base.id, |
| 11565 | crtc->active ? "enabled" : "disabled"); |
| 11566 | } |
| 11567 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11568 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 11569 | if (HAS_DDI(dev)) |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 11570 | intel_ddi_setup_hw_pll_state(dev); |
| 11571 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11572 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 11573 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 11574 | |
| 11575 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); |
| 11576 | pll->active = 0; |
| 11577 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 11578 | base.head) { |
| 11579 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
| 11580 | pll->active++; |
| 11581 | } |
| 11582 | pll->refcount = pll->active; |
| 11583 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 11584 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
| 11585 | pll->name, pll->refcount, pll->on); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 11586 | } |
| 11587 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11588 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 11589 | base.head) { |
| 11590 | pipe = 0; |
| 11591 | |
| 11592 | if (encoder->get_hw_state(encoder, &pipe)) { |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 11593 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 11594 | encoder->base.crtc = &crtc->base; |
Daniel Vetter | 1d37b68 | 2013-11-18 09:00:59 +0100 | [diff] [blame] | 11595 | encoder->get_config(encoder, &crtc->config); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11596 | } else { |
| 11597 | encoder->base.crtc = NULL; |
| 11598 | } |
| 11599 | |
| 11600 | encoder->connectors_active = false; |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 11601 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11602 | encoder->base.base.id, |
| 11603 | drm_get_encoder_name(&encoder->base), |
| 11604 | encoder->base.crtc ? "enabled" : "disabled", |
Damien Lespiau | 6f2bcce | 2013-10-16 12:29:54 +0100 | [diff] [blame] | 11605 | pipe_name(pipe)); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11606 | } |
| 11607 | |
| 11608 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
| 11609 | base.head) { |
| 11610 | if (connector->get_hw_state(connector)) { |
| 11611 | connector->base.dpms = DRM_MODE_DPMS_ON; |
| 11612 | connector->encoder->connectors_active = true; |
| 11613 | connector->base.encoder = &connector->encoder->base; |
| 11614 | } else { |
| 11615 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
| 11616 | connector->base.encoder = NULL; |
| 11617 | } |
| 11618 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", |
| 11619 | connector->base.base.id, |
| 11620 | drm_get_connector_name(&connector->base), |
| 11621 | connector->base.encoder ? "enabled" : "disabled"); |
| 11622 | } |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 11623 | } |
| 11624 | |
| 11625 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
| 11626 | * and i915 state tracking structures. */ |
| 11627 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 11628 | bool force_restore) |
| 11629 | { |
| 11630 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11631 | enum pipe pipe; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 11632 | struct intel_crtc *crtc; |
| 11633 | struct intel_encoder *encoder; |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 11634 | int i; |
Daniel Vetter | 30e984d | 2013-06-05 13:34:17 +0200 | [diff] [blame] | 11635 | |
| 11636 | intel_modeset_readout_hw_state(dev); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11637 | |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 11638 | /* |
| 11639 | * Now that we have the config, copy it to each CRTC struct |
| 11640 | * Note that this could go away if we move to using crtc_config |
| 11641 | * checking everywhere. |
| 11642 | */ |
| 11643 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
| 11644 | base.head) { |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 11645 | if (crtc->active && i915.fastboot) { |
Daniel Vetter | f6a8328 | 2014-02-11 15:28:57 -0800 | [diff] [blame] | 11646 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
Jesse Barnes | babea61 | 2013-06-26 18:57:38 +0300 | [diff] [blame] | 11647 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
| 11648 | crtc->base.base.id); |
| 11649 | drm_mode_debug_printmodeline(&crtc->base.mode); |
| 11650 | } |
| 11651 | } |
| 11652 | |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11653 | /* HW state is read out, now we need to sanitize this mess. */ |
| 11654 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
| 11655 | base.head) { |
| 11656 | intel_sanitize_encoder(encoder); |
| 11657 | } |
| 11658 | |
| 11659 | for_each_pipe(pipe) { |
| 11660 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
| 11661 | intel_sanitize_crtc(crtc); |
Daniel Vetter | c0b0341 | 2013-05-28 12:05:54 +0200 | [diff] [blame] | 11662 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
Daniel Vetter | 2492935 | 2012-07-02 20:28:59 +0200 | [diff] [blame] | 11663 | } |
Daniel Vetter | 9a93585 | 2012-07-05 22:34:27 +0200 | [diff] [blame] | 11664 | |
Daniel Vetter | 35c9537 | 2013-07-17 06:55:04 +0200 | [diff] [blame] | 11665 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
| 11666 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; |
| 11667 | |
| 11668 | if (!pll->on || pll->active) |
| 11669 | continue; |
| 11670 | |
| 11671 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); |
| 11672 | |
| 11673 | pll->disable(dev_priv, pll); |
| 11674 | pll->on = false; |
| 11675 | } |
| 11676 | |
Ville Syrjälä | 96f90c5 | 2013-12-05 15:51:38 +0200 | [diff] [blame] | 11677 | if (HAS_PCH_SPLIT(dev)) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 11678 | ilk_wm_get_hw_state(dev); |
| 11679 | |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 11680 | if (force_restore) { |
Ville Syrjälä | 7d0bc1e | 2013-09-16 17:38:33 +0300 | [diff] [blame] | 11681 | i915_redisable_vga(dev); |
| 11682 | |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 11683 | /* |
| 11684 | * We need to use raw interfaces for restoring state to avoid |
| 11685 | * checking (bogus) intermediate states. |
| 11686 | */ |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 11687 | for_each_pipe(pipe) { |
Jesse Barnes | b5644d0 | 2013-03-26 13:25:27 -0700 | [diff] [blame] | 11688 | struct drm_crtc *crtc = |
| 11689 | dev_priv->pipe_to_crtc_mapping[pipe]; |
Daniel Vetter | f30da18 | 2013-04-11 20:22:50 +0200 | [diff] [blame] | 11690 | |
| 11691 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
| 11692 | crtc->fb); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 11693 | } |
| 11694 | } else { |
| 11695 | intel_modeset_update_staged_output_state(dev); |
| 11696 | } |
Daniel Vetter | 8af6cf8 | 2012-07-10 09:50:11 +0200 | [diff] [blame] | 11697 | |
| 11698 | intel_modeset_check_state(dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 11699 | } |
| 11700 | |
| 11701 | void intel_modeset_gem_init(struct drm_device *dev) |
| 11702 | { |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 11703 | struct drm_crtc *c; |
| 11704 | struct intel_framebuffer *fb; |
| 11705 | |
Chris Wilson | 1833b13 | 2012-05-09 11:56:28 +0100 | [diff] [blame] | 11706 | intel_modeset_init_hw(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 11707 | |
| 11708 | intel_setup_overlay(dev); |
Jesse Barnes | 484b41d | 2014-03-07 08:57:55 -0800 | [diff] [blame] | 11709 | |
| 11710 | /* |
| 11711 | * Make sure any fbs we allocated at startup are properly |
| 11712 | * pinned & fenced. When we do the allocation it's too early |
| 11713 | * for this. |
| 11714 | */ |
| 11715 | mutex_lock(&dev->struct_mutex); |
| 11716 | list_for_each_entry(c, &dev->mode_config.crtc_list, head) { |
| 11717 | if (!c->fb) |
| 11718 | continue; |
| 11719 | |
| 11720 | fb = to_intel_framebuffer(c->fb); |
| 11721 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
| 11722 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
| 11723 | to_intel_crtc(c)->pipe); |
| 11724 | drm_framebuffer_unreference(c->fb); |
| 11725 | c->fb = NULL; |
| 11726 | } |
| 11727 | } |
| 11728 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11729 | } |
| 11730 | |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 11731 | void intel_connector_unregister(struct intel_connector *intel_connector) |
| 11732 | { |
| 11733 | struct drm_connector *connector = &intel_connector->base; |
| 11734 | |
| 11735 | intel_panel_destroy_backlight(connector); |
| 11736 | drm_sysfs_connector_remove(connector); |
| 11737 | } |
| 11738 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11739 | void intel_modeset_cleanup(struct drm_device *dev) |
| 11740 | { |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 11742 | struct drm_crtc *crtc; |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 11743 | struct drm_connector *connector; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11744 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 11745 | /* |
| 11746 | * Interrupts and polling as the first thing to avoid creating havoc. |
| 11747 | * Too much stuff here (turning of rps, connectors, ...) would |
| 11748 | * experience fancy races otherwise. |
| 11749 | */ |
| 11750 | drm_irq_uninstall(dev); |
| 11751 | cancel_work_sync(&dev_priv->hotplug_work); |
| 11752 | /* |
| 11753 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 11754 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 11755 | */ |
Keith Packard | f87ea76 | 2010-10-03 19:36:26 -0700 | [diff] [blame] | 11756 | drm_kms_helper_poll_fini(dev); |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 11757 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11758 | mutex_lock(&dev->struct_mutex); |
| 11759 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 11760 | intel_unregister_dsm_handler(); |
| 11761 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11762 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| 11763 | /* Skip inactive CRTCs */ |
| 11764 | if (!crtc->fb) |
| 11765 | continue; |
| 11766 | |
Daniel Vetter | 3dec009 | 2010-08-20 21:40:52 +0200 | [diff] [blame] | 11767 | intel_increase_pllclock(crtc); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 11768 | } |
| 11769 | |
Chris Wilson | 973d04f | 2011-07-08 12:22:37 +0100 | [diff] [blame] | 11770 | intel_disable_fbc(dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 11771 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 11772 | intel_disable_gt_powersave(dev); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 11773 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 11774 | ironlake_teardown_rc6(dev); |
| 11775 | |
Kristian Høgsberg | 69341a5 | 2009-11-11 12:19:17 -0500 | [diff] [blame] | 11776 | mutex_unlock(&dev->struct_mutex); |
| 11777 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 11778 | /* flush any delayed tasks or pending work */ |
| 11779 | flush_scheduled_work(); |
| 11780 | |
Jani Nikula | db31af1 | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 11781 | /* destroy the backlight and sysfs files before encoders/connectors */ |
| 11782 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 11783 | struct intel_connector *intel_connector; |
| 11784 | |
| 11785 | intel_connector = to_intel_connector(connector); |
| 11786 | intel_connector->unregister(intel_connector); |
Jani Nikula | db31af1 | 2013-11-08 16:48:53 +0200 | [diff] [blame] | 11787 | } |
Paulo Zanoni | d9255d5 | 2013-09-26 20:05:59 -0300 | [diff] [blame] | 11788 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11789 | drm_mode_config_cleanup(dev); |
Daniel Vetter | 4d7bb01 | 2012-12-18 15:24:37 +0100 | [diff] [blame] | 11790 | |
| 11791 | intel_cleanup_overlay(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11792 | } |
| 11793 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 11794 | /* |
Zhenyu Wang | f1c79df | 2010-03-30 14:39:29 +0800 | [diff] [blame] | 11795 | * Return which encoder is currently attached for connector. |
| 11796 | */ |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 11797 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11798 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 11799 | return &intel_attached_encoder(connector)->base; |
| 11800 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11801 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 11802 | void intel_connector_attach_encoder(struct intel_connector *connector, |
| 11803 | struct intel_encoder *encoder) |
| 11804 | { |
| 11805 | connector->encoder = encoder; |
| 11806 | drm_mode_connector_attach_encoder(&connector->base, |
| 11807 | &encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 11808 | } |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 11809 | |
| 11810 | /* |
| 11811 | * set vga decode state - true == enable VGA decode |
| 11812 | */ |
| 11813 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) |
| 11814 | { |
| 11815 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | a885b3c | 2013-12-17 14:34:50 +0000 | [diff] [blame] | 11816 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 11817 | u16 gmch_ctrl; |
| 11818 | |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 11819 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
| 11820 | DRM_ERROR("failed to read control word\n"); |
| 11821 | return -EIO; |
| 11822 | } |
| 11823 | |
Chris Wilson | c0cc8a5 | 2014-02-07 18:37:03 -0200 | [diff] [blame] | 11824 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
| 11825 | return 0; |
| 11826 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 11827 | if (state) |
| 11828 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; |
| 11829 | else |
| 11830 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; |
Chris Wilson | 75fa041 | 2014-02-07 18:37:02 -0200 | [diff] [blame] | 11831 | |
| 11832 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { |
| 11833 | DRM_ERROR("failed to write control word\n"); |
| 11834 | return -EIO; |
| 11835 | } |
| 11836 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 11837 | return 0; |
| 11838 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11839 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11840 | struct intel_display_error_state { |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 11841 | |
| 11842 | u32 power_well_driver; |
| 11843 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11844 | int num_transcoders; |
| 11845 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11846 | struct intel_cursor_error_state { |
| 11847 | u32 control; |
| 11848 | u32 position; |
| 11849 | u32 base; |
| 11850 | u32 size; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 11851 | } cursor[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11852 | |
| 11853 | struct intel_pipe_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11854 | bool power_domain_on; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11855 | u32 source; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 11856 | } pipe[I915_MAX_PIPES]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11857 | |
| 11858 | struct intel_plane_error_state { |
| 11859 | u32 control; |
| 11860 | u32 stride; |
| 11861 | u32 size; |
| 11862 | u32 pos; |
| 11863 | u32 addr; |
| 11864 | u32 surface; |
| 11865 | u32 tile_offset; |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 11866 | } plane[I915_MAX_PIPES]; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11867 | |
| 11868 | struct intel_transcoder_error_state { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11869 | bool power_domain_on; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11870 | enum transcoder cpu_transcoder; |
| 11871 | |
| 11872 | u32 conf; |
| 11873 | |
| 11874 | u32 htotal; |
| 11875 | u32 hblank; |
| 11876 | u32 hsync; |
| 11877 | u32 vtotal; |
| 11878 | u32 vblank; |
| 11879 | u32 vsync; |
| 11880 | } transcoder[4]; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11881 | }; |
| 11882 | |
| 11883 | struct intel_display_error_state * |
| 11884 | intel_display_capture_error_state(struct drm_device *dev) |
| 11885 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 11886 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11887 | struct intel_display_error_state *error; |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11888 | int transcoders[] = { |
| 11889 | TRANSCODER_A, |
| 11890 | TRANSCODER_B, |
| 11891 | TRANSCODER_C, |
| 11892 | TRANSCODER_EDP, |
| 11893 | }; |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11894 | int i; |
| 11895 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11896 | if (INTEL_INFO(dev)->num_pipes == 0) |
| 11897 | return NULL; |
| 11898 | |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 11899 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11900 | if (error == NULL) |
| 11901 | return NULL; |
| 11902 | |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 11903 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 11904 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
| 11905 | |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 11906 | for_each_pipe(i) { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11907 | error->pipe[i].power_domain_on = |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 11908 | intel_display_power_enabled_sw(dev_priv, |
| 11909 | POWER_DOMAIN_PIPE(i)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11910 | if (!error->pipe[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 11911 | continue; |
| 11912 | |
Paulo Zanoni | a18c4c3 | 2013-03-06 20:03:12 -0300 | [diff] [blame] | 11913 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
| 11914 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
| 11915 | error->cursor[i].position = I915_READ(CURPOS(i)); |
| 11916 | error->cursor[i].base = I915_READ(CURBASE(i)); |
| 11917 | } else { |
| 11918 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); |
| 11919 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); |
| 11920 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); |
| 11921 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11922 | |
| 11923 | error->plane[i].control = I915_READ(DSPCNTR(i)); |
| 11924 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 11925 | if (INTEL_INFO(dev)->gen <= 3) { |
Paulo Zanoni | 51889b3 | 2013-03-06 20:03:13 -0300 | [diff] [blame] | 11926 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 11927 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
| 11928 | } |
Paulo Zanoni | ca29136 | 2013-03-06 20:03:14 -0300 | [diff] [blame] | 11929 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
| 11930 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11931 | if (INTEL_INFO(dev)->gen >= 4) { |
| 11932 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
| 11933 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); |
| 11934 | } |
| 11935 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11936 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11937 | } |
| 11938 | |
| 11939 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; |
| 11940 | if (HAS_DDI(dev_priv->dev)) |
| 11941 | error->num_transcoders++; /* Account for eDP. */ |
| 11942 | |
| 11943 | for (i = 0; i < error->num_transcoders; i++) { |
| 11944 | enum transcoder cpu_transcoder = transcoders[i]; |
| 11945 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11946 | error->transcoder[i].power_domain_on = |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 11947 | intel_display_power_enabled_sw(dev_priv, |
Paulo Zanoni | 38cc1da | 2013-12-20 15:09:41 -0200 | [diff] [blame] | 11948 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11949 | if (!error->transcoder[i].power_domain_on) |
Paulo Zanoni | 9d1cb91 | 2013-11-01 13:32:08 -0200 | [diff] [blame] | 11950 | continue; |
| 11951 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11952 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 11953 | |
| 11954 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
| 11955 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
| 11956 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); |
| 11957 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); |
| 11958 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); |
| 11959 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); |
| 11960 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11961 | } |
| 11962 | |
| 11963 | return error; |
| 11964 | } |
| 11965 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11966 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 11967 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11968 | void |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11969 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11970 | struct drm_device *dev, |
| 11971 | struct intel_display_error_state *error) |
| 11972 | { |
| 11973 | int i; |
| 11974 | |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 11975 | if (!error) |
| 11976 | return; |
| 11977 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11978 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
Imre Deak | 190be11 | 2013-11-25 17:15:31 +0200 | [diff] [blame] | 11979 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11980 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
Paulo Zanoni | ff57f1b | 2013-05-03 12:15:37 -0300 | [diff] [blame] | 11981 | error->power_well_driver); |
Damien Lespiau | 5233130 | 2012-08-15 19:23:25 +0100 | [diff] [blame] | 11982 | for_each_pipe(i) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11983 | err_printf(m, "Pipe [%d]:\n", i); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 11984 | err_printf(m, " Power: %s\n", |
| 11985 | error->pipe[i].power_domain_on ? "on" : "off"); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11986 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11987 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11988 | err_printf(m, "Plane [%d]:\n", i); |
| 11989 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); |
| 11990 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 11991 | if (INTEL_INFO(dev)->gen <= 3) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11992 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
| 11993 | err_printf(m, " POS: %08x\n", error->plane[i].pos); |
Paulo Zanoni | 80ca378 | 2013-03-22 14:20:57 -0300 | [diff] [blame] | 11994 | } |
Paulo Zanoni | 4b71a57 | 2013-03-22 14:19:21 -0300 | [diff] [blame] | 11995 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11996 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 11997 | if (INTEL_INFO(dev)->gen >= 4) { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 11998 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
| 11999 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 12000 | } |
| 12001 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 12002 | err_printf(m, "Cursor [%d]:\n", i); |
| 12003 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); |
| 12004 | err_printf(m, " POS: %08x\n", error->cursor[i].position); |
| 12005 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 12006 | } |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 12007 | |
| 12008 | for (i = 0; i < error->num_transcoders; i++) { |
Chris Wilson | 1cf84bb | 2013-10-21 09:10:33 +0100 | [diff] [blame] | 12009 | err_printf(m, "CPU transcoder: %c\n", |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 12010 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 12011 | err_printf(m, " Power: %s\n", |
| 12012 | error->transcoder[i].power_domain_on ? "on" : "off"); |
Chris Wilson | 63b66e5 | 2013-08-08 15:12:06 +0200 | [diff] [blame] | 12013 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
| 12014 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); |
| 12015 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); |
| 12016 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); |
| 12017 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); |
| 12018 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); |
| 12019 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); |
| 12020 | } |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 12021 | } |